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1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017, Maxim Integrated
3
4#include <linux/acpi.h>
5#include <linux/delay.h>
6#include <linux/i2c.h>
7#include <linux/module.h>
8#include <linux/pm_runtime.h>
9#include <linux/regmap.h>
10#include <linux/slab.h>
11#include <linux/cdev.h>
12#include <sound/pcm.h>
13#include <sound/pcm_params.h>
14#include <sound/soc.h>
15#include <linux/gpio/consumer.h>
16#include <linux/of.h>
17#include <sound/tlv.h>
18#include "max98373.h"
19
20static int max98373_dac_event(struct snd_soc_dapm_widget *w,
21 struct snd_kcontrol *kcontrol, int event)
22{
23 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
24 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
25
26 switch (event) {
27 case SND_SOC_DAPM_POST_PMU:
28 regmap_update_bits(max98373->regmap,
29 MAX98373_R20FF_GLOBAL_SHDN,
30 MAX98373_GLOBAL_EN_MASK, 1);
31 usleep_range(30000, 31000);
32 break;
33 case SND_SOC_DAPM_PRE_PMD:
34 regmap_update_bits(max98373->regmap,
35 MAX98373_R20FF_GLOBAL_SHDN,
36 MAX98373_GLOBAL_EN_MASK, 0);
37 usleep_range(30000, 31000);
38 max98373->tdm_mode = false;
39 break;
40 default:
41 return 0;
42 }
43 return 0;
44}
45
46static const char * const max98373_switch_text[] = {
47 "Left", "Right", "LeftRight"};
48
49static const struct soc_enum dai_sel_enum =
50 SOC_ENUM_SINGLE(MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
51 MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
52 3, max98373_switch_text);
53
54static const struct snd_kcontrol_new max98373_dai_controls =
55 SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
56
57static const struct snd_kcontrol_new max98373_vi_control =
58 SOC_DAPM_SINGLE("Switch", MAX98373_R202C_PCM_TX_EN, 0, 1, 0);
59
60static const struct snd_kcontrol_new max98373_spkfb_control =
61 SOC_DAPM_SINGLE("Switch", MAX98373_R2043_AMP_EN, 1, 1, 0);
62
63static const struct snd_soc_dapm_widget max98373_dapm_widgets[] = {
64SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
65 MAX98373_R202B_PCM_RX_EN, 0, 0, max98373_dac_event,
66 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
67SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
68 &max98373_dai_controls),
69SND_SOC_DAPM_OUTPUT("BE_OUT"),
70SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
71 MAX98373_R2047_IV_SENSE_ADC_EN, 0, 0),
72SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
73 MAX98373_R2047_IV_SENSE_ADC_EN, 1, 0),
74SND_SOC_DAPM_AIF_OUT("Speaker FB Sense", "HiFi Capture", 0,
75 SND_SOC_NOPM, 0, 0),
76SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
77 &max98373_vi_control),
78SND_SOC_DAPM_SWITCH("SpkFB Sense", SND_SOC_NOPM, 0, 0,
79 &max98373_spkfb_control),
80SND_SOC_DAPM_SIGGEN("VMON"),
81SND_SOC_DAPM_SIGGEN("IMON"),
82SND_SOC_DAPM_SIGGEN("FBMON"),
83};
84
85static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, -6350, 50, 1);
86static const DECLARE_TLV_DB_RANGE(max98373_spk_tlv,
87 0, 8, TLV_DB_SCALE_ITEM(0, 50, 0),
88 9, 10, TLV_DB_SCALE_ITEM(500, 100, 0),
89);
90static const DECLARE_TLV_DB_RANGE(max98373_spkgain_max_tlv,
91 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
92);
93static const DECLARE_TLV_DB_RANGE(max98373_dht_step_size_tlv,
94 0, 1, TLV_DB_SCALE_ITEM(25, 25, 0),
95 2, 4, TLV_DB_SCALE_ITEM(100, 100, 0),
96);
97static const DECLARE_TLV_DB_RANGE(max98373_dht_spkgain_min_tlv,
98 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
99);
100static const DECLARE_TLV_DB_RANGE(max98373_dht_rotation_point_tlv,
101 0, 1, TLV_DB_SCALE_ITEM(-3000, 500, 0),
102 2, 4, TLV_DB_SCALE_ITEM(-2200, 200, 0),
103 5, 6, TLV_DB_SCALE_ITEM(-1500, 300, 0),
104 7, 9, TLV_DB_SCALE_ITEM(-1000, 200, 0),
105 10, 13, TLV_DB_SCALE_ITEM(-500, 100, 0),
106 14, 15, TLV_DB_SCALE_ITEM(-100, 50, 0),
107);
108static const DECLARE_TLV_DB_RANGE(max98373_limiter_thresh_tlv,
109 0, 15, TLV_DB_SCALE_ITEM(-1500, 100, 0),
110);
111
112static const DECLARE_TLV_DB_RANGE(max98373_bde_gain_tlv,
113 0, 60, TLV_DB_SCALE_ITEM(-1500, 25, 0),
114);
115
116static const char * const max98373_output_voltage_lvl_text[] = {
117 "5.43V", "6.09V", "6.83V", "7.67V", "8.60V",
118 "9.65V", "10.83V", "12.15V", "13.63V", "15.29V"
119};
120
121static SOC_ENUM_SINGLE_DECL(max98373_out_volt_enum,
122 MAX98373_R203E_AMP_PATH_GAIN, 0,
123 max98373_output_voltage_lvl_text);
124
125static const char * const max98373_dht_attack_rate_text[] = {
126 "17.5us", "35us", "70us", "140us",
127 "280us", "560us", "1120us", "2240us"
128};
129
130static SOC_ENUM_SINGLE_DECL(max98373_dht_attack_rate_enum,
131 MAX98373_R20D2_DHT_ATTACK_CFG, 0,
132 max98373_dht_attack_rate_text);
133
134static const char * const max98373_dht_release_rate_text[] = {
135 "45ms", "225ms", "450ms", "1150ms",
136 "2250ms", "3100ms", "4500ms", "6750ms"
137};
138
139static SOC_ENUM_SINGLE_DECL(max98373_dht_release_rate_enum,
140 MAX98373_R20D3_DHT_RELEASE_CFG, 0,
141 max98373_dht_release_rate_text);
142
143static const char * const max98373_limiter_attack_rate_text[] = {
144 "10us", "20us", "40us", "80us",
145 "160us", "320us", "640us", "1.28ms",
146 "2.56ms", "5.12ms", "10.24ms", "20.48ms",
147 "40.96ms", "81.92ms", "16.384ms", "32.768ms"
148};
149
150static SOC_ENUM_SINGLE_DECL(max98373_limiter_attack_rate_enum,
151 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 4,
152 max98373_limiter_attack_rate_text);
153
154static const char * const max98373_limiter_release_rate_text[] = {
155 "40us", "80us", "160us", "320us",
156 "640us", "1.28ms", "2.56ms", "5.120ms",
157 "10.24ms", "20.48ms", "40.96ms", "81.92ms",
158 "163.84ms", "327.68ms", "655.36ms", "1310.72ms"
159};
160
161static SOC_ENUM_SINGLE_DECL(max98373_limiter_release_rate_enum,
162 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0,
163 max98373_limiter_release_rate_text);
164
165static const char * const max98373_ADC_samplerate_text[] = {
166 "333kHz", "192kHz", "64kHz", "48kHz"
167};
168
169static SOC_ENUM_SINGLE_DECL(max98373_adc_samplerate_enum,
170 MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0,
171 max98373_ADC_samplerate_text);
172
173static int max98373_feedback_get(struct snd_kcontrol *kcontrol,
174 struct snd_ctl_elem_value *ucontrol)
175{
176 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
177 struct soc_mixer_control *mc =
178 (struct soc_mixer_control *)kcontrol->private_value;
179 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
180 int i;
181
182 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
183 /*
184 * Register values will be cached before suspend. The cached value
185 * will be a valid value and userspace will happy with that.
186 */
187 for (i = 0; i < max98373->cache_num; i++) {
188 if (mc->reg == max98373->cache[i].reg) {
189 ucontrol->value.integer.value[0] = max98373->cache[i].val;
190 return 0;
191 }
192 }
193 }
194
195 return snd_soc_get_volsw(kcontrol, ucontrol);
196}
197
198static const struct snd_kcontrol_new max98373_snd_controls[] = {
199SOC_SINGLE("Digital Vol Sel Switch", MAX98373_R203F_AMP_DSP_CFG,
200 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
201SOC_SINGLE("Volume Location Switch", MAX98373_R203F_AMP_DSP_CFG,
202 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
203SOC_SINGLE("Ramp Up Switch", MAX98373_R203F_AMP_DSP_CFG,
204 MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0),
205SOC_SINGLE("Ramp Down Switch", MAX98373_R203F_AMP_DSP_CFG,
206 MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0),
207/* Speaker Amplifier Overcurrent Automatic Restart Enable */
208SOC_SINGLE("OVC Autorestart Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
209 MAX98373_OVC_AUTORESTART_SHIFT, 1, 0),
210/* Thermal Shutdown Automatic Restart Enable */
211SOC_SINGLE("THERM Autorestart Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
212 MAX98373_THERM_AUTORESTART_SHIFT, 1, 0),
213/* Clock Monitor Automatic Restart Enable */
214SOC_SINGLE("CMON Autorestart Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
215 MAX98373_CMON_AUTORESTART_SHIFT, 1, 0),
216SOC_SINGLE("CLK Monitor Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
217 MAX98373_CLOCK_MON_SHIFT, 1, 0),
218SOC_SINGLE("Dither Switch", MAX98373_R203F_AMP_DSP_CFG,
219 MAX98373_AMP_DSP_CFG_DITH_SHIFT, 1, 0),
220SOC_SINGLE("DC Blocker Switch", MAX98373_R203F_AMP_DSP_CFG,
221 MAX98373_AMP_DSP_CFG_DCBLK_SHIFT, 1, 0),
222SOC_SINGLE_TLV("Digital Volume", MAX98373_R203D_AMP_DIG_VOL_CTRL,
223 0, 0x7F, 1, max98373_digital_tlv),
224SOC_SINGLE_TLV("Speaker Volume", MAX98373_R203E_AMP_PATH_GAIN,
225 MAX98373_SPK_DIGI_GAIN_SHIFT, 10, 0, max98373_spk_tlv),
226SOC_SINGLE_TLV("FS Max Volume", MAX98373_R203E_AMP_PATH_GAIN,
227 MAX98373_FS_GAIN_MAX_SHIFT, 9, 0, max98373_spkgain_max_tlv),
228SOC_ENUM("Output Voltage", max98373_out_volt_enum),
229/* Dynamic Headroom Tracking */
230SOC_SINGLE("DHT Switch", MAX98373_R20D4_DHT_EN,
231 MAX98373_DHT_EN_SHIFT, 1, 0),
232SOC_SINGLE_TLV("DHT Min Volume", MAX98373_R20D1_DHT_CFG,
233 MAX98373_DHT_SPK_GAIN_MIN_SHIFT, 9, 0, max98373_dht_spkgain_min_tlv),
234SOC_SINGLE_TLV("DHT Rot Pnt Volume", MAX98373_R20D1_DHT_CFG,
235 MAX98373_DHT_ROT_PNT_SHIFT, 15, 1, max98373_dht_rotation_point_tlv),
236SOC_SINGLE_TLV("DHT Attack Step Volume", MAX98373_R20D2_DHT_ATTACK_CFG,
237 MAX98373_DHT_ATTACK_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
238SOC_SINGLE_TLV("DHT Release Step Volume", MAX98373_R20D3_DHT_RELEASE_CFG,
239 MAX98373_DHT_RELEASE_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
240SOC_ENUM("DHT Attack Rate", max98373_dht_attack_rate_enum),
241SOC_ENUM("DHT Release Rate", max98373_dht_release_rate_enum),
242/* ADC configuration */
243SOC_SINGLE("ADC PVDD CH Switch", MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0, 1, 0),
244SOC_SINGLE("ADC PVDD FLT Switch", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
245 MAX98373_FLT_EN_SHIFT, 1, 0),
246SOC_SINGLE("ADC TEMP FLT Switch", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
247 MAX98373_FLT_EN_SHIFT, 1, 0),
248SOC_SINGLE_EXT("ADC PVDD", MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0, 0xFF, 0,
249 max98373_feedback_get, NULL),
250SOC_SINGLE_EXT("ADC TEMP", MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0, 0xFF, 0,
251 max98373_feedback_get, NULL),
252SOC_SINGLE("ADC PVDD FLT Coeff", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
253 0, 0x3, 0),
254SOC_SINGLE("ADC TEMP FLT Coeff", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
255 0, 0x3, 0),
256SOC_ENUM("ADC SampleRate", max98373_adc_samplerate_enum),
257/* Brownout Detection Engine */
258SOC_SINGLE("BDE Switch", MAX98373_R20B5_BDE_EN, MAX98373_BDE_EN_SHIFT, 1, 0),
259SOC_SINGLE("BDE LVL4 Mute Switch", MAX98373_R20B2_BDE_L4_CFG_2,
260 MAX98373_LVL4_MUTE_EN_SHIFT, 1, 0),
261SOC_SINGLE("BDE LVL4 Hold Switch", MAX98373_R20B2_BDE_L4_CFG_2,
262 MAX98373_LVL4_HOLD_EN_SHIFT, 1, 0),
263SOC_SINGLE("BDE LVL1 Thresh", MAX98373_R2097_BDE_L1_THRESH, 0, 0xFF, 0),
264SOC_SINGLE("BDE LVL2 Thresh", MAX98373_R2098_BDE_L2_THRESH, 0, 0xFF, 0),
265SOC_SINGLE("BDE LVL3 Thresh", MAX98373_R2099_BDE_L3_THRESH, 0, 0xFF, 0),
266SOC_SINGLE("BDE LVL4 Thresh", MAX98373_R209A_BDE_L4_THRESH, 0, 0xFF, 0),
267SOC_SINGLE_EXT("BDE Active Level", MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0, 8, 0,
268 max98373_feedback_get, NULL),
269SOC_SINGLE("BDE Clip Mode Switch", MAX98373_R2092_BDE_CLIPPER_MODE, 0, 1, 0),
270SOC_SINGLE("BDE Thresh Hysteresis", MAX98373_R209B_BDE_THRESH_HYST, 0, 0xFF, 0),
271SOC_SINGLE("BDE Hold Time", MAX98373_R2090_BDE_LVL_HOLD, 0, 0xFF, 0),
272SOC_SINGLE("BDE Attack Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 4, 0xF, 0),
273SOC_SINGLE("BDE Release Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0, 0xF, 0),
274SOC_SINGLE_TLV("BDE LVL1 Clip Thresh Volume", MAX98373_R20A9_BDE_L1_CFG_2,
275 0, 0x3C, 1, max98373_bde_gain_tlv),
276SOC_SINGLE_TLV("BDE LVL2 Clip Thresh Volume", MAX98373_R20AC_BDE_L2_CFG_2,
277 0, 0x3C, 1, max98373_bde_gain_tlv),
278SOC_SINGLE_TLV("BDE LVL3 Clip Thresh Volume", MAX98373_R20AF_BDE_L3_CFG_2,
279 0, 0x3C, 1, max98373_bde_gain_tlv),
280SOC_SINGLE_TLV("BDE LVL4 Clip Thresh Volume", MAX98373_R20B2_BDE_L4_CFG_2,
281 0, 0x3C, 1, max98373_bde_gain_tlv),
282SOC_SINGLE_TLV("BDE LVL1 Clip Reduction Volume", MAX98373_R20AA_BDE_L1_CFG_3,
283 0, 0x3C, 1, max98373_bde_gain_tlv),
284SOC_SINGLE_TLV("BDE LVL2 Clip Reduction Volume", MAX98373_R20AD_BDE_L2_CFG_3,
285 0, 0x3C, 1, max98373_bde_gain_tlv),
286SOC_SINGLE_TLV("BDE LVL3 Clip Reduction Volume", MAX98373_R20B0_BDE_L3_CFG_3,
287 0, 0x3C, 1, max98373_bde_gain_tlv),
288SOC_SINGLE_TLV("BDE LVL4 Clip Reduction Volume", MAX98373_R20B3_BDE_L4_CFG_3,
289 0, 0x3C, 1, max98373_bde_gain_tlv),
290SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1,
291 0, 0xF, 1, max98373_limiter_thresh_tlv),
292SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh Volume", MAX98373_R20AB_BDE_L2_CFG_1,
293 0, 0xF, 1, max98373_limiter_thresh_tlv),
294SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh Volume", MAX98373_R20AE_BDE_L3_CFG_1,
295 0, 0xF, 1, max98373_limiter_thresh_tlv),
296SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh Volume", MAX98373_R20B1_BDE_L4_CFG_1,
297 0, 0xF, 1, max98373_limiter_thresh_tlv),
298/* Limiter */
299SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN,
300 MAX98373_LIMITER_EN_SHIFT, 1, 0),
301SOC_SINGLE("Limiter Src Switch", MAX98373_R20E0_LIMITER_THRESH_CFG,
302 MAX98373_LIMITER_THRESH_SRC_SHIFT, 1, 0),
303SOC_SINGLE_TLV("Limiter Thresh Volume", MAX98373_R20E0_LIMITER_THRESH_CFG,
304 MAX98373_LIMITER_THRESH_SHIFT, 15, 0, max98373_limiter_thresh_tlv),
305SOC_ENUM("Limiter Attack Rate", max98373_limiter_attack_rate_enum),
306SOC_ENUM("Limiter Release Rate", max98373_limiter_release_rate_enum),
307};
308
309static const struct snd_soc_dapm_route max98373_audio_map[] = {
310 /* Plabyack */
311 {"DAI Sel Mux", "Left", "Amp Enable"},
312 {"DAI Sel Mux", "Right", "Amp Enable"},
313 {"DAI Sel Mux", "LeftRight", "Amp Enable"},
314 {"BE_OUT", NULL, "DAI Sel Mux"},
315 /* Capture */
316 { "VI Sense", "Switch", "VMON" },
317 { "VI Sense", "Switch", "IMON" },
318 { "SpkFB Sense", "Switch", "FBMON" },
319 { "Voltage Sense", NULL, "VI Sense" },
320 { "Current Sense", NULL, "VI Sense" },
321 { "Speaker FB Sense", NULL, "SpkFB Sense" },
322};
323
324void max98373_reset(struct max98373_priv *max98373, struct device *dev)
325{
326 int ret, reg, count;
327
328 /* Software Reset */
329 ret = regmap_update_bits(max98373->regmap,
330 MAX98373_R2000_SW_RESET,
331 MAX98373_SOFT_RESET,
332 MAX98373_SOFT_RESET);
333 if (ret)
334 dev_err(dev, "Reset command failed. (ret:%d)\n", ret);
335
336 count = 0;
337 while (count < 3) {
338 usleep_range(10000, 11000);
339 /* Software Reset Verification */
340 ret = regmap_read(max98373->regmap,
341 MAX98373_R21FF_REV_ID, ®);
342 if (!ret) {
343 dev_info(dev, "Reset completed (retry:%d)\n", count);
344 return;
345 }
346 count++;
347 }
348 dev_err(dev, "Reset failed. (ret:%d)\n", ret);
349}
350EXPORT_SYMBOL_GPL(max98373_reset);
351
352static int max98373_probe(struct snd_soc_component *component)
353{
354 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
355
356 /* Software Reset */
357 max98373_reset(max98373, component->dev);
358
359 /* IV default slot configuration */
360 regmap_write(max98373->regmap,
361 MAX98373_R2020_PCM_TX_HIZ_EN_1,
362 0xFF);
363 regmap_write(max98373->regmap,
364 MAX98373_R2021_PCM_TX_HIZ_EN_2,
365 0xFF);
366 /* L/R mix configuration */
367 regmap_write(max98373->regmap,
368 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
369 0x80);
370 regmap_write(max98373->regmap,
371 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
372 0x1);
373 /* Enable DC blocker */
374 regmap_write(max98373->regmap,
375 MAX98373_R203F_AMP_DSP_CFG,
376 0x3);
377 /* Enable IMON VMON DC blocker */
378 regmap_write(max98373->regmap,
379 MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
380 0x7);
381 /* voltage, current slot configuration */
382 regmap_write(max98373->regmap,
383 MAX98373_R2022_PCM_TX_SRC_1,
384 (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
385 max98373->v_slot) & 0xFF);
386 if (max98373->v_slot < 8)
387 regmap_update_bits(max98373->regmap,
388 MAX98373_R2020_PCM_TX_HIZ_EN_1,
389 1 << max98373->v_slot, 0);
390 else
391 regmap_update_bits(max98373->regmap,
392 MAX98373_R2021_PCM_TX_HIZ_EN_2,
393 1 << (max98373->v_slot - 8), 0);
394
395 if (max98373->i_slot < 8)
396 regmap_update_bits(max98373->regmap,
397 MAX98373_R2020_PCM_TX_HIZ_EN_1,
398 1 << max98373->i_slot, 0);
399 else
400 regmap_update_bits(max98373->regmap,
401 MAX98373_R2021_PCM_TX_HIZ_EN_2,
402 1 << (max98373->i_slot - 8), 0);
403
404 /* enable auto restart function by default */
405 regmap_write(max98373->regmap,
406 MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
407 0xF);
408
409 /* speaker feedback slot configuration */
410 regmap_write(max98373->regmap,
411 MAX98373_R2023_PCM_TX_SRC_2,
412 max98373->spkfb_slot & 0xFF);
413
414 /* Set interleave mode */
415 if (max98373->interleave_mode)
416 regmap_update_bits(max98373->regmap,
417 MAX98373_R2024_PCM_DATA_FMT_CFG,
418 MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
419 MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
420
421 /* Speaker enable */
422 regmap_update_bits(max98373->regmap,
423 MAX98373_R2043_AMP_EN,
424 MAX98373_SPK_EN_MASK, 1);
425
426 return 0;
427}
428
429const struct snd_soc_component_driver soc_codec_dev_max98373 = {
430 .probe = max98373_probe,
431 .controls = max98373_snd_controls,
432 .num_controls = ARRAY_SIZE(max98373_snd_controls),
433 .dapm_widgets = max98373_dapm_widgets,
434 .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets),
435 .dapm_routes = max98373_audio_map,
436 .num_dapm_routes = ARRAY_SIZE(max98373_audio_map),
437 .use_pmdown_time = 1,
438 .endianness = 1,
439};
440EXPORT_SYMBOL_GPL(soc_codec_dev_max98373);
441
442static int max98373_sdw_probe(struct snd_soc_component *component)
443{
444 int ret;
445
446 ret = pm_runtime_resume(component->dev);
447 if (ret < 0 && ret != -EACCES)
448 return ret;
449
450 return 0;
451}
452
453const struct snd_soc_component_driver soc_codec_dev_max98373_sdw = {
454 .probe = max98373_sdw_probe,
455 .controls = max98373_snd_controls,
456 .num_controls = ARRAY_SIZE(max98373_snd_controls),
457 .dapm_widgets = max98373_dapm_widgets,
458 .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets),
459 .dapm_routes = max98373_audio_map,
460 .num_dapm_routes = ARRAY_SIZE(max98373_audio_map),
461 .use_pmdown_time = 1,
462 .endianness = 1,
463};
464EXPORT_SYMBOL_GPL(soc_codec_dev_max98373_sdw);
465
466void max98373_slot_config(struct device *dev,
467 struct max98373_priv *max98373)
468{
469 int value;
470
471 if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value))
472 max98373->v_slot = value & 0xF;
473 else
474 max98373->v_slot = 0;
475
476 if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value))
477 max98373->i_slot = value & 0xF;
478 else
479 max98373->i_slot = 1;
480
481 /* This will assert RESET */
482 max98373->reset = devm_gpiod_get_optional(dev,
483 "maxim,reset",
484 GPIOD_OUT_HIGH);
485 if (IS_ERR(max98373->reset)) {
486 dev_err(dev, "error %ld looking up RESET GPIO line\n",
487 PTR_ERR(max98373->reset));
488 return;
489 }
490
491 /* Cycle reset */
492 if (max98373->reset) {
493 gpiod_set_consumer_name(max98373->reset ,"MAX98373_RESET");
494 gpiod_direction_output(max98373->reset, 1);
495 msleep(50);
496 gpiod_direction_output(max98373->reset, 0);
497 msleep(20);
498 }
499
500 if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value))
501 max98373->spkfb_slot = value & 0xF;
502 else
503 max98373->spkfb_slot = 2;
504}
505EXPORT_SYMBOL_GPL(max98373_slot_config);
506
507MODULE_DESCRIPTION("ALSA SoC MAX98373 driver");
508MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
509MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017, Maxim Integrated
3
4#include <linux/acpi.h>
5#include <linux/delay.h>
6#include <linux/i2c.h>
7#include <linux/module.h>
8#include <linux/pm_runtime.h>
9#include <linux/regmap.h>
10#include <linux/slab.h>
11#include <linux/cdev.h>
12#include <sound/pcm.h>
13#include <sound/pcm_params.h>
14#include <sound/soc.h>
15#include <linux/gpio.h>
16#include <linux/of.h>
17#include <linux/of_gpio.h>
18#include <sound/tlv.h>
19#include "max98373.h"
20
21static int max98373_dac_event(struct snd_soc_dapm_widget *w,
22 struct snd_kcontrol *kcontrol, int event)
23{
24 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
25 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
26
27 switch (event) {
28 case SND_SOC_DAPM_POST_PMU:
29 regmap_update_bits(max98373->regmap,
30 MAX98373_R20FF_GLOBAL_SHDN,
31 MAX98373_GLOBAL_EN_MASK, 1);
32 usleep_range(30000, 31000);
33 break;
34 case SND_SOC_DAPM_POST_PMD:
35 regmap_update_bits(max98373->regmap,
36 MAX98373_R20FF_GLOBAL_SHDN,
37 MAX98373_GLOBAL_EN_MASK, 0);
38 usleep_range(30000, 31000);
39 max98373->tdm_mode = false;
40 break;
41 default:
42 return 0;
43 }
44 return 0;
45}
46
47static const char * const max98373_switch_text[] = {
48 "Left", "Right", "LeftRight"};
49
50static const struct soc_enum dai_sel_enum =
51 SOC_ENUM_SINGLE(MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
52 MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
53 3, max98373_switch_text);
54
55static const struct snd_kcontrol_new max98373_dai_controls =
56 SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
57
58static const struct snd_kcontrol_new max98373_vi_control =
59 SOC_DAPM_SINGLE("Switch", MAX98373_R202C_PCM_TX_EN, 0, 1, 0);
60
61static const struct snd_kcontrol_new max98373_spkfb_control =
62 SOC_DAPM_SINGLE("Switch", MAX98373_R2043_AMP_EN, 1, 1, 0);
63
64static const struct snd_soc_dapm_widget max98373_dapm_widgets[] = {
65SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
66 MAX98373_R202B_PCM_RX_EN, 0, 0, max98373_dac_event,
67 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
68SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
69 &max98373_dai_controls),
70SND_SOC_DAPM_OUTPUT("BE_OUT"),
71SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
72 MAX98373_R2047_IV_SENSE_ADC_EN, 0, 0),
73SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
74 MAX98373_R2047_IV_SENSE_ADC_EN, 1, 0),
75SND_SOC_DAPM_AIF_OUT("Speaker FB Sense", "HiFi Capture", 0,
76 SND_SOC_NOPM, 0, 0),
77SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
78 &max98373_vi_control),
79SND_SOC_DAPM_SWITCH("SpkFB Sense", SND_SOC_NOPM, 0, 0,
80 &max98373_spkfb_control),
81SND_SOC_DAPM_SIGGEN("VMON"),
82SND_SOC_DAPM_SIGGEN("IMON"),
83SND_SOC_DAPM_SIGGEN("FBMON"),
84};
85
86static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, -6350, 50, 1);
87static const DECLARE_TLV_DB_RANGE(max98373_spk_tlv,
88 0, 8, TLV_DB_SCALE_ITEM(0, 50, 0),
89 9, 10, TLV_DB_SCALE_ITEM(500, 100, 0),
90);
91static const DECLARE_TLV_DB_RANGE(max98373_spkgain_max_tlv,
92 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
93);
94static const DECLARE_TLV_DB_RANGE(max98373_dht_step_size_tlv,
95 0, 1, TLV_DB_SCALE_ITEM(25, 25, 0),
96 2, 4, TLV_DB_SCALE_ITEM(100, 100, 0),
97);
98static const DECLARE_TLV_DB_RANGE(max98373_dht_spkgain_min_tlv,
99 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
100);
101static const DECLARE_TLV_DB_RANGE(max98373_dht_rotation_point_tlv,
102 0, 1, TLV_DB_SCALE_ITEM(-3000, 500, 0),
103 2, 4, TLV_DB_SCALE_ITEM(-2200, 200, 0),
104 5, 6, TLV_DB_SCALE_ITEM(-1500, 300, 0),
105 7, 9, TLV_DB_SCALE_ITEM(-1000, 200, 0),
106 10, 13, TLV_DB_SCALE_ITEM(-500, 100, 0),
107 14, 15, TLV_DB_SCALE_ITEM(-100, 50, 0),
108);
109static const DECLARE_TLV_DB_RANGE(max98373_limiter_thresh_tlv,
110 0, 15, TLV_DB_SCALE_ITEM(-1500, 100, 0),
111);
112
113static const DECLARE_TLV_DB_RANGE(max98373_bde_gain_tlv,
114 0, 60, TLV_DB_SCALE_ITEM(-1500, 25, 0),
115);
116
117static const char * const max98373_output_voltage_lvl_text[] = {
118 "5.43V", "6.09V", "6.83V", "7.67V", "8.60V",
119 "9.65V", "10.83V", "12.15V", "13.63V", "15.29V"
120};
121
122static SOC_ENUM_SINGLE_DECL(max98373_out_volt_enum,
123 MAX98373_R203E_AMP_PATH_GAIN, 0,
124 max98373_output_voltage_lvl_text);
125
126static const char * const max98373_dht_attack_rate_text[] = {
127 "17.5us", "35us", "70us", "140us",
128 "280us", "560us", "1120us", "2240us"
129};
130
131static SOC_ENUM_SINGLE_DECL(max98373_dht_attack_rate_enum,
132 MAX98373_R20D2_DHT_ATTACK_CFG, 0,
133 max98373_dht_attack_rate_text);
134
135static const char * const max98373_dht_release_rate_text[] = {
136 "45ms", "225ms", "450ms", "1150ms",
137 "2250ms", "3100ms", "4500ms", "6750ms"
138};
139
140static SOC_ENUM_SINGLE_DECL(max98373_dht_release_rate_enum,
141 MAX98373_R20D3_DHT_RELEASE_CFG, 0,
142 max98373_dht_release_rate_text);
143
144static const char * const max98373_limiter_attack_rate_text[] = {
145 "10us", "20us", "40us", "80us",
146 "160us", "320us", "640us", "1.28ms",
147 "2.56ms", "5.12ms", "10.24ms", "20.48ms",
148 "40.96ms", "81.92ms", "16.384ms", "32.768ms"
149};
150
151static SOC_ENUM_SINGLE_DECL(max98373_limiter_attack_rate_enum,
152 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 4,
153 max98373_limiter_attack_rate_text);
154
155static const char * const max98373_limiter_release_rate_text[] = {
156 "40us", "80us", "160us", "320us",
157 "640us", "1.28ms", "2.56ms", "5.120ms",
158 "10.24ms", "20.48ms", "40.96ms", "81.92ms",
159 "163.84ms", "327.68ms", "655.36ms", "1310.72ms"
160};
161
162static SOC_ENUM_SINGLE_DECL(max98373_limiter_release_rate_enum,
163 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0,
164 max98373_limiter_release_rate_text);
165
166static const char * const max98373_ADC_samplerate_text[] = {
167 "333kHz", "192kHz", "64kHz", "48kHz"
168};
169
170static SOC_ENUM_SINGLE_DECL(max98373_adc_samplerate_enum,
171 MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0,
172 max98373_ADC_samplerate_text);
173
174static int max98373_feedback_get(struct snd_kcontrol *kcontrol,
175 struct snd_ctl_elem_value *ucontrol)
176{
177 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
178 struct soc_mixer_control *mc =
179 (struct soc_mixer_control *)kcontrol->private_value;
180 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
181 int i;
182
183 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
184 /*
185 * Register values will be cached before suspend. The cached value
186 * will be a valid value and userspace will happy with that.
187 */
188 for (i = 0; i < max98373->cache_num; i++) {
189 if (mc->reg == max98373->cache[i].reg) {
190 ucontrol->value.integer.value[0] = max98373->cache[i].val;
191 return 0;
192 }
193 }
194 }
195
196 return snd_soc_get_volsw(kcontrol, ucontrol);
197}
198
199static const struct snd_kcontrol_new max98373_snd_controls[] = {
200SOC_SINGLE("Digital Vol Sel Switch", MAX98373_R203F_AMP_DSP_CFG,
201 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
202SOC_SINGLE("Volume Location Switch", MAX98373_R203F_AMP_DSP_CFG,
203 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
204SOC_SINGLE("Ramp Up Switch", MAX98373_R203F_AMP_DSP_CFG,
205 MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0),
206SOC_SINGLE("Ramp Down Switch", MAX98373_R203F_AMP_DSP_CFG,
207 MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0),
208/* Speaker Amplifier Overcurrent Automatic Restart Enable */
209SOC_SINGLE("OVC Autorestart Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
210 MAX98373_OVC_AUTORESTART_SHIFT, 1, 0),
211/* Thermal Shutdown Automatic Restart Enable */
212SOC_SINGLE("THERM Autorestart Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
213 MAX98373_THERM_AUTORESTART_SHIFT, 1, 0),
214/* Clock Monitor Automatic Restart Enable */
215SOC_SINGLE("CMON Autorestart Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
216 MAX98373_CMON_AUTORESTART_SHIFT, 1, 0),
217SOC_SINGLE("CLK Monitor Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
218 MAX98373_CLOCK_MON_SHIFT, 1, 0),
219SOC_SINGLE("Dither Switch", MAX98373_R203F_AMP_DSP_CFG,
220 MAX98373_AMP_DSP_CFG_DITH_SHIFT, 1, 0),
221SOC_SINGLE("DC Blocker Switch", MAX98373_R203F_AMP_DSP_CFG,
222 MAX98373_AMP_DSP_CFG_DCBLK_SHIFT, 1, 0),
223SOC_SINGLE_TLV("Digital Volume", MAX98373_R203D_AMP_DIG_VOL_CTRL,
224 0, 0x7F, 1, max98373_digital_tlv),
225SOC_SINGLE_TLV("Speaker Volume", MAX98373_R203E_AMP_PATH_GAIN,
226 MAX98373_SPK_DIGI_GAIN_SHIFT, 10, 0, max98373_spk_tlv),
227SOC_SINGLE_TLV("FS Max Volume", MAX98373_R203E_AMP_PATH_GAIN,
228 MAX98373_FS_GAIN_MAX_SHIFT, 9, 0, max98373_spkgain_max_tlv),
229SOC_ENUM("Output Voltage", max98373_out_volt_enum),
230/* Dynamic Headroom Tracking */
231SOC_SINGLE("DHT Switch", MAX98373_R20D4_DHT_EN,
232 MAX98373_DHT_EN_SHIFT, 1, 0),
233SOC_SINGLE_TLV("DHT Min Volume", MAX98373_R20D1_DHT_CFG,
234 MAX98373_DHT_SPK_GAIN_MIN_SHIFT, 9, 0, max98373_dht_spkgain_min_tlv),
235SOC_SINGLE_TLV("DHT Rot Pnt Volume", MAX98373_R20D1_DHT_CFG,
236 MAX98373_DHT_ROT_PNT_SHIFT, 15, 1, max98373_dht_rotation_point_tlv),
237SOC_SINGLE_TLV("DHT Attack Step Volume", MAX98373_R20D2_DHT_ATTACK_CFG,
238 MAX98373_DHT_ATTACK_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
239SOC_SINGLE_TLV("DHT Release Step Volume", MAX98373_R20D3_DHT_RELEASE_CFG,
240 MAX98373_DHT_RELEASE_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
241SOC_ENUM("DHT Attack Rate", max98373_dht_attack_rate_enum),
242SOC_ENUM("DHT Release Rate", max98373_dht_release_rate_enum),
243/* ADC configuration */
244SOC_SINGLE("ADC PVDD CH Switch", MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0, 1, 0),
245SOC_SINGLE("ADC PVDD FLT Switch", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
246 MAX98373_FLT_EN_SHIFT, 1, 0),
247SOC_SINGLE("ADC TEMP FLT Switch", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
248 MAX98373_FLT_EN_SHIFT, 1, 0),
249SOC_SINGLE_EXT("ADC PVDD", MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0, 0xFF, 0,
250 max98373_feedback_get, NULL),
251SOC_SINGLE_EXT("ADC TEMP", MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0, 0xFF, 0,
252 max98373_feedback_get, NULL),
253SOC_SINGLE("ADC PVDD FLT Coeff", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
254 0, 0x3, 0),
255SOC_SINGLE("ADC TEMP FLT Coeff", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
256 0, 0x3, 0),
257SOC_ENUM("ADC SampleRate", max98373_adc_samplerate_enum),
258/* Brownout Detection Engine */
259SOC_SINGLE("BDE Switch", MAX98373_R20B5_BDE_EN, MAX98373_BDE_EN_SHIFT, 1, 0),
260SOC_SINGLE("BDE LVL4 Mute Switch", MAX98373_R20B2_BDE_L4_CFG_2,
261 MAX98373_LVL4_MUTE_EN_SHIFT, 1, 0),
262SOC_SINGLE("BDE LVL4 Hold Switch", MAX98373_R20B2_BDE_L4_CFG_2,
263 MAX98373_LVL4_HOLD_EN_SHIFT, 1, 0),
264SOC_SINGLE("BDE LVL1 Thresh", MAX98373_R2097_BDE_L1_THRESH, 0, 0xFF, 0),
265SOC_SINGLE("BDE LVL2 Thresh", MAX98373_R2098_BDE_L2_THRESH, 0, 0xFF, 0),
266SOC_SINGLE("BDE LVL3 Thresh", MAX98373_R2099_BDE_L3_THRESH, 0, 0xFF, 0),
267SOC_SINGLE("BDE LVL4 Thresh", MAX98373_R209A_BDE_L4_THRESH, 0, 0xFF, 0),
268SOC_SINGLE_EXT("BDE Active Level", MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0, 8, 0,
269 max98373_feedback_get, NULL),
270SOC_SINGLE("BDE Clip Mode Switch", MAX98373_R2092_BDE_CLIPPER_MODE, 0, 1, 0),
271SOC_SINGLE("BDE Thresh Hysteresis", MAX98373_R209B_BDE_THRESH_HYST, 0, 0xFF, 0),
272SOC_SINGLE("BDE Hold Time", MAX98373_R2090_BDE_LVL_HOLD, 0, 0xFF, 0),
273SOC_SINGLE("BDE Attack Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 4, 0xF, 0),
274SOC_SINGLE("BDE Release Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0, 0xF, 0),
275SOC_SINGLE_TLV("BDE LVL1 Clip Thresh Volume", MAX98373_R20A9_BDE_L1_CFG_2,
276 0, 0x3C, 1, max98373_bde_gain_tlv),
277SOC_SINGLE_TLV("BDE LVL2 Clip Thresh Volume", MAX98373_R20AC_BDE_L2_CFG_2,
278 0, 0x3C, 1, max98373_bde_gain_tlv),
279SOC_SINGLE_TLV("BDE LVL3 Clip Thresh Volume", MAX98373_R20AF_BDE_L3_CFG_2,
280 0, 0x3C, 1, max98373_bde_gain_tlv),
281SOC_SINGLE_TLV("BDE LVL4 Clip Thresh Volume", MAX98373_R20B2_BDE_L4_CFG_2,
282 0, 0x3C, 1, max98373_bde_gain_tlv),
283SOC_SINGLE_TLV("BDE LVL1 Clip Reduction Volume", MAX98373_R20AA_BDE_L1_CFG_3,
284 0, 0x3C, 1, max98373_bde_gain_tlv),
285SOC_SINGLE_TLV("BDE LVL2 Clip Reduction Volume", MAX98373_R20AD_BDE_L2_CFG_3,
286 0, 0x3C, 1, max98373_bde_gain_tlv),
287SOC_SINGLE_TLV("BDE LVL3 Clip Reduction Volume", MAX98373_R20B0_BDE_L3_CFG_3,
288 0, 0x3C, 1, max98373_bde_gain_tlv),
289SOC_SINGLE_TLV("BDE LVL4 Clip Reduction Volume", MAX98373_R20B3_BDE_L4_CFG_3,
290 0, 0x3C, 1, max98373_bde_gain_tlv),
291SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1,
292 0, 0xF, 1, max98373_limiter_thresh_tlv),
293SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh Volume", MAX98373_R20AB_BDE_L2_CFG_1,
294 0, 0xF, 1, max98373_limiter_thresh_tlv),
295SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh Volume", MAX98373_R20AE_BDE_L3_CFG_1,
296 0, 0xF, 1, max98373_limiter_thresh_tlv),
297SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh Volume", MAX98373_R20B1_BDE_L4_CFG_1,
298 0, 0xF, 1, max98373_limiter_thresh_tlv),
299/* Limiter */
300SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN,
301 MAX98373_LIMITER_EN_SHIFT, 1, 0),
302SOC_SINGLE("Limiter Src Switch", MAX98373_R20E0_LIMITER_THRESH_CFG,
303 MAX98373_LIMITER_THRESH_SRC_SHIFT, 1, 0),
304SOC_SINGLE_TLV("Limiter Thresh Volume", MAX98373_R20E0_LIMITER_THRESH_CFG,
305 MAX98373_LIMITER_THRESH_SHIFT, 15, 0, max98373_limiter_thresh_tlv),
306SOC_ENUM("Limiter Attack Rate", max98373_limiter_attack_rate_enum),
307SOC_ENUM("Limiter Release Rate", max98373_limiter_release_rate_enum),
308};
309
310static const struct snd_soc_dapm_route max98373_audio_map[] = {
311 /* Plabyack */
312 {"DAI Sel Mux", "Left", "Amp Enable"},
313 {"DAI Sel Mux", "Right", "Amp Enable"},
314 {"DAI Sel Mux", "LeftRight", "Amp Enable"},
315 {"BE_OUT", NULL, "DAI Sel Mux"},
316 /* Capture */
317 { "VI Sense", "Switch", "VMON" },
318 { "VI Sense", "Switch", "IMON" },
319 { "SpkFB Sense", "Switch", "FBMON" },
320 { "Voltage Sense", NULL, "VI Sense" },
321 { "Current Sense", NULL, "VI Sense" },
322 { "Speaker FB Sense", NULL, "SpkFB Sense" },
323};
324
325void max98373_reset(struct max98373_priv *max98373, struct device *dev)
326{
327 int ret, reg, count;
328
329 /* Software Reset */
330 ret = regmap_update_bits(max98373->regmap,
331 MAX98373_R2000_SW_RESET,
332 MAX98373_SOFT_RESET,
333 MAX98373_SOFT_RESET);
334 if (ret)
335 dev_err(dev, "Reset command failed. (ret:%d)\n", ret);
336
337 count = 0;
338 while (count < 3) {
339 usleep_range(10000, 11000);
340 /* Software Reset Verification */
341 ret = regmap_read(max98373->regmap,
342 MAX98373_R21FF_REV_ID, ®);
343 if (!ret) {
344 dev_info(dev, "Reset completed (retry:%d)\n", count);
345 return;
346 }
347 count++;
348 }
349 dev_err(dev, "Reset failed. (ret:%d)\n", ret);
350}
351EXPORT_SYMBOL_GPL(max98373_reset);
352
353static int max98373_probe(struct snd_soc_component *component)
354{
355 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
356
357 /* Software Reset */
358 max98373_reset(max98373, component->dev);
359
360 /* IV default slot configuration */
361 regmap_write(max98373->regmap,
362 MAX98373_R2020_PCM_TX_HIZ_EN_1,
363 0xFF);
364 regmap_write(max98373->regmap,
365 MAX98373_R2021_PCM_TX_HIZ_EN_2,
366 0xFF);
367 /* L/R mix configuration */
368 regmap_write(max98373->regmap,
369 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
370 0x80);
371 regmap_write(max98373->regmap,
372 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
373 0x1);
374 /* Enable DC blocker */
375 regmap_write(max98373->regmap,
376 MAX98373_R203F_AMP_DSP_CFG,
377 0x3);
378 /* Enable IMON VMON DC blocker */
379 regmap_write(max98373->regmap,
380 MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
381 0x7);
382 /* voltage, current slot configuration */
383 regmap_write(max98373->regmap,
384 MAX98373_R2022_PCM_TX_SRC_1,
385 (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
386 max98373->v_slot) & 0xFF);
387 if (max98373->v_slot < 8)
388 regmap_update_bits(max98373->regmap,
389 MAX98373_R2020_PCM_TX_HIZ_EN_1,
390 1 << max98373->v_slot, 0);
391 else
392 regmap_update_bits(max98373->regmap,
393 MAX98373_R2021_PCM_TX_HIZ_EN_2,
394 1 << (max98373->v_slot - 8), 0);
395
396 if (max98373->i_slot < 8)
397 regmap_update_bits(max98373->regmap,
398 MAX98373_R2020_PCM_TX_HIZ_EN_1,
399 1 << max98373->i_slot, 0);
400 else
401 regmap_update_bits(max98373->regmap,
402 MAX98373_R2021_PCM_TX_HIZ_EN_2,
403 1 << (max98373->i_slot - 8), 0);
404
405 /* enable auto restart function by default */
406 regmap_write(max98373->regmap,
407 MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
408 0xF);
409
410 /* speaker feedback slot configuration */
411 regmap_write(max98373->regmap,
412 MAX98373_R2023_PCM_TX_SRC_2,
413 max98373->spkfb_slot & 0xFF);
414
415 /* Set interleave mode */
416 if (max98373->interleave_mode)
417 regmap_update_bits(max98373->regmap,
418 MAX98373_R2024_PCM_DATA_FMT_CFG,
419 MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
420 MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
421
422 /* Speaker enable */
423 regmap_update_bits(max98373->regmap,
424 MAX98373_R2043_AMP_EN,
425 MAX98373_SPK_EN_MASK, 1);
426
427 return 0;
428}
429
430const struct snd_soc_component_driver soc_codec_dev_max98373 = {
431 .probe = max98373_probe,
432 .controls = max98373_snd_controls,
433 .num_controls = ARRAY_SIZE(max98373_snd_controls),
434 .dapm_widgets = max98373_dapm_widgets,
435 .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets),
436 .dapm_routes = max98373_audio_map,
437 .num_dapm_routes = ARRAY_SIZE(max98373_audio_map),
438 .use_pmdown_time = 1,
439 .endianness = 1,
440};
441EXPORT_SYMBOL_GPL(soc_codec_dev_max98373);
442
443static int max98373_sdw_probe(struct snd_soc_component *component)
444{
445 int ret;
446
447 ret = pm_runtime_resume(component->dev);
448 if (ret < 0 && ret != -EACCES)
449 return ret;
450
451 return 0;
452}
453
454const struct snd_soc_component_driver soc_codec_dev_max98373_sdw = {
455 .probe = max98373_sdw_probe,
456 .controls = max98373_snd_controls,
457 .num_controls = ARRAY_SIZE(max98373_snd_controls),
458 .dapm_widgets = max98373_dapm_widgets,
459 .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets),
460 .dapm_routes = max98373_audio_map,
461 .num_dapm_routes = ARRAY_SIZE(max98373_audio_map),
462 .use_pmdown_time = 1,
463 .endianness = 1,
464};
465EXPORT_SYMBOL_GPL(soc_codec_dev_max98373_sdw);
466
467void max98373_slot_config(struct device *dev,
468 struct max98373_priv *max98373)
469{
470 int value;
471
472 if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value))
473 max98373->v_slot = value & 0xF;
474 else
475 max98373->v_slot = 0;
476
477 if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value))
478 max98373->i_slot = value & 0xF;
479 else
480 max98373->i_slot = 1;
481 if (dev->of_node) {
482 max98373->reset_gpio = of_get_named_gpio(dev->of_node,
483 "maxim,reset-gpio", 0);
484 if (!gpio_is_valid(max98373->reset_gpio)) {
485 dev_err(dev, "Looking up %s property in node %s failed %d\n",
486 "maxim,reset-gpio", dev->of_node->full_name,
487 max98373->reset_gpio);
488 } else {
489 dev_dbg(dev, "maxim,reset-gpio=%d",
490 max98373->reset_gpio);
491 }
492 } else {
493 /* this makes reset_gpio as invalid */
494 max98373->reset_gpio = -1;
495 }
496
497 if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value))
498 max98373->spkfb_slot = value & 0xF;
499 else
500 max98373->spkfb_slot = 2;
501}
502EXPORT_SYMBOL_GPL(max98373_slot_config);
503
504MODULE_DESCRIPTION("ALSA SoC MAX98373 driver");
505MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
506MODULE_LICENSE("GPL");