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1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017, Maxim Integrated
3
4#include <linux/acpi.h>
5#include <linux/delay.h>
6#include <linux/i2c.h>
7#include <linux/module.h>
8#include <linux/pm_runtime.h>
9#include <linux/regmap.h>
10#include <linux/slab.h>
11#include <linux/cdev.h>
12#include <sound/pcm.h>
13#include <sound/pcm_params.h>
14#include <sound/soc.h>
15#include <linux/gpio/consumer.h>
16#include <linux/of.h>
17#include <sound/tlv.h>
18#include "max98373.h"
19
20static int max98373_dac_event(struct snd_soc_dapm_widget *w,
21 struct snd_kcontrol *kcontrol, int event)
22{
23 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
24 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
25
26 switch (event) {
27 case SND_SOC_DAPM_POST_PMU:
28 regmap_update_bits(max98373->regmap,
29 MAX98373_R20FF_GLOBAL_SHDN,
30 MAX98373_GLOBAL_EN_MASK, 1);
31 usleep_range(30000, 31000);
32 break;
33 case SND_SOC_DAPM_PRE_PMD:
34 regmap_update_bits(max98373->regmap,
35 MAX98373_R20FF_GLOBAL_SHDN,
36 MAX98373_GLOBAL_EN_MASK, 0);
37 usleep_range(30000, 31000);
38 max98373->tdm_mode = false;
39 break;
40 default:
41 return 0;
42 }
43 return 0;
44}
45
46static const char * const max98373_switch_text[] = {
47 "Left", "Right", "LeftRight"};
48
49static const struct soc_enum dai_sel_enum =
50 SOC_ENUM_SINGLE(MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
51 MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
52 3, max98373_switch_text);
53
54static const struct snd_kcontrol_new max98373_dai_controls =
55 SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
56
57static const struct snd_kcontrol_new max98373_vi_control =
58 SOC_DAPM_SINGLE("Switch", MAX98373_R202C_PCM_TX_EN, 0, 1, 0);
59
60static const struct snd_kcontrol_new max98373_spkfb_control =
61 SOC_DAPM_SINGLE("Switch", MAX98373_R2043_AMP_EN, 1, 1, 0);
62
63static const struct snd_soc_dapm_widget max98373_dapm_widgets[] = {
64SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
65 MAX98373_R202B_PCM_RX_EN, 0, 0, max98373_dac_event,
66 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
67SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
68 &max98373_dai_controls),
69SND_SOC_DAPM_OUTPUT("BE_OUT"),
70SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
71 MAX98373_R2047_IV_SENSE_ADC_EN, 0, 0),
72SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
73 MAX98373_R2047_IV_SENSE_ADC_EN, 1, 0),
74SND_SOC_DAPM_AIF_OUT("Speaker FB Sense", "HiFi Capture", 0,
75 SND_SOC_NOPM, 0, 0),
76SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
77 &max98373_vi_control),
78SND_SOC_DAPM_SWITCH("SpkFB Sense", SND_SOC_NOPM, 0, 0,
79 &max98373_spkfb_control),
80SND_SOC_DAPM_SIGGEN("VMON"),
81SND_SOC_DAPM_SIGGEN("IMON"),
82SND_SOC_DAPM_SIGGEN("FBMON"),
83};
84
85static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, -6350, 50, 1);
86static const DECLARE_TLV_DB_RANGE(max98373_spk_tlv,
87 0, 8, TLV_DB_SCALE_ITEM(0, 50, 0),
88 9, 10, TLV_DB_SCALE_ITEM(500, 100, 0),
89);
90static const DECLARE_TLV_DB_RANGE(max98373_spkgain_max_tlv,
91 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
92);
93static const DECLARE_TLV_DB_RANGE(max98373_dht_step_size_tlv,
94 0, 1, TLV_DB_SCALE_ITEM(25, 25, 0),
95 2, 4, TLV_DB_SCALE_ITEM(100, 100, 0),
96);
97static const DECLARE_TLV_DB_RANGE(max98373_dht_spkgain_min_tlv,
98 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
99);
100static const DECLARE_TLV_DB_RANGE(max98373_dht_rotation_point_tlv,
101 0, 1, TLV_DB_SCALE_ITEM(-3000, 500, 0),
102 2, 4, TLV_DB_SCALE_ITEM(-2200, 200, 0),
103 5, 6, TLV_DB_SCALE_ITEM(-1500, 300, 0),
104 7, 9, TLV_DB_SCALE_ITEM(-1000, 200, 0),
105 10, 13, TLV_DB_SCALE_ITEM(-500, 100, 0),
106 14, 15, TLV_DB_SCALE_ITEM(-100, 50, 0),
107);
108static const DECLARE_TLV_DB_RANGE(max98373_limiter_thresh_tlv,
109 0, 15, TLV_DB_SCALE_ITEM(-1500, 100, 0),
110);
111
112static const DECLARE_TLV_DB_RANGE(max98373_bde_gain_tlv,
113 0, 60, TLV_DB_SCALE_ITEM(-1500, 25, 0),
114);
115
116static const char * const max98373_output_voltage_lvl_text[] = {
117 "5.43V", "6.09V", "6.83V", "7.67V", "8.60V",
118 "9.65V", "10.83V", "12.15V", "13.63V", "15.29V"
119};
120
121static SOC_ENUM_SINGLE_DECL(max98373_out_volt_enum,
122 MAX98373_R203E_AMP_PATH_GAIN, 0,
123 max98373_output_voltage_lvl_text);
124
125static const char * const max98373_dht_attack_rate_text[] = {
126 "17.5us", "35us", "70us", "140us",
127 "280us", "560us", "1120us", "2240us"
128};
129
130static SOC_ENUM_SINGLE_DECL(max98373_dht_attack_rate_enum,
131 MAX98373_R20D2_DHT_ATTACK_CFG, 0,
132 max98373_dht_attack_rate_text);
133
134static const char * const max98373_dht_release_rate_text[] = {
135 "45ms", "225ms", "450ms", "1150ms",
136 "2250ms", "3100ms", "4500ms", "6750ms"
137};
138
139static SOC_ENUM_SINGLE_DECL(max98373_dht_release_rate_enum,
140 MAX98373_R20D3_DHT_RELEASE_CFG, 0,
141 max98373_dht_release_rate_text);
142
143static const char * const max98373_limiter_attack_rate_text[] = {
144 "10us", "20us", "40us", "80us",
145 "160us", "320us", "640us", "1.28ms",
146 "2.56ms", "5.12ms", "10.24ms", "20.48ms",
147 "40.96ms", "81.92ms", "16.384ms", "32.768ms"
148};
149
150static SOC_ENUM_SINGLE_DECL(max98373_limiter_attack_rate_enum,
151 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 4,
152 max98373_limiter_attack_rate_text);
153
154static const char * const max98373_limiter_release_rate_text[] = {
155 "40us", "80us", "160us", "320us",
156 "640us", "1.28ms", "2.56ms", "5.120ms",
157 "10.24ms", "20.48ms", "40.96ms", "81.92ms",
158 "163.84ms", "327.68ms", "655.36ms", "1310.72ms"
159};
160
161static SOC_ENUM_SINGLE_DECL(max98373_limiter_release_rate_enum,
162 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0,
163 max98373_limiter_release_rate_text);
164
165static const char * const max98373_ADC_samplerate_text[] = {
166 "333kHz", "192kHz", "64kHz", "48kHz"
167};
168
169static SOC_ENUM_SINGLE_DECL(max98373_adc_samplerate_enum,
170 MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0,
171 max98373_ADC_samplerate_text);
172
173static int max98373_feedback_get(struct snd_kcontrol *kcontrol,
174 struct snd_ctl_elem_value *ucontrol)
175{
176 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
177 struct soc_mixer_control *mc =
178 (struct soc_mixer_control *)kcontrol->private_value;
179 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
180 int i;
181
182 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
183 /*
184 * Register values will be cached before suspend. The cached value
185 * will be a valid value and userspace will happy with that.
186 */
187 for (i = 0; i < max98373->cache_num; i++) {
188 if (mc->reg == max98373->cache[i].reg) {
189 ucontrol->value.integer.value[0] = max98373->cache[i].val;
190 return 0;
191 }
192 }
193 }
194
195 return snd_soc_get_volsw(kcontrol, ucontrol);
196}
197
198static const struct snd_kcontrol_new max98373_snd_controls[] = {
199SOC_SINGLE("Digital Vol Sel Switch", MAX98373_R203F_AMP_DSP_CFG,
200 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
201SOC_SINGLE("Volume Location Switch", MAX98373_R203F_AMP_DSP_CFG,
202 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
203SOC_SINGLE("Ramp Up Switch", MAX98373_R203F_AMP_DSP_CFG,
204 MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0),
205SOC_SINGLE("Ramp Down Switch", MAX98373_R203F_AMP_DSP_CFG,
206 MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0),
207/* Speaker Amplifier Overcurrent Automatic Restart Enable */
208SOC_SINGLE("OVC Autorestart Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
209 MAX98373_OVC_AUTORESTART_SHIFT, 1, 0),
210/* Thermal Shutdown Automatic Restart Enable */
211SOC_SINGLE("THERM Autorestart Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
212 MAX98373_THERM_AUTORESTART_SHIFT, 1, 0),
213/* Clock Monitor Automatic Restart Enable */
214SOC_SINGLE("CMON Autorestart Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
215 MAX98373_CMON_AUTORESTART_SHIFT, 1, 0),
216SOC_SINGLE("CLK Monitor Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
217 MAX98373_CLOCK_MON_SHIFT, 1, 0),
218SOC_SINGLE("Dither Switch", MAX98373_R203F_AMP_DSP_CFG,
219 MAX98373_AMP_DSP_CFG_DITH_SHIFT, 1, 0),
220SOC_SINGLE("DC Blocker Switch", MAX98373_R203F_AMP_DSP_CFG,
221 MAX98373_AMP_DSP_CFG_DCBLK_SHIFT, 1, 0),
222SOC_SINGLE_TLV("Digital Volume", MAX98373_R203D_AMP_DIG_VOL_CTRL,
223 0, 0x7F, 1, max98373_digital_tlv),
224SOC_SINGLE_TLV("Speaker Volume", MAX98373_R203E_AMP_PATH_GAIN,
225 MAX98373_SPK_DIGI_GAIN_SHIFT, 10, 0, max98373_spk_tlv),
226SOC_SINGLE_TLV("FS Max Volume", MAX98373_R203E_AMP_PATH_GAIN,
227 MAX98373_FS_GAIN_MAX_SHIFT, 9, 0, max98373_spkgain_max_tlv),
228SOC_ENUM("Output Voltage", max98373_out_volt_enum),
229/* Dynamic Headroom Tracking */
230SOC_SINGLE("DHT Switch", MAX98373_R20D4_DHT_EN,
231 MAX98373_DHT_EN_SHIFT, 1, 0),
232SOC_SINGLE_TLV("DHT Min Volume", MAX98373_R20D1_DHT_CFG,
233 MAX98373_DHT_SPK_GAIN_MIN_SHIFT, 9, 0, max98373_dht_spkgain_min_tlv),
234SOC_SINGLE_TLV("DHT Rot Pnt Volume", MAX98373_R20D1_DHT_CFG,
235 MAX98373_DHT_ROT_PNT_SHIFT, 15, 1, max98373_dht_rotation_point_tlv),
236SOC_SINGLE_TLV("DHT Attack Step Volume", MAX98373_R20D2_DHT_ATTACK_CFG,
237 MAX98373_DHT_ATTACK_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
238SOC_SINGLE_TLV("DHT Release Step Volume", MAX98373_R20D3_DHT_RELEASE_CFG,
239 MAX98373_DHT_RELEASE_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
240SOC_ENUM("DHT Attack Rate", max98373_dht_attack_rate_enum),
241SOC_ENUM("DHT Release Rate", max98373_dht_release_rate_enum),
242/* ADC configuration */
243SOC_SINGLE("ADC PVDD CH Switch", MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0, 1, 0),
244SOC_SINGLE("ADC PVDD FLT Switch", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
245 MAX98373_FLT_EN_SHIFT, 1, 0),
246SOC_SINGLE("ADC TEMP FLT Switch", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
247 MAX98373_FLT_EN_SHIFT, 1, 0),
248SOC_SINGLE_EXT("ADC PVDD", MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0, 0xFF, 0,
249 max98373_feedback_get, NULL),
250SOC_SINGLE_EXT("ADC TEMP", MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0, 0xFF, 0,
251 max98373_feedback_get, NULL),
252SOC_SINGLE("ADC PVDD FLT Coeff", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
253 0, 0x3, 0),
254SOC_SINGLE("ADC TEMP FLT Coeff", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
255 0, 0x3, 0),
256SOC_ENUM("ADC SampleRate", max98373_adc_samplerate_enum),
257/* Brownout Detection Engine */
258SOC_SINGLE("BDE Switch", MAX98373_R20B5_BDE_EN, MAX98373_BDE_EN_SHIFT, 1, 0),
259SOC_SINGLE("BDE LVL4 Mute Switch", MAX98373_R20B2_BDE_L4_CFG_2,
260 MAX98373_LVL4_MUTE_EN_SHIFT, 1, 0),
261SOC_SINGLE("BDE LVL4 Hold Switch", MAX98373_R20B2_BDE_L4_CFG_2,
262 MAX98373_LVL4_HOLD_EN_SHIFT, 1, 0),
263SOC_SINGLE("BDE LVL1 Thresh", MAX98373_R2097_BDE_L1_THRESH, 0, 0xFF, 0),
264SOC_SINGLE("BDE LVL2 Thresh", MAX98373_R2098_BDE_L2_THRESH, 0, 0xFF, 0),
265SOC_SINGLE("BDE LVL3 Thresh", MAX98373_R2099_BDE_L3_THRESH, 0, 0xFF, 0),
266SOC_SINGLE("BDE LVL4 Thresh", MAX98373_R209A_BDE_L4_THRESH, 0, 0xFF, 0),
267SOC_SINGLE_EXT("BDE Active Level", MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0, 8, 0,
268 max98373_feedback_get, NULL),
269SOC_SINGLE("BDE Clip Mode Switch", MAX98373_R2092_BDE_CLIPPER_MODE, 0, 1, 0),
270SOC_SINGLE("BDE Thresh Hysteresis", MAX98373_R209B_BDE_THRESH_HYST, 0, 0xFF, 0),
271SOC_SINGLE("BDE Hold Time", MAX98373_R2090_BDE_LVL_HOLD, 0, 0xFF, 0),
272SOC_SINGLE("BDE Attack Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 4, 0xF, 0),
273SOC_SINGLE("BDE Release Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0, 0xF, 0),
274SOC_SINGLE_TLV("BDE LVL1 Clip Thresh Volume", MAX98373_R20A9_BDE_L1_CFG_2,
275 0, 0x3C, 1, max98373_bde_gain_tlv),
276SOC_SINGLE_TLV("BDE LVL2 Clip Thresh Volume", MAX98373_R20AC_BDE_L2_CFG_2,
277 0, 0x3C, 1, max98373_bde_gain_tlv),
278SOC_SINGLE_TLV("BDE LVL3 Clip Thresh Volume", MAX98373_R20AF_BDE_L3_CFG_2,
279 0, 0x3C, 1, max98373_bde_gain_tlv),
280SOC_SINGLE_TLV("BDE LVL4 Clip Thresh Volume", MAX98373_R20B2_BDE_L4_CFG_2,
281 0, 0x3C, 1, max98373_bde_gain_tlv),
282SOC_SINGLE_TLV("BDE LVL1 Clip Reduction Volume", MAX98373_R20AA_BDE_L1_CFG_3,
283 0, 0x3C, 1, max98373_bde_gain_tlv),
284SOC_SINGLE_TLV("BDE LVL2 Clip Reduction Volume", MAX98373_R20AD_BDE_L2_CFG_3,
285 0, 0x3C, 1, max98373_bde_gain_tlv),
286SOC_SINGLE_TLV("BDE LVL3 Clip Reduction Volume", MAX98373_R20B0_BDE_L3_CFG_3,
287 0, 0x3C, 1, max98373_bde_gain_tlv),
288SOC_SINGLE_TLV("BDE LVL4 Clip Reduction Volume", MAX98373_R20B3_BDE_L4_CFG_3,
289 0, 0x3C, 1, max98373_bde_gain_tlv),
290SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1,
291 0, 0xF, 1, max98373_limiter_thresh_tlv),
292SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh Volume", MAX98373_R20AB_BDE_L2_CFG_1,
293 0, 0xF, 1, max98373_limiter_thresh_tlv),
294SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh Volume", MAX98373_R20AE_BDE_L3_CFG_1,
295 0, 0xF, 1, max98373_limiter_thresh_tlv),
296SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh Volume", MAX98373_R20B1_BDE_L4_CFG_1,
297 0, 0xF, 1, max98373_limiter_thresh_tlv),
298/* Limiter */
299SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN,
300 MAX98373_LIMITER_EN_SHIFT, 1, 0),
301SOC_SINGLE("Limiter Src Switch", MAX98373_R20E0_LIMITER_THRESH_CFG,
302 MAX98373_LIMITER_THRESH_SRC_SHIFT, 1, 0),
303SOC_SINGLE_TLV("Limiter Thresh Volume", MAX98373_R20E0_LIMITER_THRESH_CFG,
304 MAX98373_LIMITER_THRESH_SHIFT, 15, 0, max98373_limiter_thresh_tlv),
305SOC_ENUM("Limiter Attack Rate", max98373_limiter_attack_rate_enum),
306SOC_ENUM("Limiter Release Rate", max98373_limiter_release_rate_enum),
307};
308
309static const struct snd_soc_dapm_route max98373_audio_map[] = {
310 /* Plabyack */
311 {"DAI Sel Mux", "Left", "Amp Enable"},
312 {"DAI Sel Mux", "Right", "Amp Enable"},
313 {"DAI Sel Mux", "LeftRight", "Amp Enable"},
314 {"BE_OUT", NULL, "DAI Sel Mux"},
315 /* Capture */
316 { "VI Sense", "Switch", "VMON" },
317 { "VI Sense", "Switch", "IMON" },
318 { "SpkFB Sense", "Switch", "FBMON" },
319 { "Voltage Sense", NULL, "VI Sense" },
320 { "Current Sense", NULL, "VI Sense" },
321 { "Speaker FB Sense", NULL, "SpkFB Sense" },
322};
323
324void max98373_reset(struct max98373_priv *max98373, struct device *dev)
325{
326 int ret, reg, count;
327
328 /* Software Reset */
329 ret = regmap_update_bits(max98373->regmap,
330 MAX98373_R2000_SW_RESET,
331 MAX98373_SOFT_RESET,
332 MAX98373_SOFT_RESET);
333 if (ret)
334 dev_err(dev, "Reset command failed. (ret:%d)\n", ret);
335
336 count = 0;
337 while (count < 3) {
338 usleep_range(10000, 11000);
339 /* Software Reset Verification */
340 ret = regmap_read(max98373->regmap,
341 MAX98373_R21FF_REV_ID, ®);
342 if (!ret) {
343 dev_info(dev, "Reset completed (retry:%d)\n", count);
344 return;
345 }
346 count++;
347 }
348 dev_err(dev, "Reset failed. (ret:%d)\n", ret);
349}
350EXPORT_SYMBOL_GPL(max98373_reset);
351
352static int max98373_probe(struct snd_soc_component *component)
353{
354 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
355
356 /* Software Reset */
357 max98373_reset(max98373, component->dev);
358
359 /* IV default slot configuration */
360 regmap_write(max98373->regmap,
361 MAX98373_R2020_PCM_TX_HIZ_EN_1,
362 0xFF);
363 regmap_write(max98373->regmap,
364 MAX98373_R2021_PCM_TX_HIZ_EN_2,
365 0xFF);
366 /* L/R mix configuration */
367 regmap_write(max98373->regmap,
368 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
369 0x80);
370 regmap_write(max98373->regmap,
371 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
372 0x1);
373 /* Enable DC blocker */
374 regmap_write(max98373->regmap,
375 MAX98373_R203F_AMP_DSP_CFG,
376 0x3);
377 /* Enable IMON VMON DC blocker */
378 regmap_write(max98373->regmap,
379 MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
380 0x7);
381 /* voltage, current slot configuration */
382 regmap_write(max98373->regmap,
383 MAX98373_R2022_PCM_TX_SRC_1,
384 (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
385 max98373->v_slot) & 0xFF);
386 if (max98373->v_slot < 8)
387 regmap_update_bits(max98373->regmap,
388 MAX98373_R2020_PCM_TX_HIZ_EN_1,
389 1 << max98373->v_slot, 0);
390 else
391 regmap_update_bits(max98373->regmap,
392 MAX98373_R2021_PCM_TX_HIZ_EN_2,
393 1 << (max98373->v_slot - 8), 0);
394
395 if (max98373->i_slot < 8)
396 regmap_update_bits(max98373->regmap,
397 MAX98373_R2020_PCM_TX_HIZ_EN_1,
398 1 << max98373->i_slot, 0);
399 else
400 regmap_update_bits(max98373->regmap,
401 MAX98373_R2021_PCM_TX_HIZ_EN_2,
402 1 << (max98373->i_slot - 8), 0);
403
404 /* enable auto restart function by default */
405 regmap_write(max98373->regmap,
406 MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
407 0xF);
408
409 /* speaker feedback slot configuration */
410 regmap_write(max98373->regmap,
411 MAX98373_R2023_PCM_TX_SRC_2,
412 max98373->spkfb_slot & 0xFF);
413
414 /* Set interleave mode */
415 if (max98373->interleave_mode)
416 regmap_update_bits(max98373->regmap,
417 MAX98373_R2024_PCM_DATA_FMT_CFG,
418 MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
419 MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
420
421 /* Speaker enable */
422 regmap_update_bits(max98373->regmap,
423 MAX98373_R2043_AMP_EN,
424 MAX98373_SPK_EN_MASK, 1);
425
426 return 0;
427}
428
429const struct snd_soc_component_driver soc_codec_dev_max98373 = {
430 .probe = max98373_probe,
431 .controls = max98373_snd_controls,
432 .num_controls = ARRAY_SIZE(max98373_snd_controls),
433 .dapm_widgets = max98373_dapm_widgets,
434 .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets),
435 .dapm_routes = max98373_audio_map,
436 .num_dapm_routes = ARRAY_SIZE(max98373_audio_map),
437 .use_pmdown_time = 1,
438 .endianness = 1,
439};
440EXPORT_SYMBOL_GPL(soc_codec_dev_max98373);
441
442static int max98373_sdw_probe(struct snd_soc_component *component)
443{
444 int ret;
445
446 ret = pm_runtime_resume(component->dev);
447 if (ret < 0 && ret != -EACCES)
448 return ret;
449
450 return 0;
451}
452
453const struct snd_soc_component_driver soc_codec_dev_max98373_sdw = {
454 .probe = max98373_sdw_probe,
455 .controls = max98373_snd_controls,
456 .num_controls = ARRAY_SIZE(max98373_snd_controls),
457 .dapm_widgets = max98373_dapm_widgets,
458 .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets),
459 .dapm_routes = max98373_audio_map,
460 .num_dapm_routes = ARRAY_SIZE(max98373_audio_map),
461 .use_pmdown_time = 1,
462 .endianness = 1,
463};
464EXPORT_SYMBOL_GPL(soc_codec_dev_max98373_sdw);
465
466void max98373_slot_config(struct device *dev,
467 struct max98373_priv *max98373)
468{
469 int value;
470
471 if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value))
472 max98373->v_slot = value & 0xF;
473 else
474 max98373->v_slot = 0;
475
476 if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value))
477 max98373->i_slot = value & 0xF;
478 else
479 max98373->i_slot = 1;
480
481 /* This will assert RESET */
482 max98373->reset = devm_gpiod_get_optional(dev,
483 "maxim,reset",
484 GPIOD_OUT_HIGH);
485 if (IS_ERR(max98373->reset)) {
486 dev_err(dev, "error %ld looking up RESET GPIO line\n",
487 PTR_ERR(max98373->reset));
488 return;
489 }
490
491 /* Cycle reset */
492 if (max98373->reset) {
493 gpiod_set_consumer_name(max98373->reset ,"MAX98373_RESET");
494 gpiod_direction_output(max98373->reset, 1);
495 msleep(50);
496 gpiod_direction_output(max98373->reset, 0);
497 msleep(20);
498 }
499
500 if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value))
501 max98373->spkfb_slot = value & 0xF;
502 else
503 max98373->spkfb_slot = 2;
504}
505EXPORT_SYMBOL_GPL(max98373_slot_config);
506
507MODULE_DESCRIPTION("ALSA SoC MAX98373 driver");
508MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
509MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017, Maxim Integrated
3
4#include <linux/acpi.h>
5#include <linux/i2c.h>
6#include <linux/module.h>
7#include <linux/regmap.h>
8#include <linux/slab.h>
9#include <linux/cdev.h>
10#include <sound/pcm.h>
11#include <sound/pcm_params.h>
12#include <sound/soc.h>
13#include <linux/gpio.h>
14#include <linux/of_gpio.h>
15#include <sound/tlv.h>
16#include "max98373.h"
17
18static struct reg_default max98373_reg[] = {
19 {MAX98373_R2000_SW_RESET, 0x00},
20 {MAX98373_R2001_INT_RAW1, 0x00},
21 {MAX98373_R2002_INT_RAW2, 0x00},
22 {MAX98373_R2003_INT_RAW3, 0x00},
23 {MAX98373_R2004_INT_STATE1, 0x00},
24 {MAX98373_R2005_INT_STATE2, 0x00},
25 {MAX98373_R2006_INT_STATE3, 0x00},
26 {MAX98373_R2007_INT_FLAG1, 0x00},
27 {MAX98373_R2008_INT_FLAG2, 0x00},
28 {MAX98373_R2009_INT_FLAG3, 0x00},
29 {MAX98373_R200A_INT_EN1, 0x00},
30 {MAX98373_R200B_INT_EN2, 0x00},
31 {MAX98373_R200C_INT_EN3, 0x00},
32 {MAX98373_R200D_INT_FLAG_CLR1, 0x00},
33 {MAX98373_R200E_INT_FLAG_CLR2, 0x00},
34 {MAX98373_R200F_INT_FLAG_CLR3, 0x00},
35 {MAX98373_R2010_IRQ_CTRL, 0x00},
36 {MAX98373_R2014_THERM_WARN_THRESH, 0x10},
37 {MAX98373_R2015_THERM_SHDN_THRESH, 0x27},
38 {MAX98373_R2016_THERM_HYSTERESIS, 0x01},
39 {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0},
40 {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00},
41 {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55},
42 {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE},
43 {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF},
44 {MAX98373_R2022_PCM_TX_SRC_1, 0x00},
45 {MAX98373_R2023_PCM_TX_SRC_2, 0x00},
46 {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0},
47 {MAX98373_R2025_AUDIO_IF_MODE, 0x00},
48 {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04},
49 {MAX98373_R2027_PCM_SR_SETUP_1, 0x08},
50 {MAX98373_R2028_PCM_SR_SETUP_2, 0x88},
51 {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00},
52 {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00},
53 {MAX98373_R202B_PCM_RX_EN, 0x00},
54 {MAX98373_R202C_PCM_TX_EN, 0x00},
55 {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00},
56 {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00},
57 {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF},
58 {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF},
59 {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30},
60 {MAX98373_R2034_ICC_TX_CNTL, 0x00},
61 {MAX98373_R2035_ICC_TX_EN, 0x00},
62 {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05},
63 {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00},
64 {MAX98373_R203E_AMP_PATH_GAIN, 0x08},
65 {MAX98373_R203F_AMP_DSP_CFG, 0x02},
66 {MAX98373_R2040_TONE_GEN_CFG, 0x00},
67 {MAX98373_R2041_AMP_CFG, 0x03},
68 {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00},
69 {MAX98373_R2043_AMP_EN, 0x00},
70 {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04},
71 {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00},
72 {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00},
73 {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00},
74 {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00},
75 {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00},
76 {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00},
77 {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00},
78 {MAX98373_R2090_BDE_LVL_HOLD, 0x00},
79 {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00},
80 {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00},
81 {MAX98373_R2097_BDE_L1_THRESH, 0x00},
82 {MAX98373_R2098_BDE_L2_THRESH, 0x00},
83 {MAX98373_R2099_BDE_L3_THRESH, 0x00},
84 {MAX98373_R209A_BDE_L4_THRESH, 0x00},
85 {MAX98373_R209B_BDE_THRESH_HYST, 0x00},
86 {MAX98373_R20A8_BDE_L1_CFG_1, 0x00},
87 {MAX98373_R20A9_BDE_L1_CFG_2, 0x00},
88 {MAX98373_R20AA_BDE_L1_CFG_3, 0x00},
89 {MAX98373_R20AB_BDE_L2_CFG_1, 0x00},
90 {MAX98373_R20AC_BDE_L2_CFG_2, 0x00},
91 {MAX98373_R20AD_BDE_L2_CFG_3, 0x00},
92 {MAX98373_R20AE_BDE_L3_CFG_1, 0x00},
93 {MAX98373_R20AF_BDE_L3_CFG_2, 0x00},
94 {MAX98373_R20B0_BDE_L3_CFG_3, 0x00},
95 {MAX98373_R20B1_BDE_L4_CFG_1, 0x00},
96 {MAX98373_R20B2_BDE_L4_CFG_2, 0x00},
97 {MAX98373_R20B3_BDE_L4_CFG_3, 0x00},
98 {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00},
99 {MAX98373_R20B5_BDE_EN, 0x00},
100 {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00},
101 {MAX98373_R20D1_DHT_CFG, 0x01},
102 {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02},
103 {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03},
104 {MAX98373_R20D4_DHT_EN, 0x00},
105 {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00},
106 {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00},
107 {MAX98373_R20E2_LIMITER_EN, 0x00},
108 {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00},
109 {MAX98373_R20FF_GLOBAL_SHDN, 0x00},
110 {MAX98373_R21FF_REV_ID, 0x42},
111};
112
113static int max98373_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
114{
115 struct snd_soc_component *component = codec_dai->component;
116 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
117 unsigned int format = 0;
118 unsigned int invert = 0;
119
120 dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
121
122 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
123 case SND_SOC_DAIFMT_NB_NF:
124 break;
125 case SND_SOC_DAIFMT_IB_NF:
126 invert = MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE;
127 break;
128 default:
129 dev_err(component->dev, "DAI invert mode unsupported\n");
130 return -EINVAL;
131 }
132
133 regmap_update_bits(max98373->regmap,
134 MAX98373_R2026_PCM_CLOCK_RATIO,
135 MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE,
136 invert);
137
138 /* interface format */
139 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
140 case SND_SOC_DAIFMT_I2S:
141 format = MAX98373_PCM_FORMAT_I2S;
142 break;
143 case SND_SOC_DAIFMT_LEFT_J:
144 format = MAX98373_PCM_FORMAT_LJ;
145 break;
146 case SND_SOC_DAIFMT_DSP_A:
147 format = MAX98373_PCM_FORMAT_TDM_MODE1;
148 break;
149 case SND_SOC_DAIFMT_DSP_B:
150 format = MAX98373_PCM_FORMAT_TDM_MODE0;
151 break;
152 default:
153 return -EINVAL;
154 }
155
156 regmap_update_bits(max98373->regmap,
157 MAX98373_R2024_PCM_DATA_FMT_CFG,
158 MAX98373_PCM_MODE_CFG_FORMAT_MASK,
159 format << MAX98373_PCM_MODE_CFG_FORMAT_SHIFT);
160
161 return 0;
162}
163
164/* BCLKs per LRCLK */
165static const int bclk_sel_table[] = {
166 32, 48, 64, 96, 128, 192, 256, 384, 512, 320,
167};
168
169static int max98373_get_bclk_sel(int bclk)
170{
171 int i;
172 /* match BCLKs per LRCLK */
173 for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
174 if (bclk_sel_table[i] == bclk)
175 return i + 2;
176 }
177 return 0;
178}
179
180static int max98373_set_clock(struct snd_soc_component *component,
181 struct snd_pcm_hw_params *params)
182{
183 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
184 /* BCLK/LRCLK ratio calculation */
185 int blr_clk_ratio = params_channels(params) * max98373->ch_size;
186 int value;
187
188 if (!max98373->tdm_mode) {
189 /* BCLK configuration */
190 value = max98373_get_bclk_sel(blr_clk_ratio);
191 if (!value) {
192 dev_err(component->dev, "format unsupported %d\n",
193 params_format(params));
194 return -EINVAL;
195 }
196
197 regmap_update_bits(max98373->regmap,
198 MAX98373_R2026_PCM_CLOCK_RATIO,
199 MAX98373_PCM_CLK_SETUP_BSEL_MASK,
200 value);
201 }
202 return 0;
203}
204
205static int max98373_dai_hw_params(struct snd_pcm_substream *substream,
206 struct snd_pcm_hw_params *params,
207 struct snd_soc_dai *dai)
208{
209 struct snd_soc_component *component = dai->component;
210 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
211 unsigned int sampling_rate = 0;
212 unsigned int chan_sz = 0;
213
214 /* pcm mode configuration */
215 switch (snd_pcm_format_width(params_format(params))) {
216 case 16:
217 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
218 break;
219 case 24:
220 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
221 break;
222 case 32:
223 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
224 break;
225 default:
226 dev_err(component->dev, "format unsupported %d\n",
227 params_format(params));
228 goto err;
229 }
230
231 max98373->ch_size = snd_pcm_format_width(params_format(params));
232
233 regmap_update_bits(max98373->regmap,
234 MAX98373_R2024_PCM_DATA_FMT_CFG,
235 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
236
237 dev_dbg(component->dev, "format supported %d",
238 params_format(params));
239
240 /* sampling rate configuration */
241 switch (params_rate(params)) {
242 case 8000:
243 sampling_rate = MAX98373_PCM_SR_SET1_SR_8000;
244 break;
245 case 11025:
246 sampling_rate = MAX98373_PCM_SR_SET1_SR_11025;
247 break;
248 case 12000:
249 sampling_rate = MAX98373_PCM_SR_SET1_SR_12000;
250 break;
251 case 16000:
252 sampling_rate = MAX98373_PCM_SR_SET1_SR_16000;
253 break;
254 case 22050:
255 sampling_rate = MAX98373_PCM_SR_SET1_SR_22050;
256 break;
257 case 24000:
258 sampling_rate = MAX98373_PCM_SR_SET1_SR_24000;
259 break;
260 case 32000:
261 sampling_rate = MAX98373_PCM_SR_SET1_SR_32000;
262 break;
263 case 44100:
264 sampling_rate = MAX98373_PCM_SR_SET1_SR_44100;
265 break;
266 case 48000:
267 sampling_rate = MAX98373_PCM_SR_SET1_SR_48000;
268 break;
269 default:
270 dev_err(component->dev, "rate %d not supported\n",
271 params_rate(params));
272 goto err;
273 }
274
275 /* set DAI_SR to correct LRCLK frequency */
276 regmap_update_bits(max98373->regmap,
277 MAX98373_R2027_PCM_SR_SETUP_1,
278 MAX98373_PCM_SR_SET1_SR_MASK,
279 sampling_rate);
280 regmap_update_bits(max98373->regmap,
281 MAX98373_R2028_PCM_SR_SETUP_2,
282 MAX98373_PCM_SR_SET2_SR_MASK,
283 sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT);
284
285 /* set sampling rate of IV */
286 if (max98373->interleave_mode &&
287 sampling_rate > MAX98373_PCM_SR_SET1_SR_16000)
288 regmap_update_bits(max98373->regmap,
289 MAX98373_R2028_PCM_SR_SETUP_2,
290 MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
291 sampling_rate - 3);
292 else
293 regmap_update_bits(max98373->regmap,
294 MAX98373_R2028_PCM_SR_SETUP_2,
295 MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
296 sampling_rate);
297
298 return max98373_set_clock(component, params);
299err:
300 return -EINVAL;
301}
302
303static int max98373_dai_tdm_slot(struct snd_soc_dai *dai,
304 unsigned int tx_mask, unsigned int rx_mask,
305 int slots, int slot_width)
306{
307 struct snd_soc_component *component = dai->component;
308 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
309 int bsel = 0;
310 unsigned int chan_sz = 0;
311 unsigned int mask;
312 int x, slot_found;
313
314 if (!tx_mask && !rx_mask && !slots && !slot_width)
315 max98373->tdm_mode = false;
316 else
317 max98373->tdm_mode = true;
318
319 /* BCLK configuration */
320 bsel = max98373_get_bclk_sel(slots * slot_width);
321 if (bsel == 0) {
322 dev_err(component->dev, "BCLK %d not supported\n",
323 slots * slot_width);
324 return -EINVAL;
325 }
326
327 regmap_update_bits(max98373->regmap,
328 MAX98373_R2026_PCM_CLOCK_RATIO,
329 MAX98373_PCM_CLK_SETUP_BSEL_MASK,
330 bsel);
331
332 /* Channel size configuration */
333 switch (slot_width) {
334 case 16:
335 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
336 break;
337 case 24:
338 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
339 break;
340 case 32:
341 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
342 break;
343 default:
344 dev_err(component->dev, "format unsupported %d\n",
345 slot_width);
346 return -EINVAL;
347 }
348
349 regmap_update_bits(max98373->regmap,
350 MAX98373_R2024_PCM_DATA_FMT_CFG,
351 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
352
353 /* Rx slot configuration */
354 slot_found = 0;
355 mask = rx_mask;
356 for (x = 0 ; x < 16 ; x++, mask >>= 1) {
357 if (mask & 0x1) {
358 if (slot_found == 0)
359 regmap_update_bits(max98373->regmap,
360 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
361 MAX98373_PCM_TO_SPK_CH0_SRC_MASK, x);
362 else
363 regmap_write(max98373->regmap,
364 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
365 x);
366 slot_found++;
367 if (slot_found > 1)
368 break;
369 }
370 }
371
372 /* Tx slot Hi-Z configuration */
373 regmap_write(max98373->regmap,
374 MAX98373_R2020_PCM_TX_HIZ_EN_1,
375 ~tx_mask & 0xFF);
376 regmap_write(max98373->regmap,
377 MAX98373_R2021_PCM_TX_HIZ_EN_2,
378 (~tx_mask & 0xFF00) >> 8);
379
380 return 0;
381}
382
383#define MAX98373_RATES SNDRV_PCM_RATE_8000_96000
384
385#define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
386 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
387
388static const struct snd_soc_dai_ops max98373_dai_ops = {
389 .set_fmt = max98373_dai_set_fmt,
390 .hw_params = max98373_dai_hw_params,
391 .set_tdm_slot = max98373_dai_tdm_slot,
392};
393
394static int max98373_dac_event(struct snd_soc_dapm_widget *w,
395 struct snd_kcontrol *kcontrol, int event)
396{
397 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
398 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
399
400 switch (event) {
401 case SND_SOC_DAPM_POST_PMU:
402 regmap_update_bits(max98373->regmap,
403 MAX98373_R20FF_GLOBAL_SHDN,
404 MAX98373_GLOBAL_EN_MASK, 1);
405 break;
406 case SND_SOC_DAPM_POST_PMD:
407 regmap_update_bits(max98373->regmap,
408 MAX98373_R20FF_GLOBAL_SHDN,
409 MAX98373_GLOBAL_EN_MASK, 0);
410 max98373->tdm_mode = 0;
411 break;
412 default:
413 return 0;
414 }
415 return 0;
416}
417
418static const char * const max98373_switch_text[] = {
419 "Left", "Right", "LeftRight"};
420
421static const struct soc_enum dai_sel_enum =
422 SOC_ENUM_SINGLE(MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
423 MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
424 3, max98373_switch_text);
425
426static const struct snd_kcontrol_new max98373_dai_controls =
427 SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
428
429static const struct snd_kcontrol_new max98373_vi_control =
430 SOC_DAPM_SINGLE("Switch", MAX98373_R202C_PCM_TX_EN, 0, 1, 0);
431
432static const struct snd_kcontrol_new max98373_spkfb_control =
433 SOC_DAPM_SINGLE("Switch", MAX98373_R2043_AMP_EN, 1, 1, 0);
434
435static const struct snd_soc_dapm_widget max98373_dapm_widgets[] = {
436SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
437 MAX98373_R202B_PCM_RX_EN, 0, 0, max98373_dac_event,
438 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
439SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
440 &max98373_dai_controls),
441SND_SOC_DAPM_OUTPUT("BE_OUT"),
442SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
443 MAX98373_R2047_IV_SENSE_ADC_EN, 0, 0),
444SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
445 MAX98373_R2047_IV_SENSE_ADC_EN, 1, 0),
446SND_SOC_DAPM_AIF_OUT("Speaker FB Sense", "HiFi Capture", 0,
447 SND_SOC_NOPM, 0, 0),
448SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
449 &max98373_vi_control),
450SND_SOC_DAPM_SWITCH("SpkFB Sense", SND_SOC_NOPM, 0, 0,
451 &max98373_spkfb_control),
452SND_SOC_DAPM_SIGGEN("VMON"),
453SND_SOC_DAPM_SIGGEN("IMON"),
454SND_SOC_DAPM_SIGGEN("FBMON"),
455};
456
457static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, 0, -50, 0);
458static const DECLARE_TLV_DB_RANGE(max98373_spk_tlv,
459 0, 8, TLV_DB_SCALE_ITEM(0, 50, 0),
460 9, 10, TLV_DB_SCALE_ITEM(500, 100, 0),
461);
462static const DECLARE_TLV_DB_RANGE(max98373_spkgain_max_tlv,
463 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
464);
465static const DECLARE_TLV_DB_RANGE(max98373_dht_step_size_tlv,
466 0, 1, TLV_DB_SCALE_ITEM(25, 25, 0),
467 2, 4, TLV_DB_SCALE_ITEM(100, 100, 0),
468);
469static const DECLARE_TLV_DB_RANGE(max98373_dht_spkgain_min_tlv,
470 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
471);
472static const DECLARE_TLV_DB_RANGE(max98373_dht_rotation_point_tlv,
473 0, 1, TLV_DB_SCALE_ITEM(-50, -50, 0),
474 2, 7, TLV_DB_SCALE_ITEM(-200, -100, 0),
475 8, 9, TLV_DB_SCALE_ITEM(-1000, -200, 0),
476 10, 11, TLV_DB_SCALE_ITEM(-1500, -300, 0),
477 12, 13, TLV_DB_SCALE_ITEM(-2000, -200, 0),
478 14, 15, TLV_DB_SCALE_ITEM(-2500, -500, 0),
479);
480static const DECLARE_TLV_DB_RANGE(max98373_limiter_thresh_tlv,
481 0, 15, TLV_DB_SCALE_ITEM(0, -100, 0),
482);
483
484static const DECLARE_TLV_DB_RANGE(max98373_bde_gain_tlv,
485 0, 60, TLV_DB_SCALE_ITEM(0, -25, 0),
486);
487
488static bool max98373_readable_register(struct device *dev, unsigned int reg)
489{
490 switch (reg) {
491 case MAX98373_R2001_INT_RAW1 ... MAX98373_R200C_INT_EN3:
492 case MAX98373_R2010_IRQ_CTRL:
493 case MAX98373_R2014_THERM_WARN_THRESH
494 ... MAX98373_R2018_THERM_FOLDBACK_EN:
495 case MAX98373_R201E_PIN_DRIVE_STRENGTH
496 ... MAX98373_R2036_SOUNDWIRE_CTRL:
497 case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN:
498 case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG
499 ... MAX98373_R2047_IV_SENSE_ADC_EN:
500 case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE
501 ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN:
502 case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE:
503 case MAX98373_R2097_BDE_L1_THRESH
504 ... MAX98373_R209B_BDE_THRESH_HYST:
505 case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3:
506 case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK:
507 case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN:
508 case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN:
509 case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG
510 ... MAX98373_R20FF_GLOBAL_SHDN:
511 case MAX98373_R21FF_REV_ID:
512 return true;
513 default:
514 return false;
515 }
516};
517
518static bool max98373_volatile_reg(struct device *dev, unsigned int reg)
519{
520 switch (reg) {
521 case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3:
522 case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK:
523 case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK:
524 case MAX98373_R20B6_BDE_CUR_STATE_READBACK:
525 case MAX98373_R21FF_REV_ID:
526 return true;
527 default:
528 return false;
529 }
530}
531
532static const char * const max98373_output_voltage_lvl_text[] = {
533 "5.43V", "6.09V", "6.83V", "7.67V", "8.60V",
534 "9.65V", "10.83V", "12.15V", "13.63V", "15.29V"
535};
536
537static SOC_ENUM_SINGLE_DECL(max98373_out_volt_enum,
538 MAX98373_R203E_AMP_PATH_GAIN, 0,
539 max98373_output_voltage_lvl_text);
540
541static const char * const max98373_dht_attack_rate_text[] = {
542 "17.5us", "35us", "70us", "140us",
543 "280us", "560us", "1120us", "2240us"
544};
545
546static SOC_ENUM_SINGLE_DECL(max98373_dht_attack_rate_enum,
547 MAX98373_R20D2_DHT_ATTACK_CFG, 0,
548 max98373_dht_attack_rate_text);
549
550static const char * const max98373_dht_release_rate_text[] = {
551 "45ms", "225ms", "450ms", "1150ms",
552 "2250ms", "3100ms", "4500ms", "6750ms"
553};
554
555static SOC_ENUM_SINGLE_DECL(max98373_dht_release_rate_enum,
556 MAX98373_R20D3_DHT_RELEASE_CFG, 0,
557 max98373_dht_release_rate_text);
558
559static const char * const max98373_limiter_attack_rate_text[] = {
560 "10us", "20us", "40us", "80us",
561 "160us", "320us", "640us", "1.28ms",
562 "2.56ms", "5.12ms", "10.24ms", "20.48ms",
563 "40.96ms", "81.92ms", "16.384ms", "32.768ms"
564};
565
566static SOC_ENUM_SINGLE_DECL(max98373_limiter_attack_rate_enum,
567 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 4,
568 max98373_limiter_attack_rate_text);
569
570static const char * const max98373_limiter_release_rate_text[] = {
571 "40us", "80us", "160us", "320us",
572 "640us", "1.28ms", "2.56ms", "5.120ms",
573 "10.24ms", "20.48ms", "40.96ms", "81.92ms",
574 "163.84ms", "327.68ms", "655.36ms", "1310.72ms"
575};
576
577static SOC_ENUM_SINGLE_DECL(max98373_limiter_release_rate_enum,
578 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0,
579 max98373_limiter_release_rate_text);
580
581static const char * const max98373_ADC_samplerate_text[] = {
582 "333kHz", "192kHz", "64kHz", "48kHz"
583};
584
585static SOC_ENUM_SINGLE_DECL(max98373_adc_samplerate_enum,
586 MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0,
587 max98373_ADC_samplerate_text);
588
589static const struct snd_kcontrol_new max98373_snd_controls[] = {
590SOC_SINGLE("Digital Vol Sel Switch", MAX98373_R203F_AMP_DSP_CFG,
591 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
592SOC_SINGLE("Volume Location Switch", MAX98373_R203F_AMP_DSP_CFG,
593 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
594SOC_SINGLE("Ramp Up Switch", MAX98373_R203F_AMP_DSP_CFG,
595 MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0),
596SOC_SINGLE("Ramp Down Switch", MAX98373_R203F_AMP_DSP_CFG,
597 MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0),
598SOC_SINGLE("CLK Monitor Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
599 MAX98373_CLOCK_MON_SHIFT, 1, 0),
600SOC_SINGLE("Dither Switch", MAX98373_R203F_AMP_DSP_CFG,
601 MAX98373_AMP_DSP_CFG_DITH_SHIFT, 1, 0),
602SOC_SINGLE("DC Blocker Switch", MAX98373_R203F_AMP_DSP_CFG,
603 MAX98373_AMP_DSP_CFG_DCBLK_SHIFT, 1, 0),
604SOC_SINGLE_TLV("Digital Volume", MAX98373_R203D_AMP_DIG_VOL_CTRL,
605 0, 0x7F, 0, max98373_digital_tlv),
606SOC_SINGLE_TLV("Speaker Volume", MAX98373_R203E_AMP_PATH_GAIN,
607 MAX98373_SPK_DIGI_GAIN_SHIFT, 10, 0, max98373_spk_tlv),
608SOC_SINGLE_TLV("FS Max Volume", MAX98373_R203E_AMP_PATH_GAIN,
609 MAX98373_FS_GAIN_MAX_SHIFT, 9, 0, max98373_spkgain_max_tlv),
610SOC_ENUM("Output Voltage", max98373_out_volt_enum),
611/* Dynamic Headroom Tracking */
612SOC_SINGLE("DHT Switch", MAX98373_R20D4_DHT_EN,
613 MAX98373_DHT_EN_SHIFT, 1, 0),
614SOC_SINGLE_TLV("DHT Min Volume", MAX98373_R20D1_DHT_CFG,
615 MAX98373_DHT_SPK_GAIN_MIN_SHIFT, 9, 0, max98373_dht_spkgain_min_tlv),
616SOC_SINGLE_TLV("DHT Rot Pnt Volume", MAX98373_R20D1_DHT_CFG,
617 MAX98373_DHT_ROT_PNT_SHIFT, 15, 0, max98373_dht_rotation_point_tlv),
618SOC_SINGLE_TLV("DHT Attack Step Volume", MAX98373_R20D2_DHT_ATTACK_CFG,
619 MAX98373_DHT_ATTACK_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
620SOC_SINGLE_TLV("DHT Release Step Volume", MAX98373_R20D3_DHT_RELEASE_CFG,
621 MAX98373_DHT_RELEASE_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
622SOC_ENUM("DHT Attack Rate", max98373_dht_attack_rate_enum),
623SOC_ENUM("DHT Release Rate", max98373_dht_release_rate_enum),
624/* ADC configuration */
625SOC_SINGLE("ADC PVDD CH Switch", MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0, 1, 0),
626SOC_SINGLE("ADC PVDD FLT Switch", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
627 MAX98373_FLT_EN_SHIFT, 1, 0),
628SOC_SINGLE("ADC TEMP FLT Switch", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
629 MAX98373_FLT_EN_SHIFT, 1, 0),
630SOC_SINGLE("ADC PVDD", MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0, 0xFF, 0),
631SOC_SINGLE("ADC TEMP", MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0, 0xFF, 0),
632SOC_SINGLE("ADC PVDD FLT Coeff", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
633 0, 0x3, 0),
634SOC_SINGLE("ADC TEMP FLT Coeff", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
635 0, 0x3, 0),
636SOC_ENUM("ADC SampleRate", max98373_adc_samplerate_enum),
637/* Brownout Detection Engine */
638SOC_SINGLE("BDE Switch", MAX98373_R20B5_BDE_EN, MAX98373_BDE_EN_SHIFT, 1, 0),
639SOC_SINGLE("BDE LVL4 Mute Switch", MAX98373_R20B2_BDE_L4_CFG_2,
640 MAX98373_LVL4_MUTE_EN_SHIFT, 1, 0),
641SOC_SINGLE("BDE LVL4 Hold Switch", MAX98373_R20B2_BDE_L4_CFG_2,
642 MAX98373_LVL4_HOLD_EN_SHIFT, 1, 0),
643SOC_SINGLE("BDE LVL1 Thresh", MAX98373_R2097_BDE_L1_THRESH, 0, 0xFF, 0),
644SOC_SINGLE("BDE LVL2 Thresh", MAX98373_R2098_BDE_L2_THRESH, 0, 0xFF, 0),
645SOC_SINGLE("BDE LVL3 Thresh", MAX98373_R2099_BDE_L3_THRESH, 0, 0xFF, 0),
646SOC_SINGLE("BDE LVL4 Thresh", MAX98373_R209A_BDE_L4_THRESH, 0, 0xFF, 0),
647SOC_SINGLE("BDE Active Level", MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0, 8, 0),
648SOC_SINGLE("BDE Clip Mode Switch", MAX98373_R2092_BDE_CLIPPER_MODE, 0, 1, 0),
649SOC_SINGLE("BDE Thresh Hysteresis", MAX98373_R209B_BDE_THRESH_HYST, 0, 0xFF, 0),
650SOC_SINGLE("BDE Hold Time", MAX98373_R2090_BDE_LVL_HOLD, 0, 0xFF, 0),
651SOC_SINGLE("BDE Attack Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 4, 0xF, 0),
652SOC_SINGLE("BDE Release Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0, 0xF, 0),
653SOC_SINGLE_TLV("BDE LVL1 Clip Thresh Volume", MAX98373_R20A9_BDE_L1_CFG_2,
654 0, 0x3C, 0, max98373_bde_gain_tlv),
655SOC_SINGLE_TLV("BDE LVL2 Clip Thresh Volume", MAX98373_R20AC_BDE_L2_CFG_2,
656 0, 0x3C, 0, max98373_bde_gain_tlv),
657SOC_SINGLE_TLV("BDE LVL3 Clip Thresh Volume", MAX98373_R20AF_BDE_L3_CFG_2,
658 0, 0x3C, 0, max98373_bde_gain_tlv),
659SOC_SINGLE_TLV("BDE LVL4 Clip Thresh Volume", MAX98373_R20B2_BDE_L4_CFG_2,
660 0, 0x3C, 0, max98373_bde_gain_tlv),
661SOC_SINGLE_TLV("BDE LVL1 Clip Reduction Volume", MAX98373_R20AA_BDE_L1_CFG_3,
662 0, 0x3C, 0, max98373_bde_gain_tlv),
663SOC_SINGLE_TLV("BDE LVL2 Clip Reduction Volume", MAX98373_R20AD_BDE_L2_CFG_3,
664 0, 0x3C, 0, max98373_bde_gain_tlv),
665SOC_SINGLE_TLV("BDE LVL3 Clip Reduction Volume", MAX98373_R20B0_BDE_L3_CFG_3,
666 0, 0x3C, 0, max98373_bde_gain_tlv),
667SOC_SINGLE_TLV("BDE LVL4 Clip Reduction Volume", MAX98373_R20B3_BDE_L4_CFG_3,
668 0, 0x3C, 0, max98373_bde_gain_tlv),
669SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1,
670 0, 0xF, 0, max98373_limiter_thresh_tlv),
671SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh Volume", MAX98373_R20AB_BDE_L2_CFG_1,
672 0, 0xF, 0, max98373_limiter_thresh_tlv),
673SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh Volume", MAX98373_R20AE_BDE_L3_CFG_1,
674 0, 0xF, 0, max98373_limiter_thresh_tlv),
675SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh Volume", MAX98373_R20B1_BDE_L4_CFG_1,
676 0, 0xF, 0, max98373_limiter_thresh_tlv),
677/* Limiter */
678SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN,
679 MAX98373_LIMITER_EN_SHIFT, 1, 0),
680SOC_SINGLE("Limiter Src Switch", MAX98373_R20E0_LIMITER_THRESH_CFG,
681 MAX98373_LIMITER_THRESH_SRC_SHIFT, 1, 0),
682SOC_SINGLE_TLV("Limiter Thresh Volume", MAX98373_R20E0_LIMITER_THRESH_CFG,
683 MAX98373_LIMITER_THRESH_SHIFT, 15, 0, max98373_limiter_thresh_tlv),
684SOC_ENUM("Limiter Attack Rate", max98373_limiter_attack_rate_enum),
685SOC_ENUM("Limiter Release Rate", max98373_limiter_release_rate_enum),
686};
687
688static const struct snd_soc_dapm_route max98373_audio_map[] = {
689 /* Plabyack */
690 {"DAI Sel Mux", "Left", "Amp Enable"},
691 {"DAI Sel Mux", "Right", "Amp Enable"},
692 {"DAI Sel Mux", "LeftRight", "Amp Enable"},
693 {"BE_OUT", NULL, "DAI Sel Mux"},
694 /* Capture */
695 { "VI Sense", "Switch", "VMON" },
696 { "VI Sense", "Switch", "IMON" },
697 { "SpkFB Sense", "Switch", "FBMON" },
698 { "Voltage Sense", NULL, "VI Sense" },
699 { "Current Sense", NULL, "VI Sense" },
700 { "Speaker FB Sense", NULL, "SpkFB Sense" },
701};
702
703static struct snd_soc_dai_driver max98373_dai[] = {
704 {
705 .name = "max98373-aif1",
706 .playback = {
707 .stream_name = "HiFi Playback",
708 .channels_min = 1,
709 .channels_max = 2,
710 .rates = MAX98373_RATES,
711 .formats = MAX98373_FORMATS,
712 },
713 .capture = {
714 .stream_name = "HiFi Capture",
715 .channels_min = 1,
716 .channels_max = 2,
717 .rates = MAX98373_RATES,
718 .formats = MAX98373_FORMATS,
719 },
720 .ops = &max98373_dai_ops,
721 }
722};
723
724static int max98373_probe(struct snd_soc_component *component)
725{
726 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component);
727
728 /* Software Reset */
729 regmap_write(max98373->regmap,
730 MAX98373_R2000_SW_RESET, MAX98373_SOFT_RESET);
731
732 /* IV default slot configuration */
733 regmap_write(max98373->regmap,
734 MAX98373_R2020_PCM_TX_HIZ_EN_1,
735 0xFF);
736 regmap_write(max98373->regmap,
737 MAX98373_R2021_PCM_TX_HIZ_EN_2,
738 0xFF);
739 /* L/R mix configuration */
740 regmap_write(max98373->regmap,
741 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
742 0x80);
743 regmap_write(max98373->regmap,
744 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
745 0x1);
746 /* Set inital volume (0dB) */
747 regmap_write(max98373->regmap,
748 MAX98373_R203D_AMP_DIG_VOL_CTRL,
749 0x00);
750 regmap_write(max98373->regmap,
751 MAX98373_R203E_AMP_PATH_GAIN,
752 0x00);
753 /* Enable DC blocker */
754 regmap_write(max98373->regmap,
755 MAX98373_R203F_AMP_DSP_CFG,
756 0x3);
757 /* Enable IMON VMON DC blocker */
758 regmap_write(max98373->regmap,
759 MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
760 0x7);
761 /* voltage, current slot configuration */
762 regmap_write(max98373->regmap,
763 MAX98373_R2022_PCM_TX_SRC_1,
764 (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
765 max98373->v_slot) & 0xFF);
766 if (max98373->v_slot < 8)
767 regmap_update_bits(max98373->regmap,
768 MAX98373_R2020_PCM_TX_HIZ_EN_1,
769 1 << max98373->v_slot, 0);
770 else
771 regmap_update_bits(max98373->regmap,
772 MAX98373_R2021_PCM_TX_HIZ_EN_2,
773 1 << (max98373->v_slot - 8), 0);
774
775 if (max98373->i_slot < 8)
776 regmap_update_bits(max98373->regmap,
777 MAX98373_R2020_PCM_TX_HIZ_EN_1,
778 1 << max98373->i_slot, 0);
779 else
780 regmap_update_bits(max98373->regmap,
781 MAX98373_R2021_PCM_TX_HIZ_EN_2,
782 1 << (max98373->i_slot - 8), 0);
783
784 /* speaker feedback slot configuration */
785 regmap_write(max98373->regmap,
786 MAX98373_R2023_PCM_TX_SRC_2,
787 max98373->spkfb_slot & 0xFF);
788
789 /* Set interleave mode */
790 if (max98373->interleave_mode)
791 regmap_update_bits(max98373->regmap,
792 MAX98373_R2024_PCM_DATA_FMT_CFG,
793 MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
794 MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
795
796 /* Speaker enable */
797 regmap_update_bits(max98373->regmap,
798 MAX98373_R2043_AMP_EN,
799 MAX98373_SPK_EN_MASK, 1);
800
801 return 0;
802}
803
804#ifdef CONFIG_PM_SLEEP
805static int max98373_suspend(struct device *dev)
806{
807 struct max98373_priv *max98373 = dev_get_drvdata(dev);
808
809 regcache_cache_only(max98373->regmap, true);
810 regcache_mark_dirty(max98373->regmap);
811 return 0;
812}
813static int max98373_resume(struct device *dev)
814{
815 struct max98373_priv *max98373 = dev_get_drvdata(dev);
816
817 regmap_write(max98373->regmap,
818 MAX98373_R2000_SW_RESET, MAX98373_SOFT_RESET);
819 regcache_cache_only(max98373->regmap, false);
820 regcache_sync(max98373->regmap);
821 return 0;
822}
823#endif
824
825static const struct dev_pm_ops max98373_pm = {
826 SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume)
827};
828
829static const struct snd_soc_component_driver soc_codec_dev_max98373 = {
830 .probe = max98373_probe,
831 .controls = max98373_snd_controls,
832 .num_controls = ARRAY_SIZE(max98373_snd_controls),
833 .dapm_widgets = max98373_dapm_widgets,
834 .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets),
835 .dapm_routes = max98373_audio_map,
836 .num_dapm_routes = ARRAY_SIZE(max98373_audio_map),
837 .idle_bias_on = 1,
838 .use_pmdown_time = 1,
839 .endianness = 1,
840 .non_legacy_dai_naming = 1,
841};
842
843static const struct regmap_config max98373_regmap = {
844 .reg_bits = 16,
845 .val_bits = 8,
846 .max_register = MAX98373_R21FF_REV_ID,
847 .reg_defaults = max98373_reg,
848 .num_reg_defaults = ARRAY_SIZE(max98373_reg),
849 .readable_reg = max98373_readable_register,
850 .volatile_reg = max98373_volatile_reg,
851 .cache_type = REGCACHE_RBTREE,
852};
853
854static void max98373_slot_config(struct i2c_client *i2c,
855 struct max98373_priv *max98373)
856{
857 int value;
858 struct device *dev = &i2c->dev;
859
860 if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value))
861 max98373->v_slot = value & 0xF;
862 else
863 max98373->v_slot = 0;
864
865 if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value))
866 max98373->i_slot = value & 0xF;
867 else
868 max98373->i_slot = 1;
869
870 if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value))
871 max98373->spkfb_slot = value & 0xF;
872 else
873 max98373->spkfb_slot = 2;
874}
875
876static int max98373_i2c_probe(struct i2c_client *i2c,
877 const struct i2c_device_id *id)
878{
879
880 int ret = 0;
881 int reg = 0;
882 struct max98373_priv *max98373 = NULL;
883
884 max98373 = devm_kzalloc(&i2c->dev, sizeof(*max98373), GFP_KERNEL);
885
886 if (!max98373) {
887 ret = -ENOMEM;
888 return ret;
889 }
890 i2c_set_clientdata(i2c, max98373);
891
892 /* update interleave mode info */
893 if (device_property_read_bool(&i2c->dev, "maxim,interleave_mode"))
894 max98373->interleave_mode = 1;
895 else
896 max98373->interleave_mode = 0;
897
898
899 /* regmap initialization */
900 max98373->regmap
901 = devm_regmap_init_i2c(i2c, &max98373_regmap);
902 if (IS_ERR(max98373->regmap)) {
903 ret = PTR_ERR(max98373->regmap);
904 dev_err(&i2c->dev,
905 "Failed to allocate regmap: %d\n", ret);
906 return ret;
907 }
908
909 /* Check Revision ID */
910 ret = regmap_read(max98373->regmap,
911 MAX98373_R21FF_REV_ID, ®);
912 if (ret < 0) {
913 dev_err(&i2c->dev,
914 "Failed to read: 0x%02X\n", MAX98373_R21FF_REV_ID);
915 return ret;
916 }
917 dev_info(&i2c->dev, "MAX98373 revisionID: 0x%02X\n", reg);
918
919 /* voltage/current slot configuration */
920 max98373_slot_config(i2c, max98373);
921
922 /* codec registeration */
923 ret = devm_snd_soc_register_component(&i2c->dev, &soc_codec_dev_max98373,
924 max98373_dai, ARRAY_SIZE(max98373_dai));
925 if (ret < 0)
926 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
927
928 return ret;
929}
930
931static const struct i2c_device_id max98373_i2c_id[] = {
932 { "max98373", 0},
933 { },
934};
935
936MODULE_DEVICE_TABLE(i2c, max98373_i2c_id);
937
938#if defined(CONFIG_OF)
939static const struct of_device_id max98373_of_match[] = {
940 { .compatible = "maxim,max98373", },
941 { }
942};
943MODULE_DEVICE_TABLE(of, max98373_of_match);
944#endif
945
946#ifdef CONFIG_ACPI
947static const struct acpi_device_id max98373_acpi_match[] = {
948 { "MX98373", 0 },
949 {},
950};
951MODULE_DEVICE_TABLE(acpi, max98373_acpi_match);
952#endif
953
954static struct i2c_driver max98373_i2c_driver = {
955 .driver = {
956 .name = "max98373",
957 .of_match_table = of_match_ptr(max98373_of_match),
958 .acpi_match_table = ACPI_PTR(max98373_acpi_match),
959 .pm = &max98373_pm,
960 },
961 .probe = max98373_i2c_probe,
962 .id_table = max98373_i2c_id,
963};
964
965module_i2c_driver(max98373_i2c_driver)
966
967MODULE_DESCRIPTION("ALSA SoC MAX98373 driver");
968MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
969MODULE_LICENSE("GPL");