1// SPDX-License-Identifier: GPL-2.0
  2
  3#include <linux/cpuhotplug.h>
  4#include <linux/cpumask.h>
  5#include <linux/slab.h>
  6#include <linux/mm.h>
  7
  8#include <asm/apic.h>
  9
 10#include "local.h"
 11
 12#define apic_cluster(apicid) ((apicid) >> 4)
 
 
 
 
 13
 14/*
 15 * __x2apic_send_IPI_mask() possibly needs to read
 16 * x86_cpu_to_logical_apicid for all online cpus in a sequential way.
 17 * Using per cpu variable would cost one cache line per cpu.
 18 */
 19static u32 *x86_cpu_to_logical_apicid __read_mostly;
 20
 21static DEFINE_PER_CPU(cpumask_var_t, ipi_mask);
 22static DEFINE_PER_CPU_READ_MOSTLY(struct cpumask *, cluster_masks);
 
 23
 24static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 25{
 26	return x2apic_enabled();
 27}
 28
 29static void x2apic_send_IPI(int cpu, int vector)
 30{
 31	u32 dest = x86_cpu_to_logical_apicid[cpu];
 32
 33	/* x2apic MSRs are special and need a special fence: */
 34	weak_wrmsr_fence();
 35	__x2apic_send_IPI_dest(dest, vector, APIC_DEST_LOGICAL);
 36}
 37
 38static void
 39__x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest)
 40{
 41	unsigned int cpu, clustercpu;
 42	struct cpumask *tmpmsk;
 43	unsigned long flags;
 44	u32 dest;
 45
 46	/* x2apic MSRs are special and need a special fence: */
 47	weak_wrmsr_fence();
 48	local_irq_save(flags);
 49
 50	tmpmsk = this_cpu_cpumask_var_ptr(ipi_mask);
 51	cpumask_copy(tmpmsk, mask);
 52	/* If IPI should not be sent to self, clear current CPU */
 53	if (apic_dest != APIC_DEST_ALLINC)
 54		__cpumask_clear_cpu(smp_processor_id(), tmpmsk);
 55
 56	/* Collapse cpus in a cluster so a single IPI per cluster is sent */
 57	for_each_cpu(cpu, tmpmsk) {
 58		struct cpumask *cmsk = per_cpu(cluster_masks, cpu);
 59
 60		dest = 0;
 61		for_each_cpu_and(clustercpu, tmpmsk, cmsk)
 62			dest |= x86_cpu_to_logical_apicid[clustercpu];
 63
 64		if (!dest)
 65			continue;
 66
 67		__x2apic_send_IPI_dest(dest, vector, APIC_DEST_LOGICAL);
 68		/* Remove cluster CPUs from tmpmask */
 69		cpumask_andnot(tmpmsk, tmpmsk, cmsk);
 70	}
 71
 72	local_irq_restore(flags);
 73}
 74
 75static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
 76{
 77	__x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC);
 78}
 79
 80static void
 81x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 82{
 83	__x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT);
 84}
 85
 86static u32 x2apic_calc_apicid(unsigned int cpu)
 87{
 88	return x86_cpu_to_logical_apicid[cpu];
 89}
 90
 91static void init_x2apic_ldr(void)
 92{
 93	struct cpumask *cmsk = this_cpu_read(cluster_masks);
 94
 95	BUG_ON(!cmsk);
 96
 97	cpumask_set_cpu(smp_processor_id(), cmsk);
 98}
 99
100/*
101 * As an optimisation during boot, set the cluster_mask for all present
102 * CPUs at once, to prevent each of them having to iterate over the others
103 * to find the existing cluster_mask.
104 */
105static void prefill_clustermask(struct cpumask *cmsk, unsigned int cpu, u32 cluster)
106{
107	int cpu_i;
 
108
109	for_each_present_cpu(cpu_i) {
110		struct cpumask **cpu_cmsk = &per_cpu(cluster_masks, cpu_i);
111		u32 apicid = apic->cpu_present_to_apicid(cpu_i);
 
 
112
113		if (apicid == BAD_APICID || cpu_i == cpu || apic_cluster(apicid) != cluster)
114			continue;
115
116		if (WARN_ON_ONCE(*cpu_cmsk == cmsk))
117			continue;
118
119		BUG_ON(*cpu_cmsk);
120		*cpu_cmsk = cmsk;
 
 
 
 
121	}
 
 
 
 
 
 
122}
123
124static int alloc_clustermask(unsigned int cpu, u32 cluster, int node)
125{
126	struct cpumask *cmsk = NULL;
127	unsigned int cpu_i;
128
129	/*
130	 * At boot time, the CPU present mask is stable. The cluster mask is
131	 * allocated for the first CPU in the cluster and propagated to all
132	 * present siblings in the cluster. If the cluster mask is already set
133	 * on entry to this function for a given CPU, there is nothing to do.
134	 */
135	if (per_cpu(cluster_masks, cpu))
136		return 0;
137
138	if (system_state < SYSTEM_RUNNING)
139		goto alloc;
140
141	/*
142	 * On post boot hotplug for a CPU which was not present at boot time,
143	 * iterate over all possible CPUs (even those which are not present
144	 * any more) to find any existing cluster mask.
145	 */
146	for_each_possible_cpu(cpu_i) {
147		u32 apicid = apic->cpu_present_to_apicid(cpu_i);
148
149		if (apicid != BAD_APICID && apic_cluster(apicid) == cluster) {
150			cmsk = per_cpu(cluster_masks, cpu_i);
151			/*
152			 * If the cluster is already initialized, just store
153			 * the mask and return. There's no need to propagate.
154			 */
155			if (cmsk) {
156				per_cpu(cluster_masks, cpu) = cmsk;
157				return 0;
158			}
159		}
160	}
161	/*
162	 * No CPU in the cluster has ever been initialized, so fall through to
163	 * the boot time code which will also populate the cluster mask for any
164	 * other CPU in the cluster which is (now) present.
165	 */
166alloc:
167	cmsk = kzalloc_node(sizeof(*cmsk), GFP_KERNEL, node);
168	if (!cmsk)
169		return -ENOMEM;
170	per_cpu(cluster_masks, cpu) = cmsk;
171	prefill_clustermask(cmsk, cpu, cluster);
172
 
 
 
 
 
173	return 0;
174}
175
176static int x2apic_prepare_cpu(unsigned int cpu)
177{
178	u32 phys_apicid = apic->cpu_present_to_apicid(cpu);
179	u32 cluster = apic_cluster(phys_apicid);
180	u32 logical_apicid = (cluster << 16) | (1 << (phys_apicid & 0xf));
181	int node = cpu_to_node(cpu);
182
183	x86_cpu_to_logical_apicid[cpu] = logical_apicid;
184
185	if (alloc_clustermask(cpu, cluster, node) < 0)
186		return -ENOMEM;
187
188	if (!zalloc_cpumask_var_node(&per_cpu(ipi_mask, cpu), GFP_KERNEL, node))
189		return -ENOMEM;
190
191	return 0;
192}
193
194static int x2apic_dead_cpu(unsigned int dead_cpu)
195{
196	struct cpumask *cmsk = per_cpu(cluster_masks, dead_cpu);
197
198	if (cmsk)
199		cpumask_clear_cpu(dead_cpu, cmsk);
200	free_cpumask_var(per_cpu(ipi_mask, dead_cpu));
201	return 0;
202}
203
204static int x2apic_cluster_probe(void)
205{
206	u32 slots;
207
208	if (!x2apic_mode)
209		return 0;
210
211	slots = max_t(u32, L1_CACHE_BYTES/sizeof(u32), nr_cpu_ids);
212	x86_cpu_to_logical_apicid = kcalloc(slots, sizeof(u32), GFP_KERNEL);
213	if (!x86_cpu_to_logical_apicid)
214		return 0;
215
216	if (cpuhp_setup_state(CPUHP_X2APIC_PREPARE, "x86/x2apic:prepare",
217			      x2apic_prepare_cpu, x2apic_dead_cpu) < 0) {
218		pr_err("Failed to register X2APIC_PREPARE\n");
219		kfree(x86_cpu_to_logical_apicid);
220		x86_cpu_to_logical_apicid = NULL;
221		return 0;
222	}
223	init_x2apic_ldr();
224	return 1;
225}
226
227static struct apic apic_x2apic_cluster __ro_after_init = {
228
229	.name				= "cluster x2apic",
230	.probe				= x2apic_cluster_probe,
231	.acpi_madt_oem_check		= x2apic_acpi_madt_oem_check,
 
 
232
 
233	.dest_mode_logical		= true,
234
235	.disable_esr			= 0,
236
 
237	.init_apic_ldr			= init_x2apic_ldr,
 
 
238	.cpu_present_to_apicid		= default_cpu_present_to_apicid,
 
 
 
239
240	.max_apic_id			= UINT_MAX,
241	.x2apic_set_max_apicid		= true,
242	.get_apic_id			= x2apic_get_apic_id,
 
243
244	.calc_dest_apicid		= x2apic_calc_apicid,
245
246	.send_IPI			= x2apic_send_IPI,
247	.send_IPI_mask			= x2apic_send_IPI_mask,
248	.send_IPI_mask_allbutself	= x2apic_send_IPI_mask_allbutself,
249	.send_IPI_allbutself		= x2apic_send_IPI_allbutself,
250	.send_IPI_all			= x2apic_send_IPI_all,
251	.send_IPI_self			= x2apic_send_IPI_self,
252	.nmi_to_offline_cpu		= true,
 
253
254	.read				= native_apic_msr_read,
255	.write				= native_apic_msr_write,
256	.eoi				= native_apic_msr_eoi,
257	.icr_read			= native_x2apic_icr_read,
258	.icr_write			= native_x2apic_icr_write,
 
 
259};
260
261apic_driver(apic_x2apic_cluster);

  1// SPDX-License-Identifier: GPL-2.0
  2
  3#include <linux/cpuhotplug.h>
  4#include <linux/cpumask.h>
  5#include <linux/slab.h>
  6#include <linux/mm.h>
  7
  8#include <asm/apic.h>
  9
 10#include "local.h"
 11
 12struct cluster_mask {
 13	unsigned int	clusterid;
 14	int		node;
 15	struct cpumask	mask;
 16};
 17
 18/*
 19 * __x2apic_send_IPI_mask() possibly needs to read
 20 * x86_cpu_to_logical_apicid for all online cpus in a sequential way.
 21 * Using per cpu variable would cost one cache line per cpu.
 22 */
 23static u32 *x86_cpu_to_logical_apicid __read_mostly;
 24
 25static DEFINE_PER_CPU(cpumask_var_t, ipi_mask);
 26static DEFINE_PER_CPU_READ_MOSTLY(struct cluster_mask *, cluster_masks);
 27static struct cluster_mask *cluster_hotplug_mask;
 28
 29static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 30{
 31	return x2apic_enabled();
 32}
 33
 34static void x2apic_send_IPI(int cpu, int vector)
 35{
 36	u32 dest = x86_cpu_to_logical_apicid[cpu];
 37
 38	/* x2apic MSRs are special and need a special fence: */
 39	weak_wrmsr_fence();
 40	__x2apic_send_IPI_dest(dest, vector, APIC_DEST_LOGICAL);
 41}
 42
 43static void
 44__x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest)
 45{
 46	unsigned int cpu, clustercpu;
 47	struct cpumask *tmpmsk;
 48	unsigned long flags;
 49	u32 dest;
 50
 51	/* x2apic MSRs are special and need a special fence: */
 52	weak_wrmsr_fence();
 53	local_irq_save(flags);
 54
 55	tmpmsk = this_cpu_cpumask_var_ptr(ipi_mask);
 56	cpumask_copy(tmpmsk, mask);
 57	/* If IPI should not be sent to self, clear current CPU */
 58	if (apic_dest != APIC_DEST_ALLINC)
 59		__cpumask_clear_cpu(smp_processor_id(), tmpmsk);
 60
 61	/* Collapse cpus in a cluster so a single IPI per cluster is sent */
 62	for_each_cpu(cpu, tmpmsk) {
 63		struct cluster_mask *cmsk = per_cpu(cluster_masks, cpu);
 64
 65		dest = 0;
 66		for_each_cpu_and(clustercpu, tmpmsk, &cmsk->mask)
 67			dest |= x86_cpu_to_logical_apicid[clustercpu];
 68
 69		if (!dest)
 70			continue;
 71
 72		__x2apic_send_IPI_dest(dest, vector, APIC_DEST_LOGICAL);
 73		/* Remove cluster CPUs from tmpmask */
 74		cpumask_andnot(tmpmsk, tmpmsk, &cmsk->mask);
 75	}
 76
 77	local_irq_restore(flags);
 78}
 79
 80static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
 81{
 82	__x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC);
 83}
 84
 85static void
 86x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 87{
 88	__x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT);
 89}
 90
 91static void x2apic_send_IPI_allbutself(int vector)
 92{
 93	__x2apic_send_IPI_shorthand(vector, APIC_DEST_ALLBUT);
 94}
 95
 96static void x2apic_send_IPI_all(int vector)
 97{
 98	__x2apic_send_IPI_shorthand(vector, APIC_DEST_ALLINC);
 
 
 
 
 99}
100
101static u32 x2apic_calc_apicid(unsigned int cpu)
 
 
 
 
 
102{
103	return x86_cpu_to_logical_apicid[cpu];
104}
105
106static void init_x2apic_ldr(void)
107{
108	struct cluster_mask *cmsk = this_cpu_read(cluster_masks);
109	u32 cluster, apicid = apic_read(APIC_LDR);
110	unsigned int cpu;
111
112	x86_cpu_to_logical_apicid[smp_processor_id()] = apicid;
 
113
114	if (cmsk)
115		goto update;
116
117	cluster = apicid >> 16;
118	for_each_online_cpu(cpu) {
119		cmsk = per_cpu(cluster_masks, cpu);
120		/* Matching cluster found. Link and update it. */
121		if (cmsk && cmsk->clusterid == cluster)
122			goto update;
123	}
124	cmsk = cluster_hotplug_mask;
125	cmsk->clusterid = cluster;
126	cluster_hotplug_mask = NULL;
127update:
128	this_cpu_write(cluster_masks, cmsk);
129	cpumask_set_cpu(smp_processor_id(), &cmsk->mask);
130}
131
132static int alloc_clustermask(unsigned int cpu, int node)
133{
 
 
 
 
 
 
 
 
 
134	if (per_cpu(cluster_masks, cpu))
135		return 0;
 
 
 
 
136	/*
137	 * If a hotplug spare mask exists, check whether it's on the right
138	 * node. If not, free it and allocate a new one.
 
139	 */
140	if (cluster_hotplug_mask) {
141		if (cluster_hotplug_mask->node == node)
142			return 0;
143		kfree(cluster_hotplug_mask);
 
 
 
 
 
 
 
 
 
 
144	}
 
 
 
 
 
 
 
 
 
 
 
145
146	cluster_hotplug_mask = kzalloc_node(sizeof(*cluster_hotplug_mask),
147					    GFP_KERNEL, node);
148	if (!cluster_hotplug_mask)
149		return -ENOMEM;
150	cluster_hotplug_mask->node = node;
151	return 0;
152}
153
154static int x2apic_prepare_cpu(unsigned int cpu)
155{
156	if (alloc_clustermask(cpu, cpu_to_node(cpu)) < 0)
 
 
 
 
 
 
 
157		return -ENOMEM;
158	if (!zalloc_cpumask_var(&per_cpu(ipi_mask, cpu), GFP_KERNEL))
 
159		return -ENOMEM;
 
160	return 0;
161}
162
163static int x2apic_dead_cpu(unsigned int dead_cpu)
164{
165	struct cluster_mask *cmsk = per_cpu(cluster_masks, dead_cpu);
166
167	if (cmsk)
168		cpumask_clear_cpu(dead_cpu, &cmsk->mask);
169	free_cpumask_var(per_cpu(ipi_mask, dead_cpu));
170	return 0;
171}
172
173static int x2apic_cluster_probe(void)
174{
175	u32 slots;
176
177	if (!x2apic_mode)
178		return 0;
179
180	slots = max_t(u32, L1_CACHE_BYTES/sizeof(u32), nr_cpu_ids);
181	x86_cpu_to_logical_apicid = kcalloc(slots, sizeof(u32), GFP_KERNEL);
182	if (!x86_cpu_to_logical_apicid)
183		return 0;
184
185	if (cpuhp_setup_state(CPUHP_X2APIC_PREPARE, "x86/x2apic:prepare",
186			      x2apic_prepare_cpu, x2apic_dead_cpu) < 0) {
187		pr_err("Failed to register X2APIC_PREPARE\n");
188		kfree(x86_cpu_to_logical_apicid);
189		x86_cpu_to_logical_apicid = NULL;
190		return 0;
191	}
192	init_x2apic_ldr();
193	return 1;
194}
195
196static struct apic apic_x2apic_cluster __ro_after_init = {
197
198	.name				= "cluster x2apic",
199	.probe				= x2apic_cluster_probe,
200	.acpi_madt_oem_check		= x2apic_acpi_madt_oem_check,
201	.apic_id_valid			= x2apic_apic_id_valid,
202	.apic_id_registered		= x2apic_apic_id_registered,
203
204	.delivery_mode			= APIC_DELIVERY_MODE_FIXED,
205	.dest_mode_logical		= true,
206
207	.disable_esr			= 0,
208
209	.check_apicid_used		= NULL,
210	.init_apic_ldr			= init_x2apic_ldr,
211	.ioapic_phys_id_map		= NULL,
212	.setup_apic_routing		= NULL,
213	.cpu_present_to_apicid		= default_cpu_present_to_apicid,
214	.apicid_to_cpu_present		= NULL,
215	.check_phys_apicid_present	= default_check_phys_apicid_present,
216	.phys_pkg_id			= x2apic_phys_pkg_id,
217
 
 
218	.get_apic_id			= x2apic_get_apic_id,
219	.set_apic_id			= x2apic_set_apic_id,
220
221	.calc_dest_apicid		= x2apic_calc_apicid,
222
223	.send_IPI			= x2apic_send_IPI,
224	.send_IPI_mask			= x2apic_send_IPI_mask,
225	.send_IPI_mask_allbutself	= x2apic_send_IPI_mask_allbutself,
226	.send_IPI_allbutself		= x2apic_send_IPI_allbutself,
227	.send_IPI_all			= x2apic_send_IPI_all,
228	.send_IPI_self			= x2apic_send_IPI_self,
229
230	.inquire_remote_apic		= NULL,
231
232	.read				= native_apic_msr_read,
233	.write				= native_apic_msr_write,
234	.eoi_write			= native_apic_msr_eoi_write,
235	.icr_read			= native_x2apic_icr_read,
236	.icr_write			= native_x2apic_icr_write,
237	.wait_icr_idle			= native_x2apic_wait_icr_idle,
238	.safe_wait_icr_idle		= native_safe_x2apic_wait_icr_idle,
239};
240
241apic_driver(apic_x2apic_cluster);