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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 */
5
6#ifndef AM65_CPSW_NUSS_H_
7#define AM65_CPSW_NUSS_H_
8
9#include <linux/if_ether.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/netdevice.h>
13#include <linux/phylink.h>
14#include <linux/platform_device.h>
15#include <linux/soc/ti/k3-ringacc.h>
16#include <net/devlink.h>
17#include <net/xdp.h>
18#include "am65-cpsw-qos.h"
19
20struct am65_cpts;
21
22#define HOST_PORT_NUM 0
23
24#define AM65_CPSW_MAX_QUEUES 8 /* both TX & RX */
25
26#define AM65_CPSW_PORT_VLAN_REG_OFFSET 0x014
27
28struct am65_cpsw_slave_data {
29 bool mac_only;
30 struct cpsw_sl *mac_sl;
31 struct device_node *port_np;
32 phy_interface_t phy_if;
33 struct phy *ifphy;
34 struct phy *serdes_phy;
35 bool rx_pause;
36 bool tx_pause;
37 u8 mac_addr[ETH_ALEN];
38 int port_vlan;
39 struct phylink *phylink;
40 struct phylink_config phylink_config;
41};
42
43struct am65_cpsw_port {
44 struct am65_cpsw_common *common;
45 struct net_device *ndev;
46 const char *name;
47 u32 port_id;
48 void __iomem *port_base;
49 void __iomem *sgmii_base;
50 void __iomem *stat_base;
51 void __iomem *fetch_ram_base;
52 bool disabled;
53 struct am65_cpsw_slave_data slave;
54 bool tx_ts_enabled;
55 bool rx_ts_enabled;
56 struct am65_cpsw_qos qos;
57 struct devlink_port devlink_port;
58 struct bpf_prog *xdp_prog;
59 struct xdp_rxq_info xdp_rxq[AM65_CPSW_MAX_QUEUES];
60 /* Only for suspend resume context */
61 u32 vid_context;
62};
63
64enum am65_cpsw_tx_buf_type {
65 AM65_CPSW_TX_BUF_TYPE_SKB,
66 AM65_CPSW_TX_BUF_TYPE_XDP_TX,
67 AM65_CPSW_TX_BUF_TYPE_XDP_NDO,
68};
69
70struct am65_cpsw_host {
71 struct am65_cpsw_common *common;
72 void __iomem *port_base;
73 void __iomem *stat_base;
74 /* Only for suspend resume context */
75 u32 vid_context;
76};
77
78struct am65_cpsw_tx_chn {
79 struct device *dma_dev;
80 struct napi_struct napi_tx;
81 struct am65_cpsw_common *common;
82 struct k3_cppi_desc_pool *desc_pool;
83 struct k3_udma_glue_tx_channel *tx_chn;
84 spinlock_t lock; /* protect TX rings in multi-port mode */
85 struct hrtimer tx_hrtimer;
86 unsigned long tx_pace_timeout;
87 int irq;
88 u32 id;
89 u32 descs_num;
90 unsigned char dsize_log2;
91 char tx_chn_name[128];
92 u32 rate_mbps;
93};
94
95struct am65_cpsw_rx_flow {
96 u32 id;
97 struct napi_struct napi_rx;
98 struct am65_cpsw_common *common;
99 int irq;
100 bool irq_disabled;
101 struct hrtimer rx_hrtimer;
102 unsigned long rx_pace_timeout;
103 struct page_pool *page_pool;
104 char name[32];
105};
106
107struct am65_cpsw_swdata {
108 u32 flow_id;
109 struct page *page;
110};
111
112struct am65_cpsw_rx_chn {
113 struct device *dev;
114 struct device *dma_dev;
115 struct k3_cppi_desc_pool *desc_pool;
116 struct k3_udma_glue_rx_channel *rx_chn;
117 u32 descs_num;
118 unsigned char dsize_log2;
119 struct am65_cpsw_rx_flow flows[AM65_CPSW_MAX_QUEUES];
120};
121
122#define AM65_CPSW_QUIRK_I2027_NO_TX_CSUM BIT(0)
123#define AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ BIT(1)
124
125struct am65_cpsw_pdata {
126 u32 quirks;
127 u64 extra_modes;
128 enum k3_ring_mode fdqring_mode;
129 const char *ale_dev_id;
130};
131
132enum cpsw_devlink_param_id {
133 AM65_CPSW_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
134 AM65_CPSW_DL_PARAM_SWITCH_MODE,
135};
136
137struct am65_cpsw_devlink {
138 struct am65_cpsw_common *common;
139};
140
141struct am65_cpsw_common {
142 struct device *dev;
143 struct device *mdio_dev;
144 struct am65_cpsw_pdata pdata;
145
146 void __iomem *ss_base;
147 void __iomem *cpsw_base;
148
149 u32 port_num;
150 struct am65_cpsw_host host;
151 struct am65_cpsw_port *ports;
152 u32 disabled_ports_mask;
153 struct net_device *dma_ndev;
154
155 int usage_count; /* number of opened ports */
156 struct cpsw_ale *ale;
157 int tx_ch_num;
158 u32 tx_ch_rate_msk;
159 u32 rx_flow_id_base;
160
161 struct am65_cpsw_tx_chn tx_chns[AM65_CPSW_MAX_QUEUES];
162 struct completion tdown_complete;
163 atomic_t tdown_cnt;
164
165 int rx_ch_num_flows;
166 struct am65_cpsw_rx_chn rx_chns;
167
168 u32 nuss_ver;
169 u32 cpsw_ver;
170 unsigned long bus_freq;
171 bool pf_p0_rx_ptype_rrobin;
172 struct am65_cpts *cpts;
173 int est_enabled;
174 bool iet_enabled;
175
176 bool is_emac_mode;
177 u16 br_members;
178 int default_vlan;
179 struct devlink *devlink;
180 struct net_device *hw_bridge_dev;
181 struct notifier_block am65_cpsw_netdevice_nb;
182 unsigned char switch_id[MAX_PHYS_ITEM_ID_LEN];
183 /* only for suspend/resume context restore */
184 u32 *ale_context;
185};
186
187struct am65_cpsw_ndev_priv {
188 u32 msg_enable;
189 struct am65_cpsw_port *port;
190 bool offload_fwd_mark;
191 /* Serialize access to MAC Merge state between ethtool requests
192 * and link state updates
193 */
194 struct mutex mm_lock;
195};
196
197#define am65_ndev_to_priv(ndev) \
198 ((struct am65_cpsw_ndev_priv *)netdev_priv(ndev))
199#define am65_ndev_to_port(ndev) (am65_ndev_to_priv(ndev)->port)
200#define am65_ndev_to_common(ndev) (am65_ndev_to_port(ndev)->common)
201#define am65_ndev_to_slave(ndev) (&am65_ndev_to_port(ndev)->slave)
202
203#define am65_common_get_host(common) (&(common)->host)
204#define am65_common_get_port(common, id) (&(common)->ports[(id) - 1])
205
206#define am65_cpsw_napi_to_rx_flow(pnapi) \
207 container_of(pnapi, struct am65_cpsw_rx_flow, napi_rx)
208#define am65_cpsw_napi_to_tx_chn(pnapi) \
209 container_of(pnapi, struct am65_cpsw_tx_chn, napi_tx)
210
211#define AM65_CPSW_DRV_NAME "am65-cpsw-nuss"
212
213#define AM65_CPSW_IS_CPSW2G(common) ((common)->port_num == 1)
214
215extern const struct ethtool_ops am65_cpsw_ethtool_ops_slave;
216
217void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common);
218int am65_cpsw_nuss_update_tx_rx_chns(struct am65_cpsw_common *common,
219 int num_tx, int num_rx);
220
221bool am65_cpsw_port_dev_check(const struct net_device *dev);
222
223#endif /* AM65_CPSW_NUSS_H_ */
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 */
5
6#ifndef AM65_CPSW_NUSS_H_
7#define AM65_CPSW_NUSS_H_
8
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/netdevice.h>
12#include <linux/phy.h>
13#include <linux/platform_device.h>
14#include "am65-cpsw-qos.h"
15
16struct am65_cpts;
17
18#define HOST_PORT_NUM 0
19
20#define AM65_CPSW_MAX_TX_QUEUES 8
21#define AM65_CPSW_MAX_RX_QUEUES 1
22#define AM65_CPSW_MAX_RX_FLOWS 1
23
24struct am65_cpsw_slave_data {
25 bool mac_only;
26 struct cpsw_sl *mac_sl;
27 struct device_node *phy_node;
28 struct phy_device *phy;
29 phy_interface_t phy_if;
30 struct phy *ifphy;
31 bool rx_pause;
32 bool tx_pause;
33 u8 mac_addr[ETH_ALEN];
34};
35
36struct am65_cpsw_port {
37 struct am65_cpsw_common *common;
38 struct net_device *ndev;
39 const char *name;
40 u32 port_id;
41 void __iomem *port_base;
42 void __iomem *stat_base;
43 void __iomem *fetch_ram_base;
44 bool disabled;
45 struct am65_cpsw_slave_data slave;
46 bool tx_ts_enabled;
47 bool rx_ts_enabled;
48 struct am65_cpsw_qos qos;
49};
50
51struct am65_cpsw_host {
52 struct am65_cpsw_common *common;
53 void __iomem *port_base;
54 void __iomem *stat_base;
55};
56
57struct am65_cpsw_tx_chn {
58 struct napi_struct napi_tx;
59 struct am65_cpsw_common *common;
60 struct k3_cppi_desc_pool *desc_pool;
61 struct k3_udma_glue_tx_channel *tx_chn;
62 int irq;
63 u32 id;
64 u32 descs_num;
65 char tx_chn_name[128];
66};
67
68struct am65_cpsw_rx_chn {
69 struct device *dev;
70 struct k3_cppi_desc_pool *desc_pool;
71 struct k3_udma_glue_rx_channel *rx_chn;
72 u32 descs_num;
73 int irq;
74};
75
76#define AM65_CPSW_QUIRK_I2027_NO_TX_CSUM BIT(0)
77
78struct am65_cpsw_pdata {
79 u32 quirks;
80};
81
82struct am65_cpsw_common {
83 struct device *dev;
84 struct device *mdio_dev;
85 struct am65_cpsw_pdata pdata;
86
87 void __iomem *ss_base;
88 void __iomem *cpsw_base;
89
90 u32 port_num;
91 struct am65_cpsw_host host;
92 struct am65_cpsw_port *ports;
93 u32 disabled_ports_mask;
94
95 int usage_count; /* number of opened ports */
96 struct cpsw_ale *ale;
97 int tx_ch_num;
98 u32 rx_flow_id_base;
99
100 struct am65_cpsw_tx_chn tx_chns[AM65_CPSW_MAX_TX_QUEUES];
101 struct completion tdown_complete;
102 atomic_t tdown_cnt;
103
104 struct am65_cpsw_rx_chn rx_chns;
105 struct napi_struct napi_rx;
106
107 u32 nuss_ver;
108 u32 cpsw_ver;
109 bool pf_p0_rx_ptype_rrobin;
110 struct am65_cpts *cpts;
111 int est_enabled;
112};
113
114struct am65_cpsw_ndev_stats {
115 u64 tx_packets;
116 u64 tx_bytes;
117 u64 rx_packets;
118 u64 rx_bytes;
119 struct u64_stats_sync syncp;
120};
121
122struct am65_cpsw_ndev_priv {
123 u32 msg_enable;
124 struct am65_cpsw_port *port;
125 struct am65_cpsw_ndev_stats __percpu *stats;
126};
127
128#define am65_ndev_to_priv(ndev) \
129 ((struct am65_cpsw_ndev_priv *)netdev_priv(ndev))
130#define am65_ndev_to_port(ndev) (am65_ndev_to_priv(ndev)->port)
131#define am65_ndev_to_common(ndev) (am65_ndev_to_port(ndev)->common)
132#define am65_ndev_to_slave(ndev) (&am65_ndev_to_port(ndev)->slave)
133
134#define am65_common_get_host(common) (&(common)->host)
135#define am65_common_get_port(common, id) (&(common)->ports[(id) - 1])
136
137#define am65_cpsw_napi_to_common(pnapi) \
138 container_of(pnapi, struct am65_cpsw_common, napi_rx)
139#define am65_cpsw_napi_to_tx_chn(pnapi) \
140 container_of(pnapi, struct am65_cpsw_tx_chn, napi_tx)
141
142#define AM65_CPSW_DRV_NAME "am65-cpsw-nuss"
143
144#define AM65_CPSW_IS_CPSW2G(common) ((common)->port_num == 1)
145
146extern const struct ethtool_ops am65_cpsw_ethtool_ops_slave;
147
148void am65_cpsw_nuss_adjust_link(struct net_device *ndev);
149void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common);
150void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common);
151int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx);
152
153#endif /* AM65_CPSW_NUSS_H_ */