1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
  3 *
  4 */
  5
  6#ifndef AM65_CPSW_NUSS_H_
  7#define AM65_CPSW_NUSS_H_
  8
  9#include <linux/if_ether.h>
 10#include <linux/kernel.h>
 11#include <linux/module.h>
 12#include <linux/netdevice.h>
 13#include <linux/phylink.h>
 14#include <linux/platform_device.h>
 15#include <linux/soc/ti/k3-ringacc.h>
 16#include <net/devlink.h>
 17#include "am65-cpsw-qos.h"
 18
 19struct am65_cpts;
 20
 21#define HOST_PORT_NUM		0
 22
 23#define AM65_CPSW_MAX_TX_QUEUES	8
 24#define AM65_CPSW_MAX_RX_QUEUES	1
 25#define AM65_CPSW_MAX_RX_FLOWS	1
 26
 27#define AM65_CPSW_PORT_VLAN_REG_OFFSET	0x014
 28
 29struct am65_cpsw_slave_data {
 30	bool				mac_only;
 31	struct cpsw_sl			*mac_sl;
 32	struct device_node		*phy_node;
 33	phy_interface_t			phy_if;
 34	struct phy			*ifphy;
 35	struct phy			*serdes_phy;
 36	bool				rx_pause;
 37	bool				tx_pause;
 38	u8				mac_addr[ETH_ALEN];
 39	int				port_vlan;
 40	struct phylink			*phylink;
 41	struct phylink_config		phylink_config;
 42};
 43
 44struct am65_cpsw_port {
 45	struct am65_cpsw_common		*common;
 46	struct net_device		*ndev;
 47	const char			*name;
 48	u32				port_id;
 49	void __iomem			*port_base;
 50	void __iomem			*sgmii_base;
 51	void __iomem			*stat_base;
 52	void __iomem			*fetch_ram_base;
 53	bool				disabled;
 54	struct am65_cpsw_slave_data	slave;
 55	bool				tx_ts_enabled;
 56	bool				rx_ts_enabled;
 57	struct am65_cpsw_qos		qos;
 58	struct devlink_port		devlink_port;
 59	/* Only for suspend resume context */
 60	u32				vid_context;
 61};
 62
 63struct am65_cpsw_host {
 64	struct am65_cpsw_common		*common;
 65	void __iomem			*port_base;
 66	void __iomem			*stat_base;
 67	/* Only for suspend resume context */
 68	u32				vid_context;
 69};
 70
 71struct am65_cpsw_tx_chn {
 72	struct device *dma_dev;
 73	struct napi_struct napi_tx;
 74	struct am65_cpsw_common	*common;
 75	struct k3_cppi_desc_pool *desc_pool;
 76	struct k3_udma_glue_tx_channel *tx_chn;
 77	spinlock_t lock; /* protect TX rings in multi-port mode */
 78	struct hrtimer tx_hrtimer;
 79	unsigned long tx_pace_timeout;
 80	int irq;
 81	u32 id;
 82	u32 descs_num;
 83	char tx_chn_name[128];
 84	u32 rate_mbps;
 85};
 86
 87struct am65_cpsw_rx_chn {
 88	struct device *dev;
 89	struct device *dma_dev;
 90	struct k3_cppi_desc_pool *desc_pool;
 91	struct k3_udma_glue_rx_channel *rx_chn;
 92	u32 descs_num;
 93	int irq;
 94};
 95
 96#define AM65_CPSW_QUIRK_I2027_NO_TX_CSUM BIT(0)
 97#define AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ BIT(1)
 98
 99struct am65_cpsw_pdata {
100	u32	quirks;
101	u64	extra_modes;
102	enum k3_ring_mode fdqring_mode;
103	const char	*ale_dev_id;
104};
105
106enum cpsw_devlink_param_id {
107	AM65_CPSW_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
108	AM65_CPSW_DL_PARAM_SWITCH_MODE,
109};
110
111struct am65_cpsw_devlink {
112	struct am65_cpsw_common *common;
113};
114
115struct am65_cpsw_common {
116	struct device		*dev;
117	struct device		*mdio_dev;
118	struct am65_cpsw_pdata	pdata;
119
120	void __iomem		*ss_base;
121	void __iomem		*cpsw_base;
122
123	u32			port_num;
124	struct am65_cpsw_host   host;
125	struct am65_cpsw_port	*ports;
126	u32			disabled_ports_mask;
127	struct net_device	*dma_ndev;
128
129	int			usage_count; /* number of opened ports */
130	struct cpsw_ale		*ale;
131	int			tx_ch_num;
132	u32			tx_ch_rate_msk;
133	u32			rx_flow_id_base;
134
135	struct am65_cpsw_tx_chn	tx_chns[AM65_CPSW_MAX_TX_QUEUES];
136	struct completion	tdown_complete;
137	atomic_t		tdown_cnt;
138
139	struct am65_cpsw_rx_chn	rx_chns;
140	struct napi_struct	napi_rx;
141
142	bool			rx_irq_disabled;
143	struct hrtimer		rx_hrtimer;
144	unsigned long		rx_pace_timeout;
145
146	u32			nuss_ver;
147	u32			cpsw_ver;
148	unsigned long		bus_freq;
149	bool			pf_p0_rx_ptype_rrobin;
150	struct am65_cpts	*cpts;
151	int			est_enabled;
152	bool			iet_enabled;
153
154	bool		is_emac_mode;
155	u16			br_members;
156	int			default_vlan;
157	struct devlink *devlink;
158	struct net_device *hw_bridge_dev;
159	struct notifier_block am65_cpsw_netdevice_nb;
160	unsigned char switch_id[MAX_PHYS_ITEM_ID_LEN];
161	/* only for suspend/resume context restore */
162	u32			*ale_context;
163};
164
165struct am65_cpsw_ndev_stats {
166	u64 tx_packets;
167	u64 tx_bytes;
168	u64 rx_packets;
169	u64 rx_bytes;
170	struct u64_stats_sync syncp;
171};
172
173struct am65_cpsw_ndev_priv {
174	u32			msg_enable;
175	struct am65_cpsw_port	*port;
176	struct am65_cpsw_ndev_stats __percpu *stats;
177	bool offload_fwd_mark;
178	/* Serialize access to MAC Merge state between ethtool requests
179	 * and link state updates
180	 */
181	struct mutex		mm_lock;
182};
183
184#define am65_ndev_to_priv(ndev) \
185	((struct am65_cpsw_ndev_priv *)netdev_priv(ndev))
186#define am65_ndev_to_port(ndev) (am65_ndev_to_priv(ndev)->port)
187#define am65_ndev_to_common(ndev) (am65_ndev_to_port(ndev)->common)
188#define am65_ndev_to_slave(ndev) (&am65_ndev_to_port(ndev)->slave)
189
190#define am65_common_get_host(common) (&(common)->host)
191#define am65_common_get_port(common, id) (&(common)->ports[(id) - 1])
192
193#define am65_cpsw_napi_to_common(pnapi) \
194	container_of(pnapi, struct am65_cpsw_common, napi_rx)
195#define am65_cpsw_napi_to_tx_chn(pnapi) \
196	container_of(pnapi, struct am65_cpsw_tx_chn, napi_tx)
197
198#define AM65_CPSW_DRV_NAME "am65-cpsw-nuss"
199
200#define AM65_CPSW_IS_CPSW2G(common) ((common)->port_num == 1)
201
202extern const struct ethtool_ops am65_cpsw_ethtool_ops_slave;
203
204void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common);
205void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common);
206int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx);
207
208bool am65_cpsw_port_dev_check(const struct net_device *dev);
209
210#endif /* AM65_CPSW_NUSS_H_ */