Loading...
Note: File does not exist in v6.13.7.
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2008 Intel Corporation. */
3
4/* ixgb_hw.c
5 * Shared functions for accessing and configuring the adapter
6 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/pci_ids.h>
11#include "ixgb_hw.h"
12#include "ixgb_ids.h"
13
14#include <linux/etherdevice.h>
15
16/* Local function prototypes */
17
18static u32 ixgb_hash_mc_addr(struct ixgb_hw *hw, u8 * mc_addr);
19
20static void ixgb_mta_set(struct ixgb_hw *hw, u32 hash_value);
21
22static void ixgb_get_bus_info(struct ixgb_hw *hw);
23
24static bool ixgb_link_reset(struct ixgb_hw *hw);
25
26static void ixgb_optics_reset(struct ixgb_hw *hw);
27
28static void ixgb_optics_reset_bcm(struct ixgb_hw *hw);
29
30static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw);
31
32static void ixgb_clear_hw_cntrs(struct ixgb_hw *hw);
33
34static void ixgb_clear_vfta(struct ixgb_hw *hw);
35
36static void ixgb_init_rx_addrs(struct ixgb_hw *hw);
37
38static u16 ixgb_read_phy_reg(struct ixgb_hw *hw,
39 u32 reg_address,
40 u32 phy_address,
41 u32 device_type);
42
43static bool ixgb_setup_fc(struct ixgb_hw *hw);
44
45static bool mac_addr_valid(u8 *mac_addr);
46
47static u32 ixgb_mac_reset(struct ixgb_hw *hw)
48{
49 u32 ctrl_reg;
50
51 ctrl_reg = IXGB_CTRL0_RST |
52 IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */
53 IXGB_CTRL0_SDP2_DIR |
54 IXGB_CTRL0_SDP1_DIR |
55 IXGB_CTRL0_SDP0_DIR |
56 IXGB_CTRL0_SDP3 | /* Initial value 1101 */
57 IXGB_CTRL0_SDP2 |
58 IXGB_CTRL0_SDP0;
59
60#ifdef HP_ZX1
61 /* Workaround for 82597EX reset errata */
62 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg);
63#else
64 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
65#endif
66
67 /* Delay a few ms just to allow the reset to complete */
68 msleep(IXGB_DELAY_AFTER_RESET);
69 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
70#ifdef DBG
71 /* Make sure the self-clearing global reset bit did self clear */
72 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST));
73#endif
74
75 if (hw->subsystem_vendor_id == PCI_VENDOR_ID_SUN) {
76 ctrl_reg = /* Enable interrupt from XFP and SerDes */
77 IXGB_CTRL1_GPI0_EN |
78 IXGB_CTRL1_SDP6_DIR |
79 IXGB_CTRL1_SDP7_DIR |
80 IXGB_CTRL1_SDP6 |
81 IXGB_CTRL1_SDP7;
82 IXGB_WRITE_REG(hw, CTRL1, ctrl_reg);
83 ixgb_optics_reset_bcm(hw);
84 }
85
86 if (hw->phy_type == ixgb_phy_type_txn17401)
87 ixgb_optics_reset(hw);
88
89 return ctrl_reg;
90}
91
92/******************************************************************************
93 * Reset the transmit and receive units; mask and clear all interrupts.
94 *
95 * hw - Struct containing variables accessed by shared code
96 *****************************************************************************/
97bool
98ixgb_adapter_stop(struct ixgb_hw *hw)
99{
100 u32 ctrl_reg;
101 u32 icr_reg;
102
103 ENTER();
104
105 /* If we are stopped or resetting exit gracefully and wait to be
106 * started again before accessing the hardware.
107 */
108 if (hw->adapter_stopped) {
109 pr_debug("Exiting because the adapter is already stopped!!!\n");
110 return false;
111 }
112
113 /* Set the Adapter Stopped flag so other driver functions stop
114 * touching the Hardware.
115 */
116 hw->adapter_stopped = true;
117
118 /* Clear interrupt mask to stop board from generating interrupts */
119 pr_debug("Masking off all interrupts\n");
120 IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF);
121
122 /* Disable the Transmit and Receive units. Then delay to allow
123 * any pending transactions to complete before we hit the MAC with
124 * the global reset.
125 */
126 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
127 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
128 IXGB_WRITE_FLUSH(hw);
129 msleep(IXGB_DELAY_BEFORE_RESET);
130
131 /* Issue a global reset to the MAC. This will reset the chip's
132 * transmit, receive, DMA, and link units. It will not effect
133 * the current PCI configuration. The global reset bit is self-
134 * clearing, and should clear within a microsecond.
135 */
136 pr_debug("Issuing a global reset to MAC\n");
137
138 ctrl_reg = ixgb_mac_reset(hw);
139
140 /* Clear interrupt mask to stop board from generating interrupts */
141 pr_debug("Masking off all interrupts\n");
142 IXGB_WRITE_REG(hw, IMC, 0xffffffff);
143
144 /* Clear any pending interrupt events. */
145 icr_reg = IXGB_READ_REG(hw, ICR);
146
147 return ctrl_reg & IXGB_CTRL0_RST;
148}
149
150
151/******************************************************************************
152 * Identifies the vendor of the optics module on the adapter. The SR adapters
153 * support two different types of XPAK optics, so it is necessary to determine
154 * which optics are present before applying any optics-specific workarounds.
155 *
156 * hw - Struct containing variables accessed by shared code.
157 *
158 * Returns: the vendor of the XPAK optics module.
159 *****************************************************************************/
160static ixgb_xpak_vendor
161ixgb_identify_xpak_vendor(struct ixgb_hw *hw)
162{
163 u32 i;
164 u16 vendor_name[5];
165 ixgb_xpak_vendor xpak_vendor;
166
167 ENTER();
168
169 /* Read the first few bytes of the vendor string from the XPAK NVR
170 * registers. These are standard XENPAK/XPAK registers, so all XPAK
171 * devices should implement them. */
172 for (i = 0; i < 5; i++) {
173 vendor_name[i] = ixgb_read_phy_reg(hw,
174 MDIO_PMA_PMD_XPAK_VENDOR_NAME
175 + i, IXGB_PHY_ADDRESS,
176 MDIO_MMD_PMAPMD);
177 }
178
179 /* Determine the actual vendor */
180 if (vendor_name[0] == 'I' &&
181 vendor_name[1] == 'N' &&
182 vendor_name[2] == 'T' &&
183 vendor_name[3] == 'E' && vendor_name[4] == 'L') {
184 xpak_vendor = ixgb_xpak_vendor_intel;
185 } else {
186 xpak_vendor = ixgb_xpak_vendor_infineon;
187 }
188
189 return xpak_vendor;
190}
191
192/******************************************************************************
193 * Determine the physical layer module on the adapter.
194 *
195 * hw - Struct containing variables accessed by shared code. The device_id
196 * field must be (correctly) populated before calling this routine.
197 *
198 * Returns: the phy type of the adapter.
199 *****************************************************************************/
200static ixgb_phy_type
201ixgb_identify_phy(struct ixgb_hw *hw)
202{
203 ixgb_phy_type phy_type;
204 ixgb_xpak_vendor xpak_vendor;
205
206 ENTER();
207
208 /* Infer the transceiver/phy type from the device id */
209 switch (hw->device_id) {
210 case IXGB_DEVICE_ID_82597EX:
211 pr_debug("Identified TXN17401 optics\n");
212 phy_type = ixgb_phy_type_txn17401;
213 break;
214
215 case IXGB_DEVICE_ID_82597EX_SR:
216 /* The SR adapters carry two different types of XPAK optics
217 * modules; read the vendor identifier to determine the exact
218 * type of optics. */
219 xpak_vendor = ixgb_identify_xpak_vendor(hw);
220 if (xpak_vendor == ixgb_xpak_vendor_intel) {
221 pr_debug("Identified TXN17201 optics\n");
222 phy_type = ixgb_phy_type_txn17201;
223 } else {
224 pr_debug("Identified G6005 optics\n");
225 phy_type = ixgb_phy_type_g6005;
226 }
227 break;
228 case IXGB_DEVICE_ID_82597EX_LR:
229 pr_debug("Identified G6104 optics\n");
230 phy_type = ixgb_phy_type_g6104;
231 break;
232 case IXGB_DEVICE_ID_82597EX_CX4:
233 pr_debug("Identified CX4\n");
234 xpak_vendor = ixgb_identify_xpak_vendor(hw);
235 if (xpak_vendor == ixgb_xpak_vendor_intel) {
236 pr_debug("Identified TXN17201 optics\n");
237 phy_type = ixgb_phy_type_txn17201;
238 } else {
239 pr_debug("Identified G6005 optics\n");
240 phy_type = ixgb_phy_type_g6005;
241 }
242 break;
243 default:
244 pr_debug("Unknown physical layer module\n");
245 phy_type = ixgb_phy_type_unknown;
246 break;
247 }
248
249 /* update phy type for sun specific board */
250 if (hw->subsystem_vendor_id == PCI_VENDOR_ID_SUN)
251 phy_type = ixgb_phy_type_bcm;
252
253 return phy_type;
254}
255
256/******************************************************************************
257 * Performs basic configuration of the adapter.
258 *
259 * hw - Struct containing variables accessed by shared code
260 *
261 * Resets the controller.
262 * Reads and validates the EEPROM.
263 * Initializes the receive address registers.
264 * Initializes the multicast table.
265 * Clears all on-chip counters.
266 * Calls routine to setup flow control settings.
267 * Leaves the transmit and receive units disabled and uninitialized.
268 *
269 * Returns:
270 * true if successful,
271 * false if unrecoverable problems were encountered.
272 *****************************************************************************/
273bool
274ixgb_init_hw(struct ixgb_hw *hw)
275{
276 u32 i;
277 u32 ctrl_reg;
278 bool status;
279
280 ENTER();
281
282 /* Issue a global reset to the MAC. This will reset the chip's
283 * transmit, receive, DMA, and link units. It will not effect
284 * the current PCI configuration. The global reset bit is self-
285 * clearing, and should clear within a microsecond.
286 */
287 pr_debug("Issuing a global reset to MAC\n");
288
289 ctrl_reg = ixgb_mac_reset(hw);
290
291 pr_debug("Issuing an EE reset to MAC\n");
292#ifdef HP_ZX1
293 /* Workaround for 82597EX reset errata */
294 IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST);
295#else
296 IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST);
297#endif
298
299 /* Delay a few ms just to allow the reset to complete */
300 msleep(IXGB_DELAY_AFTER_EE_RESET);
301
302 if (!ixgb_get_eeprom_data(hw))
303 return false;
304
305 /* Use the device id to determine the type of phy/transceiver. */
306 hw->device_id = ixgb_get_ee_device_id(hw);
307 hw->phy_type = ixgb_identify_phy(hw);
308
309 /* Setup the receive addresses.
310 * Receive Address Registers (RARs 0 - 15).
311 */
312 ixgb_init_rx_addrs(hw);
313
314 /*
315 * Check that a valid MAC address has been set.
316 * If it is not valid, we fail hardware init.
317 */
318 if (!mac_addr_valid(hw->curr_mac_addr)) {
319 pr_debug("MAC address invalid after ixgb_init_rx_addrs\n");
320 return(false);
321 }
322
323 /* tell the routines in this file they can access hardware again */
324 hw->adapter_stopped = false;
325
326 /* Fill in the bus_info structure */
327 ixgb_get_bus_info(hw);
328
329 /* Zero out the Multicast HASH table */
330 pr_debug("Zeroing the MTA\n");
331 for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
332 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
333
334 /* Zero out the VLAN Filter Table Array */
335 ixgb_clear_vfta(hw);
336
337 /* Zero all of the hardware counters */
338 ixgb_clear_hw_cntrs(hw);
339
340 /* Call a subroutine to setup flow control. */
341 status = ixgb_setup_fc(hw);
342
343 /* 82597EX errata: Call check-for-link in case lane deskew is locked */
344 ixgb_check_for_link(hw);
345
346 return status;
347}
348
349/******************************************************************************
350 * Initializes receive address filters.
351 *
352 * hw - Struct containing variables accessed by shared code
353 *
354 * Places the MAC address in receive address register 0 and clears the rest
355 * of the receive address registers. Clears the multicast table. Assumes
356 * the receiver is in reset when the routine is called.
357 *****************************************************************************/
358static void
359ixgb_init_rx_addrs(struct ixgb_hw *hw)
360{
361 u32 i;
362
363 ENTER();
364
365 /*
366 * If the current mac address is valid, assume it is a software override
367 * to the permanent address.
368 * Otherwise, use the permanent address from the eeprom.
369 */
370 if (!mac_addr_valid(hw->curr_mac_addr)) {
371
372 /* Get the MAC address from the eeprom for later reference */
373 ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr);
374
375 pr_debug("Keeping Permanent MAC Addr = %pM\n",
376 hw->curr_mac_addr);
377 } else {
378
379 /* Setup the receive address. */
380 pr_debug("Overriding MAC Address in RAR[0]\n");
381 pr_debug("New MAC Addr = %pM\n", hw->curr_mac_addr);
382
383 ixgb_rar_set(hw, hw->curr_mac_addr, 0);
384 }
385
386 /* Zero out the other 15 receive addresses. */
387 pr_debug("Clearing RAR[1-15]\n");
388 for (i = 1; i < IXGB_RAR_ENTRIES; i++) {
389 /* Write high reg first to disable the AV bit first */
390 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
391 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
392 }
393}
394
395/******************************************************************************
396 * Updates the MAC's list of multicast addresses.
397 *
398 * hw - Struct containing variables accessed by shared code
399 * mc_addr_list - the list of new multicast addresses
400 * mc_addr_count - number of addresses
401 * pad - number of bytes between addresses in the list
402 *
403 * The given list replaces any existing list. Clears the last 15 receive
404 * address registers and the multicast table. Uses receive address registers
405 * for the first 15 multicast addresses, and hashes the rest into the
406 * multicast table.
407 *****************************************************************************/
408void
409ixgb_mc_addr_list_update(struct ixgb_hw *hw,
410 u8 *mc_addr_list,
411 u32 mc_addr_count,
412 u32 pad)
413{
414 u32 hash_value;
415 u32 i;
416 u32 rar_used_count = 1; /* RAR[0] is used for our MAC address */
417 u8 *mca;
418
419 ENTER();
420
421 /* Set the new number of MC addresses that we are being requested to use. */
422 hw->num_mc_addrs = mc_addr_count;
423
424 /* Clear RAR[1-15] */
425 pr_debug("Clearing RAR[1-15]\n");
426 for (i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
427 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
428 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
429 }
430
431 /* Clear the MTA */
432 pr_debug("Clearing MTA\n");
433 for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
434 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
435
436 /* Add the new addresses */
437 mca = mc_addr_list;
438 for (i = 0; i < mc_addr_count; i++) {
439 pr_debug("Adding the multicast addresses:\n");
440 pr_debug("MC Addr #%d = %pM\n", i, mca);
441
442 /* Place this multicast address in the RAR if there is room, *
443 * else put it in the MTA
444 */
445 if (rar_used_count < IXGB_RAR_ENTRIES) {
446 ixgb_rar_set(hw, mca, rar_used_count);
447 pr_debug("Added a multicast address to RAR[%d]\n", i);
448 rar_used_count++;
449 } else {
450 hash_value = ixgb_hash_mc_addr(hw, mca);
451
452 pr_debug("Hash value = 0x%03X\n", hash_value);
453
454 ixgb_mta_set(hw, hash_value);
455 }
456
457 mca += ETH_ALEN + pad;
458 }
459
460 pr_debug("MC Update Complete\n");
461}
462
463/******************************************************************************
464 * Hashes an address to determine its location in the multicast table
465 *
466 * hw - Struct containing variables accessed by shared code
467 * mc_addr - the multicast address to hash
468 *
469 * Returns:
470 * The hash value
471 *****************************************************************************/
472static u32
473ixgb_hash_mc_addr(struct ixgb_hw *hw,
474 u8 *mc_addr)
475{
476 u32 hash_value = 0;
477
478 ENTER();
479
480 /* The portion of the address that is used for the hash table is
481 * determined by the mc_filter_type setting.
482 */
483 switch (hw->mc_filter_type) {
484 /* [0] [1] [2] [3] [4] [5]
485 * 01 AA 00 12 34 56
486 * LSB MSB - According to H/W docs */
487 case 0:
488 /* [47:36] i.e. 0x563 for above example address */
489 hash_value =
490 ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
491 break;
492 case 1: /* [46:35] i.e. 0xAC6 for above example address */
493 hash_value =
494 ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
495 break;
496 case 2: /* [45:34] i.e. 0x5D8 for above example address */
497 hash_value =
498 ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
499 break;
500 case 3: /* [43:32] i.e. 0x634 for above example address */
501 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
502 break;
503 default:
504 /* Invalid mc_filter_type, what should we do? */
505 pr_debug("MC filter type param set incorrectly\n");
506 ASSERT(0);
507 break;
508 }
509
510 hash_value &= 0xFFF;
511 return hash_value;
512}
513
514/******************************************************************************
515 * Sets the bit in the multicast table corresponding to the hash value.
516 *
517 * hw - Struct containing variables accessed by shared code
518 * hash_value - Multicast address hash value
519 *****************************************************************************/
520static void
521ixgb_mta_set(struct ixgb_hw *hw,
522 u32 hash_value)
523{
524 u32 hash_bit, hash_reg;
525 u32 mta_reg;
526
527 /* The MTA is a register array of 128 32-bit registers.
528 * It is treated like an array of 4096 bits. We want to set
529 * bit BitArray[hash_value]. So we figure out what register
530 * the bit is in, read it, OR in the new bit, then write
531 * back the new value. The register is determined by the
532 * upper 7 bits of the hash value and the bit within that
533 * register are determined by the lower 5 bits of the value.
534 */
535 hash_reg = (hash_value >> 5) & 0x7F;
536 hash_bit = hash_value & 0x1F;
537
538 mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg);
539
540 mta_reg |= (1 << hash_bit);
541
542 IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg);
543}
544
545/******************************************************************************
546 * Puts an ethernet address into a receive address register.
547 *
548 * hw - Struct containing variables accessed by shared code
549 * addr - Address to put into receive address register
550 * index - Receive address register to write
551 *****************************************************************************/
552void
553ixgb_rar_set(struct ixgb_hw *hw,
554 u8 *addr,
555 u32 index)
556{
557 u32 rar_low, rar_high;
558
559 ENTER();
560
561 /* HW expects these in little endian so we reverse the byte order
562 * from network order (big endian) to little endian
563 */
564 rar_low = ((u32) addr[0] |
565 ((u32)addr[1] << 8) |
566 ((u32)addr[2] << 16) |
567 ((u32)addr[3] << 24));
568
569 rar_high = ((u32) addr[4] |
570 ((u32)addr[5] << 8) |
571 IXGB_RAH_AV);
572
573 IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
574 IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
575}
576
577/******************************************************************************
578 * Writes a value to the specified offset in the VLAN filter table.
579 *
580 * hw - Struct containing variables accessed by shared code
581 * offset - Offset in VLAN filer table to write
582 * value - Value to write into VLAN filter table
583 *****************************************************************************/
584void
585ixgb_write_vfta(struct ixgb_hw *hw,
586 u32 offset,
587 u32 value)
588{
589 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
590}
591
592/******************************************************************************
593 * Clears the VLAN filer table
594 *
595 * hw - Struct containing variables accessed by shared code
596 *****************************************************************************/
597static void
598ixgb_clear_vfta(struct ixgb_hw *hw)
599{
600 u32 offset;
601
602 for (offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
603 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
604}
605
606/******************************************************************************
607 * Configures the flow control settings based on SW configuration.
608 *
609 * hw - Struct containing variables accessed by shared code
610 *****************************************************************************/
611
612static bool
613ixgb_setup_fc(struct ixgb_hw *hw)
614{
615 u32 ctrl_reg;
616 u32 pap_reg = 0; /* by default, assume no pause time */
617 bool status = true;
618
619 ENTER();
620
621 /* Get the current control reg 0 settings */
622 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
623
624 /* Clear the Receive Pause Enable and Transmit Pause Enable bits */
625 ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
626
627 /* The possible values of the "flow_control" parameter are:
628 * 0: Flow control is completely disabled
629 * 1: Rx flow control is enabled (we can receive pause frames
630 * but not send pause frames).
631 * 2: Tx flow control is enabled (we can send pause frames
632 * but we do not support receiving pause frames).
633 * 3: Both Rx and TX flow control (symmetric) are enabled.
634 * other: Invalid.
635 */
636 switch (hw->fc.type) {
637 case ixgb_fc_none: /* 0 */
638 /* Set CMDC bit to disable Rx Flow control */
639 ctrl_reg |= (IXGB_CTRL0_CMDC);
640 break;
641 case ixgb_fc_rx_pause: /* 1 */
642 /* RX Flow control is enabled, and TX Flow control is
643 * disabled.
644 */
645 ctrl_reg |= (IXGB_CTRL0_RPE);
646 break;
647 case ixgb_fc_tx_pause: /* 2 */
648 /* TX Flow control is enabled, and RX Flow control is
649 * disabled, by a software over-ride.
650 */
651 ctrl_reg |= (IXGB_CTRL0_TPE);
652 pap_reg = hw->fc.pause_time;
653 break;
654 case ixgb_fc_full: /* 3 */
655 /* Flow control (both RX and TX) is enabled by a software
656 * over-ride.
657 */
658 ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
659 pap_reg = hw->fc.pause_time;
660 break;
661 default:
662 /* We should never get here. The value should be 0-3. */
663 pr_debug("Flow control param set incorrectly\n");
664 ASSERT(0);
665 break;
666 }
667
668 /* Write the new settings */
669 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
670
671 if (pap_reg != 0)
672 IXGB_WRITE_REG(hw, PAP, pap_reg);
673
674 /* Set the flow control receive threshold registers. Normally,
675 * these registers will be set to a default threshold that may be
676 * adjusted later by the driver's runtime code. However, if the
677 * ability to transmit pause frames in not enabled, then these
678 * registers will be set to 0.
679 */
680 if (!(hw->fc.type & ixgb_fc_tx_pause)) {
681 IXGB_WRITE_REG(hw, FCRTL, 0);
682 IXGB_WRITE_REG(hw, FCRTH, 0);
683 } else {
684 /* We need to set up the Receive Threshold high and low water
685 * marks as well as (optionally) enabling the transmission of XON
686 * frames. */
687 if (hw->fc.send_xon) {
688 IXGB_WRITE_REG(hw, FCRTL,
689 (hw->fc.low_water | IXGB_FCRTL_XONE));
690 } else {
691 IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water);
692 }
693 IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water);
694 }
695 return status;
696}
697
698/******************************************************************************
699 * Reads a word from a device over the Management Data Interface (MDI) bus.
700 * This interface is used to manage Physical layer devices.
701 *
702 * hw - Struct containing variables accessed by hw code
703 * reg_address - Offset of device register being read.
704 * phy_address - Address of device on MDI.
705 *
706 * Returns: Data word (16 bits) from MDI device.
707 *
708 * The 82597EX has support for several MDI access methods. This routine
709 * uses the new protocol MDI Single Command and Address Operation.
710 * This requires that first an address cycle command is sent, followed by a
711 * read command.
712 *****************************************************************************/
713static u16
714ixgb_read_phy_reg(struct ixgb_hw *hw,
715 u32 reg_address,
716 u32 phy_address,
717 u32 device_type)
718{
719 u32 i;
720 u32 data;
721 u32 command = 0;
722
723 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
724 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
725 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
726
727 /* Setup and write the address cycle command */
728 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
729 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
730 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
731 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
732
733 IXGB_WRITE_REG(hw, MSCA, command);
734
735 /**************************************************************
736 ** Check every 10 usec to see if the address cycle completed
737 ** The COMMAND bit will clear when the operation is complete.
738 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
739 ** from the CPU Write to the Ready bit assertion.
740 **************************************************************/
741
742 for (i = 0; i < 10; i++)
743 {
744 udelay(10);
745
746 command = IXGB_READ_REG(hw, MSCA);
747
748 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
749 break;
750 }
751
752 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
753
754 /* Address cycle complete, setup and write the read command */
755 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
756 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
757 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
758 (IXGB_MSCA_READ | IXGB_MSCA_MDI_COMMAND));
759
760 IXGB_WRITE_REG(hw, MSCA, command);
761
762 /**************************************************************
763 ** Check every 10 usec to see if the read command completed
764 ** The COMMAND bit will clear when the operation is complete.
765 ** The read may take as long as 64 usecs (we'll wait 100 usecs max)
766 ** from the CPU Write to the Ready bit assertion.
767 **************************************************************/
768
769 for (i = 0; i < 10; i++)
770 {
771 udelay(10);
772
773 command = IXGB_READ_REG(hw, MSCA);
774
775 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
776 break;
777 }
778
779 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
780
781 /* Operation is complete, get the data from the MDIO Read/Write Data
782 * register and return.
783 */
784 data = IXGB_READ_REG(hw, MSRWD);
785 data >>= IXGB_MSRWD_READ_DATA_SHIFT;
786 return((u16) data);
787}
788
789/******************************************************************************
790 * Writes a word to a device over the Management Data Interface (MDI) bus.
791 * This interface is used to manage Physical layer devices.
792 *
793 * hw - Struct containing variables accessed by hw code
794 * reg_address - Offset of device register being read.
795 * phy_address - Address of device on MDI.
796 * device_type - Also known as the Device ID or DID.
797 * data - 16-bit value to be written
798 *
799 * Returns: void.
800 *
801 * The 82597EX has support for several MDI access methods. This routine
802 * uses the new protocol MDI Single Command and Address Operation.
803 * This requires that first an address cycle command is sent, followed by a
804 * write command.
805 *****************************************************************************/
806static void
807ixgb_write_phy_reg(struct ixgb_hw *hw,
808 u32 reg_address,
809 u32 phy_address,
810 u32 device_type,
811 u16 data)
812{
813 u32 i;
814 u32 command = 0;
815
816 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
817 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
818 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
819
820 /* Put the data in the MDIO Read/Write Data register */
821 IXGB_WRITE_REG(hw, MSRWD, (u32)data);
822
823 /* Setup and write the address cycle command */
824 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
825 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
826 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
827 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
828
829 IXGB_WRITE_REG(hw, MSCA, command);
830
831 /**************************************************************
832 ** Check every 10 usec to see if the address cycle completed
833 ** The COMMAND bit will clear when the operation is complete.
834 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
835 ** from the CPU Write to the Ready bit assertion.
836 **************************************************************/
837
838 for (i = 0; i < 10; i++)
839 {
840 udelay(10);
841
842 command = IXGB_READ_REG(hw, MSCA);
843
844 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
845 break;
846 }
847
848 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
849
850 /* Address cycle complete, setup and write the write command */
851 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
852 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
853 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
854 (IXGB_MSCA_WRITE | IXGB_MSCA_MDI_COMMAND));
855
856 IXGB_WRITE_REG(hw, MSCA, command);
857
858 /**************************************************************
859 ** Check every 10 usec to see if the read command completed
860 ** The COMMAND bit will clear when the operation is complete.
861 ** The write may take as long as 64 usecs (we'll wait 100 usecs max)
862 ** from the CPU Write to the Ready bit assertion.
863 **************************************************************/
864
865 for (i = 0; i < 10; i++)
866 {
867 udelay(10);
868
869 command = IXGB_READ_REG(hw, MSCA);
870
871 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
872 break;
873 }
874
875 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
876
877 /* Operation is complete, return. */
878}
879
880/******************************************************************************
881 * Checks to see if the link status of the hardware has changed.
882 *
883 * hw - Struct containing variables accessed by hw code
884 *
885 * Called by any function that needs to check the link status of the adapter.
886 *****************************************************************************/
887void
888ixgb_check_for_link(struct ixgb_hw *hw)
889{
890 u32 status_reg;
891 u32 xpcss_reg;
892
893 ENTER();
894
895 xpcss_reg = IXGB_READ_REG(hw, XPCSS);
896 status_reg = IXGB_READ_REG(hw, STATUS);
897
898 if ((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
899 (status_reg & IXGB_STATUS_LU)) {
900 hw->link_up = true;
901 } else if (!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
902 (status_reg & IXGB_STATUS_LU)) {
903 pr_debug("XPCSS Not Aligned while Status:LU is set\n");
904 hw->link_up = ixgb_link_reset(hw);
905 } else {
906 /*
907 * 82597EX errata. Since the lane deskew problem may prevent
908 * link, reset the link before reporting link down.
909 */
910 hw->link_up = ixgb_link_reset(hw);
911 }
912 /* Anything else for 10 Gig?? */
913}
914
915/******************************************************************************
916 * Check for a bad link condition that may have occurred.
917 * The indication is that the RFC / LFC registers may be incrementing
918 * continually. A full adapter reset is required to recover.
919 *
920 * hw - Struct containing variables accessed by hw code
921 *
922 * Called by any function that needs to check the link status of the adapter.
923 *****************************************************************************/
924bool ixgb_check_for_bad_link(struct ixgb_hw *hw)
925{
926 u32 newLFC, newRFC;
927 bool bad_link_returncode = false;
928
929 if (hw->phy_type == ixgb_phy_type_txn17401) {
930 newLFC = IXGB_READ_REG(hw, LFC);
931 newRFC = IXGB_READ_REG(hw, RFC);
932 if ((hw->lastLFC + 250 < newLFC)
933 || (hw->lastRFC + 250 < newRFC)) {
934 pr_debug("BAD LINK! too many LFC/RFC since last check\n");
935 bad_link_returncode = true;
936 }
937 hw->lastLFC = newLFC;
938 hw->lastRFC = newRFC;
939 }
940
941 return bad_link_returncode;
942}
943
944/******************************************************************************
945 * Clears all hardware statistics counters.
946 *
947 * hw - Struct containing variables accessed by shared code
948 *****************************************************************************/
949static void
950ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
951{
952 volatile u32 temp_reg;
953
954 ENTER();
955
956 /* if we are stopped or resetting exit gracefully */
957 if (hw->adapter_stopped) {
958 pr_debug("Exiting because the adapter is stopped!!!\n");
959 return;
960 }
961
962 temp_reg = IXGB_READ_REG(hw, TPRL);
963 temp_reg = IXGB_READ_REG(hw, TPRH);
964 temp_reg = IXGB_READ_REG(hw, GPRCL);
965 temp_reg = IXGB_READ_REG(hw, GPRCH);
966 temp_reg = IXGB_READ_REG(hw, BPRCL);
967 temp_reg = IXGB_READ_REG(hw, BPRCH);
968 temp_reg = IXGB_READ_REG(hw, MPRCL);
969 temp_reg = IXGB_READ_REG(hw, MPRCH);
970 temp_reg = IXGB_READ_REG(hw, UPRCL);
971 temp_reg = IXGB_READ_REG(hw, UPRCH);
972 temp_reg = IXGB_READ_REG(hw, VPRCL);
973 temp_reg = IXGB_READ_REG(hw, VPRCH);
974 temp_reg = IXGB_READ_REG(hw, JPRCL);
975 temp_reg = IXGB_READ_REG(hw, JPRCH);
976 temp_reg = IXGB_READ_REG(hw, GORCL);
977 temp_reg = IXGB_READ_REG(hw, GORCH);
978 temp_reg = IXGB_READ_REG(hw, TORL);
979 temp_reg = IXGB_READ_REG(hw, TORH);
980 temp_reg = IXGB_READ_REG(hw, RNBC);
981 temp_reg = IXGB_READ_REG(hw, RUC);
982 temp_reg = IXGB_READ_REG(hw, ROC);
983 temp_reg = IXGB_READ_REG(hw, RLEC);
984 temp_reg = IXGB_READ_REG(hw, CRCERRS);
985 temp_reg = IXGB_READ_REG(hw, ICBC);
986 temp_reg = IXGB_READ_REG(hw, ECBC);
987 temp_reg = IXGB_READ_REG(hw, MPC);
988 temp_reg = IXGB_READ_REG(hw, TPTL);
989 temp_reg = IXGB_READ_REG(hw, TPTH);
990 temp_reg = IXGB_READ_REG(hw, GPTCL);
991 temp_reg = IXGB_READ_REG(hw, GPTCH);
992 temp_reg = IXGB_READ_REG(hw, BPTCL);
993 temp_reg = IXGB_READ_REG(hw, BPTCH);
994 temp_reg = IXGB_READ_REG(hw, MPTCL);
995 temp_reg = IXGB_READ_REG(hw, MPTCH);
996 temp_reg = IXGB_READ_REG(hw, UPTCL);
997 temp_reg = IXGB_READ_REG(hw, UPTCH);
998 temp_reg = IXGB_READ_REG(hw, VPTCL);
999 temp_reg = IXGB_READ_REG(hw, VPTCH);
1000 temp_reg = IXGB_READ_REG(hw, JPTCL);
1001 temp_reg = IXGB_READ_REG(hw, JPTCH);
1002 temp_reg = IXGB_READ_REG(hw, GOTCL);
1003 temp_reg = IXGB_READ_REG(hw, GOTCH);
1004 temp_reg = IXGB_READ_REG(hw, TOTL);
1005 temp_reg = IXGB_READ_REG(hw, TOTH);
1006 temp_reg = IXGB_READ_REG(hw, DC);
1007 temp_reg = IXGB_READ_REG(hw, PLT64C);
1008 temp_reg = IXGB_READ_REG(hw, TSCTC);
1009 temp_reg = IXGB_READ_REG(hw, TSCTFC);
1010 temp_reg = IXGB_READ_REG(hw, IBIC);
1011 temp_reg = IXGB_READ_REG(hw, RFC);
1012 temp_reg = IXGB_READ_REG(hw, LFC);
1013 temp_reg = IXGB_READ_REG(hw, PFRC);
1014 temp_reg = IXGB_READ_REG(hw, PFTC);
1015 temp_reg = IXGB_READ_REG(hw, MCFRC);
1016 temp_reg = IXGB_READ_REG(hw, MCFTC);
1017 temp_reg = IXGB_READ_REG(hw, XONRXC);
1018 temp_reg = IXGB_READ_REG(hw, XONTXC);
1019 temp_reg = IXGB_READ_REG(hw, XOFFRXC);
1020 temp_reg = IXGB_READ_REG(hw, XOFFTXC);
1021 temp_reg = IXGB_READ_REG(hw, RJC);
1022}
1023
1024/******************************************************************************
1025 * Turns on the software controllable LED
1026 *
1027 * hw - Struct containing variables accessed by shared code
1028 *****************************************************************************/
1029void
1030ixgb_led_on(struct ixgb_hw *hw)
1031{
1032 u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1033
1034 /* To turn on the LED, clear software-definable pin 0 (SDP0). */
1035 ctrl0_reg &= ~IXGB_CTRL0_SDP0;
1036 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1037}
1038
1039/******************************************************************************
1040 * Turns off the software controllable LED
1041 *
1042 * hw - Struct containing variables accessed by shared code
1043 *****************************************************************************/
1044void
1045ixgb_led_off(struct ixgb_hw *hw)
1046{
1047 u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1048
1049 /* To turn off the LED, set software-definable pin 0 (SDP0). */
1050 ctrl0_reg |= IXGB_CTRL0_SDP0;
1051 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1052}
1053
1054/******************************************************************************
1055 * Gets the current PCI bus type, speed, and width of the hardware
1056 *
1057 * hw - Struct containing variables accessed by shared code
1058 *****************************************************************************/
1059static void
1060ixgb_get_bus_info(struct ixgb_hw *hw)
1061{
1062 u32 status_reg;
1063
1064 status_reg = IXGB_READ_REG(hw, STATUS);
1065
1066 hw->bus.type = (status_reg & IXGB_STATUS_PCIX_MODE) ?
1067 ixgb_bus_type_pcix : ixgb_bus_type_pci;
1068
1069 if (hw->bus.type == ixgb_bus_type_pci) {
1070 hw->bus.speed = (status_reg & IXGB_STATUS_PCI_SPD) ?
1071 ixgb_bus_speed_66 : ixgb_bus_speed_33;
1072 } else {
1073 switch (status_reg & IXGB_STATUS_PCIX_SPD_MASK) {
1074 case IXGB_STATUS_PCIX_SPD_66:
1075 hw->bus.speed = ixgb_bus_speed_66;
1076 break;
1077 case IXGB_STATUS_PCIX_SPD_100:
1078 hw->bus.speed = ixgb_bus_speed_100;
1079 break;
1080 case IXGB_STATUS_PCIX_SPD_133:
1081 hw->bus.speed = ixgb_bus_speed_133;
1082 break;
1083 default:
1084 hw->bus.speed = ixgb_bus_speed_reserved;
1085 break;
1086 }
1087 }
1088
1089 hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ?
1090 ixgb_bus_width_64 : ixgb_bus_width_32;
1091}
1092
1093/******************************************************************************
1094 * Tests a MAC address to ensure it is a valid Individual Address
1095 *
1096 * mac_addr - pointer to MAC address.
1097 *
1098 *****************************************************************************/
1099static bool
1100mac_addr_valid(u8 *mac_addr)
1101{
1102 bool is_valid = true;
1103 ENTER();
1104
1105 /* Make sure it is not a multicast address */
1106 if (is_multicast_ether_addr(mac_addr)) {
1107 pr_debug("MAC address is multicast\n");
1108 is_valid = false;
1109 }
1110 /* Not a broadcast address */
1111 else if (is_broadcast_ether_addr(mac_addr)) {
1112 pr_debug("MAC address is broadcast\n");
1113 is_valid = false;
1114 }
1115 /* Reject the zero address */
1116 else if (is_zero_ether_addr(mac_addr)) {
1117 pr_debug("MAC address is all zeros\n");
1118 is_valid = false;
1119 }
1120 return is_valid;
1121}
1122
1123/******************************************************************************
1124 * Resets the 10GbE link. Waits the settle time and returns the state of
1125 * the link.
1126 *
1127 * hw - Struct containing variables accessed by shared code
1128 *****************************************************************************/
1129static bool
1130ixgb_link_reset(struct ixgb_hw *hw)
1131{
1132 bool link_status = false;
1133 u8 wait_retries = MAX_RESET_ITERATIONS;
1134 u8 lrst_retries = MAX_RESET_ITERATIONS;
1135
1136 do {
1137 /* Reset the link */
1138 IXGB_WRITE_REG(hw, CTRL0,
1139 IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST);
1140
1141 /* Wait for link-up and lane re-alignment */
1142 do {
1143 udelay(IXGB_DELAY_USECS_AFTER_LINK_RESET);
1144 link_status =
1145 ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU)
1146 && (IXGB_READ_REG(hw, XPCSS) &
1147 IXGB_XPCSS_ALIGN_STATUS)) ? true : false;
1148 } while (!link_status && --wait_retries);
1149
1150 } while (!link_status && --lrst_retries);
1151
1152 return link_status;
1153}
1154
1155/******************************************************************************
1156 * Resets the 10GbE optics module.
1157 *
1158 * hw - Struct containing variables accessed by shared code
1159 *****************************************************************************/
1160static void
1161ixgb_optics_reset(struct ixgb_hw *hw)
1162{
1163 if (hw->phy_type == ixgb_phy_type_txn17401) {
1164 u16 mdio_reg;
1165
1166 ixgb_write_phy_reg(hw,
1167 MDIO_CTRL1,
1168 IXGB_PHY_ADDRESS,
1169 MDIO_MMD_PMAPMD,
1170 MDIO_CTRL1_RESET);
1171
1172 mdio_reg = ixgb_read_phy_reg(hw,
1173 MDIO_CTRL1,
1174 IXGB_PHY_ADDRESS,
1175 MDIO_MMD_PMAPMD);
1176 }
1177}
1178
1179/******************************************************************************
1180 * Resets the 10GbE optics module for Sun variant NIC.
1181 *
1182 * hw - Struct containing variables accessed by shared code
1183 *****************************************************************************/
1184
1185#define IXGB_BCM8704_USER_PMD_TX_CTRL_REG 0xC803
1186#define IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL 0x0164
1187#define IXGB_BCM8704_USER_CTRL_REG 0xC800
1188#define IXGB_BCM8704_USER_CTRL_REG_VAL 0x7FBF
1189#define IXGB_BCM8704_USER_DEV3_ADDR 0x0003
1190#define IXGB_SUN_PHY_ADDRESS 0x0000
1191#define IXGB_SUN_PHY_RESET_DELAY 305
1192
1193static void
1194ixgb_optics_reset_bcm(struct ixgb_hw *hw)
1195{
1196 u32 ctrl = IXGB_READ_REG(hw, CTRL0);
1197 ctrl &= ~IXGB_CTRL0_SDP2;
1198 ctrl |= IXGB_CTRL0_SDP3;
1199 IXGB_WRITE_REG(hw, CTRL0, ctrl);
1200 IXGB_WRITE_FLUSH(hw);
1201
1202 /* SerDes needs extra delay */
1203 msleep(IXGB_SUN_PHY_RESET_DELAY);
1204
1205 /* Broadcom 7408L configuration */
1206 /* Reference clock config */
1207 ixgb_write_phy_reg(hw,
1208 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1209 IXGB_SUN_PHY_ADDRESS,
1210 IXGB_BCM8704_USER_DEV3_ADDR,
1211 IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL);
1212 /* we must read the registers twice */
1213 ixgb_read_phy_reg(hw,
1214 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1215 IXGB_SUN_PHY_ADDRESS,
1216 IXGB_BCM8704_USER_DEV3_ADDR);
1217 ixgb_read_phy_reg(hw,
1218 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1219 IXGB_SUN_PHY_ADDRESS,
1220 IXGB_BCM8704_USER_DEV3_ADDR);
1221
1222 ixgb_write_phy_reg(hw,
1223 IXGB_BCM8704_USER_CTRL_REG,
1224 IXGB_SUN_PHY_ADDRESS,
1225 IXGB_BCM8704_USER_DEV3_ADDR,
1226 IXGB_BCM8704_USER_CTRL_REG_VAL);
1227 ixgb_read_phy_reg(hw,
1228 IXGB_BCM8704_USER_CTRL_REG,
1229 IXGB_SUN_PHY_ADDRESS,
1230 IXGB_BCM8704_USER_DEV3_ADDR);
1231 ixgb_read_phy_reg(hw,
1232 IXGB_BCM8704_USER_CTRL_REG,
1233 IXGB_SUN_PHY_ADDRESS,
1234 IXGB_BCM8704_USER_DEV3_ADDR);
1235
1236 /* SerDes needs extra delay */
1237 msleep(IXGB_SUN_PHY_RESET_DELAY);
1238}