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1/*******************************************************************************
2
3 Intel PRO/10GbE Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* ixgb_hw.c
30 * Shared functions for accessing and configuring the adapter
31 */
32
33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
35#include <linux/pci_ids.h>
36#include "ixgb_hw.h"
37#include "ixgb_ids.h"
38
39#include <linux/etherdevice.h>
40
41/* Local function prototypes */
42
43static u32 ixgb_hash_mc_addr(struct ixgb_hw *hw, u8 * mc_addr);
44
45static void ixgb_mta_set(struct ixgb_hw *hw, u32 hash_value);
46
47static void ixgb_get_bus_info(struct ixgb_hw *hw);
48
49static bool ixgb_link_reset(struct ixgb_hw *hw);
50
51static void ixgb_optics_reset(struct ixgb_hw *hw);
52
53static void ixgb_optics_reset_bcm(struct ixgb_hw *hw);
54
55static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw);
56
57static void ixgb_clear_hw_cntrs(struct ixgb_hw *hw);
58
59static void ixgb_clear_vfta(struct ixgb_hw *hw);
60
61static void ixgb_init_rx_addrs(struct ixgb_hw *hw);
62
63static u16 ixgb_read_phy_reg(struct ixgb_hw *hw,
64 u32 reg_address,
65 u32 phy_address,
66 u32 device_type);
67
68static bool ixgb_setup_fc(struct ixgb_hw *hw);
69
70static bool mac_addr_valid(u8 *mac_addr);
71
72static u32 ixgb_mac_reset(struct ixgb_hw *hw)
73{
74 u32 ctrl_reg;
75
76 ctrl_reg = IXGB_CTRL0_RST |
77 IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */
78 IXGB_CTRL0_SDP2_DIR |
79 IXGB_CTRL0_SDP1_DIR |
80 IXGB_CTRL0_SDP0_DIR |
81 IXGB_CTRL0_SDP3 | /* Initial value 1101 */
82 IXGB_CTRL0_SDP2 |
83 IXGB_CTRL0_SDP0;
84
85#ifdef HP_ZX1
86 /* Workaround for 82597EX reset errata */
87 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg);
88#else
89 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
90#endif
91
92 /* Delay a few ms just to allow the reset to complete */
93 msleep(IXGB_DELAY_AFTER_RESET);
94 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
95#ifdef DBG
96 /* Make sure the self-clearing global reset bit did self clear */
97 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST));
98#endif
99
100 if (hw->subsystem_vendor_id == PCI_VENDOR_ID_SUN) {
101 ctrl_reg = /* Enable interrupt from XFP and SerDes */
102 IXGB_CTRL1_GPI0_EN |
103 IXGB_CTRL1_SDP6_DIR |
104 IXGB_CTRL1_SDP7_DIR |
105 IXGB_CTRL1_SDP6 |
106 IXGB_CTRL1_SDP7;
107 IXGB_WRITE_REG(hw, CTRL1, ctrl_reg);
108 ixgb_optics_reset_bcm(hw);
109 }
110
111 if (hw->phy_type == ixgb_phy_type_txn17401)
112 ixgb_optics_reset(hw);
113
114 return ctrl_reg;
115}
116
117/******************************************************************************
118 * Reset the transmit and receive units; mask and clear all interrupts.
119 *
120 * hw - Struct containing variables accessed by shared code
121 *****************************************************************************/
122bool
123ixgb_adapter_stop(struct ixgb_hw *hw)
124{
125 u32 ctrl_reg;
126 u32 icr_reg;
127
128 ENTER();
129
130 /* If we are stopped or resetting exit gracefully and wait to be
131 * started again before accessing the hardware.
132 */
133 if (hw->adapter_stopped) {
134 pr_debug("Exiting because the adapter is already stopped!!!\n");
135 return false;
136 }
137
138 /* Set the Adapter Stopped flag so other driver functions stop
139 * touching the Hardware.
140 */
141 hw->adapter_stopped = true;
142
143 /* Clear interrupt mask to stop board from generating interrupts */
144 pr_debug("Masking off all interrupts\n");
145 IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF);
146
147 /* Disable the Transmit and Receive units. Then delay to allow
148 * any pending transactions to complete before we hit the MAC with
149 * the global reset.
150 */
151 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
152 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
153 IXGB_WRITE_FLUSH(hw);
154 msleep(IXGB_DELAY_BEFORE_RESET);
155
156 /* Issue a global reset to the MAC. This will reset the chip's
157 * transmit, receive, DMA, and link units. It will not effect
158 * the current PCI configuration. The global reset bit is self-
159 * clearing, and should clear within a microsecond.
160 */
161 pr_debug("Issuing a global reset to MAC\n");
162
163 ctrl_reg = ixgb_mac_reset(hw);
164
165 /* Clear interrupt mask to stop board from generating interrupts */
166 pr_debug("Masking off all interrupts\n");
167 IXGB_WRITE_REG(hw, IMC, 0xffffffff);
168
169 /* Clear any pending interrupt events. */
170 icr_reg = IXGB_READ_REG(hw, ICR);
171
172 return ctrl_reg & IXGB_CTRL0_RST;
173}
174
175
176/******************************************************************************
177 * Identifies the vendor of the optics module on the adapter. The SR adapters
178 * support two different types of XPAK optics, so it is necessary to determine
179 * which optics are present before applying any optics-specific workarounds.
180 *
181 * hw - Struct containing variables accessed by shared code.
182 *
183 * Returns: the vendor of the XPAK optics module.
184 *****************************************************************************/
185static ixgb_xpak_vendor
186ixgb_identify_xpak_vendor(struct ixgb_hw *hw)
187{
188 u32 i;
189 u16 vendor_name[5];
190 ixgb_xpak_vendor xpak_vendor;
191
192 ENTER();
193
194 /* Read the first few bytes of the vendor string from the XPAK NVR
195 * registers. These are standard XENPAK/XPAK registers, so all XPAK
196 * devices should implement them. */
197 for (i = 0; i < 5; i++) {
198 vendor_name[i] = ixgb_read_phy_reg(hw,
199 MDIO_PMA_PMD_XPAK_VENDOR_NAME
200 + i, IXGB_PHY_ADDRESS,
201 MDIO_MMD_PMAPMD);
202 }
203
204 /* Determine the actual vendor */
205 if (vendor_name[0] == 'I' &&
206 vendor_name[1] == 'N' &&
207 vendor_name[2] == 'T' &&
208 vendor_name[3] == 'E' && vendor_name[4] == 'L') {
209 xpak_vendor = ixgb_xpak_vendor_intel;
210 } else {
211 xpak_vendor = ixgb_xpak_vendor_infineon;
212 }
213
214 return xpak_vendor;
215}
216
217/******************************************************************************
218 * Determine the physical layer module on the adapter.
219 *
220 * hw - Struct containing variables accessed by shared code. The device_id
221 * field must be (correctly) populated before calling this routine.
222 *
223 * Returns: the phy type of the adapter.
224 *****************************************************************************/
225static ixgb_phy_type
226ixgb_identify_phy(struct ixgb_hw *hw)
227{
228 ixgb_phy_type phy_type;
229 ixgb_xpak_vendor xpak_vendor;
230
231 ENTER();
232
233 /* Infer the transceiver/phy type from the device id */
234 switch (hw->device_id) {
235 case IXGB_DEVICE_ID_82597EX:
236 pr_debug("Identified TXN17401 optics\n");
237 phy_type = ixgb_phy_type_txn17401;
238 break;
239
240 case IXGB_DEVICE_ID_82597EX_SR:
241 /* The SR adapters carry two different types of XPAK optics
242 * modules; read the vendor identifier to determine the exact
243 * type of optics. */
244 xpak_vendor = ixgb_identify_xpak_vendor(hw);
245 if (xpak_vendor == ixgb_xpak_vendor_intel) {
246 pr_debug("Identified TXN17201 optics\n");
247 phy_type = ixgb_phy_type_txn17201;
248 } else {
249 pr_debug("Identified G6005 optics\n");
250 phy_type = ixgb_phy_type_g6005;
251 }
252 break;
253 case IXGB_DEVICE_ID_82597EX_LR:
254 pr_debug("Identified G6104 optics\n");
255 phy_type = ixgb_phy_type_g6104;
256 break;
257 case IXGB_DEVICE_ID_82597EX_CX4:
258 pr_debug("Identified CX4\n");
259 xpak_vendor = ixgb_identify_xpak_vendor(hw);
260 if (xpak_vendor == ixgb_xpak_vendor_intel) {
261 pr_debug("Identified TXN17201 optics\n");
262 phy_type = ixgb_phy_type_txn17201;
263 } else {
264 pr_debug("Identified G6005 optics\n");
265 phy_type = ixgb_phy_type_g6005;
266 }
267 break;
268 default:
269 pr_debug("Unknown physical layer module\n");
270 phy_type = ixgb_phy_type_unknown;
271 break;
272 }
273
274 /* update phy type for sun specific board */
275 if (hw->subsystem_vendor_id == PCI_VENDOR_ID_SUN)
276 phy_type = ixgb_phy_type_bcm;
277
278 return phy_type;
279}
280
281/******************************************************************************
282 * Performs basic configuration of the adapter.
283 *
284 * hw - Struct containing variables accessed by shared code
285 *
286 * Resets the controller.
287 * Reads and validates the EEPROM.
288 * Initializes the receive address registers.
289 * Initializes the multicast table.
290 * Clears all on-chip counters.
291 * Calls routine to setup flow control settings.
292 * Leaves the transmit and receive units disabled and uninitialized.
293 *
294 * Returns:
295 * true if successful,
296 * false if unrecoverable problems were encountered.
297 *****************************************************************************/
298bool
299ixgb_init_hw(struct ixgb_hw *hw)
300{
301 u32 i;
302 u32 ctrl_reg;
303 bool status;
304
305 ENTER();
306
307 /* Issue a global reset to the MAC. This will reset the chip's
308 * transmit, receive, DMA, and link units. It will not effect
309 * the current PCI configuration. The global reset bit is self-
310 * clearing, and should clear within a microsecond.
311 */
312 pr_debug("Issuing a global reset to MAC\n");
313
314 ctrl_reg = ixgb_mac_reset(hw);
315
316 pr_debug("Issuing an EE reset to MAC\n");
317#ifdef HP_ZX1
318 /* Workaround for 82597EX reset errata */
319 IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST);
320#else
321 IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST);
322#endif
323
324 /* Delay a few ms just to allow the reset to complete */
325 msleep(IXGB_DELAY_AFTER_EE_RESET);
326
327 if (!ixgb_get_eeprom_data(hw))
328 return false;
329
330 /* Use the device id to determine the type of phy/transceiver. */
331 hw->device_id = ixgb_get_ee_device_id(hw);
332 hw->phy_type = ixgb_identify_phy(hw);
333
334 /* Setup the receive addresses.
335 * Receive Address Registers (RARs 0 - 15).
336 */
337 ixgb_init_rx_addrs(hw);
338
339 /*
340 * Check that a valid MAC address has been set.
341 * If it is not valid, we fail hardware init.
342 */
343 if (!mac_addr_valid(hw->curr_mac_addr)) {
344 pr_debug("MAC address invalid after ixgb_init_rx_addrs\n");
345 return(false);
346 }
347
348 /* tell the routines in this file they can access hardware again */
349 hw->adapter_stopped = false;
350
351 /* Fill in the bus_info structure */
352 ixgb_get_bus_info(hw);
353
354 /* Zero out the Multicast HASH table */
355 pr_debug("Zeroing the MTA\n");
356 for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
357 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
358
359 /* Zero out the VLAN Filter Table Array */
360 ixgb_clear_vfta(hw);
361
362 /* Zero all of the hardware counters */
363 ixgb_clear_hw_cntrs(hw);
364
365 /* Call a subroutine to setup flow control. */
366 status = ixgb_setup_fc(hw);
367
368 /* 82597EX errata: Call check-for-link in case lane deskew is locked */
369 ixgb_check_for_link(hw);
370
371 return status;
372}
373
374/******************************************************************************
375 * Initializes receive address filters.
376 *
377 * hw - Struct containing variables accessed by shared code
378 *
379 * Places the MAC address in receive address register 0 and clears the rest
380 * of the receive address registers. Clears the multicast table. Assumes
381 * the receiver is in reset when the routine is called.
382 *****************************************************************************/
383static void
384ixgb_init_rx_addrs(struct ixgb_hw *hw)
385{
386 u32 i;
387
388 ENTER();
389
390 /*
391 * If the current mac address is valid, assume it is a software override
392 * to the permanent address.
393 * Otherwise, use the permanent address from the eeprom.
394 */
395 if (!mac_addr_valid(hw->curr_mac_addr)) {
396
397 /* Get the MAC address from the eeprom for later reference */
398 ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr);
399
400 pr_debug("Keeping Permanent MAC Addr = %pM\n",
401 hw->curr_mac_addr);
402 } else {
403
404 /* Setup the receive address. */
405 pr_debug("Overriding MAC Address in RAR[0]\n");
406 pr_debug("New MAC Addr = %pM\n", hw->curr_mac_addr);
407
408 ixgb_rar_set(hw, hw->curr_mac_addr, 0);
409 }
410
411 /* Zero out the other 15 receive addresses. */
412 pr_debug("Clearing RAR[1-15]\n");
413 for (i = 1; i < IXGB_RAR_ENTRIES; i++) {
414 /* Write high reg first to disable the AV bit first */
415 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
416 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
417 }
418}
419
420/******************************************************************************
421 * Updates the MAC's list of multicast addresses.
422 *
423 * hw - Struct containing variables accessed by shared code
424 * mc_addr_list - the list of new multicast addresses
425 * mc_addr_count - number of addresses
426 * pad - number of bytes between addresses in the list
427 *
428 * The given list replaces any existing list. Clears the last 15 receive
429 * address registers and the multicast table. Uses receive address registers
430 * for the first 15 multicast addresses, and hashes the rest into the
431 * multicast table.
432 *****************************************************************************/
433void
434ixgb_mc_addr_list_update(struct ixgb_hw *hw,
435 u8 *mc_addr_list,
436 u32 mc_addr_count,
437 u32 pad)
438{
439 u32 hash_value;
440 u32 i;
441 u32 rar_used_count = 1; /* RAR[0] is used for our MAC address */
442 u8 *mca;
443
444 ENTER();
445
446 /* Set the new number of MC addresses that we are being requested to use. */
447 hw->num_mc_addrs = mc_addr_count;
448
449 /* Clear RAR[1-15] */
450 pr_debug("Clearing RAR[1-15]\n");
451 for (i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
452 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
453 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
454 }
455
456 /* Clear the MTA */
457 pr_debug("Clearing MTA\n");
458 for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
459 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
460
461 /* Add the new addresses */
462 mca = mc_addr_list;
463 for (i = 0; i < mc_addr_count; i++) {
464 pr_debug("Adding the multicast addresses:\n");
465 pr_debug("MC Addr #%d = %pM\n", i, mca);
466
467 /* Place this multicast address in the RAR if there is room, *
468 * else put it in the MTA
469 */
470 if (rar_used_count < IXGB_RAR_ENTRIES) {
471 ixgb_rar_set(hw, mca, rar_used_count);
472 pr_debug("Added a multicast address to RAR[%d]\n", i);
473 rar_used_count++;
474 } else {
475 hash_value = ixgb_hash_mc_addr(hw, mca);
476
477 pr_debug("Hash value = 0x%03X\n", hash_value);
478
479 ixgb_mta_set(hw, hash_value);
480 }
481
482 mca += ETH_ALEN + pad;
483 }
484
485 pr_debug("MC Update Complete\n");
486}
487
488/******************************************************************************
489 * Hashes an address to determine its location in the multicast table
490 *
491 * hw - Struct containing variables accessed by shared code
492 * mc_addr - the multicast address to hash
493 *
494 * Returns:
495 * The hash value
496 *****************************************************************************/
497static u32
498ixgb_hash_mc_addr(struct ixgb_hw *hw,
499 u8 *mc_addr)
500{
501 u32 hash_value = 0;
502
503 ENTER();
504
505 /* The portion of the address that is used for the hash table is
506 * determined by the mc_filter_type setting.
507 */
508 switch (hw->mc_filter_type) {
509 /* [0] [1] [2] [3] [4] [5]
510 * 01 AA 00 12 34 56
511 * LSB MSB - According to H/W docs */
512 case 0:
513 /* [47:36] i.e. 0x563 for above example address */
514 hash_value =
515 ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
516 break;
517 case 1: /* [46:35] i.e. 0xAC6 for above example address */
518 hash_value =
519 ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
520 break;
521 case 2: /* [45:34] i.e. 0x5D8 for above example address */
522 hash_value =
523 ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
524 break;
525 case 3: /* [43:32] i.e. 0x634 for above example address */
526 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
527 break;
528 default:
529 /* Invalid mc_filter_type, what should we do? */
530 pr_debug("MC filter type param set incorrectly\n");
531 ASSERT(0);
532 break;
533 }
534
535 hash_value &= 0xFFF;
536 return hash_value;
537}
538
539/******************************************************************************
540 * Sets the bit in the multicast table corresponding to the hash value.
541 *
542 * hw - Struct containing variables accessed by shared code
543 * hash_value - Multicast address hash value
544 *****************************************************************************/
545static void
546ixgb_mta_set(struct ixgb_hw *hw,
547 u32 hash_value)
548{
549 u32 hash_bit, hash_reg;
550 u32 mta_reg;
551
552 /* The MTA is a register array of 128 32-bit registers.
553 * It is treated like an array of 4096 bits. We want to set
554 * bit BitArray[hash_value]. So we figure out what register
555 * the bit is in, read it, OR in the new bit, then write
556 * back the new value. The register is determined by the
557 * upper 7 bits of the hash value and the bit within that
558 * register are determined by the lower 5 bits of the value.
559 */
560 hash_reg = (hash_value >> 5) & 0x7F;
561 hash_bit = hash_value & 0x1F;
562
563 mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg);
564
565 mta_reg |= (1 << hash_bit);
566
567 IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg);
568}
569
570/******************************************************************************
571 * Puts an ethernet address into a receive address register.
572 *
573 * hw - Struct containing variables accessed by shared code
574 * addr - Address to put into receive address register
575 * index - Receive address register to write
576 *****************************************************************************/
577void
578ixgb_rar_set(struct ixgb_hw *hw,
579 u8 *addr,
580 u32 index)
581{
582 u32 rar_low, rar_high;
583
584 ENTER();
585
586 /* HW expects these in little endian so we reverse the byte order
587 * from network order (big endian) to little endian
588 */
589 rar_low = ((u32) addr[0] |
590 ((u32)addr[1] << 8) |
591 ((u32)addr[2] << 16) |
592 ((u32)addr[3] << 24));
593
594 rar_high = ((u32) addr[4] |
595 ((u32)addr[5] << 8) |
596 IXGB_RAH_AV);
597
598 IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
599 IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
600}
601
602/******************************************************************************
603 * Writes a value to the specified offset in the VLAN filter table.
604 *
605 * hw - Struct containing variables accessed by shared code
606 * offset - Offset in VLAN filer table to write
607 * value - Value to write into VLAN filter table
608 *****************************************************************************/
609void
610ixgb_write_vfta(struct ixgb_hw *hw,
611 u32 offset,
612 u32 value)
613{
614 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
615}
616
617/******************************************************************************
618 * Clears the VLAN filer table
619 *
620 * hw - Struct containing variables accessed by shared code
621 *****************************************************************************/
622static void
623ixgb_clear_vfta(struct ixgb_hw *hw)
624{
625 u32 offset;
626
627 for (offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
628 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
629}
630
631/******************************************************************************
632 * Configures the flow control settings based on SW configuration.
633 *
634 * hw - Struct containing variables accessed by shared code
635 *****************************************************************************/
636
637static bool
638ixgb_setup_fc(struct ixgb_hw *hw)
639{
640 u32 ctrl_reg;
641 u32 pap_reg = 0; /* by default, assume no pause time */
642 bool status = true;
643
644 ENTER();
645
646 /* Get the current control reg 0 settings */
647 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
648
649 /* Clear the Receive Pause Enable and Transmit Pause Enable bits */
650 ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
651
652 /* The possible values of the "flow_control" parameter are:
653 * 0: Flow control is completely disabled
654 * 1: Rx flow control is enabled (we can receive pause frames
655 * but not send pause frames).
656 * 2: Tx flow control is enabled (we can send pause frames
657 * but we do not support receiving pause frames).
658 * 3: Both Rx and TX flow control (symmetric) are enabled.
659 * other: Invalid.
660 */
661 switch (hw->fc.type) {
662 case ixgb_fc_none: /* 0 */
663 /* Set CMDC bit to disable Rx Flow control */
664 ctrl_reg |= (IXGB_CTRL0_CMDC);
665 break;
666 case ixgb_fc_rx_pause: /* 1 */
667 /* RX Flow control is enabled, and TX Flow control is
668 * disabled.
669 */
670 ctrl_reg |= (IXGB_CTRL0_RPE);
671 break;
672 case ixgb_fc_tx_pause: /* 2 */
673 /* TX Flow control is enabled, and RX Flow control is
674 * disabled, by a software over-ride.
675 */
676 ctrl_reg |= (IXGB_CTRL0_TPE);
677 pap_reg = hw->fc.pause_time;
678 break;
679 case ixgb_fc_full: /* 3 */
680 /* Flow control (both RX and TX) is enabled by a software
681 * over-ride.
682 */
683 ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
684 pap_reg = hw->fc.pause_time;
685 break;
686 default:
687 /* We should never get here. The value should be 0-3. */
688 pr_debug("Flow control param set incorrectly\n");
689 ASSERT(0);
690 break;
691 }
692
693 /* Write the new settings */
694 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
695
696 if (pap_reg != 0)
697 IXGB_WRITE_REG(hw, PAP, pap_reg);
698
699 /* Set the flow control receive threshold registers. Normally,
700 * these registers will be set to a default threshold that may be
701 * adjusted later by the driver's runtime code. However, if the
702 * ability to transmit pause frames in not enabled, then these
703 * registers will be set to 0.
704 */
705 if (!(hw->fc.type & ixgb_fc_tx_pause)) {
706 IXGB_WRITE_REG(hw, FCRTL, 0);
707 IXGB_WRITE_REG(hw, FCRTH, 0);
708 } else {
709 /* We need to set up the Receive Threshold high and low water
710 * marks as well as (optionally) enabling the transmission of XON
711 * frames. */
712 if (hw->fc.send_xon) {
713 IXGB_WRITE_REG(hw, FCRTL,
714 (hw->fc.low_water | IXGB_FCRTL_XONE));
715 } else {
716 IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water);
717 }
718 IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water);
719 }
720 return status;
721}
722
723/******************************************************************************
724 * Reads a word from a device over the Management Data Interface (MDI) bus.
725 * This interface is used to manage Physical layer devices.
726 *
727 * hw - Struct containing variables accessed by hw code
728 * reg_address - Offset of device register being read.
729 * phy_address - Address of device on MDI.
730 *
731 * Returns: Data word (16 bits) from MDI device.
732 *
733 * The 82597EX has support for several MDI access methods. This routine
734 * uses the new protocol MDI Single Command and Address Operation.
735 * This requires that first an address cycle command is sent, followed by a
736 * read command.
737 *****************************************************************************/
738static u16
739ixgb_read_phy_reg(struct ixgb_hw *hw,
740 u32 reg_address,
741 u32 phy_address,
742 u32 device_type)
743{
744 u32 i;
745 u32 data;
746 u32 command = 0;
747
748 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
749 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
750 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
751
752 /* Setup and write the address cycle command */
753 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
754 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
755 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
756 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
757
758 IXGB_WRITE_REG(hw, MSCA, command);
759
760 /**************************************************************
761 ** Check every 10 usec to see if the address cycle completed
762 ** The COMMAND bit will clear when the operation is complete.
763 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
764 ** from the CPU Write to the Ready bit assertion.
765 **************************************************************/
766
767 for (i = 0; i < 10; i++)
768 {
769 udelay(10);
770
771 command = IXGB_READ_REG(hw, MSCA);
772
773 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
774 break;
775 }
776
777 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
778
779 /* Address cycle complete, setup and write the read command */
780 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
781 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
782 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
783 (IXGB_MSCA_READ | IXGB_MSCA_MDI_COMMAND));
784
785 IXGB_WRITE_REG(hw, MSCA, command);
786
787 /**************************************************************
788 ** Check every 10 usec to see if the read command completed
789 ** The COMMAND bit will clear when the operation is complete.
790 ** The read may take as long as 64 usecs (we'll wait 100 usecs max)
791 ** from the CPU Write to the Ready bit assertion.
792 **************************************************************/
793
794 for (i = 0; i < 10; i++)
795 {
796 udelay(10);
797
798 command = IXGB_READ_REG(hw, MSCA);
799
800 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
801 break;
802 }
803
804 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
805
806 /* Operation is complete, get the data from the MDIO Read/Write Data
807 * register and return.
808 */
809 data = IXGB_READ_REG(hw, MSRWD);
810 data >>= IXGB_MSRWD_READ_DATA_SHIFT;
811 return((u16) data);
812}
813
814/******************************************************************************
815 * Writes a word to a device over the Management Data Interface (MDI) bus.
816 * This interface is used to manage Physical layer devices.
817 *
818 * hw - Struct containing variables accessed by hw code
819 * reg_address - Offset of device register being read.
820 * phy_address - Address of device on MDI.
821 * device_type - Also known as the Device ID or DID.
822 * data - 16-bit value to be written
823 *
824 * Returns: void.
825 *
826 * The 82597EX has support for several MDI access methods. This routine
827 * uses the new protocol MDI Single Command and Address Operation.
828 * This requires that first an address cycle command is sent, followed by a
829 * write command.
830 *****************************************************************************/
831static void
832ixgb_write_phy_reg(struct ixgb_hw *hw,
833 u32 reg_address,
834 u32 phy_address,
835 u32 device_type,
836 u16 data)
837{
838 u32 i;
839 u32 command = 0;
840
841 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
842 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
843 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
844
845 /* Put the data in the MDIO Read/Write Data register */
846 IXGB_WRITE_REG(hw, MSRWD, (u32)data);
847
848 /* Setup and write the address cycle command */
849 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
850 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
851 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
852 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
853
854 IXGB_WRITE_REG(hw, MSCA, command);
855
856 /**************************************************************
857 ** Check every 10 usec to see if the address cycle completed
858 ** The COMMAND bit will clear when the operation is complete.
859 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
860 ** from the CPU Write to the Ready bit assertion.
861 **************************************************************/
862
863 for (i = 0; i < 10; i++)
864 {
865 udelay(10);
866
867 command = IXGB_READ_REG(hw, MSCA);
868
869 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
870 break;
871 }
872
873 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
874
875 /* Address cycle complete, setup and write the write command */
876 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
877 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
878 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
879 (IXGB_MSCA_WRITE | IXGB_MSCA_MDI_COMMAND));
880
881 IXGB_WRITE_REG(hw, MSCA, command);
882
883 /**************************************************************
884 ** Check every 10 usec to see if the read command completed
885 ** The COMMAND bit will clear when the operation is complete.
886 ** The write may take as long as 64 usecs (we'll wait 100 usecs max)
887 ** from the CPU Write to the Ready bit assertion.
888 **************************************************************/
889
890 for (i = 0; i < 10; i++)
891 {
892 udelay(10);
893
894 command = IXGB_READ_REG(hw, MSCA);
895
896 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
897 break;
898 }
899
900 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
901
902 /* Operation is complete, return. */
903}
904
905/******************************************************************************
906 * Checks to see if the link status of the hardware has changed.
907 *
908 * hw - Struct containing variables accessed by hw code
909 *
910 * Called by any function that needs to check the link status of the adapter.
911 *****************************************************************************/
912void
913ixgb_check_for_link(struct ixgb_hw *hw)
914{
915 u32 status_reg;
916 u32 xpcss_reg;
917
918 ENTER();
919
920 xpcss_reg = IXGB_READ_REG(hw, XPCSS);
921 status_reg = IXGB_READ_REG(hw, STATUS);
922
923 if ((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
924 (status_reg & IXGB_STATUS_LU)) {
925 hw->link_up = true;
926 } else if (!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
927 (status_reg & IXGB_STATUS_LU)) {
928 pr_debug("XPCSS Not Aligned while Status:LU is set\n");
929 hw->link_up = ixgb_link_reset(hw);
930 } else {
931 /*
932 * 82597EX errata. Since the lane deskew problem may prevent
933 * link, reset the link before reporting link down.
934 */
935 hw->link_up = ixgb_link_reset(hw);
936 }
937 /* Anything else for 10 Gig?? */
938}
939
940/******************************************************************************
941 * Check for a bad link condition that may have occurred.
942 * The indication is that the RFC / LFC registers may be incrementing
943 * continually. A full adapter reset is required to recover.
944 *
945 * hw - Struct containing variables accessed by hw code
946 *
947 * Called by any function that needs to check the link status of the adapter.
948 *****************************************************************************/
949bool ixgb_check_for_bad_link(struct ixgb_hw *hw)
950{
951 u32 newLFC, newRFC;
952 bool bad_link_returncode = false;
953
954 if (hw->phy_type == ixgb_phy_type_txn17401) {
955 newLFC = IXGB_READ_REG(hw, LFC);
956 newRFC = IXGB_READ_REG(hw, RFC);
957 if ((hw->lastLFC + 250 < newLFC)
958 || (hw->lastRFC + 250 < newRFC)) {
959 pr_debug("BAD LINK! too many LFC/RFC since last check\n");
960 bad_link_returncode = true;
961 }
962 hw->lastLFC = newLFC;
963 hw->lastRFC = newRFC;
964 }
965
966 return bad_link_returncode;
967}
968
969/******************************************************************************
970 * Clears all hardware statistics counters.
971 *
972 * hw - Struct containing variables accessed by shared code
973 *****************************************************************************/
974static void
975ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
976{
977 volatile u32 temp_reg;
978
979 ENTER();
980
981 /* if we are stopped or resetting exit gracefully */
982 if (hw->adapter_stopped) {
983 pr_debug("Exiting because the adapter is stopped!!!\n");
984 return;
985 }
986
987 temp_reg = IXGB_READ_REG(hw, TPRL);
988 temp_reg = IXGB_READ_REG(hw, TPRH);
989 temp_reg = IXGB_READ_REG(hw, GPRCL);
990 temp_reg = IXGB_READ_REG(hw, GPRCH);
991 temp_reg = IXGB_READ_REG(hw, BPRCL);
992 temp_reg = IXGB_READ_REG(hw, BPRCH);
993 temp_reg = IXGB_READ_REG(hw, MPRCL);
994 temp_reg = IXGB_READ_REG(hw, MPRCH);
995 temp_reg = IXGB_READ_REG(hw, UPRCL);
996 temp_reg = IXGB_READ_REG(hw, UPRCH);
997 temp_reg = IXGB_READ_REG(hw, VPRCL);
998 temp_reg = IXGB_READ_REG(hw, VPRCH);
999 temp_reg = IXGB_READ_REG(hw, JPRCL);
1000 temp_reg = IXGB_READ_REG(hw, JPRCH);
1001 temp_reg = IXGB_READ_REG(hw, GORCL);
1002 temp_reg = IXGB_READ_REG(hw, GORCH);
1003 temp_reg = IXGB_READ_REG(hw, TORL);
1004 temp_reg = IXGB_READ_REG(hw, TORH);
1005 temp_reg = IXGB_READ_REG(hw, RNBC);
1006 temp_reg = IXGB_READ_REG(hw, RUC);
1007 temp_reg = IXGB_READ_REG(hw, ROC);
1008 temp_reg = IXGB_READ_REG(hw, RLEC);
1009 temp_reg = IXGB_READ_REG(hw, CRCERRS);
1010 temp_reg = IXGB_READ_REG(hw, ICBC);
1011 temp_reg = IXGB_READ_REG(hw, ECBC);
1012 temp_reg = IXGB_READ_REG(hw, MPC);
1013 temp_reg = IXGB_READ_REG(hw, TPTL);
1014 temp_reg = IXGB_READ_REG(hw, TPTH);
1015 temp_reg = IXGB_READ_REG(hw, GPTCL);
1016 temp_reg = IXGB_READ_REG(hw, GPTCH);
1017 temp_reg = IXGB_READ_REG(hw, BPTCL);
1018 temp_reg = IXGB_READ_REG(hw, BPTCH);
1019 temp_reg = IXGB_READ_REG(hw, MPTCL);
1020 temp_reg = IXGB_READ_REG(hw, MPTCH);
1021 temp_reg = IXGB_READ_REG(hw, UPTCL);
1022 temp_reg = IXGB_READ_REG(hw, UPTCH);
1023 temp_reg = IXGB_READ_REG(hw, VPTCL);
1024 temp_reg = IXGB_READ_REG(hw, VPTCH);
1025 temp_reg = IXGB_READ_REG(hw, JPTCL);
1026 temp_reg = IXGB_READ_REG(hw, JPTCH);
1027 temp_reg = IXGB_READ_REG(hw, GOTCL);
1028 temp_reg = IXGB_READ_REG(hw, GOTCH);
1029 temp_reg = IXGB_READ_REG(hw, TOTL);
1030 temp_reg = IXGB_READ_REG(hw, TOTH);
1031 temp_reg = IXGB_READ_REG(hw, DC);
1032 temp_reg = IXGB_READ_REG(hw, PLT64C);
1033 temp_reg = IXGB_READ_REG(hw, TSCTC);
1034 temp_reg = IXGB_READ_REG(hw, TSCTFC);
1035 temp_reg = IXGB_READ_REG(hw, IBIC);
1036 temp_reg = IXGB_READ_REG(hw, RFC);
1037 temp_reg = IXGB_READ_REG(hw, LFC);
1038 temp_reg = IXGB_READ_REG(hw, PFRC);
1039 temp_reg = IXGB_READ_REG(hw, PFTC);
1040 temp_reg = IXGB_READ_REG(hw, MCFRC);
1041 temp_reg = IXGB_READ_REG(hw, MCFTC);
1042 temp_reg = IXGB_READ_REG(hw, XONRXC);
1043 temp_reg = IXGB_READ_REG(hw, XONTXC);
1044 temp_reg = IXGB_READ_REG(hw, XOFFRXC);
1045 temp_reg = IXGB_READ_REG(hw, XOFFTXC);
1046 temp_reg = IXGB_READ_REG(hw, RJC);
1047}
1048
1049/******************************************************************************
1050 * Turns on the software controllable LED
1051 *
1052 * hw - Struct containing variables accessed by shared code
1053 *****************************************************************************/
1054void
1055ixgb_led_on(struct ixgb_hw *hw)
1056{
1057 u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1058
1059 /* To turn on the LED, clear software-definable pin 0 (SDP0). */
1060 ctrl0_reg &= ~IXGB_CTRL0_SDP0;
1061 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1062}
1063
1064/******************************************************************************
1065 * Turns off the software controllable LED
1066 *
1067 * hw - Struct containing variables accessed by shared code
1068 *****************************************************************************/
1069void
1070ixgb_led_off(struct ixgb_hw *hw)
1071{
1072 u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1073
1074 /* To turn off the LED, set software-definable pin 0 (SDP0). */
1075 ctrl0_reg |= IXGB_CTRL0_SDP0;
1076 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1077}
1078
1079/******************************************************************************
1080 * Gets the current PCI bus type, speed, and width of the hardware
1081 *
1082 * hw - Struct containing variables accessed by shared code
1083 *****************************************************************************/
1084static void
1085ixgb_get_bus_info(struct ixgb_hw *hw)
1086{
1087 u32 status_reg;
1088
1089 status_reg = IXGB_READ_REG(hw, STATUS);
1090
1091 hw->bus.type = (status_reg & IXGB_STATUS_PCIX_MODE) ?
1092 ixgb_bus_type_pcix : ixgb_bus_type_pci;
1093
1094 if (hw->bus.type == ixgb_bus_type_pci) {
1095 hw->bus.speed = (status_reg & IXGB_STATUS_PCI_SPD) ?
1096 ixgb_bus_speed_66 : ixgb_bus_speed_33;
1097 } else {
1098 switch (status_reg & IXGB_STATUS_PCIX_SPD_MASK) {
1099 case IXGB_STATUS_PCIX_SPD_66:
1100 hw->bus.speed = ixgb_bus_speed_66;
1101 break;
1102 case IXGB_STATUS_PCIX_SPD_100:
1103 hw->bus.speed = ixgb_bus_speed_100;
1104 break;
1105 case IXGB_STATUS_PCIX_SPD_133:
1106 hw->bus.speed = ixgb_bus_speed_133;
1107 break;
1108 default:
1109 hw->bus.speed = ixgb_bus_speed_reserved;
1110 break;
1111 }
1112 }
1113
1114 hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ?
1115 ixgb_bus_width_64 : ixgb_bus_width_32;
1116}
1117
1118/******************************************************************************
1119 * Tests a MAC address to ensure it is a valid Individual Address
1120 *
1121 * mac_addr - pointer to MAC address.
1122 *
1123 *****************************************************************************/
1124static bool
1125mac_addr_valid(u8 *mac_addr)
1126{
1127 bool is_valid = true;
1128 ENTER();
1129
1130 /* Make sure it is not a multicast address */
1131 if (is_multicast_ether_addr(mac_addr)) {
1132 pr_debug("MAC address is multicast\n");
1133 is_valid = false;
1134 }
1135 /* Not a broadcast address */
1136 else if (is_broadcast_ether_addr(mac_addr)) {
1137 pr_debug("MAC address is broadcast\n");
1138 is_valid = false;
1139 }
1140 /* Reject the zero address */
1141 else if (is_zero_ether_addr(mac_addr)) {
1142 pr_debug("MAC address is all zeros\n");
1143 is_valid = false;
1144 }
1145 return is_valid;
1146}
1147
1148/******************************************************************************
1149 * Resets the 10GbE link. Waits the settle time and returns the state of
1150 * the link.
1151 *
1152 * hw - Struct containing variables accessed by shared code
1153 *****************************************************************************/
1154static bool
1155ixgb_link_reset(struct ixgb_hw *hw)
1156{
1157 bool link_status = false;
1158 u8 wait_retries = MAX_RESET_ITERATIONS;
1159 u8 lrst_retries = MAX_RESET_ITERATIONS;
1160
1161 do {
1162 /* Reset the link */
1163 IXGB_WRITE_REG(hw, CTRL0,
1164 IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST);
1165
1166 /* Wait for link-up and lane re-alignment */
1167 do {
1168 udelay(IXGB_DELAY_USECS_AFTER_LINK_RESET);
1169 link_status =
1170 ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU)
1171 && (IXGB_READ_REG(hw, XPCSS) &
1172 IXGB_XPCSS_ALIGN_STATUS)) ? true : false;
1173 } while (!link_status && --wait_retries);
1174
1175 } while (!link_status && --lrst_retries);
1176
1177 return link_status;
1178}
1179
1180/******************************************************************************
1181 * Resets the 10GbE optics module.
1182 *
1183 * hw - Struct containing variables accessed by shared code
1184 *****************************************************************************/
1185static void
1186ixgb_optics_reset(struct ixgb_hw *hw)
1187{
1188 if (hw->phy_type == ixgb_phy_type_txn17401) {
1189 u16 mdio_reg;
1190
1191 ixgb_write_phy_reg(hw,
1192 MDIO_CTRL1,
1193 IXGB_PHY_ADDRESS,
1194 MDIO_MMD_PMAPMD,
1195 MDIO_CTRL1_RESET);
1196
1197 mdio_reg = ixgb_read_phy_reg(hw,
1198 MDIO_CTRL1,
1199 IXGB_PHY_ADDRESS,
1200 MDIO_MMD_PMAPMD);
1201 }
1202}
1203
1204/******************************************************************************
1205 * Resets the 10GbE optics module for Sun variant NIC.
1206 *
1207 * hw - Struct containing variables accessed by shared code
1208 *****************************************************************************/
1209
1210#define IXGB_BCM8704_USER_PMD_TX_CTRL_REG 0xC803
1211#define IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL 0x0164
1212#define IXGB_BCM8704_USER_CTRL_REG 0xC800
1213#define IXGB_BCM8704_USER_CTRL_REG_VAL 0x7FBF
1214#define IXGB_BCM8704_USER_DEV3_ADDR 0x0003
1215#define IXGB_SUN_PHY_ADDRESS 0x0000
1216#define IXGB_SUN_PHY_RESET_DELAY 305
1217
1218static void
1219ixgb_optics_reset_bcm(struct ixgb_hw *hw)
1220{
1221 u32 ctrl = IXGB_READ_REG(hw, CTRL0);
1222 ctrl &= ~IXGB_CTRL0_SDP2;
1223 ctrl |= IXGB_CTRL0_SDP3;
1224 IXGB_WRITE_REG(hw, CTRL0, ctrl);
1225 IXGB_WRITE_FLUSH(hw);
1226
1227 /* SerDes needs extra delay */
1228 msleep(IXGB_SUN_PHY_RESET_DELAY);
1229
1230 /* Broadcom 7408L configuration */
1231 /* Reference clock config */
1232 ixgb_write_phy_reg(hw,
1233 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1234 IXGB_SUN_PHY_ADDRESS,
1235 IXGB_BCM8704_USER_DEV3_ADDR,
1236 IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL);
1237 /* we must read the registers twice */
1238 ixgb_read_phy_reg(hw,
1239 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1240 IXGB_SUN_PHY_ADDRESS,
1241 IXGB_BCM8704_USER_DEV3_ADDR);
1242 ixgb_read_phy_reg(hw,
1243 IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1244 IXGB_SUN_PHY_ADDRESS,
1245 IXGB_BCM8704_USER_DEV3_ADDR);
1246
1247 ixgb_write_phy_reg(hw,
1248 IXGB_BCM8704_USER_CTRL_REG,
1249 IXGB_SUN_PHY_ADDRESS,
1250 IXGB_BCM8704_USER_DEV3_ADDR,
1251 IXGB_BCM8704_USER_CTRL_REG_VAL);
1252 ixgb_read_phy_reg(hw,
1253 IXGB_BCM8704_USER_CTRL_REG,
1254 IXGB_SUN_PHY_ADDRESS,
1255 IXGB_BCM8704_USER_DEV3_ADDR);
1256 ixgb_read_phy_reg(hw,
1257 IXGB_BCM8704_USER_CTRL_REG,
1258 IXGB_SUN_PHY_ADDRESS,
1259 IXGB_BCM8704_USER_DEV3_ADDR);
1260
1261 /* SerDes needs extra delay */
1262 msleep(IXGB_SUN_PHY_RESET_DELAY);
1263}