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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2013 - 2021 Intel Corporation. */
3
4#include <linux/avf/virtchnl.h>
5#include <linux/bitfield.h>
6#include <linux/delay.h>
7#include <linux/etherdevice.h>
8#include <linux/pci.h>
9#include "i40e_adminq_cmd.h"
10#include "i40e_devids.h"
11#include "i40e_prototype.h"
12#include "i40e_register.h"
13
14/**
15 * i40e_set_mac_type - Sets MAC type
16 * @hw: pointer to the HW structure
17 *
18 * This function sets the mac type of the adapter based on the
19 * vendor ID and device ID stored in the hw structure.
20 **/
21int i40e_set_mac_type(struct i40e_hw *hw)
22{
23 int status = 0;
24
25 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
26 switch (hw->device_id) {
27 case I40E_DEV_ID_SFP_XL710:
28 case I40E_DEV_ID_QEMU:
29 case I40E_DEV_ID_KX_B:
30 case I40E_DEV_ID_KX_C:
31 case I40E_DEV_ID_QSFP_A:
32 case I40E_DEV_ID_QSFP_B:
33 case I40E_DEV_ID_QSFP_C:
34 case I40E_DEV_ID_1G_BASE_T_BC:
35 case I40E_DEV_ID_5G_BASE_T_BC:
36 case I40E_DEV_ID_10G_BASE_T:
37 case I40E_DEV_ID_10G_BASE_T4:
38 case I40E_DEV_ID_10G_BASE_T_BC:
39 case I40E_DEV_ID_10G_B:
40 case I40E_DEV_ID_10G_SFP:
41 case I40E_DEV_ID_20G_KR2:
42 case I40E_DEV_ID_20G_KR2_A:
43 case I40E_DEV_ID_25G_B:
44 case I40E_DEV_ID_25G_SFP28:
45 case I40E_DEV_ID_X710_N3000:
46 case I40E_DEV_ID_XXV710_N3000:
47 hw->mac.type = I40E_MAC_XL710;
48 break;
49 case I40E_DEV_ID_KX_X722:
50 case I40E_DEV_ID_QSFP_X722:
51 case I40E_DEV_ID_SFP_X722:
52 case I40E_DEV_ID_1G_BASE_T_X722:
53 case I40E_DEV_ID_10G_BASE_T_X722:
54 case I40E_DEV_ID_SFP_I_X722:
55 case I40E_DEV_ID_SFP_X722_A:
56 hw->mac.type = I40E_MAC_X722;
57 break;
58 default:
59 hw->mac.type = I40E_MAC_GENERIC;
60 break;
61 }
62 } else {
63 status = -ENODEV;
64 }
65
66 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
67 hw->mac.type, status);
68 return status;
69}
70
71/**
72 * i40e_aq_str - convert AQ err code to a string
73 * @hw: pointer to the HW structure
74 * @aq_err: the AQ error code to convert
75 **/
76const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
77{
78 switch (aq_err) {
79 case I40E_AQ_RC_OK:
80 return "OK";
81 case I40E_AQ_RC_EPERM:
82 return "I40E_AQ_RC_EPERM";
83 case I40E_AQ_RC_ENOENT:
84 return "I40E_AQ_RC_ENOENT";
85 case I40E_AQ_RC_ESRCH:
86 return "I40E_AQ_RC_ESRCH";
87 case I40E_AQ_RC_EINTR:
88 return "I40E_AQ_RC_EINTR";
89 case I40E_AQ_RC_EIO:
90 return "I40E_AQ_RC_EIO";
91 case I40E_AQ_RC_ENXIO:
92 return "I40E_AQ_RC_ENXIO";
93 case I40E_AQ_RC_E2BIG:
94 return "I40E_AQ_RC_E2BIG";
95 case I40E_AQ_RC_EAGAIN:
96 return "I40E_AQ_RC_EAGAIN";
97 case I40E_AQ_RC_ENOMEM:
98 return "I40E_AQ_RC_ENOMEM";
99 case I40E_AQ_RC_EACCES:
100 return "I40E_AQ_RC_EACCES";
101 case I40E_AQ_RC_EFAULT:
102 return "I40E_AQ_RC_EFAULT";
103 case I40E_AQ_RC_EBUSY:
104 return "I40E_AQ_RC_EBUSY";
105 case I40E_AQ_RC_EEXIST:
106 return "I40E_AQ_RC_EEXIST";
107 case I40E_AQ_RC_EINVAL:
108 return "I40E_AQ_RC_EINVAL";
109 case I40E_AQ_RC_ENOTTY:
110 return "I40E_AQ_RC_ENOTTY";
111 case I40E_AQ_RC_ENOSPC:
112 return "I40E_AQ_RC_ENOSPC";
113 case I40E_AQ_RC_ENOSYS:
114 return "I40E_AQ_RC_ENOSYS";
115 case I40E_AQ_RC_ERANGE:
116 return "I40E_AQ_RC_ERANGE";
117 case I40E_AQ_RC_EFLUSHED:
118 return "I40E_AQ_RC_EFLUSHED";
119 case I40E_AQ_RC_BAD_ADDR:
120 return "I40E_AQ_RC_BAD_ADDR";
121 case I40E_AQ_RC_EMODE:
122 return "I40E_AQ_RC_EMODE";
123 case I40E_AQ_RC_EFBIG:
124 return "I40E_AQ_RC_EFBIG";
125 }
126
127 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
128 return hw->err_str;
129}
130
131/**
132 * i40e_debug_aq
133 * @hw: debug mask related to admin queue
134 * @mask: debug mask
135 * @desc: pointer to admin queue descriptor
136 * @buffer: pointer to command buffer
137 * @buf_len: max length of buffer
138 *
139 * Dumps debug log about adminq command with descriptor contents.
140 **/
141void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
142 void *buffer, u16 buf_len)
143{
144 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
145 u32 effective_mask = hw->debug_mask & mask;
146 char prefix[27];
147 u16 len;
148 u8 *buf = (u8 *)buffer;
149
150 if (!effective_mask || !desc)
151 return;
152
153 len = le16_to_cpu(aq_desc->datalen);
154
155 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
156 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
157 le16_to_cpu(aq_desc->opcode),
158 le16_to_cpu(aq_desc->flags),
159 le16_to_cpu(aq_desc->datalen),
160 le16_to_cpu(aq_desc->retval));
161 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
162 "\tcookie (h,l) 0x%08X 0x%08X\n",
163 le32_to_cpu(aq_desc->cookie_high),
164 le32_to_cpu(aq_desc->cookie_low));
165 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
166 "\tparam (0,1) 0x%08X 0x%08X\n",
167 le32_to_cpu(aq_desc->params.internal.param0),
168 le32_to_cpu(aq_desc->params.internal.param1));
169 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
170 "\taddr (h,l) 0x%08X 0x%08X\n",
171 le32_to_cpu(aq_desc->params.external.addr_high),
172 le32_to_cpu(aq_desc->params.external.addr_low));
173
174 if (buffer && buf_len != 0 && len != 0 &&
175 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) {
176 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
177 if (buf_len < len)
178 len = buf_len;
179
180 snprintf(prefix, sizeof(prefix),
181 "i40e %02x:%02x.%x: \t0x",
182 hw->bus.bus_id,
183 hw->bus.device,
184 hw->bus.func);
185
186 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET,
187 16, 1, buf, len, false);
188 }
189}
190
191/**
192 * i40e_check_asq_alive
193 * @hw: pointer to the hw struct
194 *
195 * Returns true if Queue is enabled else false.
196 **/
197bool i40e_check_asq_alive(struct i40e_hw *hw)
198{
199 /* Check if the queue is initialized */
200 if (!hw->aq.asq.count)
201 return false;
202
203 return !!(rd32(hw, I40E_PF_ATQLEN) & I40E_PF_ATQLEN_ATQENABLE_MASK);
204}
205
206/**
207 * i40e_aq_queue_shutdown
208 * @hw: pointer to the hw struct
209 * @unloading: is the driver unloading itself
210 *
211 * Tell the Firmware that we're shutting down the AdminQ and whether
212 * or not the driver is unloading as well.
213 **/
214int i40e_aq_queue_shutdown(struct i40e_hw *hw,
215 bool unloading)
216{
217 struct i40e_aq_desc desc;
218 struct i40e_aqc_queue_shutdown *cmd =
219 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
220 int status;
221
222 i40e_fill_default_direct_cmd_desc(&desc,
223 i40e_aqc_opc_queue_shutdown);
224
225 if (unloading)
226 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
227 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
228
229 return status;
230}
231
232/**
233 * i40e_aq_get_set_rss_lut
234 * @hw: pointer to the hardware structure
235 * @vsi_id: vsi fw index
236 * @pf_lut: for PF table set true, for VSI table set false
237 * @lut: pointer to the lut buffer provided by the caller
238 * @lut_size: size of the lut buffer
239 * @set: set true to set the table, false to get the table
240 *
241 * Internal function to get or set RSS look up table
242 **/
243static int i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
244 u16 vsi_id, bool pf_lut,
245 u8 *lut, u16 lut_size,
246 bool set)
247{
248 struct i40e_aq_desc desc;
249 struct i40e_aqc_get_set_rss_lut *cmd_resp =
250 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
251 int status;
252 u16 flags;
253
254 if (set)
255 i40e_fill_default_direct_cmd_desc(&desc,
256 i40e_aqc_opc_set_rss_lut);
257 else
258 i40e_fill_default_direct_cmd_desc(&desc,
259 i40e_aqc_opc_get_rss_lut);
260
261 /* Indirect command */
262 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
263 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
264
265 vsi_id = FIELD_PREP(I40E_AQC_SET_RSS_LUT_VSI_ID_MASK, vsi_id) |
266 FIELD_PREP(I40E_AQC_SET_RSS_LUT_VSI_VALID, 1);
267 cmd_resp->vsi_id = cpu_to_le16(vsi_id);
268
269 if (pf_lut)
270 flags = FIELD_PREP(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK,
271 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF);
272 else
273 flags = FIELD_PREP(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK,
274 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI);
275
276 cmd_resp->flags = cpu_to_le16(flags);
277 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
278
279 return status;
280}
281
282/**
283 * i40e_aq_get_rss_lut
284 * @hw: pointer to the hardware structure
285 * @vsi_id: vsi fw index
286 * @pf_lut: for PF table set true, for VSI table set false
287 * @lut: pointer to the lut buffer provided by the caller
288 * @lut_size: size of the lut buffer
289 *
290 * get the RSS lookup table, PF or VSI type
291 **/
292int i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
293 bool pf_lut, u8 *lut, u16 lut_size)
294{
295 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
296 false);
297}
298
299/**
300 * i40e_aq_set_rss_lut
301 * @hw: pointer to the hardware structure
302 * @vsi_id: vsi fw index
303 * @pf_lut: for PF table set true, for VSI table set false
304 * @lut: pointer to the lut buffer provided by the caller
305 * @lut_size: size of the lut buffer
306 *
307 * set the RSS lookup table, PF or VSI type
308 **/
309int i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
310 bool pf_lut, u8 *lut, u16 lut_size)
311{
312 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
313}
314
315/**
316 * i40e_aq_get_set_rss_key
317 * @hw: pointer to the hw struct
318 * @vsi_id: vsi fw index
319 * @key: pointer to key info struct
320 * @set: set true to set the key, false to get the key
321 *
322 * get the RSS key per VSI
323 **/
324static int i40e_aq_get_set_rss_key(struct i40e_hw *hw,
325 u16 vsi_id,
326 struct i40e_aqc_get_set_rss_key_data *key,
327 bool set)
328{
329 struct i40e_aq_desc desc;
330 struct i40e_aqc_get_set_rss_key *cmd_resp =
331 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
332 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
333 int status;
334
335 if (set)
336 i40e_fill_default_direct_cmd_desc(&desc,
337 i40e_aqc_opc_set_rss_key);
338 else
339 i40e_fill_default_direct_cmd_desc(&desc,
340 i40e_aqc_opc_get_rss_key);
341
342 /* Indirect command */
343 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
344 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
345
346 vsi_id = FIELD_PREP(I40E_AQC_SET_RSS_KEY_VSI_ID_MASK, vsi_id) |
347 FIELD_PREP(I40E_AQC_SET_RSS_KEY_VSI_VALID, 1);
348 cmd_resp->vsi_id = cpu_to_le16(vsi_id);
349
350 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
351
352 return status;
353}
354
355/**
356 * i40e_aq_get_rss_key
357 * @hw: pointer to the hw struct
358 * @vsi_id: vsi fw index
359 * @key: pointer to key info struct
360 *
361 **/
362int i40e_aq_get_rss_key(struct i40e_hw *hw,
363 u16 vsi_id,
364 struct i40e_aqc_get_set_rss_key_data *key)
365{
366 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
367}
368
369/**
370 * i40e_aq_set_rss_key
371 * @hw: pointer to the hw struct
372 * @vsi_id: vsi fw index
373 * @key: pointer to key info struct
374 *
375 * set the RSS key per VSI
376 **/
377int i40e_aq_set_rss_key(struct i40e_hw *hw,
378 u16 vsi_id,
379 struct i40e_aqc_get_set_rss_key_data *key)
380{
381 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
382}
383
384/**
385 * i40e_init_shared_code - Initialize the shared code
386 * @hw: pointer to hardware structure
387 *
388 * This assigns the MAC type and PHY code and inits the NVM.
389 * Does not touch the hardware. This function must be called prior to any
390 * other function in the shared code. The i40e_hw structure should be
391 * memset to 0 prior to calling this function. The following fields in
392 * hw structure should be filled in prior to calling this function:
393 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
394 * subsystem_vendor_id, and revision_id
395 **/
396int i40e_init_shared_code(struct i40e_hw *hw)
397{
398 u32 port, ari, func_rid;
399 int status = 0;
400
401 i40e_set_mac_type(hw);
402
403 switch (hw->mac.type) {
404 case I40E_MAC_XL710:
405 case I40E_MAC_X722:
406 break;
407 default:
408 return -ENODEV;
409 }
410
411 hw->phy.get_link_info = true;
412
413 /* Determine port number and PF number*/
414 port = FIELD_GET(I40E_PFGEN_PORTNUM_PORT_NUM_MASK,
415 rd32(hw, I40E_PFGEN_PORTNUM));
416 hw->port = (u8)port;
417 ari = FIELD_GET(I40E_GLPCI_CAPSUP_ARI_EN_MASK,
418 rd32(hw, I40E_GLPCI_CAPSUP));
419 func_rid = rd32(hw, I40E_PF_FUNC_RID);
420 if (ari)
421 hw->pf_id = (u8)(func_rid & 0xff);
422 else
423 hw->pf_id = (u8)(func_rid & 0x7);
424
425 status = i40e_init_nvm(hw);
426 return status;
427}
428
429/**
430 * i40e_aq_mac_address_read - Retrieve the MAC addresses
431 * @hw: pointer to the hw struct
432 * @flags: a return indicator of what addresses were added to the addr store
433 * @addrs: the requestor's mac addr store
434 * @cmd_details: pointer to command details structure or NULL
435 **/
436static int
437i40e_aq_mac_address_read(struct i40e_hw *hw,
438 u16 *flags,
439 struct i40e_aqc_mac_address_read_data *addrs,
440 struct i40e_asq_cmd_details *cmd_details)
441{
442 struct i40e_aq_desc desc;
443 struct i40e_aqc_mac_address_read *cmd_data =
444 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
445 int status;
446
447 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
448 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
449
450 status = i40e_asq_send_command(hw, &desc, addrs,
451 sizeof(*addrs), cmd_details);
452 *flags = le16_to_cpu(cmd_data->command_flags);
453
454 return status;
455}
456
457/**
458 * i40e_aq_mac_address_write - Change the MAC addresses
459 * @hw: pointer to the hw struct
460 * @flags: indicates which MAC to be written
461 * @mac_addr: address to write
462 * @cmd_details: pointer to command details structure or NULL
463 **/
464int i40e_aq_mac_address_write(struct i40e_hw *hw,
465 u16 flags, u8 *mac_addr,
466 struct i40e_asq_cmd_details *cmd_details)
467{
468 struct i40e_aq_desc desc;
469 struct i40e_aqc_mac_address_write *cmd_data =
470 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
471 int status;
472
473 i40e_fill_default_direct_cmd_desc(&desc,
474 i40e_aqc_opc_mac_address_write);
475 cmd_data->command_flags = cpu_to_le16(flags);
476 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
477 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
478 ((u32)mac_addr[3] << 16) |
479 ((u32)mac_addr[4] << 8) |
480 mac_addr[5]);
481
482 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
483
484 return status;
485}
486
487/**
488 * i40e_get_mac_addr - get MAC address
489 * @hw: pointer to the HW structure
490 * @mac_addr: pointer to MAC address
491 *
492 * Reads the adapter's MAC address from register
493 **/
494int i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
495{
496 struct i40e_aqc_mac_address_read_data addrs;
497 u16 flags = 0;
498 int status;
499
500 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
501
502 if (flags & I40E_AQC_LAN_ADDR_VALID)
503 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
504
505 return status;
506}
507
508/**
509 * i40e_get_port_mac_addr - get Port MAC address
510 * @hw: pointer to the HW structure
511 * @mac_addr: pointer to Port MAC address
512 *
513 * Reads the adapter's Port MAC address
514 **/
515int i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
516{
517 struct i40e_aqc_mac_address_read_data addrs;
518 u16 flags = 0;
519 int status;
520
521 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
522 if (status)
523 return status;
524
525 if (flags & I40E_AQC_PORT_ADDR_VALID)
526 ether_addr_copy(mac_addr, addrs.port_mac);
527 else
528 status = -EINVAL;
529
530 return status;
531}
532
533/**
534 * i40e_pre_tx_queue_cfg - pre tx queue configure
535 * @hw: pointer to the HW structure
536 * @queue: target PF queue index
537 * @enable: state change request
538 *
539 * Handles hw requirement to indicate intention to enable
540 * or disable target queue.
541 **/
542void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
543{
544 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
545 u32 reg_block = 0;
546 u32 reg_val;
547
548 if (abs_queue_idx >= 128) {
549 reg_block = abs_queue_idx / 128;
550 abs_queue_idx %= 128;
551 }
552
553 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
554 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
555 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
556
557 if (enable)
558 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
559 else
560 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
561
562 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
563}
564
565/**
566 * i40e_get_pba_string - Reads part number string from EEPROM
567 * @hw: pointer to hardware structure
568 *
569 * Reads the part number string from the EEPROM and stores it
570 * into newly allocated buffer and saves resulting pointer
571 * to i40e_hw->pba_id field.
572 **/
573void i40e_get_pba_string(struct i40e_hw *hw)
574{
575#define I40E_NVM_PBA_FLAGS_BLK_PRESENT 0xFAFA
576 u16 pba_word = 0;
577 u16 pba_size = 0;
578 u16 pba_ptr = 0;
579 int status;
580 char *ptr;
581 u16 i;
582
583 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
584 if (status) {
585 hw_dbg(hw, "Failed to read PBA flags.\n");
586 return;
587 }
588 if (pba_word != I40E_NVM_PBA_FLAGS_BLK_PRESENT) {
589 hw_dbg(hw, "PBA block is not present.\n");
590 return;
591 }
592
593 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
594 if (status) {
595 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
596 return;
597 }
598
599 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
600 if (status) {
601 hw_dbg(hw, "Failed to read PBA Block size.\n");
602 return;
603 }
604
605 /* Subtract one to get PBA word count (PBA Size word is included in
606 * total size) and advance pointer to first PBA word.
607 */
608 pba_size--;
609 pba_ptr++;
610 if (!pba_size) {
611 hw_dbg(hw, "PBA ID is empty.\n");
612 return;
613 }
614
615 ptr = devm_kzalloc(i40e_hw_to_dev(hw), pba_size * 2 + 1, GFP_KERNEL);
616 if (!ptr)
617 return;
618 hw->pba_id = ptr;
619
620 for (i = 0; i < pba_size; i++) {
621 status = i40e_read_nvm_word(hw, pba_ptr + i, &pba_word);
622 if (status) {
623 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
624 devm_kfree(i40e_hw_to_dev(hw), hw->pba_id);
625 hw->pba_id = NULL;
626 return;
627 }
628
629 *ptr++ = (pba_word >> 8) & 0xFF;
630 *ptr++ = pba_word & 0xFF;
631 }
632}
633
634/**
635 * i40e_get_media_type - Gets media type
636 * @hw: pointer to the hardware structure
637 **/
638static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
639{
640 enum i40e_media_type media;
641
642 switch (hw->phy.link_info.phy_type) {
643 case I40E_PHY_TYPE_10GBASE_SR:
644 case I40E_PHY_TYPE_10GBASE_LR:
645 case I40E_PHY_TYPE_1000BASE_SX:
646 case I40E_PHY_TYPE_1000BASE_LX:
647 case I40E_PHY_TYPE_40GBASE_SR4:
648 case I40E_PHY_TYPE_40GBASE_LR4:
649 case I40E_PHY_TYPE_25GBASE_LR:
650 case I40E_PHY_TYPE_25GBASE_SR:
651 media = I40E_MEDIA_TYPE_FIBER;
652 break;
653 case I40E_PHY_TYPE_100BASE_TX:
654 case I40E_PHY_TYPE_1000BASE_T:
655 case I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS:
656 case I40E_PHY_TYPE_5GBASE_T_LINK_STATUS:
657 case I40E_PHY_TYPE_10GBASE_T:
658 media = I40E_MEDIA_TYPE_BASET;
659 break;
660 case I40E_PHY_TYPE_10GBASE_CR1_CU:
661 case I40E_PHY_TYPE_40GBASE_CR4_CU:
662 case I40E_PHY_TYPE_10GBASE_CR1:
663 case I40E_PHY_TYPE_40GBASE_CR4:
664 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
665 case I40E_PHY_TYPE_40GBASE_AOC:
666 case I40E_PHY_TYPE_10GBASE_AOC:
667 case I40E_PHY_TYPE_25GBASE_CR:
668 case I40E_PHY_TYPE_25GBASE_AOC:
669 case I40E_PHY_TYPE_25GBASE_ACC:
670 media = I40E_MEDIA_TYPE_DA;
671 break;
672 case I40E_PHY_TYPE_1000BASE_KX:
673 case I40E_PHY_TYPE_10GBASE_KX4:
674 case I40E_PHY_TYPE_10GBASE_KR:
675 case I40E_PHY_TYPE_40GBASE_KR4:
676 case I40E_PHY_TYPE_20GBASE_KR2:
677 case I40E_PHY_TYPE_25GBASE_KR:
678 media = I40E_MEDIA_TYPE_BACKPLANE;
679 break;
680 case I40E_PHY_TYPE_SGMII:
681 case I40E_PHY_TYPE_XAUI:
682 case I40E_PHY_TYPE_XFI:
683 case I40E_PHY_TYPE_XLAUI:
684 case I40E_PHY_TYPE_XLPPI:
685 default:
686 media = I40E_MEDIA_TYPE_UNKNOWN;
687 break;
688 }
689
690 return media;
691}
692
693/**
694 * i40e_poll_globr - Poll for Global Reset completion
695 * @hw: pointer to the hardware structure
696 * @retry_limit: how many times to retry before failure
697 **/
698static int i40e_poll_globr(struct i40e_hw *hw,
699 u32 retry_limit)
700{
701 u32 cnt, reg = 0;
702
703 for (cnt = 0; cnt < retry_limit; cnt++) {
704 reg = rd32(hw, I40E_GLGEN_RSTAT);
705 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
706 return 0;
707 msleep(100);
708 }
709
710 hw_dbg(hw, "Global reset failed.\n");
711 hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg);
712
713 return -EIO;
714}
715
716#define I40E_PF_RESET_WAIT_COUNT_A0 200
717#define I40E_PF_RESET_WAIT_COUNT 200
718/**
719 * i40e_pf_reset - Reset the PF
720 * @hw: pointer to the hardware structure
721 *
722 * Assuming someone else has triggered a global reset,
723 * assure the global reset is complete and then reset the PF
724 **/
725int i40e_pf_reset(struct i40e_hw *hw)
726{
727 u32 cnt = 0;
728 u32 cnt1 = 0;
729 u32 reg = 0;
730 u32 grst_del;
731
732 /* Poll for Global Reset steady state in case of recent GRST.
733 * The grst delay value is in 100ms units, and we'll wait a
734 * couple counts longer to be sure we don't just miss the end.
735 */
736 grst_del = FIELD_GET(I40E_GLGEN_RSTCTL_GRSTDEL_MASK,
737 rd32(hw, I40E_GLGEN_RSTCTL));
738
739 /* It can take upto 15 secs for GRST steady state.
740 * Bump it to 16 secs max to be safe.
741 */
742 grst_del = grst_del * 20;
743
744 for (cnt = 0; cnt < grst_del; cnt++) {
745 reg = rd32(hw, I40E_GLGEN_RSTAT);
746 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
747 break;
748 msleep(100);
749 }
750 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
751 hw_dbg(hw, "Global reset polling failed to complete.\n");
752 return -EIO;
753 }
754
755 /* Now Wait for the FW to be ready */
756 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
757 reg = rd32(hw, I40E_GLNVM_ULD);
758 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
759 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
760 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
761 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
762 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
763 break;
764 }
765 usleep_range(10000, 20000);
766 }
767 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
768 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
769 hw_dbg(hw, "wait for FW Reset complete timedout\n");
770 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
771 return -EIO;
772 }
773
774 /* If there was a Global Reset in progress when we got here,
775 * we don't need to do the PF Reset
776 */
777 if (!cnt) {
778 u32 reg2 = 0;
779 if (hw->revision_id == 0)
780 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
781 else
782 cnt = I40E_PF_RESET_WAIT_COUNT;
783 reg = rd32(hw, I40E_PFGEN_CTRL);
784 wr32(hw, I40E_PFGEN_CTRL,
785 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
786 for (; cnt; cnt--) {
787 reg = rd32(hw, I40E_PFGEN_CTRL);
788 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
789 break;
790 reg2 = rd32(hw, I40E_GLGEN_RSTAT);
791 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
792 break;
793 usleep_range(1000, 2000);
794 }
795 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
796 if (i40e_poll_globr(hw, grst_del))
797 return -EIO;
798 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
799 hw_dbg(hw, "PF reset polling failed to complete.\n");
800 return -EIO;
801 }
802 }
803
804 i40e_clear_pxe_mode(hw);
805
806 return 0;
807}
808
809/**
810 * i40e_clear_hw - clear out any left over hw state
811 * @hw: pointer to the hw struct
812 *
813 * Clear queues and interrupts, typically called at init time,
814 * but after the capabilities have been found so we know how many
815 * queues and msix vectors have been allocated.
816 **/
817void i40e_clear_hw(struct i40e_hw *hw)
818{
819 u32 num_queues, base_queue;
820 u32 num_pf_int;
821 u32 num_vf_int;
822 u32 num_vfs;
823 u32 i, j;
824 u32 val;
825 u32 eol = 0x7ff;
826
827 /* get number of interrupts, queues, and VFs */
828 val = rd32(hw, I40E_GLPCI_CNF2);
829 num_pf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_PF_N_MASK, val);
830 num_vf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_VF_N_MASK, val);
831
832 val = rd32(hw, I40E_PFLAN_QALLOC);
833 base_queue = FIELD_GET(I40E_PFLAN_QALLOC_FIRSTQ_MASK, val);
834 j = FIELD_GET(I40E_PFLAN_QALLOC_LASTQ_MASK, val);
835 if (val & I40E_PFLAN_QALLOC_VALID_MASK && j >= base_queue)
836 num_queues = (j - base_queue) + 1;
837 else
838 num_queues = 0;
839
840 val = rd32(hw, I40E_PF_VT_PFALLOC);
841 i = FIELD_GET(I40E_PF_VT_PFALLOC_FIRSTVF_MASK, val);
842 j = FIELD_GET(I40E_PF_VT_PFALLOC_LASTVF_MASK, val);
843 if (val & I40E_PF_VT_PFALLOC_VALID_MASK && j >= i)
844 num_vfs = (j - i) + 1;
845 else
846 num_vfs = 0;
847
848 /* stop all the interrupts */
849 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
850 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
851 for (i = 0; i < num_pf_int - 2; i++)
852 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
853
854 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
855 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
856 wr32(hw, I40E_PFINT_LNKLST0, val);
857 for (i = 0; i < num_pf_int - 2; i++)
858 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
859 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
860 for (i = 0; i < num_vfs; i++)
861 wr32(hw, I40E_VPINT_LNKLST0(i), val);
862 for (i = 0; i < num_vf_int - 2; i++)
863 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
864
865 /* warn the HW of the coming Tx disables */
866 for (i = 0; i < num_queues; i++) {
867 u32 abs_queue_idx = base_queue + i;
868 u32 reg_block = 0;
869
870 if (abs_queue_idx >= 128) {
871 reg_block = abs_queue_idx / 128;
872 abs_queue_idx %= 128;
873 }
874
875 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
876 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
877 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
878 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
879
880 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
881 }
882 udelay(400);
883
884 /* stop all the queues */
885 for (i = 0; i < num_queues; i++) {
886 wr32(hw, I40E_QINT_TQCTL(i), 0);
887 wr32(hw, I40E_QTX_ENA(i), 0);
888 wr32(hw, I40E_QINT_RQCTL(i), 0);
889 wr32(hw, I40E_QRX_ENA(i), 0);
890 }
891
892 /* short wait for all queue disables to settle */
893 udelay(50);
894}
895
896/**
897 * i40e_clear_pxe_mode - clear pxe operations mode
898 * @hw: pointer to the hw struct
899 *
900 * Make sure all PXE mode settings are cleared, including things
901 * like descriptor fetch/write-back mode.
902 **/
903void i40e_clear_pxe_mode(struct i40e_hw *hw)
904{
905 u32 reg;
906
907 if (i40e_check_asq_alive(hw))
908 i40e_aq_clear_pxe_mode(hw, NULL);
909
910 /* Clear single descriptor fetch/write-back mode */
911 reg = rd32(hw, I40E_GLLAN_RCTL_0);
912
913 if (hw->revision_id == 0) {
914 /* As a work around clear PXE_MODE instead of setting it */
915 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
916 } else {
917 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
918 }
919}
920
921/**
922 * i40e_led_is_mine - helper to find matching led
923 * @hw: pointer to the hw struct
924 * @idx: index into GPIO registers
925 *
926 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
927 */
928static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
929{
930 u32 gpio_val = 0;
931 u32 port;
932
933 if (!I40E_IS_X710TL_DEVICE(hw->device_id) &&
934 !hw->func_caps.led[idx])
935 return 0;
936 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
937 port = FIELD_GET(I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK, gpio_val);
938
939 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
940 * if it is not our port then ignore
941 */
942 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
943 (port != hw->port))
944 return 0;
945
946 return gpio_val;
947}
948
949#define I40E_FW_LED BIT(4)
950#define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \
951 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
952
953#define I40E_LED0 22
954
955#define I40E_PIN_FUNC_SDP 0x0
956#define I40E_PIN_FUNC_LED 0x1
957
958/**
959 * i40e_led_get - return current on/off mode
960 * @hw: pointer to the hw struct
961 *
962 * The value returned is the 'mode' field as defined in the
963 * GPIO register definitions: 0x0 = off, 0xf = on, and other
964 * values are variations of possible behaviors relating to
965 * blink, link, and wire.
966 **/
967u32 i40e_led_get(struct i40e_hw *hw)
968{
969 u32 mode = 0;
970 int i;
971
972 /* as per the documentation GPIO 22-29 are the LED
973 * GPIO pins named LED0..LED7
974 */
975 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
976 u32 gpio_val = i40e_led_is_mine(hw, i);
977
978 if (!gpio_val)
979 continue;
980
981 mode = FIELD_GET(I40E_GLGEN_GPIO_CTL_LED_MODE_MASK, gpio_val);
982 break;
983 }
984
985 return mode;
986}
987
988/**
989 * i40e_led_set - set new on/off mode
990 * @hw: pointer to the hw struct
991 * @mode: 0=off, 0xf=on (else see manual for mode details)
992 * @blink: true if the LED should blink when on, false if steady
993 *
994 * if this function is used to turn on the blink it should
995 * be used to disable the blink when restoring the original state.
996 **/
997void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
998{
999 int i;
1000
1001 if (mode & ~I40E_LED_MODE_VALID) {
1002 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1003 return;
1004 }
1005
1006 /* as per the documentation GPIO 22-29 are the LED
1007 * GPIO pins named LED0..LED7
1008 */
1009 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1010 u32 gpio_val = i40e_led_is_mine(hw, i);
1011
1012 if (!gpio_val)
1013 continue;
1014
1015 if (I40E_IS_X710TL_DEVICE(hw->device_id)) {
1016 u32 pin_func = 0;
1017
1018 if (mode & I40E_FW_LED)
1019 pin_func = I40E_PIN_FUNC_SDP;
1020 else
1021 pin_func = I40E_PIN_FUNC_LED;
1022
1023 gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK;
1024 gpio_val |=
1025 FIELD_PREP(I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK,
1026 pin_func);
1027 }
1028 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1029 /* this & is a bit of paranoia, but serves as a range check */
1030 gpio_val |= FIELD_PREP(I40E_GLGEN_GPIO_CTL_LED_MODE_MASK,
1031 mode);
1032
1033 if (blink)
1034 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1035 else
1036 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1037
1038 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1039 break;
1040 }
1041}
1042
1043/* Admin command wrappers */
1044
1045/**
1046 * i40e_aq_get_phy_capabilities
1047 * @hw: pointer to the hw struct
1048 * @abilities: structure for PHY capabilities to be filled
1049 * @qualified_modules: report Qualified Modules
1050 * @report_init: report init capabilities (active are default)
1051 * @cmd_details: pointer to command details structure or NULL
1052 *
1053 * Returns the various PHY abilities supported on the Port.
1054 **/
1055int
1056i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1057 bool qualified_modules, bool report_init,
1058 struct i40e_aq_get_phy_abilities_resp *abilities,
1059 struct i40e_asq_cmd_details *cmd_details)
1060{
1061 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1062 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1063 struct i40e_aq_desc desc;
1064 int status;
1065
1066 if (!abilities)
1067 return -EINVAL;
1068
1069 do {
1070 i40e_fill_default_direct_cmd_desc(&desc,
1071 i40e_aqc_opc_get_phy_abilities);
1072
1073 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1074 if (abilities_size > I40E_AQ_LARGE_BUF)
1075 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1076
1077 if (qualified_modules)
1078 desc.params.external.param0 |=
1079 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1080
1081 if (report_init)
1082 desc.params.external.param0 |=
1083 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1084
1085 status = i40e_asq_send_command(hw, &desc, abilities,
1086 abilities_size, cmd_details);
1087
1088 switch (hw->aq.asq_last_status) {
1089 case I40E_AQ_RC_EIO:
1090 status = -EIO;
1091 break;
1092 case I40E_AQ_RC_EAGAIN:
1093 usleep_range(1000, 2000);
1094 total_delay++;
1095 status = -EIO;
1096 break;
1097 /* also covers I40E_AQ_RC_OK */
1098 default:
1099 break;
1100 }
1101
1102 } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) &&
1103 (total_delay < max_delay));
1104
1105 if (status)
1106 return status;
1107
1108 if (report_init) {
1109 if (hw->mac.type == I40E_MAC_XL710 &&
1110 i40e_is_aq_api_ver_ge(hw, I40E_FW_API_VERSION_MAJOR,
1111 I40E_MINOR_VER_GET_LINK_INFO_XL710)) {
1112 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1113 } else {
1114 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1115 hw->phy.phy_types |=
1116 ((u64)abilities->phy_type_ext << 32);
1117 }
1118 }
1119
1120 return status;
1121}
1122
1123/**
1124 * i40e_aq_set_phy_config
1125 * @hw: pointer to the hw struct
1126 * @config: structure with PHY configuration to be set
1127 * @cmd_details: pointer to command details structure or NULL
1128 *
1129 * Set the various PHY configuration parameters
1130 * supported on the Port.One or more of the Set PHY config parameters may be
1131 * ignored in an MFP mode as the PF may not have the privilege to set some
1132 * of the PHY Config parameters. This status will be indicated by the
1133 * command response.
1134 **/
1135int i40e_aq_set_phy_config(struct i40e_hw *hw,
1136 struct i40e_aq_set_phy_config *config,
1137 struct i40e_asq_cmd_details *cmd_details)
1138{
1139 struct i40e_aq_desc desc;
1140 struct i40e_aq_set_phy_config *cmd =
1141 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1142 int status;
1143
1144 if (!config)
1145 return -EINVAL;
1146
1147 i40e_fill_default_direct_cmd_desc(&desc,
1148 i40e_aqc_opc_set_phy_config);
1149
1150 *cmd = *config;
1151
1152 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1153
1154 return status;
1155}
1156
1157static noinline_for_stack int
1158i40e_set_fc_status(struct i40e_hw *hw,
1159 struct i40e_aq_get_phy_abilities_resp *abilities,
1160 bool atomic_restart)
1161{
1162 struct i40e_aq_set_phy_config config;
1163 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1164 u8 pause_mask = 0x0;
1165
1166 switch (fc_mode) {
1167 case I40E_FC_FULL:
1168 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1169 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1170 break;
1171 case I40E_FC_RX_PAUSE:
1172 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1173 break;
1174 case I40E_FC_TX_PAUSE:
1175 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1176 break;
1177 default:
1178 break;
1179 }
1180
1181 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1182 /* clear the old pause settings */
1183 config.abilities = abilities->abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1184 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1185 /* set the new abilities */
1186 config.abilities |= pause_mask;
1187 /* If the abilities have changed, then set the new config */
1188 if (config.abilities == abilities->abilities)
1189 return 0;
1190
1191 /* Auto restart link so settings take effect */
1192 if (atomic_restart)
1193 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1194 /* Copy over all the old settings */
1195 config.phy_type = abilities->phy_type;
1196 config.phy_type_ext = abilities->phy_type_ext;
1197 config.link_speed = abilities->link_speed;
1198 config.eee_capability = abilities->eee_capability;
1199 config.eeer = abilities->eeer_val;
1200 config.low_power_ctrl = abilities->d3_lpan;
1201 config.fec_config = abilities->fec_cfg_curr_mod_ext_info &
1202 I40E_AQ_PHY_FEC_CONFIG_MASK;
1203
1204 return i40e_aq_set_phy_config(hw, &config, NULL);
1205}
1206
1207/**
1208 * i40e_set_fc
1209 * @hw: pointer to the hw struct
1210 * @aq_failures: buffer to return AdminQ failure information
1211 * @atomic_restart: whether to enable atomic link restart
1212 *
1213 * Set the requested flow control mode using set_phy_config.
1214 **/
1215int i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1216 bool atomic_restart)
1217{
1218 struct i40e_aq_get_phy_abilities_resp abilities;
1219 int status;
1220
1221 *aq_failures = 0x0;
1222
1223 /* Get the current phy config */
1224 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1225 NULL);
1226 if (status) {
1227 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1228 return status;
1229 }
1230
1231 status = i40e_set_fc_status(hw, &abilities, atomic_restart);
1232 if (status)
1233 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1234
1235 /* Update the link info */
1236 status = i40e_update_link_info(hw);
1237 if (status) {
1238 /* Wait a little bit (on 40G cards it sometimes takes a really
1239 * long time for link to come back from the atomic reset)
1240 * and try once more
1241 */
1242 msleep(1000);
1243 status = i40e_update_link_info(hw);
1244 }
1245 if (status)
1246 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1247
1248 return status;
1249}
1250
1251/**
1252 * i40e_aq_clear_pxe_mode
1253 * @hw: pointer to the hw struct
1254 * @cmd_details: pointer to command details structure or NULL
1255 *
1256 * Tell the firmware that the driver is taking over from PXE
1257 **/
1258int i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1259 struct i40e_asq_cmd_details *cmd_details)
1260{
1261 struct i40e_aq_desc desc;
1262 struct i40e_aqc_clear_pxe *cmd =
1263 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1264 int status;
1265
1266 i40e_fill_default_direct_cmd_desc(&desc,
1267 i40e_aqc_opc_clear_pxe_mode);
1268
1269 cmd->rx_cnt = 0x2;
1270
1271 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1272
1273 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1274
1275 return status;
1276}
1277
1278/**
1279 * i40e_aq_set_link_restart_an
1280 * @hw: pointer to the hw struct
1281 * @enable_link: if true: enable link, if false: disable link
1282 * @cmd_details: pointer to command details structure or NULL
1283 *
1284 * Sets up the link and restarts the Auto-Negotiation over the link.
1285 **/
1286int i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1287 bool enable_link,
1288 struct i40e_asq_cmd_details *cmd_details)
1289{
1290 struct i40e_aq_desc desc;
1291 struct i40e_aqc_set_link_restart_an *cmd =
1292 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1293 int status;
1294
1295 i40e_fill_default_direct_cmd_desc(&desc,
1296 i40e_aqc_opc_set_link_restart_an);
1297
1298 cmd->command = I40E_AQ_PHY_RESTART_AN;
1299 if (enable_link)
1300 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1301 else
1302 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1303
1304 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1305
1306 return status;
1307}
1308
1309/**
1310 * i40e_aq_get_link_info
1311 * @hw: pointer to the hw struct
1312 * @enable_lse: enable/disable LinkStatusEvent reporting
1313 * @link: pointer to link status structure - optional
1314 * @cmd_details: pointer to command details structure or NULL
1315 *
1316 * Returns the link status of the adapter.
1317 **/
1318int i40e_aq_get_link_info(struct i40e_hw *hw,
1319 bool enable_lse, struct i40e_link_status *link,
1320 struct i40e_asq_cmd_details *cmd_details)
1321{
1322 struct i40e_aq_desc desc;
1323 struct i40e_aqc_get_link_status *resp =
1324 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1325 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1326 bool tx_pause, rx_pause;
1327 u16 command_flags;
1328 int status;
1329
1330 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1331
1332 if (enable_lse)
1333 command_flags = I40E_AQ_LSE_ENABLE;
1334 else
1335 command_flags = I40E_AQ_LSE_DISABLE;
1336 resp->command_flags = cpu_to_le16(command_flags);
1337
1338 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1339
1340 if (status)
1341 goto aq_get_link_info_exit;
1342
1343 /* save off old link status information */
1344 hw->phy.link_info_old = *hw_link_info;
1345
1346 /* update link status */
1347 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1348 hw->phy.media_type = i40e_get_media_type(hw);
1349 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1350 hw_link_info->link_info = resp->link_info;
1351 hw_link_info->an_info = resp->an_info;
1352 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1353 I40E_AQ_CONFIG_FEC_RS_ENA);
1354 hw_link_info->ext_info = resp->ext_info;
1355 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1356 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1357 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1358
1359 /* update fc info */
1360 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1361 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1362 if (tx_pause & rx_pause)
1363 hw->fc.current_mode = I40E_FC_FULL;
1364 else if (tx_pause)
1365 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1366 else if (rx_pause)
1367 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1368 else
1369 hw->fc.current_mode = I40E_FC_NONE;
1370
1371 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1372 hw_link_info->crc_enable = true;
1373 else
1374 hw_link_info->crc_enable = false;
1375
1376 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED))
1377 hw_link_info->lse_enable = true;
1378 else
1379 hw_link_info->lse_enable = false;
1380
1381 if (hw->mac.type == I40E_MAC_XL710 && i40e_is_fw_ver_lt(hw, 4, 40) &&
1382 hw_link_info->phy_type == 0xE)
1383 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1384
1385 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps) &&
1386 hw->mac.type != I40E_MAC_X722) {
1387 __le32 tmp;
1388
1389 memcpy(&tmp, resp->link_type, sizeof(tmp));
1390 hw->phy.phy_types = le32_to_cpu(tmp);
1391 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
1392 }
1393
1394 /* save link status information */
1395 if (link)
1396 *link = *hw_link_info;
1397
1398 /* flag cleared so helper functions don't call AQ again */
1399 hw->phy.get_link_info = false;
1400
1401aq_get_link_info_exit:
1402 return status;
1403}
1404
1405/**
1406 * i40e_aq_set_phy_int_mask
1407 * @hw: pointer to the hw struct
1408 * @mask: interrupt mask to be set
1409 * @cmd_details: pointer to command details structure or NULL
1410 *
1411 * Set link interrupt mask.
1412 **/
1413int i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1414 u16 mask,
1415 struct i40e_asq_cmd_details *cmd_details)
1416{
1417 struct i40e_aq_desc desc;
1418 struct i40e_aqc_set_phy_int_mask *cmd =
1419 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1420 int status;
1421
1422 i40e_fill_default_direct_cmd_desc(&desc,
1423 i40e_aqc_opc_set_phy_int_mask);
1424
1425 cmd->event_mask = cpu_to_le16(mask);
1426
1427 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1428
1429 return status;
1430}
1431
1432/**
1433 * i40e_aq_set_mac_loopback
1434 * @hw: pointer to the HW struct
1435 * @ena_lpbk: Enable or Disable loopback
1436 * @cmd_details: pointer to command details structure or NULL
1437 *
1438 * Enable/disable loopback on a given port
1439 */
1440int i40e_aq_set_mac_loopback(struct i40e_hw *hw, bool ena_lpbk,
1441 struct i40e_asq_cmd_details *cmd_details)
1442{
1443 struct i40e_aq_desc desc;
1444 struct i40e_aqc_set_lb_mode *cmd =
1445 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1446
1447 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_lb_modes);
1448 if (ena_lpbk) {
1449 if (hw->nvm.version <= I40E_LEGACY_LOOPBACK_NVM_VER)
1450 cmd->lb_mode = cpu_to_le16(I40E_AQ_LB_MAC_LOCAL_LEGACY);
1451 else
1452 cmd->lb_mode = cpu_to_le16(I40E_AQ_LB_MAC_LOCAL);
1453 }
1454
1455 return i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1456}
1457
1458/**
1459 * i40e_aq_set_phy_debug
1460 * @hw: pointer to the hw struct
1461 * @cmd_flags: debug command flags
1462 * @cmd_details: pointer to command details structure or NULL
1463 *
1464 * Reset the external PHY.
1465 **/
1466int i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1467 struct i40e_asq_cmd_details *cmd_details)
1468{
1469 struct i40e_aq_desc desc;
1470 struct i40e_aqc_set_phy_debug *cmd =
1471 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1472 int status;
1473
1474 i40e_fill_default_direct_cmd_desc(&desc,
1475 i40e_aqc_opc_set_phy_debug);
1476
1477 cmd->command_flags = cmd_flags;
1478
1479 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1480
1481 return status;
1482}
1483
1484/**
1485 * i40e_aq_add_vsi
1486 * @hw: pointer to the hw struct
1487 * @vsi_ctx: pointer to a vsi context struct
1488 * @cmd_details: pointer to command details structure or NULL
1489 *
1490 * Add a VSI context to the hardware.
1491**/
1492int i40e_aq_add_vsi(struct i40e_hw *hw,
1493 struct i40e_vsi_context *vsi_ctx,
1494 struct i40e_asq_cmd_details *cmd_details)
1495{
1496 struct i40e_aq_desc desc;
1497 struct i40e_aqc_add_get_update_vsi *cmd =
1498 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1499 struct i40e_aqc_add_get_update_vsi_completion *resp =
1500 (struct i40e_aqc_add_get_update_vsi_completion *)
1501 &desc.params.raw;
1502 int status;
1503
1504 i40e_fill_default_direct_cmd_desc(&desc,
1505 i40e_aqc_opc_add_vsi);
1506
1507 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1508 cmd->connection_type = vsi_ctx->connection_type;
1509 cmd->vf_id = vsi_ctx->vf_num;
1510 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1511
1512 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1513
1514 status = i40e_asq_send_command_atomic(hw, &desc, &vsi_ctx->info,
1515 sizeof(vsi_ctx->info),
1516 cmd_details, true);
1517
1518 if (status)
1519 goto aq_add_vsi_exit;
1520
1521 vsi_ctx->seid = le16_to_cpu(resp->seid);
1522 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1523 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1524 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1525
1526aq_add_vsi_exit:
1527 return status;
1528}
1529
1530/**
1531 * i40e_aq_set_default_vsi
1532 * @hw: pointer to the hw struct
1533 * @seid: vsi number
1534 * @cmd_details: pointer to command details structure or NULL
1535 **/
1536int i40e_aq_set_default_vsi(struct i40e_hw *hw,
1537 u16 seid,
1538 struct i40e_asq_cmd_details *cmd_details)
1539{
1540 struct i40e_aq_desc desc;
1541 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1542 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1543 &desc.params.raw;
1544 int status;
1545
1546 i40e_fill_default_direct_cmd_desc(&desc,
1547 i40e_aqc_opc_set_vsi_promiscuous_modes);
1548
1549 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1550 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1551 cmd->seid = cpu_to_le16(seid);
1552
1553 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1554
1555 return status;
1556}
1557
1558/**
1559 * i40e_aq_clear_default_vsi
1560 * @hw: pointer to the hw struct
1561 * @seid: vsi number
1562 * @cmd_details: pointer to command details structure or NULL
1563 **/
1564int i40e_aq_clear_default_vsi(struct i40e_hw *hw,
1565 u16 seid,
1566 struct i40e_asq_cmd_details *cmd_details)
1567{
1568 struct i40e_aq_desc desc;
1569 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1570 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1571 &desc.params.raw;
1572 int status;
1573
1574 i40e_fill_default_direct_cmd_desc(&desc,
1575 i40e_aqc_opc_set_vsi_promiscuous_modes);
1576
1577 cmd->promiscuous_flags = cpu_to_le16(0);
1578 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1579 cmd->seid = cpu_to_le16(seid);
1580
1581 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1582
1583 return status;
1584}
1585
1586/**
1587 * i40e_aq_set_vsi_unicast_promiscuous
1588 * @hw: pointer to the hw struct
1589 * @seid: vsi number
1590 * @set: set unicast promiscuous enable/disable
1591 * @cmd_details: pointer to command details structure or NULL
1592 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
1593 **/
1594int i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1595 u16 seid, bool set,
1596 struct i40e_asq_cmd_details *cmd_details,
1597 bool rx_only_promisc)
1598{
1599 struct i40e_aq_desc desc;
1600 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1601 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1602 u16 flags = 0;
1603 int status;
1604
1605 i40e_fill_default_direct_cmd_desc(&desc,
1606 i40e_aqc_opc_set_vsi_promiscuous_modes);
1607
1608 if (set) {
1609 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1610 if (rx_only_promisc && i40e_is_aq_api_ver_ge(hw, 1, 5))
1611 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
1612 }
1613
1614 cmd->promiscuous_flags = cpu_to_le16(flags);
1615
1616 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1617 if (i40e_is_aq_api_ver_ge(hw, 1, 5))
1618 cmd->valid_flags |=
1619 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
1620
1621 cmd->seid = cpu_to_le16(seid);
1622 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1623
1624 return status;
1625}
1626
1627/**
1628 * i40e_aq_set_vsi_multicast_promiscuous
1629 * @hw: pointer to the hw struct
1630 * @seid: vsi number
1631 * @set: set multicast promiscuous enable/disable
1632 * @cmd_details: pointer to command details structure or NULL
1633 **/
1634int i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1635 u16 seid, bool set,
1636 struct i40e_asq_cmd_details *cmd_details)
1637{
1638 struct i40e_aq_desc desc;
1639 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1640 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1641 u16 flags = 0;
1642 int status;
1643
1644 i40e_fill_default_direct_cmd_desc(&desc,
1645 i40e_aqc_opc_set_vsi_promiscuous_modes);
1646
1647 if (set)
1648 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1649
1650 cmd->promiscuous_flags = cpu_to_le16(flags);
1651
1652 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1653
1654 cmd->seid = cpu_to_le16(seid);
1655 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1656
1657 return status;
1658}
1659
1660/**
1661 * i40e_aq_set_vsi_mc_promisc_on_vlan
1662 * @hw: pointer to the hw struct
1663 * @seid: vsi number
1664 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
1665 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
1666 * @cmd_details: pointer to command details structure or NULL
1667 **/
1668int i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
1669 u16 seid, bool enable,
1670 u16 vid,
1671 struct i40e_asq_cmd_details *cmd_details)
1672{
1673 struct i40e_aq_desc desc;
1674 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1675 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1676 u16 flags = 0;
1677 int status;
1678
1679 i40e_fill_default_direct_cmd_desc(&desc,
1680 i40e_aqc_opc_set_vsi_promiscuous_modes);
1681
1682 if (enable)
1683 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1684
1685 cmd->promiscuous_flags = cpu_to_le16(flags);
1686 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1687 cmd->seid = cpu_to_le16(seid);
1688 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
1689
1690 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0,
1691 cmd_details, true);
1692
1693 return status;
1694}
1695
1696/**
1697 * i40e_aq_set_vsi_uc_promisc_on_vlan
1698 * @hw: pointer to the hw struct
1699 * @seid: vsi number
1700 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
1701 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
1702 * @cmd_details: pointer to command details structure or NULL
1703 **/
1704int i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
1705 u16 seid, bool enable,
1706 u16 vid,
1707 struct i40e_asq_cmd_details *cmd_details)
1708{
1709 struct i40e_aq_desc desc;
1710 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1711 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1712 u16 flags = 0;
1713 int status;
1714
1715 i40e_fill_default_direct_cmd_desc(&desc,
1716 i40e_aqc_opc_set_vsi_promiscuous_modes);
1717
1718 if (enable) {
1719 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1720 if (i40e_is_aq_api_ver_ge(hw, 1, 5))
1721 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
1722 }
1723
1724 cmd->promiscuous_flags = cpu_to_le16(flags);
1725 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1726 if (i40e_is_aq_api_ver_ge(hw, 1, 5))
1727 cmd->valid_flags |=
1728 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
1729 cmd->seid = cpu_to_le16(seid);
1730 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
1731
1732 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0,
1733 cmd_details, true);
1734
1735 return status;
1736}
1737
1738/**
1739 * i40e_aq_set_vsi_bc_promisc_on_vlan
1740 * @hw: pointer to the hw struct
1741 * @seid: vsi number
1742 * @enable: set broadcast promiscuous enable/disable for a given VLAN
1743 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
1744 * @cmd_details: pointer to command details structure or NULL
1745 **/
1746int i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
1747 u16 seid, bool enable, u16 vid,
1748 struct i40e_asq_cmd_details *cmd_details)
1749{
1750 struct i40e_aq_desc desc;
1751 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1752 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1753 u16 flags = 0;
1754 int status;
1755
1756 i40e_fill_default_direct_cmd_desc(&desc,
1757 i40e_aqc_opc_set_vsi_promiscuous_modes);
1758
1759 if (enable)
1760 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
1761
1762 cmd->promiscuous_flags = cpu_to_le16(flags);
1763 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1764 cmd->seid = cpu_to_le16(seid);
1765 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
1766
1767 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1768
1769 return status;
1770}
1771
1772/**
1773 * i40e_aq_set_vsi_broadcast
1774 * @hw: pointer to the hw struct
1775 * @seid: vsi number
1776 * @set_filter: true to set filter, false to clear filter
1777 * @cmd_details: pointer to command details structure or NULL
1778 *
1779 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1780 **/
1781int i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1782 u16 seid, bool set_filter,
1783 struct i40e_asq_cmd_details *cmd_details)
1784{
1785 struct i40e_aq_desc desc;
1786 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1787 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1788 int status;
1789
1790 i40e_fill_default_direct_cmd_desc(&desc,
1791 i40e_aqc_opc_set_vsi_promiscuous_modes);
1792
1793 if (set_filter)
1794 cmd->promiscuous_flags
1795 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1796 else
1797 cmd->promiscuous_flags
1798 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1799
1800 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1801 cmd->seid = cpu_to_le16(seid);
1802 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1803
1804 return status;
1805}
1806
1807/**
1808 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
1809 * @hw: pointer to the hw struct
1810 * @seid: vsi number
1811 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
1812 * @cmd_details: pointer to command details structure or NULL
1813 **/
1814int i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
1815 u16 seid, bool enable,
1816 struct i40e_asq_cmd_details *cmd_details)
1817{
1818 struct i40e_aq_desc desc;
1819 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1820 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1821 u16 flags = 0;
1822 int status;
1823
1824 i40e_fill_default_direct_cmd_desc(&desc,
1825 i40e_aqc_opc_set_vsi_promiscuous_modes);
1826 if (enable)
1827 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
1828
1829 cmd->promiscuous_flags = cpu_to_le16(flags);
1830 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
1831 cmd->seid = cpu_to_le16(seid);
1832
1833 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1834
1835 return status;
1836}
1837
1838/**
1839 * i40e_aq_get_vsi_params - get VSI configuration info
1840 * @hw: pointer to the hw struct
1841 * @vsi_ctx: pointer to a vsi context struct
1842 * @cmd_details: pointer to command details structure or NULL
1843 **/
1844int i40e_aq_get_vsi_params(struct i40e_hw *hw,
1845 struct i40e_vsi_context *vsi_ctx,
1846 struct i40e_asq_cmd_details *cmd_details)
1847{
1848 struct i40e_aq_desc desc;
1849 struct i40e_aqc_add_get_update_vsi *cmd =
1850 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1851 struct i40e_aqc_add_get_update_vsi_completion *resp =
1852 (struct i40e_aqc_add_get_update_vsi_completion *)
1853 &desc.params.raw;
1854 int status;
1855
1856 i40e_fill_default_direct_cmd_desc(&desc,
1857 i40e_aqc_opc_get_vsi_parameters);
1858
1859 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
1860
1861 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1862
1863 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1864 sizeof(vsi_ctx->info), NULL);
1865
1866 if (status)
1867 goto aq_get_vsi_params_exit;
1868
1869 vsi_ctx->seid = le16_to_cpu(resp->seid);
1870 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1871 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1872 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1873
1874aq_get_vsi_params_exit:
1875 return status;
1876}
1877
1878/**
1879 * i40e_aq_update_vsi_params
1880 * @hw: pointer to the hw struct
1881 * @vsi_ctx: pointer to a vsi context struct
1882 * @cmd_details: pointer to command details structure or NULL
1883 *
1884 * Update a VSI context.
1885 **/
1886int i40e_aq_update_vsi_params(struct i40e_hw *hw,
1887 struct i40e_vsi_context *vsi_ctx,
1888 struct i40e_asq_cmd_details *cmd_details)
1889{
1890 struct i40e_aq_desc desc;
1891 struct i40e_aqc_add_get_update_vsi *cmd =
1892 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1893 struct i40e_aqc_add_get_update_vsi_completion *resp =
1894 (struct i40e_aqc_add_get_update_vsi_completion *)
1895 &desc.params.raw;
1896 int status;
1897
1898 i40e_fill_default_direct_cmd_desc(&desc,
1899 i40e_aqc_opc_update_vsi_parameters);
1900 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
1901
1902 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1903
1904 status = i40e_asq_send_command_atomic(hw, &desc, &vsi_ctx->info,
1905 sizeof(vsi_ctx->info),
1906 cmd_details, true);
1907
1908 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1909 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1910
1911 return status;
1912}
1913
1914/**
1915 * i40e_aq_get_switch_config
1916 * @hw: pointer to the hardware structure
1917 * @buf: pointer to the result buffer
1918 * @buf_size: length of input buffer
1919 * @start_seid: seid to start for the report, 0 == beginning
1920 * @cmd_details: pointer to command details structure or NULL
1921 *
1922 * Fill the buf with switch configuration returned from AdminQ command
1923 **/
1924int i40e_aq_get_switch_config(struct i40e_hw *hw,
1925 struct i40e_aqc_get_switch_config_resp *buf,
1926 u16 buf_size, u16 *start_seid,
1927 struct i40e_asq_cmd_details *cmd_details)
1928{
1929 struct i40e_aq_desc desc;
1930 struct i40e_aqc_switch_seid *scfg =
1931 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1932 int status;
1933
1934 i40e_fill_default_direct_cmd_desc(&desc,
1935 i40e_aqc_opc_get_switch_config);
1936 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1937 if (buf_size > I40E_AQ_LARGE_BUF)
1938 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1939 scfg->seid = cpu_to_le16(*start_seid);
1940
1941 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1942 *start_seid = le16_to_cpu(scfg->seid);
1943
1944 return status;
1945}
1946
1947/**
1948 * i40e_aq_set_switch_config
1949 * @hw: pointer to the hardware structure
1950 * @flags: bit flag values to set
1951 * @mode: cloud filter mode
1952 * @valid_flags: which bit flags to set
1953 * @mode: cloud filter mode
1954 * @cmd_details: pointer to command details structure or NULL
1955 *
1956 * Set switch configuration bits
1957 **/
1958int i40e_aq_set_switch_config(struct i40e_hw *hw,
1959 u16 flags,
1960 u16 valid_flags, u8 mode,
1961 struct i40e_asq_cmd_details *cmd_details)
1962{
1963 struct i40e_aq_desc desc;
1964 struct i40e_aqc_set_switch_config *scfg =
1965 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
1966 int status;
1967
1968 i40e_fill_default_direct_cmd_desc(&desc,
1969 i40e_aqc_opc_set_switch_config);
1970 scfg->flags = cpu_to_le16(flags);
1971 scfg->valid_flags = cpu_to_le16(valid_flags);
1972 scfg->mode = mode;
1973 if (test_bit(I40E_HW_CAP_802_1AD, hw->caps)) {
1974 scfg->switch_tag = cpu_to_le16(hw->switch_tag);
1975 scfg->first_tag = cpu_to_le16(hw->first_tag);
1976 scfg->second_tag = cpu_to_le16(hw->second_tag);
1977 }
1978 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1979
1980 return status;
1981}
1982
1983/**
1984 * i40e_aq_get_firmware_version
1985 * @hw: pointer to the hw struct
1986 * @fw_major_version: firmware major version
1987 * @fw_minor_version: firmware minor version
1988 * @fw_build: firmware build number
1989 * @api_major_version: major queue version
1990 * @api_minor_version: minor queue version
1991 * @cmd_details: pointer to command details structure or NULL
1992 *
1993 * Get the firmware version from the admin queue commands
1994 **/
1995int i40e_aq_get_firmware_version(struct i40e_hw *hw,
1996 u16 *fw_major_version, u16 *fw_minor_version,
1997 u32 *fw_build,
1998 u16 *api_major_version, u16 *api_minor_version,
1999 struct i40e_asq_cmd_details *cmd_details)
2000{
2001 struct i40e_aq_desc desc;
2002 struct i40e_aqc_get_version *resp =
2003 (struct i40e_aqc_get_version *)&desc.params.raw;
2004 int status;
2005
2006 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2007
2008 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2009
2010 if (!status) {
2011 if (fw_major_version)
2012 *fw_major_version = le16_to_cpu(resp->fw_major);
2013 if (fw_minor_version)
2014 *fw_minor_version = le16_to_cpu(resp->fw_minor);
2015 if (fw_build)
2016 *fw_build = le32_to_cpu(resp->fw_build);
2017 if (api_major_version)
2018 *api_major_version = le16_to_cpu(resp->api_major);
2019 if (api_minor_version)
2020 *api_minor_version = le16_to_cpu(resp->api_minor);
2021 }
2022
2023 return status;
2024}
2025
2026/**
2027 * i40e_aq_send_driver_version
2028 * @hw: pointer to the hw struct
2029 * @dv: driver's major, minor version
2030 * @cmd_details: pointer to command details structure or NULL
2031 *
2032 * Send the driver version to the firmware
2033 **/
2034int i40e_aq_send_driver_version(struct i40e_hw *hw,
2035 struct i40e_driver_version *dv,
2036 struct i40e_asq_cmd_details *cmd_details)
2037{
2038 struct i40e_aq_desc desc;
2039 struct i40e_aqc_driver_version *cmd =
2040 (struct i40e_aqc_driver_version *)&desc.params.raw;
2041 int status;
2042 u16 len;
2043
2044 if (dv == NULL)
2045 return -EINVAL;
2046
2047 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2048
2049 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2050 cmd->driver_major_ver = dv->major_version;
2051 cmd->driver_minor_ver = dv->minor_version;
2052 cmd->driver_build_ver = dv->build_version;
2053 cmd->driver_subbuild_ver = dv->subbuild_version;
2054
2055 len = 0;
2056 while (len < sizeof(dv->driver_string) &&
2057 (dv->driver_string[len] < 0x80) &&
2058 dv->driver_string[len])
2059 len++;
2060 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2061 len, cmd_details);
2062
2063 return status;
2064}
2065
2066/**
2067 * i40e_get_link_status - get status of the HW network link
2068 * @hw: pointer to the hw struct
2069 * @link_up: pointer to bool (true/false = linkup/linkdown)
2070 *
2071 * Variable link_up true if link is up, false if link is down.
2072 * The variable link_up is invalid if returned value of status != 0
2073 *
2074 * Side effect: LinkStatusEvent reporting becomes enabled
2075 **/
2076int i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2077{
2078 int status = 0;
2079
2080 if (hw->phy.get_link_info) {
2081 status = i40e_update_link_info(hw);
2082
2083 if (status)
2084 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2085 status);
2086 }
2087
2088 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2089
2090 return status;
2091}
2092
2093/**
2094 * i40e_update_link_info - update status of the HW network link
2095 * @hw: pointer to the hw struct
2096 **/
2097noinline_for_stack int i40e_update_link_info(struct i40e_hw *hw)
2098{
2099 struct i40e_aq_get_phy_abilities_resp abilities;
2100 int status = 0;
2101
2102 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2103 if (status)
2104 return status;
2105
2106 /* extra checking needed to ensure link info to user is timely */
2107 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2108 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2109 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2110 status = i40e_aq_get_phy_capabilities(hw, false, false,
2111 &abilities, NULL);
2112 if (status)
2113 return status;
2114
2115 if (abilities.fec_cfg_curr_mod_ext_info &
2116 I40E_AQ_ENABLE_FEC_AUTO)
2117 hw->phy.link_info.req_fec_info =
2118 (I40E_AQ_REQUEST_FEC_KR |
2119 I40E_AQ_REQUEST_FEC_RS);
2120 else
2121 hw->phy.link_info.req_fec_info =
2122 abilities.fec_cfg_curr_mod_ext_info &
2123 (I40E_AQ_REQUEST_FEC_KR |
2124 I40E_AQ_REQUEST_FEC_RS);
2125
2126 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2127 sizeof(hw->phy.link_info.module_type));
2128 }
2129
2130 return status;
2131}
2132
2133/**
2134 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2135 * @hw: pointer to the hw struct
2136 * @uplink_seid: the MAC or other gizmo SEID
2137 * @downlink_seid: the VSI SEID
2138 * @enabled_tc: bitmap of TCs to be enabled
2139 * @default_port: true for default port VSI, false for control port
2140 * @veb_seid: pointer to where to put the resulting VEB SEID
2141 * @enable_stats: true to turn on VEB stats
2142 * @cmd_details: pointer to command details structure or NULL
2143 *
2144 * This asks the FW to add a VEB between the uplink and downlink
2145 * elements. If the uplink SEID is 0, this will be a floating VEB.
2146 **/
2147int i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2148 u16 downlink_seid, u8 enabled_tc,
2149 bool default_port, u16 *veb_seid,
2150 bool enable_stats,
2151 struct i40e_asq_cmd_details *cmd_details)
2152{
2153 struct i40e_aq_desc desc;
2154 struct i40e_aqc_add_veb *cmd =
2155 (struct i40e_aqc_add_veb *)&desc.params.raw;
2156 struct i40e_aqc_add_veb_completion *resp =
2157 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2158 u16 veb_flags = 0;
2159 int status;
2160
2161 /* SEIDs need to either both be set or both be 0 for floating VEB */
2162 if (!!uplink_seid != !!downlink_seid)
2163 return -EINVAL;
2164
2165 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2166
2167 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2168 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2169 cmd->enable_tcs = enabled_tc;
2170 if (!uplink_seid)
2171 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2172 if (default_port)
2173 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2174 else
2175 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2176
2177 /* reverse logic here: set the bitflag to disable the stats */
2178 if (!enable_stats)
2179 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2180
2181 cmd->veb_flags = cpu_to_le16(veb_flags);
2182
2183 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2184
2185 if (!status && veb_seid)
2186 *veb_seid = le16_to_cpu(resp->veb_seid);
2187
2188 return status;
2189}
2190
2191/**
2192 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2193 * @hw: pointer to the hw struct
2194 * @veb_seid: the SEID of the VEB to query
2195 * @switch_id: the uplink switch id
2196 * @floating: set to true if the VEB is floating
2197 * @statistic_index: index of the stats counter block for this VEB
2198 * @vebs_used: number of VEB's used by function
2199 * @vebs_free: total VEB's not reserved by any function
2200 * @cmd_details: pointer to command details structure or NULL
2201 *
2202 * This retrieves the parameters for a particular VEB, specified by
2203 * uplink_seid, and returns them to the caller.
2204 **/
2205int i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2206 u16 veb_seid, u16 *switch_id,
2207 bool *floating, u16 *statistic_index,
2208 u16 *vebs_used, u16 *vebs_free,
2209 struct i40e_asq_cmd_details *cmd_details)
2210{
2211 struct i40e_aq_desc desc;
2212 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2213 (struct i40e_aqc_get_veb_parameters_completion *)
2214 &desc.params.raw;
2215 int status;
2216
2217 if (veb_seid == 0)
2218 return -EINVAL;
2219
2220 i40e_fill_default_direct_cmd_desc(&desc,
2221 i40e_aqc_opc_get_veb_parameters);
2222 cmd_resp->seid = cpu_to_le16(veb_seid);
2223
2224 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2225 if (status)
2226 goto get_veb_exit;
2227
2228 if (switch_id)
2229 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2230 if (statistic_index)
2231 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2232 if (vebs_used)
2233 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2234 if (vebs_free)
2235 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2236 if (floating) {
2237 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2238
2239 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2240 *floating = true;
2241 else
2242 *floating = false;
2243 }
2244
2245get_veb_exit:
2246 return status;
2247}
2248
2249/**
2250 * i40e_prepare_add_macvlan
2251 * @mv_list: list of macvlans to be added
2252 * @desc: pointer to AQ descriptor structure
2253 * @count: length of the list
2254 * @seid: VSI for the mac address
2255 *
2256 * Internal helper function that prepares the add macvlan request
2257 * and returns the buffer size.
2258 **/
2259static u16
2260i40e_prepare_add_macvlan(struct i40e_aqc_add_macvlan_element_data *mv_list,
2261 struct i40e_aq_desc *desc, u16 count, u16 seid)
2262{
2263 struct i40e_aqc_macvlan *cmd =
2264 (struct i40e_aqc_macvlan *)&desc->params.raw;
2265 u16 buf_size;
2266 int i;
2267
2268 buf_size = count * sizeof(*mv_list);
2269
2270 /* prep the rest of the request */
2271 i40e_fill_default_direct_cmd_desc(desc, i40e_aqc_opc_add_macvlan);
2272 cmd->num_addresses = cpu_to_le16(count);
2273 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2274 cmd->seid[1] = 0;
2275 cmd->seid[2] = 0;
2276
2277 for (i = 0; i < count; i++)
2278 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2279 mv_list[i].flags |=
2280 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2281
2282 desc->flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2283 if (buf_size > I40E_AQ_LARGE_BUF)
2284 desc->flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2285
2286 return buf_size;
2287}
2288
2289/**
2290 * i40e_aq_add_macvlan
2291 * @hw: pointer to the hw struct
2292 * @seid: VSI for the mac address
2293 * @mv_list: list of macvlans to be added
2294 * @count: length of the list
2295 * @cmd_details: pointer to command details structure or NULL
2296 *
2297 * Add MAC/VLAN addresses to the HW filtering
2298 **/
2299int
2300i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2301 struct i40e_aqc_add_macvlan_element_data *mv_list,
2302 u16 count, struct i40e_asq_cmd_details *cmd_details)
2303{
2304 struct i40e_aq_desc desc;
2305 u16 buf_size;
2306
2307 if (count == 0 || !mv_list || !hw)
2308 return -EINVAL;
2309
2310 buf_size = i40e_prepare_add_macvlan(mv_list, &desc, count, seid);
2311
2312 return i40e_asq_send_command_atomic(hw, &desc, mv_list, buf_size,
2313 cmd_details, true);
2314}
2315
2316/**
2317 * i40e_aq_add_macvlan_v2
2318 * @hw: pointer to the hw struct
2319 * @seid: VSI for the mac address
2320 * @mv_list: list of macvlans to be added
2321 * @count: length of the list
2322 * @cmd_details: pointer to command details structure or NULL
2323 * @aq_status: pointer to Admin Queue status return value
2324 *
2325 * Add MAC/VLAN addresses to the HW filtering.
2326 * The _v2 version returns the last Admin Queue status in aq_status
2327 * to avoid race conditions in access to hw->aq.asq_last_status.
2328 * It also calls _v2 versions of asq_send_command functions to
2329 * get the aq_status on the stack.
2330 **/
2331int
2332i40e_aq_add_macvlan_v2(struct i40e_hw *hw, u16 seid,
2333 struct i40e_aqc_add_macvlan_element_data *mv_list,
2334 u16 count, struct i40e_asq_cmd_details *cmd_details,
2335 enum i40e_admin_queue_err *aq_status)
2336{
2337 struct i40e_aq_desc desc;
2338 u16 buf_size;
2339
2340 if (count == 0 || !mv_list || !hw)
2341 return -EINVAL;
2342
2343 buf_size = i40e_prepare_add_macvlan(mv_list, &desc, count, seid);
2344
2345 return i40e_asq_send_command_atomic_v2(hw, &desc, mv_list, buf_size,
2346 cmd_details, true, aq_status);
2347}
2348
2349/**
2350 * i40e_aq_remove_macvlan
2351 * @hw: pointer to the hw struct
2352 * @seid: VSI for the mac address
2353 * @mv_list: list of macvlans to be removed
2354 * @count: length of the list
2355 * @cmd_details: pointer to command details structure or NULL
2356 *
2357 * Remove MAC/VLAN addresses from the HW filtering
2358 **/
2359int
2360i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2361 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2362 u16 count, struct i40e_asq_cmd_details *cmd_details)
2363{
2364 struct i40e_aq_desc desc;
2365 struct i40e_aqc_macvlan *cmd =
2366 (struct i40e_aqc_macvlan *)&desc.params.raw;
2367 u16 buf_size;
2368 int status;
2369
2370 if (count == 0 || !mv_list || !hw)
2371 return -EINVAL;
2372
2373 buf_size = count * sizeof(*mv_list);
2374
2375 /* prep the rest of the request */
2376 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2377 cmd->num_addresses = cpu_to_le16(count);
2378 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2379 cmd->seid[1] = 0;
2380 cmd->seid[2] = 0;
2381
2382 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2383 if (buf_size > I40E_AQ_LARGE_BUF)
2384 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2385
2386 status = i40e_asq_send_command_atomic(hw, &desc, mv_list, buf_size,
2387 cmd_details, true);
2388
2389 return status;
2390}
2391
2392/**
2393 * i40e_aq_remove_macvlan_v2
2394 * @hw: pointer to the hw struct
2395 * @seid: VSI for the mac address
2396 * @mv_list: list of macvlans to be removed
2397 * @count: length of the list
2398 * @cmd_details: pointer to command details structure or NULL
2399 * @aq_status: pointer to Admin Queue status return value
2400 *
2401 * Remove MAC/VLAN addresses from the HW filtering.
2402 * The _v2 version returns the last Admin Queue status in aq_status
2403 * to avoid race conditions in access to hw->aq.asq_last_status.
2404 * It also calls _v2 versions of asq_send_command functions to
2405 * get the aq_status on the stack.
2406 **/
2407int
2408i40e_aq_remove_macvlan_v2(struct i40e_hw *hw, u16 seid,
2409 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2410 u16 count, struct i40e_asq_cmd_details *cmd_details,
2411 enum i40e_admin_queue_err *aq_status)
2412{
2413 struct i40e_aqc_macvlan *cmd;
2414 struct i40e_aq_desc desc;
2415 u16 buf_size;
2416
2417 if (count == 0 || !mv_list || !hw)
2418 return -EINVAL;
2419
2420 buf_size = count * sizeof(*mv_list);
2421
2422 /* prep the rest of the request */
2423 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2424 cmd = (struct i40e_aqc_macvlan *)&desc.params.raw;
2425 cmd->num_addresses = cpu_to_le16(count);
2426 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2427 cmd->seid[1] = 0;
2428 cmd->seid[2] = 0;
2429
2430 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2431 if (buf_size > I40E_AQ_LARGE_BUF)
2432 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2433
2434 return i40e_asq_send_command_atomic_v2(hw, &desc, mv_list, buf_size,
2435 cmd_details, true, aq_status);
2436}
2437
2438/**
2439 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2440 * @hw: pointer to the hw struct
2441 * @opcode: AQ opcode for add or delete mirror rule
2442 * @sw_seid: Switch SEID (to which rule refers)
2443 * @rule_type: Rule Type (ingress/egress/VLAN)
2444 * @id: Destination VSI SEID or Rule ID
2445 * @count: length of the list
2446 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2447 * @cmd_details: pointer to command details structure or NULL
2448 * @rule_id: Rule ID returned from FW
2449 * @rules_used: Number of rules used in internal switch
2450 * @rules_free: Number of rules free in internal switch
2451 *
2452 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2453 * VEBs/VEPA elements only
2454 **/
2455static int i40e_mirrorrule_op(struct i40e_hw *hw,
2456 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2457 u16 count, __le16 *mr_list,
2458 struct i40e_asq_cmd_details *cmd_details,
2459 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2460{
2461 struct i40e_aq_desc desc;
2462 struct i40e_aqc_add_delete_mirror_rule *cmd =
2463 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2464 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2465 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2466 u16 buf_size;
2467 int status;
2468
2469 buf_size = count * sizeof(*mr_list);
2470
2471 /* prep the rest of the request */
2472 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2473 cmd->seid = cpu_to_le16(sw_seid);
2474 cmd->rule_type = cpu_to_le16(rule_type &
2475 I40E_AQC_MIRROR_RULE_TYPE_MASK);
2476 cmd->num_entries = cpu_to_le16(count);
2477 /* Dest VSI for add, rule_id for delete */
2478 cmd->destination = cpu_to_le16(id);
2479 if (mr_list) {
2480 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2481 I40E_AQ_FLAG_RD));
2482 if (buf_size > I40E_AQ_LARGE_BUF)
2483 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2484 }
2485
2486 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2487 cmd_details);
2488 if (!status ||
2489 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2490 if (rule_id)
2491 *rule_id = le16_to_cpu(resp->rule_id);
2492 if (rules_used)
2493 *rules_used = le16_to_cpu(resp->mirror_rules_used);
2494 if (rules_free)
2495 *rules_free = le16_to_cpu(resp->mirror_rules_free);
2496 }
2497 return status;
2498}
2499
2500/**
2501 * i40e_aq_add_mirrorrule - add a mirror rule
2502 * @hw: pointer to the hw struct
2503 * @sw_seid: Switch SEID (to which rule refers)
2504 * @rule_type: Rule Type (ingress/egress/VLAN)
2505 * @dest_vsi: SEID of VSI to which packets will be mirrored
2506 * @count: length of the list
2507 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2508 * @cmd_details: pointer to command details structure or NULL
2509 * @rule_id: Rule ID returned from FW
2510 * @rules_used: Number of rules used in internal switch
2511 * @rules_free: Number of rules free in internal switch
2512 *
2513 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2514 **/
2515int i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2516 u16 rule_type, u16 dest_vsi, u16 count,
2517 __le16 *mr_list,
2518 struct i40e_asq_cmd_details *cmd_details,
2519 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2520{
2521 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2522 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2523 if (count == 0 || !mr_list)
2524 return -EINVAL;
2525 }
2526
2527 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2528 rule_type, dest_vsi, count, mr_list,
2529 cmd_details, rule_id, rules_used, rules_free);
2530}
2531
2532/**
2533 * i40e_aq_delete_mirrorrule - delete a mirror rule
2534 * @hw: pointer to the hw struct
2535 * @sw_seid: Switch SEID (to which rule refers)
2536 * @rule_type: Rule Type (ingress/egress/VLAN)
2537 * @count: length of the list
2538 * @rule_id: Rule ID that is returned in the receive desc as part of
2539 * add_mirrorrule.
2540 * @mr_list: list of mirrored VLAN IDs to be removed
2541 * @cmd_details: pointer to command details structure or NULL
2542 * @rules_used: Number of rules used in internal switch
2543 * @rules_free: Number of rules free in internal switch
2544 *
2545 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2546 **/
2547int i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2548 u16 rule_type, u16 rule_id, u16 count,
2549 __le16 *mr_list,
2550 struct i40e_asq_cmd_details *cmd_details,
2551 u16 *rules_used, u16 *rules_free)
2552{
2553 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
2554 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2555 /* count and mr_list shall be valid for rule_type INGRESS VLAN
2556 * mirroring. For other rule_type, count and rule_type should
2557 * not matter.
2558 */
2559 if (count == 0 || !mr_list)
2560 return -EINVAL;
2561 }
2562
2563 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2564 rule_type, rule_id, count, mr_list,
2565 cmd_details, NULL, rules_used, rules_free);
2566}
2567
2568/**
2569 * i40e_aq_send_msg_to_vf
2570 * @hw: pointer to the hardware structure
2571 * @vfid: VF id to send msg
2572 * @v_opcode: opcodes for VF-PF communication
2573 * @v_retval: return error code
2574 * @msg: pointer to the msg buffer
2575 * @msglen: msg length
2576 * @cmd_details: pointer to command details
2577 *
2578 * send msg to vf
2579 **/
2580int i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2581 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2582 struct i40e_asq_cmd_details *cmd_details)
2583{
2584 struct i40e_aq_desc desc;
2585 struct i40e_aqc_pf_vf_message *cmd =
2586 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2587 int status;
2588
2589 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2590 cmd->id = cpu_to_le32(vfid);
2591 desc.cookie_high = cpu_to_le32(v_opcode);
2592 desc.cookie_low = cpu_to_le32(v_retval);
2593 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2594 if (msglen) {
2595 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2596 I40E_AQ_FLAG_RD));
2597 if (msglen > I40E_AQ_LARGE_BUF)
2598 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2599 desc.datalen = cpu_to_le16(msglen);
2600 }
2601 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2602
2603 return status;
2604}
2605
2606/**
2607 * i40e_aq_debug_read_register
2608 * @hw: pointer to the hw struct
2609 * @reg_addr: register address
2610 * @reg_val: register value
2611 * @cmd_details: pointer to command details structure or NULL
2612 *
2613 * Read the register using the admin queue commands
2614 **/
2615int i40e_aq_debug_read_register(struct i40e_hw *hw,
2616 u32 reg_addr, u64 *reg_val,
2617 struct i40e_asq_cmd_details *cmd_details)
2618{
2619 struct i40e_aq_desc desc;
2620 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2621 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2622 int status;
2623
2624 if (reg_val == NULL)
2625 return -EINVAL;
2626
2627 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2628
2629 cmd_resp->address = cpu_to_le32(reg_addr);
2630
2631 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2632
2633 if (!status) {
2634 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2635 (u64)le32_to_cpu(cmd_resp->value_low);
2636 }
2637
2638 return status;
2639}
2640
2641/**
2642 * i40e_aq_debug_write_register
2643 * @hw: pointer to the hw struct
2644 * @reg_addr: register address
2645 * @reg_val: register value
2646 * @cmd_details: pointer to command details structure or NULL
2647 *
2648 * Write to a register using the admin queue commands
2649 **/
2650int i40e_aq_debug_write_register(struct i40e_hw *hw,
2651 u32 reg_addr, u64 reg_val,
2652 struct i40e_asq_cmd_details *cmd_details)
2653{
2654 struct i40e_aq_desc desc;
2655 struct i40e_aqc_debug_reg_read_write *cmd =
2656 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2657 int status;
2658
2659 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2660
2661 cmd->address = cpu_to_le32(reg_addr);
2662 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2663 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2664
2665 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2666
2667 return status;
2668}
2669
2670/**
2671 * i40e_aq_request_resource
2672 * @hw: pointer to the hw struct
2673 * @resource: resource id
2674 * @access: access type
2675 * @sdp_number: resource number
2676 * @timeout: the maximum time in ms that the driver may hold the resource
2677 * @cmd_details: pointer to command details structure or NULL
2678 *
2679 * requests common resource using the admin queue commands
2680 **/
2681int i40e_aq_request_resource(struct i40e_hw *hw,
2682 enum i40e_aq_resources_ids resource,
2683 enum i40e_aq_resource_access_type access,
2684 u8 sdp_number, u64 *timeout,
2685 struct i40e_asq_cmd_details *cmd_details)
2686{
2687 struct i40e_aq_desc desc;
2688 struct i40e_aqc_request_resource *cmd_resp =
2689 (struct i40e_aqc_request_resource *)&desc.params.raw;
2690 int status;
2691
2692 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2693
2694 cmd_resp->resource_id = cpu_to_le16(resource);
2695 cmd_resp->access_type = cpu_to_le16(access);
2696 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2697
2698 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2699 /* The completion specifies the maximum time in ms that the driver
2700 * may hold the resource in the Timeout field.
2701 * If the resource is held by someone else, the command completes with
2702 * busy return value and the timeout field indicates the maximum time
2703 * the current owner of the resource has to free it.
2704 */
2705 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2706 *timeout = le32_to_cpu(cmd_resp->timeout);
2707
2708 return status;
2709}
2710
2711/**
2712 * i40e_aq_release_resource
2713 * @hw: pointer to the hw struct
2714 * @resource: resource id
2715 * @sdp_number: resource number
2716 * @cmd_details: pointer to command details structure or NULL
2717 *
2718 * release common resource using the admin queue commands
2719 **/
2720int i40e_aq_release_resource(struct i40e_hw *hw,
2721 enum i40e_aq_resources_ids resource,
2722 u8 sdp_number,
2723 struct i40e_asq_cmd_details *cmd_details)
2724{
2725 struct i40e_aq_desc desc;
2726 struct i40e_aqc_request_resource *cmd =
2727 (struct i40e_aqc_request_resource *)&desc.params.raw;
2728 int status;
2729
2730 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2731
2732 cmd->resource_id = cpu_to_le16(resource);
2733 cmd->resource_number = cpu_to_le32(sdp_number);
2734
2735 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2736
2737 return status;
2738}
2739
2740/**
2741 * i40e_aq_read_nvm
2742 * @hw: pointer to the hw struct
2743 * @module_pointer: module pointer location in words from the NVM beginning
2744 * @offset: byte offset from the module beginning
2745 * @length: length of the section to be read (in bytes from the offset)
2746 * @data: command buffer (size [bytes] = length)
2747 * @last_command: tells if this is the last command in a series
2748 * @cmd_details: pointer to command details structure or NULL
2749 *
2750 * Read the NVM using the admin queue commands
2751 **/
2752int i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2753 u32 offset, u16 length, void *data,
2754 bool last_command,
2755 struct i40e_asq_cmd_details *cmd_details)
2756{
2757 struct i40e_aq_desc desc;
2758 struct i40e_aqc_nvm_update *cmd =
2759 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2760 int status;
2761
2762 /* In offset the highest byte must be zeroed. */
2763 if (offset & 0xFF000000) {
2764 status = -EINVAL;
2765 goto i40e_aq_read_nvm_exit;
2766 }
2767
2768 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2769
2770 /* If this is the last command in a series, set the proper flag. */
2771 if (last_command)
2772 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2773 cmd->module_pointer = module_pointer;
2774 cmd->offset = cpu_to_le32(offset);
2775 cmd->length = cpu_to_le16(length);
2776
2777 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2778 if (length > I40E_AQ_LARGE_BUF)
2779 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2780
2781 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2782
2783i40e_aq_read_nvm_exit:
2784 return status;
2785}
2786
2787/**
2788 * i40e_aq_erase_nvm
2789 * @hw: pointer to the hw struct
2790 * @module_pointer: module pointer location in words from the NVM beginning
2791 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2792 * @length: length of the section to be erased (expressed in 4 KB)
2793 * @last_command: tells if this is the last command in a series
2794 * @cmd_details: pointer to command details structure or NULL
2795 *
2796 * Erase the NVM sector using the admin queue commands
2797 **/
2798int i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2799 u32 offset, u16 length, bool last_command,
2800 struct i40e_asq_cmd_details *cmd_details)
2801{
2802 struct i40e_aq_desc desc;
2803 struct i40e_aqc_nvm_update *cmd =
2804 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2805 int status;
2806
2807 /* In offset the highest byte must be zeroed. */
2808 if (offset & 0xFF000000) {
2809 status = -EINVAL;
2810 goto i40e_aq_erase_nvm_exit;
2811 }
2812
2813 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2814
2815 /* If this is the last command in a series, set the proper flag. */
2816 if (last_command)
2817 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2818 cmd->module_pointer = module_pointer;
2819 cmd->offset = cpu_to_le32(offset);
2820 cmd->length = cpu_to_le16(length);
2821
2822 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2823
2824i40e_aq_erase_nvm_exit:
2825 return status;
2826}
2827
2828/**
2829 * i40e_parse_discover_capabilities
2830 * @hw: pointer to the hw struct
2831 * @buff: pointer to a buffer containing device/function capability records
2832 * @cap_count: number of capability records in the list
2833 * @list_type_opc: type of capabilities list to parse
2834 *
2835 * Parse the device/function capabilities list.
2836 **/
2837static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2838 u32 cap_count,
2839 enum i40e_admin_queue_opc list_type_opc)
2840{
2841 struct i40e_aqc_list_capabilities_element_resp *cap;
2842 u32 valid_functions, num_functions;
2843 u32 number, logical_id, phys_id;
2844 struct i40e_hw_capabilities *p;
2845 u16 id, ocp_cfg_word0;
2846 u8 major_rev;
2847 int status;
2848 u32 i = 0;
2849
2850 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2851
2852 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2853 p = &hw->dev_caps;
2854 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2855 p = &hw->func_caps;
2856 else
2857 return;
2858
2859 for (i = 0; i < cap_count; i++, cap++) {
2860 id = le16_to_cpu(cap->id);
2861 number = le32_to_cpu(cap->number);
2862 logical_id = le32_to_cpu(cap->logical_id);
2863 phys_id = le32_to_cpu(cap->phys_id);
2864 major_rev = cap->major_rev;
2865
2866 switch (id) {
2867 case I40E_AQ_CAP_ID_SWITCH_MODE:
2868 p->switch_mode = number;
2869 break;
2870 case I40E_AQ_CAP_ID_MNG_MODE:
2871 p->management_mode = number;
2872 if (major_rev > 1) {
2873 p->mng_protocols_over_mctp = logical_id;
2874 i40e_debug(hw, I40E_DEBUG_INIT,
2875 "HW Capability: Protocols over MCTP = %d\n",
2876 p->mng_protocols_over_mctp);
2877 } else {
2878 p->mng_protocols_over_mctp = 0;
2879 }
2880 break;
2881 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
2882 p->npar_enable = number;
2883 break;
2884 case I40E_AQ_CAP_ID_OS2BMC_CAP:
2885 p->os2bmc = number;
2886 break;
2887 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
2888 p->valid_functions = number;
2889 break;
2890 case I40E_AQ_CAP_ID_SRIOV:
2891 if (number == 1)
2892 p->sr_iov_1_1 = true;
2893 break;
2894 case I40E_AQ_CAP_ID_VF:
2895 p->num_vfs = number;
2896 p->vf_base_id = logical_id;
2897 break;
2898 case I40E_AQ_CAP_ID_VMDQ:
2899 if (number == 1)
2900 p->vmdq = true;
2901 break;
2902 case I40E_AQ_CAP_ID_8021QBG:
2903 if (number == 1)
2904 p->evb_802_1_qbg = true;
2905 break;
2906 case I40E_AQ_CAP_ID_8021QBR:
2907 if (number == 1)
2908 p->evb_802_1_qbh = true;
2909 break;
2910 case I40E_AQ_CAP_ID_VSI:
2911 p->num_vsis = number;
2912 break;
2913 case I40E_AQ_CAP_ID_DCB:
2914 if (number == 1) {
2915 p->dcb = true;
2916 p->enabled_tcmap = logical_id;
2917 p->maxtc = phys_id;
2918 }
2919 break;
2920 case I40E_AQ_CAP_ID_FCOE:
2921 if (number == 1)
2922 p->fcoe = true;
2923 break;
2924 case I40E_AQ_CAP_ID_ISCSI:
2925 if (number == 1)
2926 p->iscsi = true;
2927 break;
2928 case I40E_AQ_CAP_ID_RSS:
2929 p->rss = true;
2930 p->rss_table_size = number;
2931 p->rss_table_entry_width = logical_id;
2932 break;
2933 case I40E_AQ_CAP_ID_RXQ:
2934 p->num_rx_qp = number;
2935 p->base_queue = phys_id;
2936 break;
2937 case I40E_AQ_CAP_ID_TXQ:
2938 p->num_tx_qp = number;
2939 p->base_queue = phys_id;
2940 break;
2941 case I40E_AQ_CAP_ID_MSIX:
2942 p->num_msix_vectors = number;
2943 i40e_debug(hw, I40E_DEBUG_INIT,
2944 "HW Capability: MSIX vector count = %d\n",
2945 p->num_msix_vectors);
2946 break;
2947 case I40E_AQ_CAP_ID_VF_MSIX:
2948 p->num_msix_vectors_vf = number;
2949 break;
2950 case I40E_AQ_CAP_ID_FLEX10:
2951 if (major_rev == 1) {
2952 if (number == 1) {
2953 p->flex10_enable = true;
2954 p->flex10_capable = true;
2955 }
2956 } else {
2957 /* Capability revision >= 2 */
2958 if (number & 1)
2959 p->flex10_enable = true;
2960 if (number & 2)
2961 p->flex10_capable = true;
2962 }
2963 p->flex10_mode = logical_id;
2964 p->flex10_status = phys_id;
2965 break;
2966 case I40E_AQ_CAP_ID_CEM:
2967 if (number == 1)
2968 p->mgmt_cem = true;
2969 break;
2970 case I40E_AQ_CAP_ID_IWARP:
2971 if (number == 1)
2972 p->iwarp = true;
2973 break;
2974 case I40E_AQ_CAP_ID_LED:
2975 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2976 p->led[phys_id] = true;
2977 break;
2978 case I40E_AQ_CAP_ID_SDP:
2979 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2980 p->sdp[phys_id] = true;
2981 break;
2982 case I40E_AQ_CAP_ID_MDIO:
2983 if (number == 1) {
2984 p->mdio_port_num = phys_id;
2985 p->mdio_port_mode = logical_id;
2986 }
2987 break;
2988 case I40E_AQ_CAP_ID_1588:
2989 if (number == 1)
2990 p->ieee_1588 = true;
2991 break;
2992 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
2993 p->fd = true;
2994 p->fd_filters_guaranteed = number;
2995 p->fd_filters_best_effort = logical_id;
2996 break;
2997 case I40E_AQ_CAP_ID_WSR_PROT:
2998 p->wr_csr_prot = (u64)number;
2999 p->wr_csr_prot |= (u64)logical_id << 32;
3000 break;
3001 case I40E_AQ_CAP_ID_NVM_MGMT:
3002 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3003 p->sec_rev_disabled = true;
3004 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3005 p->update_disabled = true;
3006 break;
3007 default:
3008 break;
3009 }
3010 }
3011
3012 if (p->fcoe)
3013 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3014
3015 /* Software override ensuring FCoE is disabled if npar or mfp
3016 * mode because it is not supported in these modes.
3017 */
3018 if (p->npar_enable || p->flex10_enable)
3019 p->fcoe = false;
3020
3021 /* count the enabled ports (aka the "not disabled" ports) */
3022 hw->num_ports = 0;
3023 for (i = 0; i < 4; i++) {
3024 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3025 u64 port_cfg = 0;
3026
3027 /* use AQ read to get the physical register offset instead
3028 * of the port relative offset
3029 */
3030 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3031 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3032 hw->num_ports++;
3033 }
3034
3035 /* OCP cards case: if a mezz is removed the Ethernet port is at
3036 * disabled state in PRTGEN_CNF register. Additional NVM read is
3037 * needed in order to check if we are dealing with OCP card.
3038 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
3039 * physical ports results in wrong partition id calculation and thus
3040 * not supporting WoL.
3041 */
3042 if (hw->mac.type == I40E_MAC_X722) {
3043 if (!i40e_acquire_nvm(hw, I40E_RESOURCE_READ)) {
3044 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
3045 2 * I40E_SR_OCP_CFG_WORD0,
3046 sizeof(ocp_cfg_word0),
3047 &ocp_cfg_word0, true, NULL);
3048 if (!status &&
3049 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
3050 hw->num_ports = 4;
3051 i40e_release_nvm(hw);
3052 }
3053 }
3054
3055 valid_functions = p->valid_functions;
3056 num_functions = 0;
3057 while (valid_functions) {
3058 if (valid_functions & 1)
3059 num_functions++;
3060 valid_functions >>= 1;
3061 }
3062
3063 /* partition id is 1-based, and functions are evenly spread
3064 * across the ports as partitions
3065 */
3066 if (hw->num_ports != 0) {
3067 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3068 hw->num_partitions = num_functions / hw->num_ports;
3069 }
3070
3071 /* additional HW specific goodies that might
3072 * someday be HW version specific
3073 */
3074 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3075}
3076
3077/**
3078 * i40e_aq_discover_capabilities
3079 * @hw: pointer to the hw struct
3080 * @buff: a virtual buffer to hold the capabilities
3081 * @buff_size: Size of the virtual buffer
3082 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3083 * @list_type_opc: capabilities type to discover - pass in the command opcode
3084 * @cmd_details: pointer to command details structure or NULL
3085 *
3086 * Get the device capabilities descriptions from the firmware
3087 **/
3088int i40e_aq_discover_capabilities(struct i40e_hw *hw,
3089 void *buff, u16 buff_size, u16 *data_size,
3090 enum i40e_admin_queue_opc list_type_opc,
3091 struct i40e_asq_cmd_details *cmd_details)
3092{
3093 struct i40e_aqc_list_capabilites *cmd;
3094 struct i40e_aq_desc desc;
3095 int status = 0;
3096
3097 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3098
3099 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3100 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3101 status = -EINVAL;
3102 goto exit;
3103 }
3104
3105 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3106
3107 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3108 if (buff_size > I40E_AQ_LARGE_BUF)
3109 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3110
3111 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3112 *data_size = le16_to_cpu(desc.datalen);
3113
3114 if (status)
3115 goto exit;
3116
3117 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3118 list_type_opc);
3119
3120exit:
3121 return status;
3122}
3123
3124/**
3125 * i40e_aq_update_nvm
3126 * @hw: pointer to the hw struct
3127 * @module_pointer: module pointer location in words from the NVM beginning
3128 * @offset: byte offset from the module beginning
3129 * @length: length of the section to be written (in bytes from the offset)
3130 * @data: command buffer (size [bytes] = length)
3131 * @last_command: tells if this is the last command in a series
3132 * @preservation_flags: Preservation mode flags
3133 * @cmd_details: pointer to command details structure or NULL
3134 *
3135 * Update the NVM using the admin queue commands
3136 **/
3137int i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3138 u32 offset, u16 length, void *data,
3139 bool last_command, u8 preservation_flags,
3140 struct i40e_asq_cmd_details *cmd_details)
3141{
3142 struct i40e_aq_desc desc;
3143 struct i40e_aqc_nvm_update *cmd =
3144 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3145 int status;
3146
3147 /* In offset the highest byte must be zeroed. */
3148 if (offset & 0xFF000000) {
3149 status = -EINVAL;
3150 goto i40e_aq_update_nvm_exit;
3151 }
3152
3153 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3154
3155 /* If this is the last command in a series, set the proper flag. */
3156 if (last_command)
3157 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3158 if (hw->mac.type == I40E_MAC_X722) {
3159 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
3160 cmd->command_flags |=
3161 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
3162 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3163 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
3164 cmd->command_flags |=
3165 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
3166 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3167 }
3168 cmd->module_pointer = module_pointer;
3169 cmd->offset = cpu_to_le32(offset);
3170 cmd->length = cpu_to_le16(length);
3171
3172 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3173 if (length > I40E_AQ_LARGE_BUF)
3174 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3175
3176 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3177
3178i40e_aq_update_nvm_exit:
3179 return status;
3180}
3181
3182/**
3183 * i40e_aq_rearrange_nvm
3184 * @hw: pointer to the hw struct
3185 * @rearrange_nvm: defines direction of rearrangement
3186 * @cmd_details: pointer to command details structure or NULL
3187 *
3188 * Rearrange NVM structure, available only for transition FW
3189 **/
3190int i40e_aq_rearrange_nvm(struct i40e_hw *hw,
3191 u8 rearrange_nvm,
3192 struct i40e_asq_cmd_details *cmd_details)
3193{
3194 struct i40e_aqc_nvm_update *cmd;
3195 struct i40e_aq_desc desc;
3196 int status;
3197
3198 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
3199
3200 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3201
3202 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
3203 I40E_AQ_NVM_REARRANGE_TO_STRUCT);
3204
3205 if (!rearrange_nvm) {
3206 status = -EINVAL;
3207 goto i40e_aq_rearrange_nvm_exit;
3208 }
3209
3210 cmd->command_flags |= rearrange_nvm;
3211 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3212
3213i40e_aq_rearrange_nvm_exit:
3214 return status;
3215}
3216
3217/**
3218 * i40e_aq_get_lldp_mib
3219 * @hw: pointer to the hw struct
3220 * @bridge_type: type of bridge requested
3221 * @mib_type: Local, Remote or both Local and Remote MIBs
3222 * @buff: pointer to a user supplied buffer to store the MIB block
3223 * @buff_size: size of the buffer (in bytes)
3224 * @local_len : length of the returned Local LLDP MIB
3225 * @remote_len: length of the returned Remote LLDP MIB
3226 * @cmd_details: pointer to command details structure or NULL
3227 *
3228 * Requests the complete LLDP MIB (entire packet).
3229 **/
3230int i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3231 u8 mib_type, void *buff, u16 buff_size,
3232 u16 *local_len, u16 *remote_len,
3233 struct i40e_asq_cmd_details *cmd_details)
3234{
3235 struct i40e_aq_desc desc;
3236 struct i40e_aqc_lldp_get_mib *cmd =
3237 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3238 struct i40e_aqc_lldp_get_mib *resp =
3239 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3240 int status;
3241
3242 if (buff_size == 0 || !buff)
3243 return -EINVAL;
3244
3245 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3246 /* Indirect Command */
3247 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3248
3249 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3250 cmd->type |= FIELD_PREP(I40E_AQ_LLDP_BRIDGE_TYPE_MASK, bridge_type);
3251
3252 desc.datalen = cpu_to_le16(buff_size);
3253
3254 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3255 if (buff_size > I40E_AQ_LARGE_BUF)
3256 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3257
3258 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3259 if (!status) {
3260 if (local_len != NULL)
3261 *local_len = le16_to_cpu(resp->local_len);
3262 if (remote_len != NULL)
3263 *remote_len = le16_to_cpu(resp->remote_len);
3264 }
3265
3266 return status;
3267}
3268
3269/**
3270 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3271 * @hw: pointer to the hw struct
3272 * @mib_type: Local, Remote or both Local and Remote MIBs
3273 * @buff: pointer to a user supplied buffer to store the MIB block
3274 * @buff_size: size of the buffer (in bytes)
3275 * @cmd_details: pointer to command details structure or NULL
3276 *
3277 * Set the LLDP MIB.
3278 **/
3279int
3280i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3281 u8 mib_type, void *buff, u16 buff_size,
3282 struct i40e_asq_cmd_details *cmd_details)
3283{
3284 struct i40e_aqc_lldp_set_local_mib *cmd;
3285 struct i40e_aq_desc desc;
3286 int status;
3287
3288 cmd = (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3289 if (buff_size == 0 || !buff)
3290 return -EINVAL;
3291
3292 i40e_fill_default_direct_cmd_desc(&desc,
3293 i40e_aqc_opc_lldp_set_local_mib);
3294 /* Indirect Command */
3295 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3296 if (buff_size > I40E_AQ_LARGE_BUF)
3297 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3298 desc.datalen = cpu_to_le16(buff_size);
3299
3300 cmd->type = mib_type;
3301 cmd->length = cpu_to_le16(buff_size);
3302 cmd->address_high = cpu_to_le32(upper_32_bits((uintptr_t)buff));
3303 cmd->address_low = cpu_to_le32(lower_32_bits((uintptr_t)buff));
3304
3305 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3306 return status;
3307}
3308
3309/**
3310 * i40e_aq_cfg_lldp_mib_change_event
3311 * @hw: pointer to the hw struct
3312 * @enable_update: Enable or Disable event posting
3313 * @cmd_details: pointer to command details structure or NULL
3314 *
3315 * Enable or Disable posting of an event on ARQ when LLDP MIB
3316 * associated with the interface changes
3317 **/
3318int i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3319 bool enable_update,
3320 struct i40e_asq_cmd_details *cmd_details)
3321{
3322 struct i40e_aq_desc desc;
3323 struct i40e_aqc_lldp_update_mib *cmd =
3324 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3325 int status;
3326
3327 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3328
3329 if (!enable_update)
3330 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3331
3332 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3333
3334 return status;
3335}
3336
3337/**
3338 * i40e_aq_restore_lldp
3339 * @hw: pointer to the hw struct
3340 * @setting: pointer to factory setting variable or NULL
3341 * @restore: True if factory settings should be restored
3342 * @cmd_details: pointer to command details structure or NULL
3343 *
3344 * Restore LLDP Agent factory settings if @restore set to True. In other case
3345 * only returns factory setting in AQ response.
3346 **/
3347int
3348i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
3349 struct i40e_asq_cmd_details *cmd_details)
3350{
3351 struct i40e_aq_desc desc;
3352 struct i40e_aqc_lldp_restore *cmd =
3353 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
3354 int status;
3355
3356 if (!test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw->caps)) {
3357 i40e_debug(hw, I40E_DEBUG_ALL,
3358 "Restore LLDP not supported by current FW version.\n");
3359 return -ENODEV;
3360 }
3361
3362 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
3363
3364 if (restore)
3365 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
3366
3367 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3368
3369 if (setting)
3370 *setting = cmd->command & 1;
3371
3372 return status;
3373}
3374
3375/**
3376 * i40e_aq_stop_lldp
3377 * @hw: pointer to the hw struct
3378 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3379 * @persist: True if stop of LLDP should be persistent across power cycles
3380 * @cmd_details: pointer to command details structure or NULL
3381 *
3382 * Stop or Shutdown the embedded LLDP Agent
3383 **/
3384int i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3385 bool persist,
3386 struct i40e_asq_cmd_details *cmd_details)
3387{
3388 struct i40e_aq_desc desc;
3389 struct i40e_aqc_lldp_stop *cmd =
3390 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3391 int status;
3392
3393 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3394
3395 if (shutdown_agent)
3396 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3397
3398 if (persist) {
3399 if (test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw->caps))
3400 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
3401 else
3402 i40e_debug(hw, I40E_DEBUG_ALL,
3403 "Persistent Stop LLDP not supported by current FW version.\n");
3404 }
3405
3406 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3407
3408 return status;
3409}
3410
3411/**
3412 * i40e_aq_start_lldp
3413 * @hw: pointer to the hw struct
3414 * @persist: True if start of LLDP should be persistent across power cycles
3415 * @cmd_details: pointer to command details structure or NULL
3416 *
3417 * Start the embedded LLDP Agent on all ports.
3418 **/
3419int i40e_aq_start_lldp(struct i40e_hw *hw, bool persist,
3420 struct i40e_asq_cmd_details *cmd_details)
3421{
3422 struct i40e_aq_desc desc;
3423 struct i40e_aqc_lldp_start *cmd =
3424 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3425 int status;
3426
3427 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3428
3429 cmd->command = I40E_AQ_LLDP_AGENT_START;
3430
3431 if (persist) {
3432 if (test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw->caps))
3433 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
3434 else
3435 i40e_debug(hw, I40E_DEBUG_ALL,
3436 "Persistent Start LLDP not supported by current FW version.\n");
3437 }
3438
3439 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3440
3441 return status;
3442}
3443
3444/**
3445 * i40e_aq_set_dcb_parameters
3446 * @hw: pointer to the hw struct
3447 * @cmd_details: pointer to command details structure or NULL
3448 * @dcb_enable: True if DCB configuration needs to be applied
3449 *
3450 **/
3451int
3452i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
3453 struct i40e_asq_cmd_details *cmd_details)
3454{
3455 struct i40e_aq_desc desc;
3456 struct i40e_aqc_set_dcb_parameters *cmd =
3457 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
3458 int status;
3459
3460 if (!test_bit(I40E_HW_CAP_FW_LLDP_STOPPABLE, hw->caps))
3461 return -ENODEV;
3462
3463 i40e_fill_default_direct_cmd_desc(&desc,
3464 i40e_aqc_opc_set_dcb_parameters);
3465
3466 if (dcb_enable) {
3467 cmd->valid_flags = I40E_DCB_VALID;
3468 cmd->command = I40E_AQ_DCB_SET_AGENT;
3469 }
3470 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3471
3472 return status;
3473}
3474
3475/**
3476 * i40e_aq_get_cee_dcb_config
3477 * @hw: pointer to the hw struct
3478 * @buff: response buffer that stores CEE operational configuration
3479 * @buff_size: size of the buffer passed
3480 * @cmd_details: pointer to command details structure or NULL
3481 *
3482 * Get CEE DCBX mode operational configuration from firmware
3483 **/
3484int i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3485 void *buff, u16 buff_size,
3486 struct i40e_asq_cmd_details *cmd_details)
3487{
3488 struct i40e_aq_desc desc;
3489 int status;
3490
3491 if (buff_size == 0 || !buff)
3492 return -EINVAL;
3493
3494 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3495
3496 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3497 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3498 cmd_details);
3499
3500 return status;
3501}
3502
3503/**
3504 * i40e_aq_add_udp_tunnel
3505 * @hw: pointer to the hw struct
3506 * @udp_port: the UDP port to add in Host byte order
3507 * @protocol_index: protocol index type
3508 * @filter_index: pointer to filter index
3509 * @cmd_details: pointer to command details structure or NULL
3510 *
3511 * Note: Firmware expects the udp_port value to be in Little Endian format,
3512 * and this function will call cpu_to_le16 to convert from Host byte order to
3513 * Little Endian order.
3514 **/
3515int i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3516 u16 udp_port, u8 protocol_index,
3517 u8 *filter_index,
3518 struct i40e_asq_cmd_details *cmd_details)
3519{
3520 struct i40e_aq_desc desc;
3521 struct i40e_aqc_add_udp_tunnel *cmd =
3522 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3523 struct i40e_aqc_del_udp_tunnel_completion *resp =
3524 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3525 int status;
3526
3527 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3528
3529 cmd->udp_port = cpu_to_le16(udp_port);
3530 cmd->protocol_type = protocol_index;
3531
3532 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3533
3534 if (!status && filter_index)
3535 *filter_index = resp->index;
3536
3537 return status;
3538}
3539
3540/**
3541 * i40e_aq_del_udp_tunnel
3542 * @hw: pointer to the hw struct
3543 * @index: filter index
3544 * @cmd_details: pointer to command details structure or NULL
3545 **/
3546int i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3547 struct i40e_asq_cmd_details *cmd_details)
3548{
3549 struct i40e_aq_desc desc;
3550 struct i40e_aqc_remove_udp_tunnel *cmd =
3551 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3552 int status;
3553
3554 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3555
3556 cmd->index = index;
3557
3558 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3559
3560 return status;
3561}
3562
3563/**
3564 * i40e_aq_delete_element - Delete switch element
3565 * @hw: pointer to the hw struct
3566 * @seid: the SEID to delete from the switch
3567 * @cmd_details: pointer to command details structure or NULL
3568 *
3569 * This deletes a switch element from the switch.
3570 **/
3571int i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3572 struct i40e_asq_cmd_details *cmd_details)
3573{
3574 struct i40e_aq_desc desc;
3575 struct i40e_aqc_switch_seid *cmd =
3576 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3577 int status;
3578
3579 if (seid == 0)
3580 return -EINVAL;
3581
3582 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3583
3584 cmd->seid = cpu_to_le16(seid);
3585
3586 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0,
3587 cmd_details, true);
3588
3589 return status;
3590}
3591
3592/**
3593 * i40e_aq_dcb_updated - DCB Updated Command
3594 * @hw: pointer to the hw struct
3595 * @cmd_details: pointer to command details structure or NULL
3596 *
3597 * EMP will return when the shared RPB settings have been
3598 * recomputed and modified. The retval field in the descriptor
3599 * will be set to 0 when RPB is modified.
3600 **/
3601int i40e_aq_dcb_updated(struct i40e_hw *hw,
3602 struct i40e_asq_cmd_details *cmd_details)
3603{
3604 struct i40e_aq_desc desc;
3605 int status;
3606
3607 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3608
3609 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3610
3611 return status;
3612}
3613
3614/**
3615 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3616 * @hw: pointer to the hw struct
3617 * @seid: seid for the physical port/switching component/vsi
3618 * @buff: Indirect buffer to hold data parameters and response
3619 * @buff_size: Indirect buffer size
3620 * @opcode: Tx scheduler AQ command opcode
3621 * @cmd_details: pointer to command details structure or NULL
3622 *
3623 * Generic command handler for Tx scheduler AQ commands
3624 **/
3625static int i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3626 void *buff, u16 buff_size,
3627 enum i40e_admin_queue_opc opcode,
3628 struct i40e_asq_cmd_details *cmd_details)
3629{
3630 struct i40e_aq_desc desc;
3631 struct i40e_aqc_tx_sched_ind *cmd =
3632 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3633 int status;
3634 bool cmd_param_flag = false;
3635
3636 switch (opcode) {
3637 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3638 case i40e_aqc_opc_configure_vsi_tc_bw:
3639 case i40e_aqc_opc_enable_switching_comp_ets:
3640 case i40e_aqc_opc_modify_switching_comp_ets:
3641 case i40e_aqc_opc_disable_switching_comp_ets:
3642 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3643 case i40e_aqc_opc_configure_switching_comp_bw_config:
3644 cmd_param_flag = true;
3645 break;
3646 case i40e_aqc_opc_query_vsi_bw_config:
3647 case i40e_aqc_opc_query_vsi_ets_sla_config:
3648 case i40e_aqc_opc_query_switching_comp_ets_config:
3649 case i40e_aqc_opc_query_port_ets_config:
3650 case i40e_aqc_opc_query_switching_comp_bw_config:
3651 cmd_param_flag = false;
3652 break;
3653 default:
3654 return -EINVAL;
3655 }
3656
3657 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3658
3659 /* Indirect command */
3660 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3661 if (cmd_param_flag)
3662 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3663 if (buff_size > I40E_AQ_LARGE_BUF)
3664 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3665
3666 desc.datalen = cpu_to_le16(buff_size);
3667
3668 cmd->vsi_seid = cpu_to_le16(seid);
3669
3670 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3671
3672 return status;
3673}
3674
3675/**
3676 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3677 * @hw: pointer to the hw struct
3678 * @seid: VSI seid
3679 * @credit: BW limit credits (0 = disabled)
3680 * @max_credit: Max BW limit credits
3681 * @cmd_details: pointer to command details structure or NULL
3682 **/
3683int i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3684 u16 seid, u16 credit, u8 max_credit,
3685 struct i40e_asq_cmd_details *cmd_details)
3686{
3687 struct i40e_aq_desc desc;
3688 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3689 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3690 int status;
3691
3692 i40e_fill_default_direct_cmd_desc(&desc,
3693 i40e_aqc_opc_configure_vsi_bw_limit);
3694
3695 cmd->vsi_seid = cpu_to_le16(seid);
3696 cmd->credit = cpu_to_le16(credit);
3697 cmd->max_credit = max_credit;
3698
3699 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3700
3701 return status;
3702}
3703
3704/**
3705 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3706 * @hw: pointer to the hw struct
3707 * @seid: VSI seid
3708 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3709 * @cmd_details: pointer to command details structure or NULL
3710 **/
3711int i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3712 u16 seid,
3713 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3714 struct i40e_asq_cmd_details *cmd_details)
3715{
3716 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3717 i40e_aqc_opc_configure_vsi_tc_bw,
3718 cmd_details);
3719}
3720
3721/**
3722 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3723 * @hw: pointer to the hw struct
3724 * @seid: seid of the switching component connected to Physical Port
3725 * @ets_data: Buffer holding ETS parameters
3726 * @opcode: Tx scheduler AQ command opcode
3727 * @cmd_details: pointer to command details structure or NULL
3728 **/
3729int
3730i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3731 u16 seid,
3732 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3733 enum i40e_admin_queue_opc opcode,
3734 struct i40e_asq_cmd_details *cmd_details)
3735{
3736 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3737 sizeof(*ets_data), opcode, cmd_details);
3738}
3739
3740/**
3741 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3742 * @hw: pointer to the hw struct
3743 * @seid: seid of the switching component
3744 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3745 * @cmd_details: pointer to command details structure or NULL
3746 **/
3747int
3748i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3749 u16 seid,
3750 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3751 struct i40e_asq_cmd_details *cmd_details)
3752{
3753 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3754 i40e_aqc_opc_configure_switching_comp_bw_config,
3755 cmd_details);
3756}
3757
3758/**
3759 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3760 * @hw: pointer to the hw struct
3761 * @seid: seid of the VSI
3762 * @bw_data: Buffer to hold VSI BW configuration
3763 * @cmd_details: pointer to command details structure or NULL
3764 **/
3765int
3766i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3767 u16 seid,
3768 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3769 struct i40e_asq_cmd_details *cmd_details)
3770{
3771 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3772 i40e_aqc_opc_query_vsi_bw_config,
3773 cmd_details);
3774}
3775
3776/**
3777 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3778 * @hw: pointer to the hw struct
3779 * @seid: seid of the VSI
3780 * @bw_data: Buffer to hold VSI BW configuration per TC
3781 * @cmd_details: pointer to command details structure or NULL
3782 **/
3783int
3784i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3785 u16 seid,
3786 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3787 struct i40e_asq_cmd_details *cmd_details)
3788{
3789 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3790 i40e_aqc_opc_query_vsi_ets_sla_config,
3791 cmd_details);
3792}
3793
3794/**
3795 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3796 * @hw: pointer to the hw struct
3797 * @seid: seid of the switching component
3798 * @bw_data: Buffer to hold switching component's per TC BW config
3799 * @cmd_details: pointer to command details structure or NULL
3800 **/
3801int
3802i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3803 u16 seid,
3804 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3805 struct i40e_asq_cmd_details *cmd_details)
3806{
3807 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3808 i40e_aqc_opc_query_switching_comp_ets_config,
3809 cmd_details);
3810}
3811
3812/**
3813 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3814 * @hw: pointer to the hw struct
3815 * @seid: seid of the VSI or switching component connected to Physical Port
3816 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3817 * @cmd_details: pointer to command details structure or NULL
3818 **/
3819int
3820i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3821 u16 seid,
3822 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3823 struct i40e_asq_cmd_details *cmd_details)
3824{
3825 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3826 i40e_aqc_opc_query_port_ets_config,
3827 cmd_details);
3828}
3829
3830/**
3831 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3832 * @hw: pointer to the hw struct
3833 * @seid: seid of the switching component
3834 * @bw_data: Buffer to hold switching component's BW configuration
3835 * @cmd_details: pointer to command details structure or NULL
3836 **/
3837int
3838i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3839 u16 seid,
3840 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3841 struct i40e_asq_cmd_details *cmd_details)
3842{
3843 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3844 i40e_aqc_opc_query_switching_comp_bw_config,
3845 cmd_details);
3846}
3847
3848/**
3849 * i40e_validate_filter_settings
3850 * @hw: pointer to the hardware structure
3851 * @settings: Filter control settings
3852 *
3853 * Check and validate the filter control settings passed.
3854 * The function checks for the valid filter/context sizes being
3855 * passed for FCoE and PE.
3856 *
3857 * Returns 0 if the values passed are valid and within
3858 * range else returns an error.
3859 **/
3860static int
3861i40e_validate_filter_settings(struct i40e_hw *hw,
3862 struct i40e_filter_control_settings *settings)
3863{
3864 u32 fcoe_cntx_size, fcoe_filt_size;
3865 u32 fcoe_fmax;
3866 u32 val;
3867
3868 /* Validate FCoE settings passed */
3869 switch (settings->fcoe_filt_num) {
3870 case I40E_HASH_FILTER_SIZE_1K:
3871 case I40E_HASH_FILTER_SIZE_2K:
3872 case I40E_HASH_FILTER_SIZE_4K:
3873 case I40E_HASH_FILTER_SIZE_8K:
3874 case I40E_HASH_FILTER_SIZE_16K:
3875 case I40E_HASH_FILTER_SIZE_32K:
3876 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3877 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3878 break;
3879 default:
3880 return -EINVAL;
3881 }
3882
3883 switch (settings->fcoe_cntx_num) {
3884 case I40E_DMA_CNTX_SIZE_512:
3885 case I40E_DMA_CNTX_SIZE_1K:
3886 case I40E_DMA_CNTX_SIZE_2K:
3887 case I40E_DMA_CNTX_SIZE_4K:
3888 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3889 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3890 break;
3891 default:
3892 return -EINVAL;
3893 }
3894
3895 /* Validate PE settings passed */
3896 switch (settings->pe_filt_num) {
3897 case I40E_HASH_FILTER_SIZE_1K:
3898 case I40E_HASH_FILTER_SIZE_2K:
3899 case I40E_HASH_FILTER_SIZE_4K:
3900 case I40E_HASH_FILTER_SIZE_8K:
3901 case I40E_HASH_FILTER_SIZE_16K:
3902 case I40E_HASH_FILTER_SIZE_32K:
3903 case I40E_HASH_FILTER_SIZE_64K:
3904 case I40E_HASH_FILTER_SIZE_128K:
3905 case I40E_HASH_FILTER_SIZE_256K:
3906 case I40E_HASH_FILTER_SIZE_512K:
3907 case I40E_HASH_FILTER_SIZE_1M:
3908 break;
3909 default:
3910 return -EINVAL;
3911 }
3912
3913 switch (settings->pe_cntx_num) {
3914 case I40E_DMA_CNTX_SIZE_512:
3915 case I40E_DMA_CNTX_SIZE_1K:
3916 case I40E_DMA_CNTX_SIZE_2K:
3917 case I40E_DMA_CNTX_SIZE_4K:
3918 case I40E_DMA_CNTX_SIZE_8K:
3919 case I40E_DMA_CNTX_SIZE_16K:
3920 case I40E_DMA_CNTX_SIZE_32K:
3921 case I40E_DMA_CNTX_SIZE_64K:
3922 case I40E_DMA_CNTX_SIZE_128K:
3923 case I40E_DMA_CNTX_SIZE_256K:
3924 break;
3925 default:
3926 return -EINVAL;
3927 }
3928
3929 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3930 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3931 fcoe_fmax = FIELD_GET(I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK, val);
3932 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3933 return -EINVAL;
3934
3935 return 0;
3936}
3937
3938/**
3939 * i40e_set_filter_control
3940 * @hw: pointer to the hardware structure
3941 * @settings: Filter control settings
3942 *
3943 * Set the Queue Filters for PE/FCoE and enable filters required
3944 * for a single PF. It is expected that these settings are programmed
3945 * at the driver initialization time.
3946 **/
3947int i40e_set_filter_control(struct i40e_hw *hw,
3948 struct i40e_filter_control_settings *settings)
3949{
3950 u32 hash_lut_size = 0;
3951 int ret = 0;
3952 u32 val;
3953
3954 if (!settings)
3955 return -EINVAL;
3956
3957 /* Validate the input settings */
3958 ret = i40e_validate_filter_settings(hw, settings);
3959 if (ret)
3960 return ret;
3961
3962 /* Read the PF Queue Filter control register */
3963 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
3964
3965 /* Program required PE hash buckets for the PF */
3966 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3967 val |= FIELD_PREP(I40E_PFQF_CTL_0_PEHSIZE_MASK, settings->pe_filt_num);
3968 /* Program required PE contexts for the PF */
3969 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3970 val |= FIELD_PREP(I40E_PFQF_CTL_0_PEDSIZE_MASK, settings->pe_cntx_num);
3971
3972 /* Program required FCoE hash buckets for the PF */
3973 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3974 val |= FIELD_PREP(I40E_PFQF_CTL_0_PFFCHSIZE_MASK,
3975 settings->fcoe_filt_num);
3976 /* Program required FCoE DDP contexts for the PF */
3977 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3978 val |= FIELD_PREP(I40E_PFQF_CTL_0_PFFCDSIZE_MASK,
3979 settings->fcoe_cntx_num);
3980
3981 /* Program Hash LUT size for the PF */
3982 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3983 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3984 hash_lut_size = 1;
3985 val |= FIELD_PREP(I40E_PFQF_CTL_0_HASHLUTSIZE_MASK, hash_lut_size);
3986
3987 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3988 if (settings->enable_fdir)
3989 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3990 if (settings->enable_ethtype)
3991 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3992 if (settings->enable_macvlan)
3993 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3994
3995 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
3996
3997 return 0;
3998}
3999
4000/**
4001 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4002 * @hw: pointer to the hw struct
4003 * @mac_addr: MAC address to use in the filter
4004 * @ethtype: Ethertype to use in the filter
4005 * @flags: Flags that needs to be applied to the filter
4006 * @vsi_seid: seid of the control VSI
4007 * @queue: VSI queue number to send the packet to
4008 * @is_add: Add control packet filter if True else remove
4009 * @stats: Structure to hold information on control filter counts
4010 * @cmd_details: pointer to command details structure or NULL
4011 *
4012 * This command will Add or Remove control packet filter for a control VSI.
4013 * In return it will update the total number of perfect filter count in
4014 * the stats member.
4015 **/
4016int i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4017 u8 *mac_addr, u16 ethtype, u16 flags,
4018 u16 vsi_seid, u16 queue, bool is_add,
4019 struct i40e_control_filter_stats *stats,
4020 struct i40e_asq_cmd_details *cmd_details)
4021{
4022 struct i40e_aq_desc desc;
4023 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4024 (struct i40e_aqc_add_remove_control_packet_filter *)
4025 &desc.params.raw;
4026 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4027 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4028 &desc.params.raw;
4029 int status;
4030
4031 if (vsi_seid == 0)
4032 return -EINVAL;
4033
4034 if (is_add) {
4035 i40e_fill_default_direct_cmd_desc(&desc,
4036 i40e_aqc_opc_add_control_packet_filter);
4037 cmd->queue = cpu_to_le16(queue);
4038 } else {
4039 i40e_fill_default_direct_cmd_desc(&desc,
4040 i40e_aqc_opc_remove_control_packet_filter);
4041 }
4042
4043 if (mac_addr)
4044 ether_addr_copy(cmd->mac, mac_addr);
4045
4046 cmd->etype = cpu_to_le16(ethtype);
4047 cmd->flags = cpu_to_le16(flags);
4048 cmd->seid = cpu_to_le16(vsi_seid);
4049
4050 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4051
4052 if (!status && stats) {
4053 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
4054 stats->etype_used = le16_to_cpu(resp->etype_used);
4055 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
4056 stats->etype_free = le16_to_cpu(resp->etype_free);
4057 }
4058
4059 return status;
4060}
4061
4062/**
4063 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4064 * @hw: pointer to the hw struct
4065 * @seid: VSI seid to add ethertype filter from
4066 **/
4067void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4068 u16 seid)
4069{
4070#define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4071 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4072 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4073 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4074 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4075 int status;
4076
4077 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4078 seid, 0, true, NULL,
4079 NULL);
4080 if (status)
4081 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4082}
4083
4084/**
4085 * i40e_aq_alternate_read
4086 * @hw: pointer to the hardware structure
4087 * @reg_addr0: address of first dword to be read
4088 * @reg_val0: pointer for data read from 'reg_addr0'
4089 * @reg_addr1: address of second dword to be read
4090 * @reg_val1: pointer for data read from 'reg_addr1'
4091 *
4092 * Read one or two dwords from alternate structure. Fields are indicated
4093 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4094 * is not passed then only register at 'reg_addr0' is read.
4095 *
4096 **/
4097static int i40e_aq_alternate_read(struct i40e_hw *hw,
4098 u32 reg_addr0, u32 *reg_val0,
4099 u32 reg_addr1, u32 *reg_val1)
4100{
4101 struct i40e_aq_desc desc;
4102 struct i40e_aqc_alternate_write *cmd_resp =
4103 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4104 int status;
4105
4106 if (!reg_val0)
4107 return -EINVAL;
4108
4109 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4110 cmd_resp->address0 = cpu_to_le32(reg_addr0);
4111 cmd_resp->address1 = cpu_to_le32(reg_addr1);
4112
4113 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4114
4115 if (!status) {
4116 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4117
4118 if (reg_val1)
4119 *reg_val1 = le32_to_cpu(cmd_resp->data1);
4120 }
4121
4122 return status;
4123}
4124
4125/**
4126 * i40e_aq_suspend_port_tx
4127 * @hw: pointer to the hardware structure
4128 * @seid: port seid
4129 * @cmd_details: pointer to command details structure or NULL
4130 *
4131 * Suspend port's Tx traffic
4132 **/
4133int i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid,
4134 struct i40e_asq_cmd_details *cmd_details)
4135{
4136 struct i40e_aqc_tx_sched_ind *cmd;
4137 struct i40e_aq_desc desc;
4138 int status;
4139
4140 cmd = (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4141 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_suspend_port_tx);
4142 cmd->vsi_seid = cpu_to_le16(seid);
4143 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4144
4145 return status;
4146}
4147
4148/**
4149 * i40e_aq_resume_port_tx
4150 * @hw: pointer to the hardware structure
4151 * @cmd_details: pointer to command details structure or NULL
4152 *
4153 * Resume port's Tx traffic
4154 **/
4155int i40e_aq_resume_port_tx(struct i40e_hw *hw,
4156 struct i40e_asq_cmd_details *cmd_details)
4157{
4158 struct i40e_aq_desc desc;
4159 int status;
4160
4161 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4162
4163 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4164
4165 return status;
4166}
4167
4168/**
4169 * i40e_set_pci_config_data - store PCI bus info
4170 * @hw: pointer to hardware structure
4171 * @link_status: the link status word from PCI config space
4172 *
4173 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4174 **/
4175void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4176{
4177 hw->bus.type = i40e_bus_type_pci_express;
4178
4179 switch (link_status & PCI_EXP_LNKSTA_NLW) {
4180 case PCI_EXP_LNKSTA_NLW_X1:
4181 hw->bus.width = i40e_bus_width_pcie_x1;
4182 break;
4183 case PCI_EXP_LNKSTA_NLW_X2:
4184 hw->bus.width = i40e_bus_width_pcie_x2;
4185 break;
4186 case PCI_EXP_LNKSTA_NLW_X4:
4187 hw->bus.width = i40e_bus_width_pcie_x4;
4188 break;
4189 case PCI_EXP_LNKSTA_NLW_X8:
4190 hw->bus.width = i40e_bus_width_pcie_x8;
4191 break;
4192 default:
4193 hw->bus.width = i40e_bus_width_unknown;
4194 break;
4195 }
4196
4197 switch (link_status & PCI_EXP_LNKSTA_CLS) {
4198 case PCI_EXP_LNKSTA_CLS_2_5GB:
4199 hw->bus.speed = i40e_bus_speed_2500;
4200 break;
4201 case PCI_EXP_LNKSTA_CLS_5_0GB:
4202 hw->bus.speed = i40e_bus_speed_5000;
4203 break;
4204 case PCI_EXP_LNKSTA_CLS_8_0GB:
4205 hw->bus.speed = i40e_bus_speed_8000;
4206 break;
4207 default:
4208 hw->bus.speed = i40e_bus_speed_unknown;
4209 break;
4210 }
4211}
4212
4213/**
4214 * i40e_aq_debug_dump
4215 * @hw: pointer to the hardware structure
4216 * @cluster_id: specific cluster to dump
4217 * @table_id: table id within cluster
4218 * @start_index: index of line in the block to read
4219 * @buff_size: dump buffer size
4220 * @buff: dump buffer
4221 * @ret_buff_size: actual buffer size returned
4222 * @ret_next_table: next block to read
4223 * @ret_next_index: next index to read
4224 * @cmd_details: pointer to command details structure or NULL
4225 *
4226 * Dump internal FW/HW data for debug purposes.
4227 *
4228 **/
4229int i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4230 u8 table_id, u32 start_index, u16 buff_size,
4231 void *buff, u16 *ret_buff_size,
4232 u8 *ret_next_table, u32 *ret_next_index,
4233 struct i40e_asq_cmd_details *cmd_details)
4234{
4235 struct i40e_aq_desc desc;
4236 struct i40e_aqc_debug_dump_internals *cmd =
4237 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4238 struct i40e_aqc_debug_dump_internals *resp =
4239 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4240 int status;
4241
4242 if (buff_size == 0 || !buff)
4243 return -EINVAL;
4244
4245 i40e_fill_default_direct_cmd_desc(&desc,
4246 i40e_aqc_opc_debug_dump_internals);
4247 /* Indirect Command */
4248 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4249 if (buff_size > I40E_AQ_LARGE_BUF)
4250 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4251
4252 cmd->cluster_id = cluster_id;
4253 cmd->table_id = table_id;
4254 cmd->idx = cpu_to_le32(start_index);
4255
4256 desc.datalen = cpu_to_le16(buff_size);
4257
4258 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4259 if (!status) {
4260 if (ret_buff_size)
4261 *ret_buff_size = le16_to_cpu(desc.datalen);
4262 if (ret_next_table)
4263 *ret_next_table = resp->table_id;
4264 if (ret_next_index)
4265 *ret_next_index = le32_to_cpu(resp->idx);
4266 }
4267
4268 return status;
4269}
4270
4271/**
4272 * i40e_read_bw_from_alt_ram
4273 * @hw: pointer to the hardware structure
4274 * @max_bw: pointer for max_bw read
4275 * @min_bw: pointer for min_bw read
4276 * @min_valid: pointer for bool that is true if min_bw is a valid value
4277 * @max_valid: pointer for bool that is true if max_bw is a valid value
4278 *
4279 * Read bw from the alternate ram for the given pf
4280 **/
4281int i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4282 u32 *max_bw, u32 *min_bw,
4283 bool *min_valid, bool *max_valid)
4284{
4285 u32 max_bw_addr, min_bw_addr;
4286 int status;
4287
4288 /* Calculate the address of the min/max bw registers */
4289 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4290 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4291 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4292 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4293 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4294 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4295
4296 /* Read the bandwidths from alt ram */
4297 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4298 min_bw_addr, min_bw);
4299
4300 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4301 *min_valid = true;
4302 else
4303 *min_valid = false;
4304
4305 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4306 *max_valid = true;
4307 else
4308 *max_valid = false;
4309
4310 return status;
4311}
4312
4313/**
4314 * i40e_aq_configure_partition_bw
4315 * @hw: pointer to the hardware structure
4316 * @bw_data: Buffer holding valid pfs and bw limits
4317 * @cmd_details: pointer to command details
4318 *
4319 * Configure partitions guaranteed/max bw
4320 **/
4321int
4322i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4323 struct i40e_aqc_configure_partition_bw_data *bw_data,
4324 struct i40e_asq_cmd_details *cmd_details)
4325{
4326 u16 bwd_size = sizeof(*bw_data);
4327 struct i40e_aq_desc desc;
4328 int status;
4329
4330 i40e_fill_default_direct_cmd_desc(&desc,
4331 i40e_aqc_opc_configure_partition_bw);
4332
4333 /* Indirect command */
4334 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4335 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4336
4337 if (bwd_size > I40E_AQ_LARGE_BUF)
4338 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4339
4340 desc.datalen = cpu_to_le16(bwd_size);
4341
4342 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4343 cmd_details);
4344
4345 return status;
4346}
4347
4348/**
4349 * i40e_read_phy_register_clause22
4350 * @hw: pointer to the HW structure
4351 * @reg: register address in the page
4352 * @phy_addr: PHY address on MDIO interface
4353 * @value: PHY register value
4354 *
4355 * Reads specified PHY register value
4356 **/
4357int i40e_read_phy_register_clause22(struct i40e_hw *hw,
4358 u16 reg, u8 phy_addr, u16 *value)
4359{
4360 u8 port_num = (u8)hw->func_caps.mdio_port_num;
4361 int status = -EIO;
4362 u32 command = 0;
4363 u16 retry = 1000;
4364
4365 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4366 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4367 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
4368 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4369 (I40E_GLGEN_MSCA_MDICMD_MASK);
4370 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4371 do {
4372 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4373 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4374 status = 0;
4375 break;
4376 }
4377 udelay(10);
4378 retry--;
4379 } while (retry);
4380
4381 if (status) {
4382 i40e_debug(hw, I40E_DEBUG_PHY,
4383 "PHY: Can't write command to external PHY.\n");
4384 } else {
4385 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4386 *value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command);
4387 }
4388
4389 return status;
4390}
4391
4392/**
4393 * i40e_write_phy_register_clause22
4394 * @hw: pointer to the HW structure
4395 * @reg: register address in the page
4396 * @phy_addr: PHY address on MDIO interface
4397 * @value: PHY register value
4398 *
4399 * Writes specified PHY register value
4400 **/
4401int i40e_write_phy_register_clause22(struct i40e_hw *hw,
4402 u16 reg, u8 phy_addr, u16 value)
4403{
4404 u8 port_num = (u8)hw->func_caps.mdio_port_num;
4405 int status = -EIO;
4406 u32 command = 0;
4407 u16 retry = 1000;
4408
4409 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4410 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4411
4412 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4413 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4414 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
4415 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4416 (I40E_GLGEN_MSCA_MDICMD_MASK);
4417
4418 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4419 do {
4420 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4421 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4422 status = 0;
4423 break;
4424 }
4425 udelay(10);
4426 retry--;
4427 } while (retry);
4428
4429 return status;
4430}
4431
4432/**
4433 * i40e_read_phy_register_clause45
4434 * @hw: pointer to the HW structure
4435 * @page: registers page number
4436 * @reg: register address in the page
4437 * @phy_addr: PHY address on MDIO interface
4438 * @value: PHY register value
4439 *
4440 * Reads specified PHY register value
4441 **/
4442int i40e_read_phy_register_clause45(struct i40e_hw *hw,
4443 u8 page, u16 reg, u8 phy_addr, u16 *value)
4444{
4445 u8 port_num = hw->func_caps.mdio_port_num;
4446 int status = -EIO;
4447 u32 command = 0;
4448 u16 retry = 1000;
4449
4450 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4451 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4452 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4453 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4454 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4455 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4456 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4457 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4458 do {
4459 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4460 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4461 status = 0;
4462 break;
4463 }
4464 usleep_range(10, 20);
4465 retry--;
4466 } while (retry);
4467
4468 if (status) {
4469 i40e_debug(hw, I40E_DEBUG_PHY,
4470 "PHY: Can't write command to external PHY.\n");
4471 goto phy_read_end;
4472 }
4473
4474 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4475 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4476 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
4477 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4478 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4479 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4480 status = -EIO;
4481 retry = 1000;
4482 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4483 do {
4484 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4485 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4486 status = 0;
4487 break;
4488 }
4489 usleep_range(10, 20);
4490 retry--;
4491 } while (retry);
4492
4493 if (!status) {
4494 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4495 *value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command);
4496 } else {
4497 i40e_debug(hw, I40E_DEBUG_PHY,
4498 "PHY: Can't read register value from external PHY.\n");
4499 }
4500
4501phy_read_end:
4502 return status;
4503}
4504
4505/**
4506 * i40e_write_phy_register_clause45
4507 * @hw: pointer to the HW structure
4508 * @page: registers page number
4509 * @reg: register address in the page
4510 * @phy_addr: PHY address on MDIO interface
4511 * @value: PHY register value
4512 *
4513 * Writes value to specified PHY register
4514 **/
4515int i40e_write_phy_register_clause45(struct i40e_hw *hw,
4516 u8 page, u16 reg, u8 phy_addr, u16 value)
4517{
4518 u8 port_num = hw->func_caps.mdio_port_num;
4519 int status = -EIO;
4520 u16 retry = 1000;
4521 u32 command = 0;
4522
4523 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4524 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4525 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4526 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4527 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4528 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4529 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4530 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4531 do {
4532 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4533 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4534 status = 0;
4535 break;
4536 }
4537 usleep_range(10, 20);
4538 retry--;
4539 } while (retry);
4540 if (status) {
4541 i40e_debug(hw, I40E_DEBUG_PHY,
4542 "PHY: Can't write command to external PHY.\n");
4543 goto phy_write_end;
4544 }
4545
4546 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4547 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4548
4549 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4550 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4551 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
4552 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4553 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4554 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4555 status = -EIO;
4556 retry = 1000;
4557 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4558 do {
4559 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4560 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4561 status = 0;
4562 break;
4563 }
4564 usleep_range(10, 20);
4565 retry--;
4566 } while (retry);
4567
4568phy_write_end:
4569 return status;
4570}
4571
4572/**
4573 * i40e_write_phy_register
4574 * @hw: pointer to the HW structure
4575 * @page: registers page number
4576 * @reg: register address in the page
4577 * @phy_addr: PHY address on MDIO interface
4578 * @value: PHY register value
4579 *
4580 * Writes value to specified PHY register
4581 **/
4582int i40e_write_phy_register(struct i40e_hw *hw,
4583 u8 page, u16 reg, u8 phy_addr, u16 value)
4584{
4585 int status;
4586
4587 switch (hw->device_id) {
4588 case I40E_DEV_ID_1G_BASE_T_X722:
4589 status = i40e_write_phy_register_clause22(hw, reg, phy_addr,
4590 value);
4591 break;
4592 case I40E_DEV_ID_1G_BASE_T_BC:
4593 case I40E_DEV_ID_5G_BASE_T_BC:
4594 case I40E_DEV_ID_10G_BASE_T:
4595 case I40E_DEV_ID_10G_BASE_T4:
4596 case I40E_DEV_ID_10G_BASE_T_BC:
4597 case I40E_DEV_ID_10G_BASE_T_X722:
4598 case I40E_DEV_ID_25G_B:
4599 case I40E_DEV_ID_25G_SFP28:
4600 status = i40e_write_phy_register_clause45(hw, page, reg,
4601 phy_addr, value);
4602 break;
4603 default:
4604 status = -EIO;
4605 break;
4606 }
4607
4608 return status;
4609}
4610
4611/**
4612 * i40e_read_phy_register
4613 * @hw: pointer to the HW structure
4614 * @page: registers page number
4615 * @reg: register address in the page
4616 * @phy_addr: PHY address on MDIO interface
4617 * @value: PHY register value
4618 *
4619 * Reads specified PHY register value
4620 **/
4621int i40e_read_phy_register(struct i40e_hw *hw,
4622 u8 page, u16 reg, u8 phy_addr, u16 *value)
4623{
4624 int status;
4625
4626 switch (hw->device_id) {
4627 case I40E_DEV_ID_1G_BASE_T_X722:
4628 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
4629 value);
4630 break;
4631 case I40E_DEV_ID_1G_BASE_T_BC:
4632 case I40E_DEV_ID_5G_BASE_T_BC:
4633 case I40E_DEV_ID_10G_BASE_T:
4634 case I40E_DEV_ID_10G_BASE_T4:
4635 case I40E_DEV_ID_10G_BASE_T_BC:
4636 case I40E_DEV_ID_10G_BASE_T_X722:
4637 case I40E_DEV_ID_25G_B:
4638 case I40E_DEV_ID_25G_SFP28:
4639 status = i40e_read_phy_register_clause45(hw, page, reg,
4640 phy_addr, value);
4641 break;
4642 default:
4643 status = -EIO;
4644 break;
4645 }
4646
4647 return status;
4648}
4649
4650/**
4651 * i40e_get_phy_address
4652 * @hw: pointer to the HW structure
4653 * @dev_num: PHY port num that address we want
4654 *
4655 * Gets PHY address for current port
4656 **/
4657u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4658{
4659 u8 port_num = hw->func_caps.mdio_port_num;
4660 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4661
4662 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4663}
4664
4665/**
4666 * i40e_blink_phy_link_led
4667 * @hw: pointer to the HW structure
4668 * @time: time how long led will blinks in secs
4669 * @interval: gap between LED on and off in msecs
4670 *
4671 * Blinks PHY link LED
4672 **/
4673int i40e_blink_phy_link_led(struct i40e_hw *hw,
4674 u32 time, u32 interval)
4675{
4676 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
4677 u16 gpio_led_port;
4678 u8 phy_addr = 0;
4679 int status = 0;
4680 u16 led_ctl;
4681 u8 port_num;
4682 u16 led_reg;
4683 u32 i;
4684
4685 i = rd32(hw, I40E_PFGEN_PORTNUM);
4686 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4687 phy_addr = i40e_get_phy_address(hw, port_num);
4688
4689 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4690 led_addr++) {
4691 status = i40e_read_phy_register_clause45(hw,
4692 I40E_PHY_COM_REG_PAGE,
4693 led_addr, phy_addr,
4694 &led_reg);
4695 if (status)
4696 goto phy_blinking_end;
4697 led_ctl = led_reg;
4698 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4699 led_reg = 0;
4700 status = i40e_write_phy_register_clause45(hw,
4701 I40E_PHY_COM_REG_PAGE,
4702 led_addr, phy_addr,
4703 led_reg);
4704 if (status)
4705 goto phy_blinking_end;
4706 break;
4707 }
4708 }
4709
4710 if (time > 0 && interval > 0) {
4711 for (i = 0; i < time * 1000; i += interval) {
4712 status = i40e_read_phy_register_clause45(hw,
4713 I40E_PHY_COM_REG_PAGE,
4714 led_addr, phy_addr, &led_reg);
4715 if (status)
4716 goto restore_config;
4717 if (led_reg & I40E_PHY_LED_MANUAL_ON)
4718 led_reg = 0;
4719 else
4720 led_reg = I40E_PHY_LED_MANUAL_ON;
4721 status = i40e_write_phy_register_clause45(hw,
4722 I40E_PHY_COM_REG_PAGE,
4723 led_addr, phy_addr, led_reg);
4724 if (status)
4725 goto restore_config;
4726 msleep(interval);
4727 }
4728 }
4729
4730restore_config:
4731 status = i40e_write_phy_register_clause45(hw,
4732 I40E_PHY_COM_REG_PAGE,
4733 led_addr, phy_addr, led_ctl);
4734
4735phy_blinking_end:
4736 return status;
4737}
4738
4739/**
4740 * i40e_led_get_reg - read LED register
4741 * @hw: pointer to the HW structure
4742 * @led_addr: LED register address
4743 * @reg_val: read register value
4744 **/
4745static int i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
4746 u32 *reg_val)
4747{
4748 u8 phy_addr = 0;
4749 u8 port_num;
4750 int status;
4751 u32 i;
4752
4753 *reg_val = 0;
4754 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) {
4755 status =
4756 i40e_aq_get_phy_register(hw,
4757 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
4758 I40E_PHY_COM_REG_PAGE, true,
4759 I40E_PHY_LED_PROV_REG_1,
4760 reg_val, NULL);
4761 } else {
4762 i = rd32(hw, I40E_PFGEN_PORTNUM);
4763 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4764 phy_addr = i40e_get_phy_address(hw, port_num);
4765 status = i40e_read_phy_register_clause45(hw,
4766 I40E_PHY_COM_REG_PAGE,
4767 led_addr, phy_addr,
4768 (u16 *)reg_val);
4769 }
4770 return status;
4771}
4772
4773/**
4774 * i40e_led_set_reg - write LED register
4775 * @hw: pointer to the HW structure
4776 * @led_addr: LED register address
4777 * @reg_val: register value to write
4778 **/
4779static int i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
4780 u32 reg_val)
4781{
4782 u8 phy_addr = 0;
4783 u8 port_num;
4784 int status;
4785 u32 i;
4786
4787 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) {
4788 status =
4789 i40e_aq_set_phy_register(hw,
4790 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
4791 I40E_PHY_COM_REG_PAGE, true,
4792 I40E_PHY_LED_PROV_REG_1,
4793 reg_val, NULL);
4794 } else {
4795 i = rd32(hw, I40E_PFGEN_PORTNUM);
4796 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4797 phy_addr = i40e_get_phy_address(hw, port_num);
4798 status = i40e_write_phy_register_clause45(hw,
4799 I40E_PHY_COM_REG_PAGE,
4800 led_addr, phy_addr,
4801 (u16)reg_val);
4802 }
4803
4804 return status;
4805}
4806
4807/**
4808 * i40e_led_get_phy - return current on/off mode
4809 * @hw: pointer to the hw struct
4810 * @led_addr: address of led register to use
4811 * @val: original value of register to use
4812 *
4813 **/
4814int i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
4815 u16 *val)
4816{
4817 u16 gpio_led_port;
4818 u8 phy_addr = 0;
4819 u32 reg_val_aq;
4820 int status = 0;
4821 u16 temp_addr;
4822 u16 reg_val;
4823 u8 port_num;
4824 u32 i;
4825
4826 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) {
4827 status =
4828 i40e_aq_get_phy_register(hw,
4829 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
4830 I40E_PHY_COM_REG_PAGE, true,
4831 I40E_PHY_LED_PROV_REG_1,
4832 ®_val_aq, NULL);
4833 if (status == 0)
4834 *val = (u16)reg_val_aq;
4835 return status;
4836 }
4837 temp_addr = I40E_PHY_LED_PROV_REG_1;
4838 i = rd32(hw, I40E_PFGEN_PORTNUM);
4839 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4840 phy_addr = i40e_get_phy_address(hw, port_num);
4841
4842 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4843 temp_addr++) {
4844 status = i40e_read_phy_register_clause45(hw,
4845 I40E_PHY_COM_REG_PAGE,
4846 temp_addr, phy_addr,
4847 ®_val);
4848 if (status)
4849 return status;
4850 *val = reg_val;
4851 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
4852 *led_addr = temp_addr;
4853 break;
4854 }
4855 }
4856 return status;
4857}
4858
4859/**
4860 * i40e_led_set_phy
4861 * @hw: pointer to the HW structure
4862 * @on: true or false
4863 * @led_addr: address of led register to use
4864 * @mode: original val plus bit for set or ignore
4865 *
4866 * Set led's on or off when controlled by the PHY
4867 *
4868 **/
4869int i40e_led_set_phy(struct i40e_hw *hw, bool on,
4870 u16 led_addr, u32 mode)
4871{
4872 u32 led_ctl = 0;
4873 u32 led_reg = 0;
4874 int status = 0;
4875
4876 status = i40e_led_get_reg(hw, led_addr, &led_reg);
4877 if (status)
4878 return status;
4879 led_ctl = led_reg;
4880 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4881 led_reg = 0;
4882 status = i40e_led_set_reg(hw, led_addr, led_reg);
4883 if (status)
4884 return status;
4885 }
4886 status = i40e_led_get_reg(hw, led_addr, &led_reg);
4887 if (status)
4888 goto restore_config;
4889 if (on)
4890 led_reg = I40E_PHY_LED_MANUAL_ON;
4891 else
4892 led_reg = 0;
4893
4894 status = i40e_led_set_reg(hw, led_addr, led_reg);
4895 if (status)
4896 goto restore_config;
4897 if (mode & I40E_PHY_LED_MODE_ORIG) {
4898 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
4899 status = i40e_led_set_reg(hw, led_addr, led_ctl);
4900 }
4901 return status;
4902
4903restore_config:
4904 status = i40e_led_set_reg(hw, led_addr, led_ctl);
4905 return status;
4906}
4907
4908/**
4909 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
4910 * @hw: pointer to the hw struct
4911 * @reg_addr: register address
4912 * @reg_val: ptr to register value
4913 * @cmd_details: pointer to command details structure or NULL
4914 *
4915 * Use the firmware to read the Rx control register,
4916 * especially useful if the Rx unit is under heavy pressure
4917 **/
4918int i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
4919 u32 reg_addr, u32 *reg_val,
4920 struct i40e_asq_cmd_details *cmd_details)
4921{
4922 struct i40e_aq_desc desc;
4923 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
4924 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4925 int status;
4926
4927 if (!reg_val)
4928 return -EINVAL;
4929
4930 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
4931
4932 cmd_resp->address = cpu_to_le32(reg_addr);
4933
4934 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4935
4936 if (status == 0)
4937 *reg_val = le32_to_cpu(cmd_resp->value);
4938
4939 return status;
4940}
4941
4942/**
4943 * i40e_read_rx_ctl - read from an Rx control register
4944 * @hw: pointer to the hw struct
4945 * @reg_addr: register address
4946 **/
4947u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
4948{
4949 bool use_register = false;
4950 int status = 0;
4951 int retry = 5;
4952 u32 val = 0;
4953
4954 if (i40e_is_aq_api_ver_lt(hw, 1, 5) || hw->mac.type == I40E_MAC_X722)
4955 use_register = true;
4956
4957 if (!use_register) {
4958do_retry:
4959 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
4960 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
4961 usleep_range(1000, 2000);
4962 retry--;
4963 goto do_retry;
4964 }
4965 }
4966
4967 /* if the AQ access failed, try the old-fashioned way */
4968 if (status || use_register)
4969 val = rd32(hw, reg_addr);
4970
4971 return val;
4972}
4973
4974/**
4975 * i40e_aq_rx_ctl_write_register
4976 * @hw: pointer to the hw struct
4977 * @reg_addr: register address
4978 * @reg_val: register value
4979 * @cmd_details: pointer to command details structure or NULL
4980 *
4981 * Use the firmware to write to an Rx control register,
4982 * especially useful if the Rx unit is under heavy pressure
4983 **/
4984int i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
4985 u32 reg_addr, u32 reg_val,
4986 struct i40e_asq_cmd_details *cmd_details)
4987{
4988 struct i40e_aq_desc desc;
4989 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
4990 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4991 int status;
4992
4993 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
4994
4995 cmd->address = cpu_to_le32(reg_addr);
4996 cmd->value = cpu_to_le32(reg_val);
4997
4998 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4999
5000 return status;
5001}
5002
5003/**
5004 * i40e_write_rx_ctl - write to an Rx control register
5005 * @hw: pointer to the hw struct
5006 * @reg_addr: register address
5007 * @reg_val: register value
5008 **/
5009void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
5010{
5011 bool use_register = false;
5012 int status = 0;
5013 int retry = 5;
5014
5015 if (i40e_is_aq_api_ver_lt(hw, 1, 5) || hw->mac.type == I40E_MAC_X722)
5016 use_register = true;
5017
5018 if (!use_register) {
5019do_retry:
5020 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
5021 reg_val, NULL);
5022 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5023 usleep_range(1000, 2000);
5024 retry--;
5025 goto do_retry;
5026 }
5027 }
5028
5029 /* if the AQ access failed, try the old-fashioned way */
5030 if (status || use_register)
5031 wr32(hw, reg_addr, reg_val);
5032}
5033
5034/**
5035 * i40e_mdio_if_number_selection - MDIO I/F number selection
5036 * @hw: pointer to the hw struct
5037 * @set_mdio: use MDIO I/F number specified by mdio_num
5038 * @mdio_num: MDIO I/F number
5039 * @cmd: pointer to PHY Register command structure
5040 **/
5041static void i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio,
5042 u8 mdio_num,
5043 struct i40e_aqc_phy_register_access *cmd)
5044{
5045 if (!set_mdio ||
5046 cmd->phy_interface != I40E_AQ_PHY_REG_ACCESS_EXTERNAL)
5047 return;
5048
5049 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS_EXTENDED, hw->caps)) {
5050 cmd->cmd_flags |=
5051 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER |
5052 FIELD_PREP(I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK,
5053 mdio_num);
5054 } else {
5055 i40e_debug(hw, I40E_DEBUG_PHY, "MDIO I/F number selection not supported by current FW version.\n");
5056 }
5057}
5058
5059/**
5060 * i40e_aq_set_phy_register_ext
5061 * @hw: pointer to the hw struct
5062 * @phy_select: select which phy should be accessed
5063 * @dev_addr: PHY device address
5064 * @page_change: flag to indicate if phy page should be updated
5065 * @set_mdio: use MDIO I/F number specified by mdio_num
5066 * @mdio_num: MDIO I/F number
5067 * @reg_addr: PHY register address
5068 * @reg_val: new register value
5069 * @cmd_details: pointer to command details structure or NULL
5070 *
5071 * Write the external PHY register.
5072 * NOTE: In common cases MDIO I/F number should not be changed, thats why you
5073 * may use simple wrapper i40e_aq_set_phy_register.
5074 **/
5075int i40e_aq_set_phy_register_ext(struct i40e_hw *hw,
5076 u8 phy_select, u8 dev_addr, bool page_change,
5077 bool set_mdio, u8 mdio_num,
5078 u32 reg_addr, u32 reg_val,
5079 struct i40e_asq_cmd_details *cmd_details)
5080{
5081 struct i40e_aq_desc desc;
5082 struct i40e_aqc_phy_register_access *cmd =
5083 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5084 int status;
5085
5086 i40e_fill_default_direct_cmd_desc(&desc,
5087 i40e_aqc_opc_set_phy_register);
5088
5089 cmd->phy_interface = phy_select;
5090 cmd->dev_address = dev_addr;
5091 cmd->reg_address = cpu_to_le32(reg_addr);
5092 cmd->reg_value = cpu_to_le32(reg_val);
5093
5094 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
5095
5096 if (!page_change)
5097 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
5098
5099 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5100
5101 return status;
5102}
5103
5104/**
5105 * i40e_aq_get_phy_register_ext
5106 * @hw: pointer to the hw struct
5107 * @phy_select: select which phy should be accessed
5108 * @dev_addr: PHY device address
5109 * @page_change: flag to indicate if phy page should be updated
5110 * @set_mdio: use MDIO I/F number specified by mdio_num
5111 * @mdio_num: MDIO I/F number
5112 * @reg_addr: PHY register address
5113 * @reg_val: read register value
5114 * @cmd_details: pointer to command details structure or NULL
5115 *
5116 * Read the external PHY register.
5117 * NOTE: In common cases MDIO I/F number should not be changed, thats why you
5118 * may use simple wrapper i40e_aq_get_phy_register.
5119 **/
5120int i40e_aq_get_phy_register_ext(struct i40e_hw *hw,
5121 u8 phy_select, u8 dev_addr, bool page_change,
5122 bool set_mdio, u8 mdio_num,
5123 u32 reg_addr, u32 *reg_val,
5124 struct i40e_asq_cmd_details *cmd_details)
5125{
5126 struct i40e_aq_desc desc;
5127 struct i40e_aqc_phy_register_access *cmd =
5128 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5129 int status;
5130
5131 i40e_fill_default_direct_cmd_desc(&desc,
5132 i40e_aqc_opc_get_phy_register);
5133
5134 cmd->phy_interface = phy_select;
5135 cmd->dev_address = dev_addr;
5136 cmd->reg_address = cpu_to_le32(reg_addr);
5137
5138 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
5139
5140 if (!page_change)
5141 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
5142
5143 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5144 if (!status)
5145 *reg_val = le32_to_cpu(cmd->reg_value);
5146
5147 return status;
5148}
5149
5150/**
5151 * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
5152 * @hw: pointer to the hw struct
5153 * @buff: command buffer (size in bytes = buff_size)
5154 * @buff_size: buffer size in bytes
5155 * @track_id: package tracking id
5156 * @error_offset: returns error offset
5157 * @error_info: returns error information
5158 * @cmd_details: pointer to command details structure or NULL
5159 **/
5160int i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
5161 u16 buff_size, u32 track_id,
5162 u32 *error_offset, u32 *error_info,
5163 struct i40e_asq_cmd_details *cmd_details)
5164{
5165 struct i40e_aq_desc desc;
5166 struct i40e_aqc_write_personalization_profile *cmd =
5167 (struct i40e_aqc_write_personalization_profile *)
5168 &desc.params.raw;
5169 struct i40e_aqc_write_ddp_resp *resp;
5170 int status;
5171
5172 i40e_fill_default_direct_cmd_desc(&desc,
5173 i40e_aqc_opc_write_personalization_profile);
5174
5175 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
5176 if (buff_size > I40E_AQ_LARGE_BUF)
5177 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5178
5179 desc.datalen = cpu_to_le16(buff_size);
5180
5181 cmd->profile_track_id = cpu_to_le32(track_id);
5182
5183 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5184 if (!status) {
5185 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
5186 if (error_offset)
5187 *error_offset = le32_to_cpu(resp->error_offset);
5188 if (error_info)
5189 *error_info = le32_to_cpu(resp->error_info);
5190 }
5191
5192 return status;
5193}
5194
5195/**
5196 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
5197 * @hw: pointer to the hw struct
5198 * @buff: command buffer (size in bytes = buff_size)
5199 * @buff_size: buffer size in bytes
5200 * @flags: AdminQ command flags
5201 * @cmd_details: pointer to command details structure or NULL
5202 **/
5203int i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
5204 u16 buff_size, u8 flags,
5205 struct i40e_asq_cmd_details *cmd_details)
5206{
5207 struct i40e_aq_desc desc;
5208 struct i40e_aqc_get_applied_profiles *cmd =
5209 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
5210 int status;
5211
5212 i40e_fill_default_direct_cmd_desc(&desc,
5213 i40e_aqc_opc_get_personalization_profile_list);
5214
5215 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
5216 if (buff_size > I40E_AQ_LARGE_BUF)
5217 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5218 desc.datalen = cpu_to_le16(buff_size);
5219
5220 cmd->flags = flags;
5221
5222 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5223
5224 return status;
5225}
5226
5227/**
5228 * i40e_find_segment_in_package
5229 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
5230 * @pkg_hdr: pointer to the package header to be searched
5231 *
5232 * This function searches a package file for a particular segment type. On
5233 * success it returns a pointer to the segment header, otherwise it will
5234 * return NULL.
5235 **/
5236struct i40e_generic_seg_header *
5237i40e_find_segment_in_package(u32 segment_type,
5238 struct i40e_package_header *pkg_hdr)
5239{
5240 struct i40e_generic_seg_header *segment;
5241 u32 i;
5242
5243 /* Search all package segments for the requested segment type */
5244 for (i = 0; i < pkg_hdr->segment_count; i++) {
5245 segment =
5246 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
5247 pkg_hdr->segment_offset[i]);
5248
5249 if (segment->type == segment_type)
5250 return segment;
5251 }
5252
5253 return NULL;
5254}
5255
5256/* Get section table in profile */
5257#define I40E_SECTION_TABLE(profile, sec_tbl) \
5258 do { \
5259 struct i40e_profile_segment *p = (profile); \
5260 u32 count; \
5261 u32 *nvm; \
5262 count = p->device_table_count; \
5263 nvm = (u32 *)&p->device_table[count]; \
5264 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
5265 } while (0)
5266
5267/* Get section header in profile */
5268#define I40E_SECTION_HEADER(profile, offset) \
5269 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
5270
5271/**
5272 * i40e_find_section_in_profile
5273 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
5274 * @profile: pointer to the i40e segment header to be searched
5275 *
5276 * This function searches i40e segment for a particular section type. On
5277 * success it returns a pointer to the section header, otherwise it will
5278 * return NULL.
5279 **/
5280struct i40e_profile_section_header *
5281i40e_find_section_in_profile(u32 section_type,
5282 struct i40e_profile_segment *profile)
5283{
5284 struct i40e_profile_section_header *sec;
5285 struct i40e_section_table *sec_tbl;
5286 u32 sec_off;
5287 u32 i;
5288
5289 if (profile->header.type != SEGMENT_TYPE_I40E)
5290 return NULL;
5291
5292 I40E_SECTION_TABLE(profile, sec_tbl);
5293
5294 for (i = 0; i < sec_tbl->section_count; i++) {
5295 sec_off = sec_tbl->section_offset[i];
5296 sec = I40E_SECTION_HEADER(profile, sec_off);
5297 if (sec->section.type == section_type)
5298 return sec;
5299 }
5300
5301 return NULL;
5302}
5303
5304/**
5305 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
5306 * @hw: pointer to the hw struct
5307 * @aq: command buffer containing all data to execute AQ
5308 **/
5309static int i40e_ddp_exec_aq_section(struct i40e_hw *hw,
5310 struct i40e_profile_aq_section *aq)
5311{
5312 struct i40e_aq_desc desc;
5313 u8 *msg = NULL;
5314 u16 msglen;
5315 int status;
5316
5317 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
5318 desc.flags |= cpu_to_le16(aq->flags);
5319 memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw));
5320
5321 msglen = aq->datalen;
5322 if (msglen) {
5323 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
5324 I40E_AQ_FLAG_RD));
5325 if (msglen > I40E_AQ_LARGE_BUF)
5326 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5327 desc.datalen = cpu_to_le16(msglen);
5328 msg = &aq->data[0];
5329 }
5330
5331 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
5332
5333 if (status) {
5334 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5335 "unable to exec DDP AQ opcode %u, error %d\n",
5336 aq->opcode, status);
5337 return status;
5338 }
5339
5340 /* copy returned desc to aq_buf */
5341 memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw));
5342
5343 return 0;
5344}
5345
5346/**
5347 * i40e_validate_profile
5348 * @hw: pointer to the hardware structure
5349 * @profile: pointer to the profile segment of the package to be validated
5350 * @track_id: package tracking id
5351 * @rollback: flag if the profile is for rollback.
5352 *
5353 * Validates supported devices and profile's sections.
5354 */
5355static int
5356i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5357 u32 track_id, bool rollback)
5358{
5359 struct i40e_profile_section_header *sec = NULL;
5360 struct i40e_section_table *sec_tbl;
5361 u32 vendor_dev_id;
5362 int status = 0;
5363 u32 dev_cnt;
5364 u32 sec_off;
5365 u32 i;
5366
5367 if (track_id == I40E_DDP_TRACKID_INVALID) {
5368 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
5369 return -EOPNOTSUPP;
5370 }
5371
5372 dev_cnt = profile->device_table_count;
5373 for (i = 0; i < dev_cnt; i++) {
5374 vendor_dev_id = profile->device_table[i].vendor_dev_id;
5375 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL &&
5376 hw->device_id == (vendor_dev_id & 0xFFFF))
5377 break;
5378 }
5379 if (dev_cnt && i == dev_cnt) {
5380 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5381 "Device doesn't support DDP\n");
5382 return -ENODEV;
5383 }
5384
5385 I40E_SECTION_TABLE(profile, sec_tbl);
5386
5387 /* Validate sections types */
5388 for (i = 0; i < sec_tbl->section_count; i++) {
5389 sec_off = sec_tbl->section_offset[i];
5390 sec = I40E_SECTION_HEADER(profile, sec_off);
5391 if (rollback) {
5392 if (sec->section.type == SECTION_TYPE_MMIO ||
5393 sec->section.type == SECTION_TYPE_AQ ||
5394 sec->section.type == SECTION_TYPE_RB_AQ) {
5395 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5396 "Not a roll-back package\n");
5397 return -EOPNOTSUPP;
5398 }
5399 } else {
5400 if (sec->section.type == SECTION_TYPE_RB_AQ ||
5401 sec->section.type == SECTION_TYPE_RB_MMIO) {
5402 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5403 "Not an original package\n");
5404 return -EOPNOTSUPP;
5405 }
5406 }
5407 }
5408
5409 return status;
5410}
5411
5412/**
5413 * i40e_write_profile
5414 * @hw: pointer to the hardware structure
5415 * @profile: pointer to the profile segment of the package to be downloaded
5416 * @track_id: package tracking id
5417 *
5418 * Handles the download of a complete package.
5419 */
5420int
5421i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5422 u32 track_id)
5423{
5424 struct i40e_profile_section_header *sec = NULL;
5425 struct i40e_profile_aq_section *ddp_aq;
5426 struct i40e_section_table *sec_tbl;
5427 u32 offset = 0, info = 0;
5428 u32 section_size = 0;
5429 int status = 0;
5430 u32 sec_off;
5431 u32 i;
5432
5433 status = i40e_validate_profile(hw, profile, track_id, false);
5434 if (status)
5435 return status;
5436
5437 I40E_SECTION_TABLE(profile, sec_tbl);
5438
5439 for (i = 0; i < sec_tbl->section_count; i++) {
5440 sec_off = sec_tbl->section_offset[i];
5441 sec = I40E_SECTION_HEADER(profile, sec_off);
5442 /* Process generic admin command */
5443 if (sec->section.type == SECTION_TYPE_AQ) {
5444 ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
5445 status = i40e_ddp_exec_aq_section(hw, ddp_aq);
5446 if (status) {
5447 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5448 "Failed to execute aq: section %d, opcode %u\n",
5449 i, ddp_aq->opcode);
5450 break;
5451 }
5452 sec->section.type = SECTION_TYPE_RB_AQ;
5453 }
5454
5455 /* Skip any non-mmio sections */
5456 if (sec->section.type != SECTION_TYPE_MMIO)
5457 continue;
5458
5459 section_size = sec->section.size +
5460 sizeof(struct i40e_profile_section_header);
5461
5462 /* Write MMIO section */
5463 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
5464 track_id, &offset, &info, NULL);
5465 if (status) {
5466 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5467 "Failed to write profile: section %d, offset %d, info %d\n",
5468 i, offset, info);
5469 break;
5470 }
5471 }
5472 return status;
5473}
5474
5475/**
5476 * i40e_rollback_profile
5477 * @hw: pointer to the hardware structure
5478 * @profile: pointer to the profile segment of the package to be removed
5479 * @track_id: package tracking id
5480 *
5481 * Rolls back previously loaded package.
5482 */
5483int
5484i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5485 u32 track_id)
5486{
5487 struct i40e_profile_section_header *sec = NULL;
5488 struct i40e_section_table *sec_tbl;
5489 u32 offset = 0, info = 0;
5490 u32 section_size = 0;
5491 int status = 0;
5492 u32 sec_off;
5493 int i;
5494
5495 status = i40e_validate_profile(hw, profile, track_id, true);
5496 if (status)
5497 return status;
5498
5499 I40E_SECTION_TABLE(profile, sec_tbl);
5500
5501 /* For rollback write sections in reverse */
5502 for (i = sec_tbl->section_count - 1; i >= 0; i--) {
5503 sec_off = sec_tbl->section_offset[i];
5504 sec = I40E_SECTION_HEADER(profile, sec_off);
5505
5506 /* Skip any non-rollback sections */
5507 if (sec->section.type != SECTION_TYPE_RB_MMIO)
5508 continue;
5509
5510 section_size = sec->section.size +
5511 sizeof(struct i40e_profile_section_header);
5512
5513 /* Write roll-back MMIO section */
5514 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
5515 track_id, &offset, &info, NULL);
5516 if (status) {
5517 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5518 "Failed to write profile: section %d, offset %d, info %d\n",
5519 i, offset, info);
5520 break;
5521 }
5522 }
5523 return status;
5524}
5525
5526/**
5527 * i40e_add_pinfo_to_list
5528 * @hw: pointer to the hardware structure
5529 * @profile: pointer to the profile segment of the package
5530 * @profile_info_sec: buffer for information section
5531 * @track_id: package tracking id
5532 *
5533 * Register a profile to the list of loaded profiles.
5534 */
5535int
5536i40e_add_pinfo_to_list(struct i40e_hw *hw,
5537 struct i40e_profile_segment *profile,
5538 u8 *profile_info_sec, u32 track_id)
5539{
5540 struct i40e_profile_section_header *sec = NULL;
5541 struct i40e_profile_info *pinfo;
5542 u32 offset = 0, info = 0;
5543 int status = 0;
5544
5545 sec = (struct i40e_profile_section_header *)profile_info_sec;
5546 sec->tbl_size = 1;
5547 sec->data_end = sizeof(struct i40e_profile_section_header) +
5548 sizeof(struct i40e_profile_info);
5549 sec->section.type = SECTION_TYPE_INFO;
5550 sec->section.offset = sizeof(struct i40e_profile_section_header);
5551 sec->section.size = sizeof(struct i40e_profile_info);
5552 pinfo = (struct i40e_profile_info *)(profile_info_sec +
5553 sec->section.offset);
5554 pinfo->track_id = track_id;
5555 pinfo->version = profile->version;
5556 pinfo->op = I40E_DDP_ADD_TRACKID;
5557 memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
5558
5559 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
5560 track_id, &offset, &info, NULL);
5561
5562 return status;
5563}
5564
5565/**
5566 * i40e_aq_add_cloud_filters
5567 * @hw: pointer to the hardware structure
5568 * @seid: VSI seid to add cloud filters from
5569 * @filters: Buffer which contains the filters to be added
5570 * @filter_count: number of filters contained in the buffer
5571 *
5572 * Set the cloud filters for a given VSI. The contents of the
5573 * i40e_aqc_cloud_filters_element_data are filled in by the caller
5574 * of the function.
5575 *
5576 **/
5577int
5578i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid,
5579 struct i40e_aqc_cloud_filters_element_data *filters,
5580 u8 filter_count)
5581{
5582 struct i40e_aq_desc desc;
5583 struct i40e_aqc_add_remove_cloud_filters *cmd =
5584 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5585 u16 buff_len;
5586 int status;
5587
5588 i40e_fill_default_direct_cmd_desc(&desc,
5589 i40e_aqc_opc_add_cloud_filters);
5590
5591 buff_len = filter_count * sizeof(*filters);
5592 desc.datalen = cpu_to_le16(buff_len);
5593 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5594 cmd->num_filters = filter_count;
5595 cmd->seid = cpu_to_le16(seid);
5596
5597 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5598
5599 return status;
5600}
5601
5602/**
5603 * i40e_aq_add_cloud_filters_bb
5604 * @hw: pointer to the hardware structure
5605 * @seid: VSI seid to add cloud filters from
5606 * @filters: Buffer which contains the filters in big buffer to be added
5607 * @filter_count: number of filters contained in the buffer
5608 *
5609 * Set the big buffer cloud filters for a given VSI. The contents of the
5610 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5611 * function.
5612 *
5613 **/
5614int
5615i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5616 struct i40e_aqc_cloud_filters_element_bb *filters,
5617 u8 filter_count)
5618{
5619 struct i40e_aq_desc desc;
5620 struct i40e_aqc_add_remove_cloud_filters *cmd =
5621 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5622 u16 buff_len;
5623 int status;
5624 int i;
5625
5626 i40e_fill_default_direct_cmd_desc(&desc,
5627 i40e_aqc_opc_add_cloud_filters);
5628
5629 buff_len = filter_count * sizeof(*filters);
5630 desc.datalen = cpu_to_le16(buff_len);
5631 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5632 cmd->num_filters = filter_count;
5633 cmd->seid = cpu_to_le16(seid);
5634 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5635
5636 for (i = 0; i < filter_count; i++) {
5637 u16 tnl_type;
5638 u32 ti;
5639
5640 tnl_type = le16_get_bits(filters[i].element.flags,
5641 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK);
5642
5643 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5644 * one more byte further than normally used for Tenant ID in
5645 * other tunnel types.
5646 */
5647 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5648 ti = le32_to_cpu(filters[i].element.tenant_id);
5649 filters[i].element.tenant_id = cpu_to_le32(ti << 8);
5650 }
5651 }
5652
5653 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5654
5655 return status;
5656}
5657
5658/**
5659 * i40e_aq_rem_cloud_filters
5660 * @hw: pointer to the hardware structure
5661 * @seid: VSI seid to remove cloud filters from
5662 * @filters: Buffer which contains the filters to be removed
5663 * @filter_count: number of filters contained in the buffer
5664 *
5665 * Remove the cloud filters for a given VSI. The contents of the
5666 * i40e_aqc_cloud_filters_element_data are filled in by the caller
5667 * of the function.
5668 *
5669 **/
5670int
5671i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5672 struct i40e_aqc_cloud_filters_element_data *filters,
5673 u8 filter_count)
5674{
5675 struct i40e_aq_desc desc;
5676 struct i40e_aqc_add_remove_cloud_filters *cmd =
5677 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5678 u16 buff_len;
5679 int status;
5680
5681 i40e_fill_default_direct_cmd_desc(&desc,
5682 i40e_aqc_opc_remove_cloud_filters);
5683
5684 buff_len = filter_count * sizeof(*filters);
5685 desc.datalen = cpu_to_le16(buff_len);
5686 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5687 cmd->num_filters = filter_count;
5688 cmd->seid = cpu_to_le16(seid);
5689
5690 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5691
5692 return status;
5693}
5694
5695/**
5696 * i40e_aq_rem_cloud_filters_bb
5697 * @hw: pointer to the hardware structure
5698 * @seid: VSI seid to remove cloud filters from
5699 * @filters: Buffer which contains the filters in big buffer to be removed
5700 * @filter_count: number of filters contained in the buffer
5701 *
5702 * Remove the big buffer cloud filters for a given VSI. The contents of the
5703 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5704 * function.
5705 *
5706 **/
5707int
5708i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5709 struct i40e_aqc_cloud_filters_element_bb *filters,
5710 u8 filter_count)
5711{
5712 struct i40e_aq_desc desc;
5713 struct i40e_aqc_add_remove_cloud_filters *cmd =
5714 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5715 u16 buff_len;
5716 int status;
5717 int i;
5718
5719 i40e_fill_default_direct_cmd_desc(&desc,
5720 i40e_aqc_opc_remove_cloud_filters);
5721
5722 buff_len = filter_count * sizeof(*filters);
5723 desc.datalen = cpu_to_le16(buff_len);
5724 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5725 cmd->num_filters = filter_count;
5726 cmd->seid = cpu_to_le16(seid);
5727 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5728
5729 for (i = 0; i < filter_count; i++) {
5730 u16 tnl_type;
5731 u32 ti;
5732
5733 tnl_type = le16_get_bits(filters[i].element.flags,
5734 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK);
5735
5736 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5737 * one more byte further than normally used for Tenant ID in
5738 * other tunnel types.
5739 */
5740 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5741 ti = le32_to_cpu(filters[i].element.tenant_id);
5742 filters[i].element.tenant_id = cpu_to_le32(ti << 8);
5743 }
5744 }
5745
5746 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5747
5748 return status;
5749}
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2013 - 2018 Intel Corporation. */
3
4#include "i40e.h"
5#include "i40e_type.h"
6#include "i40e_adminq.h"
7#include "i40e_prototype.h"
8#include <linux/avf/virtchnl.h>
9
10/**
11 * i40e_set_mac_type - Sets MAC type
12 * @hw: pointer to the HW structure
13 *
14 * This function sets the mac type of the adapter based on the
15 * vendor ID and device ID stored in the hw structure.
16 **/
17i40e_status i40e_set_mac_type(struct i40e_hw *hw)
18{
19 i40e_status status = 0;
20
21 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
22 switch (hw->device_id) {
23 case I40E_DEV_ID_SFP_XL710:
24 case I40E_DEV_ID_QEMU:
25 case I40E_DEV_ID_KX_B:
26 case I40E_DEV_ID_KX_C:
27 case I40E_DEV_ID_QSFP_A:
28 case I40E_DEV_ID_QSFP_B:
29 case I40E_DEV_ID_QSFP_C:
30 case I40E_DEV_ID_5G_BASE_T_BC:
31 case I40E_DEV_ID_10G_BASE_T:
32 case I40E_DEV_ID_10G_BASE_T4:
33 case I40E_DEV_ID_10G_BASE_T_BC:
34 case I40E_DEV_ID_10G_B:
35 case I40E_DEV_ID_10G_SFP:
36 case I40E_DEV_ID_20G_KR2:
37 case I40E_DEV_ID_20G_KR2_A:
38 case I40E_DEV_ID_25G_B:
39 case I40E_DEV_ID_25G_SFP28:
40 case I40E_DEV_ID_X710_N3000:
41 case I40E_DEV_ID_XXV710_N3000:
42 hw->mac.type = I40E_MAC_XL710;
43 break;
44 case I40E_DEV_ID_KX_X722:
45 case I40E_DEV_ID_QSFP_X722:
46 case I40E_DEV_ID_SFP_X722:
47 case I40E_DEV_ID_1G_BASE_T_X722:
48 case I40E_DEV_ID_10G_BASE_T_X722:
49 case I40E_DEV_ID_SFP_I_X722:
50 hw->mac.type = I40E_MAC_X722;
51 break;
52 default:
53 hw->mac.type = I40E_MAC_GENERIC;
54 break;
55 }
56 } else {
57 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
58 }
59
60 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
61 hw->mac.type, status);
62 return status;
63}
64
65/**
66 * i40e_aq_str - convert AQ err code to a string
67 * @hw: pointer to the HW structure
68 * @aq_err: the AQ error code to convert
69 **/
70const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
71{
72 switch (aq_err) {
73 case I40E_AQ_RC_OK:
74 return "OK";
75 case I40E_AQ_RC_EPERM:
76 return "I40E_AQ_RC_EPERM";
77 case I40E_AQ_RC_ENOENT:
78 return "I40E_AQ_RC_ENOENT";
79 case I40E_AQ_RC_ESRCH:
80 return "I40E_AQ_RC_ESRCH";
81 case I40E_AQ_RC_EINTR:
82 return "I40E_AQ_RC_EINTR";
83 case I40E_AQ_RC_EIO:
84 return "I40E_AQ_RC_EIO";
85 case I40E_AQ_RC_ENXIO:
86 return "I40E_AQ_RC_ENXIO";
87 case I40E_AQ_RC_E2BIG:
88 return "I40E_AQ_RC_E2BIG";
89 case I40E_AQ_RC_EAGAIN:
90 return "I40E_AQ_RC_EAGAIN";
91 case I40E_AQ_RC_ENOMEM:
92 return "I40E_AQ_RC_ENOMEM";
93 case I40E_AQ_RC_EACCES:
94 return "I40E_AQ_RC_EACCES";
95 case I40E_AQ_RC_EFAULT:
96 return "I40E_AQ_RC_EFAULT";
97 case I40E_AQ_RC_EBUSY:
98 return "I40E_AQ_RC_EBUSY";
99 case I40E_AQ_RC_EEXIST:
100 return "I40E_AQ_RC_EEXIST";
101 case I40E_AQ_RC_EINVAL:
102 return "I40E_AQ_RC_EINVAL";
103 case I40E_AQ_RC_ENOTTY:
104 return "I40E_AQ_RC_ENOTTY";
105 case I40E_AQ_RC_ENOSPC:
106 return "I40E_AQ_RC_ENOSPC";
107 case I40E_AQ_RC_ENOSYS:
108 return "I40E_AQ_RC_ENOSYS";
109 case I40E_AQ_RC_ERANGE:
110 return "I40E_AQ_RC_ERANGE";
111 case I40E_AQ_RC_EFLUSHED:
112 return "I40E_AQ_RC_EFLUSHED";
113 case I40E_AQ_RC_BAD_ADDR:
114 return "I40E_AQ_RC_BAD_ADDR";
115 case I40E_AQ_RC_EMODE:
116 return "I40E_AQ_RC_EMODE";
117 case I40E_AQ_RC_EFBIG:
118 return "I40E_AQ_RC_EFBIG";
119 }
120
121 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
122 return hw->err_str;
123}
124
125/**
126 * i40e_stat_str - convert status err code to a string
127 * @hw: pointer to the HW structure
128 * @stat_err: the status error code to convert
129 **/
130const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
131{
132 switch (stat_err) {
133 case 0:
134 return "OK";
135 case I40E_ERR_NVM:
136 return "I40E_ERR_NVM";
137 case I40E_ERR_NVM_CHECKSUM:
138 return "I40E_ERR_NVM_CHECKSUM";
139 case I40E_ERR_PHY:
140 return "I40E_ERR_PHY";
141 case I40E_ERR_CONFIG:
142 return "I40E_ERR_CONFIG";
143 case I40E_ERR_PARAM:
144 return "I40E_ERR_PARAM";
145 case I40E_ERR_MAC_TYPE:
146 return "I40E_ERR_MAC_TYPE";
147 case I40E_ERR_UNKNOWN_PHY:
148 return "I40E_ERR_UNKNOWN_PHY";
149 case I40E_ERR_LINK_SETUP:
150 return "I40E_ERR_LINK_SETUP";
151 case I40E_ERR_ADAPTER_STOPPED:
152 return "I40E_ERR_ADAPTER_STOPPED";
153 case I40E_ERR_INVALID_MAC_ADDR:
154 return "I40E_ERR_INVALID_MAC_ADDR";
155 case I40E_ERR_DEVICE_NOT_SUPPORTED:
156 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
157 case I40E_ERR_MASTER_REQUESTS_PENDING:
158 return "I40E_ERR_MASTER_REQUESTS_PENDING";
159 case I40E_ERR_INVALID_LINK_SETTINGS:
160 return "I40E_ERR_INVALID_LINK_SETTINGS";
161 case I40E_ERR_AUTONEG_NOT_COMPLETE:
162 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
163 case I40E_ERR_RESET_FAILED:
164 return "I40E_ERR_RESET_FAILED";
165 case I40E_ERR_SWFW_SYNC:
166 return "I40E_ERR_SWFW_SYNC";
167 case I40E_ERR_NO_AVAILABLE_VSI:
168 return "I40E_ERR_NO_AVAILABLE_VSI";
169 case I40E_ERR_NO_MEMORY:
170 return "I40E_ERR_NO_MEMORY";
171 case I40E_ERR_BAD_PTR:
172 return "I40E_ERR_BAD_PTR";
173 case I40E_ERR_RING_FULL:
174 return "I40E_ERR_RING_FULL";
175 case I40E_ERR_INVALID_PD_ID:
176 return "I40E_ERR_INVALID_PD_ID";
177 case I40E_ERR_INVALID_QP_ID:
178 return "I40E_ERR_INVALID_QP_ID";
179 case I40E_ERR_INVALID_CQ_ID:
180 return "I40E_ERR_INVALID_CQ_ID";
181 case I40E_ERR_INVALID_CEQ_ID:
182 return "I40E_ERR_INVALID_CEQ_ID";
183 case I40E_ERR_INVALID_AEQ_ID:
184 return "I40E_ERR_INVALID_AEQ_ID";
185 case I40E_ERR_INVALID_SIZE:
186 return "I40E_ERR_INVALID_SIZE";
187 case I40E_ERR_INVALID_ARP_INDEX:
188 return "I40E_ERR_INVALID_ARP_INDEX";
189 case I40E_ERR_INVALID_FPM_FUNC_ID:
190 return "I40E_ERR_INVALID_FPM_FUNC_ID";
191 case I40E_ERR_QP_INVALID_MSG_SIZE:
192 return "I40E_ERR_QP_INVALID_MSG_SIZE";
193 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
194 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
195 case I40E_ERR_INVALID_FRAG_COUNT:
196 return "I40E_ERR_INVALID_FRAG_COUNT";
197 case I40E_ERR_QUEUE_EMPTY:
198 return "I40E_ERR_QUEUE_EMPTY";
199 case I40E_ERR_INVALID_ALIGNMENT:
200 return "I40E_ERR_INVALID_ALIGNMENT";
201 case I40E_ERR_FLUSHED_QUEUE:
202 return "I40E_ERR_FLUSHED_QUEUE";
203 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
204 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
205 case I40E_ERR_INVALID_IMM_DATA_SIZE:
206 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
207 case I40E_ERR_TIMEOUT:
208 return "I40E_ERR_TIMEOUT";
209 case I40E_ERR_OPCODE_MISMATCH:
210 return "I40E_ERR_OPCODE_MISMATCH";
211 case I40E_ERR_CQP_COMPL_ERROR:
212 return "I40E_ERR_CQP_COMPL_ERROR";
213 case I40E_ERR_INVALID_VF_ID:
214 return "I40E_ERR_INVALID_VF_ID";
215 case I40E_ERR_INVALID_HMCFN_ID:
216 return "I40E_ERR_INVALID_HMCFN_ID";
217 case I40E_ERR_BACKING_PAGE_ERROR:
218 return "I40E_ERR_BACKING_PAGE_ERROR";
219 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
220 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
221 case I40E_ERR_INVALID_PBLE_INDEX:
222 return "I40E_ERR_INVALID_PBLE_INDEX";
223 case I40E_ERR_INVALID_SD_INDEX:
224 return "I40E_ERR_INVALID_SD_INDEX";
225 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
226 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
227 case I40E_ERR_INVALID_SD_TYPE:
228 return "I40E_ERR_INVALID_SD_TYPE";
229 case I40E_ERR_MEMCPY_FAILED:
230 return "I40E_ERR_MEMCPY_FAILED";
231 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
232 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
233 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
234 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
235 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
236 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
237 case I40E_ERR_SRQ_ENABLED:
238 return "I40E_ERR_SRQ_ENABLED";
239 case I40E_ERR_ADMIN_QUEUE_ERROR:
240 return "I40E_ERR_ADMIN_QUEUE_ERROR";
241 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
242 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
243 case I40E_ERR_BUF_TOO_SHORT:
244 return "I40E_ERR_BUF_TOO_SHORT";
245 case I40E_ERR_ADMIN_QUEUE_FULL:
246 return "I40E_ERR_ADMIN_QUEUE_FULL";
247 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
248 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
249 case I40E_ERR_BAD_IWARP_CQE:
250 return "I40E_ERR_BAD_IWARP_CQE";
251 case I40E_ERR_NVM_BLANK_MODE:
252 return "I40E_ERR_NVM_BLANK_MODE";
253 case I40E_ERR_NOT_IMPLEMENTED:
254 return "I40E_ERR_NOT_IMPLEMENTED";
255 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
256 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
257 case I40E_ERR_DIAG_TEST_FAILED:
258 return "I40E_ERR_DIAG_TEST_FAILED";
259 case I40E_ERR_NOT_READY:
260 return "I40E_ERR_NOT_READY";
261 case I40E_NOT_SUPPORTED:
262 return "I40E_NOT_SUPPORTED";
263 case I40E_ERR_FIRMWARE_API_VERSION:
264 return "I40E_ERR_FIRMWARE_API_VERSION";
265 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
266 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
267 }
268
269 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
270 return hw->err_str;
271}
272
273/**
274 * i40e_debug_aq
275 * @hw: debug mask related to admin queue
276 * @mask: debug mask
277 * @desc: pointer to admin queue descriptor
278 * @buffer: pointer to command buffer
279 * @buf_len: max length of buffer
280 *
281 * Dumps debug log about adminq command with descriptor contents.
282 **/
283void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
284 void *buffer, u16 buf_len)
285{
286 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
287 u32 effective_mask = hw->debug_mask & mask;
288 char prefix[27];
289 u16 len;
290 u8 *buf = (u8 *)buffer;
291
292 if (!effective_mask || !desc)
293 return;
294
295 len = le16_to_cpu(aq_desc->datalen);
296
297 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
298 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
299 le16_to_cpu(aq_desc->opcode),
300 le16_to_cpu(aq_desc->flags),
301 le16_to_cpu(aq_desc->datalen),
302 le16_to_cpu(aq_desc->retval));
303 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
304 "\tcookie (h,l) 0x%08X 0x%08X\n",
305 le32_to_cpu(aq_desc->cookie_high),
306 le32_to_cpu(aq_desc->cookie_low));
307 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
308 "\tparam (0,1) 0x%08X 0x%08X\n",
309 le32_to_cpu(aq_desc->params.internal.param0),
310 le32_to_cpu(aq_desc->params.internal.param1));
311 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
312 "\taddr (h,l) 0x%08X 0x%08X\n",
313 le32_to_cpu(aq_desc->params.external.addr_high),
314 le32_to_cpu(aq_desc->params.external.addr_low));
315
316 if (buffer && buf_len != 0 && len != 0 &&
317 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) {
318 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
319 if (buf_len < len)
320 len = buf_len;
321
322 snprintf(prefix, sizeof(prefix),
323 "i40e %02x:%02x.%x: \t0x",
324 hw->bus.bus_id,
325 hw->bus.device,
326 hw->bus.func);
327
328 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET,
329 16, 1, buf, len, false);
330 }
331}
332
333/**
334 * i40e_check_asq_alive
335 * @hw: pointer to the hw struct
336 *
337 * Returns true if Queue is enabled else false.
338 **/
339bool i40e_check_asq_alive(struct i40e_hw *hw)
340{
341 if (hw->aq.asq.len)
342 return !!(rd32(hw, hw->aq.asq.len) &
343 I40E_PF_ATQLEN_ATQENABLE_MASK);
344 else
345 return false;
346}
347
348/**
349 * i40e_aq_queue_shutdown
350 * @hw: pointer to the hw struct
351 * @unloading: is the driver unloading itself
352 *
353 * Tell the Firmware that we're shutting down the AdminQ and whether
354 * or not the driver is unloading as well.
355 **/
356i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
357 bool unloading)
358{
359 struct i40e_aq_desc desc;
360 struct i40e_aqc_queue_shutdown *cmd =
361 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
362 i40e_status status;
363
364 i40e_fill_default_direct_cmd_desc(&desc,
365 i40e_aqc_opc_queue_shutdown);
366
367 if (unloading)
368 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
369 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
370
371 return status;
372}
373
374/**
375 * i40e_aq_get_set_rss_lut
376 * @hw: pointer to the hardware structure
377 * @vsi_id: vsi fw index
378 * @pf_lut: for PF table set true, for VSI table set false
379 * @lut: pointer to the lut buffer provided by the caller
380 * @lut_size: size of the lut buffer
381 * @set: set true to set the table, false to get the table
382 *
383 * Internal function to get or set RSS look up table
384 **/
385static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
386 u16 vsi_id, bool pf_lut,
387 u8 *lut, u16 lut_size,
388 bool set)
389{
390 i40e_status status;
391 struct i40e_aq_desc desc;
392 struct i40e_aqc_get_set_rss_lut *cmd_resp =
393 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
394
395 if (set)
396 i40e_fill_default_direct_cmd_desc(&desc,
397 i40e_aqc_opc_set_rss_lut);
398 else
399 i40e_fill_default_direct_cmd_desc(&desc,
400 i40e_aqc_opc_get_rss_lut);
401
402 /* Indirect command */
403 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
404 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
405
406 cmd_resp->vsi_id =
407 cpu_to_le16((u16)((vsi_id <<
408 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
409 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
410 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
411
412 if (pf_lut)
413 cmd_resp->flags |= cpu_to_le16((u16)
414 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
415 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
416 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
417 else
418 cmd_resp->flags |= cpu_to_le16((u16)
419 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
420 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
421 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
422
423 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
424
425 return status;
426}
427
428/**
429 * i40e_aq_get_rss_lut
430 * @hw: pointer to the hardware structure
431 * @vsi_id: vsi fw index
432 * @pf_lut: for PF table set true, for VSI table set false
433 * @lut: pointer to the lut buffer provided by the caller
434 * @lut_size: size of the lut buffer
435 *
436 * get the RSS lookup table, PF or VSI type
437 **/
438i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
439 bool pf_lut, u8 *lut, u16 lut_size)
440{
441 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
442 false);
443}
444
445/**
446 * i40e_aq_set_rss_lut
447 * @hw: pointer to the hardware structure
448 * @vsi_id: vsi fw index
449 * @pf_lut: for PF table set true, for VSI table set false
450 * @lut: pointer to the lut buffer provided by the caller
451 * @lut_size: size of the lut buffer
452 *
453 * set the RSS lookup table, PF or VSI type
454 **/
455i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
456 bool pf_lut, u8 *lut, u16 lut_size)
457{
458 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
459}
460
461/**
462 * i40e_aq_get_set_rss_key
463 * @hw: pointer to the hw struct
464 * @vsi_id: vsi fw index
465 * @key: pointer to key info struct
466 * @set: set true to set the key, false to get the key
467 *
468 * get the RSS key per VSI
469 **/
470static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
471 u16 vsi_id,
472 struct i40e_aqc_get_set_rss_key_data *key,
473 bool set)
474{
475 i40e_status status;
476 struct i40e_aq_desc desc;
477 struct i40e_aqc_get_set_rss_key *cmd_resp =
478 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
479 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
480
481 if (set)
482 i40e_fill_default_direct_cmd_desc(&desc,
483 i40e_aqc_opc_set_rss_key);
484 else
485 i40e_fill_default_direct_cmd_desc(&desc,
486 i40e_aqc_opc_get_rss_key);
487
488 /* Indirect command */
489 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
490 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
491
492 cmd_resp->vsi_id =
493 cpu_to_le16((u16)((vsi_id <<
494 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
495 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
496 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
497
498 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
499
500 return status;
501}
502
503/**
504 * i40e_aq_get_rss_key
505 * @hw: pointer to the hw struct
506 * @vsi_id: vsi fw index
507 * @key: pointer to key info struct
508 *
509 **/
510i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
511 u16 vsi_id,
512 struct i40e_aqc_get_set_rss_key_data *key)
513{
514 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
515}
516
517/**
518 * i40e_aq_set_rss_key
519 * @hw: pointer to the hw struct
520 * @vsi_id: vsi fw index
521 * @key: pointer to key info struct
522 *
523 * set the RSS key per VSI
524 **/
525i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
526 u16 vsi_id,
527 struct i40e_aqc_get_set_rss_key_data *key)
528{
529 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
530}
531
532/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
533 * hardware to a bit-field that can be used by SW to more easily determine the
534 * packet type.
535 *
536 * Macros are used to shorten the table lines and make this table human
537 * readable.
538 *
539 * We store the PTYPE in the top byte of the bit field - this is just so that
540 * we can check that the table doesn't have a row missing, as the index into
541 * the table should be the PTYPE.
542 *
543 * Typical work flow:
544 *
545 * IF NOT i40e_ptype_lookup[ptype].known
546 * THEN
547 * Packet is unknown
548 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
549 * Use the rest of the fields to look at the tunnels, inner protocols, etc
550 * ELSE
551 * Use the enum i40e_rx_l2_ptype to decode the packet type
552 * ENDIF
553 */
554
555/* macro to make the table lines short */
556#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
557 { PTYPE, \
558 1, \
559 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
560 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
561 I40E_RX_PTYPE_##OUTER_FRAG, \
562 I40E_RX_PTYPE_TUNNEL_##T, \
563 I40E_RX_PTYPE_TUNNEL_END_##TE, \
564 I40E_RX_PTYPE_##TEF, \
565 I40E_RX_PTYPE_INNER_PROT_##I, \
566 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
567
568#define I40E_PTT_UNUSED_ENTRY(PTYPE) \
569 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
570
571/* shorter macros makes the table fit but are terse */
572#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
573#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
574#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
575
576/* Lookup table mapping the HW PTYPE to the bit field for decoding */
577struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
578 /* L2 Packet types */
579 I40E_PTT_UNUSED_ENTRY(0),
580 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
581 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
582 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
583 I40E_PTT_UNUSED_ENTRY(4),
584 I40E_PTT_UNUSED_ENTRY(5),
585 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
586 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
587 I40E_PTT_UNUSED_ENTRY(8),
588 I40E_PTT_UNUSED_ENTRY(9),
589 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
590 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
591 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
592 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
593 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
594 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
595 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
596 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
597 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
598 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
599 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
600 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
601
602 /* Non Tunneled IPv4 */
603 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
604 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
605 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
606 I40E_PTT_UNUSED_ENTRY(25),
607 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
608 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
609 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
610
611 /* IPv4 --> IPv4 */
612 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
613 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
614 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
615 I40E_PTT_UNUSED_ENTRY(32),
616 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
617 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
618 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
619
620 /* IPv4 --> IPv6 */
621 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
622 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
623 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
624 I40E_PTT_UNUSED_ENTRY(39),
625 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
626 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
627 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
628
629 /* IPv4 --> GRE/NAT */
630 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
631
632 /* IPv4 --> GRE/NAT --> IPv4 */
633 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
634 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
635 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
636 I40E_PTT_UNUSED_ENTRY(47),
637 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
638 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
639 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
640
641 /* IPv4 --> GRE/NAT --> IPv6 */
642 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
643 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
644 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
645 I40E_PTT_UNUSED_ENTRY(54),
646 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
647 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
648 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
649
650 /* IPv4 --> GRE/NAT --> MAC */
651 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
652
653 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
654 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
655 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
656 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
657 I40E_PTT_UNUSED_ENTRY(62),
658 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
659 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
660 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
661
662 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
663 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
664 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
665 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
666 I40E_PTT_UNUSED_ENTRY(69),
667 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
668 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
669 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
670
671 /* IPv4 --> GRE/NAT --> MAC/VLAN */
672 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
673
674 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
675 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
676 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
677 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
678 I40E_PTT_UNUSED_ENTRY(77),
679 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
680 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
681 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
682
683 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
684 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
685 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
686 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
687 I40E_PTT_UNUSED_ENTRY(84),
688 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
689 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
690 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
691
692 /* Non Tunneled IPv6 */
693 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
694 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
695 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
696 I40E_PTT_UNUSED_ENTRY(91),
697 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
698 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
699 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
700
701 /* IPv6 --> IPv4 */
702 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
703 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
704 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
705 I40E_PTT_UNUSED_ENTRY(98),
706 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
707 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
708 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
709
710 /* IPv6 --> IPv6 */
711 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
712 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
713 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
714 I40E_PTT_UNUSED_ENTRY(105),
715 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
716 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
717 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
718
719 /* IPv6 --> GRE/NAT */
720 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
721
722 /* IPv6 --> GRE/NAT -> IPv4 */
723 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
724 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
725 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
726 I40E_PTT_UNUSED_ENTRY(113),
727 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
728 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
729 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
730
731 /* IPv6 --> GRE/NAT -> IPv6 */
732 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
733 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
734 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
735 I40E_PTT_UNUSED_ENTRY(120),
736 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
737 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
738 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
739
740 /* IPv6 --> GRE/NAT -> MAC */
741 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
742
743 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
744 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
745 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
746 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
747 I40E_PTT_UNUSED_ENTRY(128),
748 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
749 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
750 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
751
752 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
753 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
754 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
755 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
756 I40E_PTT_UNUSED_ENTRY(135),
757 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
758 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
759 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
760
761 /* IPv6 --> GRE/NAT -> MAC/VLAN */
762 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
763
764 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
765 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
766 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
767 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
768 I40E_PTT_UNUSED_ENTRY(143),
769 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
770 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
771 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
772
773 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
774 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
775 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
776 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
777 I40E_PTT_UNUSED_ENTRY(150),
778 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
779 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
780 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
781
782 /* unused entries */
783 I40E_PTT_UNUSED_ENTRY(154),
784 I40E_PTT_UNUSED_ENTRY(155),
785 I40E_PTT_UNUSED_ENTRY(156),
786 I40E_PTT_UNUSED_ENTRY(157),
787 I40E_PTT_UNUSED_ENTRY(158),
788 I40E_PTT_UNUSED_ENTRY(159),
789
790 I40E_PTT_UNUSED_ENTRY(160),
791 I40E_PTT_UNUSED_ENTRY(161),
792 I40E_PTT_UNUSED_ENTRY(162),
793 I40E_PTT_UNUSED_ENTRY(163),
794 I40E_PTT_UNUSED_ENTRY(164),
795 I40E_PTT_UNUSED_ENTRY(165),
796 I40E_PTT_UNUSED_ENTRY(166),
797 I40E_PTT_UNUSED_ENTRY(167),
798 I40E_PTT_UNUSED_ENTRY(168),
799 I40E_PTT_UNUSED_ENTRY(169),
800
801 I40E_PTT_UNUSED_ENTRY(170),
802 I40E_PTT_UNUSED_ENTRY(171),
803 I40E_PTT_UNUSED_ENTRY(172),
804 I40E_PTT_UNUSED_ENTRY(173),
805 I40E_PTT_UNUSED_ENTRY(174),
806 I40E_PTT_UNUSED_ENTRY(175),
807 I40E_PTT_UNUSED_ENTRY(176),
808 I40E_PTT_UNUSED_ENTRY(177),
809 I40E_PTT_UNUSED_ENTRY(178),
810 I40E_PTT_UNUSED_ENTRY(179),
811
812 I40E_PTT_UNUSED_ENTRY(180),
813 I40E_PTT_UNUSED_ENTRY(181),
814 I40E_PTT_UNUSED_ENTRY(182),
815 I40E_PTT_UNUSED_ENTRY(183),
816 I40E_PTT_UNUSED_ENTRY(184),
817 I40E_PTT_UNUSED_ENTRY(185),
818 I40E_PTT_UNUSED_ENTRY(186),
819 I40E_PTT_UNUSED_ENTRY(187),
820 I40E_PTT_UNUSED_ENTRY(188),
821 I40E_PTT_UNUSED_ENTRY(189),
822
823 I40E_PTT_UNUSED_ENTRY(190),
824 I40E_PTT_UNUSED_ENTRY(191),
825 I40E_PTT_UNUSED_ENTRY(192),
826 I40E_PTT_UNUSED_ENTRY(193),
827 I40E_PTT_UNUSED_ENTRY(194),
828 I40E_PTT_UNUSED_ENTRY(195),
829 I40E_PTT_UNUSED_ENTRY(196),
830 I40E_PTT_UNUSED_ENTRY(197),
831 I40E_PTT_UNUSED_ENTRY(198),
832 I40E_PTT_UNUSED_ENTRY(199),
833
834 I40E_PTT_UNUSED_ENTRY(200),
835 I40E_PTT_UNUSED_ENTRY(201),
836 I40E_PTT_UNUSED_ENTRY(202),
837 I40E_PTT_UNUSED_ENTRY(203),
838 I40E_PTT_UNUSED_ENTRY(204),
839 I40E_PTT_UNUSED_ENTRY(205),
840 I40E_PTT_UNUSED_ENTRY(206),
841 I40E_PTT_UNUSED_ENTRY(207),
842 I40E_PTT_UNUSED_ENTRY(208),
843 I40E_PTT_UNUSED_ENTRY(209),
844
845 I40E_PTT_UNUSED_ENTRY(210),
846 I40E_PTT_UNUSED_ENTRY(211),
847 I40E_PTT_UNUSED_ENTRY(212),
848 I40E_PTT_UNUSED_ENTRY(213),
849 I40E_PTT_UNUSED_ENTRY(214),
850 I40E_PTT_UNUSED_ENTRY(215),
851 I40E_PTT_UNUSED_ENTRY(216),
852 I40E_PTT_UNUSED_ENTRY(217),
853 I40E_PTT_UNUSED_ENTRY(218),
854 I40E_PTT_UNUSED_ENTRY(219),
855
856 I40E_PTT_UNUSED_ENTRY(220),
857 I40E_PTT_UNUSED_ENTRY(221),
858 I40E_PTT_UNUSED_ENTRY(222),
859 I40E_PTT_UNUSED_ENTRY(223),
860 I40E_PTT_UNUSED_ENTRY(224),
861 I40E_PTT_UNUSED_ENTRY(225),
862 I40E_PTT_UNUSED_ENTRY(226),
863 I40E_PTT_UNUSED_ENTRY(227),
864 I40E_PTT_UNUSED_ENTRY(228),
865 I40E_PTT_UNUSED_ENTRY(229),
866
867 I40E_PTT_UNUSED_ENTRY(230),
868 I40E_PTT_UNUSED_ENTRY(231),
869 I40E_PTT_UNUSED_ENTRY(232),
870 I40E_PTT_UNUSED_ENTRY(233),
871 I40E_PTT_UNUSED_ENTRY(234),
872 I40E_PTT_UNUSED_ENTRY(235),
873 I40E_PTT_UNUSED_ENTRY(236),
874 I40E_PTT_UNUSED_ENTRY(237),
875 I40E_PTT_UNUSED_ENTRY(238),
876 I40E_PTT_UNUSED_ENTRY(239),
877
878 I40E_PTT_UNUSED_ENTRY(240),
879 I40E_PTT_UNUSED_ENTRY(241),
880 I40E_PTT_UNUSED_ENTRY(242),
881 I40E_PTT_UNUSED_ENTRY(243),
882 I40E_PTT_UNUSED_ENTRY(244),
883 I40E_PTT_UNUSED_ENTRY(245),
884 I40E_PTT_UNUSED_ENTRY(246),
885 I40E_PTT_UNUSED_ENTRY(247),
886 I40E_PTT_UNUSED_ENTRY(248),
887 I40E_PTT_UNUSED_ENTRY(249),
888
889 I40E_PTT_UNUSED_ENTRY(250),
890 I40E_PTT_UNUSED_ENTRY(251),
891 I40E_PTT_UNUSED_ENTRY(252),
892 I40E_PTT_UNUSED_ENTRY(253),
893 I40E_PTT_UNUSED_ENTRY(254),
894 I40E_PTT_UNUSED_ENTRY(255)
895};
896
897/**
898 * i40e_init_shared_code - Initialize the shared code
899 * @hw: pointer to hardware structure
900 *
901 * This assigns the MAC type and PHY code and inits the NVM.
902 * Does not touch the hardware. This function must be called prior to any
903 * other function in the shared code. The i40e_hw structure should be
904 * memset to 0 prior to calling this function. The following fields in
905 * hw structure should be filled in prior to calling this function:
906 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
907 * subsystem_vendor_id, and revision_id
908 **/
909i40e_status i40e_init_shared_code(struct i40e_hw *hw)
910{
911 i40e_status status = 0;
912 u32 port, ari, func_rid;
913
914 i40e_set_mac_type(hw);
915
916 switch (hw->mac.type) {
917 case I40E_MAC_XL710:
918 case I40E_MAC_X722:
919 break;
920 default:
921 return I40E_ERR_DEVICE_NOT_SUPPORTED;
922 }
923
924 hw->phy.get_link_info = true;
925
926 /* Determine port number and PF number*/
927 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
928 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
929 hw->port = (u8)port;
930 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
931 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
932 func_rid = rd32(hw, I40E_PF_FUNC_RID);
933 if (ari)
934 hw->pf_id = (u8)(func_rid & 0xff);
935 else
936 hw->pf_id = (u8)(func_rid & 0x7);
937
938 status = i40e_init_nvm(hw);
939 return status;
940}
941
942/**
943 * i40e_aq_mac_address_read - Retrieve the MAC addresses
944 * @hw: pointer to the hw struct
945 * @flags: a return indicator of what addresses were added to the addr store
946 * @addrs: the requestor's mac addr store
947 * @cmd_details: pointer to command details structure or NULL
948 **/
949static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
950 u16 *flags,
951 struct i40e_aqc_mac_address_read_data *addrs,
952 struct i40e_asq_cmd_details *cmd_details)
953{
954 struct i40e_aq_desc desc;
955 struct i40e_aqc_mac_address_read *cmd_data =
956 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
957 i40e_status status;
958
959 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
960 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
961
962 status = i40e_asq_send_command(hw, &desc, addrs,
963 sizeof(*addrs), cmd_details);
964 *flags = le16_to_cpu(cmd_data->command_flags);
965
966 return status;
967}
968
969/**
970 * i40e_aq_mac_address_write - Change the MAC addresses
971 * @hw: pointer to the hw struct
972 * @flags: indicates which MAC to be written
973 * @mac_addr: address to write
974 * @cmd_details: pointer to command details structure or NULL
975 **/
976i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
977 u16 flags, u8 *mac_addr,
978 struct i40e_asq_cmd_details *cmd_details)
979{
980 struct i40e_aq_desc desc;
981 struct i40e_aqc_mac_address_write *cmd_data =
982 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
983 i40e_status status;
984
985 i40e_fill_default_direct_cmd_desc(&desc,
986 i40e_aqc_opc_mac_address_write);
987 cmd_data->command_flags = cpu_to_le16(flags);
988 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
989 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
990 ((u32)mac_addr[3] << 16) |
991 ((u32)mac_addr[4] << 8) |
992 mac_addr[5]);
993
994 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
995
996 return status;
997}
998
999/**
1000 * i40e_get_mac_addr - get MAC address
1001 * @hw: pointer to the HW structure
1002 * @mac_addr: pointer to MAC address
1003 *
1004 * Reads the adapter's MAC address from register
1005 **/
1006i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1007{
1008 struct i40e_aqc_mac_address_read_data addrs;
1009 i40e_status status;
1010 u16 flags = 0;
1011
1012 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1013
1014 if (flags & I40E_AQC_LAN_ADDR_VALID)
1015 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
1016
1017 return status;
1018}
1019
1020/**
1021 * i40e_get_port_mac_addr - get Port MAC address
1022 * @hw: pointer to the HW structure
1023 * @mac_addr: pointer to Port MAC address
1024 *
1025 * Reads the adapter's Port MAC address
1026 **/
1027i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1028{
1029 struct i40e_aqc_mac_address_read_data addrs;
1030 i40e_status status;
1031 u16 flags = 0;
1032
1033 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1034 if (status)
1035 return status;
1036
1037 if (flags & I40E_AQC_PORT_ADDR_VALID)
1038 ether_addr_copy(mac_addr, addrs.port_mac);
1039 else
1040 status = I40E_ERR_INVALID_MAC_ADDR;
1041
1042 return status;
1043}
1044
1045/**
1046 * i40e_pre_tx_queue_cfg - pre tx queue configure
1047 * @hw: pointer to the HW structure
1048 * @queue: target PF queue index
1049 * @enable: state change request
1050 *
1051 * Handles hw requirement to indicate intention to enable
1052 * or disable target queue.
1053 **/
1054void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1055{
1056 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1057 u32 reg_block = 0;
1058 u32 reg_val;
1059
1060 if (abs_queue_idx >= 128) {
1061 reg_block = abs_queue_idx / 128;
1062 abs_queue_idx %= 128;
1063 }
1064
1065 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1066 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1067 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1068
1069 if (enable)
1070 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1071 else
1072 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1073
1074 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1075}
1076
1077/**
1078 * i40e_read_pba_string - Reads part number string from EEPROM
1079 * @hw: pointer to hardware structure
1080 * @pba_num: stores the part number string from the EEPROM
1081 * @pba_num_size: part number string buffer length
1082 *
1083 * Reads the part number string from the EEPROM.
1084 **/
1085i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1086 u32 pba_num_size)
1087{
1088 i40e_status status = 0;
1089 u16 pba_word = 0;
1090 u16 pba_size = 0;
1091 u16 pba_ptr = 0;
1092 u16 i = 0;
1093
1094 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1095 if (status || (pba_word != 0xFAFA)) {
1096 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1097 return status;
1098 }
1099
1100 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1101 if (status) {
1102 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1103 return status;
1104 }
1105
1106 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1107 if (status) {
1108 hw_dbg(hw, "Failed to read PBA Block size.\n");
1109 return status;
1110 }
1111
1112 /* Subtract one to get PBA word count (PBA Size word is included in
1113 * total size)
1114 */
1115 pba_size--;
1116 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1117 hw_dbg(hw, "Buffer too small for PBA data.\n");
1118 return I40E_ERR_PARAM;
1119 }
1120
1121 for (i = 0; i < pba_size; i++) {
1122 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1123 if (status) {
1124 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1125 return status;
1126 }
1127
1128 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1129 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1130 }
1131 pba_num[(pba_size * 2)] = '\0';
1132
1133 return status;
1134}
1135
1136/**
1137 * i40e_get_media_type - Gets media type
1138 * @hw: pointer to the hardware structure
1139 **/
1140static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1141{
1142 enum i40e_media_type media;
1143
1144 switch (hw->phy.link_info.phy_type) {
1145 case I40E_PHY_TYPE_10GBASE_SR:
1146 case I40E_PHY_TYPE_10GBASE_LR:
1147 case I40E_PHY_TYPE_1000BASE_SX:
1148 case I40E_PHY_TYPE_1000BASE_LX:
1149 case I40E_PHY_TYPE_40GBASE_SR4:
1150 case I40E_PHY_TYPE_40GBASE_LR4:
1151 case I40E_PHY_TYPE_25GBASE_LR:
1152 case I40E_PHY_TYPE_25GBASE_SR:
1153 media = I40E_MEDIA_TYPE_FIBER;
1154 break;
1155 case I40E_PHY_TYPE_100BASE_TX:
1156 case I40E_PHY_TYPE_1000BASE_T:
1157 case I40E_PHY_TYPE_2_5GBASE_T:
1158 case I40E_PHY_TYPE_5GBASE_T:
1159 case I40E_PHY_TYPE_10GBASE_T:
1160 media = I40E_MEDIA_TYPE_BASET;
1161 break;
1162 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1163 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1164 case I40E_PHY_TYPE_10GBASE_CR1:
1165 case I40E_PHY_TYPE_40GBASE_CR4:
1166 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1167 case I40E_PHY_TYPE_40GBASE_AOC:
1168 case I40E_PHY_TYPE_10GBASE_AOC:
1169 case I40E_PHY_TYPE_25GBASE_CR:
1170 case I40E_PHY_TYPE_25GBASE_AOC:
1171 case I40E_PHY_TYPE_25GBASE_ACC:
1172 media = I40E_MEDIA_TYPE_DA;
1173 break;
1174 case I40E_PHY_TYPE_1000BASE_KX:
1175 case I40E_PHY_TYPE_10GBASE_KX4:
1176 case I40E_PHY_TYPE_10GBASE_KR:
1177 case I40E_PHY_TYPE_40GBASE_KR4:
1178 case I40E_PHY_TYPE_20GBASE_KR2:
1179 case I40E_PHY_TYPE_25GBASE_KR:
1180 media = I40E_MEDIA_TYPE_BACKPLANE;
1181 break;
1182 case I40E_PHY_TYPE_SGMII:
1183 case I40E_PHY_TYPE_XAUI:
1184 case I40E_PHY_TYPE_XFI:
1185 case I40E_PHY_TYPE_XLAUI:
1186 case I40E_PHY_TYPE_XLPPI:
1187 default:
1188 media = I40E_MEDIA_TYPE_UNKNOWN;
1189 break;
1190 }
1191
1192 return media;
1193}
1194
1195/**
1196 * i40e_poll_globr - Poll for Global Reset completion
1197 * @hw: pointer to the hardware structure
1198 * @retry_limit: how many times to retry before failure
1199 **/
1200static i40e_status i40e_poll_globr(struct i40e_hw *hw,
1201 u32 retry_limit)
1202{
1203 u32 cnt, reg = 0;
1204
1205 for (cnt = 0; cnt < retry_limit; cnt++) {
1206 reg = rd32(hw, I40E_GLGEN_RSTAT);
1207 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1208 return 0;
1209 msleep(100);
1210 }
1211
1212 hw_dbg(hw, "Global reset failed.\n");
1213 hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg);
1214
1215 return I40E_ERR_RESET_FAILED;
1216}
1217
1218#define I40E_PF_RESET_WAIT_COUNT_A0 200
1219#define I40E_PF_RESET_WAIT_COUNT 200
1220/**
1221 * i40e_pf_reset - Reset the PF
1222 * @hw: pointer to the hardware structure
1223 *
1224 * Assuming someone else has triggered a global reset,
1225 * assure the global reset is complete and then reset the PF
1226 **/
1227i40e_status i40e_pf_reset(struct i40e_hw *hw)
1228{
1229 u32 cnt = 0;
1230 u32 cnt1 = 0;
1231 u32 reg = 0;
1232 u32 grst_del;
1233
1234 /* Poll for Global Reset steady state in case of recent GRST.
1235 * The grst delay value is in 100ms units, and we'll wait a
1236 * couple counts longer to be sure we don't just miss the end.
1237 */
1238 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1239 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1240 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1241
1242 /* It can take upto 15 secs for GRST steady state.
1243 * Bump it to 16 secs max to be safe.
1244 */
1245 grst_del = grst_del * 20;
1246
1247 for (cnt = 0; cnt < grst_del; cnt++) {
1248 reg = rd32(hw, I40E_GLGEN_RSTAT);
1249 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1250 break;
1251 msleep(100);
1252 }
1253 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1254 hw_dbg(hw, "Global reset polling failed to complete.\n");
1255 return I40E_ERR_RESET_FAILED;
1256 }
1257
1258 /* Now Wait for the FW to be ready */
1259 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1260 reg = rd32(hw, I40E_GLNVM_ULD);
1261 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1262 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1263 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1264 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1265 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1266 break;
1267 }
1268 usleep_range(10000, 20000);
1269 }
1270 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1271 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1272 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1273 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
1274 return I40E_ERR_RESET_FAILED;
1275 }
1276
1277 /* If there was a Global Reset in progress when we got here,
1278 * we don't need to do the PF Reset
1279 */
1280 if (!cnt) {
1281 u32 reg2 = 0;
1282 if (hw->revision_id == 0)
1283 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1284 else
1285 cnt = I40E_PF_RESET_WAIT_COUNT;
1286 reg = rd32(hw, I40E_PFGEN_CTRL);
1287 wr32(hw, I40E_PFGEN_CTRL,
1288 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1289 for (; cnt; cnt--) {
1290 reg = rd32(hw, I40E_PFGEN_CTRL);
1291 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1292 break;
1293 reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1294 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1295 break;
1296 usleep_range(1000, 2000);
1297 }
1298 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1299 if (i40e_poll_globr(hw, grst_del))
1300 return I40E_ERR_RESET_FAILED;
1301 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1302 hw_dbg(hw, "PF reset polling failed to complete.\n");
1303 return I40E_ERR_RESET_FAILED;
1304 }
1305 }
1306
1307 i40e_clear_pxe_mode(hw);
1308
1309 return 0;
1310}
1311
1312/**
1313 * i40e_clear_hw - clear out any left over hw state
1314 * @hw: pointer to the hw struct
1315 *
1316 * Clear queues and interrupts, typically called at init time,
1317 * but after the capabilities have been found so we know how many
1318 * queues and msix vectors have been allocated.
1319 **/
1320void i40e_clear_hw(struct i40e_hw *hw)
1321{
1322 u32 num_queues, base_queue;
1323 u32 num_pf_int;
1324 u32 num_vf_int;
1325 u32 num_vfs;
1326 u32 i, j;
1327 u32 val;
1328 u32 eol = 0x7ff;
1329
1330 /* get number of interrupts, queues, and VFs */
1331 val = rd32(hw, I40E_GLPCI_CNF2);
1332 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1333 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1334 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1335 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1336
1337 val = rd32(hw, I40E_PFLAN_QALLOC);
1338 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1339 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1340 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1341 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1342 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1343 num_queues = (j - base_queue) + 1;
1344 else
1345 num_queues = 0;
1346
1347 val = rd32(hw, I40E_PF_VT_PFALLOC);
1348 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1349 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1350 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1351 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1352 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1353 num_vfs = (j - i) + 1;
1354 else
1355 num_vfs = 0;
1356
1357 /* stop all the interrupts */
1358 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1359 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1360 for (i = 0; i < num_pf_int - 2; i++)
1361 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1362
1363 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1364 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1365 wr32(hw, I40E_PFINT_LNKLST0, val);
1366 for (i = 0; i < num_pf_int - 2; i++)
1367 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1368 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1369 for (i = 0; i < num_vfs; i++)
1370 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1371 for (i = 0; i < num_vf_int - 2; i++)
1372 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1373
1374 /* warn the HW of the coming Tx disables */
1375 for (i = 0; i < num_queues; i++) {
1376 u32 abs_queue_idx = base_queue + i;
1377 u32 reg_block = 0;
1378
1379 if (abs_queue_idx >= 128) {
1380 reg_block = abs_queue_idx / 128;
1381 abs_queue_idx %= 128;
1382 }
1383
1384 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1385 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1386 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1387 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1388
1389 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1390 }
1391 udelay(400);
1392
1393 /* stop all the queues */
1394 for (i = 0; i < num_queues; i++) {
1395 wr32(hw, I40E_QINT_TQCTL(i), 0);
1396 wr32(hw, I40E_QTX_ENA(i), 0);
1397 wr32(hw, I40E_QINT_RQCTL(i), 0);
1398 wr32(hw, I40E_QRX_ENA(i), 0);
1399 }
1400
1401 /* short wait for all queue disables to settle */
1402 udelay(50);
1403}
1404
1405/**
1406 * i40e_clear_pxe_mode - clear pxe operations mode
1407 * @hw: pointer to the hw struct
1408 *
1409 * Make sure all PXE mode settings are cleared, including things
1410 * like descriptor fetch/write-back mode.
1411 **/
1412void i40e_clear_pxe_mode(struct i40e_hw *hw)
1413{
1414 u32 reg;
1415
1416 if (i40e_check_asq_alive(hw))
1417 i40e_aq_clear_pxe_mode(hw, NULL);
1418
1419 /* Clear single descriptor fetch/write-back mode */
1420 reg = rd32(hw, I40E_GLLAN_RCTL_0);
1421
1422 if (hw->revision_id == 0) {
1423 /* As a work around clear PXE_MODE instead of setting it */
1424 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1425 } else {
1426 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1427 }
1428}
1429
1430/**
1431 * i40e_led_is_mine - helper to find matching led
1432 * @hw: pointer to the hw struct
1433 * @idx: index into GPIO registers
1434 *
1435 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1436 */
1437static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1438{
1439 u32 gpio_val = 0;
1440 u32 port;
1441
1442 if (!I40E_IS_X710TL_DEVICE(hw->device_id) &&
1443 !hw->func_caps.led[idx])
1444 return 0;
1445 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1446 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1447 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1448
1449 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1450 * if it is not our port then ignore
1451 */
1452 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1453 (port != hw->port))
1454 return 0;
1455
1456 return gpio_val;
1457}
1458
1459#define I40E_FW_LED BIT(4)
1460#define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \
1461 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
1462
1463#define I40E_LED0 22
1464
1465#define I40E_PIN_FUNC_SDP 0x0
1466#define I40E_PIN_FUNC_LED 0x1
1467
1468/**
1469 * i40e_led_get - return current on/off mode
1470 * @hw: pointer to the hw struct
1471 *
1472 * The value returned is the 'mode' field as defined in the
1473 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1474 * values are variations of possible behaviors relating to
1475 * blink, link, and wire.
1476 **/
1477u32 i40e_led_get(struct i40e_hw *hw)
1478{
1479 u32 mode = 0;
1480 int i;
1481
1482 /* as per the documentation GPIO 22-29 are the LED
1483 * GPIO pins named LED0..LED7
1484 */
1485 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1486 u32 gpio_val = i40e_led_is_mine(hw, i);
1487
1488 if (!gpio_val)
1489 continue;
1490
1491 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1492 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1493 break;
1494 }
1495
1496 return mode;
1497}
1498
1499/**
1500 * i40e_led_set - set new on/off mode
1501 * @hw: pointer to the hw struct
1502 * @mode: 0=off, 0xf=on (else see manual for mode details)
1503 * @blink: true if the LED should blink when on, false if steady
1504 *
1505 * if this function is used to turn on the blink it should
1506 * be used to disable the blink when restoring the original state.
1507 **/
1508void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1509{
1510 int i;
1511
1512 if (mode & ~I40E_LED_MODE_VALID) {
1513 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1514 return;
1515 }
1516
1517 /* as per the documentation GPIO 22-29 are the LED
1518 * GPIO pins named LED0..LED7
1519 */
1520 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1521 u32 gpio_val = i40e_led_is_mine(hw, i);
1522
1523 if (!gpio_val)
1524 continue;
1525
1526 if (I40E_IS_X710TL_DEVICE(hw->device_id)) {
1527 u32 pin_func = 0;
1528
1529 if (mode & I40E_FW_LED)
1530 pin_func = I40E_PIN_FUNC_SDP;
1531 else
1532 pin_func = I40E_PIN_FUNC_LED;
1533
1534 gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK;
1535 gpio_val |= ((pin_func <<
1536 I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) &
1537 I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK);
1538 }
1539 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1540 /* this & is a bit of paranoia, but serves as a range check */
1541 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1542 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1543
1544 if (blink)
1545 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1546 else
1547 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1548
1549 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1550 break;
1551 }
1552}
1553
1554/* Admin command wrappers */
1555
1556/**
1557 * i40e_aq_get_phy_capabilities
1558 * @hw: pointer to the hw struct
1559 * @abilities: structure for PHY capabilities to be filled
1560 * @qualified_modules: report Qualified Modules
1561 * @report_init: report init capabilities (active are default)
1562 * @cmd_details: pointer to command details structure or NULL
1563 *
1564 * Returns the various PHY abilities supported on the Port.
1565 **/
1566i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1567 bool qualified_modules, bool report_init,
1568 struct i40e_aq_get_phy_abilities_resp *abilities,
1569 struct i40e_asq_cmd_details *cmd_details)
1570{
1571 struct i40e_aq_desc desc;
1572 i40e_status status;
1573 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1574 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1575
1576 if (!abilities)
1577 return I40E_ERR_PARAM;
1578
1579 do {
1580 i40e_fill_default_direct_cmd_desc(&desc,
1581 i40e_aqc_opc_get_phy_abilities);
1582
1583 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1584 if (abilities_size > I40E_AQ_LARGE_BUF)
1585 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1586
1587 if (qualified_modules)
1588 desc.params.external.param0 |=
1589 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1590
1591 if (report_init)
1592 desc.params.external.param0 |=
1593 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1594
1595 status = i40e_asq_send_command(hw, &desc, abilities,
1596 abilities_size, cmd_details);
1597
1598 switch (hw->aq.asq_last_status) {
1599 case I40E_AQ_RC_EIO:
1600 status = I40E_ERR_UNKNOWN_PHY;
1601 break;
1602 case I40E_AQ_RC_EAGAIN:
1603 usleep_range(1000, 2000);
1604 total_delay++;
1605 status = I40E_ERR_TIMEOUT;
1606 break;
1607 /* also covers I40E_AQ_RC_OK */
1608 default:
1609 break;
1610 }
1611
1612 } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) &&
1613 (total_delay < max_delay));
1614
1615 if (status)
1616 return status;
1617
1618 if (report_init) {
1619 if (hw->mac.type == I40E_MAC_XL710 &&
1620 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1621 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1622 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1623 } else {
1624 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1625 hw->phy.phy_types |=
1626 ((u64)abilities->phy_type_ext << 32);
1627 }
1628 }
1629
1630 return status;
1631}
1632
1633/**
1634 * i40e_aq_set_phy_config
1635 * @hw: pointer to the hw struct
1636 * @config: structure with PHY configuration to be set
1637 * @cmd_details: pointer to command details structure or NULL
1638 *
1639 * Set the various PHY configuration parameters
1640 * supported on the Port.One or more of the Set PHY config parameters may be
1641 * ignored in an MFP mode as the PF may not have the privilege to set some
1642 * of the PHY Config parameters. This status will be indicated by the
1643 * command response.
1644 **/
1645enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1646 struct i40e_aq_set_phy_config *config,
1647 struct i40e_asq_cmd_details *cmd_details)
1648{
1649 struct i40e_aq_desc desc;
1650 struct i40e_aq_set_phy_config *cmd =
1651 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1652 enum i40e_status_code status;
1653
1654 if (!config)
1655 return I40E_ERR_PARAM;
1656
1657 i40e_fill_default_direct_cmd_desc(&desc,
1658 i40e_aqc_opc_set_phy_config);
1659
1660 *cmd = *config;
1661
1662 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1663
1664 return status;
1665}
1666
1667static noinline_for_stack enum i40e_status_code
1668i40e_set_fc_status(struct i40e_hw *hw,
1669 struct i40e_aq_get_phy_abilities_resp *abilities,
1670 bool atomic_restart)
1671{
1672 struct i40e_aq_set_phy_config config;
1673 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1674 u8 pause_mask = 0x0;
1675
1676 switch (fc_mode) {
1677 case I40E_FC_FULL:
1678 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1679 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1680 break;
1681 case I40E_FC_RX_PAUSE:
1682 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1683 break;
1684 case I40E_FC_TX_PAUSE:
1685 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1686 break;
1687 default:
1688 break;
1689 }
1690
1691 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1692 /* clear the old pause settings */
1693 config.abilities = abilities->abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1694 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1695 /* set the new abilities */
1696 config.abilities |= pause_mask;
1697 /* If the abilities have changed, then set the new config */
1698 if (config.abilities == abilities->abilities)
1699 return 0;
1700
1701 /* Auto restart link so settings take effect */
1702 if (atomic_restart)
1703 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1704 /* Copy over all the old settings */
1705 config.phy_type = abilities->phy_type;
1706 config.phy_type_ext = abilities->phy_type_ext;
1707 config.link_speed = abilities->link_speed;
1708 config.eee_capability = abilities->eee_capability;
1709 config.eeer = abilities->eeer_val;
1710 config.low_power_ctrl = abilities->d3_lpan;
1711 config.fec_config = abilities->fec_cfg_curr_mod_ext_info &
1712 I40E_AQ_PHY_FEC_CONFIG_MASK;
1713
1714 return i40e_aq_set_phy_config(hw, &config, NULL);
1715}
1716
1717/**
1718 * i40e_set_fc
1719 * @hw: pointer to the hw struct
1720 * @aq_failures: buffer to return AdminQ failure information
1721 * @atomic_restart: whether to enable atomic link restart
1722 *
1723 * Set the requested flow control mode using set_phy_config.
1724 **/
1725enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1726 bool atomic_restart)
1727{
1728 struct i40e_aq_get_phy_abilities_resp abilities;
1729 enum i40e_status_code status;
1730
1731 *aq_failures = 0x0;
1732
1733 /* Get the current phy config */
1734 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1735 NULL);
1736 if (status) {
1737 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1738 return status;
1739 }
1740
1741 status = i40e_set_fc_status(hw, &abilities, atomic_restart);
1742 if (status)
1743 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1744
1745 /* Update the link info */
1746 status = i40e_update_link_info(hw);
1747 if (status) {
1748 /* Wait a little bit (on 40G cards it sometimes takes a really
1749 * long time for link to come back from the atomic reset)
1750 * and try once more
1751 */
1752 msleep(1000);
1753 status = i40e_update_link_info(hw);
1754 }
1755 if (status)
1756 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1757
1758 return status;
1759}
1760
1761/**
1762 * i40e_aq_clear_pxe_mode
1763 * @hw: pointer to the hw struct
1764 * @cmd_details: pointer to command details structure or NULL
1765 *
1766 * Tell the firmware that the driver is taking over from PXE
1767 **/
1768i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1769 struct i40e_asq_cmd_details *cmd_details)
1770{
1771 i40e_status status;
1772 struct i40e_aq_desc desc;
1773 struct i40e_aqc_clear_pxe *cmd =
1774 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1775
1776 i40e_fill_default_direct_cmd_desc(&desc,
1777 i40e_aqc_opc_clear_pxe_mode);
1778
1779 cmd->rx_cnt = 0x2;
1780
1781 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1782
1783 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1784
1785 return status;
1786}
1787
1788/**
1789 * i40e_aq_set_link_restart_an
1790 * @hw: pointer to the hw struct
1791 * @enable_link: if true: enable link, if false: disable link
1792 * @cmd_details: pointer to command details structure or NULL
1793 *
1794 * Sets up the link and restarts the Auto-Negotiation over the link.
1795 **/
1796i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1797 bool enable_link,
1798 struct i40e_asq_cmd_details *cmd_details)
1799{
1800 struct i40e_aq_desc desc;
1801 struct i40e_aqc_set_link_restart_an *cmd =
1802 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1803 i40e_status status;
1804
1805 i40e_fill_default_direct_cmd_desc(&desc,
1806 i40e_aqc_opc_set_link_restart_an);
1807
1808 cmd->command = I40E_AQ_PHY_RESTART_AN;
1809 if (enable_link)
1810 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1811 else
1812 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1813
1814 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1815
1816 return status;
1817}
1818
1819/**
1820 * i40e_aq_get_link_info
1821 * @hw: pointer to the hw struct
1822 * @enable_lse: enable/disable LinkStatusEvent reporting
1823 * @link: pointer to link status structure - optional
1824 * @cmd_details: pointer to command details structure or NULL
1825 *
1826 * Returns the link status of the adapter.
1827 **/
1828i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1829 bool enable_lse, struct i40e_link_status *link,
1830 struct i40e_asq_cmd_details *cmd_details)
1831{
1832 struct i40e_aq_desc desc;
1833 struct i40e_aqc_get_link_status *resp =
1834 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1835 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1836 i40e_status status;
1837 bool tx_pause, rx_pause;
1838 u16 command_flags;
1839
1840 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1841
1842 if (enable_lse)
1843 command_flags = I40E_AQ_LSE_ENABLE;
1844 else
1845 command_flags = I40E_AQ_LSE_DISABLE;
1846 resp->command_flags = cpu_to_le16(command_flags);
1847
1848 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1849
1850 if (status)
1851 goto aq_get_link_info_exit;
1852
1853 /* save off old link status information */
1854 hw->phy.link_info_old = *hw_link_info;
1855
1856 /* update link status */
1857 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1858 hw->phy.media_type = i40e_get_media_type(hw);
1859 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1860 hw_link_info->link_info = resp->link_info;
1861 hw_link_info->an_info = resp->an_info;
1862 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1863 I40E_AQ_CONFIG_FEC_RS_ENA);
1864 hw_link_info->ext_info = resp->ext_info;
1865 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1866 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1867 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1868
1869 /* update fc info */
1870 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1871 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1872 if (tx_pause & rx_pause)
1873 hw->fc.current_mode = I40E_FC_FULL;
1874 else if (tx_pause)
1875 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1876 else if (rx_pause)
1877 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1878 else
1879 hw->fc.current_mode = I40E_FC_NONE;
1880
1881 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1882 hw_link_info->crc_enable = true;
1883 else
1884 hw_link_info->crc_enable = false;
1885
1886 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED))
1887 hw_link_info->lse_enable = true;
1888 else
1889 hw_link_info->lse_enable = false;
1890
1891 if ((hw->mac.type == I40E_MAC_XL710) &&
1892 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1893 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1894 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1895
1896 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE &&
1897 hw->mac.type != I40E_MAC_X722) {
1898 __le32 tmp;
1899
1900 memcpy(&tmp, resp->link_type, sizeof(tmp));
1901 hw->phy.phy_types = le32_to_cpu(tmp);
1902 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
1903 }
1904
1905 /* save link status information */
1906 if (link)
1907 *link = *hw_link_info;
1908
1909 /* flag cleared so helper functions don't call AQ again */
1910 hw->phy.get_link_info = false;
1911
1912aq_get_link_info_exit:
1913 return status;
1914}
1915
1916/**
1917 * i40e_aq_set_phy_int_mask
1918 * @hw: pointer to the hw struct
1919 * @mask: interrupt mask to be set
1920 * @cmd_details: pointer to command details structure or NULL
1921 *
1922 * Set link interrupt mask.
1923 **/
1924i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1925 u16 mask,
1926 struct i40e_asq_cmd_details *cmd_details)
1927{
1928 struct i40e_aq_desc desc;
1929 struct i40e_aqc_set_phy_int_mask *cmd =
1930 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1931 i40e_status status;
1932
1933 i40e_fill_default_direct_cmd_desc(&desc,
1934 i40e_aqc_opc_set_phy_int_mask);
1935
1936 cmd->event_mask = cpu_to_le16(mask);
1937
1938 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1939
1940 return status;
1941}
1942
1943/**
1944 * i40e_aq_set_phy_debug
1945 * @hw: pointer to the hw struct
1946 * @cmd_flags: debug command flags
1947 * @cmd_details: pointer to command details structure or NULL
1948 *
1949 * Reset the external PHY.
1950 **/
1951i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1952 struct i40e_asq_cmd_details *cmd_details)
1953{
1954 struct i40e_aq_desc desc;
1955 struct i40e_aqc_set_phy_debug *cmd =
1956 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1957 i40e_status status;
1958
1959 i40e_fill_default_direct_cmd_desc(&desc,
1960 i40e_aqc_opc_set_phy_debug);
1961
1962 cmd->command_flags = cmd_flags;
1963
1964 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1965
1966 return status;
1967}
1968
1969/**
1970 * i40e_is_aq_api_ver_ge
1971 * @aq: pointer to AdminQ info containing HW API version to compare
1972 * @maj: API major value
1973 * @min: API minor value
1974 *
1975 * Assert whether current HW API version is greater/equal than provided.
1976 **/
1977static bool i40e_is_aq_api_ver_ge(struct i40e_adminq_info *aq, u16 maj,
1978 u16 min)
1979{
1980 return (aq->api_maj_ver > maj ||
1981 (aq->api_maj_ver == maj && aq->api_min_ver >= min));
1982}
1983
1984/**
1985 * i40e_aq_add_vsi
1986 * @hw: pointer to the hw struct
1987 * @vsi_ctx: pointer to a vsi context struct
1988 * @cmd_details: pointer to command details structure or NULL
1989 *
1990 * Add a VSI context to the hardware.
1991**/
1992i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1993 struct i40e_vsi_context *vsi_ctx,
1994 struct i40e_asq_cmd_details *cmd_details)
1995{
1996 struct i40e_aq_desc desc;
1997 struct i40e_aqc_add_get_update_vsi *cmd =
1998 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1999 struct i40e_aqc_add_get_update_vsi_completion *resp =
2000 (struct i40e_aqc_add_get_update_vsi_completion *)
2001 &desc.params.raw;
2002 i40e_status status;
2003
2004 i40e_fill_default_direct_cmd_desc(&desc,
2005 i40e_aqc_opc_add_vsi);
2006
2007 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
2008 cmd->connection_type = vsi_ctx->connection_type;
2009 cmd->vf_id = vsi_ctx->vf_num;
2010 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
2011
2012 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2013
2014 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2015 sizeof(vsi_ctx->info), cmd_details);
2016
2017 if (status)
2018 goto aq_add_vsi_exit;
2019
2020 vsi_ctx->seid = le16_to_cpu(resp->seid);
2021 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2022 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2023 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2024
2025aq_add_vsi_exit:
2026 return status;
2027}
2028
2029/**
2030 * i40e_aq_set_default_vsi
2031 * @hw: pointer to the hw struct
2032 * @seid: vsi number
2033 * @cmd_details: pointer to command details structure or NULL
2034 **/
2035i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw,
2036 u16 seid,
2037 struct i40e_asq_cmd_details *cmd_details)
2038{
2039 struct i40e_aq_desc desc;
2040 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2041 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2042 &desc.params.raw;
2043 i40e_status status;
2044
2045 i40e_fill_default_direct_cmd_desc(&desc,
2046 i40e_aqc_opc_set_vsi_promiscuous_modes);
2047
2048 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2049 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2050 cmd->seid = cpu_to_le16(seid);
2051
2052 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2053
2054 return status;
2055}
2056
2057/**
2058 * i40e_aq_clear_default_vsi
2059 * @hw: pointer to the hw struct
2060 * @seid: vsi number
2061 * @cmd_details: pointer to command details structure or NULL
2062 **/
2063i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2064 u16 seid,
2065 struct i40e_asq_cmd_details *cmd_details)
2066{
2067 struct i40e_aq_desc desc;
2068 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2069 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2070 &desc.params.raw;
2071 i40e_status status;
2072
2073 i40e_fill_default_direct_cmd_desc(&desc,
2074 i40e_aqc_opc_set_vsi_promiscuous_modes);
2075
2076 cmd->promiscuous_flags = cpu_to_le16(0);
2077 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2078 cmd->seid = cpu_to_le16(seid);
2079
2080 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2081
2082 return status;
2083}
2084
2085/**
2086 * i40e_aq_set_vsi_unicast_promiscuous
2087 * @hw: pointer to the hw struct
2088 * @seid: vsi number
2089 * @set: set unicast promiscuous enable/disable
2090 * @cmd_details: pointer to command details structure or NULL
2091 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2092 **/
2093i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2094 u16 seid, bool set,
2095 struct i40e_asq_cmd_details *cmd_details,
2096 bool rx_only_promisc)
2097{
2098 struct i40e_aq_desc desc;
2099 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2100 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2101 i40e_status status;
2102 u16 flags = 0;
2103
2104 i40e_fill_default_direct_cmd_desc(&desc,
2105 i40e_aqc_opc_set_vsi_promiscuous_modes);
2106
2107 if (set) {
2108 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2109 if (rx_only_promisc && i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2110 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
2111 }
2112
2113 cmd->promiscuous_flags = cpu_to_le16(flags);
2114
2115 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2116 if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2117 cmd->valid_flags |=
2118 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
2119
2120 cmd->seid = cpu_to_le16(seid);
2121 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2122
2123 return status;
2124}
2125
2126/**
2127 * i40e_aq_set_vsi_multicast_promiscuous
2128 * @hw: pointer to the hw struct
2129 * @seid: vsi number
2130 * @set: set multicast promiscuous enable/disable
2131 * @cmd_details: pointer to command details structure or NULL
2132 **/
2133i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2134 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2135{
2136 struct i40e_aq_desc desc;
2137 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2138 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2139 i40e_status status;
2140 u16 flags = 0;
2141
2142 i40e_fill_default_direct_cmd_desc(&desc,
2143 i40e_aqc_opc_set_vsi_promiscuous_modes);
2144
2145 if (set)
2146 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2147
2148 cmd->promiscuous_flags = cpu_to_le16(flags);
2149
2150 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2151
2152 cmd->seid = cpu_to_le16(seid);
2153 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2154
2155 return status;
2156}
2157
2158/**
2159 * i40e_aq_set_vsi_mc_promisc_on_vlan
2160 * @hw: pointer to the hw struct
2161 * @seid: vsi number
2162 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2163 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2164 * @cmd_details: pointer to command details structure or NULL
2165 **/
2166enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2167 u16 seid, bool enable,
2168 u16 vid,
2169 struct i40e_asq_cmd_details *cmd_details)
2170{
2171 struct i40e_aq_desc desc;
2172 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2173 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2174 enum i40e_status_code status;
2175 u16 flags = 0;
2176
2177 i40e_fill_default_direct_cmd_desc(&desc,
2178 i40e_aqc_opc_set_vsi_promiscuous_modes);
2179
2180 if (enable)
2181 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2182
2183 cmd->promiscuous_flags = cpu_to_le16(flags);
2184 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2185 cmd->seid = cpu_to_le16(seid);
2186 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2187
2188 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2189
2190 return status;
2191}
2192
2193/**
2194 * i40e_aq_set_vsi_uc_promisc_on_vlan
2195 * @hw: pointer to the hw struct
2196 * @seid: vsi number
2197 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2198 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2199 * @cmd_details: pointer to command details structure or NULL
2200 **/
2201enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2202 u16 seid, bool enable,
2203 u16 vid,
2204 struct i40e_asq_cmd_details *cmd_details)
2205{
2206 struct i40e_aq_desc desc;
2207 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2208 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2209 enum i40e_status_code status;
2210 u16 flags = 0;
2211
2212 i40e_fill_default_direct_cmd_desc(&desc,
2213 i40e_aqc_opc_set_vsi_promiscuous_modes);
2214
2215 if (enable) {
2216 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2217 if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2218 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
2219 }
2220
2221 cmd->promiscuous_flags = cpu_to_le16(flags);
2222 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2223 if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2224 cmd->valid_flags |=
2225 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
2226 cmd->seid = cpu_to_le16(seid);
2227 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2228
2229 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2230
2231 return status;
2232}
2233
2234/**
2235 * i40e_aq_set_vsi_bc_promisc_on_vlan
2236 * @hw: pointer to the hw struct
2237 * @seid: vsi number
2238 * @enable: set broadcast promiscuous enable/disable for a given VLAN
2239 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2240 * @cmd_details: pointer to command details structure or NULL
2241 **/
2242i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2243 u16 seid, bool enable, u16 vid,
2244 struct i40e_asq_cmd_details *cmd_details)
2245{
2246 struct i40e_aq_desc desc;
2247 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2248 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2249 i40e_status status;
2250 u16 flags = 0;
2251
2252 i40e_fill_default_direct_cmd_desc(&desc,
2253 i40e_aqc_opc_set_vsi_promiscuous_modes);
2254
2255 if (enable)
2256 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2257
2258 cmd->promiscuous_flags = cpu_to_le16(flags);
2259 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2260 cmd->seid = cpu_to_le16(seid);
2261 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2262
2263 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2264
2265 return status;
2266}
2267
2268/**
2269 * i40e_aq_set_vsi_broadcast
2270 * @hw: pointer to the hw struct
2271 * @seid: vsi number
2272 * @set_filter: true to set filter, false to clear filter
2273 * @cmd_details: pointer to command details structure or NULL
2274 *
2275 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2276 **/
2277i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2278 u16 seid, bool set_filter,
2279 struct i40e_asq_cmd_details *cmd_details)
2280{
2281 struct i40e_aq_desc desc;
2282 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2283 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2284 i40e_status status;
2285
2286 i40e_fill_default_direct_cmd_desc(&desc,
2287 i40e_aqc_opc_set_vsi_promiscuous_modes);
2288
2289 if (set_filter)
2290 cmd->promiscuous_flags
2291 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2292 else
2293 cmd->promiscuous_flags
2294 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2295
2296 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2297 cmd->seid = cpu_to_le16(seid);
2298 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2299
2300 return status;
2301}
2302
2303/**
2304 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2305 * @hw: pointer to the hw struct
2306 * @seid: vsi number
2307 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2308 * @cmd_details: pointer to command details structure or NULL
2309 **/
2310i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2311 u16 seid, bool enable,
2312 struct i40e_asq_cmd_details *cmd_details)
2313{
2314 struct i40e_aq_desc desc;
2315 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2316 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2317 i40e_status status;
2318 u16 flags = 0;
2319
2320 i40e_fill_default_direct_cmd_desc(&desc,
2321 i40e_aqc_opc_set_vsi_promiscuous_modes);
2322 if (enable)
2323 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2324
2325 cmd->promiscuous_flags = cpu_to_le16(flags);
2326 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2327 cmd->seid = cpu_to_le16(seid);
2328
2329 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2330
2331 return status;
2332}
2333
2334/**
2335 * i40e_get_vsi_params - get VSI configuration info
2336 * @hw: pointer to the hw struct
2337 * @vsi_ctx: pointer to a vsi context struct
2338 * @cmd_details: pointer to command details structure or NULL
2339 **/
2340i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2341 struct i40e_vsi_context *vsi_ctx,
2342 struct i40e_asq_cmd_details *cmd_details)
2343{
2344 struct i40e_aq_desc desc;
2345 struct i40e_aqc_add_get_update_vsi *cmd =
2346 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2347 struct i40e_aqc_add_get_update_vsi_completion *resp =
2348 (struct i40e_aqc_add_get_update_vsi_completion *)
2349 &desc.params.raw;
2350 i40e_status status;
2351
2352 i40e_fill_default_direct_cmd_desc(&desc,
2353 i40e_aqc_opc_get_vsi_parameters);
2354
2355 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2356
2357 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2358
2359 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2360 sizeof(vsi_ctx->info), NULL);
2361
2362 if (status)
2363 goto aq_get_vsi_params_exit;
2364
2365 vsi_ctx->seid = le16_to_cpu(resp->seid);
2366 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2367 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2368 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2369
2370aq_get_vsi_params_exit:
2371 return status;
2372}
2373
2374/**
2375 * i40e_aq_update_vsi_params
2376 * @hw: pointer to the hw struct
2377 * @vsi_ctx: pointer to a vsi context struct
2378 * @cmd_details: pointer to command details structure or NULL
2379 *
2380 * Update a VSI context.
2381 **/
2382i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2383 struct i40e_vsi_context *vsi_ctx,
2384 struct i40e_asq_cmd_details *cmd_details)
2385{
2386 struct i40e_aq_desc desc;
2387 struct i40e_aqc_add_get_update_vsi *cmd =
2388 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2389 struct i40e_aqc_add_get_update_vsi_completion *resp =
2390 (struct i40e_aqc_add_get_update_vsi_completion *)
2391 &desc.params.raw;
2392 i40e_status status;
2393
2394 i40e_fill_default_direct_cmd_desc(&desc,
2395 i40e_aqc_opc_update_vsi_parameters);
2396 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2397
2398 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2399
2400 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2401 sizeof(vsi_ctx->info), cmd_details);
2402
2403 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2404 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2405
2406 return status;
2407}
2408
2409/**
2410 * i40e_aq_get_switch_config
2411 * @hw: pointer to the hardware structure
2412 * @buf: pointer to the result buffer
2413 * @buf_size: length of input buffer
2414 * @start_seid: seid to start for the report, 0 == beginning
2415 * @cmd_details: pointer to command details structure or NULL
2416 *
2417 * Fill the buf with switch configuration returned from AdminQ command
2418 **/
2419i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2420 struct i40e_aqc_get_switch_config_resp *buf,
2421 u16 buf_size, u16 *start_seid,
2422 struct i40e_asq_cmd_details *cmd_details)
2423{
2424 struct i40e_aq_desc desc;
2425 struct i40e_aqc_switch_seid *scfg =
2426 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2427 i40e_status status;
2428
2429 i40e_fill_default_direct_cmd_desc(&desc,
2430 i40e_aqc_opc_get_switch_config);
2431 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2432 if (buf_size > I40E_AQ_LARGE_BUF)
2433 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2434 scfg->seid = cpu_to_le16(*start_seid);
2435
2436 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2437 *start_seid = le16_to_cpu(scfg->seid);
2438
2439 return status;
2440}
2441
2442/**
2443 * i40e_aq_set_switch_config
2444 * @hw: pointer to the hardware structure
2445 * @flags: bit flag values to set
2446 * @mode: cloud filter mode
2447 * @valid_flags: which bit flags to set
2448 * @mode: cloud filter mode
2449 * @cmd_details: pointer to command details structure or NULL
2450 *
2451 * Set switch configuration bits
2452 **/
2453enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2454 u16 flags,
2455 u16 valid_flags, u8 mode,
2456 struct i40e_asq_cmd_details *cmd_details)
2457{
2458 struct i40e_aq_desc desc;
2459 struct i40e_aqc_set_switch_config *scfg =
2460 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2461 enum i40e_status_code status;
2462
2463 i40e_fill_default_direct_cmd_desc(&desc,
2464 i40e_aqc_opc_set_switch_config);
2465 scfg->flags = cpu_to_le16(flags);
2466 scfg->valid_flags = cpu_to_le16(valid_flags);
2467 scfg->mode = mode;
2468 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2469 scfg->switch_tag = cpu_to_le16(hw->switch_tag);
2470 scfg->first_tag = cpu_to_le16(hw->first_tag);
2471 scfg->second_tag = cpu_to_le16(hw->second_tag);
2472 }
2473 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2474
2475 return status;
2476}
2477
2478/**
2479 * i40e_aq_get_firmware_version
2480 * @hw: pointer to the hw struct
2481 * @fw_major_version: firmware major version
2482 * @fw_minor_version: firmware minor version
2483 * @fw_build: firmware build number
2484 * @api_major_version: major queue version
2485 * @api_minor_version: minor queue version
2486 * @cmd_details: pointer to command details structure or NULL
2487 *
2488 * Get the firmware version from the admin queue commands
2489 **/
2490i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2491 u16 *fw_major_version, u16 *fw_minor_version,
2492 u32 *fw_build,
2493 u16 *api_major_version, u16 *api_minor_version,
2494 struct i40e_asq_cmd_details *cmd_details)
2495{
2496 struct i40e_aq_desc desc;
2497 struct i40e_aqc_get_version *resp =
2498 (struct i40e_aqc_get_version *)&desc.params.raw;
2499 i40e_status status;
2500
2501 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2502
2503 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2504
2505 if (!status) {
2506 if (fw_major_version)
2507 *fw_major_version = le16_to_cpu(resp->fw_major);
2508 if (fw_minor_version)
2509 *fw_minor_version = le16_to_cpu(resp->fw_minor);
2510 if (fw_build)
2511 *fw_build = le32_to_cpu(resp->fw_build);
2512 if (api_major_version)
2513 *api_major_version = le16_to_cpu(resp->api_major);
2514 if (api_minor_version)
2515 *api_minor_version = le16_to_cpu(resp->api_minor);
2516 }
2517
2518 return status;
2519}
2520
2521/**
2522 * i40e_aq_send_driver_version
2523 * @hw: pointer to the hw struct
2524 * @dv: driver's major, minor version
2525 * @cmd_details: pointer to command details structure or NULL
2526 *
2527 * Send the driver version to the firmware
2528 **/
2529i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2530 struct i40e_driver_version *dv,
2531 struct i40e_asq_cmd_details *cmd_details)
2532{
2533 struct i40e_aq_desc desc;
2534 struct i40e_aqc_driver_version *cmd =
2535 (struct i40e_aqc_driver_version *)&desc.params.raw;
2536 i40e_status status;
2537 u16 len;
2538
2539 if (dv == NULL)
2540 return I40E_ERR_PARAM;
2541
2542 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2543
2544 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2545 cmd->driver_major_ver = dv->major_version;
2546 cmd->driver_minor_ver = dv->minor_version;
2547 cmd->driver_build_ver = dv->build_version;
2548 cmd->driver_subbuild_ver = dv->subbuild_version;
2549
2550 len = 0;
2551 while (len < sizeof(dv->driver_string) &&
2552 (dv->driver_string[len] < 0x80) &&
2553 dv->driver_string[len])
2554 len++;
2555 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2556 len, cmd_details);
2557
2558 return status;
2559}
2560
2561/**
2562 * i40e_get_link_status - get status of the HW network link
2563 * @hw: pointer to the hw struct
2564 * @link_up: pointer to bool (true/false = linkup/linkdown)
2565 *
2566 * Variable link_up true if link is up, false if link is down.
2567 * The variable link_up is invalid if returned value of status != 0
2568 *
2569 * Side effect: LinkStatusEvent reporting becomes enabled
2570 **/
2571i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2572{
2573 i40e_status status = 0;
2574
2575 if (hw->phy.get_link_info) {
2576 status = i40e_update_link_info(hw);
2577
2578 if (status)
2579 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2580 status);
2581 }
2582
2583 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2584
2585 return status;
2586}
2587
2588/**
2589 * i40e_updatelink_status - update status of the HW network link
2590 * @hw: pointer to the hw struct
2591 **/
2592noinline_for_stack i40e_status i40e_update_link_info(struct i40e_hw *hw)
2593{
2594 struct i40e_aq_get_phy_abilities_resp abilities;
2595 i40e_status status = 0;
2596
2597 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2598 if (status)
2599 return status;
2600
2601 /* extra checking needed to ensure link info to user is timely */
2602 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2603 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2604 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2605 status = i40e_aq_get_phy_capabilities(hw, false, false,
2606 &abilities, NULL);
2607 if (status)
2608 return status;
2609
2610 if (abilities.fec_cfg_curr_mod_ext_info &
2611 I40E_AQ_ENABLE_FEC_AUTO)
2612 hw->phy.link_info.req_fec_info =
2613 (I40E_AQ_REQUEST_FEC_KR |
2614 I40E_AQ_REQUEST_FEC_RS);
2615 else
2616 hw->phy.link_info.req_fec_info =
2617 abilities.fec_cfg_curr_mod_ext_info &
2618 (I40E_AQ_REQUEST_FEC_KR |
2619 I40E_AQ_REQUEST_FEC_RS);
2620
2621 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2622 sizeof(hw->phy.link_info.module_type));
2623 }
2624
2625 return status;
2626}
2627
2628/**
2629 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2630 * @hw: pointer to the hw struct
2631 * @uplink_seid: the MAC or other gizmo SEID
2632 * @downlink_seid: the VSI SEID
2633 * @enabled_tc: bitmap of TCs to be enabled
2634 * @default_port: true for default port VSI, false for control port
2635 * @veb_seid: pointer to where to put the resulting VEB SEID
2636 * @enable_stats: true to turn on VEB stats
2637 * @cmd_details: pointer to command details structure or NULL
2638 *
2639 * This asks the FW to add a VEB between the uplink and downlink
2640 * elements. If the uplink SEID is 0, this will be a floating VEB.
2641 **/
2642i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2643 u16 downlink_seid, u8 enabled_tc,
2644 bool default_port, u16 *veb_seid,
2645 bool enable_stats,
2646 struct i40e_asq_cmd_details *cmd_details)
2647{
2648 struct i40e_aq_desc desc;
2649 struct i40e_aqc_add_veb *cmd =
2650 (struct i40e_aqc_add_veb *)&desc.params.raw;
2651 struct i40e_aqc_add_veb_completion *resp =
2652 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2653 i40e_status status;
2654 u16 veb_flags = 0;
2655
2656 /* SEIDs need to either both be set or both be 0 for floating VEB */
2657 if (!!uplink_seid != !!downlink_seid)
2658 return I40E_ERR_PARAM;
2659
2660 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2661
2662 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2663 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2664 cmd->enable_tcs = enabled_tc;
2665 if (!uplink_seid)
2666 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2667 if (default_port)
2668 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2669 else
2670 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2671
2672 /* reverse logic here: set the bitflag to disable the stats */
2673 if (!enable_stats)
2674 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2675
2676 cmd->veb_flags = cpu_to_le16(veb_flags);
2677
2678 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2679
2680 if (!status && veb_seid)
2681 *veb_seid = le16_to_cpu(resp->veb_seid);
2682
2683 return status;
2684}
2685
2686/**
2687 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2688 * @hw: pointer to the hw struct
2689 * @veb_seid: the SEID of the VEB to query
2690 * @switch_id: the uplink switch id
2691 * @floating: set to true if the VEB is floating
2692 * @statistic_index: index of the stats counter block for this VEB
2693 * @vebs_used: number of VEB's used by function
2694 * @vebs_free: total VEB's not reserved by any function
2695 * @cmd_details: pointer to command details structure or NULL
2696 *
2697 * This retrieves the parameters for a particular VEB, specified by
2698 * uplink_seid, and returns them to the caller.
2699 **/
2700i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2701 u16 veb_seid, u16 *switch_id,
2702 bool *floating, u16 *statistic_index,
2703 u16 *vebs_used, u16 *vebs_free,
2704 struct i40e_asq_cmd_details *cmd_details)
2705{
2706 struct i40e_aq_desc desc;
2707 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2708 (struct i40e_aqc_get_veb_parameters_completion *)
2709 &desc.params.raw;
2710 i40e_status status;
2711
2712 if (veb_seid == 0)
2713 return I40E_ERR_PARAM;
2714
2715 i40e_fill_default_direct_cmd_desc(&desc,
2716 i40e_aqc_opc_get_veb_parameters);
2717 cmd_resp->seid = cpu_to_le16(veb_seid);
2718
2719 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2720 if (status)
2721 goto get_veb_exit;
2722
2723 if (switch_id)
2724 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2725 if (statistic_index)
2726 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2727 if (vebs_used)
2728 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2729 if (vebs_free)
2730 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2731 if (floating) {
2732 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2733
2734 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2735 *floating = true;
2736 else
2737 *floating = false;
2738 }
2739
2740get_veb_exit:
2741 return status;
2742}
2743
2744/**
2745 * i40e_aq_add_macvlan
2746 * @hw: pointer to the hw struct
2747 * @seid: VSI for the mac address
2748 * @mv_list: list of macvlans to be added
2749 * @count: length of the list
2750 * @cmd_details: pointer to command details structure or NULL
2751 *
2752 * Add MAC/VLAN addresses to the HW filtering
2753 **/
2754i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2755 struct i40e_aqc_add_macvlan_element_data *mv_list,
2756 u16 count, struct i40e_asq_cmd_details *cmd_details)
2757{
2758 struct i40e_aq_desc desc;
2759 struct i40e_aqc_macvlan *cmd =
2760 (struct i40e_aqc_macvlan *)&desc.params.raw;
2761 i40e_status status;
2762 u16 buf_size;
2763 int i;
2764
2765 if (count == 0 || !mv_list || !hw)
2766 return I40E_ERR_PARAM;
2767
2768 buf_size = count * sizeof(*mv_list);
2769
2770 /* prep the rest of the request */
2771 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2772 cmd->num_addresses = cpu_to_le16(count);
2773 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2774 cmd->seid[1] = 0;
2775 cmd->seid[2] = 0;
2776
2777 for (i = 0; i < count; i++)
2778 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2779 mv_list[i].flags |=
2780 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2781
2782 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2783 if (buf_size > I40E_AQ_LARGE_BUF)
2784 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2785
2786 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2787 cmd_details);
2788
2789 return status;
2790}
2791
2792/**
2793 * i40e_aq_remove_macvlan
2794 * @hw: pointer to the hw struct
2795 * @seid: VSI for the mac address
2796 * @mv_list: list of macvlans to be removed
2797 * @count: length of the list
2798 * @cmd_details: pointer to command details structure or NULL
2799 *
2800 * Remove MAC/VLAN addresses from the HW filtering
2801 **/
2802i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2803 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2804 u16 count, struct i40e_asq_cmd_details *cmd_details)
2805{
2806 struct i40e_aq_desc desc;
2807 struct i40e_aqc_macvlan *cmd =
2808 (struct i40e_aqc_macvlan *)&desc.params.raw;
2809 i40e_status status;
2810 u16 buf_size;
2811
2812 if (count == 0 || !mv_list || !hw)
2813 return I40E_ERR_PARAM;
2814
2815 buf_size = count * sizeof(*mv_list);
2816
2817 /* prep the rest of the request */
2818 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2819 cmd->num_addresses = cpu_to_le16(count);
2820 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2821 cmd->seid[1] = 0;
2822 cmd->seid[2] = 0;
2823
2824 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2825 if (buf_size > I40E_AQ_LARGE_BUF)
2826 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2827
2828 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2829 cmd_details);
2830
2831 return status;
2832}
2833
2834/**
2835 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2836 * @hw: pointer to the hw struct
2837 * @opcode: AQ opcode for add or delete mirror rule
2838 * @sw_seid: Switch SEID (to which rule refers)
2839 * @rule_type: Rule Type (ingress/egress/VLAN)
2840 * @id: Destination VSI SEID or Rule ID
2841 * @count: length of the list
2842 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2843 * @cmd_details: pointer to command details structure or NULL
2844 * @rule_id: Rule ID returned from FW
2845 * @rules_used: Number of rules used in internal switch
2846 * @rules_free: Number of rules free in internal switch
2847 *
2848 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2849 * VEBs/VEPA elements only
2850 **/
2851static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw,
2852 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2853 u16 count, __le16 *mr_list,
2854 struct i40e_asq_cmd_details *cmd_details,
2855 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2856{
2857 struct i40e_aq_desc desc;
2858 struct i40e_aqc_add_delete_mirror_rule *cmd =
2859 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2860 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2861 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2862 i40e_status status;
2863 u16 buf_size;
2864
2865 buf_size = count * sizeof(*mr_list);
2866
2867 /* prep the rest of the request */
2868 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2869 cmd->seid = cpu_to_le16(sw_seid);
2870 cmd->rule_type = cpu_to_le16(rule_type &
2871 I40E_AQC_MIRROR_RULE_TYPE_MASK);
2872 cmd->num_entries = cpu_to_le16(count);
2873 /* Dest VSI for add, rule_id for delete */
2874 cmd->destination = cpu_to_le16(id);
2875 if (mr_list) {
2876 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2877 I40E_AQ_FLAG_RD));
2878 if (buf_size > I40E_AQ_LARGE_BUF)
2879 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2880 }
2881
2882 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2883 cmd_details);
2884 if (!status ||
2885 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2886 if (rule_id)
2887 *rule_id = le16_to_cpu(resp->rule_id);
2888 if (rules_used)
2889 *rules_used = le16_to_cpu(resp->mirror_rules_used);
2890 if (rules_free)
2891 *rules_free = le16_to_cpu(resp->mirror_rules_free);
2892 }
2893 return status;
2894}
2895
2896/**
2897 * i40e_aq_add_mirrorrule - add a mirror rule
2898 * @hw: pointer to the hw struct
2899 * @sw_seid: Switch SEID (to which rule refers)
2900 * @rule_type: Rule Type (ingress/egress/VLAN)
2901 * @dest_vsi: SEID of VSI to which packets will be mirrored
2902 * @count: length of the list
2903 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2904 * @cmd_details: pointer to command details structure or NULL
2905 * @rule_id: Rule ID returned from FW
2906 * @rules_used: Number of rules used in internal switch
2907 * @rules_free: Number of rules free in internal switch
2908 *
2909 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2910 **/
2911i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2912 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2913 struct i40e_asq_cmd_details *cmd_details,
2914 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2915{
2916 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2917 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2918 if (count == 0 || !mr_list)
2919 return I40E_ERR_PARAM;
2920 }
2921
2922 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2923 rule_type, dest_vsi, count, mr_list,
2924 cmd_details, rule_id, rules_used, rules_free);
2925}
2926
2927/**
2928 * i40e_aq_delete_mirrorrule - delete a mirror rule
2929 * @hw: pointer to the hw struct
2930 * @sw_seid: Switch SEID (to which rule refers)
2931 * @rule_type: Rule Type (ingress/egress/VLAN)
2932 * @count: length of the list
2933 * @rule_id: Rule ID that is returned in the receive desc as part of
2934 * add_mirrorrule.
2935 * @mr_list: list of mirrored VLAN IDs to be removed
2936 * @cmd_details: pointer to command details structure or NULL
2937 * @rules_used: Number of rules used in internal switch
2938 * @rules_free: Number of rules free in internal switch
2939 *
2940 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2941 **/
2942i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2943 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2944 struct i40e_asq_cmd_details *cmd_details,
2945 u16 *rules_used, u16 *rules_free)
2946{
2947 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
2948 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2949 /* count and mr_list shall be valid for rule_type INGRESS VLAN
2950 * mirroring. For other rule_type, count and rule_type should
2951 * not matter.
2952 */
2953 if (count == 0 || !mr_list)
2954 return I40E_ERR_PARAM;
2955 }
2956
2957 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2958 rule_type, rule_id, count, mr_list,
2959 cmd_details, NULL, rules_used, rules_free);
2960}
2961
2962/**
2963 * i40e_aq_send_msg_to_vf
2964 * @hw: pointer to the hardware structure
2965 * @vfid: VF id to send msg
2966 * @v_opcode: opcodes for VF-PF communication
2967 * @v_retval: return error code
2968 * @msg: pointer to the msg buffer
2969 * @msglen: msg length
2970 * @cmd_details: pointer to command details
2971 *
2972 * send msg to vf
2973 **/
2974i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2975 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2976 struct i40e_asq_cmd_details *cmd_details)
2977{
2978 struct i40e_aq_desc desc;
2979 struct i40e_aqc_pf_vf_message *cmd =
2980 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2981 i40e_status status;
2982
2983 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2984 cmd->id = cpu_to_le32(vfid);
2985 desc.cookie_high = cpu_to_le32(v_opcode);
2986 desc.cookie_low = cpu_to_le32(v_retval);
2987 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2988 if (msglen) {
2989 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2990 I40E_AQ_FLAG_RD));
2991 if (msglen > I40E_AQ_LARGE_BUF)
2992 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2993 desc.datalen = cpu_to_le16(msglen);
2994 }
2995 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2996
2997 return status;
2998}
2999
3000/**
3001 * i40e_aq_debug_read_register
3002 * @hw: pointer to the hw struct
3003 * @reg_addr: register address
3004 * @reg_val: register value
3005 * @cmd_details: pointer to command details structure or NULL
3006 *
3007 * Read the register using the admin queue commands
3008 **/
3009i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
3010 u32 reg_addr, u64 *reg_val,
3011 struct i40e_asq_cmd_details *cmd_details)
3012{
3013 struct i40e_aq_desc desc;
3014 struct i40e_aqc_debug_reg_read_write *cmd_resp =
3015 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3016 i40e_status status;
3017
3018 if (reg_val == NULL)
3019 return I40E_ERR_PARAM;
3020
3021 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3022
3023 cmd_resp->address = cpu_to_le32(reg_addr);
3024
3025 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3026
3027 if (!status) {
3028 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
3029 (u64)le32_to_cpu(cmd_resp->value_low);
3030 }
3031
3032 return status;
3033}
3034
3035/**
3036 * i40e_aq_debug_write_register
3037 * @hw: pointer to the hw struct
3038 * @reg_addr: register address
3039 * @reg_val: register value
3040 * @cmd_details: pointer to command details structure or NULL
3041 *
3042 * Write to a register using the admin queue commands
3043 **/
3044i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
3045 u32 reg_addr, u64 reg_val,
3046 struct i40e_asq_cmd_details *cmd_details)
3047{
3048 struct i40e_aq_desc desc;
3049 struct i40e_aqc_debug_reg_read_write *cmd =
3050 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3051 i40e_status status;
3052
3053 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3054
3055 cmd->address = cpu_to_le32(reg_addr);
3056 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
3057 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
3058
3059 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3060
3061 return status;
3062}
3063
3064/**
3065 * i40e_aq_request_resource
3066 * @hw: pointer to the hw struct
3067 * @resource: resource id
3068 * @access: access type
3069 * @sdp_number: resource number
3070 * @timeout: the maximum time in ms that the driver may hold the resource
3071 * @cmd_details: pointer to command details structure or NULL
3072 *
3073 * requests common resource using the admin queue commands
3074 **/
3075i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
3076 enum i40e_aq_resources_ids resource,
3077 enum i40e_aq_resource_access_type access,
3078 u8 sdp_number, u64 *timeout,
3079 struct i40e_asq_cmd_details *cmd_details)
3080{
3081 struct i40e_aq_desc desc;
3082 struct i40e_aqc_request_resource *cmd_resp =
3083 (struct i40e_aqc_request_resource *)&desc.params.raw;
3084 i40e_status status;
3085
3086 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3087
3088 cmd_resp->resource_id = cpu_to_le16(resource);
3089 cmd_resp->access_type = cpu_to_le16(access);
3090 cmd_resp->resource_number = cpu_to_le32(sdp_number);
3091
3092 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3093 /* The completion specifies the maximum time in ms that the driver
3094 * may hold the resource in the Timeout field.
3095 * If the resource is held by someone else, the command completes with
3096 * busy return value and the timeout field indicates the maximum time
3097 * the current owner of the resource has to free it.
3098 */
3099 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3100 *timeout = le32_to_cpu(cmd_resp->timeout);
3101
3102 return status;
3103}
3104
3105/**
3106 * i40e_aq_release_resource
3107 * @hw: pointer to the hw struct
3108 * @resource: resource id
3109 * @sdp_number: resource number
3110 * @cmd_details: pointer to command details structure or NULL
3111 *
3112 * release common resource using the admin queue commands
3113 **/
3114i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
3115 enum i40e_aq_resources_ids resource,
3116 u8 sdp_number,
3117 struct i40e_asq_cmd_details *cmd_details)
3118{
3119 struct i40e_aq_desc desc;
3120 struct i40e_aqc_request_resource *cmd =
3121 (struct i40e_aqc_request_resource *)&desc.params.raw;
3122 i40e_status status;
3123
3124 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3125
3126 cmd->resource_id = cpu_to_le16(resource);
3127 cmd->resource_number = cpu_to_le32(sdp_number);
3128
3129 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3130
3131 return status;
3132}
3133
3134/**
3135 * i40e_aq_read_nvm
3136 * @hw: pointer to the hw struct
3137 * @module_pointer: module pointer location in words from the NVM beginning
3138 * @offset: byte offset from the module beginning
3139 * @length: length of the section to be read (in bytes from the offset)
3140 * @data: command buffer (size [bytes] = length)
3141 * @last_command: tells if this is the last command in a series
3142 * @cmd_details: pointer to command details structure or NULL
3143 *
3144 * Read the NVM using the admin queue commands
3145 **/
3146i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3147 u32 offset, u16 length, void *data,
3148 bool last_command,
3149 struct i40e_asq_cmd_details *cmd_details)
3150{
3151 struct i40e_aq_desc desc;
3152 struct i40e_aqc_nvm_update *cmd =
3153 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3154 i40e_status status;
3155
3156 /* In offset the highest byte must be zeroed. */
3157 if (offset & 0xFF000000) {
3158 status = I40E_ERR_PARAM;
3159 goto i40e_aq_read_nvm_exit;
3160 }
3161
3162 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3163
3164 /* If this is the last command in a series, set the proper flag. */
3165 if (last_command)
3166 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3167 cmd->module_pointer = module_pointer;
3168 cmd->offset = cpu_to_le32(offset);
3169 cmd->length = cpu_to_le16(length);
3170
3171 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3172 if (length > I40E_AQ_LARGE_BUF)
3173 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3174
3175 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3176
3177i40e_aq_read_nvm_exit:
3178 return status;
3179}
3180
3181/**
3182 * i40e_aq_erase_nvm
3183 * @hw: pointer to the hw struct
3184 * @module_pointer: module pointer location in words from the NVM beginning
3185 * @offset: offset in the module (expressed in 4 KB from module's beginning)
3186 * @length: length of the section to be erased (expressed in 4 KB)
3187 * @last_command: tells if this is the last command in a series
3188 * @cmd_details: pointer to command details structure or NULL
3189 *
3190 * Erase the NVM sector using the admin queue commands
3191 **/
3192i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3193 u32 offset, u16 length, bool last_command,
3194 struct i40e_asq_cmd_details *cmd_details)
3195{
3196 struct i40e_aq_desc desc;
3197 struct i40e_aqc_nvm_update *cmd =
3198 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3199 i40e_status status;
3200
3201 /* In offset the highest byte must be zeroed. */
3202 if (offset & 0xFF000000) {
3203 status = I40E_ERR_PARAM;
3204 goto i40e_aq_erase_nvm_exit;
3205 }
3206
3207 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3208
3209 /* If this is the last command in a series, set the proper flag. */
3210 if (last_command)
3211 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3212 cmd->module_pointer = module_pointer;
3213 cmd->offset = cpu_to_le32(offset);
3214 cmd->length = cpu_to_le16(length);
3215
3216 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3217
3218i40e_aq_erase_nvm_exit:
3219 return status;
3220}
3221
3222/**
3223 * i40e_parse_discover_capabilities
3224 * @hw: pointer to the hw struct
3225 * @buff: pointer to a buffer containing device/function capability records
3226 * @cap_count: number of capability records in the list
3227 * @list_type_opc: type of capabilities list to parse
3228 *
3229 * Parse the device/function capabilities list.
3230 **/
3231static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3232 u32 cap_count,
3233 enum i40e_admin_queue_opc list_type_opc)
3234{
3235 struct i40e_aqc_list_capabilities_element_resp *cap;
3236 u32 valid_functions, num_functions;
3237 u32 number, logical_id, phys_id;
3238 struct i40e_hw_capabilities *p;
3239 u16 id, ocp_cfg_word0;
3240 i40e_status status;
3241 u8 major_rev;
3242 u32 i = 0;
3243
3244 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3245
3246 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3247 p = &hw->dev_caps;
3248 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3249 p = &hw->func_caps;
3250 else
3251 return;
3252
3253 for (i = 0; i < cap_count; i++, cap++) {
3254 id = le16_to_cpu(cap->id);
3255 number = le32_to_cpu(cap->number);
3256 logical_id = le32_to_cpu(cap->logical_id);
3257 phys_id = le32_to_cpu(cap->phys_id);
3258 major_rev = cap->major_rev;
3259
3260 switch (id) {
3261 case I40E_AQ_CAP_ID_SWITCH_MODE:
3262 p->switch_mode = number;
3263 break;
3264 case I40E_AQ_CAP_ID_MNG_MODE:
3265 p->management_mode = number;
3266 if (major_rev > 1) {
3267 p->mng_protocols_over_mctp = logical_id;
3268 i40e_debug(hw, I40E_DEBUG_INIT,
3269 "HW Capability: Protocols over MCTP = %d\n",
3270 p->mng_protocols_over_mctp);
3271 } else {
3272 p->mng_protocols_over_mctp = 0;
3273 }
3274 break;
3275 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3276 p->npar_enable = number;
3277 break;
3278 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3279 p->os2bmc = number;
3280 break;
3281 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3282 p->valid_functions = number;
3283 break;
3284 case I40E_AQ_CAP_ID_SRIOV:
3285 if (number == 1)
3286 p->sr_iov_1_1 = true;
3287 break;
3288 case I40E_AQ_CAP_ID_VF:
3289 p->num_vfs = number;
3290 p->vf_base_id = logical_id;
3291 break;
3292 case I40E_AQ_CAP_ID_VMDQ:
3293 if (number == 1)
3294 p->vmdq = true;
3295 break;
3296 case I40E_AQ_CAP_ID_8021QBG:
3297 if (number == 1)
3298 p->evb_802_1_qbg = true;
3299 break;
3300 case I40E_AQ_CAP_ID_8021QBR:
3301 if (number == 1)
3302 p->evb_802_1_qbh = true;
3303 break;
3304 case I40E_AQ_CAP_ID_VSI:
3305 p->num_vsis = number;
3306 break;
3307 case I40E_AQ_CAP_ID_DCB:
3308 if (number == 1) {
3309 p->dcb = true;
3310 p->enabled_tcmap = logical_id;
3311 p->maxtc = phys_id;
3312 }
3313 break;
3314 case I40E_AQ_CAP_ID_FCOE:
3315 if (number == 1)
3316 p->fcoe = true;
3317 break;
3318 case I40E_AQ_CAP_ID_ISCSI:
3319 if (number == 1)
3320 p->iscsi = true;
3321 break;
3322 case I40E_AQ_CAP_ID_RSS:
3323 p->rss = true;
3324 p->rss_table_size = number;
3325 p->rss_table_entry_width = logical_id;
3326 break;
3327 case I40E_AQ_CAP_ID_RXQ:
3328 p->num_rx_qp = number;
3329 p->base_queue = phys_id;
3330 break;
3331 case I40E_AQ_CAP_ID_TXQ:
3332 p->num_tx_qp = number;
3333 p->base_queue = phys_id;
3334 break;
3335 case I40E_AQ_CAP_ID_MSIX:
3336 p->num_msix_vectors = number;
3337 i40e_debug(hw, I40E_DEBUG_INIT,
3338 "HW Capability: MSIX vector count = %d\n",
3339 p->num_msix_vectors);
3340 break;
3341 case I40E_AQ_CAP_ID_VF_MSIX:
3342 p->num_msix_vectors_vf = number;
3343 break;
3344 case I40E_AQ_CAP_ID_FLEX10:
3345 if (major_rev == 1) {
3346 if (number == 1) {
3347 p->flex10_enable = true;
3348 p->flex10_capable = true;
3349 }
3350 } else {
3351 /* Capability revision >= 2 */
3352 if (number & 1)
3353 p->flex10_enable = true;
3354 if (number & 2)
3355 p->flex10_capable = true;
3356 }
3357 p->flex10_mode = logical_id;
3358 p->flex10_status = phys_id;
3359 break;
3360 case I40E_AQ_CAP_ID_CEM:
3361 if (number == 1)
3362 p->mgmt_cem = true;
3363 break;
3364 case I40E_AQ_CAP_ID_IWARP:
3365 if (number == 1)
3366 p->iwarp = true;
3367 break;
3368 case I40E_AQ_CAP_ID_LED:
3369 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3370 p->led[phys_id] = true;
3371 break;
3372 case I40E_AQ_CAP_ID_SDP:
3373 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3374 p->sdp[phys_id] = true;
3375 break;
3376 case I40E_AQ_CAP_ID_MDIO:
3377 if (number == 1) {
3378 p->mdio_port_num = phys_id;
3379 p->mdio_port_mode = logical_id;
3380 }
3381 break;
3382 case I40E_AQ_CAP_ID_1588:
3383 if (number == 1)
3384 p->ieee_1588 = true;
3385 break;
3386 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3387 p->fd = true;
3388 p->fd_filters_guaranteed = number;
3389 p->fd_filters_best_effort = logical_id;
3390 break;
3391 case I40E_AQ_CAP_ID_WSR_PROT:
3392 p->wr_csr_prot = (u64)number;
3393 p->wr_csr_prot |= (u64)logical_id << 32;
3394 break;
3395 case I40E_AQ_CAP_ID_NVM_MGMT:
3396 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3397 p->sec_rev_disabled = true;
3398 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3399 p->update_disabled = true;
3400 break;
3401 default:
3402 break;
3403 }
3404 }
3405
3406 if (p->fcoe)
3407 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3408
3409 /* Software override ensuring FCoE is disabled if npar or mfp
3410 * mode because it is not supported in these modes.
3411 */
3412 if (p->npar_enable || p->flex10_enable)
3413 p->fcoe = false;
3414
3415 /* count the enabled ports (aka the "not disabled" ports) */
3416 hw->num_ports = 0;
3417 for (i = 0; i < 4; i++) {
3418 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3419 u64 port_cfg = 0;
3420
3421 /* use AQ read to get the physical register offset instead
3422 * of the port relative offset
3423 */
3424 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3425 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3426 hw->num_ports++;
3427 }
3428
3429 /* OCP cards case: if a mezz is removed the Ethernet port is at
3430 * disabled state in PRTGEN_CNF register. Additional NVM read is
3431 * needed in order to check if we are dealing with OCP card.
3432 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
3433 * physical ports results in wrong partition id calculation and thus
3434 * not supporting WoL.
3435 */
3436 if (hw->mac.type == I40E_MAC_X722) {
3437 if (!i40e_acquire_nvm(hw, I40E_RESOURCE_READ)) {
3438 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
3439 2 * I40E_SR_OCP_CFG_WORD0,
3440 sizeof(ocp_cfg_word0),
3441 &ocp_cfg_word0, true, NULL);
3442 if (!status &&
3443 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
3444 hw->num_ports = 4;
3445 i40e_release_nvm(hw);
3446 }
3447 }
3448
3449 valid_functions = p->valid_functions;
3450 num_functions = 0;
3451 while (valid_functions) {
3452 if (valid_functions & 1)
3453 num_functions++;
3454 valid_functions >>= 1;
3455 }
3456
3457 /* partition id is 1-based, and functions are evenly spread
3458 * across the ports as partitions
3459 */
3460 if (hw->num_ports != 0) {
3461 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3462 hw->num_partitions = num_functions / hw->num_ports;
3463 }
3464
3465 /* additional HW specific goodies that might
3466 * someday be HW version specific
3467 */
3468 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3469}
3470
3471/**
3472 * i40e_aq_discover_capabilities
3473 * @hw: pointer to the hw struct
3474 * @buff: a virtual buffer to hold the capabilities
3475 * @buff_size: Size of the virtual buffer
3476 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3477 * @list_type_opc: capabilities type to discover - pass in the command opcode
3478 * @cmd_details: pointer to command details structure or NULL
3479 *
3480 * Get the device capabilities descriptions from the firmware
3481 **/
3482i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3483 void *buff, u16 buff_size, u16 *data_size,
3484 enum i40e_admin_queue_opc list_type_opc,
3485 struct i40e_asq_cmd_details *cmd_details)
3486{
3487 struct i40e_aqc_list_capabilites *cmd;
3488 struct i40e_aq_desc desc;
3489 i40e_status status = 0;
3490
3491 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3492
3493 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3494 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3495 status = I40E_ERR_PARAM;
3496 goto exit;
3497 }
3498
3499 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3500
3501 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3502 if (buff_size > I40E_AQ_LARGE_BUF)
3503 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3504
3505 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3506 *data_size = le16_to_cpu(desc.datalen);
3507
3508 if (status)
3509 goto exit;
3510
3511 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3512 list_type_opc);
3513
3514exit:
3515 return status;
3516}
3517
3518/**
3519 * i40e_aq_update_nvm
3520 * @hw: pointer to the hw struct
3521 * @module_pointer: module pointer location in words from the NVM beginning
3522 * @offset: byte offset from the module beginning
3523 * @length: length of the section to be written (in bytes from the offset)
3524 * @data: command buffer (size [bytes] = length)
3525 * @last_command: tells if this is the last command in a series
3526 * @preservation_flags: Preservation mode flags
3527 * @cmd_details: pointer to command details structure or NULL
3528 *
3529 * Update the NVM using the admin queue commands
3530 **/
3531i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3532 u32 offset, u16 length, void *data,
3533 bool last_command, u8 preservation_flags,
3534 struct i40e_asq_cmd_details *cmd_details)
3535{
3536 struct i40e_aq_desc desc;
3537 struct i40e_aqc_nvm_update *cmd =
3538 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3539 i40e_status status;
3540
3541 /* In offset the highest byte must be zeroed. */
3542 if (offset & 0xFF000000) {
3543 status = I40E_ERR_PARAM;
3544 goto i40e_aq_update_nvm_exit;
3545 }
3546
3547 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3548
3549 /* If this is the last command in a series, set the proper flag. */
3550 if (last_command)
3551 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3552 if (hw->mac.type == I40E_MAC_X722) {
3553 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
3554 cmd->command_flags |=
3555 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
3556 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3557 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
3558 cmd->command_flags |=
3559 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
3560 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3561 }
3562 cmd->module_pointer = module_pointer;
3563 cmd->offset = cpu_to_le32(offset);
3564 cmd->length = cpu_to_le16(length);
3565
3566 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3567 if (length > I40E_AQ_LARGE_BUF)
3568 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3569
3570 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3571
3572i40e_aq_update_nvm_exit:
3573 return status;
3574}
3575
3576/**
3577 * i40e_aq_rearrange_nvm
3578 * @hw: pointer to the hw struct
3579 * @rearrange_nvm: defines direction of rearrangement
3580 * @cmd_details: pointer to command details structure or NULL
3581 *
3582 * Rearrange NVM structure, available only for transition FW
3583 **/
3584i40e_status i40e_aq_rearrange_nvm(struct i40e_hw *hw,
3585 u8 rearrange_nvm,
3586 struct i40e_asq_cmd_details *cmd_details)
3587{
3588 struct i40e_aqc_nvm_update *cmd;
3589 i40e_status status;
3590 struct i40e_aq_desc desc;
3591
3592 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
3593
3594 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3595
3596 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
3597 I40E_AQ_NVM_REARRANGE_TO_STRUCT);
3598
3599 if (!rearrange_nvm) {
3600 status = I40E_ERR_PARAM;
3601 goto i40e_aq_rearrange_nvm_exit;
3602 }
3603
3604 cmd->command_flags |= rearrange_nvm;
3605 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3606
3607i40e_aq_rearrange_nvm_exit:
3608 return status;
3609}
3610
3611/**
3612 * i40e_aq_get_lldp_mib
3613 * @hw: pointer to the hw struct
3614 * @bridge_type: type of bridge requested
3615 * @mib_type: Local, Remote or both Local and Remote MIBs
3616 * @buff: pointer to a user supplied buffer to store the MIB block
3617 * @buff_size: size of the buffer (in bytes)
3618 * @local_len : length of the returned Local LLDP MIB
3619 * @remote_len: length of the returned Remote LLDP MIB
3620 * @cmd_details: pointer to command details structure or NULL
3621 *
3622 * Requests the complete LLDP MIB (entire packet).
3623 **/
3624i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3625 u8 mib_type, void *buff, u16 buff_size,
3626 u16 *local_len, u16 *remote_len,
3627 struct i40e_asq_cmd_details *cmd_details)
3628{
3629 struct i40e_aq_desc desc;
3630 struct i40e_aqc_lldp_get_mib *cmd =
3631 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3632 struct i40e_aqc_lldp_get_mib *resp =
3633 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3634 i40e_status status;
3635
3636 if (buff_size == 0 || !buff)
3637 return I40E_ERR_PARAM;
3638
3639 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3640 /* Indirect Command */
3641 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3642
3643 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3644 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3645 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3646
3647 desc.datalen = cpu_to_le16(buff_size);
3648
3649 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3650 if (buff_size > I40E_AQ_LARGE_BUF)
3651 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3652
3653 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3654 if (!status) {
3655 if (local_len != NULL)
3656 *local_len = le16_to_cpu(resp->local_len);
3657 if (remote_len != NULL)
3658 *remote_len = le16_to_cpu(resp->remote_len);
3659 }
3660
3661 return status;
3662}
3663
3664/**
3665 * i40e_aq_cfg_lldp_mib_change_event
3666 * @hw: pointer to the hw struct
3667 * @enable_update: Enable or Disable event posting
3668 * @cmd_details: pointer to command details structure or NULL
3669 *
3670 * Enable or Disable posting of an event on ARQ when LLDP MIB
3671 * associated with the interface changes
3672 **/
3673i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3674 bool enable_update,
3675 struct i40e_asq_cmd_details *cmd_details)
3676{
3677 struct i40e_aq_desc desc;
3678 struct i40e_aqc_lldp_update_mib *cmd =
3679 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3680 i40e_status status;
3681
3682 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3683
3684 if (!enable_update)
3685 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3686
3687 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3688
3689 return status;
3690}
3691
3692/**
3693 * i40e_aq_restore_lldp
3694 * @hw: pointer to the hw struct
3695 * @setting: pointer to factory setting variable or NULL
3696 * @restore: True if factory settings should be restored
3697 * @cmd_details: pointer to command details structure or NULL
3698 *
3699 * Restore LLDP Agent factory settings if @restore set to True. In other case
3700 * only returns factory setting in AQ response.
3701 **/
3702enum i40e_status_code
3703i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
3704 struct i40e_asq_cmd_details *cmd_details)
3705{
3706 struct i40e_aq_desc desc;
3707 struct i40e_aqc_lldp_restore *cmd =
3708 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
3709 i40e_status status;
3710
3711 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) {
3712 i40e_debug(hw, I40E_DEBUG_ALL,
3713 "Restore LLDP not supported by current FW version.\n");
3714 return I40E_ERR_DEVICE_NOT_SUPPORTED;
3715 }
3716
3717 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
3718
3719 if (restore)
3720 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
3721
3722 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3723
3724 if (setting)
3725 *setting = cmd->command & 1;
3726
3727 return status;
3728}
3729
3730/**
3731 * i40e_aq_stop_lldp
3732 * @hw: pointer to the hw struct
3733 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3734 * @persist: True if stop of LLDP should be persistent across power cycles
3735 * @cmd_details: pointer to command details structure or NULL
3736 *
3737 * Stop or Shutdown the embedded LLDP Agent
3738 **/
3739i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3740 bool persist,
3741 struct i40e_asq_cmd_details *cmd_details)
3742{
3743 struct i40e_aq_desc desc;
3744 struct i40e_aqc_lldp_stop *cmd =
3745 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3746 i40e_status status;
3747
3748 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3749
3750 if (shutdown_agent)
3751 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3752
3753 if (persist) {
3754 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
3755 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
3756 else
3757 i40e_debug(hw, I40E_DEBUG_ALL,
3758 "Persistent Stop LLDP not supported by current FW version.\n");
3759 }
3760
3761 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3762
3763 return status;
3764}
3765
3766/**
3767 * i40e_aq_start_lldp
3768 * @hw: pointer to the hw struct
3769 * @buff: buffer for result
3770 * @persist: True if start of LLDP should be persistent across power cycles
3771 * @buff_size: buffer size
3772 * @cmd_details: pointer to command details structure or NULL
3773 *
3774 * Start the embedded LLDP Agent on all ports.
3775 **/
3776i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, bool persist,
3777 struct i40e_asq_cmd_details *cmd_details)
3778{
3779 struct i40e_aq_desc desc;
3780 struct i40e_aqc_lldp_start *cmd =
3781 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3782 i40e_status status;
3783
3784 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3785
3786 cmd->command = I40E_AQ_LLDP_AGENT_START;
3787
3788 if (persist) {
3789 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
3790 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
3791 else
3792 i40e_debug(hw, I40E_DEBUG_ALL,
3793 "Persistent Start LLDP not supported by current FW version.\n");
3794 }
3795
3796 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3797
3798 return status;
3799}
3800
3801/**
3802 * i40e_aq_set_dcb_parameters
3803 * @hw: pointer to the hw struct
3804 * @cmd_details: pointer to command details structure or NULL
3805 * @dcb_enable: True if DCB configuration needs to be applied
3806 *
3807 **/
3808enum i40e_status_code
3809i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
3810 struct i40e_asq_cmd_details *cmd_details)
3811{
3812 struct i40e_aq_desc desc;
3813 struct i40e_aqc_set_dcb_parameters *cmd =
3814 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
3815 i40e_status status;
3816
3817 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
3818 return I40E_ERR_DEVICE_NOT_SUPPORTED;
3819
3820 i40e_fill_default_direct_cmd_desc(&desc,
3821 i40e_aqc_opc_set_dcb_parameters);
3822
3823 if (dcb_enable) {
3824 cmd->valid_flags = I40E_DCB_VALID;
3825 cmd->command = I40E_AQ_DCB_SET_AGENT;
3826 }
3827 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3828
3829 return status;
3830}
3831
3832/**
3833 * i40e_aq_get_cee_dcb_config
3834 * @hw: pointer to the hw struct
3835 * @buff: response buffer that stores CEE operational configuration
3836 * @buff_size: size of the buffer passed
3837 * @cmd_details: pointer to command details structure or NULL
3838 *
3839 * Get CEE DCBX mode operational configuration from firmware
3840 **/
3841i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3842 void *buff, u16 buff_size,
3843 struct i40e_asq_cmd_details *cmd_details)
3844{
3845 struct i40e_aq_desc desc;
3846 i40e_status status;
3847
3848 if (buff_size == 0 || !buff)
3849 return I40E_ERR_PARAM;
3850
3851 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3852
3853 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3854 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3855 cmd_details);
3856
3857 return status;
3858}
3859
3860/**
3861 * i40e_aq_add_udp_tunnel
3862 * @hw: pointer to the hw struct
3863 * @udp_port: the UDP port to add in Host byte order
3864 * @protocol_index: protocol index type
3865 * @filter_index: pointer to filter index
3866 * @cmd_details: pointer to command details structure or NULL
3867 *
3868 * Note: Firmware expects the udp_port value to be in Little Endian format,
3869 * and this function will call cpu_to_le16 to convert from Host byte order to
3870 * Little Endian order.
3871 **/
3872i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3873 u16 udp_port, u8 protocol_index,
3874 u8 *filter_index,
3875 struct i40e_asq_cmd_details *cmd_details)
3876{
3877 struct i40e_aq_desc desc;
3878 struct i40e_aqc_add_udp_tunnel *cmd =
3879 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3880 struct i40e_aqc_del_udp_tunnel_completion *resp =
3881 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3882 i40e_status status;
3883
3884 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3885
3886 cmd->udp_port = cpu_to_le16(udp_port);
3887 cmd->protocol_type = protocol_index;
3888
3889 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3890
3891 if (!status && filter_index)
3892 *filter_index = resp->index;
3893
3894 return status;
3895}
3896
3897/**
3898 * i40e_aq_del_udp_tunnel
3899 * @hw: pointer to the hw struct
3900 * @index: filter index
3901 * @cmd_details: pointer to command details structure or NULL
3902 **/
3903i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3904 struct i40e_asq_cmd_details *cmd_details)
3905{
3906 struct i40e_aq_desc desc;
3907 struct i40e_aqc_remove_udp_tunnel *cmd =
3908 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3909 i40e_status status;
3910
3911 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3912
3913 cmd->index = index;
3914
3915 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3916
3917 return status;
3918}
3919
3920/**
3921 * i40e_aq_delete_element - Delete switch element
3922 * @hw: pointer to the hw struct
3923 * @seid: the SEID to delete from the switch
3924 * @cmd_details: pointer to command details structure or NULL
3925 *
3926 * This deletes a switch element from the switch.
3927 **/
3928i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3929 struct i40e_asq_cmd_details *cmd_details)
3930{
3931 struct i40e_aq_desc desc;
3932 struct i40e_aqc_switch_seid *cmd =
3933 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3934 i40e_status status;
3935
3936 if (seid == 0)
3937 return I40E_ERR_PARAM;
3938
3939 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3940
3941 cmd->seid = cpu_to_le16(seid);
3942
3943 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3944
3945 return status;
3946}
3947
3948/**
3949 * i40e_aq_dcb_updated - DCB Updated Command
3950 * @hw: pointer to the hw struct
3951 * @cmd_details: pointer to command details structure or NULL
3952 *
3953 * EMP will return when the shared RPB settings have been
3954 * recomputed and modified. The retval field in the descriptor
3955 * will be set to 0 when RPB is modified.
3956 **/
3957i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3958 struct i40e_asq_cmd_details *cmd_details)
3959{
3960 struct i40e_aq_desc desc;
3961 i40e_status status;
3962
3963 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3964
3965 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3966
3967 return status;
3968}
3969
3970/**
3971 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3972 * @hw: pointer to the hw struct
3973 * @seid: seid for the physical port/switching component/vsi
3974 * @buff: Indirect buffer to hold data parameters and response
3975 * @buff_size: Indirect buffer size
3976 * @opcode: Tx scheduler AQ command opcode
3977 * @cmd_details: pointer to command details structure or NULL
3978 *
3979 * Generic command handler for Tx scheduler AQ commands
3980 **/
3981static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3982 void *buff, u16 buff_size,
3983 enum i40e_admin_queue_opc opcode,
3984 struct i40e_asq_cmd_details *cmd_details)
3985{
3986 struct i40e_aq_desc desc;
3987 struct i40e_aqc_tx_sched_ind *cmd =
3988 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3989 i40e_status status;
3990 bool cmd_param_flag = false;
3991
3992 switch (opcode) {
3993 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3994 case i40e_aqc_opc_configure_vsi_tc_bw:
3995 case i40e_aqc_opc_enable_switching_comp_ets:
3996 case i40e_aqc_opc_modify_switching_comp_ets:
3997 case i40e_aqc_opc_disable_switching_comp_ets:
3998 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3999 case i40e_aqc_opc_configure_switching_comp_bw_config:
4000 cmd_param_flag = true;
4001 break;
4002 case i40e_aqc_opc_query_vsi_bw_config:
4003 case i40e_aqc_opc_query_vsi_ets_sla_config:
4004 case i40e_aqc_opc_query_switching_comp_ets_config:
4005 case i40e_aqc_opc_query_port_ets_config:
4006 case i40e_aqc_opc_query_switching_comp_bw_config:
4007 cmd_param_flag = false;
4008 break;
4009 default:
4010 return I40E_ERR_PARAM;
4011 }
4012
4013 i40e_fill_default_direct_cmd_desc(&desc, opcode);
4014
4015 /* Indirect command */
4016 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4017 if (cmd_param_flag)
4018 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4019 if (buff_size > I40E_AQ_LARGE_BUF)
4020 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4021
4022 desc.datalen = cpu_to_le16(buff_size);
4023
4024 cmd->vsi_seid = cpu_to_le16(seid);
4025
4026 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4027
4028 return status;
4029}
4030
4031/**
4032 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4033 * @hw: pointer to the hw struct
4034 * @seid: VSI seid
4035 * @credit: BW limit credits (0 = disabled)
4036 * @max_credit: Max BW limit credits
4037 * @cmd_details: pointer to command details structure or NULL
4038 **/
4039i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4040 u16 seid, u16 credit, u8 max_credit,
4041 struct i40e_asq_cmd_details *cmd_details)
4042{
4043 struct i40e_aq_desc desc;
4044 struct i40e_aqc_configure_vsi_bw_limit *cmd =
4045 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4046 i40e_status status;
4047
4048 i40e_fill_default_direct_cmd_desc(&desc,
4049 i40e_aqc_opc_configure_vsi_bw_limit);
4050
4051 cmd->vsi_seid = cpu_to_le16(seid);
4052 cmd->credit = cpu_to_le16(credit);
4053 cmd->max_credit = max_credit;
4054
4055 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4056
4057 return status;
4058}
4059
4060/**
4061 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
4062 * @hw: pointer to the hw struct
4063 * @seid: VSI seid
4064 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4065 * @cmd_details: pointer to command details structure or NULL
4066 **/
4067i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4068 u16 seid,
4069 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4070 struct i40e_asq_cmd_details *cmd_details)
4071{
4072 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4073 i40e_aqc_opc_configure_vsi_tc_bw,
4074 cmd_details);
4075}
4076
4077/**
4078 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
4079 * @hw: pointer to the hw struct
4080 * @seid: seid of the switching component connected to Physical Port
4081 * @ets_data: Buffer holding ETS parameters
4082 * @opcode: Tx scheduler AQ command opcode
4083 * @cmd_details: pointer to command details structure or NULL
4084 **/
4085i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
4086 u16 seid,
4087 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
4088 enum i40e_admin_queue_opc opcode,
4089 struct i40e_asq_cmd_details *cmd_details)
4090{
4091 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
4092 sizeof(*ets_data), opcode, cmd_details);
4093}
4094
4095/**
4096 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
4097 * @hw: pointer to the hw struct
4098 * @seid: seid of the switching component
4099 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
4100 * @cmd_details: pointer to command details structure or NULL
4101 **/
4102i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
4103 u16 seid,
4104 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
4105 struct i40e_asq_cmd_details *cmd_details)
4106{
4107 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4108 i40e_aqc_opc_configure_switching_comp_bw_config,
4109 cmd_details);
4110}
4111
4112/**
4113 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4114 * @hw: pointer to the hw struct
4115 * @seid: seid of the VSI
4116 * @bw_data: Buffer to hold VSI BW configuration
4117 * @cmd_details: pointer to command details structure or NULL
4118 **/
4119i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4120 u16 seid,
4121 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4122 struct i40e_asq_cmd_details *cmd_details)
4123{
4124 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4125 i40e_aqc_opc_query_vsi_bw_config,
4126 cmd_details);
4127}
4128
4129/**
4130 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4131 * @hw: pointer to the hw struct
4132 * @seid: seid of the VSI
4133 * @bw_data: Buffer to hold VSI BW configuration per TC
4134 * @cmd_details: pointer to command details structure or NULL
4135 **/
4136i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4137 u16 seid,
4138 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4139 struct i40e_asq_cmd_details *cmd_details)
4140{
4141 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4142 i40e_aqc_opc_query_vsi_ets_sla_config,
4143 cmd_details);
4144}
4145
4146/**
4147 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4148 * @hw: pointer to the hw struct
4149 * @seid: seid of the switching component
4150 * @bw_data: Buffer to hold switching component's per TC BW config
4151 * @cmd_details: pointer to command details structure or NULL
4152 **/
4153i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4154 u16 seid,
4155 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4156 struct i40e_asq_cmd_details *cmd_details)
4157{
4158 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4159 i40e_aqc_opc_query_switching_comp_ets_config,
4160 cmd_details);
4161}
4162
4163/**
4164 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4165 * @hw: pointer to the hw struct
4166 * @seid: seid of the VSI or switching component connected to Physical Port
4167 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4168 * @cmd_details: pointer to command details structure or NULL
4169 **/
4170i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4171 u16 seid,
4172 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4173 struct i40e_asq_cmd_details *cmd_details)
4174{
4175 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4176 i40e_aqc_opc_query_port_ets_config,
4177 cmd_details);
4178}
4179
4180/**
4181 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4182 * @hw: pointer to the hw struct
4183 * @seid: seid of the switching component
4184 * @bw_data: Buffer to hold switching component's BW configuration
4185 * @cmd_details: pointer to command details structure or NULL
4186 **/
4187i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4188 u16 seid,
4189 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4190 struct i40e_asq_cmd_details *cmd_details)
4191{
4192 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4193 i40e_aqc_opc_query_switching_comp_bw_config,
4194 cmd_details);
4195}
4196
4197/**
4198 * i40e_validate_filter_settings
4199 * @hw: pointer to the hardware structure
4200 * @settings: Filter control settings
4201 *
4202 * Check and validate the filter control settings passed.
4203 * The function checks for the valid filter/context sizes being
4204 * passed for FCoE and PE.
4205 *
4206 * Returns 0 if the values passed are valid and within
4207 * range else returns an error.
4208 **/
4209static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
4210 struct i40e_filter_control_settings *settings)
4211{
4212 u32 fcoe_cntx_size, fcoe_filt_size;
4213 u32 pe_cntx_size, pe_filt_size;
4214 u32 fcoe_fmax;
4215 u32 val;
4216
4217 /* Validate FCoE settings passed */
4218 switch (settings->fcoe_filt_num) {
4219 case I40E_HASH_FILTER_SIZE_1K:
4220 case I40E_HASH_FILTER_SIZE_2K:
4221 case I40E_HASH_FILTER_SIZE_4K:
4222 case I40E_HASH_FILTER_SIZE_8K:
4223 case I40E_HASH_FILTER_SIZE_16K:
4224 case I40E_HASH_FILTER_SIZE_32K:
4225 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4226 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4227 break;
4228 default:
4229 return I40E_ERR_PARAM;
4230 }
4231
4232 switch (settings->fcoe_cntx_num) {
4233 case I40E_DMA_CNTX_SIZE_512:
4234 case I40E_DMA_CNTX_SIZE_1K:
4235 case I40E_DMA_CNTX_SIZE_2K:
4236 case I40E_DMA_CNTX_SIZE_4K:
4237 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4238 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4239 break;
4240 default:
4241 return I40E_ERR_PARAM;
4242 }
4243
4244 /* Validate PE settings passed */
4245 switch (settings->pe_filt_num) {
4246 case I40E_HASH_FILTER_SIZE_1K:
4247 case I40E_HASH_FILTER_SIZE_2K:
4248 case I40E_HASH_FILTER_SIZE_4K:
4249 case I40E_HASH_FILTER_SIZE_8K:
4250 case I40E_HASH_FILTER_SIZE_16K:
4251 case I40E_HASH_FILTER_SIZE_32K:
4252 case I40E_HASH_FILTER_SIZE_64K:
4253 case I40E_HASH_FILTER_SIZE_128K:
4254 case I40E_HASH_FILTER_SIZE_256K:
4255 case I40E_HASH_FILTER_SIZE_512K:
4256 case I40E_HASH_FILTER_SIZE_1M:
4257 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4258 pe_filt_size <<= (u32)settings->pe_filt_num;
4259 break;
4260 default:
4261 return I40E_ERR_PARAM;
4262 }
4263
4264 switch (settings->pe_cntx_num) {
4265 case I40E_DMA_CNTX_SIZE_512:
4266 case I40E_DMA_CNTX_SIZE_1K:
4267 case I40E_DMA_CNTX_SIZE_2K:
4268 case I40E_DMA_CNTX_SIZE_4K:
4269 case I40E_DMA_CNTX_SIZE_8K:
4270 case I40E_DMA_CNTX_SIZE_16K:
4271 case I40E_DMA_CNTX_SIZE_32K:
4272 case I40E_DMA_CNTX_SIZE_64K:
4273 case I40E_DMA_CNTX_SIZE_128K:
4274 case I40E_DMA_CNTX_SIZE_256K:
4275 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4276 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4277 break;
4278 default:
4279 return I40E_ERR_PARAM;
4280 }
4281
4282 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4283 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4284 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4285 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4286 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4287 return I40E_ERR_INVALID_SIZE;
4288
4289 return 0;
4290}
4291
4292/**
4293 * i40e_set_filter_control
4294 * @hw: pointer to the hardware structure
4295 * @settings: Filter control settings
4296 *
4297 * Set the Queue Filters for PE/FCoE and enable filters required
4298 * for a single PF. It is expected that these settings are programmed
4299 * at the driver initialization time.
4300 **/
4301i40e_status i40e_set_filter_control(struct i40e_hw *hw,
4302 struct i40e_filter_control_settings *settings)
4303{
4304 i40e_status ret = 0;
4305 u32 hash_lut_size = 0;
4306 u32 val;
4307
4308 if (!settings)
4309 return I40E_ERR_PARAM;
4310
4311 /* Validate the input settings */
4312 ret = i40e_validate_filter_settings(hw, settings);
4313 if (ret)
4314 return ret;
4315
4316 /* Read the PF Queue Filter control register */
4317 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
4318
4319 /* Program required PE hash buckets for the PF */
4320 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4321 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4322 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4323 /* Program required PE contexts for the PF */
4324 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4325 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4326 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4327
4328 /* Program required FCoE hash buckets for the PF */
4329 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4330 val |= ((u32)settings->fcoe_filt_num <<
4331 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4332 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4333 /* Program required FCoE DDP contexts for the PF */
4334 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4335 val |= ((u32)settings->fcoe_cntx_num <<
4336 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4337 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4338
4339 /* Program Hash LUT size for the PF */
4340 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4341 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4342 hash_lut_size = 1;
4343 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4344 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4345
4346 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4347 if (settings->enable_fdir)
4348 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4349 if (settings->enable_ethtype)
4350 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4351 if (settings->enable_macvlan)
4352 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4353
4354 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
4355
4356 return 0;
4357}
4358
4359/**
4360 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4361 * @hw: pointer to the hw struct
4362 * @mac_addr: MAC address to use in the filter
4363 * @ethtype: Ethertype to use in the filter
4364 * @flags: Flags that needs to be applied to the filter
4365 * @vsi_seid: seid of the control VSI
4366 * @queue: VSI queue number to send the packet to
4367 * @is_add: Add control packet filter if True else remove
4368 * @stats: Structure to hold information on control filter counts
4369 * @cmd_details: pointer to command details structure or NULL
4370 *
4371 * This command will Add or Remove control packet filter for a control VSI.
4372 * In return it will update the total number of perfect filter count in
4373 * the stats member.
4374 **/
4375i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4376 u8 *mac_addr, u16 ethtype, u16 flags,
4377 u16 vsi_seid, u16 queue, bool is_add,
4378 struct i40e_control_filter_stats *stats,
4379 struct i40e_asq_cmd_details *cmd_details)
4380{
4381 struct i40e_aq_desc desc;
4382 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4383 (struct i40e_aqc_add_remove_control_packet_filter *)
4384 &desc.params.raw;
4385 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4386 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4387 &desc.params.raw;
4388 i40e_status status;
4389
4390 if (vsi_seid == 0)
4391 return I40E_ERR_PARAM;
4392
4393 if (is_add) {
4394 i40e_fill_default_direct_cmd_desc(&desc,
4395 i40e_aqc_opc_add_control_packet_filter);
4396 cmd->queue = cpu_to_le16(queue);
4397 } else {
4398 i40e_fill_default_direct_cmd_desc(&desc,
4399 i40e_aqc_opc_remove_control_packet_filter);
4400 }
4401
4402 if (mac_addr)
4403 ether_addr_copy(cmd->mac, mac_addr);
4404
4405 cmd->etype = cpu_to_le16(ethtype);
4406 cmd->flags = cpu_to_le16(flags);
4407 cmd->seid = cpu_to_le16(vsi_seid);
4408
4409 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4410
4411 if (!status && stats) {
4412 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
4413 stats->etype_used = le16_to_cpu(resp->etype_used);
4414 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
4415 stats->etype_free = le16_to_cpu(resp->etype_free);
4416 }
4417
4418 return status;
4419}
4420
4421/**
4422 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4423 * @hw: pointer to the hw struct
4424 * @seid: VSI seid to add ethertype filter from
4425 **/
4426void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4427 u16 seid)
4428{
4429#define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4430 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4431 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4432 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4433 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4434 i40e_status status;
4435
4436 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4437 seid, 0, true, NULL,
4438 NULL);
4439 if (status)
4440 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4441}
4442
4443/**
4444 * i40e_aq_alternate_read
4445 * @hw: pointer to the hardware structure
4446 * @reg_addr0: address of first dword to be read
4447 * @reg_val0: pointer for data read from 'reg_addr0'
4448 * @reg_addr1: address of second dword to be read
4449 * @reg_val1: pointer for data read from 'reg_addr1'
4450 *
4451 * Read one or two dwords from alternate structure. Fields are indicated
4452 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4453 * is not passed then only register at 'reg_addr0' is read.
4454 *
4455 **/
4456static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
4457 u32 reg_addr0, u32 *reg_val0,
4458 u32 reg_addr1, u32 *reg_val1)
4459{
4460 struct i40e_aq_desc desc;
4461 struct i40e_aqc_alternate_write *cmd_resp =
4462 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4463 i40e_status status;
4464
4465 if (!reg_val0)
4466 return I40E_ERR_PARAM;
4467
4468 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4469 cmd_resp->address0 = cpu_to_le32(reg_addr0);
4470 cmd_resp->address1 = cpu_to_le32(reg_addr1);
4471
4472 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4473
4474 if (!status) {
4475 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4476
4477 if (reg_val1)
4478 *reg_val1 = le32_to_cpu(cmd_resp->data1);
4479 }
4480
4481 return status;
4482}
4483
4484/**
4485 * i40e_aq_resume_port_tx
4486 * @hw: pointer to the hardware structure
4487 * @cmd_details: pointer to command details structure or NULL
4488 *
4489 * Resume port's Tx traffic
4490 **/
4491i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
4492 struct i40e_asq_cmd_details *cmd_details)
4493{
4494 struct i40e_aq_desc desc;
4495 i40e_status status;
4496
4497 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4498
4499 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4500
4501 return status;
4502}
4503
4504/**
4505 * i40e_set_pci_config_data - store PCI bus info
4506 * @hw: pointer to hardware structure
4507 * @link_status: the link status word from PCI config space
4508 *
4509 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4510 **/
4511void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4512{
4513 hw->bus.type = i40e_bus_type_pci_express;
4514
4515 switch (link_status & PCI_EXP_LNKSTA_NLW) {
4516 case PCI_EXP_LNKSTA_NLW_X1:
4517 hw->bus.width = i40e_bus_width_pcie_x1;
4518 break;
4519 case PCI_EXP_LNKSTA_NLW_X2:
4520 hw->bus.width = i40e_bus_width_pcie_x2;
4521 break;
4522 case PCI_EXP_LNKSTA_NLW_X4:
4523 hw->bus.width = i40e_bus_width_pcie_x4;
4524 break;
4525 case PCI_EXP_LNKSTA_NLW_X8:
4526 hw->bus.width = i40e_bus_width_pcie_x8;
4527 break;
4528 default:
4529 hw->bus.width = i40e_bus_width_unknown;
4530 break;
4531 }
4532
4533 switch (link_status & PCI_EXP_LNKSTA_CLS) {
4534 case PCI_EXP_LNKSTA_CLS_2_5GB:
4535 hw->bus.speed = i40e_bus_speed_2500;
4536 break;
4537 case PCI_EXP_LNKSTA_CLS_5_0GB:
4538 hw->bus.speed = i40e_bus_speed_5000;
4539 break;
4540 case PCI_EXP_LNKSTA_CLS_8_0GB:
4541 hw->bus.speed = i40e_bus_speed_8000;
4542 break;
4543 default:
4544 hw->bus.speed = i40e_bus_speed_unknown;
4545 break;
4546 }
4547}
4548
4549/**
4550 * i40e_aq_debug_dump
4551 * @hw: pointer to the hardware structure
4552 * @cluster_id: specific cluster to dump
4553 * @table_id: table id within cluster
4554 * @start_index: index of line in the block to read
4555 * @buff_size: dump buffer size
4556 * @buff: dump buffer
4557 * @ret_buff_size: actual buffer size returned
4558 * @ret_next_table: next block to read
4559 * @ret_next_index: next index to read
4560 * @cmd_details: pointer to command details structure or NULL
4561 *
4562 * Dump internal FW/HW data for debug purposes.
4563 *
4564 **/
4565i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4566 u8 table_id, u32 start_index, u16 buff_size,
4567 void *buff, u16 *ret_buff_size,
4568 u8 *ret_next_table, u32 *ret_next_index,
4569 struct i40e_asq_cmd_details *cmd_details)
4570{
4571 struct i40e_aq_desc desc;
4572 struct i40e_aqc_debug_dump_internals *cmd =
4573 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4574 struct i40e_aqc_debug_dump_internals *resp =
4575 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4576 i40e_status status;
4577
4578 if (buff_size == 0 || !buff)
4579 return I40E_ERR_PARAM;
4580
4581 i40e_fill_default_direct_cmd_desc(&desc,
4582 i40e_aqc_opc_debug_dump_internals);
4583 /* Indirect Command */
4584 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4585 if (buff_size > I40E_AQ_LARGE_BUF)
4586 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4587
4588 cmd->cluster_id = cluster_id;
4589 cmd->table_id = table_id;
4590 cmd->idx = cpu_to_le32(start_index);
4591
4592 desc.datalen = cpu_to_le16(buff_size);
4593
4594 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4595 if (!status) {
4596 if (ret_buff_size)
4597 *ret_buff_size = le16_to_cpu(desc.datalen);
4598 if (ret_next_table)
4599 *ret_next_table = resp->table_id;
4600 if (ret_next_index)
4601 *ret_next_index = le32_to_cpu(resp->idx);
4602 }
4603
4604 return status;
4605}
4606
4607/**
4608 * i40e_read_bw_from_alt_ram
4609 * @hw: pointer to the hardware structure
4610 * @max_bw: pointer for max_bw read
4611 * @min_bw: pointer for min_bw read
4612 * @min_valid: pointer for bool that is true if min_bw is a valid value
4613 * @max_valid: pointer for bool that is true if max_bw is a valid value
4614 *
4615 * Read bw from the alternate ram for the given pf
4616 **/
4617i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4618 u32 *max_bw, u32 *min_bw,
4619 bool *min_valid, bool *max_valid)
4620{
4621 i40e_status status;
4622 u32 max_bw_addr, min_bw_addr;
4623
4624 /* Calculate the address of the min/max bw registers */
4625 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4626 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4627 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4628 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4629 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4630 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4631
4632 /* Read the bandwidths from alt ram */
4633 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4634 min_bw_addr, min_bw);
4635
4636 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4637 *min_valid = true;
4638 else
4639 *min_valid = false;
4640
4641 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4642 *max_valid = true;
4643 else
4644 *max_valid = false;
4645
4646 return status;
4647}
4648
4649/**
4650 * i40e_aq_configure_partition_bw
4651 * @hw: pointer to the hardware structure
4652 * @bw_data: Buffer holding valid pfs and bw limits
4653 * @cmd_details: pointer to command details
4654 *
4655 * Configure partitions guaranteed/max bw
4656 **/
4657i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4658 struct i40e_aqc_configure_partition_bw_data *bw_data,
4659 struct i40e_asq_cmd_details *cmd_details)
4660{
4661 i40e_status status;
4662 struct i40e_aq_desc desc;
4663 u16 bwd_size = sizeof(*bw_data);
4664
4665 i40e_fill_default_direct_cmd_desc(&desc,
4666 i40e_aqc_opc_configure_partition_bw);
4667
4668 /* Indirect command */
4669 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4670 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4671
4672 if (bwd_size > I40E_AQ_LARGE_BUF)
4673 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4674
4675 desc.datalen = cpu_to_le16(bwd_size);
4676
4677 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4678 cmd_details);
4679
4680 return status;
4681}
4682
4683/**
4684 * i40e_read_phy_register_clause22
4685 * @hw: pointer to the HW structure
4686 * @reg: register address in the page
4687 * @phy_addr: PHY address on MDIO interface
4688 * @value: PHY register value
4689 *
4690 * Reads specified PHY register value
4691 **/
4692i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw,
4693 u16 reg, u8 phy_addr, u16 *value)
4694{
4695 i40e_status status = I40E_ERR_TIMEOUT;
4696 u8 port_num = (u8)hw->func_caps.mdio_port_num;
4697 u32 command = 0;
4698 u16 retry = 1000;
4699
4700 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4701 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4702 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
4703 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4704 (I40E_GLGEN_MSCA_MDICMD_MASK);
4705 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4706 do {
4707 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4708 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4709 status = 0;
4710 break;
4711 }
4712 udelay(10);
4713 retry--;
4714 } while (retry);
4715
4716 if (status) {
4717 i40e_debug(hw, I40E_DEBUG_PHY,
4718 "PHY: Can't write command to external PHY.\n");
4719 } else {
4720 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4721 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4722 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4723 }
4724
4725 return status;
4726}
4727
4728/**
4729 * i40e_write_phy_register_clause22
4730 * @hw: pointer to the HW structure
4731 * @reg: register address in the page
4732 * @phy_addr: PHY address on MDIO interface
4733 * @value: PHY register value
4734 *
4735 * Writes specified PHY register value
4736 **/
4737i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw,
4738 u16 reg, u8 phy_addr, u16 value)
4739{
4740 i40e_status status = I40E_ERR_TIMEOUT;
4741 u8 port_num = (u8)hw->func_caps.mdio_port_num;
4742 u32 command = 0;
4743 u16 retry = 1000;
4744
4745 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4746 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4747
4748 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4749 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4750 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
4751 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4752 (I40E_GLGEN_MSCA_MDICMD_MASK);
4753
4754 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4755 do {
4756 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4757 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4758 status = 0;
4759 break;
4760 }
4761 udelay(10);
4762 retry--;
4763 } while (retry);
4764
4765 return status;
4766}
4767
4768/**
4769 * i40e_read_phy_register_clause45
4770 * @hw: pointer to the HW structure
4771 * @page: registers page number
4772 * @reg: register address in the page
4773 * @phy_addr: PHY address on MDIO interface
4774 * @value: PHY register value
4775 *
4776 * Reads specified PHY register value
4777 **/
4778i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw,
4779 u8 page, u16 reg, u8 phy_addr, u16 *value)
4780{
4781 i40e_status status = I40E_ERR_TIMEOUT;
4782 u32 command = 0;
4783 u16 retry = 1000;
4784 u8 port_num = hw->func_caps.mdio_port_num;
4785
4786 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4787 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4788 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4789 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4790 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4791 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4792 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4793 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4794 do {
4795 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4796 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4797 status = 0;
4798 break;
4799 }
4800 usleep_range(10, 20);
4801 retry--;
4802 } while (retry);
4803
4804 if (status) {
4805 i40e_debug(hw, I40E_DEBUG_PHY,
4806 "PHY: Can't write command to external PHY.\n");
4807 goto phy_read_end;
4808 }
4809
4810 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4811 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4812 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
4813 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4814 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4815 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4816 status = I40E_ERR_TIMEOUT;
4817 retry = 1000;
4818 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4819 do {
4820 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4821 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4822 status = 0;
4823 break;
4824 }
4825 usleep_range(10, 20);
4826 retry--;
4827 } while (retry);
4828
4829 if (!status) {
4830 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4831 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4832 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4833 } else {
4834 i40e_debug(hw, I40E_DEBUG_PHY,
4835 "PHY: Can't read register value from external PHY.\n");
4836 }
4837
4838phy_read_end:
4839 return status;
4840}
4841
4842/**
4843 * i40e_write_phy_register_clause45
4844 * @hw: pointer to the HW structure
4845 * @page: registers page number
4846 * @reg: register address in the page
4847 * @phy_addr: PHY address on MDIO interface
4848 * @value: PHY register value
4849 *
4850 * Writes value to specified PHY register
4851 **/
4852i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw,
4853 u8 page, u16 reg, u8 phy_addr, u16 value)
4854{
4855 i40e_status status = I40E_ERR_TIMEOUT;
4856 u32 command = 0;
4857 u16 retry = 1000;
4858 u8 port_num = hw->func_caps.mdio_port_num;
4859
4860 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4861 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4862 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4863 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4864 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4865 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4866 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4867 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4868 do {
4869 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4870 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4871 status = 0;
4872 break;
4873 }
4874 usleep_range(10, 20);
4875 retry--;
4876 } while (retry);
4877 if (status) {
4878 i40e_debug(hw, I40E_DEBUG_PHY,
4879 "PHY: Can't write command to external PHY.\n");
4880 goto phy_write_end;
4881 }
4882
4883 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4884 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4885
4886 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4887 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4888 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
4889 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4890 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4891 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4892 status = I40E_ERR_TIMEOUT;
4893 retry = 1000;
4894 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4895 do {
4896 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4897 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4898 status = 0;
4899 break;
4900 }
4901 usleep_range(10, 20);
4902 retry--;
4903 } while (retry);
4904
4905phy_write_end:
4906 return status;
4907}
4908
4909/**
4910 * i40e_write_phy_register
4911 * @hw: pointer to the HW structure
4912 * @page: registers page number
4913 * @reg: register address in the page
4914 * @phy_addr: PHY address on MDIO interface
4915 * @value: PHY register value
4916 *
4917 * Writes value to specified PHY register
4918 **/
4919i40e_status i40e_write_phy_register(struct i40e_hw *hw,
4920 u8 page, u16 reg, u8 phy_addr, u16 value)
4921{
4922 i40e_status status;
4923
4924 switch (hw->device_id) {
4925 case I40E_DEV_ID_1G_BASE_T_X722:
4926 status = i40e_write_phy_register_clause22(hw, reg, phy_addr,
4927 value);
4928 break;
4929 case I40E_DEV_ID_5G_BASE_T_BC:
4930 case I40E_DEV_ID_10G_BASE_T:
4931 case I40E_DEV_ID_10G_BASE_T4:
4932 case I40E_DEV_ID_10G_BASE_T_BC:
4933 case I40E_DEV_ID_10G_BASE_T_X722:
4934 case I40E_DEV_ID_25G_B:
4935 case I40E_DEV_ID_25G_SFP28:
4936 status = i40e_write_phy_register_clause45(hw, page, reg,
4937 phy_addr, value);
4938 break;
4939 default:
4940 status = I40E_ERR_UNKNOWN_PHY;
4941 break;
4942 }
4943
4944 return status;
4945}
4946
4947/**
4948 * i40e_read_phy_register
4949 * @hw: pointer to the HW structure
4950 * @page: registers page number
4951 * @reg: register address in the page
4952 * @phy_addr: PHY address on MDIO interface
4953 * @value: PHY register value
4954 *
4955 * Reads specified PHY register value
4956 **/
4957i40e_status i40e_read_phy_register(struct i40e_hw *hw,
4958 u8 page, u16 reg, u8 phy_addr, u16 *value)
4959{
4960 i40e_status status;
4961
4962 switch (hw->device_id) {
4963 case I40E_DEV_ID_1G_BASE_T_X722:
4964 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
4965 value);
4966 break;
4967 case I40E_DEV_ID_5G_BASE_T_BC:
4968 case I40E_DEV_ID_10G_BASE_T:
4969 case I40E_DEV_ID_10G_BASE_T4:
4970 case I40E_DEV_ID_10G_BASE_T_BC:
4971 case I40E_DEV_ID_10G_BASE_T_X722:
4972 case I40E_DEV_ID_25G_B:
4973 case I40E_DEV_ID_25G_SFP28:
4974 status = i40e_read_phy_register_clause45(hw, page, reg,
4975 phy_addr, value);
4976 break;
4977 default:
4978 status = I40E_ERR_UNKNOWN_PHY;
4979 break;
4980 }
4981
4982 return status;
4983}
4984
4985/**
4986 * i40e_get_phy_address
4987 * @hw: pointer to the HW structure
4988 * @dev_num: PHY port num that address we want
4989 *
4990 * Gets PHY address for current port
4991 **/
4992u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4993{
4994 u8 port_num = hw->func_caps.mdio_port_num;
4995 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4996
4997 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4998}
4999
5000/**
5001 * i40e_blink_phy_led
5002 * @hw: pointer to the HW structure
5003 * @time: time how long led will blinks in secs
5004 * @interval: gap between LED on and off in msecs
5005 *
5006 * Blinks PHY link LED
5007 **/
5008i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
5009 u32 time, u32 interval)
5010{
5011 i40e_status status = 0;
5012 u32 i;
5013 u16 led_ctl;
5014 u16 gpio_led_port;
5015 u16 led_reg;
5016 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
5017 u8 phy_addr = 0;
5018 u8 port_num;
5019
5020 i = rd32(hw, I40E_PFGEN_PORTNUM);
5021 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5022 phy_addr = i40e_get_phy_address(hw, port_num);
5023
5024 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
5025 led_addr++) {
5026 status = i40e_read_phy_register_clause45(hw,
5027 I40E_PHY_COM_REG_PAGE,
5028 led_addr, phy_addr,
5029 &led_reg);
5030 if (status)
5031 goto phy_blinking_end;
5032 led_ctl = led_reg;
5033 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
5034 led_reg = 0;
5035 status = i40e_write_phy_register_clause45(hw,
5036 I40E_PHY_COM_REG_PAGE,
5037 led_addr, phy_addr,
5038 led_reg);
5039 if (status)
5040 goto phy_blinking_end;
5041 break;
5042 }
5043 }
5044
5045 if (time > 0 && interval > 0) {
5046 for (i = 0; i < time * 1000; i += interval) {
5047 status = i40e_read_phy_register_clause45(hw,
5048 I40E_PHY_COM_REG_PAGE,
5049 led_addr, phy_addr, &led_reg);
5050 if (status)
5051 goto restore_config;
5052 if (led_reg & I40E_PHY_LED_MANUAL_ON)
5053 led_reg = 0;
5054 else
5055 led_reg = I40E_PHY_LED_MANUAL_ON;
5056 status = i40e_write_phy_register_clause45(hw,
5057 I40E_PHY_COM_REG_PAGE,
5058 led_addr, phy_addr, led_reg);
5059 if (status)
5060 goto restore_config;
5061 msleep(interval);
5062 }
5063 }
5064
5065restore_config:
5066 status = i40e_write_phy_register_clause45(hw,
5067 I40E_PHY_COM_REG_PAGE,
5068 led_addr, phy_addr, led_ctl);
5069
5070phy_blinking_end:
5071 return status;
5072}
5073
5074/**
5075 * i40e_led_get_reg - read LED register
5076 * @hw: pointer to the HW structure
5077 * @led_addr: LED register address
5078 * @reg_val: read register value
5079 **/
5080static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
5081 u32 *reg_val)
5082{
5083 enum i40e_status_code status;
5084 u8 phy_addr = 0;
5085 u8 port_num;
5086 u32 i;
5087
5088 *reg_val = 0;
5089 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5090 status =
5091 i40e_aq_get_phy_register(hw,
5092 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5093 I40E_PHY_COM_REG_PAGE, true,
5094 I40E_PHY_LED_PROV_REG_1,
5095 reg_val, NULL);
5096 } else {
5097 i = rd32(hw, I40E_PFGEN_PORTNUM);
5098 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5099 phy_addr = i40e_get_phy_address(hw, port_num);
5100 status = i40e_read_phy_register_clause45(hw,
5101 I40E_PHY_COM_REG_PAGE,
5102 led_addr, phy_addr,
5103 (u16 *)reg_val);
5104 }
5105 return status;
5106}
5107
5108/**
5109 * i40e_led_set_reg - write LED register
5110 * @hw: pointer to the HW structure
5111 * @led_addr: LED register address
5112 * @reg_val: register value to write
5113 **/
5114static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
5115 u32 reg_val)
5116{
5117 enum i40e_status_code status;
5118 u8 phy_addr = 0;
5119 u8 port_num;
5120 u32 i;
5121
5122 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5123 status =
5124 i40e_aq_set_phy_register(hw,
5125 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5126 I40E_PHY_COM_REG_PAGE, true,
5127 I40E_PHY_LED_PROV_REG_1,
5128 reg_val, NULL);
5129 } else {
5130 i = rd32(hw, I40E_PFGEN_PORTNUM);
5131 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5132 phy_addr = i40e_get_phy_address(hw, port_num);
5133 status = i40e_write_phy_register_clause45(hw,
5134 I40E_PHY_COM_REG_PAGE,
5135 led_addr, phy_addr,
5136 (u16)reg_val);
5137 }
5138
5139 return status;
5140}
5141
5142/**
5143 * i40e_led_get_phy - return current on/off mode
5144 * @hw: pointer to the hw struct
5145 * @led_addr: address of led register to use
5146 * @val: original value of register to use
5147 *
5148 **/
5149i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
5150 u16 *val)
5151{
5152 i40e_status status = 0;
5153 u16 gpio_led_port;
5154 u8 phy_addr = 0;
5155 u16 reg_val;
5156 u16 temp_addr;
5157 u8 port_num;
5158 u32 i;
5159 u32 reg_val_aq;
5160
5161 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5162 status =
5163 i40e_aq_get_phy_register(hw,
5164 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5165 I40E_PHY_COM_REG_PAGE, true,
5166 I40E_PHY_LED_PROV_REG_1,
5167 ®_val_aq, NULL);
5168 if (status == I40E_SUCCESS)
5169 *val = (u16)reg_val_aq;
5170 return status;
5171 }
5172 temp_addr = I40E_PHY_LED_PROV_REG_1;
5173 i = rd32(hw, I40E_PFGEN_PORTNUM);
5174 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5175 phy_addr = i40e_get_phy_address(hw, port_num);
5176
5177 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
5178 temp_addr++) {
5179 status = i40e_read_phy_register_clause45(hw,
5180 I40E_PHY_COM_REG_PAGE,
5181 temp_addr, phy_addr,
5182 ®_val);
5183 if (status)
5184 return status;
5185 *val = reg_val;
5186 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
5187 *led_addr = temp_addr;
5188 break;
5189 }
5190 }
5191 return status;
5192}
5193
5194/**
5195 * i40e_led_set_phy
5196 * @hw: pointer to the HW structure
5197 * @on: true or false
5198 * @led_addr: address of led register to use
5199 * @mode: original val plus bit for set or ignore
5200 *
5201 * Set led's on or off when controlled by the PHY
5202 *
5203 **/
5204i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
5205 u16 led_addr, u32 mode)
5206{
5207 i40e_status status = 0;
5208 u32 led_ctl = 0;
5209 u32 led_reg = 0;
5210
5211 status = i40e_led_get_reg(hw, led_addr, &led_reg);
5212 if (status)
5213 return status;
5214 led_ctl = led_reg;
5215 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
5216 led_reg = 0;
5217 status = i40e_led_set_reg(hw, led_addr, led_reg);
5218 if (status)
5219 return status;
5220 }
5221 status = i40e_led_get_reg(hw, led_addr, &led_reg);
5222 if (status)
5223 goto restore_config;
5224 if (on)
5225 led_reg = I40E_PHY_LED_MANUAL_ON;
5226 else
5227 led_reg = 0;
5228
5229 status = i40e_led_set_reg(hw, led_addr, led_reg);
5230 if (status)
5231 goto restore_config;
5232 if (mode & I40E_PHY_LED_MODE_ORIG) {
5233 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
5234 status = i40e_led_set_reg(hw, led_addr, led_ctl);
5235 }
5236 return status;
5237
5238restore_config:
5239 status = i40e_led_set_reg(hw, led_addr, led_ctl);
5240 return status;
5241}
5242
5243/**
5244 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
5245 * @hw: pointer to the hw struct
5246 * @reg_addr: register address
5247 * @reg_val: ptr to register value
5248 * @cmd_details: pointer to command details structure or NULL
5249 *
5250 * Use the firmware to read the Rx control register,
5251 * especially useful if the Rx unit is under heavy pressure
5252 **/
5253i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
5254 u32 reg_addr, u32 *reg_val,
5255 struct i40e_asq_cmd_details *cmd_details)
5256{
5257 struct i40e_aq_desc desc;
5258 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
5259 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
5260 i40e_status status;
5261
5262 if (!reg_val)
5263 return I40E_ERR_PARAM;
5264
5265 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
5266
5267 cmd_resp->address = cpu_to_le32(reg_addr);
5268
5269 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5270
5271 if (status == 0)
5272 *reg_val = le32_to_cpu(cmd_resp->value);
5273
5274 return status;
5275}
5276
5277/**
5278 * i40e_read_rx_ctl - read from an Rx control register
5279 * @hw: pointer to the hw struct
5280 * @reg_addr: register address
5281 **/
5282u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
5283{
5284 i40e_status status = 0;
5285 bool use_register;
5286 int retry = 5;
5287 u32 val = 0;
5288
5289 use_register = (((hw->aq.api_maj_ver == 1) &&
5290 (hw->aq.api_min_ver < 5)) ||
5291 (hw->mac.type == I40E_MAC_X722));
5292 if (!use_register) {
5293do_retry:
5294 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
5295 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5296 usleep_range(1000, 2000);
5297 retry--;
5298 goto do_retry;
5299 }
5300 }
5301
5302 /* if the AQ access failed, try the old-fashioned way */
5303 if (status || use_register)
5304 val = rd32(hw, reg_addr);
5305
5306 return val;
5307}
5308
5309/**
5310 * i40e_aq_rx_ctl_write_register
5311 * @hw: pointer to the hw struct
5312 * @reg_addr: register address
5313 * @reg_val: register value
5314 * @cmd_details: pointer to command details structure or NULL
5315 *
5316 * Use the firmware to write to an Rx control register,
5317 * especially useful if the Rx unit is under heavy pressure
5318 **/
5319i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
5320 u32 reg_addr, u32 reg_val,
5321 struct i40e_asq_cmd_details *cmd_details)
5322{
5323 struct i40e_aq_desc desc;
5324 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
5325 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
5326 i40e_status status;
5327
5328 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
5329
5330 cmd->address = cpu_to_le32(reg_addr);
5331 cmd->value = cpu_to_le32(reg_val);
5332
5333 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5334
5335 return status;
5336}
5337
5338/**
5339 * i40e_write_rx_ctl - write to an Rx control register
5340 * @hw: pointer to the hw struct
5341 * @reg_addr: register address
5342 * @reg_val: register value
5343 **/
5344void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
5345{
5346 i40e_status status = 0;
5347 bool use_register;
5348 int retry = 5;
5349
5350 use_register = (((hw->aq.api_maj_ver == 1) &&
5351 (hw->aq.api_min_ver < 5)) ||
5352 (hw->mac.type == I40E_MAC_X722));
5353 if (!use_register) {
5354do_retry:
5355 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
5356 reg_val, NULL);
5357 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5358 usleep_range(1000, 2000);
5359 retry--;
5360 goto do_retry;
5361 }
5362 }
5363
5364 /* if the AQ access failed, try the old-fashioned way */
5365 if (status || use_register)
5366 wr32(hw, reg_addr, reg_val);
5367}
5368
5369/**
5370 * i40e_mdio_if_number_selection - MDIO I/F number selection
5371 * @hw: pointer to the hw struct
5372 * @set_mdio: use MDIO I/F number specified by mdio_num
5373 * @mdio_num: MDIO I/F number
5374 * @cmd: pointer to PHY Register command structure
5375 **/
5376static void i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio,
5377 u8 mdio_num,
5378 struct i40e_aqc_phy_register_access *cmd)
5379{
5380 if (set_mdio && cmd->phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL) {
5381 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED)
5382 cmd->cmd_flags |=
5383 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER |
5384 ((mdio_num <<
5385 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) &
5386 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK);
5387 else
5388 i40e_debug(hw, I40E_DEBUG_PHY,
5389 "MDIO I/F number selection not supported by current FW version.\n");
5390 }
5391}
5392
5393/**
5394 * i40e_aq_set_phy_register_ext
5395 * @hw: pointer to the hw struct
5396 * @phy_select: select which phy should be accessed
5397 * @dev_addr: PHY device address
5398 * @set_mdio: use MDIO I/F number specified by mdio_num
5399 * @mdio_num: MDIO I/F number
5400 * @reg_addr: PHY register address
5401 * @reg_val: new register value
5402 * @cmd_details: pointer to command details structure or NULL
5403 *
5404 * Write the external PHY register.
5405 * NOTE: In common cases MDIO I/F number should not be changed, thats why you
5406 * may use simple wrapper i40e_aq_set_phy_register.
5407 **/
5408enum i40e_status_code i40e_aq_set_phy_register_ext(struct i40e_hw *hw,
5409 u8 phy_select, u8 dev_addr, bool page_change,
5410 bool set_mdio, u8 mdio_num,
5411 u32 reg_addr, u32 reg_val,
5412 struct i40e_asq_cmd_details *cmd_details)
5413{
5414 struct i40e_aq_desc desc;
5415 struct i40e_aqc_phy_register_access *cmd =
5416 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5417 i40e_status status;
5418
5419 i40e_fill_default_direct_cmd_desc(&desc,
5420 i40e_aqc_opc_set_phy_register);
5421
5422 cmd->phy_interface = phy_select;
5423 cmd->dev_address = dev_addr;
5424 cmd->reg_address = cpu_to_le32(reg_addr);
5425 cmd->reg_value = cpu_to_le32(reg_val);
5426
5427 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
5428
5429 if (!page_change)
5430 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
5431
5432 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5433
5434 return status;
5435}
5436
5437/**
5438 * i40e_aq_get_phy_register_ext
5439 * @hw: pointer to the hw struct
5440 * @phy_select: select which phy should be accessed
5441 * @dev_addr: PHY device address
5442 * @set_mdio: use MDIO I/F number specified by mdio_num
5443 * @mdio_num: MDIO I/F number
5444 * @reg_addr: PHY register address
5445 * @reg_val: read register value
5446 * @cmd_details: pointer to command details structure or NULL
5447 *
5448 * Read the external PHY register.
5449 * NOTE: In common cases MDIO I/F number should not be changed, thats why you
5450 * may use simple wrapper i40e_aq_get_phy_register.
5451 **/
5452enum i40e_status_code i40e_aq_get_phy_register_ext(struct i40e_hw *hw,
5453 u8 phy_select, u8 dev_addr, bool page_change,
5454 bool set_mdio, u8 mdio_num,
5455 u32 reg_addr, u32 *reg_val,
5456 struct i40e_asq_cmd_details *cmd_details)
5457{
5458 struct i40e_aq_desc desc;
5459 struct i40e_aqc_phy_register_access *cmd =
5460 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5461 i40e_status status;
5462
5463 i40e_fill_default_direct_cmd_desc(&desc,
5464 i40e_aqc_opc_get_phy_register);
5465
5466 cmd->phy_interface = phy_select;
5467 cmd->dev_address = dev_addr;
5468 cmd->reg_address = cpu_to_le32(reg_addr);
5469
5470 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
5471
5472 if (!page_change)
5473 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
5474
5475 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5476 if (!status)
5477 *reg_val = le32_to_cpu(cmd->reg_value);
5478
5479 return status;
5480}
5481
5482/**
5483 * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
5484 * @hw: pointer to the hw struct
5485 * @buff: command buffer (size in bytes = buff_size)
5486 * @buff_size: buffer size in bytes
5487 * @track_id: package tracking id
5488 * @error_offset: returns error offset
5489 * @error_info: returns error information
5490 * @cmd_details: pointer to command details structure or NULL
5491 **/
5492enum
5493i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
5494 u16 buff_size, u32 track_id,
5495 u32 *error_offset, u32 *error_info,
5496 struct i40e_asq_cmd_details *cmd_details)
5497{
5498 struct i40e_aq_desc desc;
5499 struct i40e_aqc_write_personalization_profile *cmd =
5500 (struct i40e_aqc_write_personalization_profile *)
5501 &desc.params.raw;
5502 struct i40e_aqc_write_ddp_resp *resp;
5503 i40e_status status;
5504
5505 i40e_fill_default_direct_cmd_desc(&desc,
5506 i40e_aqc_opc_write_personalization_profile);
5507
5508 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
5509 if (buff_size > I40E_AQ_LARGE_BUF)
5510 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5511
5512 desc.datalen = cpu_to_le16(buff_size);
5513
5514 cmd->profile_track_id = cpu_to_le32(track_id);
5515
5516 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5517 if (!status) {
5518 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
5519 if (error_offset)
5520 *error_offset = le32_to_cpu(resp->error_offset);
5521 if (error_info)
5522 *error_info = le32_to_cpu(resp->error_info);
5523 }
5524
5525 return status;
5526}
5527
5528/**
5529 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
5530 * @hw: pointer to the hw struct
5531 * @buff: command buffer (size in bytes = buff_size)
5532 * @buff_size: buffer size in bytes
5533 * @flags: AdminQ command flags
5534 * @cmd_details: pointer to command details structure or NULL
5535 **/
5536enum
5537i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
5538 u16 buff_size, u8 flags,
5539 struct i40e_asq_cmd_details *cmd_details)
5540{
5541 struct i40e_aq_desc desc;
5542 struct i40e_aqc_get_applied_profiles *cmd =
5543 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
5544 i40e_status status;
5545
5546 i40e_fill_default_direct_cmd_desc(&desc,
5547 i40e_aqc_opc_get_personalization_profile_list);
5548
5549 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
5550 if (buff_size > I40E_AQ_LARGE_BUF)
5551 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5552 desc.datalen = cpu_to_le16(buff_size);
5553
5554 cmd->flags = flags;
5555
5556 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5557
5558 return status;
5559}
5560
5561/**
5562 * i40e_find_segment_in_package
5563 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
5564 * @pkg_hdr: pointer to the package header to be searched
5565 *
5566 * This function searches a package file for a particular segment type. On
5567 * success it returns a pointer to the segment header, otherwise it will
5568 * return NULL.
5569 **/
5570struct i40e_generic_seg_header *
5571i40e_find_segment_in_package(u32 segment_type,
5572 struct i40e_package_header *pkg_hdr)
5573{
5574 struct i40e_generic_seg_header *segment;
5575 u32 i;
5576
5577 /* Search all package segments for the requested segment type */
5578 for (i = 0; i < pkg_hdr->segment_count; i++) {
5579 segment =
5580 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
5581 pkg_hdr->segment_offset[i]);
5582
5583 if (segment->type == segment_type)
5584 return segment;
5585 }
5586
5587 return NULL;
5588}
5589
5590/* Get section table in profile */
5591#define I40E_SECTION_TABLE(profile, sec_tbl) \
5592 do { \
5593 struct i40e_profile_segment *p = (profile); \
5594 u32 count; \
5595 u32 *nvm; \
5596 count = p->device_table_count; \
5597 nvm = (u32 *)&p->device_table[count]; \
5598 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
5599 } while (0)
5600
5601/* Get section header in profile */
5602#define I40E_SECTION_HEADER(profile, offset) \
5603 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
5604
5605/**
5606 * i40e_find_section_in_profile
5607 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
5608 * @profile: pointer to the i40e segment header to be searched
5609 *
5610 * This function searches i40e segment for a particular section type. On
5611 * success it returns a pointer to the section header, otherwise it will
5612 * return NULL.
5613 **/
5614struct i40e_profile_section_header *
5615i40e_find_section_in_profile(u32 section_type,
5616 struct i40e_profile_segment *profile)
5617{
5618 struct i40e_profile_section_header *sec;
5619 struct i40e_section_table *sec_tbl;
5620 u32 sec_off;
5621 u32 i;
5622
5623 if (profile->header.type != SEGMENT_TYPE_I40E)
5624 return NULL;
5625
5626 I40E_SECTION_TABLE(profile, sec_tbl);
5627
5628 for (i = 0; i < sec_tbl->section_count; i++) {
5629 sec_off = sec_tbl->section_offset[i];
5630 sec = I40E_SECTION_HEADER(profile, sec_off);
5631 if (sec->section.type == section_type)
5632 return sec;
5633 }
5634
5635 return NULL;
5636}
5637
5638/**
5639 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
5640 * @hw: pointer to the hw struct
5641 * @aq: command buffer containing all data to execute AQ
5642 **/
5643static enum
5644i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
5645 struct i40e_profile_aq_section *aq)
5646{
5647 i40e_status status;
5648 struct i40e_aq_desc desc;
5649 u8 *msg = NULL;
5650 u16 msglen;
5651
5652 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
5653 desc.flags |= cpu_to_le16(aq->flags);
5654 memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw));
5655
5656 msglen = aq->datalen;
5657 if (msglen) {
5658 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
5659 I40E_AQ_FLAG_RD));
5660 if (msglen > I40E_AQ_LARGE_BUF)
5661 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5662 desc.datalen = cpu_to_le16(msglen);
5663 msg = &aq->data[0];
5664 }
5665
5666 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
5667
5668 if (status) {
5669 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5670 "unable to exec DDP AQ opcode %u, error %d\n",
5671 aq->opcode, status);
5672 return status;
5673 }
5674
5675 /* copy returned desc to aq_buf */
5676 memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw));
5677
5678 return 0;
5679}
5680
5681/**
5682 * i40e_validate_profile
5683 * @hw: pointer to the hardware structure
5684 * @profile: pointer to the profile segment of the package to be validated
5685 * @track_id: package tracking id
5686 * @rollback: flag if the profile is for rollback.
5687 *
5688 * Validates supported devices and profile's sections.
5689 */
5690static enum i40e_status_code
5691i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5692 u32 track_id, bool rollback)
5693{
5694 struct i40e_profile_section_header *sec = NULL;
5695 i40e_status status = 0;
5696 struct i40e_section_table *sec_tbl;
5697 u32 vendor_dev_id;
5698 u32 dev_cnt;
5699 u32 sec_off;
5700 u32 i;
5701
5702 if (track_id == I40E_DDP_TRACKID_INVALID) {
5703 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
5704 return I40E_NOT_SUPPORTED;
5705 }
5706
5707 dev_cnt = profile->device_table_count;
5708 for (i = 0; i < dev_cnt; i++) {
5709 vendor_dev_id = profile->device_table[i].vendor_dev_id;
5710 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL &&
5711 hw->device_id == (vendor_dev_id & 0xFFFF))
5712 break;
5713 }
5714 if (dev_cnt && i == dev_cnt) {
5715 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5716 "Device doesn't support DDP\n");
5717 return I40E_ERR_DEVICE_NOT_SUPPORTED;
5718 }
5719
5720 I40E_SECTION_TABLE(profile, sec_tbl);
5721
5722 /* Validate sections types */
5723 for (i = 0; i < sec_tbl->section_count; i++) {
5724 sec_off = sec_tbl->section_offset[i];
5725 sec = I40E_SECTION_HEADER(profile, sec_off);
5726 if (rollback) {
5727 if (sec->section.type == SECTION_TYPE_MMIO ||
5728 sec->section.type == SECTION_TYPE_AQ ||
5729 sec->section.type == SECTION_TYPE_RB_AQ) {
5730 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5731 "Not a roll-back package\n");
5732 return I40E_NOT_SUPPORTED;
5733 }
5734 } else {
5735 if (sec->section.type == SECTION_TYPE_RB_AQ ||
5736 sec->section.type == SECTION_TYPE_RB_MMIO) {
5737 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5738 "Not an original package\n");
5739 return I40E_NOT_SUPPORTED;
5740 }
5741 }
5742 }
5743
5744 return status;
5745}
5746
5747/**
5748 * i40e_write_profile
5749 * @hw: pointer to the hardware structure
5750 * @profile: pointer to the profile segment of the package to be downloaded
5751 * @track_id: package tracking id
5752 *
5753 * Handles the download of a complete package.
5754 */
5755enum i40e_status_code
5756i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5757 u32 track_id)
5758{
5759 i40e_status status = 0;
5760 struct i40e_section_table *sec_tbl;
5761 struct i40e_profile_section_header *sec = NULL;
5762 struct i40e_profile_aq_section *ddp_aq;
5763 u32 section_size = 0;
5764 u32 offset = 0, info = 0;
5765 u32 sec_off;
5766 u32 i;
5767
5768 status = i40e_validate_profile(hw, profile, track_id, false);
5769 if (status)
5770 return status;
5771
5772 I40E_SECTION_TABLE(profile, sec_tbl);
5773
5774 for (i = 0; i < sec_tbl->section_count; i++) {
5775 sec_off = sec_tbl->section_offset[i];
5776 sec = I40E_SECTION_HEADER(profile, sec_off);
5777 /* Process generic admin command */
5778 if (sec->section.type == SECTION_TYPE_AQ) {
5779 ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
5780 status = i40e_ddp_exec_aq_section(hw, ddp_aq);
5781 if (status) {
5782 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5783 "Failed to execute aq: section %d, opcode %u\n",
5784 i, ddp_aq->opcode);
5785 break;
5786 }
5787 sec->section.type = SECTION_TYPE_RB_AQ;
5788 }
5789
5790 /* Skip any non-mmio sections */
5791 if (sec->section.type != SECTION_TYPE_MMIO)
5792 continue;
5793
5794 section_size = sec->section.size +
5795 sizeof(struct i40e_profile_section_header);
5796
5797 /* Write MMIO section */
5798 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
5799 track_id, &offset, &info, NULL);
5800 if (status) {
5801 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5802 "Failed to write profile: section %d, offset %d, info %d\n",
5803 i, offset, info);
5804 break;
5805 }
5806 }
5807 return status;
5808}
5809
5810/**
5811 * i40e_rollback_profile
5812 * @hw: pointer to the hardware structure
5813 * @profile: pointer to the profile segment of the package to be removed
5814 * @track_id: package tracking id
5815 *
5816 * Rolls back previously loaded package.
5817 */
5818enum i40e_status_code
5819i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5820 u32 track_id)
5821{
5822 struct i40e_profile_section_header *sec = NULL;
5823 i40e_status status = 0;
5824 struct i40e_section_table *sec_tbl;
5825 u32 offset = 0, info = 0;
5826 u32 section_size = 0;
5827 u32 sec_off;
5828 int i;
5829
5830 status = i40e_validate_profile(hw, profile, track_id, true);
5831 if (status)
5832 return status;
5833
5834 I40E_SECTION_TABLE(profile, sec_tbl);
5835
5836 /* For rollback write sections in reverse */
5837 for (i = sec_tbl->section_count - 1; i >= 0; i--) {
5838 sec_off = sec_tbl->section_offset[i];
5839 sec = I40E_SECTION_HEADER(profile, sec_off);
5840
5841 /* Skip any non-rollback sections */
5842 if (sec->section.type != SECTION_TYPE_RB_MMIO)
5843 continue;
5844
5845 section_size = sec->section.size +
5846 sizeof(struct i40e_profile_section_header);
5847
5848 /* Write roll-back MMIO section */
5849 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
5850 track_id, &offset, &info, NULL);
5851 if (status) {
5852 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5853 "Failed to write profile: section %d, offset %d, info %d\n",
5854 i, offset, info);
5855 break;
5856 }
5857 }
5858 return status;
5859}
5860
5861/**
5862 * i40e_add_pinfo_to_list
5863 * @hw: pointer to the hardware structure
5864 * @profile: pointer to the profile segment of the package
5865 * @profile_info_sec: buffer for information section
5866 * @track_id: package tracking id
5867 *
5868 * Register a profile to the list of loaded profiles.
5869 */
5870enum i40e_status_code
5871i40e_add_pinfo_to_list(struct i40e_hw *hw,
5872 struct i40e_profile_segment *profile,
5873 u8 *profile_info_sec, u32 track_id)
5874{
5875 i40e_status status = 0;
5876 struct i40e_profile_section_header *sec = NULL;
5877 struct i40e_profile_info *pinfo;
5878 u32 offset = 0, info = 0;
5879
5880 sec = (struct i40e_profile_section_header *)profile_info_sec;
5881 sec->tbl_size = 1;
5882 sec->data_end = sizeof(struct i40e_profile_section_header) +
5883 sizeof(struct i40e_profile_info);
5884 sec->section.type = SECTION_TYPE_INFO;
5885 sec->section.offset = sizeof(struct i40e_profile_section_header);
5886 sec->section.size = sizeof(struct i40e_profile_info);
5887 pinfo = (struct i40e_profile_info *)(profile_info_sec +
5888 sec->section.offset);
5889 pinfo->track_id = track_id;
5890 pinfo->version = profile->version;
5891 pinfo->op = I40E_DDP_ADD_TRACKID;
5892 memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
5893
5894 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
5895 track_id, &offset, &info, NULL);
5896
5897 return status;
5898}
5899
5900/**
5901 * i40e_aq_add_cloud_filters
5902 * @hw: pointer to the hardware structure
5903 * @seid: VSI seid to add cloud filters from
5904 * @filters: Buffer which contains the filters to be added
5905 * @filter_count: number of filters contained in the buffer
5906 *
5907 * Set the cloud filters for a given VSI. The contents of the
5908 * i40e_aqc_cloud_filters_element_data are filled in by the caller
5909 * of the function.
5910 *
5911 **/
5912enum i40e_status_code
5913i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid,
5914 struct i40e_aqc_cloud_filters_element_data *filters,
5915 u8 filter_count)
5916{
5917 struct i40e_aq_desc desc;
5918 struct i40e_aqc_add_remove_cloud_filters *cmd =
5919 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5920 enum i40e_status_code status;
5921 u16 buff_len;
5922
5923 i40e_fill_default_direct_cmd_desc(&desc,
5924 i40e_aqc_opc_add_cloud_filters);
5925
5926 buff_len = filter_count * sizeof(*filters);
5927 desc.datalen = cpu_to_le16(buff_len);
5928 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5929 cmd->num_filters = filter_count;
5930 cmd->seid = cpu_to_le16(seid);
5931
5932 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5933
5934 return status;
5935}
5936
5937/**
5938 * i40e_aq_add_cloud_filters_bb
5939 * @hw: pointer to the hardware structure
5940 * @seid: VSI seid to add cloud filters from
5941 * @filters: Buffer which contains the filters in big buffer to be added
5942 * @filter_count: number of filters contained in the buffer
5943 *
5944 * Set the big buffer cloud filters for a given VSI. The contents of the
5945 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5946 * function.
5947 *
5948 **/
5949enum i40e_status_code
5950i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5951 struct i40e_aqc_cloud_filters_element_bb *filters,
5952 u8 filter_count)
5953{
5954 struct i40e_aq_desc desc;
5955 struct i40e_aqc_add_remove_cloud_filters *cmd =
5956 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5957 i40e_status status;
5958 u16 buff_len;
5959 int i;
5960
5961 i40e_fill_default_direct_cmd_desc(&desc,
5962 i40e_aqc_opc_add_cloud_filters);
5963
5964 buff_len = filter_count * sizeof(*filters);
5965 desc.datalen = cpu_to_le16(buff_len);
5966 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5967 cmd->num_filters = filter_count;
5968 cmd->seid = cpu_to_le16(seid);
5969 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5970
5971 for (i = 0; i < filter_count; i++) {
5972 u16 tnl_type;
5973 u32 ti;
5974
5975 tnl_type = (le16_to_cpu(filters[i].element.flags) &
5976 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5977 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5978
5979 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5980 * one more byte further than normally used for Tenant ID in
5981 * other tunnel types.
5982 */
5983 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5984 ti = le32_to_cpu(filters[i].element.tenant_id);
5985 filters[i].element.tenant_id = cpu_to_le32(ti << 8);
5986 }
5987 }
5988
5989 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5990
5991 return status;
5992}
5993
5994/**
5995 * i40e_aq_rem_cloud_filters
5996 * @hw: pointer to the hardware structure
5997 * @seid: VSI seid to remove cloud filters from
5998 * @filters: Buffer which contains the filters to be removed
5999 * @filter_count: number of filters contained in the buffer
6000 *
6001 * Remove the cloud filters for a given VSI. The contents of the
6002 * i40e_aqc_cloud_filters_element_data are filled in by the caller
6003 * of the function.
6004 *
6005 **/
6006enum i40e_status_code
6007i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
6008 struct i40e_aqc_cloud_filters_element_data *filters,
6009 u8 filter_count)
6010{
6011 struct i40e_aq_desc desc;
6012 struct i40e_aqc_add_remove_cloud_filters *cmd =
6013 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
6014 enum i40e_status_code status;
6015 u16 buff_len;
6016
6017 i40e_fill_default_direct_cmd_desc(&desc,
6018 i40e_aqc_opc_remove_cloud_filters);
6019
6020 buff_len = filter_count * sizeof(*filters);
6021 desc.datalen = cpu_to_le16(buff_len);
6022 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6023 cmd->num_filters = filter_count;
6024 cmd->seid = cpu_to_le16(seid);
6025
6026 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
6027
6028 return status;
6029}
6030
6031/**
6032 * i40e_aq_rem_cloud_filters_bb
6033 * @hw: pointer to the hardware structure
6034 * @seid: VSI seid to remove cloud filters from
6035 * @filters: Buffer which contains the filters in big buffer to be removed
6036 * @filter_count: number of filters contained in the buffer
6037 *
6038 * Remove the big buffer cloud filters for a given VSI. The contents of the
6039 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
6040 * function.
6041 *
6042 **/
6043enum i40e_status_code
6044i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
6045 struct i40e_aqc_cloud_filters_element_bb *filters,
6046 u8 filter_count)
6047{
6048 struct i40e_aq_desc desc;
6049 struct i40e_aqc_add_remove_cloud_filters *cmd =
6050 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
6051 i40e_status status;
6052 u16 buff_len;
6053 int i;
6054
6055 i40e_fill_default_direct_cmd_desc(&desc,
6056 i40e_aqc_opc_remove_cloud_filters);
6057
6058 buff_len = filter_count * sizeof(*filters);
6059 desc.datalen = cpu_to_le16(buff_len);
6060 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6061 cmd->num_filters = filter_count;
6062 cmd->seid = cpu_to_le16(seid);
6063 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
6064
6065 for (i = 0; i < filter_count; i++) {
6066 u16 tnl_type;
6067 u32 ti;
6068
6069 tnl_type = (le16_to_cpu(filters[i].element.flags) &
6070 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
6071 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
6072
6073 /* Due to hardware eccentricities, the VNI for Geneve is shifted
6074 * one more byte further than normally used for Tenant ID in
6075 * other tunnel types.
6076 */
6077 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
6078 ti = le32_to_cpu(filters[i].element.tenant_id);
6079 filters[i].element.tenant_id = cpu_to_le32(ti << 8);
6080 }
6081 }
6082
6083 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
6084
6085 return status;
6086}