Loading...
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2013 - 2021 Intel Corporation. */
3
4#include <linux/avf/virtchnl.h>
5#include <linux/bitfield.h>
6#include <linux/delay.h>
7#include <linux/etherdevice.h>
8#include <linux/pci.h>
9#include "i40e_adminq_cmd.h"
10#include "i40e_devids.h"
11#include "i40e_prototype.h"
12#include "i40e_register.h"
13
14/**
15 * i40e_set_mac_type - Sets MAC type
16 * @hw: pointer to the HW structure
17 *
18 * This function sets the mac type of the adapter based on the
19 * vendor ID and device ID stored in the hw structure.
20 **/
21int i40e_set_mac_type(struct i40e_hw *hw)
22{
23 int status = 0;
24
25 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
26 switch (hw->device_id) {
27 case I40E_DEV_ID_SFP_XL710:
28 case I40E_DEV_ID_QEMU:
29 case I40E_DEV_ID_KX_B:
30 case I40E_DEV_ID_KX_C:
31 case I40E_DEV_ID_QSFP_A:
32 case I40E_DEV_ID_QSFP_B:
33 case I40E_DEV_ID_QSFP_C:
34 case I40E_DEV_ID_1G_BASE_T_BC:
35 case I40E_DEV_ID_5G_BASE_T_BC:
36 case I40E_DEV_ID_10G_BASE_T:
37 case I40E_DEV_ID_10G_BASE_T4:
38 case I40E_DEV_ID_10G_BASE_T_BC:
39 case I40E_DEV_ID_10G_B:
40 case I40E_DEV_ID_10G_SFP:
41 case I40E_DEV_ID_20G_KR2:
42 case I40E_DEV_ID_20G_KR2_A:
43 case I40E_DEV_ID_25G_B:
44 case I40E_DEV_ID_25G_SFP28:
45 case I40E_DEV_ID_X710_N3000:
46 case I40E_DEV_ID_XXV710_N3000:
47 hw->mac.type = I40E_MAC_XL710;
48 break;
49 case I40E_DEV_ID_KX_X722:
50 case I40E_DEV_ID_QSFP_X722:
51 case I40E_DEV_ID_SFP_X722:
52 case I40E_DEV_ID_1G_BASE_T_X722:
53 case I40E_DEV_ID_10G_BASE_T_X722:
54 case I40E_DEV_ID_SFP_I_X722:
55 case I40E_DEV_ID_SFP_X722_A:
56 hw->mac.type = I40E_MAC_X722;
57 break;
58 default:
59 hw->mac.type = I40E_MAC_GENERIC;
60 break;
61 }
62 } else {
63 status = -ENODEV;
64 }
65
66 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
67 hw->mac.type, status);
68 return status;
69}
70
71/**
72 * i40e_aq_str - convert AQ err code to a string
73 * @hw: pointer to the HW structure
74 * @aq_err: the AQ error code to convert
75 **/
76const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
77{
78 switch (aq_err) {
79 case I40E_AQ_RC_OK:
80 return "OK";
81 case I40E_AQ_RC_EPERM:
82 return "I40E_AQ_RC_EPERM";
83 case I40E_AQ_RC_ENOENT:
84 return "I40E_AQ_RC_ENOENT";
85 case I40E_AQ_RC_ESRCH:
86 return "I40E_AQ_RC_ESRCH";
87 case I40E_AQ_RC_EINTR:
88 return "I40E_AQ_RC_EINTR";
89 case I40E_AQ_RC_EIO:
90 return "I40E_AQ_RC_EIO";
91 case I40E_AQ_RC_ENXIO:
92 return "I40E_AQ_RC_ENXIO";
93 case I40E_AQ_RC_E2BIG:
94 return "I40E_AQ_RC_E2BIG";
95 case I40E_AQ_RC_EAGAIN:
96 return "I40E_AQ_RC_EAGAIN";
97 case I40E_AQ_RC_ENOMEM:
98 return "I40E_AQ_RC_ENOMEM";
99 case I40E_AQ_RC_EACCES:
100 return "I40E_AQ_RC_EACCES";
101 case I40E_AQ_RC_EFAULT:
102 return "I40E_AQ_RC_EFAULT";
103 case I40E_AQ_RC_EBUSY:
104 return "I40E_AQ_RC_EBUSY";
105 case I40E_AQ_RC_EEXIST:
106 return "I40E_AQ_RC_EEXIST";
107 case I40E_AQ_RC_EINVAL:
108 return "I40E_AQ_RC_EINVAL";
109 case I40E_AQ_RC_ENOTTY:
110 return "I40E_AQ_RC_ENOTTY";
111 case I40E_AQ_RC_ENOSPC:
112 return "I40E_AQ_RC_ENOSPC";
113 case I40E_AQ_RC_ENOSYS:
114 return "I40E_AQ_RC_ENOSYS";
115 case I40E_AQ_RC_ERANGE:
116 return "I40E_AQ_RC_ERANGE";
117 case I40E_AQ_RC_EFLUSHED:
118 return "I40E_AQ_RC_EFLUSHED";
119 case I40E_AQ_RC_BAD_ADDR:
120 return "I40E_AQ_RC_BAD_ADDR";
121 case I40E_AQ_RC_EMODE:
122 return "I40E_AQ_RC_EMODE";
123 case I40E_AQ_RC_EFBIG:
124 return "I40E_AQ_RC_EFBIG";
125 }
126
127 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
128 return hw->err_str;
129}
130
131/**
132 * i40e_debug_aq
133 * @hw: debug mask related to admin queue
134 * @mask: debug mask
135 * @desc: pointer to admin queue descriptor
136 * @buffer: pointer to command buffer
137 * @buf_len: max length of buffer
138 *
139 * Dumps debug log about adminq command with descriptor contents.
140 **/
141void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
142 void *buffer, u16 buf_len)
143{
144 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
145 u32 effective_mask = hw->debug_mask & mask;
146 char prefix[27];
147 u16 len;
148 u8 *buf = (u8 *)buffer;
149
150 if (!effective_mask || !desc)
151 return;
152
153 len = le16_to_cpu(aq_desc->datalen);
154
155 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
156 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
157 le16_to_cpu(aq_desc->opcode),
158 le16_to_cpu(aq_desc->flags),
159 le16_to_cpu(aq_desc->datalen),
160 le16_to_cpu(aq_desc->retval));
161 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
162 "\tcookie (h,l) 0x%08X 0x%08X\n",
163 le32_to_cpu(aq_desc->cookie_high),
164 le32_to_cpu(aq_desc->cookie_low));
165 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
166 "\tparam (0,1) 0x%08X 0x%08X\n",
167 le32_to_cpu(aq_desc->params.internal.param0),
168 le32_to_cpu(aq_desc->params.internal.param1));
169 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
170 "\taddr (h,l) 0x%08X 0x%08X\n",
171 le32_to_cpu(aq_desc->params.external.addr_high),
172 le32_to_cpu(aq_desc->params.external.addr_low));
173
174 if (buffer && buf_len != 0 && len != 0 &&
175 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) {
176 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
177 if (buf_len < len)
178 len = buf_len;
179
180 snprintf(prefix, sizeof(prefix),
181 "i40e %02x:%02x.%x: \t0x",
182 hw->bus.bus_id,
183 hw->bus.device,
184 hw->bus.func);
185
186 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET,
187 16, 1, buf, len, false);
188 }
189}
190
191/**
192 * i40e_check_asq_alive
193 * @hw: pointer to the hw struct
194 *
195 * Returns true if Queue is enabled else false.
196 **/
197bool i40e_check_asq_alive(struct i40e_hw *hw)
198{
199 /* Check if the queue is initialized */
200 if (!hw->aq.asq.count)
201 return false;
202
203 return !!(rd32(hw, I40E_PF_ATQLEN) & I40E_PF_ATQLEN_ATQENABLE_MASK);
204}
205
206/**
207 * i40e_aq_queue_shutdown
208 * @hw: pointer to the hw struct
209 * @unloading: is the driver unloading itself
210 *
211 * Tell the Firmware that we're shutting down the AdminQ and whether
212 * or not the driver is unloading as well.
213 **/
214int i40e_aq_queue_shutdown(struct i40e_hw *hw,
215 bool unloading)
216{
217 struct i40e_aq_desc desc;
218 struct i40e_aqc_queue_shutdown *cmd =
219 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
220 int status;
221
222 i40e_fill_default_direct_cmd_desc(&desc,
223 i40e_aqc_opc_queue_shutdown);
224
225 if (unloading)
226 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
227 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
228
229 return status;
230}
231
232/**
233 * i40e_aq_get_set_rss_lut
234 * @hw: pointer to the hardware structure
235 * @vsi_id: vsi fw index
236 * @pf_lut: for PF table set true, for VSI table set false
237 * @lut: pointer to the lut buffer provided by the caller
238 * @lut_size: size of the lut buffer
239 * @set: set true to set the table, false to get the table
240 *
241 * Internal function to get or set RSS look up table
242 **/
243static int i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
244 u16 vsi_id, bool pf_lut,
245 u8 *lut, u16 lut_size,
246 bool set)
247{
248 struct i40e_aq_desc desc;
249 struct i40e_aqc_get_set_rss_lut *cmd_resp =
250 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
251 int status;
252 u16 flags;
253
254 if (set)
255 i40e_fill_default_direct_cmd_desc(&desc,
256 i40e_aqc_opc_set_rss_lut);
257 else
258 i40e_fill_default_direct_cmd_desc(&desc,
259 i40e_aqc_opc_get_rss_lut);
260
261 /* Indirect command */
262 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
263 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
264
265 vsi_id = FIELD_PREP(I40E_AQC_SET_RSS_LUT_VSI_ID_MASK, vsi_id) |
266 FIELD_PREP(I40E_AQC_SET_RSS_LUT_VSI_VALID, 1);
267 cmd_resp->vsi_id = cpu_to_le16(vsi_id);
268
269 if (pf_lut)
270 flags = FIELD_PREP(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK,
271 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF);
272 else
273 flags = FIELD_PREP(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK,
274 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI);
275
276 cmd_resp->flags = cpu_to_le16(flags);
277 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
278
279 return status;
280}
281
282/**
283 * i40e_aq_get_rss_lut
284 * @hw: pointer to the hardware structure
285 * @vsi_id: vsi fw index
286 * @pf_lut: for PF table set true, for VSI table set false
287 * @lut: pointer to the lut buffer provided by the caller
288 * @lut_size: size of the lut buffer
289 *
290 * get the RSS lookup table, PF or VSI type
291 **/
292int i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
293 bool pf_lut, u8 *lut, u16 lut_size)
294{
295 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
296 false);
297}
298
299/**
300 * i40e_aq_set_rss_lut
301 * @hw: pointer to the hardware structure
302 * @vsi_id: vsi fw index
303 * @pf_lut: for PF table set true, for VSI table set false
304 * @lut: pointer to the lut buffer provided by the caller
305 * @lut_size: size of the lut buffer
306 *
307 * set the RSS lookup table, PF or VSI type
308 **/
309int i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
310 bool pf_lut, u8 *lut, u16 lut_size)
311{
312 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
313}
314
315/**
316 * i40e_aq_get_set_rss_key
317 * @hw: pointer to the hw struct
318 * @vsi_id: vsi fw index
319 * @key: pointer to key info struct
320 * @set: set true to set the key, false to get the key
321 *
322 * get the RSS key per VSI
323 **/
324static int i40e_aq_get_set_rss_key(struct i40e_hw *hw,
325 u16 vsi_id,
326 struct i40e_aqc_get_set_rss_key_data *key,
327 bool set)
328{
329 struct i40e_aq_desc desc;
330 struct i40e_aqc_get_set_rss_key *cmd_resp =
331 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
332 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
333 int status;
334
335 if (set)
336 i40e_fill_default_direct_cmd_desc(&desc,
337 i40e_aqc_opc_set_rss_key);
338 else
339 i40e_fill_default_direct_cmd_desc(&desc,
340 i40e_aqc_opc_get_rss_key);
341
342 /* Indirect command */
343 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
344 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
345
346 vsi_id = FIELD_PREP(I40E_AQC_SET_RSS_KEY_VSI_ID_MASK, vsi_id) |
347 FIELD_PREP(I40E_AQC_SET_RSS_KEY_VSI_VALID, 1);
348 cmd_resp->vsi_id = cpu_to_le16(vsi_id);
349
350 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
351
352 return status;
353}
354
355/**
356 * i40e_aq_get_rss_key
357 * @hw: pointer to the hw struct
358 * @vsi_id: vsi fw index
359 * @key: pointer to key info struct
360 *
361 **/
362int i40e_aq_get_rss_key(struct i40e_hw *hw,
363 u16 vsi_id,
364 struct i40e_aqc_get_set_rss_key_data *key)
365{
366 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
367}
368
369/**
370 * i40e_aq_set_rss_key
371 * @hw: pointer to the hw struct
372 * @vsi_id: vsi fw index
373 * @key: pointer to key info struct
374 *
375 * set the RSS key per VSI
376 **/
377int i40e_aq_set_rss_key(struct i40e_hw *hw,
378 u16 vsi_id,
379 struct i40e_aqc_get_set_rss_key_data *key)
380{
381 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
382}
383
384/**
385 * i40e_init_shared_code - Initialize the shared code
386 * @hw: pointer to hardware structure
387 *
388 * This assigns the MAC type and PHY code and inits the NVM.
389 * Does not touch the hardware. This function must be called prior to any
390 * other function in the shared code. The i40e_hw structure should be
391 * memset to 0 prior to calling this function. The following fields in
392 * hw structure should be filled in prior to calling this function:
393 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
394 * subsystem_vendor_id, and revision_id
395 **/
396int i40e_init_shared_code(struct i40e_hw *hw)
397{
398 u32 port, ari, func_rid;
399 int status = 0;
400
401 i40e_set_mac_type(hw);
402
403 switch (hw->mac.type) {
404 case I40E_MAC_XL710:
405 case I40E_MAC_X722:
406 break;
407 default:
408 return -ENODEV;
409 }
410
411 hw->phy.get_link_info = true;
412
413 /* Determine port number and PF number*/
414 port = FIELD_GET(I40E_PFGEN_PORTNUM_PORT_NUM_MASK,
415 rd32(hw, I40E_PFGEN_PORTNUM));
416 hw->port = (u8)port;
417 ari = FIELD_GET(I40E_GLPCI_CAPSUP_ARI_EN_MASK,
418 rd32(hw, I40E_GLPCI_CAPSUP));
419 func_rid = rd32(hw, I40E_PF_FUNC_RID);
420 if (ari)
421 hw->pf_id = (u8)(func_rid & 0xff);
422 else
423 hw->pf_id = (u8)(func_rid & 0x7);
424
425 status = i40e_init_nvm(hw);
426 return status;
427}
428
429/**
430 * i40e_aq_mac_address_read - Retrieve the MAC addresses
431 * @hw: pointer to the hw struct
432 * @flags: a return indicator of what addresses were added to the addr store
433 * @addrs: the requestor's mac addr store
434 * @cmd_details: pointer to command details structure or NULL
435 **/
436static int
437i40e_aq_mac_address_read(struct i40e_hw *hw,
438 u16 *flags,
439 struct i40e_aqc_mac_address_read_data *addrs,
440 struct i40e_asq_cmd_details *cmd_details)
441{
442 struct i40e_aq_desc desc;
443 struct i40e_aqc_mac_address_read *cmd_data =
444 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
445 int status;
446
447 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
448 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
449
450 status = i40e_asq_send_command(hw, &desc, addrs,
451 sizeof(*addrs), cmd_details);
452 *flags = le16_to_cpu(cmd_data->command_flags);
453
454 return status;
455}
456
457/**
458 * i40e_aq_mac_address_write - Change the MAC addresses
459 * @hw: pointer to the hw struct
460 * @flags: indicates which MAC to be written
461 * @mac_addr: address to write
462 * @cmd_details: pointer to command details structure or NULL
463 **/
464int i40e_aq_mac_address_write(struct i40e_hw *hw,
465 u16 flags, u8 *mac_addr,
466 struct i40e_asq_cmd_details *cmd_details)
467{
468 struct i40e_aq_desc desc;
469 struct i40e_aqc_mac_address_write *cmd_data =
470 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
471 int status;
472
473 i40e_fill_default_direct_cmd_desc(&desc,
474 i40e_aqc_opc_mac_address_write);
475 cmd_data->command_flags = cpu_to_le16(flags);
476 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
477 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
478 ((u32)mac_addr[3] << 16) |
479 ((u32)mac_addr[4] << 8) |
480 mac_addr[5]);
481
482 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
483
484 return status;
485}
486
487/**
488 * i40e_get_mac_addr - get MAC address
489 * @hw: pointer to the HW structure
490 * @mac_addr: pointer to MAC address
491 *
492 * Reads the adapter's MAC address from register
493 **/
494int i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
495{
496 struct i40e_aqc_mac_address_read_data addrs;
497 u16 flags = 0;
498 int status;
499
500 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
501
502 if (flags & I40E_AQC_LAN_ADDR_VALID)
503 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
504
505 return status;
506}
507
508/**
509 * i40e_get_port_mac_addr - get Port MAC address
510 * @hw: pointer to the HW structure
511 * @mac_addr: pointer to Port MAC address
512 *
513 * Reads the adapter's Port MAC address
514 **/
515int i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
516{
517 struct i40e_aqc_mac_address_read_data addrs;
518 u16 flags = 0;
519 int status;
520
521 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
522 if (status)
523 return status;
524
525 if (flags & I40E_AQC_PORT_ADDR_VALID)
526 ether_addr_copy(mac_addr, addrs.port_mac);
527 else
528 status = -EINVAL;
529
530 return status;
531}
532
533/**
534 * i40e_pre_tx_queue_cfg - pre tx queue configure
535 * @hw: pointer to the HW structure
536 * @queue: target PF queue index
537 * @enable: state change request
538 *
539 * Handles hw requirement to indicate intention to enable
540 * or disable target queue.
541 **/
542void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
543{
544 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
545 u32 reg_block = 0;
546 u32 reg_val;
547
548 if (abs_queue_idx >= 128) {
549 reg_block = abs_queue_idx / 128;
550 abs_queue_idx %= 128;
551 }
552
553 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
554 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
555 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
556
557 if (enable)
558 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
559 else
560 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
561
562 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
563}
564
565/**
566 * i40e_get_pba_string - Reads part number string from EEPROM
567 * @hw: pointer to hardware structure
568 *
569 * Reads the part number string from the EEPROM and stores it
570 * into newly allocated buffer and saves resulting pointer
571 * to i40e_hw->pba_id field.
572 **/
573void i40e_get_pba_string(struct i40e_hw *hw)
574{
575#define I40E_NVM_PBA_FLAGS_BLK_PRESENT 0xFAFA
576 u16 pba_word = 0;
577 u16 pba_size = 0;
578 u16 pba_ptr = 0;
579 int status;
580 char *ptr;
581 u16 i;
582
583 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
584 if (status) {
585 hw_dbg(hw, "Failed to read PBA flags.\n");
586 return;
587 }
588 if (pba_word != I40E_NVM_PBA_FLAGS_BLK_PRESENT) {
589 hw_dbg(hw, "PBA block is not present.\n");
590 return;
591 }
592
593 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
594 if (status) {
595 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
596 return;
597 }
598
599 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
600 if (status) {
601 hw_dbg(hw, "Failed to read PBA Block size.\n");
602 return;
603 }
604
605 /* Subtract one to get PBA word count (PBA Size word is included in
606 * total size) and advance pointer to first PBA word.
607 */
608 pba_size--;
609 pba_ptr++;
610 if (!pba_size) {
611 hw_dbg(hw, "PBA ID is empty.\n");
612 return;
613 }
614
615 ptr = devm_kzalloc(i40e_hw_to_dev(hw), pba_size * 2 + 1, GFP_KERNEL);
616 if (!ptr)
617 return;
618 hw->pba_id = ptr;
619
620 for (i = 0; i < pba_size; i++) {
621 status = i40e_read_nvm_word(hw, pba_ptr + i, &pba_word);
622 if (status) {
623 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
624 devm_kfree(i40e_hw_to_dev(hw), hw->pba_id);
625 hw->pba_id = NULL;
626 return;
627 }
628
629 *ptr++ = (pba_word >> 8) & 0xFF;
630 *ptr++ = pba_word & 0xFF;
631 }
632}
633
634/**
635 * i40e_get_media_type - Gets media type
636 * @hw: pointer to the hardware structure
637 **/
638static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
639{
640 enum i40e_media_type media;
641
642 switch (hw->phy.link_info.phy_type) {
643 case I40E_PHY_TYPE_10GBASE_SR:
644 case I40E_PHY_TYPE_10GBASE_LR:
645 case I40E_PHY_TYPE_1000BASE_SX:
646 case I40E_PHY_TYPE_1000BASE_LX:
647 case I40E_PHY_TYPE_40GBASE_SR4:
648 case I40E_PHY_TYPE_40GBASE_LR4:
649 case I40E_PHY_TYPE_25GBASE_LR:
650 case I40E_PHY_TYPE_25GBASE_SR:
651 media = I40E_MEDIA_TYPE_FIBER;
652 break;
653 case I40E_PHY_TYPE_100BASE_TX:
654 case I40E_PHY_TYPE_1000BASE_T:
655 case I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS:
656 case I40E_PHY_TYPE_5GBASE_T_LINK_STATUS:
657 case I40E_PHY_TYPE_10GBASE_T:
658 media = I40E_MEDIA_TYPE_BASET;
659 break;
660 case I40E_PHY_TYPE_10GBASE_CR1_CU:
661 case I40E_PHY_TYPE_40GBASE_CR4_CU:
662 case I40E_PHY_TYPE_10GBASE_CR1:
663 case I40E_PHY_TYPE_40GBASE_CR4:
664 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
665 case I40E_PHY_TYPE_40GBASE_AOC:
666 case I40E_PHY_TYPE_10GBASE_AOC:
667 case I40E_PHY_TYPE_25GBASE_CR:
668 case I40E_PHY_TYPE_25GBASE_AOC:
669 case I40E_PHY_TYPE_25GBASE_ACC:
670 media = I40E_MEDIA_TYPE_DA;
671 break;
672 case I40E_PHY_TYPE_1000BASE_KX:
673 case I40E_PHY_TYPE_10GBASE_KX4:
674 case I40E_PHY_TYPE_10GBASE_KR:
675 case I40E_PHY_TYPE_40GBASE_KR4:
676 case I40E_PHY_TYPE_20GBASE_KR2:
677 case I40E_PHY_TYPE_25GBASE_KR:
678 media = I40E_MEDIA_TYPE_BACKPLANE;
679 break;
680 case I40E_PHY_TYPE_SGMII:
681 case I40E_PHY_TYPE_XAUI:
682 case I40E_PHY_TYPE_XFI:
683 case I40E_PHY_TYPE_XLAUI:
684 case I40E_PHY_TYPE_XLPPI:
685 default:
686 media = I40E_MEDIA_TYPE_UNKNOWN;
687 break;
688 }
689
690 return media;
691}
692
693/**
694 * i40e_poll_globr - Poll for Global Reset completion
695 * @hw: pointer to the hardware structure
696 * @retry_limit: how many times to retry before failure
697 **/
698static int i40e_poll_globr(struct i40e_hw *hw,
699 u32 retry_limit)
700{
701 u32 cnt, reg = 0;
702
703 for (cnt = 0; cnt < retry_limit; cnt++) {
704 reg = rd32(hw, I40E_GLGEN_RSTAT);
705 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
706 return 0;
707 msleep(100);
708 }
709
710 hw_dbg(hw, "Global reset failed.\n");
711 hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg);
712
713 return -EIO;
714}
715
716#define I40E_PF_RESET_WAIT_COUNT_A0 200
717#define I40E_PF_RESET_WAIT_COUNT 200
718/**
719 * i40e_pf_reset - Reset the PF
720 * @hw: pointer to the hardware structure
721 *
722 * Assuming someone else has triggered a global reset,
723 * assure the global reset is complete and then reset the PF
724 **/
725int i40e_pf_reset(struct i40e_hw *hw)
726{
727 u32 cnt = 0;
728 u32 cnt1 = 0;
729 u32 reg = 0;
730 u32 grst_del;
731
732 /* Poll for Global Reset steady state in case of recent GRST.
733 * The grst delay value is in 100ms units, and we'll wait a
734 * couple counts longer to be sure we don't just miss the end.
735 */
736 grst_del = FIELD_GET(I40E_GLGEN_RSTCTL_GRSTDEL_MASK,
737 rd32(hw, I40E_GLGEN_RSTCTL));
738
739 /* It can take upto 15 secs for GRST steady state.
740 * Bump it to 16 secs max to be safe.
741 */
742 grst_del = grst_del * 20;
743
744 for (cnt = 0; cnt < grst_del; cnt++) {
745 reg = rd32(hw, I40E_GLGEN_RSTAT);
746 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
747 break;
748 msleep(100);
749 }
750 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
751 hw_dbg(hw, "Global reset polling failed to complete.\n");
752 return -EIO;
753 }
754
755 /* Now Wait for the FW to be ready */
756 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
757 reg = rd32(hw, I40E_GLNVM_ULD);
758 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
759 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
760 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
761 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
762 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
763 break;
764 }
765 usleep_range(10000, 20000);
766 }
767 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
768 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
769 hw_dbg(hw, "wait for FW Reset complete timedout\n");
770 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
771 return -EIO;
772 }
773
774 /* If there was a Global Reset in progress when we got here,
775 * we don't need to do the PF Reset
776 */
777 if (!cnt) {
778 u32 reg2 = 0;
779 if (hw->revision_id == 0)
780 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
781 else
782 cnt = I40E_PF_RESET_WAIT_COUNT;
783 reg = rd32(hw, I40E_PFGEN_CTRL);
784 wr32(hw, I40E_PFGEN_CTRL,
785 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
786 for (; cnt; cnt--) {
787 reg = rd32(hw, I40E_PFGEN_CTRL);
788 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
789 break;
790 reg2 = rd32(hw, I40E_GLGEN_RSTAT);
791 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
792 break;
793 usleep_range(1000, 2000);
794 }
795 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
796 if (i40e_poll_globr(hw, grst_del))
797 return -EIO;
798 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
799 hw_dbg(hw, "PF reset polling failed to complete.\n");
800 return -EIO;
801 }
802 }
803
804 i40e_clear_pxe_mode(hw);
805
806 return 0;
807}
808
809/**
810 * i40e_clear_hw - clear out any left over hw state
811 * @hw: pointer to the hw struct
812 *
813 * Clear queues and interrupts, typically called at init time,
814 * but after the capabilities have been found so we know how many
815 * queues and msix vectors have been allocated.
816 **/
817void i40e_clear_hw(struct i40e_hw *hw)
818{
819 u32 num_queues, base_queue;
820 u32 num_pf_int;
821 u32 num_vf_int;
822 u32 num_vfs;
823 u32 i, j;
824 u32 val;
825 u32 eol = 0x7ff;
826
827 /* get number of interrupts, queues, and VFs */
828 val = rd32(hw, I40E_GLPCI_CNF2);
829 num_pf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_PF_N_MASK, val);
830 num_vf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_VF_N_MASK, val);
831
832 val = rd32(hw, I40E_PFLAN_QALLOC);
833 base_queue = FIELD_GET(I40E_PFLAN_QALLOC_FIRSTQ_MASK, val);
834 j = FIELD_GET(I40E_PFLAN_QALLOC_LASTQ_MASK, val);
835 if (val & I40E_PFLAN_QALLOC_VALID_MASK && j >= base_queue)
836 num_queues = (j - base_queue) + 1;
837 else
838 num_queues = 0;
839
840 val = rd32(hw, I40E_PF_VT_PFALLOC);
841 i = FIELD_GET(I40E_PF_VT_PFALLOC_FIRSTVF_MASK, val);
842 j = FIELD_GET(I40E_PF_VT_PFALLOC_LASTVF_MASK, val);
843 if (val & I40E_PF_VT_PFALLOC_VALID_MASK && j >= i)
844 num_vfs = (j - i) + 1;
845 else
846 num_vfs = 0;
847
848 /* stop all the interrupts */
849 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
850 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
851 for (i = 0; i < num_pf_int - 2; i++)
852 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
853
854 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
855 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
856 wr32(hw, I40E_PFINT_LNKLST0, val);
857 for (i = 0; i < num_pf_int - 2; i++)
858 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
859 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
860 for (i = 0; i < num_vfs; i++)
861 wr32(hw, I40E_VPINT_LNKLST0(i), val);
862 for (i = 0; i < num_vf_int - 2; i++)
863 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
864
865 /* warn the HW of the coming Tx disables */
866 for (i = 0; i < num_queues; i++) {
867 u32 abs_queue_idx = base_queue + i;
868 u32 reg_block = 0;
869
870 if (abs_queue_idx >= 128) {
871 reg_block = abs_queue_idx / 128;
872 abs_queue_idx %= 128;
873 }
874
875 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
876 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
877 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
878 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
879
880 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
881 }
882 udelay(400);
883
884 /* stop all the queues */
885 for (i = 0; i < num_queues; i++) {
886 wr32(hw, I40E_QINT_TQCTL(i), 0);
887 wr32(hw, I40E_QTX_ENA(i), 0);
888 wr32(hw, I40E_QINT_RQCTL(i), 0);
889 wr32(hw, I40E_QRX_ENA(i), 0);
890 }
891
892 /* short wait for all queue disables to settle */
893 udelay(50);
894}
895
896/**
897 * i40e_clear_pxe_mode - clear pxe operations mode
898 * @hw: pointer to the hw struct
899 *
900 * Make sure all PXE mode settings are cleared, including things
901 * like descriptor fetch/write-back mode.
902 **/
903void i40e_clear_pxe_mode(struct i40e_hw *hw)
904{
905 u32 reg;
906
907 if (i40e_check_asq_alive(hw))
908 i40e_aq_clear_pxe_mode(hw, NULL);
909
910 /* Clear single descriptor fetch/write-back mode */
911 reg = rd32(hw, I40E_GLLAN_RCTL_0);
912
913 if (hw->revision_id == 0) {
914 /* As a work around clear PXE_MODE instead of setting it */
915 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
916 } else {
917 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
918 }
919}
920
921/**
922 * i40e_led_is_mine - helper to find matching led
923 * @hw: pointer to the hw struct
924 * @idx: index into GPIO registers
925 *
926 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
927 */
928static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
929{
930 u32 gpio_val = 0;
931 u32 port;
932
933 if (!I40E_IS_X710TL_DEVICE(hw->device_id) &&
934 !hw->func_caps.led[idx])
935 return 0;
936 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
937 port = FIELD_GET(I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK, gpio_val);
938
939 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
940 * if it is not our port then ignore
941 */
942 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
943 (port != hw->port))
944 return 0;
945
946 return gpio_val;
947}
948
949#define I40E_FW_LED BIT(4)
950#define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \
951 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
952
953#define I40E_LED0 22
954
955#define I40E_PIN_FUNC_SDP 0x0
956#define I40E_PIN_FUNC_LED 0x1
957
958/**
959 * i40e_led_get - return current on/off mode
960 * @hw: pointer to the hw struct
961 *
962 * The value returned is the 'mode' field as defined in the
963 * GPIO register definitions: 0x0 = off, 0xf = on, and other
964 * values are variations of possible behaviors relating to
965 * blink, link, and wire.
966 **/
967u32 i40e_led_get(struct i40e_hw *hw)
968{
969 u32 mode = 0;
970 int i;
971
972 /* as per the documentation GPIO 22-29 are the LED
973 * GPIO pins named LED0..LED7
974 */
975 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
976 u32 gpio_val = i40e_led_is_mine(hw, i);
977
978 if (!gpio_val)
979 continue;
980
981 mode = FIELD_GET(I40E_GLGEN_GPIO_CTL_LED_MODE_MASK, gpio_val);
982 break;
983 }
984
985 return mode;
986}
987
988/**
989 * i40e_led_set - set new on/off mode
990 * @hw: pointer to the hw struct
991 * @mode: 0=off, 0xf=on (else see manual for mode details)
992 * @blink: true if the LED should blink when on, false if steady
993 *
994 * if this function is used to turn on the blink it should
995 * be used to disable the blink when restoring the original state.
996 **/
997void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
998{
999 int i;
1000
1001 if (mode & ~I40E_LED_MODE_VALID) {
1002 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1003 return;
1004 }
1005
1006 /* as per the documentation GPIO 22-29 are the LED
1007 * GPIO pins named LED0..LED7
1008 */
1009 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1010 u32 gpio_val = i40e_led_is_mine(hw, i);
1011
1012 if (!gpio_val)
1013 continue;
1014
1015 if (I40E_IS_X710TL_DEVICE(hw->device_id)) {
1016 u32 pin_func = 0;
1017
1018 if (mode & I40E_FW_LED)
1019 pin_func = I40E_PIN_FUNC_SDP;
1020 else
1021 pin_func = I40E_PIN_FUNC_LED;
1022
1023 gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK;
1024 gpio_val |=
1025 FIELD_PREP(I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK,
1026 pin_func);
1027 }
1028 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1029 /* this & is a bit of paranoia, but serves as a range check */
1030 gpio_val |= FIELD_PREP(I40E_GLGEN_GPIO_CTL_LED_MODE_MASK,
1031 mode);
1032
1033 if (blink)
1034 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1035 else
1036 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1037
1038 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1039 break;
1040 }
1041}
1042
1043/* Admin command wrappers */
1044
1045/**
1046 * i40e_aq_get_phy_capabilities
1047 * @hw: pointer to the hw struct
1048 * @abilities: structure for PHY capabilities to be filled
1049 * @qualified_modules: report Qualified Modules
1050 * @report_init: report init capabilities (active are default)
1051 * @cmd_details: pointer to command details structure or NULL
1052 *
1053 * Returns the various PHY abilities supported on the Port.
1054 **/
1055int
1056i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1057 bool qualified_modules, bool report_init,
1058 struct i40e_aq_get_phy_abilities_resp *abilities,
1059 struct i40e_asq_cmd_details *cmd_details)
1060{
1061 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1062 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1063 struct i40e_aq_desc desc;
1064 int status;
1065
1066 if (!abilities)
1067 return -EINVAL;
1068
1069 do {
1070 i40e_fill_default_direct_cmd_desc(&desc,
1071 i40e_aqc_opc_get_phy_abilities);
1072
1073 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1074 if (abilities_size > I40E_AQ_LARGE_BUF)
1075 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1076
1077 if (qualified_modules)
1078 desc.params.external.param0 |=
1079 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1080
1081 if (report_init)
1082 desc.params.external.param0 |=
1083 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1084
1085 status = i40e_asq_send_command(hw, &desc, abilities,
1086 abilities_size, cmd_details);
1087
1088 switch (hw->aq.asq_last_status) {
1089 case I40E_AQ_RC_EIO:
1090 status = -EIO;
1091 break;
1092 case I40E_AQ_RC_EAGAIN:
1093 usleep_range(1000, 2000);
1094 total_delay++;
1095 status = -EIO;
1096 break;
1097 /* also covers I40E_AQ_RC_OK */
1098 default:
1099 break;
1100 }
1101
1102 } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) &&
1103 (total_delay < max_delay));
1104
1105 if (status)
1106 return status;
1107
1108 if (report_init) {
1109 if (hw->mac.type == I40E_MAC_XL710 &&
1110 i40e_is_aq_api_ver_ge(hw, I40E_FW_API_VERSION_MAJOR,
1111 I40E_MINOR_VER_GET_LINK_INFO_XL710)) {
1112 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1113 } else {
1114 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1115 hw->phy.phy_types |=
1116 ((u64)abilities->phy_type_ext << 32);
1117 }
1118 }
1119
1120 return status;
1121}
1122
1123/**
1124 * i40e_aq_set_phy_config
1125 * @hw: pointer to the hw struct
1126 * @config: structure with PHY configuration to be set
1127 * @cmd_details: pointer to command details structure or NULL
1128 *
1129 * Set the various PHY configuration parameters
1130 * supported on the Port.One or more of the Set PHY config parameters may be
1131 * ignored in an MFP mode as the PF may not have the privilege to set some
1132 * of the PHY Config parameters. This status will be indicated by the
1133 * command response.
1134 **/
1135int i40e_aq_set_phy_config(struct i40e_hw *hw,
1136 struct i40e_aq_set_phy_config *config,
1137 struct i40e_asq_cmd_details *cmd_details)
1138{
1139 struct i40e_aq_desc desc;
1140 struct i40e_aq_set_phy_config *cmd =
1141 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1142 int status;
1143
1144 if (!config)
1145 return -EINVAL;
1146
1147 i40e_fill_default_direct_cmd_desc(&desc,
1148 i40e_aqc_opc_set_phy_config);
1149
1150 *cmd = *config;
1151
1152 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1153
1154 return status;
1155}
1156
1157static noinline_for_stack int
1158i40e_set_fc_status(struct i40e_hw *hw,
1159 struct i40e_aq_get_phy_abilities_resp *abilities,
1160 bool atomic_restart)
1161{
1162 struct i40e_aq_set_phy_config config;
1163 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1164 u8 pause_mask = 0x0;
1165
1166 switch (fc_mode) {
1167 case I40E_FC_FULL:
1168 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1169 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1170 break;
1171 case I40E_FC_RX_PAUSE:
1172 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1173 break;
1174 case I40E_FC_TX_PAUSE:
1175 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1176 break;
1177 default:
1178 break;
1179 }
1180
1181 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1182 /* clear the old pause settings */
1183 config.abilities = abilities->abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1184 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1185 /* set the new abilities */
1186 config.abilities |= pause_mask;
1187 /* If the abilities have changed, then set the new config */
1188 if (config.abilities == abilities->abilities)
1189 return 0;
1190
1191 /* Auto restart link so settings take effect */
1192 if (atomic_restart)
1193 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1194 /* Copy over all the old settings */
1195 config.phy_type = abilities->phy_type;
1196 config.phy_type_ext = abilities->phy_type_ext;
1197 config.link_speed = abilities->link_speed;
1198 config.eee_capability = abilities->eee_capability;
1199 config.eeer = abilities->eeer_val;
1200 config.low_power_ctrl = abilities->d3_lpan;
1201 config.fec_config = abilities->fec_cfg_curr_mod_ext_info &
1202 I40E_AQ_PHY_FEC_CONFIG_MASK;
1203
1204 return i40e_aq_set_phy_config(hw, &config, NULL);
1205}
1206
1207/**
1208 * i40e_set_fc
1209 * @hw: pointer to the hw struct
1210 * @aq_failures: buffer to return AdminQ failure information
1211 * @atomic_restart: whether to enable atomic link restart
1212 *
1213 * Set the requested flow control mode using set_phy_config.
1214 **/
1215int i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1216 bool atomic_restart)
1217{
1218 struct i40e_aq_get_phy_abilities_resp abilities;
1219 int status;
1220
1221 *aq_failures = 0x0;
1222
1223 /* Get the current phy config */
1224 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1225 NULL);
1226 if (status) {
1227 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1228 return status;
1229 }
1230
1231 status = i40e_set_fc_status(hw, &abilities, atomic_restart);
1232 if (status)
1233 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1234
1235 /* Update the link info */
1236 status = i40e_update_link_info(hw);
1237 if (status) {
1238 /* Wait a little bit (on 40G cards it sometimes takes a really
1239 * long time for link to come back from the atomic reset)
1240 * and try once more
1241 */
1242 msleep(1000);
1243 status = i40e_update_link_info(hw);
1244 }
1245 if (status)
1246 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1247
1248 return status;
1249}
1250
1251/**
1252 * i40e_aq_clear_pxe_mode
1253 * @hw: pointer to the hw struct
1254 * @cmd_details: pointer to command details structure or NULL
1255 *
1256 * Tell the firmware that the driver is taking over from PXE
1257 **/
1258int i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1259 struct i40e_asq_cmd_details *cmd_details)
1260{
1261 struct i40e_aq_desc desc;
1262 struct i40e_aqc_clear_pxe *cmd =
1263 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1264 int status;
1265
1266 i40e_fill_default_direct_cmd_desc(&desc,
1267 i40e_aqc_opc_clear_pxe_mode);
1268
1269 cmd->rx_cnt = 0x2;
1270
1271 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1272
1273 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1274
1275 return status;
1276}
1277
1278/**
1279 * i40e_aq_set_link_restart_an
1280 * @hw: pointer to the hw struct
1281 * @enable_link: if true: enable link, if false: disable link
1282 * @cmd_details: pointer to command details structure or NULL
1283 *
1284 * Sets up the link and restarts the Auto-Negotiation over the link.
1285 **/
1286int i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1287 bool enable_link,
1288 struct i40e_asq_cmd_details *cmd_details)
1289{
1290 struct i40e_aq_desc desc;
1291 struct i40e_aqc_set_link_restart_an *cmd =
1292 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1293 int status;
1294
1295 i40e_fill_default_direct_cmd_desc(&desc,
1296 i40e_aqc_opc_set_link_restart_an);
1297
1298 cmd->command = I40E_AQ_PHY_RESTART_AN;
1299 if (enable_link)
1300 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1301 else
1302 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1303
1304 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1305
1306 return status;
1307}
1308
1309/**
1310 * i40e_aq_get_link_info
1311 * @hw: pointer to the hw struct
1312 * @enable_lse: enable/disable LinkStatusEvent reporting
1313 * @link: pointer to link status structure - optional
1314 * @cmd_details: pointer to command details structure or NULL
1315 *
1316 * Returns the link status of the adapter.
1317 **/
1318int i40e_aq_get_link_info(struct i40e_hw *hw,
1319 bool enable_lse, struct i40e_link_status *link,
1320 struct i40e_asq_cmd_details *cmd_details)
1321{
1322 struct i40e_aq_desc desc;
1323 struct i40e_aqc_get_link_status *resp =
1324 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1325 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1326 bool tx_pause, rx_pause;
1327 u16 command_flags;
1328 int status;
1329
1330 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1331
1332 if (enable_lse)
1333 command_flags = I40E_AQ_LSE_ENABLE;
1334 else
1335 command_flags = I40E_AQ_LSE_DISABLE;
1336 resp->command_flags = cpu_to_le16(command_flags);
1337
1338 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1339
1340 if (status)
1341 goto aq_get_link_info_exit;
1342
1343 /* save off old link status information */
1344 hw->phy.link_info_old = *hw_link_info;
1345
1346 /* update link status */
1347 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1348 hw->phy.media_type = i40e_get_media_type(hw);
1349 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1350 hw_link_info->link_info = resp->link_info;
1351 hw_link_info->an_info = resp->an_info;
1352 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1353 I40E_AQ_CONFIG_FEC_RS_ENA);
1354 hw_link_info->ext_info = resp->ext_info;
1355 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1356 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1357 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1358
1359 /* update fc info */
1360 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1361 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1362 if (tx_pause & rx_pause)
1363 hw->fc.current_mode = I40E_FC_FULL;
1364 else if (tx_pause)
1365 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1366 else if (rx_pause)
1367 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1368 else
1369 hw->fc.current_mode = I40E_FC_NONE;
1370
1371 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1372 hw_link_info->crc_enable = true;
1373 else
1374 hw_link_info->crc_enable = false;
1375
1376 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED))
1377 hw_link_info->lse_enable = true;
1378 else
1379 hw_link_info->lse_enable = false;
1380
1381 if (hw->mac.type == I40E_MAC_XL710 && i40e_is_fw_ver_lt(hw, 4, 40) &&
1382 hw_link_info->phy_type == 0xE)
1383 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1384
1385 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps) &&
1386 hw->mac.type != I40E_MAC_X722) {
1387 __le32 tmp;
1388
1389 memcpy(&tmp, resp->link_type, sizeof(tmp));
1390 hw->phy.phy_types = le32_to_cpu(tmp);
1391 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
1392 }
1393
1394 /* save link status information */
1395 if (link)
1396 *link = *hw_link_info;
1397
1398 /* flag cleared so helper functions don't call AQ again */
1399 hw->phy.get_link_info = false;
1400
1401aq_get_link_info_exit:
1402 return status;
1403}
1404
1405/**
1406 * i40e_aq_set_phy_int_mask
1407 * @hw: pointer to the hw struct
1408 * @mask: interrupt mask to be set
1409 * @cmd_details: pointer to command details structure or NULL
1410 *
1411 * Set link interrupt mask.
1412 **/
1413int i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1414 u16 mask,
1415 struct i40e_asq_cmd_details *cmd_details)
1416{
1417 struct i40e_aq_desc desc;
1418 struct i40e_aqc_set_phy_int_mask *cmd =
1419 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1420 int status;
1421
1422 i40e_fill_default_direct_cmd_desc(&desc,
1423 i40e_aqc_opc_set_phy_int_mask);
1424
1425 cmd->event_mask = cpu_to_le16(mask);
1426
1427 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1428
1429 return status;
1430}
1431
1432/**
1433 * i40e_aq_set_mac_loopback
1434 * @hw: pointer to the HW struct
1435 * @ena_lpbk: Enable or Disable loopback
1436 * @cmd_details: pointer to command details structure or NULL
1437 *
1438 * Enable/disable loopback on a given port
1439 */
1440int i40e_aq_set_mac_loopback(struct i40e_hw *hw, bool ena_lpbk,
1441 struct i40e_asq_cmd_details *cmd_details)
1442{
1443 struct i40e_aq_desc desc;
1444 struct i40e_aqc_set_lb_mode *cmd =
1445 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1446
1447 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_lb_modes);
1448 if (ena_lpbk) {
1449 if (hw->nvm.version <= I40E_LEGACY_LOOPBACK_NVM_VER)
1450 cmd->lb_mode = cpu_to_le16(I40E_AQ_LB_MAC_LOCAL_LEGACY);
1451 else
1452 cmd->lb_mode = cpu_to_le16(I40E_AQ_LB_MAC_LOCAL);
1453 }
1454
1455 return i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1456}
1457
1458/**
1459 * i40e_aq_set_phy_debug
1460 * @hw: pointer to the hw struct
1461 * @cmd_flags: debug command flags
1462 * @cmd_details: pointer to command details structure or NULL
1463 *
1464 * Reset the external PHY.
1465 **/
1466int i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1467 struct i40e_asq_cmd_details *cmd_details)
1468{
1469 struct i40e_aq_desc desc;
1470 struct i40e_aqc_set_phy_debug *cmd =
1471 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1472 int status;
1473
1474 i40e_fill_default_direct_cmd_desc(&desc,
1475 i40e_aqc_opc_set_phy_debug);
1476
1477 cmd->command_flags = cmd_flags;
1478
1479 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1480
1481 return status;
1482}
1483
1484/**
1485 * i40e_aq_add_vsi
1486 * @hw: pointer to the hw struct
1487 * @vsi_ctx: pointer to a vsi context struct
1488 * @cmd_details: pointer to command details structure or NULL
1489 *
1490 * Add a VSI context to the hardware.
1491**/
1492int i40e_aq_add_vsi(struct i40e_hw *hw,
1493 struct i40e_vsi_context *vsi_ctx,
1494 struct i40e_asq_cmd_details *cmd_details)
1495{
1496 struct i40e_aq_desc desc;
1497 struct i40e_aqc_add_get_update_vsi *cmd =
1498 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1499 struct i40e_aqc_add_get_update_vsi_completion *resp =
1500 (struct i40e_aqc_add_get_update_vsi_completion *)
1501 &desc.params.raw;
1502 int status;
1503
1504 i40e_fill_default_direct_cmd_desc(&desc,
1505 i40e_aqc_opc_add_vsi);
1506
1507 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1508 cmd->connection_type = vsi_ctx->connection_type;
1509 cmd->vf_id = vsi_ctx->vf_num;
1510 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1511
1512 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1513
1514 status = i40e_asq_send_command_atomic(hw, &desc, &vsi_ctx->info,
1515 sizeof(vsi_ctx->info),
1516 cmd_details, true);
1517
1518 if (status)
1519 goto aq_add_vsi_exit;
1520
1521 vsi_ctx->seid = le16_to_cpu(resp->seid);
1522 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1523 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1524 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1525
1526aq_add_vsi_exit:
1527 return status;
1528}
1529
1530/**
1531 * i40e_aq_set_default_vsi
1532 * @hw: pointer to the hw struct
1533 * @seid: vsi number
1534 * @cmd_details: pointer to command details structure or NULL
1535 **/
1536int i40e_aq_set_default_vsi(struct i40e_hw *hw,
1537 u16 seid,
1538 struct i40e_asq_cmd_details *cmd_details)
1539{
1540 struct i40e_aq_desc desc;
1541 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1542 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1543 &desc.params.raw;
1544 int status;
1545
1546 i40e_fill_default_direct_cmd_desc(&desc,
1547 i40e_aqc_opc_set_vsi_promiscuous_modes);
1548
1549 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1550 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1551 cmd->seid = cpu_to_le16(seid);
1552
1553 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1554
1555 return status;
1556}
1557
1558/**
1559 * i40e_aq_clear_default_vsi
1560 * @hw: pointer to the hw struct
1561 * @seid: vsi number
1562 * @cmd_details: pointer to command details structure or NULL
1563 **/
1564int i40e_aq_clear_default_vsi(struct i40e_hw *hw,
1565 u16 seid,
1566 struct i40e_asq_cmd_details *cmd_details)
1567{
1568 struct i40e_aq_desc desc;
1569 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1570 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1571 &desc.params.raw;
1572 int status;
1573
1574 i40e_fill_default_direct_cmd_desc(&desc,
1575 i40e_aqc_opc_set_vsi_promiscuous_modes);
1576
1577 cmd->promiscuous_flags = cpu_to_le16(0);
1578 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1579 cmd->seid = cpu_to_le16(seid);
1580
1581 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1582
1583 return status;
1584}
1585
1586/**
1587 * i40e_aq_set_vsi_unicast_promiscuous
1588 * @hw: pointer to the hw struct
1589 * @seid: vsi number
1590 * @set: set unicast promiscuous enable/disable
1591 * @cmd_details: pointer to command details structure or NULL
1592 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
1593 **/
1594int i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1595 u16 seid, bool set,
1596 struct i40e_asq_cmd_details *cmd_details,
1597 bool rx_only_promisc)
1598{
1599 struct i40e_aq_desc desc;
1600 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1601 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1602 u16 flags = 0;
1603 int status;
1604
1605 i40e_fill_default_direct_cmd_desc(&desc,
1606 i40e_aqc_opc_set_vsi_promiscuous_modes);
1607
1608 if (set) {
1609 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1610 if (rx_only_promisc && i40e_is_aq_api_ver_ge(hw, 1, 5))
1611 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
1612 }
1613
1614 cmd->promiscuous_flags = cpu_to_le16(flags);
1615
1616 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1617 if (i40e_is_aq_api_ver_ge(hw, 1, 5))
1618 cmd->valid_flags |=
1619 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
1620
1621 cmd->seid = cpu_to_le16(seid);
1622 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1623
1624 return status;
1625}
1626
1627/**
1628 * i40e_aq_set_vsi_multicast_promiscuous
1629 * @hw: pointer to the hw struct
1630 * @seid: vsi number
1631 * @set: set multicast promiscuous enable/disable
1632 * @cmd_details: pointer to command details structure or NULL
1633 **/
1634int i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1635 u16 seid, bool set,
1636 struct i40e_asq_cmd_details *cmd_details)
1637{
1638 struct i40e_aq_desc desc;
1639 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1640 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1641 u16 flags = 0;
1642 int status;
1643
1644 i40e_fill_default_direct_cmd_desc(&desc,
1645 i40e_aqc_opc_set_vsi_promiscuous_modes);
1646
1647 if (set)
1648 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1649
1650 cmd->promiscuous_flags = cpu_to_le16(flags);
1651
1652 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1653
1654 cmd->seid = cpu_to_le16(seid);
1655 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1656
1657 return status;
1658}
1659
1660/**
1661 * i40e_aq_set_vsi_mc_promisc_on_vlan
1662 * @hw: pointer to the hw struct
1663 * @seid: vsi number
1664 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
1665 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
1666 * @cmd_details: pointer to command details structure or NULL
1667 **/
1668int i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
1669 u16 seid, bool enable,
1670 u16 vid,
1671 struct i40e_asq_cmd_details *cmd_details)
1672{
1673 struct i40e_aq_desc desc;
1674 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1675 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1676 u16 flags = 0;
1677 int status;
1678
1679 i40e_fill_default_direct_cmd_desc(&desc,
1680 i40e_aqc_opc_set_vsi_promiscuous_modes);
1681
1682 if (enable)
1683 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1684
1685 cmd->promiscuous_flags = cpu_to_le16(flags);
1686 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1687 cmd->seid = cpu_to_le16(seid);
1688 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
1689
1690 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0,
1691 cmd_details, true);
1692
1693 return status;
1694}
1695
1696/**
1697 * i40e_aq_set_vsi_uc_promisc_on_vlan
1698 * @hw: pointer to the hw struct
1699 * @seid: vsi number
1700 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
1701 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
1702 * @cmd_details: pointer to command details structure or NULL
1703 **/
1704int i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
1705 u16 seid, bool enable,
1706 u16 vid,
1707 struct i40e_asq_cmd_details *cmd_details)
1708{
1709 struct i40e_aq_desc desc;
1710 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1711 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1712 u16 flags = 0;
1713 int status;
1714
1715 i40e_fill_default_direct_cmd_desc(&desc,
1716 i40e_aqc_opc_set_vsi_promiscuous_modes);
1717
1718 if (enable) {
1719 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1720 if (i40e_is_aq_api_ver_ge(hw, 1, 5))
1721 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
1722 }
1723
1724 cmd->promiscuous_flags = cpu_to_le16(flags);
1725 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1726 if (i40e_is_aq_api_ver_ge(hw, 1, 5))
1727 cmd->valid_flags |=
1728 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
1729 cmd->seid = cpu_to_le16(seid);
1730 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
1731
1732 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0,
1733 cmd_details, true);
1734
1735 return status;
1736}
1737
1738/**
1739 * i40e_aq_set_vsi_bc_promisc_on_vlan
1740 * @hw: pointer to the hw struct
1741 * @seid: vsi number
1742 * @enable: set broadcast promiscuous enable/disable for a given VLAN
1743 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
1744 * @cmd_details: pointer to command details structure or NULL
1745 **/
1746int i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
1747 u16 seid, bool enable, u16 vid,
1748 struct i40e_asq_cmd_details *cmd_details)
1749{
1750 struct i40e_aq_desc desc;
1751 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1752 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1753 u16 flags = 0;
1754 int status;
1755
1756 i40e_fill_default_direct_cmd_desc(&desc,
1757 i40e_aqc_opc_set_vsi_promiscuous_modes);
1758
1759 if (enable)
1760 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
1761
1762 cmd->promiscuous_flags = cpu_to_le16(flags);
1763 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1764 cmd->seid = cpu_to_le16(seid);
1765 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
1766
1767 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1768
1769 return status;
1770}
1771
1772/**
1773 * i40e_aq_set_vsi_broadcast
1774 * @hw: pointer to the hw struct
1775 * @seid: vsi number
1776 * @set_filter: true to set filter, false to clear filter
1777 * @cmd_details: pointer to command details structure or NULL
1778 *
1779 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1780 **/
1781int i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1782 u16 seid, bool set_filter,
1783 struct i40e_asq_cmd_details *cmd_details)
1784{
1785 struct i40e_aq_desc desc;
1786 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1787 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1788 int status;
1789
1790 i40e_fill_default_direct_cmd_desc(&desc,
1791 i40e_aqc_opc_set_vsi_promiscuous_modes);
1792
1793 if (set_filter)
1794 cmd->promiscuous_flags
1795 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1796 else
1797 cmd->promiscuous_flags
1798 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1799
1800 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1801 cmd->seid = cpu_to_le16(seid);
1802 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1803
1804 return status;
1805}
1806
1807/**
1808 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
1809 * @hw: pointer to the hw struct
1810 * @seid: vsi number
1811 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
1812 * @cmd_details: pointer to command details structure or NULL
1813 **/
1814int i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
1815 u16 seid, bool enable,
1816 struct i40e_asq_cmd_details *cmd_details)
1817{
1818 struct i40e_aq_desc desc;
1819 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1820 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1821 u16 flags = 0;
1822 int status;
1823
1824 i40e_fill_default_direct_cmd_desc(&desc,
1825 i40e_aqc_opc_set_vsi_promiscuous_modes);
1826 if (enable)
1827 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
1828
1829 cmd->promiscuous_flags = cpu_to_le16(flags);
1830 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
1831 cmd->seid = cpu_to_le16(seid);
1832
1833 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1834
1835 return status;
1836}
1837
1838/**
1839 * i40e_aq_get_vsi_params - get VSI configuration info
1840 * @hw: pointer to the hw struct
1841 * @vsi_ctx: pointer to a vsi context struct
1842 * @cmd_details: pointer to command details structure or NULL
1843 **/
1844int i40e_aq_get_vsi_params(struct i40e_hw *hw,
1845 struct i40e_vsi_context *vsi_ctx,
1846 struct i40e_asq_cmd_details *cmd_details)
1847{
1848 struct i40e_aq_desc desc;
1849 struct i40e_aqc_add_get_update_vsi *cmd =
1850 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1851 struct i40e_aqc_add_get_update_vsi_completion *resp =
1852 (struct i40e_aqc_add_get_update_vsi_completion *)
1853 &desc.params.raw;
1854 int status;
1855
1856 i40e_fill_default_direct_cmd_desc(&desc,
1857 i40e_aqc_opc_get_vsi_parameters);
1858
1859 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
1860
1861 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1862
1863 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1864 sizeof(vsi_ctx->info), NULL);
1865
1866 if (status)
1867 goto aq_get_vsi_params_exit;
1868
1869 vsi_ctx->seid = le16_to_cpu(resp->seid);
1870 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1871 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1872 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1873
1874aq_get_vsi_params_exit:
1875 return status;
1876}
1877
1878/**
1879 * i40e_aq_update_vsi_params
1880 * @hw: pointer to the hw struct
1881 * @vsi_ctx: pointer to a vsi context struct
1882 * @cmd_details: pointer to command details structure or NULL
1883 *
1884 * Update a VSI context.
1885 **/
1886int i40e_aq_update_vsi_params(struct i40e_hw *hw,
1887 struct i40e_vsi_context *vsi_ctx,
1888 struct i40e_asq_cmd_details *cmd_details)
1889{
1890 struct i40e_aq_desc desc;
1891 struct i40e_aqc_add_get_update_vsi *cmd =
1892 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1893 struct i40e_aqc_add_get_update_vsi_completion *resp =
1894 (struct i40e_aqc_add_get_update_vsi_completion *)
1895 &desc.params.raw;
1896 int status;
1897
1898 i40e_fill_default_direct_cmd_desc(&desc,
1899 i40e_aqc_opc_update_vsi_parameters);
1900 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
1901
1902 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1903
1904 status = i40e_asq_send_command_atomic(hw, &desc, &vsi_ctx->info,
1905 sizeof(vsi_ctx->info),
1906 cmd_details, true);
1907
1908 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1909 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1910
1911 return status;
1912}
1913
1914/**
1915 * i40e_aq_get_switch_config
1916 * @hw: pointer to the hardware structure
1917 * @buf: pointer to the result buffer
1918 * @buf_size: length of input buffer
1919 * @start_seid: seid to start for the report, 0 == beginning
1920 * @cmd_details: pointer to command details structure or NULL
1921 *
1922 * Fill the buf with switch configuration returned from AdminQ command
1923 **/
1924int i40e_aq_get_switch_config(struct i40e_hw *hw,
1925 struct i40e_aqc_get_switch_config_resp *buf,
1926 u16 buf_size, u16 *start_seid,
1927 struct i40e_asq_cmd_details *cmd_details)
1928{
1929 struct i40e_aq_desc desc;
1930 struct i40e_aqc_switch_seid *scfg =
1931 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1932 int status;
1933
1934 i40e_fill_default_direct_cmd_desc(&desc,
1935 i40e_aqc_opc_get_switch_config);
1936 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1937 if (buf_size > I40E_AQ_LARGE_BUF)
1938 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1939 scfg->seid = cpu_to_le16(*start_seid);
1940
1941 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1942 *start_seid = le16_to_cpu(scfg->seid);
1943
1944 return status;
1945}
1946
1947/**
1948 * i40e_aq_set_switch_config
1949 * @hw: pointer to the hardware structure
1950 * @flags: bit flag values to set
1951 * @mode: cloud filter mode
1952 * @valid_flags: which bit flags to set
1953 * @mode: cloud filter mode
1954 * @cmd_details: pointer to command details structure or NULL
1955 *
1956 * Set switch configuration bits
1957 **/
1958int i40e_aq_set_switch_config(struct i40e_hw *hw,
1959 u16 flags,
1960 u16 valid_flags, u8 mode,
1961 struct i40e_asq_cmd_details *cmd_details)
1962{
1963 struct i40e_aq_desc desc;
1964 struct i40e_aqc_set_switch_config *scfg =
1965 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
1966 int status;
1967
1968 i40e_fill_default_direct_cmd_desc(&desc,
1969 i40e_aqc_opc_set_switch_config);
1970 scfg->flags = cpu_to_le16(flags);
1971 scfg->valid_flags = cpu_to_le16(valid_flags);
1972 scfg->mode = mode;
1973 if (test_bit(I40E_HW_CAP_802_1AD, hw->caps)) {
1974 scfg->switch_tag = cpu_to_le16(hw->switch_tag);
1975 scfg->first_tag = cpu_to_le16(hw->first_tag);
1976 scfg->second_tag = cpu_to_le16(hw->second_tag);
1977 }
1978 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1979
1980 return status;
1981}
1982
1983/**
1984 * i40e_aq_get_firmware_version
1985 * @hw: pointer to the hw struct
1986 * @fw_major_version: firmware major version
1987 * @fw_minor_version: firmware minor version
1988 * @fw_build: firmware build number
1989 * @api_major_version: major queue version
1990 * @api_minor_version: minor queue version
1991 * @cmd_details: pointer to command details structure or NULL
1992 *
1993 * Get the firmware version from the admin queue commands
1994 **/
1995int i40e_aq_get_firmware_version(struct i40e_hw *hw,
1996 u16 *fw_major_version, u16 *fw_minor_version,
1997 u32 *fw_build,
1998 u16 *api_major_version, u16 *api_minor_version,
1999 struct i40e_asq_cmd_details *cmd_details)
2000{
2001 struct i40e_aq_desc desc;
2002 struct i40e_aqc_get_version *resp =
2003 (struct i40e_aqc_get_version *)&desc.params.raw;
2004 int status;
2005
2006 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2007
2008 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2009
2010 if (!status) {
2011 if (fw_major_version)
2012 *fw_major_version = le16_to_cpu(resp->fw_major);
2013 if (fw_minor_version)
2014 *fw_minor_version = le16_to_cpu(resp->fw_minor);
2015 if (fw_build)
2016 *fw_build = le32_to_cpu(resp->fw_build);
2017 if (api_major_version)
2018 *api_major_version = le16_to_cpu(resp->api_major);
2019 if (api_minor_version)
2020 *api_minor_version = le16_to_cpu(resp->api_minor);
2021 }
2022
2023 return status;
2024}
2025
2026/**
2027 * i40e_aq_send_driver_version
2028 * @hw: pointer to the hw struct
2029 * @dv: driver's major, minor version
2030 * @cmd_details: pointer to command details structure or NULL
2031 *
2032 * Send the driver version to the firmware
2033 **/
2034int i40e_aq_send_driver_version(struct i40e_hw *hw,
2035 struct i40e_driver_version *dv,
2036 struct i40e_asq_cmd_details *cmd_details)
2037{
2038 struct i40e_aq_desc desc;
2039 struct i40e_aqc_driver_version *cmd =
2040 (struct i40e_aqc_driver_version *)&desc.params.raw;
2041 int status;
2042 u16 len;
2043
2044 if (dv == NULL)
2045 return -EINVAL;
2046
2047 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2048
2049 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2050 cmd->driver_major_ver = dv->major_version;
2051 cmd->driver_minor_ver = dv->minor_version;
2052 cmd->driver_build_ver = dv->build_version;
2053 cmd->driver_subbuild_ver = dv->subbuild_version;
2054
2055 len = 0;
2056 while (len < sizeof(dv->driver_string) &&
2057 (dv->driver_string[len] < 0x80) &&
2058 dv->driver_string[len])
2059 len++;
2060 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2061 len, cmd_details);
2062
2063 return status;
2064}
2065
2066/**
2067 * i40e_get_link_status - get status of the HW network link
2068 * @hw: pointer to the hw struct
2069 * @link_up: pointer to bool (true/false = linkup/linkdown)
2070 *
2071 * Variable link_up true if link is up, false if link is down.
2072 * The variable link_up is invalid if returned value of status != 0
2073 *
2074 * Side effect: LinkStatusEvent reporting becomes enabled
2075 **/
2076int i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2077{
2078 int status = 0;
2079
2080 if (hw->phy.get_link_info) {
2081 status = i40e_update_link_info(hw);
2082
2083 if (status)
2084 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2085 status);
2086 }
2087
2088 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2089
2090 return status;
2091}
2092
2093/**
2094 * i40e_update_link_info - update status of the HW network link
2095 * @hw: pointer to the hw struct
2096 **/
2097noinline_for_stack int i40e_update_link_info(struct i40e_hw *hw)
2098{
2099 struct i40e_aq_get_phy_abilities_resp abilities;
2100 int status = 0;
2101
2102 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2103 if (status)
2104 return status;
2105
2106 /* extra checking needed to ensure link info to user is timely */
2107 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2108 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2109 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2110 status = i40e_aq_get_phy_capabilities(hw, false, false,
2111 &abilities, NULL);
2112 if (status)
2113 return status;
2114
2115 if (abilities.fec_cfg_curr_mod_ext_info &
2116 I40E_AQ_ENABLE_FEC_AUTO)
2117 hw->phy.link_info.req_fec_info =
2118 (I40E_AQ_REQUEST_FEC_KR |
2119 I40E_AQ_REQUEST_FEC_RS);
2120 else
2121 hw->phy.link_info.req_fec_info =
2122 abilities.fec_cfg_curr_mod_ext_info &
2123 (I40E_AQ_REQUEST_FEC_KR |
2124 I40E_AQ_REQUEST_FEC_RS);
2125
2126 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2127 sizeof(hw->phy.link_info.module_type));
2128 }
2129
2130 return status;
2131}
2132
2133/**
2134 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2135 * @hw: pointer to the hw struct
2136 * @uplink_seid: the MAC or other gizmo SEID
2137 * @downlink_seid: the VSI SEID
2138 * @enabled_tc: bitmap of TCs to be enabled
2139 * @default_port: true for default port VSI, false for control port
2140 * @veb_seid: pointer to where to put the resulting VEB SEID
2141 * @enable_stats: true to turn on VEB stats
2142 * @cmd_details: pointer to command details structure or NULL
2143 *
2144 * This asks the FW to add a VEB between the uplink and downlink
2145 * elements. If the uplink SEID is 0, this will be a floating VEB.
2146 **/
2147int i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2148 u16 downlink_seid, u8 enabled_tc,
2149 bool default_port, u16 *veb_seid,
2150 bool enable_stats,
2151 struct i40e_asq_cmd_details *cmd_details)
2152{
2153 struct i40e_aq_desc desc;
2154 struct i40e_aqc_add_veb *cmd =
2155 (struct i40e_aqc_add_veb *)&desc.params.raw;
2156 struct i40e_aqc_add_veb_completion *resp =
2157 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2158 u16 veb_flags = 0;
2159 int status;
2160
2161 /* SEIDs need to either both be set or both be 0 for floating VEB */
2162 if (!!uplink_seid != !!downlink_seid)
2163 return -EINVAL;
2164
2165 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2166
2167 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2168 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2169 cmd->enable_tcs = enabled_tc;
2170 if (!uplink_seid)
2171 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2172 if (default_port)
2173 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2174 else
2175 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2176
2177 /* reverse logic here: set the bitflag to disable the stats */
2178 if (!enable_stats)
2179 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2180
2181 cmd->veb_flags = cpu_to_le16(veb_flags);
2182
2183 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2184
2185 if (!status && veb_seid)
2186 *veb_seid = le16_to_cpu(resp->veb_seid);
2187
2188 return status;
2189}
2190
2191/**
2192 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2193 * @hw: pointer to the hw struct
2194 * @veb_seid: the SEID of the VEB to query
2195 * @switch_id: the uplink switch id
2196 * @floating: set to true if the VEB is floating
2197 * @statistic_index: index of the stats counter block for this VEB
2198 * @vebs_used: number of VEB's used by function
2199 * @vebs_free: total VEB's not reserved by any function
2200 * @cmd_details: pointer to command details structure or NULL
2201 *
2202 * This retrieves the parameters for a particular VEB, specified by
2203 * uplink_seid, and returns them to the caller.
2204 **/
2205int i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2206 u16 veb_seid, u16 *switch_id,
2207 bool *floating, u16 *statistic_index,
2208 u16 *vebs_used, u16 *vebs_free,
2209 struct i40e_asq_cmd_details *cmd_details)
2210{
2211 struct i40e_aq_desc desc;
2212 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2213 (struct i40e_aqc_get_veb_parameters_completion *)
2214 &desc.params.raw;
2215 int status;
2216
2217 if (veb_seid == 0)
2218 return -EINVAL;
2219
2220 i40e_fill_default_direct_cmd_desc(&desc,
2221 i40e_aqc_opc_get_veb_parameters);
2222 cmd_resp->seid = cpu_to_le16(veb_seid);
2223
2224 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2225 if (status)
2226 goto get_veb_exit;
2227
2228 if (switch_id)
2229 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2230 if (statistic_index)
2231 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2232 if (vebs_used)
2233 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2234 if (vebs_free)
2235 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2236 if (floating) {
2237 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2238
2239 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2240 *floating = true;
2241 else
2242 *floating = false;
2243 }
2244
2245get_veb_exit:
2246 return status;
2247}
2248
2249/**
2250 * i40e_prepare_add_macvlan
2251 * @mv_list: list of macvlans to be added
2252 * @desc: pointer to AQ descriptor structure
2253 * @count: length of the list
2254 * @seid: VSI for the mac address
2255 *
2256 * Internal helper function that prepares the add macvlan request
2257 * and returns the buffer size.
2258 **/
2259static u16
2260i40e_prepare_add_macvlan(struct i40e_aqc_add_macvlan_element_data *mv_list,
2261 struct i40e_aq_desc *desc, u16 count, u16 seid)
2262{
2263 struct i40e_aqc_macvlan *cmd =
2264 (struct i40e_aqc_macvlan *)&desc->params.raw;
2265 u16 buf_size;
2266 int i;
2267
2268 buf_size = count * sizeof(*mv_list);
2269
2270 /* prep the rest of the request */
2271 i40e_fill_default_direct_cmd_desc(desc, i40e_aqc_opc_add_macvlan);
2272 cmd->num_addresses = cpu_to_le16(count);
2273 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2274 cmd->seid[1] = 0;
2275 cmd->seid[2] = 0;
2276
2277 for (i = 0; i < count; i++)
2278 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2279 mv_list[i].flags |=
2280 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2281
2282 desc->flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2283 if (buf_size > I40E_AQ_LARGE_BUF)
2284 desc->flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2285
2286 return buf_size;
2287}
2288
2289/**
2290 * i40e_aq_add_macvlan
2291 * @hw: pointer to the hw struct
2292 * @seid: VSI for the mac address
2293 * @mv_list: list of macvlans to be added
2294 * @count: length of the list
2295 * @cmd_details: pointer to command details structure or NULL
2296 *
2297 * Add MAC/VLAN addresses to the HW filtering
2298 **/
2299int
2300i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2301 struct i40e_aqc_add_macvlan_element_data *mv_list,
2302 u16 count, struct i40e_asq_cmd_details *cmd_details)
2303{
2304 struct i40e_aq_desc desc;
2305 u16 buf_size;
2306
2307 if (count == 0 || !mv_list || !hw)
2308 return -EINVAL;
2309
2310 buf_size = i40e_prepare_add_macvlan(mv_list, &desc, count, seid);
2311
2312 return i40e_asq_send_command_atomic(hw, &desc, mv_list, buf_size,
2313 cmd_details, true);
2314}
2315
2316/**
2317 * i40e_aq_add_macvlan_v2
2318 * @hw: pointer to the hw struct
2319 * @seid: VSI for the mac address
2320 * @mv_list: list of macvlans to be added
2321 * @count: length of the list
2322 * @cmd_details: pointer to command details structure or NULL
2323 * @aq_status: pointer to Admin Queue status return value
2324 *
2325 * Add MAC/VLAN addresses to the HW filtering.
2326 * The _v2 version returns the last Admin Queue status in aq_status
2327 * to avoid race conditions in access to hw->aq.asq_last_status.
2328 * It also calls _v2 versions of asq_send_command functions to
2329 * get the aq_status on the stack.
2330 **/
2331int
2332i40e_aq_add_macvlan_v2(struct i40e_hw *hw, u16 seid,
2333 struct i40e_aqc_add_macvlan_element_data *mv_list,
2334 u16 count, struct i40e_asq_cmd_details *cmd_details,
2335 enum i40e_admin_queue_err *aq_status)
2336{
2337 struct i40e_aq_desc desc;
2338 u16 buf_size;
2339
2340 if (count == 0 || !mv_list || !hw)
2341 return -EINVAL;
2342
2343 buf_size = i40e_prepare_add_macvlan(mv_list, &desc, count, seid);
2344
2345 return i40e_asq_send_command_atomic_v2(hw, &desc, mv_list, buf_size,
2346 cmd_details, true, aq_status);
2347}
2348
2349/**
2350 * i40e_aq_remove_macvlan
2351 * @hw: pointer to the hw struct
2352 * @seid: VSI for the mac address
2353 * @mv_list: list of macvlans to be removed
2354 * @count: length of the list
2355 * @cmd_details: pointer to command details structure or NULL
2356 *
2357 * Remove MAC/VLAN addresses from the HW filtering
2358 **/
2359int
2360i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2361 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2362 u16 count, struct i40e_asq_cmd_details *cmd_details)
2363{
2364 struct i40e_aq_desc desc;
2365 struct i40e_aqc_macvlan *cmd =
2366 (struct i40e_aqc_macvlan *)&desc.params.raw;
2367 u16 buf_size;
2368 int status;
2369
2370 if (count == 0 || !mv_list || !hw)
2371 return -EINVAL;
2372
2373 buf_size = count * sizeof(*mv_list);
2374
2375 /* prep the rest of the request */
2376 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2377 cmd->num_addresses = cpu_to_le16(count);
2378 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2379 cmd->seid[1] = 0;
2380 cmd->seid[2] = 0;
2381
2382 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2383 if (buf_size > I40E_AQ_LARGE_BUF)
2384 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2385
2386 status = i40e_asq_send_command_atomic(hw, &desc, mv_list, buf_size,
2387 cmd_details, true);
2388
2389 return status;
2390}
2391
2392/**
2393 * i40e_aq_remove_macvlan_v2
2394 * @hw: pointer to the hw struct
2395 * @seid: VSI for the mac address
2396 * @mv_list: list of macvlans to be removed
2397 * @count: length of the list
2398 * @cmd_details: pointer to command details structure or NULL
2399 * @aq_status: pointer to Admin Queue status return value
2400 *
2401 * Remove MAC/VLAN addresses from the HW filtering.
2402 * The _v2 version returns the last Admin Queue status in aq_status
2403 * to avoid race conditions in access to hw->aq.asq_last_status.
2404 * It also calls _v2 versions of asq_send_command functions to
2405 * get the aq_status on the stack.
2406 **/
2407int
2408i40e_aq_remove_macvlan_v2(struct i40e_hw *hw, u16 seid,
2409 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2410 u16 count, struct i40e_asq_cmd_details *cmd_details,
2411 enum i40e_admin_queue_err *aq_status)
2412{
2413 struct i40e_aqc_macvlan *cmd;
2414 struct i40e_aq_desc desc;
2415 u16 buf_size;
2416
2417 if (count == 0 || !mv_list || !hw)
2418 return -EINVAL;
2419
2420 buf_size = count * sizeof(*mv_list);
2421
2422 /* prep the rest of the request */
2423 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2424 cmd = (struct i40e_aqc_macvlan *)&desc.params.raw;
2425 cmd->num_addresses = cpu_to_le16(count);
2426 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2427 cmd->seid[1] = 0;
2428 cmd->seid[2] = 0;
2429
2430 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2431 if (buf_size > I40E_AQ_LARGE_BUF)
2432 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2433
2434 return i40e_asq_send_command_atomic_v2(hw, &desc, mv_list, buf_size,
2435 cmd_details, true, aq_status);
2436}
2437
2438/**
2439 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2440 * @hw: pointer to the hw struct
2441 * @opcode: AQ opcode for add or delete mirror rule
2442 * @sw_seid: Switch SEID (to which rule refers)
2443 * @rule_type: Rule Type (ingress/egress/VLAN)
2444 * @id: Destination VSI SEID or Rule ID
2445 * @count: length of the list
2446 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2447 * @cmd_details: pointer to command details structure or NULL
2448 * @rule_id: Rule ID returned from FW
2449 * @rules_used: Number of rules used in internal switch
2450 * @rules_free: Number of rules free in internal switch
2451 *
2452 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2453 * VEBs/VEPA elements only
2454 **/
2455static int i40e_mirrorrule_op(struct i40e_hw *hw,
2456 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2457 u16 count, __le16 *mr_list,
2458 struct i40e_asq_cmd_details *cmd_details,
2459 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2460{
2461 struct i40e_aq_desc desc;
2462 struct i40e_aqc_add_delete_mirror_rule *cmd =
2463 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2464 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2465 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2466 u16 buf_size;
2467 int status;
2468
2469 buf_size = count * sizeof(*mr_list);
2470
2471 /* prep the rest of the request */
2472 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2473 cmd->seid = cpu_to_le16(sw_seid);
2474 cmd->rule_type = cpu_to_le16(rule_type &
2475 I40E_AQC_MIRROR_RULE_TYPE_MASK);
2476 cmd->num_entries = cpu_to_le16(count);
2477 /* Dest VSI for add, rule_id for delete */
2478 cmd->destination = cpu_to_le16(id);
2479 if (mr_list) {
2480 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2481 I40E_AQ_FLAG_RD));
2482 if (buf_size > I40E_AQ_LARGE_BUF)
2483 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2484 }
2485
2486 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2487 cmd_details);
2488 if (!status ||
2489 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2490 if (rule_id)
2491 *rule_id = le16_to_cpu(resp->rule_id);
2492 if (rules_used)
2493 *rules_used = le16_to_cpu(resp->mirror_rules_used);
2494 if (rules_free)
2495 *rules_free = le16_to_cpu(resp->mirror_rules_free);
2496 }
2497 return status;
2498}
2499
2500/**
2501 * i40e_aq_add_mirrorrule - add a mirror rule
2502 * @hw: pointer to the hw struct
2503 * @sw_seid: Switch SEID (to which rule refers)
2504 * @rule_type: Rule Type (ingress/egress/VLAN)
2505 * @dest_vsi: SEID of VSI to which packets will be mirrored
2506 * @count: length of the list
2507 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2508 * @cmd_details: pointer to command details structure or NULL
2509 * @rule_id: Rule ID returned from FW
2510 * @rules_used: Number of rules used in internal switch
2511 * @rules_free: Number of rules free in internal switch
2512 *
2513 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2514 **/
2515int i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2516 u16 rule_type, u16 dest_vsi, u16 count,
2517 __le16 *mr_list,
2518 struct i40e_asq_cmd_details *cmd_details,
2519 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2520{
2521 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2522 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2523 if (count == 0 || !mr_list)
2524 return -EINVAL;
2525 }
2526
2527 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2528 rule_type, dest_vsi, count, mr_list,
2529 cmd_details, rule_id, rules_used, rules_free);
2530}
2531
2532/**
2533 * i40e_aq_delete_mirrorrule - delete a mirror rule
2534 * @hw: pointer to the hw struct
2535 * @sw_seid: Switch SEID (to which rule refers)
2536 * @rule_type: Rule Type (ingress/egress/VLAN)
2537 * @count: length of the list
2538 * @rule_id: Rule ID that is returned in the receive desc as part of
2539 * add_mirrorrule.
2540 * @mr_list: list of mirrored VLAN IDs to be removed
2541 * @cmd_details: pointer to command details structure or NULL
2542 * @rules_used: Number of rules used in internal switch
2543 * @rules_free: Number of rules free in internal switch
2544 *
2545 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2546 **/
2547int i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2548 u16 rule_type, u16 rule_id, u16 count,
2549 __le16 *mr_list,
2550 struct i40e_asq_cmd_details *cmd_details,
2551 u16 *rules_used, u16 *rules_free)
2552{
2553 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
2554 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2555 /* count and mr_list shall be valid for rule_type INGRESS VLAN
2556 * mirroring. For other rule_type, count and rule_type should
2557 * not matter.
2558 */
2559 if (count == 0 || !mr_list)
2560 return -EINVAL;
2561 }
2562
2563 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2564 rule_type, rule_id, count, mr_list,
2565 cmd_details, NULL, rules_used, rules_free);
2566}
2567
2568/**
2569 * i40e_aq_send_msg_to_vf
2570 * @hw: pointer to the hardware structure
2571 * @vfid: VF id to send msg
2572 * @v_opcode: opcodes for VF-PF communication
2573 * @v_retval: return error code
2574 * @msg: pointer to the msg buffer
2575 * @msglen: msg length
2576 * @cmd_details: pointer to command details
2577 *
2578 * send msg to vf
2579 **/
2580int i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2581 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2582 struct i40e_asq_cmd_details *cmd_details)
2583{
2584 struct i40e_aq_desc desc;
2585 struct i40e_aqc_pf_vf_message *cmd =
2586 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2587 int status;
2588
2589 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2590 cmd->id = cpu_to_le32(vfid);
2591 desc.cookie_high = cpu_to_le32(v_opcode);
2592 desc.cookie_low = cpu_to_le32(v_retval);
2593 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2594 if (msglen) {
2595 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2596 I40E_AQ_FLAG_RD));
2597 if (msglen > I40E_AQ_LARGE_BUF)
2598 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2599 desc.datalen = cpu_to_le16(msglen);
2600 }
2601 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2602
2603 return status;
2604}
2605
2606/**
2607 * i40e_aq_debug_read_register
2608 * @hw: pointer to the hw struct
2609 * @reg_addr: register address
2610 * @reg_val: register value
2611 * @cmd_details: pointer to command details structure or NULL
2612 *
2613 * Read the register using the admin queue commands
2614 **/
2615int i40e_aq_debug_read_register(struct i40e_hw *hw,
2616 u32 reg_addr, u64 *reg_val,
2617 struct i40e_asq_cmd_details *cmd_details)
2618{
2619 struct i40e_aq_desc desc;
2620 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2621 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2622 int status;
2623
2624 if (reg_val == NULL)
2625 return -EINVAL;
2626
2627 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2628
2629 cmd_resp->address = cpu_to_le32(reg_addr);
2630
2631 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2632
2633 if (!status) {
2634 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2635 (u64)le32_to_cpu(cmd_resp->value_low);
2636 }
2637
2638 return status;
2639}
2640
2641/**
2642 * i40e_aq_debug_write_register
2643 * @hw: pointer to the hw struct
2644 * @reg_addr: register address
2645 * @reg_val: register value
2646 * @cmd_details: pointer to command details structure or NULL
2647 *
2648 * Write to a register using the admin queue commands
2649 **/
2650int i40e_aq_debug_write_register(struct i40e_hw *hw,
2651 u32 reg_addr, u64 reg_val,
2652 struct i40e_asq_cmd_details *cmd_details)
2653{
2654 struct i40e_aq_desc desc;
2655 struct i40e_aqc_debug_reg_read_write *cmd =
2656 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2657 int status;
2658
2659 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2660
2661 cmd->address = cpu_to_le32(reg_addr);
2662 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2663 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2664
2665 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2666
2667 return status;
2668}
2669
2670/**
2671 * i40e_aq_request_resource
2672 * @hw: pointer to the hw struct
2673 * @resource: resource id
2674 * @access: access type
2675 * @sdp_number: resource number
2676 * @timeout: the maximum time in ms that the driver may hold the resource
2677 * @cmd_details: pointer to command details structure or NULL
2678 *
2679 * requests common resource using the admin queue commands
2680 **/
2681int i40e_aq_request_resource(struct i40e_hw *hw,
2682 enum i40e_aq_resources_ids resource,
2683 enum i40e_aq_resource_access_type access,
2684 u8 sdp_number, u64 *timeout,
2685 struct i40e_asq_cmd_details *cmd_details)
2686{
2687 struct i40e_aq_desc desc;
2688 struct i40e_aqc_request_resource *cmd_resp =
2689 (struct i40e_aqc_request_resource *)&desc.params.raw;
2690 int status;
2691
2692 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2693
2694 cmd_resp->resource_id = cpu_to_le16(resource);
2695 cmd_resp->access_type = cpu_to_le16(access);
2696 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2697
2698 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2699 /* The completion specifies the maximum time in ms that the driver
2700 * may hold the resource in the Timeout field.
2701 * If the resource is held by someone else, the command completes with
2702 * busy return value and the timeout field indicates the maximum time
2703 * the current owner of the resource has to free it.
2704 */
2705 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2706 *timeout = le32_to_cpu(cmd_resp->timeout);
2707
2708 return status;
2709}
2710
2711/**
2712 * i40e_aq_release_resource
2713 * @hw: pointer to the hw struct
2714 * @resource: resource id
2715 * @sdp_number: resource number
2716 * @cmd_details: pointer to command details structure or NULL
2717 *
2718 * release common resource using the admin queue commands
2719 **/
2720int i40e_aq_release_resource(struct i40e_hw *hw,
2721 enum i40e_aq_resources_ids resource,
2722 u8 sdp_number,
2723 struct i40e_asq_cmd_details *cmd_details)
2724{
2725 struct i40e_aq_desc desc;
2726 struct i40e_aqc_request_resource *cmd =
2727 (struct i40e_aqc_request_resource *)&desc.params.raw;
2728 int status;
2729
2730 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2731
2732 cmd->resource_id = cpu_to_le16(resource);
2733 cmd->resource_number = cpu_to_le32(sdp_number);
2734
2735 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2736
2737 return status;
2738}
2739
2740/**
2741 * i40e_aq_read_nvm
2742 * @hw: pointer to the hw struct
2743 * @module_pointer: module pointer location in words from the NVM beginning
2744 * @offset: byte offset from the module beginning
2745 * @length: length of the section to be read (in bytes from the offset)
2746 * @data: command buffer (size [bytes] = length)
2747 * @last_command: tells if this is the last command in a series
2748 * @cmd_details: pointer to command details structure or NULL
2749 *
2750 * Read the NVM using the admin queue commands
2751 **/
2752int i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2753 u32 offset, u16 length, void *data,
2754 bool last_command,
2755 struct i40e_asq_cmd_details *cmd_details)
2756{
2757 struct i40e_aq_desc desc;
2758 struct i40e_aqc_nvm_update *cmd =
2759 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2760 int status;
2761
2762 /* In offset the highest byte must be zeroed. */
2763 if (offset & 0xFF000000) {
2764 status = -EINVAL;
2765 goto i40e_aq_read_nvm_exit;
2766 }
2767
2768 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2769
2770 /* If this is the last command in a series, set the proper flag. */
2771 if (last_command)
2772 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2773 cmd->module_pointer = module_pointer;
2774 cmd->offset = cpu_to_le32(offset);
2775 cmd->length = cpu_to_le16(length);
2776
2777 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2778 if (length > I40E_AQ_LARGE_BUF)
2779 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2780
2781 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2782
2783i40e_aq_read_nvm_exit:
2784 return status;
2785}
2786
2787/**
2788 * i40e_aq_erase_nvm
2789 * @hw: pointer to the hw struct
2790 * @module_pointer: module pointer location in words from the NVM beginning
2791 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2792 * @length: length of the section to be erased (expressed in 4 KB)
2793 * @last_command: tells if this is the last command in a series
2794 * @cmd_details: pointer to command details structure or NULL
2795 *
2796 * Erase the NVM sector using the admin queue commands
2797 **/
2798int i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2799 u32 offset, u16 length, bool last_command,
2800 struct i40e_asq_cmd_details *cmd_details)
2801{
2802 struct i40e_aq_desc desc;
2803 struct i40e_aqc_nvm_update *cmd =
2804 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2805 int status;
2806
2807 /* In offset the highest byte must be zeroed. */
2808 if (offset & 0xFF000000) {
2809 status = -EINVAL;
2810 goto i40e_aq_erase_nvm_exit;
2811 }
2812
2813 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2814
2815 /* If this is the last command in a series, set the proper flag. */
2816 if (last_command)
2817 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2818 cmd->module_pointer = module_pointer;
2819 cmd->offset = cpu_to_le32(offset);
2820 cmd->length = cpu_to_le16(length);
2821
2822 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2823
2824i40e_aq_erase_nvm_exit:
2825 return status;
2826}
2827
2828/**
2829 * i40e_parse_discover_capabilities
2830 * @hw: pointer to the hw struct
2831 * @buff: pointer to a buffer containing device/function capability records
2832 * @cap_count: number of capability records in the list
2833 * @list_type_opc: type of capabilities list to parse
2834 *
2835 * Parse the device/function capabilities list.
2836 **/
2837static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2838 u32 cap_count,
2839 enum i40e_admin_queue_opc list_type_opc)
2840{
2841 struct i40e_aqc_list_capabilities_element_resp *cap;
2842 u32 valid_functions, num_functions;
2843 u32 number, logical_id, phys_id;
2844 struct i40e_hw_capabilities *p;
2845 u16 id, ocp_cfg_word0;
2846 u8 major_rev;
2847 int status;
2848 u32 i = 0;
2849
2850 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2851
2852 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2853 p = &hw->dev_caps;
2854 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2855 p = &hw->func_caps;
2856 else
2857 return;
2858
2859 for (i = 0; i < cap_count; i++, cap++) {
2860 id = le16_to_cpu(cap->id);
2861 number = le32_to_cpu(cap->number);
2862 logical_id = le32_to_cpu(cap->logical_id);
2863 phys_id = le32_to_cpu(cap->phys_id);
2864 major_rev = cap->major_rev;
2865
2866 switch (id) {
2867 case I40E_AQ_CAP_ID_SWITCH_MODE:
2868 p->switch_mode = number;
2869 break;
2870 case I40E_AQ_CAP_ID_MNG_MODE:
2871 p->management_mode = number;
2872 if (major_rev > 1) {
2873 p->mng_protocols_over_mctp = logical_id;
2874 i40e_debug(hw, I40E_DEBUG_INIT,
2875 "HW Capability: Protocols over MCTP = %d\n",
2876 p->mng_protocols_over_mctp);
2877 } else {
2878 p->mng_protocols_over_mctp = 0;
2879 }
2880 break;
2881 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
2882 p->npar_enable = number;
2883 break;
2884 case I40E_AQ_CAP_ID_OS2BMC_CAP:
2885 p->os2bmc = number;
2886 break;
2887 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
2888 p->valid_functions = number;
2889 break;
2890 case I40E_AQ_CAP_ID_SRIOV:
2891 if (number == 1)
2892 p->sr_iov_1_1 = true;
2893 break;
2894 case I40E_AQ_CAP_ID_VF:
2895 p->num_vfs = number;
2896 p->vf_base_id = logical_id;
2897 break;
2898 case I40E_AQ_CAP_ID_VMDQ:
2899 if (number == 1)
2900 p->vmdq = true;
2901 break;
2902 case I40E_AQ_CAP_ID_8021QBG:
2903 if (number == 1)
2904 p->evb_802_1_qbg = true;
2905 break;
2906 case I40E_AQ_CAP_ID_8021QBR:
2907 if (number == 1)
2908 p->evb_802_1_qbh = true;
2909 break;
2910 case I40E_AQ_CAP_ID_VSI:
2911 p->num_vsis = number;
2912 break;
2913 case I40E_AQ_CAP_ID_DCB:
2914 if (number == 1) {
2915 p->dcb = true;
2916 p->enabled_tcmap = logical_id;
2917 p->maxtc = phys_id;
2918 }
2919 break;
2920 case I40E_AQ_CAP_ID_FCOE:
2921 if (number == 1)
2922 p->fcoe = true;
2923 break;
2924 case I40E_AQ_CAP_ID_ISCSI:
2925 if (number == 1)
2926 p->iscsi = true;
2927 break;
2928 case I40E_AQ_CAP_ID_RSS:
2929 p->rss = true;
2930 p->rss_table_size = number;
2931 p->rss_table_entry_width = logical_id;
2932 break;
2933 case I40E_AQ_CAP_ID_RXQ:
2934 p->num_rx_qp = number;
2935 p->base_queue = phys_id;
2936 break;
2937 case I40E_AQ_CAP_ID_TXQ:
2938 p->num_tx_qp = number;
2939 p->base_queue = phys_id;
2940 break;
2941 case I40E_AQ_CAP_ID_MSIX:
2942 p->num_msix_vectors = number;
2943 i40e_debug(hw, I40E_DEBUG_INIT,
2944 "HW Capability: MSIX vector count = %d\n",
2945 p->num_msix_vectors);
2946 break;
2947 case I40E_AQ_CAP_ID_VF_MSIX:
2948 p->num_msix_vectors_vf = number;
2949 break;
2950 case I40E_AQ_CAP_ID_FLEX10:
2951 if (major_rev == 1) {
2952 if (number == 1) {
2953 p->flex10_enable = true;
2954 p->flex10_capable = true;
2955 }
2956 } else {
2957 /* Capability revision >= 2 */
2958 if (number & 1)
2959 p->flex10_enable = true;
2960 if (number & 2)
2961 p->flex10_capable = true;
2962 }
2963 p->flex10_mode = logical_id;
2964 p->flex10_status = phys_id;
2965 break;
2966 case I40E_AQ_CAP_ID_CEM:
2967 if (number == 1)
2968 p->mgmt_cem = true;
2969 break;
2970 case I40E_AQ_CAP_ID_IWARP:
2971 if (number == 1)
2972 p->iwarp = true;
2973 break;
2974 case I40E_AQ_CAP_ID_LED:
2975 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2976 p->led[phys_id] = true;
2977 break;
2978 case I40E_AQ_CAP_ID_SDP:
2979 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2980 p->sdp[phys_id] = true;
2981 break;
2982 case I40E_AQ_CAP_ID_MDIO:
2983 if (number == 1) {
2984 p->mdio_port_num = phys_id;
2985 p->mdio_port_mode = logical_id;
2986 }
2987 break;
2988 case I40E_AQ_CAP_ID_1588:
2989 if (number == 1)
2990 p->ieee_1588 = true;
2991 break;
2992 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
2993 p->fd = true;
2994 p->fd_filters_guaranteed = number;
2995 p->fd_filters_best_effort = logical_id;
2996 break;
2997 case I40E_AQ_CAP_ID_WSR_PROT:
2998 p->wr_csr_prot = (u64)number;
2999 p->wr_csr_prot |= (u64)logical_id << 32;
3000 break;
3001 case I40E_AQ_CAP_ID_NVM_MGMT:
3002 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3003 p->sec_rev_disabled = true;
3004 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3005 p->update_disabled = true;
3006 break;
3007 default:
3008 break;
3009 }
3010 }
3011
3012 if (p->fcoe)
3013 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3014
3015 /* Software override ensuring FCoE is disabled if npar or mfp
3016 * mode because it is not supported in these modes.
3017 */
3018 if (p->npar_enable || p->flex10_enable)
3019 p->fcoe = false;
3020
3021 /* count the enabled ports (aka the "not disabled" ports) */
3022 hw->num_ports = 0;
3023 for (i = 0; i < 4; i++) {
3024 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3025 u64 port_cfg = 0;
3026
3027 /* use AQ read to get the physical register offset instead
3028 * of the port relative offset
3029 */
3030 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3031 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3032 hw->num_ports++;
3033 }
3034
3035 /* OCP cards case: if a mezz is removed the Ethernet port is at
3036 * disabled state in PRTGEN_CNF register. Additional NVM read is
3037 * needed in order to check if we are dealing with OCP card.
3038 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
3039 * physical ports results in wrong partition id calculation and thus
3040 * not supporting WoL.
3041 */
3042 if (hw->mac.type == I40E_MAC_X722) {
3043 if (!i40e_acquire_nvm(hw, I40E_RESOURCE_READ)) {
3044 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
3045 2 * I40E_SR_OCP_CFG_WORD0,
3046 sizeof(ocp_cfg_word0),
3047 &ocp_cfg_word0, true, NULL);
3048 if (!status &&
3049 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
3050 hw->num_ports = 4;
3051 i40e_release_nvm(hw);
3052 }
3053 }
3054
3055 valid_functions = p->valid_functions;
3056 num_functions = 0;
3057 while (valid_functions) {
3058 if (valid_functions & 1)
3059 num_functions++;
3060 valid_functions >>= 1;
3061 }
3062
3063 /* partition id is 1-based, and functions are evenly spread
3064 * across the ports as partitions
3065 */
3066 if (hw->num_ports != 0) {
3067 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3068 hw->num_partitions = num_functions / hw->num_ports;
3069 }
3070
3071 /* additional HW specific goodies that might
3072 * someday be HW version specific
3073 */
3074 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3075}
3076
3077/**
3078 * i40e_aq_discover_capabilities
3079 * @hw: pointer to the hw struct
3080 * @buff: a virtual buffer to hold the capabilities
3081 * @buff_size: Size of the virtual buffer
3082 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3083 * @list_type_opc: capabilities type to discover - pass in the command opcode
3084 * @cmd_details: pointer to command details structure or NULL
3085 *
3086 * Get the device capabilities descriptions from the firmware
3087 **/
3088int i40e_aq_discover_capabilities(struct i40e_hw *hw,
3089 void *buff, u16 buff_size, u16 *data_size,
3090 enum i40e_admin_queue_opc list_type_opc,
3091 struct i40e_asq_cmd_details *cmd_details)
3092{
3093 struct i40e_aqc_list_capabilites *cmd;
3094 struct i40e_aq_desc desc;
3095 int status = 0;
3096
3097 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3098
3099 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3100 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3101 status = -EINVAL;
3102 goto exit;
3103 }
3104
3105 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3106
3107 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3108 if (buff_size > I40E_AQ_LARGE_BUF)
3109 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3110
3111 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3112 *data_size = le16_to_cpu(desc.datalen);
3113
3114 if (status)
3115 goto exit;
3116
3117 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3118 list_type_opc);
3119
3120exit:
3121 return status;
3122}
3123
3124/**
3125 * i40e_aq_update_nvm
3126 * @hw: pointer to the hw struct
3127 * @module_pointer: module pointer location in words from the NVM beginning
3128 * @offset: byte offset from the module beginning
3129 * @length: length of the section to be written (in bytes from the offset)
3130 * @data: command buffer (size [bytes] = length)
3131 * @last_command: tells if this is the last command in a series
3132 * @preservation_flags: Preservation mode flags
3133 * @cmd_details: pointer to command details structure or NULL
3134 *
3135 * Update the NVM using the admin queue commands
3136 **/
3137int i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3138 u32 offset, u16 length, void *data,
3139 bool last_command, u8 preservation_flags,
3140 struct i40e_asq_cmd_details *cmd_details)
3141{
3142 struct i40e_aq_desc desc;
3143 struct i40e_aqc_nvm_update *cmd =
3144 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3145 int status;
3146
3147 /* In offset the highest byte must be zeroed. */
3148 if (offset & 0xFF000000) {
3149 status = -EINVAL;
3150 goto i40e_aq_update_nvm_exit;
3151 }
3152
3153 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3154
3155 /* If this is the last command in a series, set the proper flag. */
3156 if (last_command)
3157 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3158 if (hw->mac.type == I40E_MAC_X722) {
3159 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
3160 cmd->command_flags |=
3161 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
3162 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3163 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
3164 cmd->command_flags |=
3165 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
3166 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3167 }
3168 cmd->module_pointer = module_pointer;
3169 cmd->offset = cpu_to_le32(offset);
3170 cmd->length = cpu_to_le16(length);
3171
3172 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3173 if (length > I40E_AQ_LARGE_BUF)
3174 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3175
3176 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3177
3178i40e_aq_update_nvm_exit:
3179 return status;
3180}
3181
3182/**
3183 * i40e_aq_rearrange_nvm
3184 * @hw: pointer to the hw struct
3185 * @rearrange_nvm: defines direction of rearrangement
3186 * @cmd_details: pointer to command details structure or NULL
3187 *
3188 * Rearrange NVM structure, available only for transition FW
3189 **/
3190int i40e_aq_rearrange_nvm(struct i40e_hw *hw,
3191 u8 rearrange_nvm,
3192 struct i40e_asq_cmd_details *cmd_details)
3193{
3194 struct i40e_aqc_nvm_update *cmd;
3195 struct i40e_aq_desc desc;
3196 int status;
3197
3198 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
3199
3200 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3201
3202 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
3203 I40E_AQ_NVM_REARRANGE_TO_STRUCT);
3204
3205 if (!rearrange_nvm) {
3206 status = -EINVAL;
3207 goto i40e_aq_rearrange_nvm_exit;
3208 }
3209
3210 cmd->command_flags |= rearrange_nvm;
3211 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3212
3213i40e_aq_rearrange_nvm_exit:
3214 return status;
3215}
3216
3217/**
3218 * i40e_aq_get_lldp_mib
3219 * @hw: pointer to the hw struct
3220 * @bridge_type: type of bridge requested
3221 * @mib_type: Local, Remote or both Local and Remote MIBs
3222 * @buff: pointer to a user supplied buffer to store the MIB block
3223 * @buff_size: size of the buffer (in bytes)
3224 * @local_len : length of the returned Local LLDP MIB
3225 * @remote_len: length of the returned Remote LLDP MIB
3226 * @cmd_details: pointer to command details structure or NULL
3227 *
3228 * Requests the complete LLDP MIB (entire packet).
3229 **/
3230int i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3231 u8 mib_type, void *buff, u16 buff_size,
3232 u16 *local_len, u16 *remote_len,
3233 struct i40e_asq_cmd_details *cmd_details)
3234{
3235 struct i40e_aq_desc desc;
3236 struct i40e_aqc_lldp_get_mib *cmd =
3237 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3238 struct i40e_aqc_lldp_get_mib *resp =
3239 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3240 int status;
3241
3242 if (buff_size == 0 || !buff)
3243 return -EINVAL;
3244
3245 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3246 /* Indirect Command */
3247 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3248
3249 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3250 cmd->type |= FIELD_PREP(I40E_AQ_LLDP_BRIDGE_TYPE_MASK, bridge_type);
3251
3252 desc.datalen = cpu_to_le16(buff_size);
3253
3254 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3255 if (buff_size > I40E_AQ_LARGE_BUF)
3256 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3257
3258 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3259 if (!status) {
3260 if (local_len != NULL)
3261 *local_len = le16_to_cpu(resp->local_len);
3262 if (remote_len != NULL)
3263 *remote_len = le16_to_cpu(resp->remote_len);
3264 }
3265
3266 return status;
3267}
3268
3269/**
3270 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3271 * @hw: pointer to the hw struct
3272 * @mib_type: Local, Remote or both Local and Remote MIBs
3273 * @buff: pointer to a user supplied buffer to store the MIB block
3274 * @buff_size: size of the buffer (in bytes)
3275 * @cmd_details: pointer to command details structure or NULL
3276 *
3277 * Set the LLDP MIB.
3278 **/
3279int
3280i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3281 u8 mib_type, void *buff, u16 buff_size,
3282 struct i40e_asq_cmd_details *cmd_details)
3283{
3284 struct i40e_aqc_lldp_set_local_mib *cmd;
3285 struct i40e_aq_desc desc;
3286 int status;
3287
3288 cmd = (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3289 if (buff_size == 0 || !buff)
3290 return -EINVAL;
3291
3292 i40e_fill_default_direct_cmd_desc(&desc,
3293 i40e_aqc_opc_lldp_set_local_mib);
3294 /* Indirect Command */
3295 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3296 if (buff_size > I40E_AQ_LARGE_BUF)
3297 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3298 desc.datalen = cpu_to_le16(buff_size);
3299
3300 cmd->type = mib_type;
3301 cmd->length = cpu_to_le16(buff_size);
3302 cmd->address_high = cpu_to_le32(upper_32_bits((uintptr_t)buff));
3303 cmd->address_low = cpu_to_le32(lower_32_bits((uintptr_t)buff));
3304
3305 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3306 return status;
3307}
3308
3309/**
3310 * i40e_aq_cfg_lldp_mib_change_event
3311 * @hw: pointer to the hw struct
3312 * @enable_update: Enable or Disable event posting
3313 * @cmd_details: pointer to command details structure or NULL
3314 *
3315 * Enable or Disable posting of an event on ARQ when LLDP MIB
3316 * associated with the interface changes
3317 **/
3318int i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3319 bool enable_update,
3320 struct i40e_asq_cmd_details *cmd_details)
3321{
3322 struct i40e_aq_desc desc;
3323 struct i40e_aqc_lldp_update_mib *cmd =
3324 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3325 int status;
3326
3327 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3328
3329 if (!enable_update)
3330 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3331
3332 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3333
3334 return status;
3335}
3336
3337/**
3338 * i40e_aq_restore_lldp
3339 * @hw: pointer to the hw struct
3340 * @setting: pointer to factory setting variable or NULL
3341 * @restore: True if factory settings should be restored
3342 * @cmd_details: pointer to command details structure or NULL
3343 *
3344 * Restore LLDP Agent factory settings if @restore set to True. In other case
3345 * only returns factory setting in AQ response.
3346 **/
3347int
3348i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
3349 struct i40e_asq_cmd_details *cmd_details)
3350{
3351 struct i40e_aq_desc desc;
3352 struct i40e_aqc_lldp_restore *cmd =
3353 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
3354 int status;
3355
3356 if (!test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw->caps)) {
3357 i40e_debug(hw, I40E_DEBUG_ALL,
3358 "Restore LLDP not supported by current FW version.\n");
3359 return -ENODEV;
3360 }
3361
3362 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
3363
3364 if (restore)
3365 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
3366
3367 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3368
3369 if (setting)
3370 *setting = cmd->command & 1;
3371
3372 return status;
3373}
3374
3375/**
3376 * i40e_aq_stop_lldp
3377 * @hw: pointer to the hw struct
3378 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3379 * @persist: True if stop of LLDP should be persistent across power cycles
3380 * @cmd_details: pointer to command details structure or NULL
3381 *
3382 * Stop or Shutdown the embedded LLDP Agent
3383 **/
3384int i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3385 bool persist,
3386 struct i40e_asq_cmd_details *cmd_details)
3387{
3388 struct i40e_aq_desc desc;
3389 struct i40e_aqc_lldp_stop *cmd =
3390 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3391 int status;
3392
3393 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3394
3395 if (shutdown_agent)
3396 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3397
3398 if (persist) {
3399 if (test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw->caps))
3400 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
3401 else
3402 i40e_debug(hw, I40E_DEBUG_ALL,
3403 "Persistent Stop LLDP not supported by current FW version.\n");
3404 }
3405
3406 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3407
3408 return status;
3409}
3410
3411/**
3412 * i40e_aq_start_lldp
3413 * @hw: pointer to the hw struct
3414 * @persist: True if start of LLDP should be persistent across power cycles
3415 * @cmd_details: pointer to command details structure or NULL
3416 *
3417 * Start the embedded LLDP Agent on all ports.
3418 **/
3419int i40e_aq_start_lldp(struct i40e_hw *hw, bool persist,
3420 struct i40e_asq_cmd_details *cmd_details)
3421{
3422 struct i40e_aq_desc desc;
3423 struct i40e_aqc_lldp_start *cmd =
3424 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3425 int status;
3426
3427 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3428
3429 cmd->command = I40E_AQ_LLDP_AGENT_START;
3430
3431 if (persist) {
3432 if (test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw->caps))
3433 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
3434 else
3435 i40e_debug(hw, I40E_DEBUG_ALL,
3436 "Persistent Start LLDP not supported by current FW version.\n");
3437 }
3438
3439 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3440
3441 return status;
3442}
3443
3444/**
3445 * i40e_aq_set_dcb_parameters
3446 * @hw: pointer to the hw struct
3447 * @cmd_details: pointer to command details structure or NULL
3448 * @dcb_enable: True if DCB configuration needs to be applied
3449 *
3450 **/
3451int
3452i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
3453 struct i40e_asq_cmd_details *cmd_details)
3454{
3455 struct i40e_aq_desc desc;
3456 struct i40e_aqc_set_dcb_parameters *cmd =
3457 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
3458 int status;
3459
3460 if (!test_bit(I40E_HW_CAP_FW_LLDP_STOPPABLE, hw->caps))
3461 return -ENODEV;
3462
3463 i40e_fill_default_direct_cmd_desc(&desc,
3464 i40e_aqc_opc_set_dcb_parameters);
3465
3466 if (dcb_enable) {
3467 cmd->valid_flags = I40E_DCB_VALID;
3468 cmd->command = I40E_AQ_DCB_SET_AGENT;
3469 }
3470 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3471
3472 return status;
3473}
3474
3475/**
3476 * i40e_aq_get_cee_dcb_config
3477 * @hw: pointer to the hw struct
3478 * @buff: response buffer that stores CEE operational configuration
3479 * @buff_size: size of the buffer passed
3480 * @cmd_details: pointer to command details structure or NULL
3481 *
3482 * Get CEE DCBX mode operational configuration from firmware
3483 **/
3484int i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3485 void *buff, u16 buff_size,
3486 struct i40e_asq_cmd_details *cmd_details)
3487{
3488 struct i40e_aq_desc desc;
3489 int status;
3490
3491 if (buff_size == 0 || !buff)
3492 return -EINVAL;
3493
3494 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3495
3496 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3497 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3498 cmd_details);
3499
3500 return status;
3501}
3502
3503/**
3504 * i40e_aq_add_udp_tunnel
3505 * @hw: pointer to the hw struct
3506 * @udp_port: the UDP port to add in Host byte order
3507 * @protocol_index: protocol index type
3508 * @filter_index: pointer to filter index
3509 * @cmd_details: pointer to command details structure or NULL
3510 *
3511 * Note: Firmware expects the udp_port value to be in Little Endian format,
3512 * and this function will call cpu_to_le16 to convert from Host byte order to
3513 * Little Endian order.
3514 **/
3515int i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3516 u16 udp_port, u8 protocol_index,
3517 u8 *filter_index,
3518 struct i40e_asq_cmd_details *cmd_details)
3519{
3520 struct i40e_aq_desc desc;
3521 struct i40e_aqc_add_udp_tunnel *cmd =
3522 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3523 struct i40e_aqc_del_udp_tunnel_completion *resp =
3524 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3525 int status;
3526
3527 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3528
3529 cmd->udp_port = cpu_to_le16(udp_port);
3530 cmd->protocol_type = protocol_index;
3531
3532 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3533
3534 if (!status && filter_index)
3535 *filter_index = resp->index;
3536
3537 return status;
3538}
3539
3540/**
3541 * i40e_aq_del_udp_tunnel
3542 * @hw: pointer to the hw struct
3543 * @index: filter index
3544 * @cmd_details: pointer to command details structure or NULL
3545 **/
3546int i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3547 struct i40e_asq_cmd_details *cmd_details)
3548{
3549 struct i40e_aq_desc desc;
3550 struct i40e_aqc_remove_udp_tunnel *cmd =
3551 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3552 int status;
3553
3554 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3555
3556 cmd->index = index;
3557
3558 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3559
3560 return status;
3561}
3562
3563/**
3564 * i40e_aq_delete_element - Delete switch element
3565 * @hw: pointer to the hw struct
3566 * @seid: the SEID to delete from the switch
3567 * @cmd_details: pointer to command details structure or NULL
3568 *
3569 * This deletes a switch element from the switch.
3570 **/
3571int i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3572 struct i40e_asq_cmd_details *cmd_details)
3573{
3574 struct i40e_aq_desc desc;
3575 struct i40e_aqc_switch_seid *cmd =
3576 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3577 int status;
3578
3579 if (seid == 0)
3580 return -EINVAL;
3581
3582 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3583
3584 cmd->seid = cpu_to_le16(seid);
3585
3586 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0,
3587 cmd_details, true);
3588
3589 return status;
3590}
3591
3592/**
3593 * i40e_aq_dcb_updated - DCB Updated Command
3594 * @hw: pointer to the hw struct
3595 * @cmd_details: pointer to command details structure or NULL
3596 *
3597 * EMP will return when the shared RPB settings have been
3598 * recomputed and modified. The retval field in the descriptor
3599 * will be set to 0 when RPB is modified.
3600 **/
3601int i40e_aq_dcb_updated(struct i40e_hw *hw,
3602 struct i40e_asq_cmd_details *cmd_details)
3603{
3604 struct i40e_aq_desc desc;
3605 int status;
3606
3607 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3608
3609 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3610
3611 return status;
3612}
3613
3614/**
3615 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3616 * @hw: pointer to the hw struct
3617 * @seid: seid for the physical port/switching component/vsi
3618 * @buff: Indirect buffer to hold data parameters and response
3619 * @buff_size: Indirect buffer size
3620 * @opcode: Tx scheduler AQ command opcode
3621 * @cmd_details: pointer to command details structure or NULL
3622 *
3623 * Generic command handler for Tx scheduler AQ commands
3624 **/
3625static int i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3626 void *buff, u16 buff_size,
3627 enum i40e_admin_queue_opc opcode,
3628 struct i40e_asq_cmd_details *cmd_details)
3629{
3630 struct i40e_aq_desc desc;
3631 struct i40e_aqc_tx_sched_ind *cmd =
3632 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3633 int status;
3634 bool cmd_param_flag = false;
3635
3636 switch (opcode) {
3637 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3638 case i40e_aqc_opc_configure_vsi_tc_bw:
3639 case i40e_aqc_opc_enable_switching_comp_ets:
3640 case i40e_aqc_opc_modify_switching_comp_ets:
3641 case i40e_aqc_opc_disable_switching_comp_ets:
3642 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3643 case i40e_aqc_opc_configure_switching_comp_bw_config:
3644 cmd_param_flag = true;
3645 break;
3646 case i40e_aqc_opc_query_vsi_bw_config:
3647 case i40e_aqc_opc_query_vsi_ets_sla_config:
3648 case i40e_aqc_opc_query_switching_comp_ets_config:
3649 case i40e_aqc_opc_query_port_ets_config:
3650 case i40e_aqc_opc_query_switching_comp_bw_config:
3651 cmd_param_flag = false;
3652 break;
3653 default:
3654 return -EINVAL;
3655 }
3656
3657 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3658
3659 /* Indirect command */
3660 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3661 if (cmd_param_flag)
3662 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3663 if (buff_size > I40E_AQ_LARGE_BUF)
3664 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3665
3666 desc.datalen = cpu_to_le16(buff_size);
3667
3668 cmd->vsi_seid = cpu_to_le16(seid);
3669
3670 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3671
3672 return status;
3673}
3674
3675/**
3676 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3677 * @hw: pointer to the hw struct
3678 * @seid: VSI seid
3679 * @credit: BW limit credits (0 = disabled)
3680 * @max_credit: Max BW limit credits
3681 * @cmd_details: pointer to command details structure or NULL
3682 **/
3683int i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3684 u16 seid, u16 credit, u8 max_credit,
3685 struct i40e_asq_cmd_details *cmd_details)
3686{
3687 struct i40e_aq_desc desc;
3688 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3689 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3690 int status;
3691
3692 i40e_fill_default_direct_cmd_desc(&desc,
3693 i40e_aqc_opc_configure_vsi_bw_limit);
3694
3695 cmd->vsi_seid = cpu_to_le16(seid);
3696 cmd->credit = cpu_to_le16(credit);
3697 cmd->max_credit = max_credit;
3698
3699 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3700
3701 return status;
3702}
3703
3704/**
3705 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3706 * @hw: pointer to the hw struct
3707 * @seid: VSI seid
3708 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3709 * @cmd_details: pointer to command details structure or NULL
3710 **/
3711int i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3712 u16 seid,
3713 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3714 struct i40e_asq_cmd_details *cmd_details)
3715{
3716 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3717 i40e_aqc_opc_configure_vsi_tc_bw,
3718 cmd_details);
3719}
3720
3721/**
3722 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3723 * @hw: pointer to the hw struct
3724 * @seid: seid of the switching component connected to Physical Port
3725 * @ets_data: Buffer holding ETS parameters
3726 * @opcode: Tx scheduler AQ command opcode
3727 * @cmd_details: pointer to command details structure or NULL
3728 **/
3729int
3730i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3731 u16 seid,
3732 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3733 enum i40e_admin_queue_opc opcode,
3734 struct i40e_asq_cmd_details *cmd_details)
3735{
3736 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3737 sizeof(*ets_data), opcode, cmd_details);
3738}
3739
3740/**
3741 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3742 * @hw: pointer to the hw struct
3743 * @seid: seid of the switching component
3744 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3745 * @cmd_details: pointer to command details structure or NULL
3746 **/
3747int
3748i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3749 u16 seid,
3750 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3751 struct i40e_asq_cmd_details *cmd_details)
3752{
3753 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3754 i40e_aqc_opc_configure_switching_comp_bw_config,
3755 cmd_details);
3756}
3757
3758/**
3759 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3760 * @hw: pointer to the hw struct
3761 * @seid: seid of the VSI
3762 * @bw_data: Buffer to hold VSI BW configuration
3763 * @cmd_details: pointer to command details structure or NULL
3764 **/
3765int
3766i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3767 u16 seid,
3768 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3769 struct i40e_asq_cmd_details *cmd_details)
3770{
3771 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3772 i40e_aqc_opc_query_vsi_bw_config,
3773 cmd_details);
3774}
3775
3776/**
3777 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3778 * @hw: pointer to the hw struct
3779 * @seid: seid of the VSI
3780 * @bw_data: Buffer to hold VSI BW configuration per TC
3781 * @cmd_details: pointer to command details structure or NULL
3782 **/
3783int
3784i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3785 u16 seid,
3786 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3787 struct i40e_asq_cmd_details *cmd_details)
3788{
3789 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3790 i40e_aqc_opc_query_vsi_ets_sla_config,
3791 cmd_details);
3792}
3793
3794/**
3795 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3796 * @hw: pointer to the hw struct
3797 * @seid: seid of the switching component
3798 * @bw_data: Buffer to hold switching component's per TC BW config
3799 * @cmd_details: pointer to command details structure or NULL
3800 **/
3801int
3802i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3803 u16 seid,
3804 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3805 struct i40e_asq_cmd_details *cmd_details)
3806{
3807 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3808 i40e_aqc_opc_query_switching_comp_ets_config,
3809 cmd_details);
3810}
3811
3812/**
3813 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3814 * @hw: pointer to the hw struct
3815 * @seid: seid of the VSI or switching component connected to Physical Port
3816 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3817 * @cmd_details: pointer to command details structure or NULL
3818 **/
3819int
3820i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3821 u16 seid,
3822 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3823 struct i40e_asq_cmd_details *cmd_details)
3824{
3825 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3826 i40e_aqc_opc_query_port_ets_config,
3827 cmd_details);
3828}
3829
3830/**
3831 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3832 * @hw: pointer to the hw struct
3833 * @seid: seid of the switching component
3834 * @bw_data: Buffer to hold switching component's BW configuration
3835 * @cmd_details: pointer to command details structure or NULL
3836 **/
3837int
3838i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3839 u16 seid,
3840 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3841 struct i40e_asq_cmd_details *cmd_details)
3842{
3843 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3844 i40e_aqc_opc_query_switching_comp_bw_config,
3845 cmd_details);
3846}
3847
3848/**
3849 * i40e_validate_filter_settings
3850 * @hw: pointer to the hardware structure
3851 * @settings: Filter control settings
3852 *
3853 * Check and validate the filter control settings passed.
3854 * The function checks for the valid filter/context sizes being
3855 * passed for FCoE and PE.
3856 *
3857 * Returns 0 if the values passed are valid and within
3858 * range else returns an error.
3859 **/
3860static int
3861i40e_validate_filter_settings(struct i40e_hw *hw,
3862 struct i40e_filter_control_settings *settings)
3863{
3864 u32 fcoe_cntx_size, fcoe_filt_size;
3865 u32 fcoe_fmax;
3866 u32 val;
3867
3868 /* Validate FCoE settings passed */
3869 switch (settings->fcoe_filt_num) {
3870 case I40E_HASH_FILTER_SIZE_1K:
3871 case I40E_HASH_FILTER_SIZE_2K:
3872 case I40E_HASH_FILTER_SIZE_4K:
3873 case I40E_HASH_FILTER_SIZE_8K:
3874 case I40E_HASH_FILTER_SIZE_16K:
3875 case I40E_HASH_FILTER_SIZE_32K:
3876 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3877 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3878 break;
3879 default:
3880 return -EINVAL;
3881 }
3882
3883 switch (settings->fcoe_cntx_num) {
3884 case I40E_DMA_CNTX_SIZE_512:
3885 case I40E_DMA_CNTX_SIZE_1K:
3886 case I40E_DMA_CNTX_SIZE_2K:
3887 case I40E_DMA_CNTX_SIZE_4K:
3888 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3889 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3890 break;
3891 default:
3892 return -EINVAL;
3893 }
3894
3895 /* Validate PE settings passed */
3896 switch (settings->pe_filt_num) {
3897 case I40E_HASH_FILTER_SIZE_1K:
3898 case I40E_HASH_FILTER_SIZE_2K:
3899 case I40E_HASH_FILTER_SIZE_4K:
3900 case I40E_HASH_FILTER_SIZE_8K:
3901 case I40E_HASH_FILTER_SIZE_16K:
3902 case I40E_HASH_FILTER_SIZE_32K:
3903 case I40E_HASH_FILTER_SIZE_64K:
3904 case I40E_HASH_FILTER_SIZE_128K:
3905 case I40E_HASH_FILTER_SIZE_256K:
3906 case I40E_HASH_FILTER_SIZE_512K:
3907 case I40E_HASH_FILTER_SIZE_1M:
3908 break;
3909 default:
3910 return -EINVAL;
3911 }
3912
3913 switch (settings->pe_cntx_num) {
3914 case I40E_DMA_CNTX_SIZE_512:
3915 case I40E_DMA_CNTX_SIZE_1K:
3916 case I40E_DMA_CNTX_SIZE_2K:
3917 case I40E_DMA_CNTX_SIZE_4K:
3918 case I40E_DMA_CNTX_SIZE_8K:
3919 case I40E_DMA_CNTX_SIZE_16K:
3920 case I40E_DMA_CNTX_SIZE_32K:
3921 case I40E_DMA_CNTX_SIZE_64K:
3922 case I40E_DMA_CNTX_SIZE_128K:
3923 case I40E_DMA_CNTX_SIZE_256K:
3924 break;
3925 default:
3926 return -EINVAL;
3927 }
3928
3929 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3930 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3931 fcoe_fmax = FIELD_GET(I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK, val);
3932 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3933 return -EINVAL;
3934
3935 return 0;
3936}
3937
3938/**
3939 * i40e_set_filter_control
3940 * @hw: pointer to the hardware structure
3941 * @settings: Filter control settings
3942 *
3943 * Set the Queue Filters for PE/FCoE and enable filters required
3944 * for a single PF. It is expected that these settings are programmed
3945 * at the driver initialization time.
3946 **/
3947int i40e_set_filter_control(struct i40e_hw *hw,
3948 struct i40e_filter_control_settings *settings)
3949{
3950 u32 hash_lut_size = 0;
3951 int ret = 0;
3952 u32 val;
3953
3954 if (!settings)
3955 return -EINVAL;
3956
3957 /* Validate the input settings */
3958 ret = i40e_validate_filter_settings(hw, settings);
3959 if (ret)
3960 return ret;
3961
3962 /* Read the PF Queue Filter control register */
3963 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
3964
3965 /* Program required PE hash buckets for the PF */
3966 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3967 val |= FIELD_PREP(I40E_PFQF_CTL_0_PEHSIZE_MASK, settings->pe_filt_num);
3968 /* Program required PE contexts for the PF */
3969 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3970 val |= FIELD_PREP(I40E_PFQF_CTL_0_PEDSIZE_MASK, settings->pe_cntx_num);
3971
3972 /* Program required FCoE hash buckets for the PF */
3973 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3974 val |= FIELD_PREP(I40E_PFQF_CTL_0_PFFCHSIZE_MASK,
3975 settings->fcoe_filt_num);
3976 /* Program required FCoE DDP contexts for the PF */
3977 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3978 val |= FIELD_PREP(I40E_PFQF_CTL_0_PFFCDSIZE_MASK,
3979 settings->fcoe_cntx_num);
3980
3981 /* Program Hash LUT size for the PF */
3982 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3983 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3984 hash_lut_size = 1;
3985 val |= FIELD_PREP(I40E_PFQF_CTL_0_HASHLUTSIZE_MASK, hash_lut_size);
3986
3987 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3988 if (settings->enable_fdir)
3989 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3990 if (settings->enable_ethtype)
3991 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3992 if (settings->enable_macvlan)
3993 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3994
3995 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
3996
3997 return 0;
3998}
3999
4000/**
4001 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4002 * @hw: pointer to the hw struct
4003 * @mac_addr: MAC address to use in the filter
4004 * @ethtype: Ethertype to use in the filter
4005 * @flags: Flags that needs to be applied to the filter
4006 * @vsi_seid: seid of the control VSI
4007 * @queue: VSI queue number to send the packet to
4008 * @is_add: Add control packet filter if True else remove
4009 * @stats: Structure to hold information on control filter counts
4010 * @cmd_details: pointer to command details structure or NULL
4011 *
4012 * This command will Add or Remove control packet filter for a control VSI.
4013 * In return it will update the total number of perfect filter count in
4014 * the stats member.
4015 **/
4016int i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4017 u8 *mac_addr, u16 ethtype, u16 flags,
4018 u16 vsi_seid, u16 queue, bool is_add,
4019 struct i40e_control_filter_stats *stats,
4020 struct i40e_asq_cmd_details *cmd_details)
4021{
4022 struct i40e_aq_desc desc;
4023 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4024 (struct i40e_aqc_add_remove_control_packet_filter *)
4025 &desc.params.raw;
4026 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4027 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4028 &desc.params.raw;
4029 int status;
4030
4031 if (vsi_seid == 0)
4032 return -EINVAL;
4033
4034 if (is_add) {
4035 i40e_fill_default_direct_cmd_desc(&desc,
4036 i40e_aqc_opc_add_control_packet_filter);
4037 cmd->queue = cpu_to_le16(queue);
4038 } else {
4039 i40e_fill_default_direct_cmd_desc(&desc,
4040 i40e_aqc_opc_remove_control_packet_filter);
4041 }
4042
4043 if (mac_addr)
4044 ether_addr_copy(cmd->mac, mac_addr);
4045
4046 cmd->etype = cpu_to_le16(ethtype);
4047 cmd->flags = cpu_to_le16(flags);
4048 cmd->seid = cpu_to_le16(vsi_seid);
4049
4050 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4051
4052 if (!status && stats) {
4053 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
4054 stats->etype_used = le16_to_cpu(resp->etype_used);
4055 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
4056 stats->etype_free = le16_to_cpu(resp->etype_free);
4057 }
4058
4059 return status;
4060}
4061
4062/**
4063 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4064 * @hw: pointer to the hw struct
4065 * @seid: VSI seid to add ethertype filter from
4066 **/
4067void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4068 u16 seid)
4069{
4070#define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4071 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4072 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4073 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4074 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4075 int status;
4076
4077 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4078 seid, 0, true, NULL,
4079 NULL);
4080 if (status)
4081 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4082}
4083
4084/**
4085 * i40e_aq_alternate_read
4086 * @hw: pointer to the hardware structure
4087 * @reg_addr0: address of first dword to be read
4088 * @reg_val0: pointer for data read from 'reg_addr0'
4089 * @reg_addr1: address of second dword to be read
4090 * @reg_val1: pointer for data read from 'reg_addr1'
4091 *
4092 * Read one or two dwords from alternate structure. Fields are indicated
4093 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4094 * is not passed then only register at 'reg_addr0' is read.
4095 *
4096 **/
4097static int i40e_aq_alternate_read(struct i40e_hw *hw,
4098 u32 reg_addr0, u32 *reg_val0,
4099 u32 reg_addr1, u32 *reg_val1)
4100{
4101 struct i40e_aq_desc desc;
4102 struct i40e_aqc_alternate_write *cmd_resp =
4103 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4104 int status;
4105
4106 if (!reg_val0)
4107 return -EINVAL;
4108
4109 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4110 cmd_resp->address0 = cpu_to_le32(reg_addr0);
4111 cmd_resp->address1 = cpu_to_le32(reg_addr1);
4112
4113 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4114
4115 if (!status) {
4116 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4117
4118 if (reg_val1)
4119 *reg_val1 = le32_to_cpu(cmd_resp->data1);
4120 }
4121
4122 return status;
4123}
4124
4125/**
4126 * i40e_aq_suspend_port_tx
4127 * @hw: pointer to the hardware structure
4128 * @seid: port seid
4129 * @cmd_details: pointer to command details structure or NULL
4130 *
4131 * Suspend port's Tx traffic
4132 **/
4133int i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid,
4134 struct i40e_asq_cmd_details *cmd_details)
4135{
4136 struct i40e_aqc_tx_sched_ind *cmd;
4137 struct i40e_aq_desc desc;
4138 int status;
4139
4140 cmd = (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4141 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_suspend_port_tx);
4142 cmd->vsi_seid = cpu_to_le16(seid);
4143 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4144
4145 return status;
4146}
4147
4148/**
4149 * i40e_aq_resume_port_tx
4150 * @hw: pointer to the hardware structure
4151 * @cmd_details: pointer to command details structure or NULL
4152 *
4153 * Resume port's Tx traffic
4154 **/
4155int i40e_aq_resume_port_tx(struct i40e_hw *hw,
4156 struct i40e_asq_cmd_details *cmd_details)
4157{
4158 struct i40e_aq_desc desc;
4159 int status;
4160
4161 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4162
4163 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4164
4165 return status;
4166}
4167
4168/**
4169 * i40e_set_pci_config_data - store PCI bus info
4170 * @hw: pointer to hardware structure
4171 * @link_status: the link status word from PCI config space
4172 *
4173 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4174 **/
4175void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4176{
4177 hw->bus.type = i40e_bus_type_pci_express;
4178
4179 switch (link_status & PCI_EXP_LNKSTA_NLW) {
4180 case PCI_EXP_LNKSTA_NLW_X1:
4181 hw->bus.width = i40e_bus_width_pcie_x1;
4182 break;
4183 case PCI_EXP_LNKSTA_NLW_X2:
4184 hw->bus.width = i40e_bus_width_pcie_x2;
4185 break;
4186 case PCI_EXP_LNKSTA_NLW_X4:
4187 hw->bus.width = i40e_bus_width_pcie_x4;
4188 break;
4189 case PCI_EXP_LNKSTA_NLW_X8:
4190 hw->bus.width = i40e_bus_width_pcie_x8;
4191 break;
4192 default:
4193 hw->bus.width = i40e_bus_width_unknown;
4194 break;
4195 }
4196
4197 switch (link_status & PCI_EXP_LNKSTA_CLS) {
4198 case PCI_EXP_LNKSTA_CLS_2_5GB:
4199 hw->bus.speed = i40e_bus_speed_2500;
4200 break;
4201 case PCI_EXP_LNKSTA_CLS_5_0GB:
4202 hw->bus.speed = i40e_bus_speed_5000;
4203 break;
4204 case PCI_EXP_LNKSTA_CLS_8_0GB:
4205 hw->bus.speed = i40e_bus_speed_8000;
4206 break;
4207 default:
4208 hw->bus.speed = i40e_bus_speed_unknown;
4209 break;
4210 }
4211}
4212
4213/**
4214 * i40e_aq_debug_dump
4215 * @hw: pointer to the hardware structure
4216 * @cluster_id: specific cluster to dump
4217 * @table_id: table id within cluster
4218 * @start_index: index of line in the block to read
4219 * @buff_size: dump buffer size
4220 * @buff: dump buffer
4221 * @ret_buff_size: actual buffer size returned
4222 * @ret_next_table: next block to read
4223 * @ret_next_index: next index to read
4224 * @cmd_details: pointer to command details structure or NULL
4225 *
4226 * Dump internal FW/HW data for debug purposes.
4227 *
4228 **/
4229int i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4230 u8 table_id, u32 start_index, u16 buff_size,
4231 void *buff, u16 *ret_buff_size,
4232 u8 *ret_next_table, u32 *ret_next_index,
4233 struct i40e_asq_cmd_details *cmd_details)
4234{
4235 struct i40e_aq_desc desc;
4236 struct i40e_aqc_debug_dump_internals *cmd =
4237 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4238 struct i40e_aqc_debug_dump_internals *resp =
4239 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4240 int status;
4241
4242 if (buff_size == 0 || !buff)
4243 return -EINVAL;
4244
4245 i40e_fill_default_direct_cmd_desc(&desc,
4246 i40e_aqc_opc_debug_dump_internals);
4247 /* Indirect Command */
4248 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4249 if (buff_size > I40E_AQ_LARGE_BUF)
4250 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4251
4252 cmd->cluster_id = cluster_id;
4253 cmd->table_id = table_id;
4254 cmd->idx = cpu_to_le32(start_index);
4255
4256 desc.datalen = cpu_to_le16(buff_size);
4257
4258 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4259 if (!status) {
4260 if (ret_buff_size)
4261 *ret_buff_size = le16_to_cpu(desc.datalen);
4262 if (ret_next_table)
4263 *ret_next_table = resp->table_id;
4264 if (ret_next_index)
4265 *ret_next_index = le32_to_cpu(resp->idx);
4266 }
4267
4268 return status;
4269}
4270
4271/**
4272 * i40e_read_bw_from_alt_ram
4273 * @hw: pointer to the hardware structure
4274 * @max_bw: pointer for max_bw read
4275 * @min_bw: pointer for min_bw read
4276 * @min_valid: pointer for bool that is true if min_bw is a valid value
4277 * @max_valid: pointer for bool that is true if max_bw is a valid value
4278 *
4279 * Read bw from the alternate ram for the given pf
4280 **/
4281int i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4282 u32 *max_bw, u32 *min_bw,
4283 bool *min_valid, bool *max_valid)
4284{
4285 u32 max_bw_addr, min_bw_addr;
4286 int status;
4287
4288 /* Calculate the address of the min/max bw registers */
4289 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4290 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4291 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4292 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4293 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4294 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4295
4296 /* Read the bandwidths from alt ram */
4297 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4298 min_bw_addr, min_bw);
4299
4300 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4301 *min_valid = true;
4302 else
4303 *min_valid = false;
4304
4305 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4306 *max_valid = true;
4307 else
4308 *max_valid = false;
4309
4310 return status;
4311}
4312
4313/**
4314 * i40e_aq_configure_partition_bw
4315 * @hw: pointer to the hardware structure
4316 * @bw_data: Buffer holding valid pfs and bw limits
4317 * @cmd_details: pointer to command details
4318 *
4319 * Configure partitions guaranteed/max bw
4320 **/
4321int
4322i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4323 struct i40e_aqc_configure_partition_bw_data *bw_data,
4324 struct i40e_asq_cmd_details *cmd_details)
4325{
4326 u16 bwd_size = sizeof(*bw_data);
4327 struct i40e_aq_desc desc;
4328 int status;
4329
4330 i40e_fill_default_direct_cmd_desc(&desc,
4331 i40e_aqc_opc_configure_partition_bw);
4332
4333 /* Indirect command */
4334 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4335 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4336
4337 if (bwd_size > I40E_AQ_LARGE_BUF)
4338 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4339
4340 desc.datalen = cpu_to_le16(bwd_size);
4341
4342 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4343 cmd_details);
4344
4345 return status;
4346}
4347
4348/**
4349 * i40e_read_phy_register_clause22
4350 * @hw: pointer to the HW structure
4351 * @reg: register address in the page
4352 * @phy_addr: PHY address on MDIO interface
4353 * @value: PHY register value
4354 *
4355 * Reads specified PHY register value
4356 **/
4357int i40e_read_phy_register_clause22(struct i40e_hw *hw,
4358 u16 reg, u8 phy_addr, u16 *value)
4359{
4360 u8 port_num = (u8)hw->func_caps.mdio_port_num;
4361 int status = -EIO;
4362 u32 command = 0;
4363 u16 retry = 1000;
4364
4365 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4366 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4367 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
4368 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4369 (I40E_GLGEN_MSCA_MDICMD_MASK);
4370 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4371 do {
4372 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4373 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4374 status = 0;
4375 break;
4376 }
4377 udelay(10);
4378 retry--;
4379 } while (retry);
4380
4381 if (status) {
4382 i40e_debug(hw, I40E_DEBUG_PHY,
4383 "PHY: Can't write command to external PHY.\n");
4384 } else {
4385 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4386 *value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command);
4387 }
4388
4389 return status;
4390}
4391
4392/**
4393 * i40e_write_phy_register_clause22
4394 * @hw: pointer to the HW structure
4395 * @reg: register address in the page
4396 * @phy_addr: PHY address on MDIO interface
4397 * @value: PHY register value
4398 *
4399 * Writes specified PHY register value
4400 **/
4401int i40e_write_phy_register_clause22(struct i40e_hw *hw,
4402 u16 reg, u8 phy_addr, u16 value)
4403{
4404 u8 port_num = (u8)hw->func_caps.mdio_port_num;
4405 int status = -EIO;
4406 u32 command = 0;
4407 u16 retry = 1000;
4408
4409 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4410 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4411
4412 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4413 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4414 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
4415 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4416 (I40E_GLGEN_MSCA_MDICMD_MASK);
4417
4418 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4419 do {
4420 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4421 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4422 status = 0;
4423 break;
4424 }
4425 udelay(10);
4426 retry--;
4427 } while (retry);
4428
4429 return status;
4430}
4431
4432/**
4433 * i40e_read_phy_register_clause45
4434 * @hw: pointer to the HW structure
4435 * @page: registers page number
4436 * @reg: register address in the page
4437 * @phy_addr: PHY address on MDIO interface
4438 * @value: PHY register value
4439 *
4440 * Reads specified PHY register value
4441 **/
4442int i40e_read_phy_register_clause45(struct i40e_hw *hw,
4443 u8 page, u16 reg, u8 phy_addr, u16 *value)
4444{
4445 u8 port_num = hw->func_caps.mdio_port_num;
4446 int status = -EIO;
4447 u32 command = 0;
4448 u16 retry = 1000;
4449
4450 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4451 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4452 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4453 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4454 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4455 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4456 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4457 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4458 do {
4459 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4460 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4461 status = 0;
4462 break;
4463 }
4464 usleep_range(10, 20);
4465 retry--;
4466 } while (retry);
4467
4468 if (status) {
4469 i40e_debug(hw, I40E_DEBUG_PHY,
4470 "PHY: Can't write command to external PHY.\n");
4471 goto phy_read_end;
4472 }
4473
4474 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4475 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4476 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
4477 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4478 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4479 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4480 status = -EIO;
4481 retry = 1000;
4482 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4483 do {
4484 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4485 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4486 status = 0;
4487 break;
4488 }
4489 usleep_range(10, 20);
4490 retry--;
4491 } while (retry);
4492
4493 if (!status) {
4494 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4495 *value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command);
4496 } else {
4497 i40e_debug(hw, I40E_DEBUG_PHY,
4498 "PHY: Can't read register value from external PHY.\n");
4499 }
4500
4501phy_read_end:
4502 return status;
4503}
4504
4505/**
4506 * i40e_write_phy_register_clause45
4507 * @hw: pointer to the HW structure
4508 * @page: registers page number
4509 * @reg: register address in the page
4510 * @phy_addr: PHY address on MDIO interface
4511 * @value: PHY register value
4512 *
4513 * Writes value to specified PHY register
4514 **/
4515int i40e_write_phy_register_clause45(struct i40e_hw *hw,
4516 u8 page, u16 reg, u8 phy_addr, u16 value)
4517{
4518 u8 port_num = hw->func_caps.mdio_port_num;
4519 int status = -EIO;
4520 u16 retry = 1000;
4521 u32 command = 0;
4522
4523 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4524 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4525 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4526 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4527 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4528 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4529 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4530 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4531 do {
4532 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4533 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4534 status = 0;
4535 break;
4536 }
4537 usleep_range(10, 20);
4538 retry--;
4539 } while (retry);
4540 if (status) {
4541 i40e_debug(hw, I40E_DEBUG_PHY,
4542 "PHY: Can't write command to external PHY.\n");
4543 goto phy_write_end;
4544 }
4545
4546 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4547 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4548
4549 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4550 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4551 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
4552 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4553 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4554 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4555 status = -EIO;
4556 retry = 1000;
4557 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4558 do {
4559 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4560 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4561 status = 0;
4562 break;
4563 }
4564 usleep_range(10, 20);
4565 retry--;
4566 } while (retry);
4567
4568phy_write_end:
4569 return status;
4570}
4571
4572/**
4573 * i40e_write_phy_register
4574 * @hw: pointer to the HW structure
4575 * @page: registers page number
4576 * @reg: register address in the page
4577 * @phy_addr: PHY address on MDIO interface
4578 * @value: PHY register value
4579 *
4580 * Writes value to specified PHY register
4581 **/
4582int i40e_write_phy_register(struct i40e_hw *hw,
4583 u8 page, u16 reg, u8 phy_addr, u16 value)
4584{
4585 int status;
4586
4587 switch (hw->device_id) {
4588 case I40E_DEV_ID_1G_BASE_T_X722:
4589 status = i40e_write_phy_register_clause22(hw, reg, phy_addr,
4590 value);
4591 break;
4592 case I40E_DEV_ID_1G_BASE_T_BC:
4593 case I40E_DEV_ID_5G_BASE_T_BC:
4594 case I40E_DEV_ID_10G_BASE_T:
4595 case I40E_DEV_ID_10G_BASE_T4:
4596 case I40E_DEV_ID_10G_BASE_T_BC:
4597 case I40E_DEV_ID_10G_BASE_T_X722:
4598 case I40E_DEV_ID_25G_B:
4599 case I40E_DEV_ID_25G_SFP28:
4600 status = i40e_write_phy_register_clause45(hw, page, reg,
4601 phy_addr, value);
4602 break;
4603 default:
4604 status = -EIO;
4605 break;
4606 }
4607
4608 return status;
4609}
4610
4611/**
4612 * i40e_read_phy_register
4613 * @hw: pointer to the HW structure
4614 * @page: registers page number
4615 * @reg: register address in the page
4616 * @phy_addr: PHY address on MDIO interface
4617 * @value: PHY register value
4618 *
4619 * Reads specified PHY register value
4620 **/
4621int i40e_read_phy_register(struct i40e_hw *hw,
4622 u8 page, u16 reg, u8 phy_addr, u16 *value)
4623{
4624 int status;
4625
4626 switch (hw->device_id) {
4627 case I40E_DEV_ID_1G_BASE_T_X722:
4628 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
4629 value);
4630 break;
4631 case I40E_DEV_ID_1G_BASE_T_BC:
4632 case I40E_DEV_ID_5G_BASE_T_BC:
4633 case I40E_DEV_ID_10G_BASE_T:
4634 case I40E_DEV_ID_10G_BASE_T4:
4635 case I40E_DEV_ID_10G_BASE_T_BC:
4636 case I40E_DEV_ID_10G_BASE_T_X722:
4637 case I40E_DEV_ID_25G_B:
4638 case I40E_DEV_ID_25G_SFP28:
4639 status = i40e_read_phy_register_clause45(hw, page, reg,
4640 phy_addr, value);
4641 break;
4642 default:
4643 status = -EIO;
4644 break;
4645 }
4646
4647 return status;
4648}
4649
4650/**
4651 * i40e_get_phy_address
4652 * @hw: pointer to the HW structure
4653 * @dev_num: PHY port num that address we want
4654 *
4655 * Gets PHY address for current port
4656 **/
4657u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4658{
4659 u8 port_num = hw->func_caps.mdio_port_num;
4660 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4661
4662 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4663}
4664
4665/**
4666 * i40e_blink_phy_link_led
4667 * @hw: pointer to the HW structure
4668 * @time: time how long led will blinks in secs
4669 * @interval: gap between LED on and off in msecs
4670 *
4671 * Blinks PHY link LED
4672 **/
4673int i40e_blink_phy_link_led(struct i40e_hw *hw,
4674 u32 time, u32 interval)
4675{
4676 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
4677 u16 gpio_led_port;
4678 u8 phy_addr = 0;
4679 int status = 0;
4680 u16 led_ctl;
4681 u8 port_num;
4682 u16 led_reg;
4683 u32 i;
4684
4685 i = rd32(hw, I40E_PFGEN_PORTNUM);
4686 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4687 phy_addr = i40e_get_phy_address(hw, port_num);
4688
4689 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4690 led_addr++) {
4691 status = i40e_read_phy_register_clause45(hw,
4692 I40E_PHY_COM_REG_PAGE,
4693 led_addr, phy_addr,
4694 &led_reg);
4695 if (status)
4696 goto phy_blinking_end;
4697 led_ctl = led_reg;
4698 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4699 led_reg = 0;
4700 status = i40e_write_phy_register_clause45(hw,
4701 I40E_PHY_COM_REG_PAGE,
4702 led_addr, phy_addr,
4703 led_reg);
4704 if (status)
4705 goto phy_blinking_end;
4706 break;
4707 }
4708 }
4709
4710 if (time > 0 && interval > 0) {
4711 for (i = 0; i < time * 1000; i += interval) {
4712 status = i40e_read_phy_register_clause45(hw,
4713 I40E_PHY_COM_REG_PAGE,
4714 led_addr, phy_addr, &led_reg);
4715 if (status)
4716 goto restore_config;
4717 if (led_reg & I40E_PHY_LED_MANUAL_ON)
4718 led_reg = 0;
4719 else
4720 led_reg = I40E_PHY_LED_MANUAL_ON;
4721 status = i40e_write_phy_register_clause45(hw,
4722 I40E_PHY_COM_REG_PAGE,
4723 led_addr, phy_addr, led_reg);
4724 if (status)
4725 goto restore_config;
4726 msleep(interval);
4727 }
4728 }
4729
4730restore_config:
4731 status = i40e_write_phy_register_clause45(hw,
4732 I40E_PHY_COM_REG_PAGE,
4733 led_addr, phy_addr, led_ctl);
4734
4735phy_blinking_end:
4736 return status;
4737}
4738
4739/**
4740 * i40e_led_get_reg - read LED register
4741 * @hw: pointer to the HW structure
4742 * @led_addr: LED register address
4743 * @reg_val: read register value
4744 **/
4745static int i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
4746 u32 *reg_val)
4747{
4748 u8 phy_addr = 0;
4749 u8 port_num;
4750 int status;
4751 u32 i;
4752
4753 *reg_val = 0;
4754 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) {
4755 status =
4756 i40e_aq_get_phy_register(hw,
4757 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
4758 I40E_PHY_COM_REG_PAGE, true,
4759 I40E_PHY_LED_PROV_REG_1,
4760 reg_val, NULL);
4761 } else {
4762 i = rd32(hw, I40E_PFGEN_PORTNUM);
4763 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4764 phy_addr = i40e_get_phy_address(hw, port_num);
4765 status = i40e_read_phy_register_clause45(hw,
4766 I40E_PHY_COM_REG_PAGE,
4767 led_addr, phy_addr,
4768 (u16 *)reg_val);
4769 }
4770 return status;
4771}
4772
4773/**
4774 * i40e_led_set_reg - write LED register
4775 * @hw: pointer to the HW structure
4776 * @led_addr: LED register address
4777 * @reg_val: register value to write
4778 **/
4779static int i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
4780 u32 reg_val)
4781{
4782 u8 phy_addr = 0;
4783 u8 port_num;
4784 int status;
4785 u32 i;
4786
4787 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) {
4788 status =
4789 i40e_aq_set_phy_register(hw,
4790 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
4791 I40E_PHY_COM_REG_PAGE, true,
4792 I40E_PHY_LED_PROV_REG_1,
4793 reg_val, NULL);
4794 } else {
4795 i = rd32(hw, I40E_PFGEN_PORTNUM);
4796 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4797 phy_addr = i40e_get_phy_address(hw, port_num);
4798 status = i40e_write_phy_register_clause45(hw,
4799 I40E_PHY_COM_REG_PAGE,
4800 led_addr, phy_addr,
4801 (u16)reg_val);
4802 }
4803
4804 return status;
4805}
4806
4807/**
4808 * i40e_led_get_phy - return current on/off mode
4809 * @hw: pointer to the hw struct
4810 * @led_addr: address of led register to use
4811 * @val: original value of register to use
4812 *
4813 **/
4814int i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
4815 u16 *val)
4816{
4817 u16 gpio_led_port;
4818 u8 phy_addr = 0;
4819 u32 reg_val_aq;
4820 int status = 0;
4821 u16 temp_addr;
4822 u16 reg_val;
4823 u8 port_num;
4824 u32 i;
4825
4826 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) {
4827 status =
4828 i40e_aq_get_phy_register(hw,
4829 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
4830 I40E_PHY_COM_REG_PAGE, true,
4831 I40E_PHY_LED_PROV_REG_1,
4832 ®_val_aq, NULL);
4833 if (status == 0)
4834 *val = (u16)reg_val_aq;
4835 return status;
4836 }
4837 temp_addr = I40E_PHY_LED_PROV_REG_1;
4838 i = rd32(hw, I40E_PFGEN_PORTNUM);
4839 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4840 phy_addr = i40e_get_phy_address(hw, port_num);
4841
4842 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4843 temp_addr++) {
4844 status = i40e_read_phy_register_clause45(hw,
4845 I40E_PHY_COM_REG_PAGE,
4846 temp_addr, phy_addr,
4847 ®_val);
4848 if (status)
4849 return status;
4850 *val = reg_val;
4851 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
4852 *led_addr = temp_addr;
4853 break;
4854 }
4855 }
4856 return status;
4857}
4858
4859/**
4860 * i40e_led_set_phy
4861 * @hw: pointer to the HW structure
4862 * @on: true or false
4863 * @led_addr: address of led register to use
4864 * @mode: original val plus bit for set or ignore
4865 *
4866 * Set led's on or off when controlled by the PHY
4867 *
4868 **/
4869int i40e_led_set_phy(struct i40e_hw *hw, bool on,
4870 u16 led_addr, u32 mode)
4871{
4872 u32 led_ctl = 0;
4873 u32 led_reg = 0;
4874 int status = 0;
4875
4876 status = i40e_led_get_reg(hw, led_addr, &led_reg);
4877 if (status)
4878 return status;
4879 led_ctl = led_reg;
4880 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4881 led_reg = 0;
4882 status = i40e_led_set_reg(hw, led_addr, led_reg);
4883 if (status)
4884 return status;
4885 }
4886 status = i40e_led_get_reg(hw, led_addr, &led_reg);
4887 if (status)
4888 goto restore_config;
4889 if (on)
4890 led_reg = I40E_PHY_LED_MANUAL_ON;
4891 else
4892 led_reg = 0;
4893
4894 status = i40e_led_set_reg(hw, led_addr, led_reg);
4895 if (status)
4896 goto restore_config;
4897 if (mode & I40E_PHY_LED_MODE_ORIG) {
4898 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
4899 status = i40e_led_set_reg(hw, led_addr, led_ctl);
4900 }
4901 return status;
4902
4903restore_config:
4904 status = i40e_led_set_reg(hw, led_addr, led_ctl);
4905 return status;
4906}
4907
4908/**
4909 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
4910 * @hw: pointer to the hw struct
4911 * @reg_addr: register address
4912 * @reg_val: ptr to register value
4913 * @cmd_details: pointer to command details structure or NULL
4914 *
4915 * Use the firmware to read the Rx control register,
4916 * especially useful if the Rx unit is under heavy pressure
4917 **/
4918int i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
4919 u32 reg_addr, u32 *reg_val,
4920 struct i40e_asq_cmd_details *cmd_details)
4921{
4922 struct i40e_aq_desc desc;
4923 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
4924 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4925 int status;
4926
4927 if (!reg_val)
4928 return -EINVAL;
4929
4930 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
4931
4932 cmd_resp->address = cpu_to_le32(reg_addr);
4933
4934 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4935
4936 if (status == 0)
4937 *reg_val = le32_to_cpu(cmd_resp->value);
4938
4939 return status;
4940}
4941
4942/**
4943 * i40e_read_rx_ctl - read from an Rx control register
4944 * @hw: pointer to the hw struct
4945 * @reg_addr: register address
4946 **/
4947u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
4948{
4949 bool use_register = false;
4950 int status = 0;
4951 int retry = 5;
4952 u32 val = 0;
4953
4954 if (i40e_is_aq_api_ver_lt(hw, 1, 5) || hw->mac.type == I40E_MAC_X722)
4955 use_register = true;
4956
4957 if (!use_register) {
4958do_retry:
4959 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
4960 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
4961 usleep_range(1000, 2000);
4962 retry--;
4963 goto do_retry;
4964 }
4965 }
4966
4967 /* if the AQ access failed, try the old-fashioned way */
4968 if (status || use_register)
4969 val = rd32(hw, reg_addr);
4970
4971 return val;
4972}
4973
4974/**
4975 * i40e_aq_rx_ctl_write_register
4976 * @hw: pointer to the hw struct
4977 * @reg_addr: register address
4978 * @reg_val: register value
4979 * @cmd_details: pointer to command details structure or NULL
4980 *
4981 * Use the firmware to write to an Rx control register,
4982 * especially useful if the Rx unit is under heavy pressure
4983 **/
4984int i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
4985 u32 reg_addr, u32 reg_val,
4986 struct i40e_asq_cmd_details *cmd_details)
4987{
4988 struct i40e_aq_desc desc;
4989 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
4990 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4991 int status;
4992
4993 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
4994
4995 cmd->address = cpu_to_le32(reg_addr);
4996 cmd->value = cpu_to_le32(reg_val);
4997
4998 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4999
5000 return status;
5001}
5002
5003/**
5004 * i40e_write_rx_ctl - write to an Rx control register
5005 * @hw: pointer to the hw struct
5006 * @reg_addr: register address
5007 * @reg_val: register value
5008 **/
5009void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
5010{
5011 bool use_register = false;
5012 int status = 0;
5013 int retry = 5;
5014
5015 if (i40e_is_aq_api_ver_lt(hw, 1, 5) || hw->mac.type == I40E_MAC_X722)
5016 use_register = true;
5017
5018 if (!use_register) {
5019do_retry:
5020 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
5021 reg_val, NULL);
5022 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5023 usleep_range(1000, 2000);
5024 retry--;
5025 goto do_retry;
5026 }
5027 }
5028
5029 /* if the AQ access failed, try the old-fashioned way */
5030 if (status || use_register)
5031 wr32(hw, reg_addr, reg_val);
5032}
5033
5034/**
5035 * i40e_mdio_if_number_selection - MDIO I/F number selection
5036 * @hw: pointer to the hw struct
5037 * @set_mdio: use MDIO I/F number specified by mdio_num
5038 * @mdio_num: MDIO I/F number
5039 * @cmd: pointer to PHY Register command structure
5040 **/
5041static void i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio,
5042 u8 mdio_num,
5043 struct i40e_aqc_phy_register_access *cmd)
5044{
5045 if (!set_mdio ||
5046 cmd->phy_interface != I40E_AQ_PHY_REG_ACCESS_EXTERNAL)
5047 return;
5048
5049 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS_EXTENDED, hw->caps)) {
5050 cmd->cmd_flags |=
5051 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER |
5052 FIELD_PREP(I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK,
5053 mdio_num);
5054 } else {
5055 i40e_debug(hw, I40E_DEBUG_PHY, "MDIO I/F number selection not supported by current FW version.\n");
5056 }
5057}
5058
5059/**
5060 * i40e_aq_set_phy_register_ext
5061 * @hw: pointer to the hw struct
5062 * @phy_select: select which phy should be accessed
5063 * @dev_addr: PHY device address
5064 * @page_change: flag to indicate if phy page should be updated
5065 * @set_mdio: use MDIO I/F number specified by mdio_num
5066 * @mdio_num: MDIO I/F number
5067 * @reg_addr: PHY register address
5068 * @reg_val: new register value
5069 * @cmd_details: pointer to command details structure or NULL
5070 *
5071 * Write the external PHY register.
5072 * NOTE: In common cases MDIO I/F number should not be changed, thats why you
5073 * may use simple wrapper i40e_aq_set_phy_register.
5074 **/
5075int i40e_aq_set_phy_register_ext(struct i40e_hw *hw,
5076 u8 phy_select, u8 dev_addr, bool page_change,
5077 bool set_mdio, u8 mdio_num,
5078 u32 reg_addr, u32 reg_val,
5079 struct i40e_asq_cmd_details *cmd_details)
5080{
5081 struct i40e_aq_desc desc;
5082 struct i40e_aqc_phy_register_access *cmd =
5083 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5084 int status;
5085
5086 i40e_fill_default_direct_cmd_desc(&desc,
5087 i40e_aqc_opc_set_phy_register);
5088
5089 cmd->phy_interface = phy_select;
5090 cmd->dev_address = dev_addr;
5091 cmd->reg_address = cpu_to_le32(reg_addr);
5092 cmd->reg_value = cpu_to_le32(reg_val);
5093
5094 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
5095
5096 if (!page_change)
5097 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
5098
5099 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5100
5101 return status;
5102}
5103
5104/**
5105 * i40e_aq_get_phy_register_ext
5106 * @hw: pointer to the hw struct
5107 * @phy_select: select which phy should be accessed
5108 * @dev_addr: PHY device address
5109 * @page_change: flag to indicate if phy page should be updated
5110 * @set_mdio: use MDIO I/F number specified by mdio_num
5111 * @mdio_num: MDIO I/F number
5112 * @reg_addr: PHY register address
5113 * @reg_val: read register value
5114 * @cmd_details: pointer to command details structure or NULL
5115 *
5116 * Read the external PHY register.
5117 * NOTE: In common cases MDIO I/F number should not be changed, thats why you
5118 * may use simple wrapper i40e_aq_get_phy_register.
5119 **/
5120int i40e_aq_get_phy_register_ext(struct i40e_hw *hw,
5121 u8 phy_select, u8 dev_addr, bool page_change,
5122 bool set_mdio, u8 mdio_num,
5123 u32 reg_addr, u32 *reg_val,
5124 struct i40e_asq_cmd_details *cmd_details)
5125{
5126 struct i40e_aq_desc desc;
5127 struct i40e_aqc_phy_register_access *cmd =
5128 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5129 int status;
5130
5131 i40e_fill_default_direct_cmd_desc(&desc,
5132 i40e_aqc_opc_get_phy_register);
5133
5134 cmd->phy_interface = phy_select;
5135 cmd->dev_address = dev_addr;
5136 cmd->reg_address = cpu_to_le32(reg_addr);
5137
5138 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
5139
5140 if (!page_change)
5141 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
5142
5143 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5144 if (!status)
5145 *reg_val = le32_to_cpu(cmd->reg_value);
5146
5147 return status;
5148}
5149
5150/**
5151 * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
5152 * @hw: pointer to the hw struct
5153 * @buff: command buffer (size in bytes = buff_size)
5154 * @buff_size: buffer size in bytes
5155 * @track_id: package tracking id
5156 * @error_offset: returns error offset
5157 * @error_info: returns error information
5158 * @cmd_details: pointer to command details structure or NULL
5159 **/
5160int i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
5161 u16 buff_size, u32 track_id,
5162 u32 *error_offset, u32 *error_info,
5163 struct i40e_asq_cmd_details *cmd_details)
5164{
5165 struct i40e_aq_desc desc;
5166 struct i40e_aqc_write_personalization_profile *cmd =
5167 (struct i40e_aqc_write_personalization_profile *)
5168 &desc.params.raw;
5169 struct i40e_aqc_write_ddp_resp *resp;
5170 int status;
5171
5172 i40e_fill_default_direct_cmd_desc(&desc,
5173 i40e_aqc_opc_write_personalization_profile);
5174
5175 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
5176 if (buff_size > I40E_AQ_LARGE_BUF)
5177 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5178
5179 desc.datalen = cpu_to_le16(buff_size);
5180
5181 cmd->profile_track_id = cpu_to_le32(track_id);
5182
5183 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5184 if (!status) {
5185 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
5186 if (error_offset)
5187 *error_offset = le32_to_cpu(resp->error_offset);
5188 if (error_info)
5189 *error_info = le32_to_cpu(resp->error_info);
5190 }
5191
5192 return status;
5193}
5194
5195/**
5196 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
5197 * @hw: pointer to the hw struct
5198 * @buff: command buffer (size in bytes = buff_size)
5199 * @buff_size: buffer size in bytes
5200 * @flags: AdminQ command flags
5201 * @cmd_details: pointer to command details structure or NULL
5202 **/
5203int i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
5204 u16 buff_size, u8 flags,
5205 struct i40e_asq_cmd_details *cmd_details)
5206{
5207 struct i40e_aq_desc desc;
5208 struct i40e_aqc_get_applied_profiles *cmd =
5209 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
5210 int status;
5211
5212 i40e_fill_default_direct_cmd_desc(&desc,
5213 i40e_aqc_opc_get_personalization_profile_list);
5214
5215 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
5216 if (buff_size > I40E_AQ_LARGE_BUF)
5217 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5218 desc.datalen = cpu_to_le16(buff_size);
5219
5220 cmd->flags = flags;
5221
5222 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5223
5224 return status;
5225}
5226
5227/**
5228 * i40e_find_segment_in_package
5229 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
5230 * @pkg_hdr: pointer to the package header to be searched
5231 *
5232 * This function searches a package file for a particular segment type. On
5233 * success it returns a pointer to the segment header, otherwise it will
5234 * return NULL.
5235 **/
5236struct i40e_generic_seg_header *
5237i40e_find_segment_in_package(u32 segment_type,
5238 struct i40e_package_header *pkg_hdr)
5239{
5240 struct i40e_generic_seg_header *segment;
5241 u32 i;
5242
5243 /* Search all package segments for the requested segment type */
5244 for (i = 0; i < pkg_hdr->segment_count; i++) {
5245 segment =
5246 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
5247 pkg_hdr->segment_offset[i]);
5248
5249 if (segment->type == segment_type)
5250 return segment;
5251 }
5252
5253 return NULL;
5254}
5255
5256/* Get section table in profile */
5257#define I40E_SECTION_TABLE(profile, sec_tbl) \
5258 do { \
5259 struct i40e_profile_segment *p = (profile); \
5260 u32 count; \
5261 u32 *nvm; \
5262 count = p->device_table_count; \
5263 nvm = (u32 *)&p->device_table[count]; \
5264 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
5265 } while (0)
5266
5267/* Get section header in profile */
5268#define I40E_SECTION_HEADER(profile, offset) \
5269 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
5270
5271/**
5272 * i40e_find_section_in_profile
5273 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
5274 * @profile: pointer to the i40e segment header to be searched
5275 *
5276 * This function searches i40e segment for a particular section type. On
5277 * success it returns a pointer to the section header, otherwise it will
5278 * return NULL.
5279 **/
5280struct i40e_profile_section_header *
5281i40e_find_section_in_profile(u32 section_type,
5282 struct i40e_profile_segment *profile)
5283{
5284 struct i40e_profile_section_header *sec;
5285 struct i40e_section_table *sec_tbl;
5286 u32 sec_off;
5287 u32 i;
5288
5289 if (profile->header.type != SEGMENT_TYPE_I40E)
5290 return NULL;
5291
5292 I40E_SECTION_TABLE(profile, sec_tbl);
5293
5294 for (i = 0; i < sec_tbl->section_count; i++) {
5295 sec_off = sec_tbl->section_offset[i];
5296 sec = I40E_SECTION_HEADER(profile, sec_off);
5297 if (sec->section.type == section_type)
5298 return sec;
5299 }
5300
5301 return NULL;
5302}
5303
5304/**
5305 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
5306 * @hw: pointer to the hw struct
5307 * @aq: command buffer containing all data to execute AQ
5308 **/
5309static int i40e_ddp_exec_aq_section(struct i40e_hw *hw,
5310 struct i40e_profile_aq_section *aq)
5311{
5312 struct i40e_aq_desc desc;
5313 u8 *msg = NULL;
5314 u16 msglen;
5315 int status;
5316
5317 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
5318 desc.flags |= cpu_to_le16(aq->flags);
5319 memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw));
5320
5321 msglen = aq->datalen;
5322 if (msglen) {
5323 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
5324 I40E_AQ_FLAG_RD));
5325 if (msglen > I40E_AQ_LARGE_BUF)
5326 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5327 desc.datalen = cpu_to_le16(msglen);
5328 msg = &aq->data[0];
5329 }
5330
5331 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
5332
5333 if (status) {
5334 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5335 "unable to exec DDP AQ opcode %u, error %d\n",
5336 aq->opcode, status);
5337 return status;
5338 }
5339
5340 /* copy returned desc to aq_buf */
5341 memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw));
5342
5343 return 0;
5344}
5345
5346/**
5347 * i40e_validate_profile
5348 * @hw: pointer to the hardware structure
5349 * @profile: pointer to the profile segment of the package to be validated
5350 * @track_id: package tracking id
5351 * @rollback: flag if the profile is for rollback.
5352 *
5353 * Validates supported devices and profile's sections.
5354 */
5355static int
5356i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5357 u32 track_id, bool rollback)
5358{
5359 struct i40e_profile_section_header *sec = NULL;
5360 struct i40e_section_table *sec_tbl;
5361 u32 vendor_dev_id;
5362 int status = 0;
5363 u32 dev_cnt;
5364 u32 sec_off;
5365 u32 i;
5366
5367 if (track_id == I40E_DDP_TRACKID_INVALID) {
5368 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
5369 return -EOPNOTSUPP;
5370 }
5371
5372 dev_cnt = profile->device_table_count;
5373 for (i = 0; i < dev_cnt; i++) {
5374 vendor_dev_id = profile->device_table[i].vendor_dev_id;
5375 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL &&
5376 hw->device_id == (vendor_dev_id & 0xFFFF))
5377 break;
5378 }
5379 if (dev_cnt && i == dev_cnt) {
5380 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5381 "Device doesn't support DDP\n");
5382 return -ENODEV;
5383 }
5384
5385 I40E_SECTION_TABLE(profile, sec_tbl);
5386
5387 /* Validate sections types */
5388 for (i = 0; i < sec_tbl->section_count; i++) {
5389 sec_off = sec_tbl->section_offset[i];
5390 sec = I40E_SECTION_HEADER(profile, sec_off);
5391 if (rollback) {
5392 if (sec->section.type == SECTION_TYPE_MMIO ||
5393 sec->section.type == SECTION_TYPE_AQ ||
5394 sec->section.type == SECTION_TYPE_RB_AQ) {
5395 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5396 "Not a roll-back package\n");
5397 return -EOPNOTSUPP;
5398 }
5399 } else {
5400 if (sec->section.type == SECTION_TYPE_RB_AQ ||
5401 sec->section.type == SECTION_TYPE_RB_MMIO) {
5402 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5403 "Not an original package\n");
5404 return -EOPNOTSUPP;
5405 }
5406 }
5407 }
5408
5409 return status;
5410}
5411
5412/**
5413 * i40e_write_profile
5414 * @hw: pointer to the hardware structure
5415 * @profile: pointer to the profile segment of the package to be downloaded
5416 * @track_id: package tracking id
5417 *
5418 * Handles the download of a complete package.
5419 */
5420int
5421i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5422 u32 track_id)
5423{
5424 struct i40e_profile_section_header *sec = NULL;
5425 struct i40e_profile_aq_section *ddp_aq;
5426 struct i40e_section_table *sec_tbl;
5427 u32 offset = 0, info = 0;
5428 u32 section_size = 0;
5429 int status = 0;
5430 u32 sec_off;
5431 u32 i;
5432
5433 status = i40e_validate_profile(hw, profile, track_id, false);
5434 if (status)
5435 return status;
5436
5437 I40E_SECTION_TABLE(profile, sec_tbl);
5438
5439 for (i = 0; i < sec_tbl->section_count; i++) {
5440 sec_off = sec_tbl->section_offset[i];
5441 sec = I40E_SECTION_HEADER(profile, sec_off);
5442 /* Process generic admin command */
5443 if (sec->section.type == SECTION_TYPE_AQ) {
5444 ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
5445 status = i40e_ddp_exec_aq_section(hw, ddp_aq);
5446 if (status) {
5447 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5448 "Failed to execute aq: section %d, opcode %u\n",
5449 i, ddp_aq->opcode);
5450 break;
5451 }
5452 sec->section.type = SECTION_TYPE_RB_AQ;
5453 }
5454
5455 /* Skip any non-mmio sections */
5456 if (sec->section.type != SECTION_TYPE_MMIO)
5457 continue;
5458
5459 section_size = sec->section.size +
5460 sizeof(struct i40e_profile_section_header);
5461
5462 /* Write MMIO section */
5463 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
5464 track_id, &offset, &info, NULL);
5465 if (status) {
5466 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5467 "Failed to write profile: section %d, offset %d, info %d\n",
5468 i, offset, info);
5469 break;
5470 }
5471 }
5472 return status;
5473}
5474
5475/**
5476 * i40e_rollback_profile
5477 * @hw: pointer to the hardware structure
5478 * @profile: pointer to the profile segment of the package to be removed
5479 * @track_id: package tracking id
5480 *
5481 * Rolls back previously loaded package.
5482 */
5483int
5484i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5485 u32 track_id)
5486{
5487 struct i40e_profile_section_header *sec = NULL;
5488 struct i40e_section_table *sec_tbl;
5489 u32 offset = 0, info = 0;
5490 u32 section_size = 0;
5491 int status = 0;
5492 u32 sec_off;
5493 int i;
5494
5495 status = i40e_validate_profile(hw, profile, track_id, true);
5496 if (status)
5497 return status;
5498
5499 I40E_SECTION_TABLE(profile, sec_tbl);
5500
5501 /* For rollback write sections in reverse */
5502 for (i = sec_tbl->section_count - 1; i >= 0; i--) {
5503 sec_off = sec_tbl->section_offset[i];
5504 sec = I40E_SECTION_HEADER(profile, sec_off);
5505
5506 /* Skip any non-rollback sections */
5507 if (sec->section.type != SECTION_TYPE_RB_MMIO)
5508 continue;
5509
5510 section_size = sec->section.size +
5511 sizeof(struct i40e_profile_section_header);
5512
5513 /* Write roll-back MMIO section */
5514 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
5515 track_id, &offset, &info, NULL);
5516 if (status) {
5517 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5518 "Failed to write profile: section %d, offset %d, info %d\n",
5519 i, offset, info);
5520 break;
5521 }
5522 }
5523 return status;
5524}
5525
5526/**
5527 * i40e_add_pinfo_to_list
5528 * @hw: pointer to the hardware structure
5529 * @profile: pointer to the profile segment of the package
5530 * @profile_info_sec: buffer for information section
5531 * @track_id: package tracking id
5532 *
5533 * Register a profile to the list of loaded profiles.
5534 */
5535int
5536i40e_add_pinfo_to_list(struct i40e_hw *hw,
5537 struct i40e_profile_segment *profile,
5538 u8 *profile_info_sec, u32 track_id)
5539{
5540 struct i40e_profile_section_header *sec = NULL;
5541 struct i40e_profile_info *pinfo;
5542 u32 offset = 0, info = 0;
5543 int status = 0;
5544
5545 sec = (struct i40e_profile_section_header *)profile_info_sec;
5546 sec->tbl_size = 1;
5547 sec->data_end = sizeof(struct i40e_profile_section_header) +
5548 sizeof(struct i40e_profile_info);
5549 sec->section.type = SECTION_TYPE_INFO;
5550 sec->section.offset = sizeof(struct i40e_profile_section_header);
5551 sec->section.size = sizeof(struct i40e_profile_info);
5552 pinfo = (struct i40e_profile_info *)(profile_info_sec +
5553 sec->section.offset);
5554 pinfo->track_id = track_id;
5555 pinfo->version = profile->version;
5556 pinfo->op = I40E_DDP_ADD_TRACKID;
5557 memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
5558
5559 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
5560 track_id, &offset, &info, NULL);
5561
5562 return status;
5563}
5564
5565/**
5566 * i40e_aq_add_cloud_filters
5567 * @hw: pointer to the hardware structure
5568 * @seid: VSI seid to add cloud filters from
5569 * @filters: Buffer which contains the filters to be added
5570 * @filter_count: number of filters contained in the buffer
5571 *
5572 * Set the cloud filters for a given VSI. The contents of the
5573 * i40e_aqc_cloud_filters_element_data are filled in by the caller
5574 * of the function.
5575 *
5576 **/
5577int
5578i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid,
5579 struct i40e_aqc_cloud_filters_element_data *filters,
5580 u8 filter_count)
5581{
5582 struct i40e_aq_desc desc;
5583 struct i40e_aqc_add_remove_cloud_filters *cmd =
5584 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5585 u16 buff_len;
5586 int status;
5587
5588 i40e_fill_default_direct_cmd_desc(&desc,
5589 i40e_aqc_opc_add_cloud_filters);
5590
5591 buff_len = filter_count * sizeof(*filters);
5592 desc.datalen = cpu_to_le16(buff_len);
5593 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5594 cmd->num_filters = filter_count;
5595 cmd->seid = cpu_to_le16(seid);
5596
5597 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5598
5599 return status;
5600}
5601
5602/**
5603 * i40e_aq_add_cloud_filters_bb
5604 * @hw: pointer to the hardware structure
5605 * @seid: VSI seid to add cloud filters from
5606 * @filters: Buffer which contains the filters in big buffer to be added
5607 * @filter_count: number of filters contained in the buffer
5608 *
5609 * Set the big buffer cloud filters for a given VSI. The contents of the
5610 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5611 * function.
5612 *
5613 **/
5614int
5615i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5616 struct i40e_aqc_cloud_filters_element_bb *filters,
5617 u8 filter_count)
5618{
5619 struct i40e_aq_desc desc;
5620 struct i40e_aqc_add_remove_cloud_filters *cmd =
5621 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5622 u16 buff_len;
5623 int status;
5624 int i;
5625
5626 i40e_fill_default_direct_cmd_desc(&desc,
5627 i40e_aqc_opc_add_cloud_filters);
5628
5629 buff_len = filter_count * sizeof(*filters);
5630 desc.datalen = cpu_to_le16(buff_len);
5631 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5632 cmd->num_filters = filter_count;
5633 cmd->seid = cpu_to_le16(seid);
5634 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5635
5636 for (i = 0; i < filter_count; i++) {
5637 u16 tnl_type;
5638 u32 ti;
5639
5640 tnl_type = le16_get_bits(filters[i].element.flags,
5641 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK);
5642
5643 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5644 * one more byte further than normally used for Tenant ID in
5645 * other tunnel types.
5646 */
5647 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5648 ti = le32_to_cpu(filters[i].element.tenant_id);
5649 filters[i].element.tenant_id = cpu_to_le32(ti << 8);
5650 }
5651 }
5652
5653 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5654
5655 return status;
5656}
5657
5658/**
5659 * i40e_aq_rem_cloud_filters
5660 * @hw: pointer to the hardware structure
5661 * @seid: VSI seid to remove cloud filters from
5662 * @filters: Buffer which contains the filters to be removed
5663 * @filter_count: number of filters contained in the buffer
5664 *
5665 * Remove the cloud filters for a given VSI. The contents of the
5666 * i40e_aqc_cloud_filters_element_data are filled in by the caller
5667 * of the function.
5668 *
5669 **/
5670int
5671i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5672 struct i40e_aqc_cloud_filters_element_data *filters,
5673 u8 filter_count)
5674{
5675 struct i40e_aq_desc desc;
5676 struct i40e_aqc_add_remove_cloud_filters *cmd =
5677 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5678 u16 buff_len;
5679 int status;
5680
5681 i40e_fill_default_direct_cmd_desc(&desc,
5682 i40e_aqc_opc_remove_cloud_filters);
5683
5684 buff_len = filter_count * sizeof(*filters);
5685 desc.datalen = cpu_to_le16(buff_len);
5686 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5687 cmd->num_filters = filter_count;
5688 cmd->seid = cpu_to_le16(seid);
5689
5690 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5691
5692 return status;
5693}
5694
5695/**
5696 * i40e_aq_rem_cloud_filters_bb
5697 * @hw: pointer to the hardware structure
5698 * @seid: VSI seid to remove cloud filters from
5699 * @filters: Buffer which contains the filters in big buffer to be removed
5700 * @filter_count: number of filters contained in the buffer
5701 *
5702 * Remove the big buffer cloud filters for a given VSI. The contents of the
5703 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5704 * function.
5705 *
5706 **/
5707int
5708i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5709 struct i40e_aqc_cloud_filters_element_bb *filters,
5710 u8 filter_count)
5711{
5712 struct i40e_aq_desc desc;
5713 struct i40e_aqc_add_remove_cloud_filters *cmd =
5714 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5715 u16 buff_len;
5716 int status;
5717 int i;
5718
5719 i40e_fill_default_direct_cmd_desc(&desc,
5720 i40e_aqc_opc_remove_cloud_filters);
5721
5722 buff_len = filter_count * sizeof(*filters);
5723 desc.datalen = cpu_to_le16(buff_len);
5724 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5725 cmd->num_filters = filter_count;
5726 cmd->seid = cpu_to_le16(seid);
5727 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5728
5729 for (i = 0; i < filter_count; i++) {
5730 u16 tnl_type;
5731 u32 ti;
5732
5733 tnl_type = le16_get_bits(filters[i].element.flags,
5734 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK);
5735
5736 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5737 * one more byte further than normally used for Tenant ID in
5738 * other tunnel types.
5739 */
5740 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5741 ti = le32_to_cpu(filters[i].element.tenant_id);
5742 filters[i].element.tenant_id = cpu_to_le32(ti << 8);
5743 }
5744 }
5745
5746 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5747
5748 return status;
5749}
1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2016 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e_type.h"
28#include "i40e_adminq.h"
29#include "i40e_prototype.h"
30#include "i40e_virtchnl.h"
31
32/**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40{
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
45 case I40E_DEV_ID_SFP_XL710:
46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_B:
48 case I40E_DEV_ID_KX_C:
49 case I40E_DEV_ID_QSFP_A:
50 case I40E_DEV_ID_QSFP_B:
51 case I40E_DEV_ID_QSFP_C:
52 case I40E_DEV_ID_10G_BASE_T:
53 case I40E_DEV_ID_10G_BASE_T4:
54 case I40E_DEV_ID_20G_KR2:
55 case I40E_DEV_ID_20G_KR2_A:
56 hw->mac.type = I40E_MAC_XL710;
57 break;
58 case I40E_DEV_ID_KX_X722:
59 case I40E_DEV_ID_QSFP_X722:
60 case I40E_DEV_ID_SFP_X722:
61 case I40E_DEV_ID_1G_BASE_T_X722:
62 case I40E_DEV_ID_10G_BASE_T_X722:
63 hw->mac.type = I40E_MAC_X722;
64 break;
65 default:
66 hw->mac.type = I40E_MAC_GENERIC;
67 break;
68 }
69 } else {
70 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
71 }
72
73 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
74 hw->mac.type, status);
75 return status;
76}
77
78/**
79 * i40e_aq_str - convert AQ err code to a string
80 * @hw: pointer to the HW structure
81 * @aq_err: the AQ error code to convert
82 **/
83const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
84{
85 switch (aq_err) {
86 case I40E_AQ_RC_OK:
87 return "OK";
88 case I40E_AQ_RC_EPERM:
89 return "I40E_AQ_RC_EPERM";
90 case I40E_AQ_RC_ENOENT:
91 return "I40E_AQ_RC_ENOENT";
92 case I40E_AQ_RC_ESRCH:
93 return "I40E_AQ_RC_ESRCH";
94 case I40E_AQ_RC_EINTR:
95 return "I40E_AQ_RC_EINTR";
96 case I40E_AQ_RC_EIO:
97 return "I40E_AQ_RC_EIO";
98 case I40E_AQ_RC_ENXIO:
99 return "I40E_AQ_RC_ENXIO";
100 case I40E_AQ_RC_E2BIG:
101 return "I40E_AQ_RC_E2BIG";
102 case I40E_AQ_RC_EAGAIN:
103 return "I40E_AQ_RC_EAGAIN";
104 case I40E_AQ_RC_ENOMEM:
105 return "I40E_AQ_RC_ENOMEM";
106 case I40E_AQ_RC_EACCES:
107 return "I40E_AQ_RC_EACCES";
108 case I40E_AQ_RC_EFAULT:
109 return "I40E_AQ_RC_EFAULT";
110 case I40E_AQ_RC_EBUSY:
111 return "I40E_AQ_RC_EBUSY";
112 case I40E_AQ_RC_EEXIST:
113 return "I40E_AQ_RC_EEXIST";
114 case I40E_AQ_RC_EINVAL:
115 return "I40E_AQ_RC_EINVAL";
116 case I40E_AQ_RC_ENOTTY:
117 return "I40E_AQ_RC_ENOTTY";
118 case I40E_AQ_RC_ENOSPC:
119 return "I40E_AQ_RC_ENOSPC";
120 case I40E_AQ_RC_ENOSYS:
121 return "I40E_AQ_RC_ENOSYS";
122 case I40E_AQ_RC_ERANGE:
123 return "I40E_AQ_RC_ERANGE";
124 case I40E_AQ_RC_EFLUSHED:
125 return "I40E_AQ_RC_EFLUSHED";
126 case I40E_AQ_RC_BAD_ADDR:
127 return "I40E_AQ_RC_BAD_ADDR";
128 case I40E_AQ_RC_EMODE:
129 return "I40E_AQ_RC_EMODE";
130 case I40E_AQ_RC_EFBIG:
131 return "I40E_AQ_RC_EFBIG";
132 }
133
134 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
135 return hw->err_str;
136}
137
138/**
139 * i40e_stat_str - convert status err code to a string
140 * @hw: pointer to the HW structure
141 * @stat_err: the status error code to convert
142 **/
143const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
144{
145 switch (stat_err) {
146 case 0:
147 return "OK";
148 case I40E_ERR_NVM:
149 return "I40E_ERR_NVM";
150 case I40E_ERR_NVM_CHECKSUM:
151 return "I40E_ERR_NVM_CHECKSUM";
152 case I40E_ERR_PHY:
153 return "I40E_ERR_PHY";
154 case I40E_ERR_CONFIG:
155 return "I40E_ERR_CONFIG";
156 case I40E_ERR_PARAM:
157 return "I40E_ERR_PARAM";
158 case I40E_ERR_MAC_TYPE:
159 return "I40E_ERR_MAC_TYPE";
160 case I40E_ERR_UNKNOWN_PHY:
161 return "I40E_ERR_UNKNOWN_PHY";
162 case I40E_ERR_LINK_SETUP:
163 return "I40E_ERR_LINK_SETUP";
164 case I40E_ERR_ADAPTER_STOPPED:
165 return "I40E_ERR_ADAPTER_STOPPED";
166 case I40E_ERR_INVALID_MAC_ADDR:
167 return "I40E_ERR_INVALID_MAC_ADDR";
168 case I40E_ERR_DEVICE_NOT_SUPPORTED:
169 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
170 case I40E_ERR_MASTER_REQUESTS_PENDING:
171 return "I40E_ERR_MASTER_REQUESTS_PENDING";
172 case I40E_ERR_INVALID_LINK_SETTINGS:
173 return "I40E_ERR_INVALID_LINK_SETTINGS";
174 case I40E_ERR_AUTONEG_NOT_COMPLETE:
175 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
176 case I40E_ERR_RESET_FAILED:
177 return "I40E_ERR_RESET_FAILED";
178 case I40E_ERR_SWFW_SYNC:
179 return "I40E_ERR_SWFW_SYNC";
180 case I40E_ERR_NO_AVAILABLE_VSI:
181 return "I40E_ERR_NO_AVAILABLE_VSI";
182 case I40E_ERR_NO_MEMORY:
183 return "I40E_ERR_NO_MEMORY";
184 case I40E_ERR_BAD_PTR:
185 return "I40E_ERR_BAD_PTR";
186 case I40E_ERR_RING_FULL:
187 return "I40E_ERR_RING_FULL";
188 case I40E_ERR_INVALID_PD_ID:
189 return "I40E_ERR_INVALID_PD_ID";
190 case I40E_ERR_INVALID_QP_ID:
191 return "I40E_ERR_INVALID_QP_ID";
192 case I40E_ERR_INVALID_CQ_ID:
193 return "I40E_ERR_INVALID_CQ_ID";
194 case I40E_ERR_INVALID_CEQ_ID:
195 return "I40E_ERR_INVALID_CEQ_ID";
196 case I40E_ERR_INVALID_AEQ_ID:
197 return "I40E_ERR_INVALID_AEQ_ID";
198 case I40E_ERR_INVALID_SIZE:
199 return "I40E_ERR_INVALID_SIZE";
200 case I40E_ERR_INVALID_ARP_INDEX:
201 return "I40E_ERR_INVALID_ARP_INDEX";
202 case I40E_ERR_INVALID_FPM_FUNC_ID:
203 return "I40E_ERR_INVALID_FPM_FUNC_ID";
204 case I40E_ERR_QP_INVALID_MSG_SIZE:
205 return "I40E_ERR_QP_INVALID_MSG_SIZE";
206 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
207 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
208 case I40E_ERR_INVALID_FRAG_COUNT:
209 return "I40E_ERR_INVALID_FRAG_COUNT";
210 case I40E_ERR_QUEUE_EMPTY:
211 return "I40E_ERR_QUEUE_EMPTY";
212 case I40E_ERR_INVALID_ALIGNMENT:
213 return "I40E_ERR_INVALID_ALIGNMENT";
214 case I40E_ERR_FLUSHED_QUEUE:
215 return "I40E_ERR_FLUSHED_QUEUE";
216 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
217 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
218 case I40E_ERR_INVALID_IMM_DATA_SIZE:
219 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
220 case I40E_ERR_TIMEOUT:
221 return "I40E_ERR_TIMEOUT";
222 case I40E_ERR_OPCODE_MISMATCH:
223 return "I40E_ERR_OPCODE_MISMATCH";
224 case I40E_ERR_CQP_COMPL_ERROR:
225 return "I40E_ERR_CQP_COMPL_ERROR";
226 case I40E_ERR_INVALID_VF_ID:
227 return "I40E_ERR_INVALID_VF_ID";
228 case I40E_ERR_INVALID_HMCFN_ID:
229 return "I40E_ERR_INVALID_HMCFN_ID";
230 case I40E_ERR_BACKING_PAGE_ERROR:
231 return "I40E_ERR_BACKING_PAGE_ERROR";
232 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
233 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
234 case I40E_ERR_INVALID_PBLE_INDEX:
235 return "I40E_ERR_INVALID_PBLE_INDEX";
236 case I40E_ERR_INVALID_SD_INDEX:
237 return "I40E_ERR_INVALID_SD_INDEX";
238 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
239 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
240 case I40E_ERR_INVALID_SD_TYPE:
241 return "I40E_ERR_INVALID_SD_TYPE";
242 case I40E_ERR_MEMCPY_FAILED:
243 return "I40E_ERR_MEMCPY_FAILED";
244 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
245 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
246 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
247 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
248 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
249 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
250 case I40E_ERR_SRQ_ENABLED:
251 return "I40E_ERR_SRQ_ENABLED";
252 case I40E_ERR_ADMIN_QUEUE_ERROR:
253 return "I40E_ERR_ADMIN_QUEUE_ERROR";
254 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
255 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
256 case I40E_ERR_BUF_TOO_SHORT:
257 return "I40E_ERR_BUF_TOO_SHORT";
258 case I40E_ERR_ADMIN_QUEUE_FULL:
259 return "I40E_ERR_ADMIN_QUEUE_FULL";
260 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
261 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
262 case I40E_ERR_BAD_IWARP_CQE:
263 return "I40E_ERR_BAD_IWARP_CQE";
264 case I40E_ERR_NVM_BLANK_MODE:
265 return "I40E_ERR_NVM_BLANK_MODE";
266 case I40E_ERR_NOT_IMPLEMENTED:
267 return "I40E_ERR_NOT_IMPLEMENTED";
268 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
269 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
270 case I40E_ERR_DIAG_TEST_FAILED:
271 return "I40E_ERR_DIAG_TEST_FAILED";
272 case I40E_ERR_NOT_READY:
273 return "I40E_ERR_NOT_READY";
274 case I40E_NOT_SUPPORTED:
275 return "I40E_NOT_SUPPORTED";
276 case I40E_ERR_FIRMWARE_API_VERSION:
277 return "I40E_ERR_FIRMWARE_API_VERSION";
278 }
279
280 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
281 return hw->err_str;
282}
283
284/**
285 * i40e_debug_aq
286 * @hw: debug mask related to admin queue
287 * @mask: debug mask
288 * @desc: pointer to admin queue descriptor
289 * @buffer: pointer to command buffer
290 * @buf_len: max length of buffer
291 *
292 * Dumps debug log about adminq command with descriptor contents.
293 **/
294void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
295 void *buffer, u16 buf_len)
296{
297 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
298 u16 len = le16_to_cpu(aq_desc->datalen);
299 u8 *buf = (u8 *)buffer;
300 u16 i = 0;
301
302 if ((!(mask & hw->debug_mask)) || (desc == NULL))
303 return;
304
305 i40e_debug(hw, mask,
306 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
307 le16_to_cpu(aq_desc->opcode),
308 le16_to_cpu(aq_desc->flags),
309 le16_to_cpu(aq_desc->datalen),
310 le16_to_cpu(aq_desc->retval));
311 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
312 le32_to_cpu(aq_desc->cookie_high),
313 le32_to_cpu(aq_desc->cookie_low));
314 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
315 le32_to_cpu(aq_desc->params.internal.param0),
316 le32_to_cpu(aq_desc->params.internal.param1));
317 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
318 le32_to_cpu(aq_desc->params.external.addr_high),
319 le32_to_cpu(aq_desc->params.external.addr_low));
320
321 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
322 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
323 if (buf_len < len)
324 len = buf_len;
325 /* write the full 16-byte chunks */
326 for (i = 0; i < (len - 16); i += 16)
327 i40e_debug(hw, mask, "\t0x%04X %16ph\n", i, buf + i);
328 /* write whatever's left over without overrunning the buffer */
329 if (i < len)
330 i40e_debug(hw, mask, "\t0x%04X %*ph\n",
331 i, len - i, buf + i);
332 }
333}
334
335/**
336 * i40e_check_asq_alive
337 * @hw: pointer to the hw struct
338 *
339 * Returns true if Queue is enabled else false.
340 **/
341bool i40e_check_asq_alive(struct i40e_hw *hw)
342{
343 if (hw->aq.asq.len)
344 return !!(rd32(hw, hw->aq.asq.len) &
345 I40E_PF_ATQLEN_ATQENABLE_MASK);
346 else
347 return false;
348}
349
350/**
351 * i40e_aq_queue_shutdown
352 * @hw: pointer to the hw struct
353 * @unloading: is the driver unloading itself
354 *
355 * Tell the Firmware that we're shutting down the AdminQ and whether
356 * or not the driver is unloading as well.
357 **/
358i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
359 bool unloading)
360{
361 struct i40e_aq_desc desc;
362 struct i40e_aqc_queue_shutdown *cmd =
363 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
364 i40e_status status;
365
366 i40e_fill_default_direct_cmd_desc(&desc,
367 i40e_aqc_opc_queue_shutdown);
368
369 if (unloading)
370 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
371 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
372
373 return status;
374}
375
376/**
377 * i40e_aq_get_set_rss_lut
378 * @hw: pointer to the hardware structure
379 * @vsi_id: vsi fw index
380 * @pf_lut: for PF table set true, for VSI table set false
381 * @lut: pointer to the lut buffer provided by the caller
382 * @lut_size: size of the lut buffer
383 * @set: set true to set the table, false to get the table
384 *
385 * Internal function to get or set RSS look up table
386 **/
387static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
388 u16 vsi_id, bool pf_lut,
389 u8 *lut, u16 lut_size,
390 bool set)
391{
392 i40e_status status;
393 struct i40e_aq_desc desc;
394 struct i40e_aqc_get_set_rss_lut *cmd_resp =
395 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
396
397 if (set)
398 i40e_fill_default_direct_cmd_desc(&desc,
399 i40e_aqc_opc_set_rss_lut);
400 else
401 i40e_fill_default_direct_cmd_desc(&desc,
402 i40e_aqc_opc_get_rss_lut);
403
404 /* Indirect command */
405 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
406 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
407
408 cmd_resp->vsi_id =
409 cpu_to_le16((u16)((vsi_id <<
410 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
411 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
412 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
413
414 if (pf_lut)
415 cmd_resp->flags |= cpu_to_le16((u16)
416 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
417 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
418 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
419 else
420 cmd_resp->flags |= cpu_to_le16((u16)
421 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
422 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
423 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
424
425 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
426
427 return status;
428}
429
430/**
431 * i40e_aq_get_rss_lut
432 * @hw: pointer to the hardware structure
433 * @vsi_id: vsi fw index
434 * @pf_lut: for PF table set true, for VSI table set false
435 * @lut: pointer to the lut buffer provided by the caller
436 * @lut_size: size of the lut buffer
437 *
438 * get the RSS lookup table, PF or VSI type
439 **/
440i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
441 bool pf_lut, u8 *lut, u16 lut_size)
442{
443 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
444 false);
445}
446
447/**
448 * i40e_aq_set_rss_lut
449 * @hw: pointer to the hardware structure
450 * @vsi_id: vsi fw index
451 * @pf_lut: for PF table set true, for VSI table set false
452 * @lut: pointer to the lut buffer provided by the caller
453 * @lut_size: size of the lut buffer
454 *
455 * set the RSS lookup table, PF or VSI type
456 **/
457i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
458 bool pf_lut, u8 *lut, u16 lut_size)
459{
460 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
461}
462
463/**
464 * i40e_aq_get_set_rss_key
465 * @hw: pointer to the hw struct
466 * @vsi_id: vsi fw index
467 * @key: pointer to key info struct
468 * @set: set true to set the key, false to get the key
469 *
470 * get the RSS key per VSI
471 **/
472static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
473 u16 vsi_id,
474 struct i40e_aqc_get_set_rss_key_data *key,
475 bool set)
476{
477 i40e_status status;
478 struct i40e_aq_desc desc;
479 struct i40e_aqc_get_set_rss_key *cmd_resp =
480 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
481 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
482
483 if (set)
484 i40e_fill_default_direct_cmd_desc(&desc,
485 i40e_aqc_opc_set_rss_key);
486 else
487 i40e_fill_default_direct_cmd_desc(&desc,
488 i40e_aqc_opc_get_rss_key);
489
490 /* Indirect command */
491 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
492 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
493
494 cmd_resp->vsi_id =
495 cpu_to_le16((u16)((vsi_id <<
496 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
497 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
498 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
499
500 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
501
502 return status;
503}
504
505/**
506 * i40e_aq_get_rss_key
507 * @hw: pointer to the hw struct
508 * @vsi_id: vsi fw index
509 * @key: pointer to key info struct
510 *
511 **/
512i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
513 u16 vsi_id,
514 struct i40e_aqc_get_set_rss_key_data *key)
515{
516 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
517}
518
519/**
520 * i40e_aq_set_rss_key
521 * @hw: pointer to the hw struct
522 * @vsi_id: vsi fw index
523 * @key: pointer to key info struct
524 *
525 * set the RSS key per VSI
526 **/
527i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
528 u16 vsi_id,
529 struct i40e_aqc_get_set_rss_key_data *key)
530{
531 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
532}
533
534/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
535 * hardware to a bit-field that can be used by SW to more easily determine the
536 * packet type.
537 *
538 * Macros are used to shorten the table lines and make this table human
539 * readable.
540 *
541 * We store the PTYPE in the top byte of the bit field - this is just so that
542 * we can check that the table doesn't have a row missing, as the index into
543 * the table should be the PTYPE.
544 *
545 * Typical work flow:
546 *
547 * IF NOT i40e_ptype_lookup[ptype].known
548 * THEN
549 * Packet is unknown
550 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
551 * Use the rest of the fields to look at the tunnels, inner protocols, etc
552 * ELSE
553 * Use the enum i40e_rx_l2_ptype to decode the packet type
554 * ENDIF
555 */
556
557/* macro to make the table lines short */
558#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
559 { PTYPE, \
560 1, \
561 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
562 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
563 I40E_RX_PTYPE_##OUTER_FRAG, \
564 I40E_RX_PTYPE_TUNNEL_##T, \
565 I40E_RX_PTYPE_TUNNEL_END_##TE, \
566 I40E_RX_PTYPE_##TEF, \
567 I40E_RX_PTYPE_INNER_PROT_##I, \
568 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
569
570#define I40E_PTT_UNUSED_ENTRY(PTYPE) \
571 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
572
573/* shorter macros makes the table fit but are terse */
574#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
575#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
576#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
577
578/* Lookup table mapping the HW PTYPE to the bit field for decoding */
579struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
580 /* L2 Packet types */
581 I40E_PTT_UNUSED_ENTRY(0),
582 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
583 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
584 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
585 I40E_PTT_UNUSED_ENTRY(4),
586 I40E_PTT_UNUSED_ENTRY(5),
587 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
588 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
589 I40E_PTT_UNUSED_ENTRY(8),
590 I40E_PTT_UNUSED_ENTRY(9),
591 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
592 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
593 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
594 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
595 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
596 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
597 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
598 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
599 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
600 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
601 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
602 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
603
604 /* Non Tunneled IPv4 */
605 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
606 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
607 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
608 I40E_PTT_UNUSED_ENTRY(25),
609 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
610 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
611 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
612
613 /* IPv4 --> IPv4 */
614 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
615 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
616 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
617 I40E_PTT_UNUSED_ENTRY(32),
618 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
619 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
620 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
621
622 /* IPv4 --> IPv6 */
623 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
624 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
625 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
626 I40E_PTT_UNUSED_ENTRY(39),
627 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
628 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
629 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
630
631 /* IPv4 --> GRE/NAT */
632 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
633
634 /* IPv4 --> GRE/NAT --> IPv4 */
635 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
636 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
637 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
638 I40E_PTT_UNUSED_ENTRY(47),
639 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
640 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
641 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
642
643 /* IPv4 --> GRE/NAT --> IPv6 */
644 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
645 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
646 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
647 I40E_PTT_UNUSED_ENTRY(54),
648 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
649 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
650 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
651
652 /* IPv4 --> GRE/NAT --> MAC */
653 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
654
655 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
656 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
657 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
658 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
659 I40E_PTT_UNUSED_ENTRY(62),
660 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
661 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
662 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
663
664 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
665 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
666 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
667 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
668 I40E_PTT_UNUSED_ENTRY(69),
669 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
670 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
671 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
672
673 /* IPv4 --> GRE/NAT --> MAC/VLAN */
674 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
675
676 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
677 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
678 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
679 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
680 I40E_PTT_UNUSED_ENTRY(77),
681 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
682 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
683 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
684
685 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
686 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
687 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
688 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
689 I40E_PTT_UNUSED_ENTRY(84),
690 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
691 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
692 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
693
694 /* Non Tunneled IPv6 */
695 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
696 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
697 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
698 I40E_PTT_UNUSED_ENTRY(91),
699 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
700 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
701 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
702
703 /* IPv6 --> IPv4 */
704 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
705 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
706 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
707 I40E_PTT_UNUSED_ENTRY(98),
708 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
709 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
710 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
711
712 /* IPv6 --> IPv6 */
713 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
714 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
715 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
716 I40E_PTT_UNUSED_ENTRY(105),
717 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
718 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
719 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
720
721 /* IPv6 --> GRE/NAT */
722 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
723
724 /* IPv6 --> GRE/NAT -> IPv4 */
725 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
726 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
727 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
728 I40E_PTT_UNUSED_ENTRY(113),
729 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
730 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
731 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
732
733 /* IPv6 --> GRE/NAT -> IPv6 */
734 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
735 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
736 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
737 I40E_PTT_UNUSED_ENTRY(120),
738 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
739 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
740 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
741
742 /* IPv6 --> GRE/NAT -> MAC */
743 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
744
745 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
746 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
747 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
748 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
749 I40E_PTT_UNUSED_ENTRY(128),
750 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
751 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
752 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
753
754 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
755 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
756 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
757 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
758 I40E_PTT_UNUSED_ENTRY(135),
759 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
760 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
761 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
762
763 /* IPv6 --> GRE/NAT -> MAC/VLAN */
764 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
765
766 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
767 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
768 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
769 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
770 I40E_PTT_UNUSED_ENTRY(143),
771 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
772 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
773 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
774
775 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
776 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
777 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
778 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
779 I40E_PTT_UNUSED_ENTRY(150),
780 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
781 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
782 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
783
784 /* unused entries */
785 I40E_PTT_UNUSED_ENTRY(154),
786 I40E_PTT_UNUSED_ENTRY(155),
787 I40E_PTT_UNUSED_ENTRY(156),
788 I40E_PTT_UNUSED_ENTRY(157),
789 I40E_PTT_UNUSED_ENTRY(158),
790 I40E_PTT_UNUSED_ENTRY(159),
791
792 I40E_PTT_UNUSED_ENTRY(160),
793 I40E_PTT_UNUSED_ENTRY(161),
794 I40E_PTT_UNUSED_ENTRY(162),
795 I40E_PTT_UNUSED_ENTRY(163),
796 I40E_PTT_UNUSED_ENTRY(164),
797 I40E_PTT_UNUSED_ENTRY(165),
798 I40E_PTT_UNUSED_ENTRY(166),
799 I40E_PTT_UNUSED_ENTRY(167),
800 I40E_PTT_UNUSED_ENTRY(168),
801 I40E_PTT_UNUSED_ENTRY(169),
802
803 I40E_PTT_UNUSED_ENTRY(170),
804 I40E_PTT_UNUSED_ENTRY(171),
805 I40E_PTT_UNUSED_ENTRY(172),
806 I40E_PTT_UNUSED_ENTRY(173),
807 I40E_PTT_UNUSED_ENTRY(174),
808 I40E_PTT_UNUSED_ENTRY(175),
809 I40E_PTT_UNUSED_ENTRY(176),
810 I40E_PTT_UNUSED_ENTRY(177),
811 I40E_PTT_UNUSED_ENTRY(178),
812 I40E_PTT_UNUSED_ENTRY(179),
813
814 I40E_PTT_UNUSED_ENTRY(180),
815 I40E_PTT_UNUSED_ENTRY(181),
816 I40E_PTT_UNUSED_ENTRY(182),
817 I40E_PTT_UNUSED_ENTRY(183),
818 I40E_PTT_UNUSED_ENTRY(184),
819 I40E_PTT_UNUSED_ENTRY(185),
820 I40E_PTT_UNUSED_ENTRY(186),
821 I40E_PTT_UNUSED_ENTRY(187),
822 I40E_PTT_UNUSED_ENTRY(188),
823 I40E_PTT_UNUSED_ENTRY(189),
824
825 I40E_PTT_UNUSED_ENTRY(190),
826 I40E_PTT_UNUSED_ENTRY(191),
827 I40E_PTT_UNUSED_ENTRY(192),
828 I40E_PTT_UNUSED_ENTRY(193),
829 I40E_PTT_UNUSED_ENTRY(194),
830 I40E_PTT_UNUSED_ENTRY(195),
831 I40E_PTT_UNUSED_ENTRY(196),
832 I40E_PTT_UNUSED_ENTRY(197),
833 I40E_PTT_UNUSED_ENTRY(198),
834 I40E_PTT_UNUSED_ENTRY(199),
835
836 I40E_PTT_UNUSED_ENTRY(200),
837 I40E_PTT_UNUSED_ENTRY(201),
838 I40E_PTT_UNUSED_ENTRY(202),
839 I40E_PTT_UNUSED_ENTRY(203),
840 I40E_PTT_UNUSED_ENTRY(204),
841 I40E_PTT_UNUSED_ENTRY(205),
842 I40E_PTT_UNUSED_ENTRY(206),
843 I40E_PTT_UNUSED_ENTRY(207),
844 I40E_PTT_UNUSED_ENTRY(208),
845 I40E_PTT_UNUSED_ENTRY(209),
846
847 I40E_PTT_UNUSED_ENTRY(210),
848 I40E_PTT_UNUSED_ENTRY(211),
849 I40E_PTT_UNUSED_ENTRY(212),
850 I40E_PTT_UNUSED_ENTRY(213),
851 I40E_PTT_UNUSED_ENTRY(214),
852 I40E_PTT_UNUSED_ENTRY(215),
853 I40E_PTT_UNUSED_ENTRY(216),
854 I40E_PTT_UNUSED_ENTRY(217),
855 I40E_PTT_UNUSED_ENTRY(218),
856 I40E_PTT_UNUSED_ENTRY(219),
857
858 I40E_PTT_UNUSED_ENTRY(220),
859 I40E_PTT_UNUSED_ENTRY(221),
860 I40E_PTT_UNUSED_ENTRY(222),
861 I40E_PTT_UNUSED_ENTRY(223),
862 I40E_PTT_UNUSED_ENTRY(224),
863 I40E_PTT_UNUSED_ENTRY(225),
864 I40E_PTT_UNUSED_ENTRY(226),
865 I40E_PTT_UNUSED_ENTRY(227),
866 I40E_PTT_UNUSED_ENTRY(228),
867 I40E_PTT_UNUSED_ENTRY(229),
868
869 I40E_PTT_UNUSED_ENTRY(230),
870 I40E_PTT_UNUSED_ENTRY(231),
871 I40E_PTT_UNUSED_ENTRY(232),
872 I40E_PTT_UNUSED_ENTRY(233),
873 I40E_PTT_UNUSED_ENTRY(234),
874 I40E_PTT_UNUSED_ENTRY(235),
875 I40E_PTT_UNUSED_ENTRY(236),
876 I40E_PTT_UNUSED_ENTRY(237),
877 I40E_PTT_UNUSED_ENTRY(238),
878 I40E_PTT_UNUSED_ENTRY(239),
879
880 I40E_PTT_UNUSED_ENTRY(240),
881 I40E_PTT_UNUSED_ENTRY(241),
882 I40E_PTT_UNUSED_ENTRY(242),
883 I40E_PTT_UNUSED_ENTRY(243),
884 I40E_PTT_UNUSED_ENTRY(244),
885 I40E_PTT_UNUSED_ENTRY(245),
886 I40E_PTT_UNUSED_ENTRY(246),
887 I40E_PTT_UNUSED_ENTRY(247),
888 I40E_PTT_UNUSED_ENTRY(248),
889 I40E_PTT_UNUSED_ENTRY(249),
890
891 I40E_PTT_UNUSED_ENTRY(250),
892 I40E_PTT_UNUSED_ENTRY(251),
893 I40E_PTT_UNUSED_ENTRY(252),
894 I40E_PTT_UNUSED_ENTRY(253),
895 I40E_PTT_UNUSED_ENTRY(254),
896 I40E_PTT_UNUSED_ENTRY(255)
897};
898
899/**
900 * i40e_init_shared_code - Initialize the shared code
901 * @hw: pointer to hardware structure
902 *
903 * This assigns the MAC type and PHY code and inits the NVM.
904 * Does not touch the hardware. This function must be called prior to any
905 * other function in the shared code. The i40e_hw structure should be
906 * memset to 0 prior to calling this function. The following fields in
907 * hw structure should be filled in prior to calling this function:
908 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
909 * subsystem_vendor_id, and revision_id
910 **/
911i40e_status i40e_init_shared_code(struct i40e_hw *hw)
912{
913 i40e_status status = 0;
914 u32 port, ari, func_rid;
915
916 i40e_set_mac_type(hw);
917
918 switch (hw->mac.type) {
919 case I40E_MAC_XL710:
920 case I40E_MAC_X722:
921 break;
922 default:
923 return I40E_ERR_DEVICE_NOT_SUPPORTED;
924 }
925
926 hw->phy.get_link_info = true;
927
928 /* Determine port number and PF number*/
929 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
930 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
931 hw->port = (u8)port;
932 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
933 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
934 func_rid = rd32(hw, I40E_PF_FUNC_RID);
935 if (ari)
936 hw->pf_id = (u8)(func_rid & 0xff);
937 else
938 hw->pf_id = (u8)(func_rid & 0x7);
939
940 if (hw->mac.type == I40E_MAC_X722)
941 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
942
943 status = i40e_init_nvm(hw);
944 return status;
945}
946
947/**
948 * i40e_aq_mac_address_read - Retrieve the MAC addresses
949 * @hw: pointer to the hw struct
950 * @flags: a return indicator of what addresses were added to the addr store
951 * @addrs: the requestor's mac addr store
952 * @cmd_details: pointer to command details structure or NULL
953 **/
954static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
955 u16 *flags,
956 struct i40e_aqc_mac_address_read_data *addrs,
957 struct i40e_asq_cmd_details *cmd_details)
958{
959 struct i40e_aq_desc desc;
960 struct i40e_aqc_mac_address_read *cmd_data =
961 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
962 i40e_status status;
963
964 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
965 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
966
967 status = i40e_asq_send_command(hw, &desc, addrs,
968 sizeof(*addrs), cmd_details);
969 *flags = le16_to_cpu(cmd_data->command_flags);
970
971 return status;
972}
973
974/**
975 * i40e_aq_mac_address_write - Change the MAC addresses
976 * @hw: pointer to the hw struct
977 * @flags: indicates which MAC to be written
978 * @mac_addr: address to write
979 * @cmd_details: pointer to command details structure or NULL
980 **/
981i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
982 u16 flags, u8 *mac_addr,
983 struct i40e_asq_cmd_details *cmd_details)
984{
985 struct i40e_aq_desc desc;
986 struct i40e_aqc_mac_address_write *cmd_data =
987 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
988 i40e_status status;
989
990 i40e_fill_default_direct_cmd_desc(&desc,
991 i40e_aqc_opc_mac_address_write);
992 cmd_data->command_flags = cpu_to_le16(flags);
993 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
994 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
995 ((u32)mac_addr[3] << 16) |
996 ((u32)mac_addr[4] << 8) |
997 mac_addr[5]);
998
999 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1000
1001 return status;
1002}
1003
1004/**
1005 * i40e_get_mac_addr - get MAC address
1006 * @hw: pointer to the HW structure
1007 * @mac_addr: pointer to MAC address
1008 *
1009 * Reads the adapter's MAC address from register
1010 **/
1011i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1012{
1013 struct i40e_aqc_mac_address_read_data addrs;
1014 i40e_status status;
1015 u16 flags = 0;
1016
1017 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1018
1019 if (flags & I40E_AQC_LAN_ADDR_VALID)
1020 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
1021
1022 return status;
1023}
1024
1025/**
1026 * i40e_get_port_mac_addr - get Port MAC address
1027 * @hw: pointer to the HW structure
1028 * @mac_addr: pointer to Port MAC address
1029 *
1030 * Reads the adapter's Port MAC address
1031 **/
1032i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1033{
1034 struct i40e_aqc_mac_address_read_data addrs;
1035 i40e_status status;
1036 u16 flags = 0;
1037
1038 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1039 if (status)
1040 return status;
1041
1042 if (flags & I40E_AQC_PORT_ADDR_VALID)
1043 ether_addr_copy(mac_addr, addrs.port_mac);
1044 else
1045 status = I40E_ERR_INVALID_MAC_ADDR;
1046
1047 return status;
1048}
1049
1050/**
1051 * i40e_pre_tx_queue_cfg - pre tx queue configure
1052 * @hw: pointer to the HW structure
1053 * @queue: target PF queue index
1054 * @enable: state change request
1055 *
1056 * Handles hw requirement to indicate intention to enable
1057 * or disable target queue.
1058 **/
1059void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1060{
1061 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1062 u32 reg_block = 0;
1063 u32 reg_val;
1064
1065 if (abs_queue_idx >= 128) {
1066 reg_block = abs_queue_idx / 128;
1067 abs_queue_idx %= 128;
1068 }
1069
1070 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1071 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1072 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1073
1074 if (enable)
1075 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1076 else
1077 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1078
1079 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1080}
1081#ifdef I40E_FCOE
1082
1083/**
1084 * i40e_get_san_mac_addr - get SAN MAC address
1085 * @hw: pointer to the HW structure
1086 * @mac_addr: pointer to SAN MAC address
1087 *
1088 * Reads the adapter's SAN MAC address from NVM
1089 **/
1090i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1091{
1092 struct i40e_aqc_mac_address_read_data addrs;
1093 i40e_status status;
1094 u16 flags = 0;
1095
1096 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1097 if (status)
1098 return status;
1099
1100 if (flags & I40E_AQC_SAN_ADDR_VALID)
1101 ether_addr_copy(mac_addr, addrs.pf_san_mac);
1102 else
1103 status = I40E_ERR_INVALID_MAC_ADDR;
1104
1105 return status;
1106}
1107#endif
1108
1109/**
1110 * i40e_read_pba_string - Reads part number string from EEPROM
1111 * @hw: pointer to hardware structure
1112 * @pba_num: stores the part number string from the EEPROM
1113 * @pba_num_size: part number string buffer length
1114 *
1115 * Reads the part number string from the EEPROM.
1116 **/
1117i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1118 u32 pba_num_size)
1119{
1120 i40e_status status = 0;
1121 u16 pba_word = 0;
1122 u16 pba_size = 0;
1123 u16 pba_ptr = 0;
1124 u16 i = 0;
1125
1126 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1127 if (status || (pba_word != 0xFAFA)) {
1128 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1129 return status;
1130 }
1131
1132 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1133 if (status) {
1134 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1135 return status;
1136 }
1137
1138 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1139 if (status) {
1140 hw_dbg(hw, "Failed to read PBA Block size.\n");
1141 return status;
1142 }
1143
1144 /* Subtract one to get PBA word count (PBA Size word is included in
1145 * total size)
1146 */
1147 pba_size--;
1148 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1149 hw_dbg(hw, "Buffer to small for PBA data.\n");
1150 return I40E_ERR_PARAM;
1151 }
1152
1153 for (i = 0; i < pba_size; i++) {
1154 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1155 if (status) {
1156 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1157 return status;
1158 }
1159
1160 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1161 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1162 }
1163 pba_num[(pba_size * 2)] = '\0';
1164
1165 return status;
1166}
1167
1168/**
1169 * i40e_get_media_type - Gets media type
1170 * @hw: pointer to the hardware structure
1171 **/
1172static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1173{
1174 enum i40e_media_type media;
1175
1176 switch (hw->phy.link_info.phy_type) {
1177 case I40E_PHY_TYPE_10GBASE_SR:
1178 case I40E_PHY_TYPE_10GBASE_LR:
1179 case I40E_PHY_TYPE_1000BASE_SX:
1180 case I40E_PHY_TYPE_1000BASE_LX:
1181 case I40E_PHY_TYPE_40GBASE_SR4:
1182 case I40E_PHY_TYPE_40GBASE_LR4:
1183 media = I40E_MEDIA_TYPE_FIBER;
1184 break;
1185 case I40E_PHY_TYPE_100BASE_TX:
1186 case I40E_PHY_TYPE_1000BASE_T:
1187 case I40E_PHY_TYPE_10GBASE_T:
1188 media = I40E_MEDIA_TYPE_BASET;
1189 break;
1190 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1191 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1192 case I40E_PHY_TYPE_10GBASE_CR1:
1193 case I40E_PHY_TYPE_40GBASE_CR4:
1194 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1195 case I40E_PHY_TYPE_40GBASE_AOC:
1196 case I40E_PHY_TYPE_10GBASE_AOC:
1197 media = I40E_MEDIA_TYPE_DA;
1198 break;
1199 case I40E_PHY_TYPE_1000BASE_KX:
1200 case I40E_PHY_TYPE_10GBASE_KX4:
1201 case I40E_PHY_TYPE_10GBASE_KR:
1202 case I40E_PHY_TYPE_40GBASE_KR4:
1203 case I40E_PHY_TYPE_20GBASE_KR2:
1204 media = I40E_MEDIA_TYPE_BACKPLANE;
1205 break;
1206 case I40E_PHY_TYPE_SGMII:
1207 case I40E_PHY_TYPE_XAUI:
1208 case I40E_PHY_TYPE_XFI:
1209 case I40E_PHY_TYPE_XLAUI:
1210 case I40E_PHY_TYPE_XLPPI:
1211 default:
1212 media = I40E_MEDIA_TYPE_UNKNOWN;
1213 break;
1214 }
1215
1216 return media;
1217}
1218
1219#define I40E_PF_RESET_WAIT_COUNT_A0 200
1220#define I40E_PF_RESET_WAIT_COUNT 200
1221/**
1222 * i40e_pf_reset - Reset the PF
1223 * @hw: pointer to the hardware structure
1224 *
1225 * Assuming someone else has triggered a global reset,
1226 * assure the global reset is complete and then reset the PF
1227 **/
1228i40e_status i40e_pf_reset(struct i40e_hw *hw)
1229{
1230 u32 cnt = 0;
1231 u32 cnt1 = 0;
1232 u32 reg = 0;
1233 u32 grst_del;
1234
1235 /* Poll for Global Reset steady state in case of recent GRST.
1236 * The grst delay value is in 100ms units, and we'll wait a
1237 * couple counts longer to be sure we don't just miss the end.
1238 */
1239 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1240 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1241 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1242
1243 /* It can take upto 15 secs for GRST steady state.
1244 * Bump it to 16 secs max to be safe.
1245 */
1246 grst_del = grst_del * 20;
1247
1248 for (cnt = 0; cnt < grst_del; cnt++) {
1249 reg = rd32(hw, I40E_GLGEN_RSTAT);
1250 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1251 break;
1252 msleep(100);
1253 }
1254 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1255 hw_dbg(hw, "Global reset polling failed to complete.\n");
1256 return I40E_ERR_RESET_FAILED;
1257 }
1258
1259 /* Now Wait for the FW to be ready */
1260 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1261 reg = rd32(hw, I40E_GLNVM_ULD);
1262 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1263 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1264 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1265 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1266 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1267 break;
1268 }
1269 usleep_range(10000, 20000);
1270 }
1271 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1272 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1273 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1274 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
1275 return I40E_ERR_RESET_FAILED;
1276 }
1277
1278 /* If there was a Global Reset in progress when we got here,
1279 * we don't need to do the PF Reset
1280 */
1281 if (!cnt) {
1282 if (hw->revision_id == 0)
1283 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1284 else
1285 cnt = I40E_PF_RESET_WAIT_COUNT;
1286 reg = rd32(hw, I40E_PFGEN_CTRL);
1287 wr32(hw, I40E_PFGEN_CTRL,
1288 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1289 for (; cnt; cnt--) {
1290 reg = rd32(hw, I40E_PFGEN_CTRL);
1291 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1292 break;
1293 usleep_range(1000, 2000);
1294 }
1295 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1296 hw_dbg(hw, "PF reset polling failed to complete.\n");
1297 return I40E_ERR_RESET_FAILED;
1298 }
1299 }
1300
1301 i40e_clear_pxe_mode(hw);
1302
1303 return 0;
1304}
1305
1306/**
1307 * i40e_clear_hw - clear out any left over hw state
1308 * @hw: pointer to the hw struct
1309 *
1310 * Clear queues and interrupts, typically called at init time,
1311 * but after the capabilities have been found so we know how many
1312 * queues and msix vectors have been allocated.
1313 **/
1314void i40e_clear_hw(struct i40e_hw *hw)
1315{
1316 u32 num_queues, base_queue;
1317 u32 num_pf_int;
1318 u32 num_vf_int;
1319 u32 num_vfs;
1320 u32 i, j;
1321 u32 val;
1322 u32 eol = 0x7ff;
1323
1324 /* get number of interrupts, queues, and VFs */
1325 val = rd32(hw, I40E_GLPCI_CNF2);
1326 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1327 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1328 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1329 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1330
1331 val = rd32(hw, I40E_PFLAN_QALLOC);
1332 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1333 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1334 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1335 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1336 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1337 num_queues = (j - base_queue) + 1;
1338 else
1339 num_queues = 0;
1340
1341 val = rd32(hw, I40E_PF_VT_PFALLOC);
1342 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1343 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1344 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1345 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1346 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1347 num_vfs = (j - i) + 1;
1348 else
1349 num_vfs = 0;
1350
1351 /* stop all the interrupts */
1352 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1353 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1354 for (i = 0; i < num_pf_int - 2; i++)
1355 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1356
1357 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1358 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1359 wr32(hw, I40E_PFINT_LNKLST0, val);
1360 for (i = 0; i < num_pf_int - 2; i++)
1361 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1362 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1363 for (i = 0; i < num_vfs; i++)
1364 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1365 for (i = 0; i < num_vf_int - 2; i++)
1366 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1367
1368 /* warn the HW of the coming Tx disables */
1369 for (i = 0; i < num_queues; i++) {
1370 u32 abs_queue_idx = base_queue + i;
1371 u32 reg_block = 0;
1372
1373 if (abs_queue_idx >= 128) {
1374 reg_block = abs_queue_idx / 128;
1375 abs_queue_idx %= 128;
1376 }
1377
1378 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1379 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1380 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1381 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1382
1383 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1384 }
1385 udelay(400);
1386
1387 /* stop all the queues */
1388 for (i = 0; i < num_queues; i++) {
1389 wr32(hw, I40E_QINT_TQCTL(i), 0);
1390 wr32(hw, I40E_QTX_ENA(i), 0);
1391 wr32(hw, I40E_QINT_RQCTL(i), 0);
1392 wr32(hw, I40E_QRX_ENA(i), 0);
1393 }
1394
1395 /* short wait for all queue disables to settle */
1396 udelay(50);
1397}
1398
1399/**
1400 * i40e_clear_pxe_mode - clear pxe operations mode
1401 * @hw: pointer to the hw struct
1402 *
1403 * Make sure all PXE mode settings are cleared, including things
1404 * like descriptor fetch/write-back mode.
1405 **/
1406void i40e_clear_pxe_mode(struct i40e_hw *hw)
1407{
1408 u32 reg;
1409
1410 if (i40e_check_asq_alive(hw))
1411 i40e_aq_clear_pxe_mode(hw, NULL);
1412
1413 /* Clear single descriptor fetch/write-back mode */
1414 reg = rd32(hw, I40E_GLLAN_RCTL_0);
1415
1416 if (hw->revision_id == 0) {
1417 /* As a work around clear PXE_MODE instead of setting it */
1418 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1419 } else {
1420 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1421 }
1422}
1423
1424/**
1425 * i40e_led_is_mine - helper to find matching led
1426 * @hw: pointer to the hw struct
1427 * @idx: index into GPIO registers
1428 *
1429 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1430 */
1431static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1432{
1433 u32 gpio_val = 0;
1434 u32 port;
1435
1436 if (!hw->func_caps.led[idx])
1437 return 0;
1438
1439 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1440 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1441 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1442
1443 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1444 * if it is not our port then ignore
1445 */
1446 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1447 (port != hw->port))
1448 return 0;
1449
1450 return gpio_val;
1451}
1452
1453#define I40E_COMBINED_ACTIVITY 0xA
1454#define I40E_FILTER_ACTIVITY 0xE
1455#define I40E_LINK_ACTIVITY 0xC
1456#define I40E_MAC_ACTIVITY 0xD
1457#define I40E_LED0 22
1458
1459/**
1460 * i40e_led_get - return current on/off mode
1461 * @hw: pointer to the hw struct
1462 *
1463 * The value returned is the 'mode' field as defined in the
1464 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1465 * values are variations of possible behaviors relating to
1466 * blink, link, and wire.
1467 **/
1468u32 i40e_led_get(struct i40e_hw *hw)
1469{
1470 u32 current_mode = 0;
1471 u32 mode = 0;
1472 int i;
1473
1474 /* as per the documentation GPIO 22-29 are the LED
1475 * GPIO pins named LED0..LED7
1476 */
1477 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1478 u32 gpio_val = i40e_led_is_mine(hw, i);
1479
1480 if (!gpio_val)
1481 continue;
1482
1483 /* ignore gpio LED src mode entries related to the activity
1484 * LEDs
1485 */
1486 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1487 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1488 switch (current_mode) {
1489 case I40E_COMBINED_ACTIVITY:
1490 case I40E_FILTER_ACTIVITY:
1491 case I40E_MAC_ACTIVITY:
1492 continue;
1493 default:
1494 break;
1495 }
1496
1497 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1498 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1499 break;
1500 }
1501
1502 return mode;
1503}
1504
1505/**
1506 * i40e_led_set - set new on/off mode
1507 * @hw: pointer to the hw struct
1508 * @mode: 0=off, 0xf=on (else see manual for mode details)
1509 * @blink: true if the LED should blink when on, false if steady
1510 *
1511 * if this function is used to turn on the blink it should
1512 * be used to disable the blink when restoring the original state.
1513 **/
1514void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1515{
1516 u32 current_mode = 0;
1517 int i;
1518
1519 if (mode & 0xfffffff0)
1520 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1521
1522 /* as per the documentation GPIO 22-29 are the LED
1523 * GPIO pins named LED0..LED7
1524 */
1525 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1526 u32 gpio_val = i40e_led_is_mine(hw, i);
1527
1528 if (!gpio_val)
1529 continue;
1530
1531 /* ignore gpio LED src mode entries related to the activity
1532 * LEDs
1533 */
1534 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1535 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1536 switch (current_mode) {
1537 case I40E_COMBINED_ACTIVITY:
1538 case I40E_FILTER_ACTIVITY:
1539 case I40E_MAC_ACTIVITY:
1540 continue;
1541 default:
1542 break;
1543 }
1544
1545 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1546 /* this & is a bit of paranoia, but serves as a range check */
1547 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1548 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1549
1550 if (mode == I40E_LINK_ACTIVITY)
1551 blink = false;
1552
1553 if (blink)
1554 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1555 else
1556 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1557
1558 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1559 break;
1560 }
1561}
1562
1563/* Admin command wrappers */
1564
1565/**
1566 * i40e_aq_get_phy_capabilities
1567 * @hw: pointer to the hw struct
1568 * @abilities: structure for PHY capabilities to be filled
1569 * @qualified_modules: report Qualified Modules
1570 * @report_init: report init capabilities (active are default)
1571 * @cmd_details: pointer to command details structure or NULL
1572 *
1573 * Returns the various PHY abilities supported on the Port.
1574 **/
1575i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1576 bool qualified_modules, bool report_init,
1577 struct i40e_aq_get_phy_abilities_resp *abilities,
1578 struct i40e_asq_cmd_details *cmd_details)
1579{
1580 struct i40e_aq_desc desc;
1581 i40e_status status;
1582 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1583
1584 if (!abilities)
1585 return I40E_ERR_PARAM;
1586
1587 i40e_fill_default_direct_cmd_desc(&desc,
1588 i40e_aqc_opc_get_phy_abilities);
1589
1590 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1591 if (abilities_size > I40E_AQ_LARGE_BUF)
1592 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1593
1594 if (qualified_modules)
1595 desc.params.external.param0 |=
1596 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1597
1598 if (report_init)
1599 desc.params.external.param0 |=
1600 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1601
1602 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1603 cmd_details);
1604
1605 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1606 status = I40E_ERR_UNKNOWN_PHY;
1607
1608 if (report_init)
1609 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1610
1611 return status;
1612}
1613
1614/**
1615 * i40e_aq_set_phy_config
1616 * @hw: pointer to the hw struct
1617 * @config: structure with PHY configuration to be set
1618 * @cmd_details: pointer to command details structure or NULL
1619 *
1620 * Set the various PHY configuration parameters
1621 * supported on the Port.One or more of the Set PHY config parameters may be
1622 * ignored in an MFP mode as the PF may not have the privilege to set some
1623 * of the PHY Config parameters. This status will be indicated by the
1624 * command response.
1625 **/
1626enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1627 struct i40e_aq_set_phy_config *config,
1628 struct i40e_asq_cmd_details *cmd_details)
1629{
1630 struct i40e_aq_desc desc;
1631 struct i40e_aq_set_phy_config *cmd =
1632 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1633 enum i40e_status_code status;
1634
1635 if (!config)
1636 return I40E_ERR_PARAM;
1637
1638 i40e_fill_default_direct_cmd_desc(&desc,
1639 i40e_aqc_opc_set_phy_config);
1640
1641 *cmd = *config;
1642
1643 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1644
1645 return status;
1646}
1647
1648/**
1649 * i40e_set_fc
1650 * @hw: pointer to the hw struct
1651 *
1652 * Set the requested flow control mode using set_phy_config.
1653 **/
1654enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1655 bool atomic_restart)
1656{
1657 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1658 struct i40e_aq_get_phy_abilities_resp abilities;
1659 struct i40e_aq_set_phy_config config;
1660 enum i40e_status_code status;
1661 u8 pause_mask = 0x0;
1662
1663 *aq_failures = 0x0;
1664
1665 switch (fc_mode) {
1666 case I40E_FC_FULL:
1667 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1668 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1669 break;
1670 case I40E_FC_RX_PAUSE:
1671 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1672 break;
1673 case I40E_FC_TX_PAUSE:
1674 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1675 break;
1676 default:
1677 break;
1678 }
1679
1680 /* Get the current phy config */
1681 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1682 NULL);
1683 if (status) {
1684 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1685 return status;
1686 }
1687
1688 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1689 /* clear the old pause settings */
1690 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1691 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1692 /* set the new abilities */
1693 config.abilities |= pause_mask;
1694 /* If the abilities have changed, then set the new config */
1695 if (config.abilities != abilities.abilities) {
1696 /* Auto restart link so settings take effect */
1697 if (atomic_restart)
1698 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1699 /* Copy over all the old settings */
1700 config.phy_type = abilities.phy_type;
1701 config.link_speed = abilities.link_speed;
1702 config.eee_capability = abilities.eee_capability;
1703 config.eeer = abilities.eeer_val;
1704 config.low_power_ctrl = abilities.d3_lpan;
1705 status = i40e_aq_set_phy_config(hw, &config, NULL);
1706
1707 if (status)
1708 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1709 }
1710 /* Update the link info */
1711 status = i40e_update_link_info(hw);
1712 if (status) {
1713 /* Wait a little bit (on 40G cards it sometimes takes a really
1714 * long time for link to come back from the atomic reset)
1715 * and try once more
1716 */
1717 msleep(1000);
1718 status = i40e_update_link_info(hw);
1719 }
1720 if (status)
1721 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1722
1723 return status;
1724}
1725
1726/**
1727 * i40e_aq_clear_pxe_mode
1728 * @hw: pointer to the hw struct
1729 * @cmd_details: pointer to command details structure or NULL
1730 *
1731 * Tell the firmware that the driver is taking over from PXE
1732 **/
1733i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1734 struct i40e_asq_cmd_details *cmd_details)
1735{
1736 i40e_status status;
1737 struct i40e_aq_desc desc;
1738 struct i40e_aqc_clear_pxe *cmd =
1739 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1740
1741 i40e_fill_default_direct_cmd_desc(&desc,
1742 i40e_aqc_opc_clear_pxe_mode);
1743
1744 cmd->rx_cnt = 0x2;
1745
1746 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1747
1748 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1749
1750 return status;
1751}
1752
1753/**
1754 * i40e_aq_set_link_restart_an
1755 * @hw: pointer to the hw struct
1756 * @enable_link: if true: enable link, if false: disable link
1757 * @cmd_details: pointer to command details structure or NULL
1758 *
1759 * Sets up the link and restarts the Auto-Negotiation over the link.
1760 **/
1761i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1762 bool enable_link,
1763 struct i40e_asq_cmd_details *cmd_details)
1764{
1765 struct i40e_aq_desc desc;
1766 struct i40e_aqc_set_link_restart_an *cmd =
1767 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1768 i40e_status status;
1769
1770 i40e_fill_default_direct_cmd_desc(&desc,
1771 i40e_aqc_opc_set_link_restart_an);
1772
1773 cmd->command = I40E_AQ_PHY_RESTART_AN;
1774 if (enable_link)
1775 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1776 else
1777 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1778
1779 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1780
1781 return status;
1782}
1783
1784/**
1785 * i40e_aq_get_link_info
1786 * @hw: pointer to the hw struct
1787 * @enable_lse: enable/disable LinkStatusEvent reporting
1788 * @link: pointer to link status structure - optional
1789 * @cmd_details: pointer to command details structure or NULL
1790 *
1791 * Returns the link status of the adapter.
1792 **/
1793i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1794 bool enable_lse, struct i40e_link_status *link,
1795 struct i40e_asq_cmd_details *cmd_details)
1796{
1797 struct i40e_aq_desc desc;
1798 struct i40e_aqc_get_link_status *resp =
1799 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1800 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1801 i40e_status status;
1802 bool tx_pause, rx_pause;
1803 u16 command_flags;
1804
1805 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1806
1807 if (enable_lse)
1808 command_flags = I40E_AQ_LSE_ENABLE;
1809 else
1810 command_flags = I40E_AQ_LSE_DISABLE;
1811 resp->command_flags = cpu_to_le16(command_flags);
1812
1813 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1814
1815 if (status)
1816 goto aq_get_link_info_exit;
1817
1818 /* save off old link status information */
1819 hw->phy.link_info_old = *hw_link_info;
1820
1821 /* update link status */
1822 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1823 hw->phy.media_type = i40e_get_media_type(hw);
1824 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1825 hw_link_info->link_info = resp->link_info;
1826 hw_link_info->an_info = resp->an_info;
1827 hw_link_info->ext_info = resp->ext_info;
1828 hw_link_info->loopback = resp->loopback;
1829 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1830 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1831
1832 /* update fc info */
1833 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1834 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1835 if (tx_pause & rx_pause)
1836 hw->fc.current_mode = I40E_FC_FULL;
1837 else if (tx_pause)
1838 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1839 else if (rx_pause)
1840 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1841 else
1842 hw->fc.current_mode = I40E_FC_NONE;
1843
1844 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1845 hw_link_info->crc_enable = true;
1846 else
1847 hw_link_info->crc_enable = false;
1848
1849 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1850 hw_link_info->lse_enable = true;
1851 else
1852 hw_link_info->lse_enable = false;
1853
1854 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1855 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1856 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1857
1858 /* save link status information */
1859 if (link)
1860 *link = *hw_link_info;
1861
1862 /* flag cleared so helper functions don't call AQ again */
1863 hw->phy.get_link_info = false;
1864
1865aq_get_link_info_exit:
1866 return status;
1867}
1868
1869/**
1870 * i40e_aq_set_phy_int_mask
1871 * @hw: pointer to the hw struct
1872 * @mask: interrupt mask to be set
1873 * @cmd_details: pointer to command details structure or NULL
1874 *
1875 * Set link interrupt mask.
1876 **/
1877i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1878 u16 mask,
1879 struct i40e_asq_cmd_details *cmd_details)
1880{
1881 struct i40e_aq_desc desc;
1882 struct i40e_aqc_set_phy_int_mask *cmd =
1883 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1884 i40e_status status;
1885
1886 i40e_fill_default_direct_cmd_desc(&desc,
1887 i40e_aqc_opc_set_phy_int_mask);
1888
1889 cmd->event_mask = cpu_to_le16(mask);
1890
1891 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1892
1893 return status;
1894}
1895
1896/**
1897 * i40e_aq_set_phy_debug
1898 * @hw: pointer to the hw struct
1899 * @cmd_flags: debug command flags
1900 * @cmd_details: pointer to command details structure or NULL
1901 *
1902 * Reset the external PHY.
1903 **/
1904enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1905 struct i40e_asq_cmd_details *cmd_details)
1906{
1907 struct i40e_aq_desc desc;
1908 struct i40e_aqc_set_phy_debug *cmd =
1909 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1910 enum i40e_status_code status;
1911
1912 i40e_fill_default_direct_cmd_desc(&desc,
1913 i40e_aqc_opc_set_phy_debug);
1914
1915 cmd->command_flags = cmd_flags;
1916
1917 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1918
1919 return status;
1920}
1921
1922/**
1923 * i40e_aq_add_vsi
1924 * @hw: pointer to the hw struct
1925 * @vsi_ctx: pointer to a vsi context struct
1926 * @cmd_details: pointer to command details structure or NULL
1927 *
1928 * Add a VSI context to the hardware.
1929**/
1930i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1931 struct i40e_vsi_context *vsi_ctx,
1932 struct i40e_asq_cmd_details *cmd_details)
1933{
1934 struct i40e_aq_desc desc;
1935 struct i40e_aqc_add_get_update_vsi *cmd =
1936 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1937 struct i40e_aqc_add_get_update_vsi_completion *resp =
1938 (struct i40e_aqc_add_get_update_vsi_completion *)
1939 &desc.params.raw;
1940 i40e_status status;
1941
1942 i40e_fill_default_direct_cmd_desc(&desc,
1943 i40e_aqc_opc_add_vsi);
1944
1945 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1946 cmd->connection_type = vsi_ctx->connection_type;
1947 cmd->vf_id = vsi_ctx->vf_num;
1948 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1949
1950 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1951
1952 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1953 sizeof(vsi_ctx->info), cmd_details);
1954
1955 if (status)
1956 goto aq_add_vsi_exit;
1957
1958 vsi_ctx->seid = le16_to_cpu(resp->seid);
1959 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1960 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1961 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1962
1963aq_add_vsi_exit:
1964 return status;
1965}
1966
1967/**
1968 * i40e_aq_set_vsi_unicast_promiscuous
1969 * @hw: pointer to the hw struct
1970 * @seid: vsi number
1971 * @set: set unicast promiscuous enable/disable
1972 * @cmd_details: pointer to command details structure or NULL
1973 **/
1974i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1975 u16 seid, bool set,
1976 struct i40e_asq_cmd_details *cmd_details)
1977{
1978 struct i40e_aq_desc desc;
1979 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1980 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1981 i40e_status status;
1982 u16 flags = 0;
1983
1984 i40e_fill_default_direct_cmd_desc(&desc,
1985 i40e_aqc_opc_set_vsi_promiscuous_modes);
1986
1987 if (set) {
1988 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1989 if (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
1990 (hw->aq.api_maj_ver > 1))
1991 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
1992 }
1993
1994 cmd->promiscuous_flags = cpu_to_le16(flags);
1995
1996 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1997 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
1998 (hw->aq.api_maj_ver > 1))
1999 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX);
2000
2001 cmd->seid = cpu_to_le16(seid);
2002 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2003
2004 return status;
2005}
2006
2007/**
2008 * i40e_aq_set_vsi_multicast_promiscuous
2009 * @hw: pointer to the hw struct
2010 * @seid: vsi number
2011 * @set: set multicast promiscuous enable/disable
2012 * @cmd_details: pointer to command details structure or NULL
2013 **/
2014i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2015 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2016{
2017 struct i40e_aq_desc desc;
2018 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2019 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2020 i40e_status status;
2021 u16 flags = 0;
2022
2023 i40e_fill_default_direct_cmd_desc(&desc,
2024 i40e_aqc_opc_set_vsi_promiscuous_modes);
2025
2026 if (set)
2027 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2028
2029 cmd->promiscuous_flags = cpu_to_le16(flags);
2030
2031 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2032
2033 cmd->seid = cpu_to_le16(seid);
2034 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2035
2036 return status;
2037}
2038
2039/**
2040 * i40e_aq_set_vsi_broadcast
2041 * @hw: pointer to the hw struct
2042 * @seid: vsi number
2043 * @set_filter: true to set filter, false to clear filter
2044 * @cmd_details: pointer to command details structure or NULL
2045 *
2046 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2047 **/
2048i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2049 u16 seid, bool set_filter,
2050 struct i40e_asq_cmd_details *cmd_details)
2051{
2052 struct i40e_aq_desc desc;
2053 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2054 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2055 i40e_status status;
2056
2057 i40e_fill_default_direct_cmd_desc(&desc,
2058 i40e_aqc_opc_set_vsi_promiscuous_modes);
2059
2060 if (set_filter)
2061 cmd->promiscuous_flags
2062 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2063 else
2064 cmd->promiscuous_flags
2065 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2066
2067 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2068 cmd->seid = cpu_to_le16(seid);
2069 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2070
2071 return status;
2072}
2073
2074/**
2075 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2076 * @hw: pointer to the hw struct
2077 * @seid: vsi number
2078 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2079 * @cmd_details: pointer to command details structure or NULL
2080 **/
2081i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2082 u16 seid, bool enable,
2083 struct i40e_asq_cmd_details *cmd_details)
2084{
2085 struct i40e_aq_desc desc;
2086 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2087 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2088 i40e_status status;
2089 u16 flags = 0;
2090
2091 i40e_fill_default_direct_cmd_desc(&desc,
2092 i40e_aqc_opc_set_vsi_promiscuous_modes);
2093 if (enable)
2094 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2095
2096 cmd->promiscuous_flags = cpu_to_le16(flags);
2097 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2098 cmd->seid = cpu_to_le16(seid);
2099
2100 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2101
2102 return status;
2103}
2104
2105/**
2106 * i40e_get_vsi_params - get VSI configuration info
2107 * @hw: pointer to the hw struct
2108 * @vsi_ctx: pointer to a vsi context struct
2109 * @cmd_details: pointer to command details structure or NULL
2110 **/
2111i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2112 struct i40e_vsi_context *vsi_ctx,
2113 struct i40e_asq_cmd_details *cmd_details)
2114{
2115 struct i40e_aq_desc desc;
2116 struct i40e_aqc_add_get_update_vsi *cmd =
2117 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2118 struct i40e_aqc_add_get_update_vsi_completion *resp =
2119 (struct i40e_aqc_add_get_update_vsi_completion *)
2120 &desc.params.raw;
2121 i40e_status status;
2122
2123 i40e_fill_default_direct_cmd_desc(&desc,
2124 i40e_aqc_opc_get_vsi_parameters);
2125
2126 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2127
2128 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2129
2130 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2131 sizeof(vsi_ctx->info), NULL);
2132
2133 if (status)
2134 goto aq_get_vsi_params_exit;
2135
2136 vsi_ctx->seid = le16_to_cpu(resp->seid);
2137 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2138 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2139 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2140
2141aq_get_vsi_params_exit:
2142 return status;
2143}
2144
2145/**
2146 * i40e_aq_update_vsi_params
2147 * @hw: pointer to the hw struct
2148 * @vsi_ctx: pointer to a vsi context struct
2149 * @cmd_details: pointer to command details structure or NULL
2150 *
2151 * Update a VSI context.
2152 **/
2153i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2154 struct i40e_vsi_context *vsi_ctx,
2155 struct i40e_asq_cmd_details *cmd_details)
2156{
2157 struct i40e_aq_desc desc;
2158 struct i40e_aqc_add_get_update_vsi *cmd =
2159 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2160 i40e_status status;
2161
2162 i40e_fill_default_direct_cmd_desc(&desc,
2163 i40e_aqc_opc_update_vsi_parameters);
2164 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2165
2166 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2167
2168 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2169 sizeof(vsi_ctx->info), cmd_details);
2170
2171 return status;
2172}
2173
2174/**
2175 * i40e_aq_get_switch_config
2176 * @hw: pointer to the hardware structure
2177 * @buf: pointer to the result buffer
2178 * @buf_size: length of input buffer
2179 * @start_seid: seid to start for the report, 0 == beginning
2180 * @cmd_details: pointer to command details structure or NULL
2181 *
2182 * Fill the buf with switch configuration returned from AdminQ command
2183 **/
2184i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2185 struct i40e_aqc_get_switch_config_resp *buf,
2186 u16 buf_size, u16 *start_seid,
2187 struct i40e_asq_cmd_details *cmd_details)
2188{
2189 struct i40e_aq_desc desc;
2190 struct i40e_aqc_switch_seid *scfg =
2191 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2192 i40e_status status;
2193
2194 i40e_fill_default_direct_cmd_desc(&desc,
2195 i40e_aqc_opc_get_switch_config);
2196 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2197 if (buf_size > I40E_AQ_LARGE_BUF)
2198 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2199 scfg->seid = cpu_to_le16(*start_seid);
2200
2201 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2202 *start_seid = le16_to_cpu(scfg->seid);
2203
2204 return status;
2205}
2206
2207/**
2208 * i40e_aq_get_firmware_version
2209 * @hw: pointer to the hw struct
2210 * @fw_major_version: firmware major version
2211 * @fw_minor_version: firmware minor version
2212 * @fw_build: firmware build number
2213 * @api_major_version: major queue version
2214 * @api_minor_version: minor queue version
2215 * @cmd_details: pointer to command details structure or NULL
2216 *
2217 * Get the firmware version from the admin queue commands
2218 **/
2219i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2220 u16 *fw_major_version, u16 *fw_minor_version,
2221 u32 *fw_build,
2222 u16 *api_major_version, u16 *api_minor_version,
2223 struct i40e_asq_cmd_details *cmd_details)
2224{
2225 struct i40e_aq_desc desc;
2226 struct i40e_aqc_get_version *resp =
2227 (struct i40e_aqc_get_version *)&desc.params.raw;
2228 i40e_status status;
2229
2230 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2231
2232 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2233
2234 if (!status) {
2235 if (fw_major_version)
2236 *fw_major_version = le16_to_cpu(resp->fw_major);
2237 if (fw_minor_version)
2238 *fw_minor_version = le16_to_cpu(resp->fw_minor);
2239 if (fw_build)
2240 *fw_build = le32_to_cpu(resp->fw_build);
2241 if (api_major_version)
2242 *api_major_version = le16_to_cpu(resp->api_major);
2243 if (api_minor_version)
2244 *api_minor_version = le16_to_cpu(resp->api_minor);
2245 }
2246
2247 return status;
2248}
2249
2250/**
2251 * i40e_aq_send_driver_version
2252 * @hw: pointer to the hw struct
2253 * @dv: driver's major, minor version
2254 * @cmd_details: pointer to command details structure or NULL
2255 *
2256 * Send the driver version to the firmware
2257 **/
2258i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2259 struct i40e_driver_version *dv,
2260 struct i40e_asq_cmd_details *cmd_details)
2261{
2262 struct i40e_aq_desc desc;
2263 struct i40e_aqc_driver_version *cmd =
2264 (struct i40e_aqc_driver_version *)&desc.params.raw;
2265 i40e_status status;
2266 u16 len;
2267
2268 if (dv == NULL)
2269 return I40E_ERR_PARAM;
2270
2271 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2272
2273 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2274 cmd->driver_major_ver = dv->major_version;
2275 cmd->driver_minor_ver = dv->minor_version;
2276 cmd->driver_build_ver = dv->build_version;
2277 cmd->driver_subbuild_ver = dv->subbuild_version;
2278
2279 len = 0;
2280 while (len < sizeof(dv->driver_string) &&
2281 (dv->driver_string[len] < 0x80) &&
2282 dv->driver_string[len])
2283 len++;
2284 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2285 len, cmd_details);
2286
2287 return status;
2288}
2289
2290/**
2291 * i40e_get_link_status - get status of the HW network link
2292 * @hw: pointer to the hw struct
2293 * @link_up: pointer to bool (true/false = linkup/linkdown)
2294 *
2295 * Variable link_up true if link is up, false if link is down.
2296 * The variable link_up is invalid if returned value of status != 0
2297 *
2298 * Side effect: LinkStatusEvent reporting becomes enabled
2299 **/
2300i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2301{
2302 i40e_status status = 0;
2303
2304 if (hw->phy.get_link_info) {
2305 status = i40e_update_link_info(hw);
2306
2307 if (status)
2308 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2309 status);
2310 }
2311
2312 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2313
2314 return status;
2315}
2316
2317/**
2318 * i40e_updatelink_status - update status of the HW network link
2319 * @hw: pointer to the hw struct
2320 **/
2321i40e_status i40e_update_link_info(struct i40e_hw *hw)
2322{
2323 struct i40e_aq_get_phy_abilities_resp abilities;
2324 i40e_status status = 0;
2325
2326 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2327 if (status)
2328 return status;
2329
2330 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2331 status = i40e_aq_get_phy_capabilities(hw, false, false,
2332 &abilities, NULL);
2333 if (status)
2334 return status;
2335
2336 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2337 sizeof(hw->phy.link_info.module_type));
2338 }
2339
2340 return status;
2341}
2342
2343/**
2344 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2345 * @hw: pointer to the hw struct
2346 * @uplink_seid: the MAC or other gizmo SEID
2347 * @downlink_seid: the VSI SEID
2348 * @enabled_tc: bitmap of TCs to be enabled
2349 * @default_port: true for default port VSI, false for control port
2350 * @veb_seid: pointer to where to put the resulting VEB SEID
2351 * @enable_stats: true to turn on VEB stats
2352 * @cmd_details: pointer to command details structure or NULL
2353 *
2354 * This asks the FW to add a VEB between the uplink and downlink
2355 * elements. If the uplink SEID is 0, this will be a floating VEB.
2356 **/
2357i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2358 u16 downlink_seid, u8 enabled_tc,
2359 bool default_port, u16 *veb_seid,
2360 bool enable_stats,
2361 struct i40e_asq_cmd_details *cmd_details)
2362{
2363 struct i40e_aq_desc desc;
2364 struct i40e_aqc_add_veb *cmd =
2365 (struct i40e_aqc_add_veb *)&desc.params.raw;
2366 struct i40e_aqc_add_veb_completion *resp =
2367 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2368 i40e_status status;
2369 u16 veb_flags = 0;
2370
2371 /* SEIDs need to either both be set or both be 0 for floating VEB */
2372 if (!!uplink_seid != !!downlink_seid)
2373 return I40E_ERR_PARAM;
2374
2375 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2376
2377 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2378 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2379 cmd->enable_tcs = enabled_tc;
2380 if (!uplink_seid)
2381 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2382 if (default_port)
2383 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2384 else
2385 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2386
2387 /* reverse logic here: set the bitflag to disable the stats */
2388 if (!enable_stats)
2389 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2390
2391 cmd->veb_flags = cpu_to_le16(veb_flags);
2392
2393 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2394
2395 if (!status && veb_seid)
2396 *veb_seid = le16_to_cpu(resp->veb_seid);
2397
2398 return status;
2399}
2400
2401/**
2402 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2403 * @hw: pointer to the hw struct
2404 * @veb_seid: the SEID of the VEB to query
2405 * @switch_id: the uplink switch id
2406 * @floating: set to true if the VEB is floating
2407 * @statistic_index: index of the stats counter block for this VEB
2408 * @vebs_used: number of VEB's used by function
2409 * @vebs_free: total VEB's not reserved by any function
2410 * @cmd_details: pointer to command details structure or NULL
2411 *
2412 * This retrieves the parameters for a particular VEB, specified by
2413 * uplink_seid, and returns them to the caller.
2414 **/
2415i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2416 u16 veb_seid, u16 *switch_id,
2417 bool *floating, u16 *statistic_index,
2418 u16 *vebs_used, u16 *vebs_free,
2419 struct i40e_asq_cmd_details *cmd_details)
2420{
2421 struct i40e_aq_desc desc;
2422 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2423 (struct i40e_aqc_get_veb_parameters_completion *)
2424 &desc.params.raw;
2425 i40e_status status;
2426
2427 if (veb_seid == 0)
2428 return I40E_ERR_PARAM;
2429
2430 i40e_fill_default_direct_cmd_desc(&desc,
2431 i40e_aqc_opc_get_veb_parameters);
2432 cmd_resp->seid = cpu_to_le16(veb_seid);
2433
2434 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2435 if (status)
2436 goto get_veb_exit;
2437
2438 if (switch_id)
2439 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2440 if (statistic_index)
2441 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2442 if (vebs_used)
2443 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2444 if (vebs_free)
2445 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2446 if (floating) {
2447 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2448
2449 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2450 *floating = true;
2451 else
2452 *floating = false;
2453 }
2454
2455get_veb_exit:
2456 return status;
2457}
2458
2459/**
2460 * i40e_aq_add_macvlan
2461 * @hw: pointer to the hw struct
2462 * @seid: VSI for the mac address
2463 * @mv_list: list of macvlans to be added
2464 * @count: length of the list
2465 * @cmd_details: pointer to command details structure or NULL
2466 *
2467 * Add MAC/VLAN addresses to the HW filtering
2468 **/
2469i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2470 struct i40e_aqc_add_macvlan_element_data *mv_list,
2471 u16 count, struct i40e_asq_cmd_details *cmd_details)
2472{
2473 struct i40e_aq_desc desc;
2474 struct i40e_aqc_macvlan *cmd =
2475 (struct i40e_aqc_macvlan *)&desc.params.raw;
2476 i40e_status status;
2477 u16 buf_size;
2478 int i;
2479
2480 if (count == 0 || !mv_list || !hw)
2481 return I40E_ERR_PARAM;
2482
2483 buf_size = count * sizeof(*mv_list);
2484
2485 /* prep the rest of the request */
2486 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2487 cmd->num_addresses = cpu_to_le16(count);
2488 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2489 cmd->seid[1] = 0;
2490 cmd->seid[2] = 0;
2491
2492 for (i = 0; i < count; i++)
2493 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2494 mv_list[i].flags |=
2495 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2496
2497 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2498 if (buf_size > I40E_AQ_LARGE_BUF)
2499 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2500
2501 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2502 cmd_details);
2503
2504 return status;
2505}
2506
2507/**
2508 * i40e_aq_remove_macvlan
2509 * @hw: pointer to the hw struct
2510 * @seid: VSI for the mac address
2511 * @mv_list: list of macvlans to be removed
2512 * @count: length of the list
2513 * @cmd_details: pointer to command details structure or NULL
2514 *
2515 * Remove MAC/VLAN addresses from the HW filtering
2516 **/
2517i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2518 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2519 u16 count, struct i40e_asq_cmd_details *cmd_details)
2520{
2521 struct i40e_aq_desc desc;
2522 struct i40e_aqc_macvlan *cmd =
2523 (struct i40e_aqc_macvlan *)&desc.params.raw;
2524 i40e_status status;
2525 u16 buf_size;
2526
2527 if (count == 0 || !mv_list || !hw)
2528 return I40E_ERR_PARAM;
2529
2530 buf_size = count * sizeof(*mv_list);
2531
2532 /* prep the rest of the request */
2533 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2534 cmd->num_addresses = cpu_to_le16(count);
2535 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2536 cmd->seid[1] = 0;
2537 cmd->seid[2] = 0;
2538
2539 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2540 if (buf_size > I40E_AQ_LARGE_BUF)
2541 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2542
2543 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2544 cmd_details);
2545
2546 return status;
2547}
2548
2549/**
2550 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2551 * @hw: pointer to the hw struct
2552 * @opcode: AQ opcode for add or delete mirror rule
2553 * @sw_seid: Switch SEID (to which rule refers)
2554 * @rule_type: Rule Type (ingress/egress/VLAN)
2555 * @id: Destination VSI SEID or Rule ID
2556 * @count: length of the list
2557 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2558 * @cmd_details: pointer to command details structure or NULL
2559 * @rule_id: Rule ID returned from FW
2560 * @rule_used: Number of rules used in internal switch
2561 * @rule_free: Number of rules free in internal switch
2562 *
2563 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2564 * VEBs/VEPA elements only
2565 **/
2566static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw,
2567 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2568 u16 count, __le16 *mr_list,
2569 struct i40e_asq_cmd_details *cmd_details,
2570 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2571{
2572 struct i40e_aq_desc desc;
2573 struct i40e_aqc_add_delete_mirror_rule *cmd =
2574 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2575 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2576 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2577 i40e_status status;
2578 u16 buf_size;
2579
2580 buf_size = count * sizeof(*mr_list);
2581
2582 /* prep the rest of the request */
2583 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2584 cmd->seid = cpu_to_le16(sw_seid);
2585 cmd->rule_type = cpu_to_le16(rule_type &
2586 I40E_AQC_MIRROR_RULE_TYPE_MASK);
2587 cmd->num_entries = cpu_to_le16(count);
2588 /* Dest VSI for add, rule_id for delete */
2589 cmd->destination = cpu_to_le16(id);
2590 if (mr_list) {
2591 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2592 I40E_AQ_FLAG_RD));
2593 if (buf_size > I40E_AQ_LARGE_BUF)
2594 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2595 }
2596
2597 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2598 cmd_details);
2599 if (!status ||
2600 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2601 if (rule_id)
2602 *rule_id = le16_to_cpu(resp->rule_id);
2603 if (rules_used)
2604 *rules_used = le16_to_cpu(resp->mirror_rules_used);
2605 if (rules_free)
2606 *rules_free = le16_to_cpu(resp->mirror_rules_free);
2607 }
2608 return status;
2609}
2610
2611/**
2612 * i40e_aq_add_mirrorrule - add a mirror rule
2613 * @hw: pointer to the hw struct
2614 * @sw_seid: Switch SEID (to which rule refers)
2615 * @rule_type: Rule Type (ingress/egress/VLAN)
2616 * @dest_vsi: SEID of VSI to which packets will be mirrored
2617 * @count: length of the list
2618 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2619 * @cmd_details: pointer to command details structure or NULL
2620 * @rule_id: Rule ID returned from FW
2621 * @rule_used: Number of rules used in internal switch
2622 * @rule_free: Number of rules free in internal switch
2623 *
2624 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2625 **/
2626i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2627 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2628 struct i40e_asq_cmd_details *cmd_details,
2629 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2630{
2631 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2632 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2633 if (count == 0 || !mr_list)
2634 return I40E_ERR_PARAM;
2635 }
2636
2637 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2638 rule_type, dest_vsi, count, mr_list,
2639 cmd_details, rule_id, rules_used, rules_free);
2640}
2641
2642/**
2643 * i40e_aq_delete_mirrorrule - delete a mirror rule
2644 * @hw: pointer to the hw struct
2645 * @sw_seid: Switch SEID (to which rule refers)
2646 * @rule_type: Rule Type (ingress/egress/VLAN)
2647 * @count: length of the list
2648 * @rule_id: Rule ID that is returned in the receive desc as part of
2649 * add_mirrorrule.
2650 * @mr_list: list of mirrored VLAN IDs to be removed
2651 * @cmd_details: pointer to command details structure or NULL
2652 * @rule_used: Number of rules used in internal switch
2653 * @rule_free: Number of rules free in internal switch
2654 *
2655 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2656 **/
2657i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2658 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2659 struct i40e_asq_cmd_details *cmd_details,
2660 u16 *rules_used, u16 *rules_free)
2661{
2662 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
2663 if (rule_type != I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2664 if (!rule_id)
2665 return I40E_ERR_PARAM;
2666 } else {
2667 /* count and mr_list shall be valid for rule_type INGRESS VLAN
2668 * mirroring. For other rule_type, count and rule_type should
2669 * not matter.
2670 */
2671 if (count == 0 || !mr_list)
2672 return I40E_ERR_PARAM;
2673 }
2674
2675 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2676 rule_type, rule_id, count, mr_list,
2677 cmd_details, NULL, rules_used, rules_free);
2678}
2679
2680/**
2681 * i40e_aq_send_msg_to_vf
2682 * @hw: pointer to the hardware structure
2683 * @vfid: VF id to send msg
2684 * @v_opcode: opcodes for VF-PF communication
2685 * @v_retval: return error code
2686 * @msg: pointer to the msg buffer
2687 * @msglen: msg length
2688 * @cmd_details: pointer to command details
2689 *
2690 * send msg to vf
2691 **/
2692i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2693 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2694 struct i40e_asq_cmd_details *cmd_details)
2695{
2696 struct i40e_aq_desc desc;
2697 struct i40e_aqc_pf_vf_message *cmd =
2698 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2699 i40e_status status;
2700
2701 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2702 cmd->id = cpu_to_le32(vfid);
2703 desc.cookie_high = cpu_to_le32(v_opcode);
2704 desc.cookie_low = cpu_to_le32(v_retval);
2705 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2706 if (msglen) {
2707 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2708 I40E_AQ_FLAG_RD));
2709 if (msglen > I40E_AQ_LARGE_BUF)
2710 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2711 desc.datalen = cpu_to_le16(msglen);
2712 }
2713 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2714
2715 return status;
2716}
2717
2718/**
2719 * i40e_aq_debug_read_register
2720 * @hw: pointer to the hw struct
2721 * @reg_addr: register address
2722 * @reg_val: register value
2723 * @cmd_details: pointer to command details structure or NULL
2724 *
2725 * Read the register using the admin queue commands
2726 **/
2727i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2728 u32 reg_addr, u64 *reg_val,
2729 struct i40e_asq_cmd_details *cmd_details)
2730{
2731 struct i40e_aq_desc desc;
2732 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2733 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2734 i40e_status status;
2735
2736 if (reg_val == NULL)
2737 return I40E_ERR_PARAM;
2738
2739 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2740
2741 cmd_resp->address = cpu_to_le32(reg_addr);
2742
2743 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2744
2745 if (!status) {
2746 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2747 (u64)le32_to_cpu(cmd_resp->value_low);
2748 }
2749
2750 return status;
2751}
2752
2753/**
2754 * i40e_aq_debug_write_register
2755 * @hw: pointer to the hw struct
2756 * @reg_addr: register address
2757 * @reg_val: register value
2758 * @cmd_details: pointer to command details structure or NULL
2759 *
2760 * Write to a register using the admin queue commands
2761 **/
2762i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2763 u32 reg_addr, u64 reg_val,
2764 struct i40e_asq_cmd_details *cmd_details)
2765{
2766 struct i40e_aq_desc desc;
2767 struct i40e_aqc_debug_reg_read_write *cmd =
2768 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2769 i40e_status status;
2770
2771 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2772
2773 cmd->address = cpu_to_le32(reg_addr);
2774 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2775 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2776
2777 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2778
2779 return status;
2780}
2781
2782/**
2783 * i40e_aq_set_hmc_resource_profile
2784 * @hw: pointer to the hw struct
2785 * @profile: type of profile the HMC is to be set as
2786 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
2787 * @cmd_details: pointer to command details structure or NULL
2788 *
2789 * set the HMC profile of the device.
2790 **/
2791i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2792 enum i40e_aq_hmc_profile profile,
2793 u8 pe_vf_enabled_count,
2794 struct i40e_asq_cmd_details *cmd_details)
2795{
2796 struct i40e_aq_desc desc;
2797 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2798 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2799 i40e_status status;
2800
2801 i40e_fill_default_direct_cmd_desc(&desc,
2802 i40e_aqc_opc_set_hmc_resource_profile);
2803
2804 cmd->pm_profile = (u8)profile;
2805 cmd->pe_vf_enabled = pe_vf_enabled_count;
2806
2807 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2808
2809 return status;
2810}
2811
2812/**
2813 * i40e_aq_request_resource
2814 * @hw: pointer to the hw struct
2815 * @resource: resource id
2816 * @access: access type
2817 * @sdp_number: resource number
2818 * @timeout: the maximum time in ms that the driver may hold the resource
2819 * @cmd_details: pointer to command details structure or NULL
2820 *
2821 * requests common resource using the admin queue commands
2822 **/
2823i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2824 enum i40e_aq_resources_ids resource,
2825 enum i40e_aq_resource_access_type access,
2826 u8 sdp_number, u64 *timeout,
2827 struct i40e_asq_cmd_details *cmd_details)
2828{
2829 struct i40e_aq_desc desc;
2830 struct i40e_aqc_request_resource *cmd_resp =
2831 (struct i40e_aqc_request_resource *)&desc.params.raw;
2832 i40e_status status;
2833
2834 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2835
2836 cmd_resp->resource_id = cpu_to_le16(resource);
2837 cmd_resp->access_type = cpu_to_le16(access);
2838 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2839
2840 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2841 /* The completion specifies the maximum time in ms that the driver
2842 * may hold the resource in the Timeout field.
2843 * If the resource is held by someone else, the command completes with
2844 * busy return value and the timeout field indicates the maximum time
2845 * the current owner of the resource has to free it.
2846 */
2847 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2848 *timeout = le32_to_cpu(cmd_resp->timeout);
2849
2850 return status;
2851}
2852
2853/**
2854 * i40e_aq_release_resource
2855 * @hw: pointer to the hw struct
2856 * @resource: resource id
2857 * @sdp_number: resource number
2858 * @cmd_details: pointer to command details structure or NULL
2859 *
2860 * release common resource using the admin queue commands
2861 **/
2862i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2863 enum i40e_aq_resources_ids resource,
2864 u8 sdp_number,
2865 struct i40e_asq_cmd_details *cmd_details)
2866{
2867 struct i40e_aq_desc desc;
2868 struct i40e_aqc_request_resource *cmd =
2869 (struct i40e_aqc_request_resource *)&desc.params.raw;
2870 i40e_status status;
2871
2872 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2873
2874 cmd->resource_id = cpu_to_le16(resource);
2875 cmd->resource_number = cpu_to_le32(sdp_number);
2876
2877 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2878
2879 return status;
2880}
2881
2882/**
2883 * i40e_aq_read_nvm
2884 * @hw: pointer to the hw struct
2885 * @module_pointer: module pointer location in words from the NVM beginning
2886 * @offset: byte offset from the module beginning
2887 * @length: length of the section to be read (in bytes from the offset)
2888 * @data: command buffer (size [bytes] = length)
2889 * @last_command: tells if this is the last command in a series
2890 * @cmd_details: pointer to command details structure or NULL
2891 *
2892 * Read the NVM using the admin queue commands
2893 **/
2894i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2895 u32 offset, u16 length, void *data,
2896 bool last_command,
2897 struct i40e_asq_cmd_details *cmd_details)
2898{
2899 struct i40e_aq_desc desc;
2900 struct i40e_aqc_nvm_update *cmd =
2901 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2902 i40e_status status;
2903
2904 /* In offset the highest byte must be zeroed. */
2905 if (offset & 0xFF000000) {
2906 status = I40E_ERR_PARAM;
2907 goto i40e_aq_read_nvm_exit;
2908 }
2909
2910 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2911
2912 /* If this is the last command in a series, set the proper flag. */
2913 if (last_command)
2914 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2915 cmd->module_pointer = module_pointer;
2916 cmd->offset = cpu_to_le32(offset);
2917 cmd->length = cpu_to_le16(length);
2918
2919 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2920 if (length > I40E_AQ_LARGE_BUF)
2921 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2922
2923 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2924
2925i40e_aq_read_nvm_exit:
2926 return status;
2927}
2928
2929/**
2930 * i40e_aq_erase_nvm
2931 * @hw: pointer to the hw struct
2932 * @module_pointer: module pointer location in words from the NVM beginning
2933 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2934 * @length: length of the section to be erased (expressed in 4 KB)
2935 * @last_command: tells if this is the last command in a series
2936 * @cmd_details: pointer to command details structure or NULL
2937 *
2938 * Erase the NVM sector using the admin queue commands
2939 **/
2940i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2941 u32 offset, u16 length, bool last_command,
2942 struct i40e_asq_cmd_details *cmd_details)
2943{
2944 struct i40e_aq_desc desc;
2945 struct i40e_aqc_nvm_update *cmd =
2946 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2947 i40e_status status;
2948
2949 /* In offset the highest byte must be zeroed. */
2950 if (offset & 0xFF000000) {
2951 status = I40E_ERR_PARAM;
2952 goto i40e_aq_erase_nvm_exit;
2953 }
2954
2955 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2956
2957 /* If this is the last command in a series, set the proper flag. */
2958 if (last_command)
2959 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2960 cmd->module_pointer = module_pointer;
2961 cmd->offset = cpu_to_le32(offset);
2962 cmd->length = cpu_to_le16(length);
2963
2964 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2965
2966i40e_aq_erase_nvm_exit:
2967 return status;
2968}
2969
2970/**
2971 * i40e_parse_discover_capabilities
2972 * @hw: pointer to the hw struct
2973 * @buff: pointer to a buffer containing device/function capability records
2974 * @cap_count: number of capability records in the list
2975 * @list_type_opc: type of capabilities list to parse
2976 *
2977 * Parse the device/function capabilities list.
2978 **/
2979static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2980 u32 cap_count,
2981 enum i40e_admin_queue_opc list_type_opc)
2982{
2983 struct i40e_aqc_list_capabilities_element_resp *cap;
2984 u32 valid_functions, num_functions;
2985 u32 number, logical_id, phys_id;
2986 struct i40e_hw_capabilities *p;
2987 u8 major_rev;
2988 u32 i = 0;
2989 u16 id;
2990
2991 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2992
2993 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2994 p = &hw->dev_caps;
2995 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2996 p = &hw->func_caps;
2997 else
2998 return;
2999
3000 for (i = 0; i < cap_count; i++, cap++) {
3001 id = le16_to_cpu(cap->id);
3002 number = le32_to_cpu(cap->number);
3003 logical_id = le32_to_cpu(cap->logical_id);
3004 phys_id = le32_to_cpu(cap->phys_id);
3005 major_rev = cap->major_rev;
3006
3007 switch (id) {
3008 case I40E_AQ_CAP_ID_SWITCH_MODE:
3009 p->switch_mode = number;
3010 break;
3011 case I40E_AQ_CAP_ID_MNG_MODE:
3012 p->management_mode = number;
3013 break;
3014 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3015 p->npar_enable = number;
3016 break;
3017 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3018 p->os2bmc = number;
3019 break;
3020 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3021 p->valid_functions = number;
3022 break;
3023 case I40E_AQ_CAP_ID_SRIOV:
3024 if (number == 1)
3025 p->sr_iov_1_1 = true;
3026 break;
3027 case I40E_AQ_CAP_ID_VF:
3028 p->num_vfs = number;
3029 p->vf_base_id = logical_id;
3030 break;
3031 case I40E_AQ_CAP_ID_VMDQ:
3032 if (number == 1)
3033 p->vmdq = true;
3034 break;
3035 case I40E_AQ_CAP_ID_8021QBG:
3036 if (number == 1)
3037 p->evb_802_1_qbg = true;
3038 break;
3039 case I40E_AQ_CAP_ID_8021QBR:
3040 if (number == 1)
3041 p->evb_802_1_qbh = true;
3042 break;
3043 case I40E_AQ_CAP_ID_VSI:
3044 p->num_vsis = number;
3045 break;
3046 case I40E_AQ_CAP_ID_DCB:
3047 if (number == 1) {
3048 p->dcb = true;
3049 p->enabled_tcmap = logical_id;
3050 p->maxtc = phys_id;
3051 }
3052 break;
3053 case I40E_AQ_CAP_ID_FCOE:
3054 if (number == 1)
3055 p->fcoe = true;
3056 break;
3057 case I40E_AQ_CAP_ID_ISCSI:
3058 if (number == 1)
3059 p->iscsi = true;
3060 break;
3061 case I40E_AQ_CAP_ID_RSS:
3062 p->rss = true;
3063 p->rss_table_size = number;
3064 p->rss_table_entry_width = logical_id;
3065 break;
3066 case I40E_AQ_CAP_ID_RXQ:
3067 p->num_rx_qp = number;
3068 p->base_queue = phys_id;
3069 break;
3070 case I40E_AQ_CAP_ID_TXQ:
3071 p->num_tx_qp = number;
3072 p->base_queue = phys_id;
3073 break;
3074 case I40E_AQ_CAP_ID_MSIX:
3075 p->num_msix_vectors = number;
3076 break;
3077 case I40E_AQ_CAP_ID_VF_MSIX:
3078 p->num_msix_vectors_vf = number;
3079 break;
3080 case I40E_AQ_CAP_ID_FLEX10:
3081 if (major_rev == 1) {
3082 if (number == 1) {
3083 p->flex10_enable = true;
3084 p->flex10_capable = true;
3085 }
3086 } else {
3087 /* Capability revision >= 2 */
3088 if (number & 1)
3089 p->flex10_enable = true;
3090 if (number & 2)
3091 p->flex10_capable = true;
3092 }
3093 p->flex10_mode = logical_id;
3094 p->flex10_status = phys_id;
3095 break;
3096 case I40E_AQ_CAP_ID_CEM:
3097 if (number == 1)
3098 p->mgmt_cem = true;
3099 break;
3100 case I40E_AQ_CAP_ID_IWARP:
3101 if (number == 1)
3102 p->iwarp = true;
3103 break;
3104 case I40E_AQ_CAP_ID_LED:
3105 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3106 p->led[phys_id] = true;
3107 break;
3108 case I40E_AQ_CAP_ID_SDP:
3109 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3110 p->sdp[phys_id] = true;
3111 break;
3112 case I40E_AQ_CAP_ID_MDIO:
3113 if (number == 1) {
3114 p->mdio_port_num = phys_id;
3115 p->mdio_port_mode = logical_id;
3116 }
3117 break;
3118 case I40E_AQ_CAP_ID_1588:
3119 if (number == 1)
3120 p->ieee_1588 = true;
3121 break;
3122 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3123 p->fd = true;
3124 p->fd_filters_guaranteed = number;
3125 p->fd_filters_best_effort = logical_id;
3126 break;
3127 case I40E_AQ_CAP_ID_WSR_PROT:
3128 p->wr_csr_prot = (u64)number;
3129 p->wr_csr_prot |= (u64)logical_id << 32;
3130 break;
3131 default:
3132 break;
3133 }
3134 }
3135
3136 if (p->fcoe)
3137 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3138
3139 /* Software override ensuring FCoE is disabled if npar or mfp
3140 * mode because it is not supported in these modes.
3141 */
3142 if (p->npar_enable || p->flex10_enable)
3143 p->fcoe = false;
3144
3145 /* count the enabled ports (aka the "not disabled" ports) */
3146 hw->num_ports = 0;
3147 for (i = 0; i < 4; i++) {
3148 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3149 u64 port_cfg = 0;
3150
3151 /* use AQ read to get the physical register offset instead
3152 * of the port relative offset
3153 */
3154 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3155 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3156 hw->num_ports++;
3157 }
3158
3159 valid_functions = p->valid_functions;
3160 num_functions = 0;
3161 while (valid_functions) {
3162 if (valid_functions & 1)
3163 num_functions++;
3164 valid_functions >>= 1;
3165 }
3166
3167 /* partition id is 1-based, and functions are evenly spread
3168 * across the ports as partitions
3169 */
3170 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3171 hw->num_partitions = num_functions / hw->num_ports;
3172
3173 /* additional HW specific goodies that might
3174 * someday be HW version specific
3175 */
3176 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3177}
3178
3179/**
3180 * i40e_aq_discover_capabilities
3181 * @hw: pointer to the hw struct
3182 * @buff: a virtual buffer to hold the capabilities
3183 * @buff_size: Size of the virtual buffer
3184 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3185 * @list_type_opc: capabilities type to discover - pass in the command opcode
3186 * @cmd_details: pointer to command details structure or NULL
3187 *
3188 * Get the device capabilities descriptions from the firmware
3189 **/
3190i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3191 void *buff, u16 buff_size, u16 *data_size,
3192 enum i40e_admin_queue_opc list_type_opc,
3193 struct i40e_asq_cmd_details *cmd_details)
3194{
3195 struct i40e_aqc_list_capabilites *cmd;
3196 struct i40e_aq_desc desc;
3197 i40e_status status = 0;
3198
3199 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3200
3201 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3202 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3203 status = I40E_ERR_PARAM;
3204 goto exit;
3205 }
3206
3207 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3208
3209 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3210 if (buff_size > I40E_AQ_LARGE_BUF)
3211 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3212
3213 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3214 *data_size = le16_to_cpu(desc.datalen);
3215
3216 if (status)
3217 goto exit;
3218
3219 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3220 list_type_opc);
3221
3222exit:
3223 return status;
3224}
3225
3226/**
3227 * i40e_aq_update_nvm
3228 * @hw: pointer to the hw struct
3229 * @module_pointer: module pointer location in words from the NVM beginning
3230 * @offset: byte offset from the module beginning
3231 * @length: length of the section to be written (in bytes from the offset)
3232 * @data: command buffer (size [bytes] = length)
3233 * @last_command: tells if this is the last command in a series
3234 * @cmd_details: pointer to command details structure or NULL
3235 *
3236 * Update the NVM using the admin queue commands
3237 **/
3238i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3239 u32 offset, u16 length, void *data,
3240 bool last_command,
3241 struct i40e_asq_cmd_details *cmd_details)
3242{
3243 struct i40e_aq_desc desc;
3244 struct i40e_aqc_nvm_update *cmd =
3245 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3246 i40e_status status;
3247
3248 /* In offset the highest byte must be zeroed. */
3249 if (offset & 0xFF000000) {
3250 status = I40E_ERR_PARAM;
3251 goto i40e_aq_update_nvm_exit;
3252 }
3253
3254 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3255
3256 /* If this is the last command in a series, set the proper flag. */
3257 if (last_command)
3258 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3259 cmd->module_pointer = module_pointer;
3260 cmd->offset = cpu_to_le32(offset);
3261 cmd->length = cpu_to_le16(length);
3262
3263 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3264 if (length > I40E_AQ_LARGE_BUF)
3265 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3266
3267 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3268
3269i40e_aq_update_nvm_exit:
3270 return status;
3271}
3272
3273/**
3274 * i40e_aq_get_lldp_mib
3275 * @hw: pointer to the hw struct
3276 * @bridge_type: type of bridge requested
3277 * @mib_type: Local, Remote or both Local and Remote MIBs
3278 * @buff: pointer to a user supplied buffer to store the MIB block
3279 * @buff_size: size of the buffer (in bytes)
3280 * @local_len : length of the returned Local LLDP MIB
3281 * @remote_len: length of the returned Remote LLDP MIB
3282 * @cmd_details: pointer to command details structure or NULL
3283 *
3284 * Requests the complete LLDP MIB (entire packet).
3285 **/
3286i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3287 u8 mib_type, void *buff, u16 buff_size,
3288 u16 *local_len, u16 *remote_len,
3289 struct i40e_asq_cmd_details *cmd_details)
3290{
3291 struct i40e_aq_desc desc;
3292 struct i40e_aqc_lldp_get_mib *cmd =
3293 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3294 struct i40e_aqc_lldp_get_mib *resp =
3295 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3296 i40e_status status;
3297
3298 if (buff_size == 0 || !buff)
3299 return I40E_ERR_PARAM;
3300
3301 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3302 /* Indirect Command */
3303 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3304
3305 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3306 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3307 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3308
3309 desc.datalen = cpu_to_le16(buff_size);
3310
3311 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3312 if (buff_size > I40E_AQ_LARGE_BUF)
3313 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3314
3315 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3316 if (!status) {
3317 if (local_len != NULL)
3318 *local_len = le16_to_cpu(resp->local_len);
3319 if (remote_len != NULL)
3320 *remote_len = le16_to_cpu(resp->remote_len);
3321 }
3322
3323 return status;
3324}
3325
3326/**
3327 * i40e_aq_cfg_lldp_mib_change_event
3328 * @hw: pointer to the hw struct
3329 * @enable_update: Enable or Disable event posting
3330 * @cmd_details: pointer to command details structure or NULL
3331 *
3332 * Enable or Disable posting of an event on ARQ when LLDP MIB
3333 * associated with the interface changes
3334 **/
3335i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3336 bool enable_update,
3337 struct i40e_asq_cmd_details *cmd_details)
3338{
3339 struct i40e_aq_desc desc;
3340 struct i40e_aqc_lldp_update_mib *cmd =
3341 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3342 i40e_status status;
3343
3344 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3345
3346 if (!enable_update)
3347 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3348
3349 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3350
3351 return status;
3352}
3353
3354/**
3355 * i40e_aq_stop_lldp
3356 * @hw: pointer to the hw struct
3357 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3358 * @cmd_details: pointer to command details structure or NULL
3359 *
3360 * Stop or Shutdown the embedded LLDP Agent
3361 **/
3362i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3363 struct i40e_asq_cmd_details *cmd_details)
3364{
3365 struct i40e_aq_desc desc;
3366 struct i40e_aqc_lldp_stop *cmd =
3367 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3368 i40e_status status;
3369
3370 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3371
3372 if (shutdown_agent)
3373 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3374
3375 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3376
3377 return status;
3378}
3379
3380/**
3381 * i40e_aq_start_lldp
3382 * @hw: pointer to the hw struct
3383 * @cmd_details: pointer to command details structure or NULL
3384 *
3385 * Start the embedded LLDP Agent on all ports.
3386 **/
3387i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
3388 struct i40e_asq_cmd_details *cmd_details)
3389{
3390 struct i40e_aq_desc desc;
3391 struct i40e_aqc_lldp_start *cmd =
3392 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3393 i40e_status status;
3394
3395 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3396
3397 cmd->command = I40E_AQ_LLDP_AGENT_START;
3398
3399 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3400
3401 return status;
3402}
3403
3404/**
3405 * i40e_aq_get_cee_dcb_config
3406 * @hw: pointer to the hw struct
3407 * @buff: response buffer that stores CEE operational configuration
3408 * @buff_size: size of the buffer passed
3409 * @cmd_details: pointer to command details structure or NULL
3410 *
3411 * Get CEE DCBX mode operational configuration from firmware
3412 **/
3413i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3414 void *buff, u16 buff_size,
3415 struct i40e_asq_cmd_details *cmd_details)
3416{
3417 struct i40e_aq_desc desc;
3418 i40e_status status;
3419
3420 if (buff_size == 0 || !buff)
3421 return I40E_ERR_PARAM;
3422
3423 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3424
3425 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3426 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3427 cmd_details);
3428
3429 return status;
3430}
3431
3432/**
3433 * i40e_aq_add_udp_tunnel
3434 * @hw: pointer to the hw struct
3435 * @udp_port: the UDP port to add
3436 * @header_len: length of the tunneling header length in DWords
3437 * @protocol_index: protocol index type
3438 * @filter_index: pointer to filter index
3439 * @cmd_details: pointer to command details structure or NULL
3440 **/
3441i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3442 u16 udp_port, u8 protocol_index,
3443 u8 *filter_index,
3444 struct i40e_asq_cmd_details *cmd_details)
3445{
3446 struct i40e_aq_desc desc;
3447 struct i40e_aqc_add_udp_tunnel *cmd =
3448 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3449 struct i40e_aqc_del_udp_tunnel_completion *resp =
3450 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3451 i40e_status status;
3452
3453 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3454
3455 cmd->udp_port = cpu_to_le16(udp_port);
3456 cmd->protocol_type = protocol_index;
3457
3458 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3459
3460 if (!status && filter_index)
3461 *filter_index = resp->index;
3462
3463 return status;
3464}
3465
3466/**
3467 * i40e_aq_del_udp_tunnel
3468 * @hw: pointer to the hw struct
3469 * @index: filter index
3470 * @cmd_details: pointer to command details structure or NULL
3471 **/
3472i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3473 struct i40e_asq_cmd_details *cmd_details)
3474{
3475 struct i40e_aq_desc desc;
3476 struct i40e_aqc_remove_udp_tunnel *cmd =
3477 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3478 i40e_status status;
3479
3480 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3481
3482 cmd->index = index;
3483
3484 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3485
3486 return status;
3487}
3488
3489/**
3490 * i40e_aq_delete_element - Delete switch element
3491 * @hw: pointer to the hw struct
3492 * @seid: the SEID to delete from the switch
3493 * @cmd_details: pointer to command details structure or NULL
3494 *
3495 * This deletes a switch element from the switch.
3496 **/
3497i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3498 struct i40e_asq_cmd_details *cmd_details)
3499{
3500 struct i40e_aq_desc desc;
3501 struct i40e_aqc_switch_seid *cmd =
3502 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3503 i40e_status status;
3504
3505 if (seid == 0)
3506 return I40E_ERR_PARAM;
3507
3508 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3509
3510 cmd->seid = cpu_to_le16(seid);
3511
3512 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3513
3514 return status;
3515}
3516
3517/**
3518 * i40e_aq_dcb_updated - DCB Updated Command
3519 * @hw: pointer to the hw struct
3520 * @cmd_details: pointer to command details structure or NULL
3521 *
3522 * EMP will return when the shared RPB settings have been
3523 * recomputed and modified. The retval field in the descriptor
3524 * will be set to 0 when RPB is modified.
3525 **/
3526i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3527 struct i40e_asq_cmd_details *cmd_details)
3528{
3529 struct i40e_aq_desc desc;
3530 i40e_status status;
3531
3532 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3533
3534 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3535
3536 return status;
3537}
3538
3539/**
3540 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3541 * @hw: pointer to the hw struct
3542 * @seid: seid for the physical port/switching component/vsi
3543 * @buff: Indirect buffer to hold data parameters and response
3544 * @buff_size: Indirect buffer size
3545 * @opcode: Tx scheduler AQ command opcode
3546 * @cmd_details: pointer to command details structure or NULL
3547 *
3548 * Generic command handler for Tx scheduler AQ commands
3549 **/
3550static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3551 void *buff, u16 buff_size,
3552 enum i40e_admin_queue_opc opcode,
3553 struct i40e_asq_cmd_details *cmd_details)
3554{
3555 struct i40e_aq_desc desc;
3556 struct i40e_aqc_tx_sched_ind *cmd =
3557 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3558 i40e_status status;
3559 bool cmd_param_flag = false;
3560
3561 switch (opcode) {
3562 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3563 case i40e_aqc_opc_configure_vsi_tc_bw:
3564 case i40e_aqc_opc_enable_switching_comp_ets:
3565 case i40e_aqc_opc_modify_switching_comp_ets:
3566 case i40e_aqc_opc_disable_switching_comp_ets:
3567 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3568 case i40e_aqc_opc_configure_switching_comp_bw_config:
3569 cmd_param_flag = true;
3570 break;
3571 case i40e_aqc_opc_query_vsi_bw_config:
3572 case i40e_aqc_opc_query_vsi_ets_sla_config:
3573 case i40e_aqc_opc_query_switching_comp_ets_config:
3574 case i40e_aqc_opc_query_port_ets_config:
3575 case i40e_aqc_opc_query_switching_comp_bw_config:
3576 cmd_param_flag = false;
3577 break;
3578 default:
3579 return I40E_ERR_PARAM;
3580 }
3581
3582 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3583
3584 /* Indirect command */
3585 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3586 if (cmd_param_flag)
3587 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3588 if (buff_size > I40E_AQ_LARGE_BUF)
3589 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3590
3591 desc.datalen = cpu_to_le16(buff_size);
3592
3593 cmd->vsi_seid = cpu_to_le16(seid);
3594
3595 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3596
3597 return status;
3598}
3599
3600/**
3601 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3602 * @hw: pointer to the hw struct
3603 * @seid: VSI seid
3604 * @credit: BW limit credits (0 = disabled)
3605 * @max_credit: Max BW limit credits
3606 * @cmd_details: pointer to command details structure or NULL
3607 **/
3608i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3609 u16 seid, u16 credit, u8 max_credit,
3610 struct i40e_asq_cmd_details *cmd_details)
3611{
3612 struct i40e_aq_desc desc;
3613 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3614 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3615 i40e_status status;
3616
3617 i40e_fill_default_direct_cmd_desc(&desc,
3618 i40e_aqc_opc_configure_vsi_bw_limit);
3619
3620 cmd->vsi_seid = cpu_to_le16(seid);
3621 cmd->credit = cpu_to_le16(credit);
3622 cmd->max_credit = max_credit;
3623
3624 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3625
3626 return status;
3627}
3628
3629/**
3630 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3631 * @hw: pointer to the hw struct
3632 * @seid: VSI seid
3633 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3634 * @cmd_details: pointer to command details structure or NULL
3635 **/
3636i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3637 u16 seid,
3638 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3639 struct i40e_asq_cmd_details *cmd_details)
3640{
3641 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3642 i40e_aqc_opc_configure_vsi_tc_bw,
3643 cmd_details);
3644}
3645
3646/**
3647 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3648 * @hw: pointer to the hw struct
3649 * @seid: seid of the switching component connected to Physical Port
3650 * @ets_data: Buffer holding ETS parameters
3651 * @cmd_details: pointer to command details structure or NULL
3652 **/
3653i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3654 u16 seid,
3655 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3656 enum i40e_admin_queue_opc opcode,
3657 struct i40e_asq_cmd_details *cmd_details)
3658{
3659 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3660 sizeof(*ets_data), opcode, cmd_details);
3661}
3662
3663/**
3664 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3665 * @hw: pointer to the hw struct
3666 * @seid: seid of the switching component
3667 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3668 * @cmd_details: pointer to command details structure or NULL
3669 **/
3670i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3671 u16 seid,
3672 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3673 struct i40e_asq_cmd_details *cmd_details)
3674{
3675 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3676 i40e_aqc_opc_configure_switching_comp_bw_config,
3677 cmd_details);
3678}
3679
3680/**
3681 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3682 * @hw: pointer to the hw struct
3683 * @seid: seid of the VSI
3684 * @bw_data: Buffer to hold VSI BW configuration
3685 * @cmd_details: pointer to command details structure or NULL
3686 **/
3687i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3688 u16 seid,
3689 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3690 struct i40e_asq_cmd_details *cmd_details)
3691{
3692 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3693 i40e_aqc_opc_query_vsi_bw_config,
3694 cmd_details);
3695}
3696
3697/**
3698 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3699 * @hw: pointer to the hw struct
3700 * @seid: seid of the VSI
3701 * @bw_data: Buffer to hold VSI BW configuration per TC
3702 * @cmd_details: pointer to command details structure or NULL
3703 **/
3704i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3705 u16 seid,
3706 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3707 struct i40e_asq_cmd_details *cmd_details)
3708{
3709 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3710 i40e_aqc_opc_query_vsi_ets_sla_config,
3711 cmd_details);
3712}
3713
3714/**
3715 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3716 * @hw: pointer to the hw struct
3717 * @seid: seid of the switching component
3718 * @bw_data: Buffer to hold switching component's per TC BW config
3719 * @cmd_details: pointer to command details structure or NULL
3720 **/
3721i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3722 u16 seid,
3723 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3724 struct i40e_asq_cmd_details *cmd_details)
3725{
3726 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3727 i40e_aqc_opc_query_switching_comp_ets_config,
3728 cmd_details);
3729}
3730
3731/**
3732 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3733 * @hw: pointer to the hw struct
3734 * @seid: seid of the VSI or switching component connected to Physical Port
3735 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3736 * @cmd_details: pointer to command details structure or NULL
3737 **/
3738i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3739 u16 seid,
3740 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3741 struct i40e_asq_cmd_details *cmd_details)
3742{
3743 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3744 i40e_aqc_opc_query_port_ets_config,
3745 cmd_details);
3746}
3747
3748/**
3749 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3750 * @hw: pointer to the hw struct
3751 * @seid: seid of the switching component
3752 * @bw_data: Buffer to hold switching component's BW configuration
3753 * @cmd_details: pointer to command details structure or NULL
3754 **/
3755i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3756 u16 seid,
3757 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3758 struct i40e_asq_cmd_details *cmd_details)
3759{
3760 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3761 i40e_aqc_opc_query_switching_comp_bw_config,
3762 cmd_details);
3763}
3764
3765/**
3766 * i40e_validate_filter_settings
3767 * @hw: pointer to the hardware structure
3768 * @settings: Filter control settings
3769 *
3770 * Check and validate the filter control settings passed.
3771 * The function checks for the valid filter/context sizes being
3772 * passed for FCoE and PE.
3773 *
3774 * Returns 0 if the values passed are valid and within
3775 * range else returns an error.
3776 **/
3777static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3778 struct i40e_filter_control_settings *settings)
3779{
3780 u32 fcoe_cntx_size, fcoe_filt_size;
3781 u32 pe_cntx_size, pe_filt_size;
3782 u32 fcoe_fmax;
3783 u32 val;
3784
3785 /* Validate FCoE settings passed */
3786 switch (settings->fcoe_filt_num) {
3787 case I40E_HASH_FILTER_SIZE_1K:
3788 case I40E_HASH_FILTER_SIZE_2K:
3789 case I40E_HASH_FILTER_SIZE_4K:
3790 case I40E_HASH_FILTER_SIZE_8K:
3791 case I40E_HASH_FILTER_SIZE_16K:
3792 case I40E_HASH_FILTER_SIZE_32K:
3793 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3794 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3795 break;
3796 default:
3797 return I40E_ERR_PARAM;
3798 }
3799
3800 switch (settings->fcoe_cntx_num) {
3801 case I40E_DMA_CNTX_SIZE_512:
3802 case I40E_DMA_CNTX_SIZE_1K:
3803 case I40E_DMA_CNTX_SIZE_2K:
3804 case I40E_DMA_CNTX_SIZE_4K:
3805 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3806 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3807 break;
3808 default:
3809 return I40E_ERR_PARAM;
3810 }
3811
3812 /* Validate PE settings passed */
3813 switch (settings->pe_filt_num) {
3814 case I40E_HASH_FILTER_SIZE_1K:
3815 case I40E_HASH_FILTER_SIZE_2K:
3816 case I40E_HASH_FILTER_SIZE_4K:
3817 case I40E_HASH_FILTER_SIZE_8K:
3818 case I40E_HASH_FILTER_SIZE_16K:
3819 case I40E_HASH_FILTER_SIZE_32K:
3820 case I40E_HASH_FILTER_SIZE_64K:
3821 case I40E_HASH_FILTER_SIZE_128K:
3822 case I40E_HASH_FILTER_SIZE_256K:
3823 case I40E_HASH_FILTER_SIZE_512K:
3824 case I40E_HASH_FILTER_SIZE_1M:
3825 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3826 pe_filt_size <<= (u32)settings->pe_filt_num;
3827 break;
3828 default:
3829 return I40E_ERR_PARAM;
3830 }
3831
3832 switch (settings->pe_cntx_num) {
3833 case I40E_DMA_CNTX_SIZE_512:
3834 case I40E_DMA_CNTX_SIZE_1K:
3835 case I40E_DMA_CNTX_SIZE_2K:
3836 case I40E_DMA_CNTX_SIZE_4K:
3837 case I40E_DMA_CNTX_SIZE_8K:
3838 case I40E_DMA_CNTX_SIZE_16K:
3839 case I40E_DMA_CNTX_SIZE_32K:
3840 case I40E_DMA_CNTX_SIZE_64K:
3841 case I40E_DMA_CNTX_SIZE_128K:
3842 case I40E_DMA_CNTX_SIZE_256K:
3843 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3844 pe_cntx_size <<= (u32)settings->pe_cntx_num;
3845 break;
3846 default:
3847 return I40E_ERR_PARAM;
3848 }
3849
3850 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3851 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3852 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
3853 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
3854 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3855 return I40E_ERR_INVALID_SIZE;
3856
3857 return 0;
3858}
3859
3860/**
3861 * i40e_set_filter_control
3862 * @hw: pointer to the hardware structure
3863 * @settings: Filter control settings
3864 *
3865 * Set the Queue Filters for PE/FCoE and enable filters required
3866 * for a single PF. It is expected that these settings are programmed
3867 * at the driver initialization time.
3868 **/
3869i40e_status i40e_set_filter_control(struct i40e_hw *hw,
3870 struct i40e_filter_control_settings *settings)
3871{
3872 i40e_status ret = 0;
3873 u32 hash_lut_size = 0;
3874 u32 val;
3875
3876 if (!settings)
3877 return I40E_ERR_PARAM;
3878
3879 /* Validate the input settings */
3880 ret = i40e_validate_filter_settings(hw, settings);
3881 if (ret)
3882 return ret;
3883
3884 /* Read the PF Queue Filter control register */
3885 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
3886
3887 /* Program required PE hash buckets for the PF */
3888 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3889 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
3890 I40E_PFQF_CTL_0_PEHSIZE_MASK;
3891 /* Program required PE contexts for the PF */
3892 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3893 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
3894 I40E_PFQF_CTL_0_PEDSIZE_MASK;
3895
3896 /* Program required FCoE hash buckets for the PF */
3897 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3898 val |= ((u32)settings->fcoe_filt_num <<
3899 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
3900 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3901 /* Program required FCoE DDP contexts for the PF */
3902 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3903 val |= ((u32)settings->fcoe_cntx_num <<
3904 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
3905 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3906
3907 /* Program Hash LUT size for the PF */
3908 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3909 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3910 hash_lut_size = 1;
3911 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
3912 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3913
3914 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3915 if (settings->enable_fdir)
3916 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3917 if (settings->enable_ethtype)
3918 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3919 if (settings->enable_macvlan)
3920 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3921
3922 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
3923
3924 return 0;
3925}
3926
3927/**
3928 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
3929 * @hw: pointer to the hw struct
3930 * @mac_addr: MAC address to use in the filter
3931 * @ethtype: Ethertype to use in the filter
3932 * @flags: Flags that needs to be applied to the filter
3933 * @vsi_seid: seid of the control VSI
3934 * @queue: VSI queue number to send the packet to
3935 * @is_add: Add control packet filter if True else remove
3936 * @stats: Structure to hold information on control filter counts
3937 * @cmd_details: pointer to command details structure or NULL
3938 *
3939 * This command will Add or Remove control packet filter for a control VSI.
3940 * In return it will update the total number of perfect filter count in
3941 * the stats member.
3942 **/
3943i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
3944 u8 *mac_addr, u16 ethtype, u16 flags,
3945 u16 vsi_seid, u16 queue, bool is_add,
3946 struct i40e_control_filter_stats *stats,
3947 struct i40e_asq_cmd_details *cmd_details)
3948{
3949 struct i40e_aq_desc desc;
3950 struct i40e_aqc_add_remove_control_packet_filter *cmd =
3951 (struct i40e_aqc_add_remove_control_packet_filter *)
3952 &desc.params.raw;
3953 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
3954 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
3955 &desc.params.raw;
3956 i40e_status status;
3957
3958 if (vsi_seid == 0)
3959 return I40E_ERR_PARAM;
3960
3961 if (is_add) {
3962 i40e_fill_default_direct_cmd_desc(&desc,
3963 i40e_aqc_opc_add_control_packet_filter);
3964 cmd->queue = cpu_to_le16(queue);
3965 } else {
3966 i40e_fill_default_direct_cmd_desc(&desc,
3967 i40e_aqc_opc_remove_control_packet_filter);
3968 }
3969
3970 if (mac_addr)
3971 ether_addr_copy(cmd->mac, mac_addr);
3972
3973 cmd->etype = cpu_to_le16(ethtype);
3974 cmd->flags = cpu_to_le16(flags);
3975 cmd->seid = cpu_to_le16(vsi_seid);
3976
3977 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3978
3979 if (!status && stats) {
3980 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
3981 stats->etype_used = le16_to_cpu(resp->etype_used);
3982 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
3983 stats->etype_free = le16_to_cpu(resp->etype_free);
3984 }
3985
3986 return status;
3987}
3988
3989/**
3990 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
3991 * @hw: pointer to the hw struct
3992 * @seid: VSI seid to add ethertype filter from
3993 **/
3994#define I40E_FLOW_CONTROL_ETHTYPE 0x8808
3995void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
3996 u16 seid)
3997{
3998 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
3999 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4000 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4001 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4002 i40e_status status;
4003
4004 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4005 seid, 0, true, NULL,
4006 NULL);
4007 if (status)
4008 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4009}
4010
4011/**
4012 * i40e_aq_alternate_read
4013 * @hw: pointer to the hardware structure
4014 * @reg_addr0: address of first dword to be read
4015 * @reg_val0: pointer for data read from 'reg_addr0'
4016 * @reg_addr1: address of second dword to be read
4017 * @reg_val1: pointer for data read from 'reg_addr1'
4018 *
4019 * Read one or two dwords from alternate structure. Fields are indicated
4020 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4021 * is not passed then only register at 'reg_addr0' is read.
4022 *
4023 **/
4024static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
4025 u32 reg_addr0, u32 *reg_val0,
4026 u32 reg_addr1, u32 *reg_val1)
4027{
4028 struct i40e_aq_desc desc;
4029 struct i40e_aqc_alternate_write *cmd_resp =
4030 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4031 i40e_status status;
4032
4033 if (!reg_val0)
4034 return I40E_ERR_PARAM;
4035
4036 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4037 cmd_resp->address0 = cpu_to_le32(reg_addr0);
4038 cmd_resp->address1 = cpu_to_le32(reg_addr1);
4039
4040 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4041
4042 if (!status) {
4043 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4044
4045 if (reg_val1)
4046 *reg_val1 = le32_to_cpu(cmd_resp->data1);
4047 }
4048
4049 return status;
4050}
4051
4052/**
4053 * i40e_aq_resume_port_tx
4054 * @hw: pointer to the hardware structure
4055 * @cmd_details: pointer to command details structure or NULL
4056 *
4057 * Resume port's Tx traffic
4058 **/
4059i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
4060 struct i40e_asq_cmd_details *cmd_details)
4061{
4062 struct i40e_aq_desc desc;
4063 i40e_status status;
4064
4065 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4066
4067 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4068
4069 return status;
4070}
4071
4072/**
4073 * i40e_set_pci_config_data - store PCI bus info
4074 * @hw: pointer to hardware structure
4075 * @link_status: the link status word from PCI config space
4076 *
4077 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4078 **/
4079void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4080{
4081 hw->bus.type = i40e_bus_type_pci_express;
4082
4083 switch (link_status & PCI_EXP_LNKSTA_NLW) {
4084 case PCI_EXP_LNKSTA_NLW_X1:
4085 hw->bus.width = i40e_bus_width_pcie_x1;
4086 break;
4087 case PCI_EXP_LNKSTA_NLW_X2:
4088 hw->bus.width = i40e_bus_width_pcie_x2;
4089 break;
4090 case PCI_EXP_LNKSTA_NLW_X4:
4091 hw->bus.width = i40e_bus_width_pcie_x4;
4092 break;
4093 case PCI_EXP_LNKSTA_NLW_X8:
4094 hw->bus.width = i40e_bus_width_pcie_x8;
4095 break;
4096 default:
4097 hw->bus.width = i40e_bus_width_unknown;
4098 break;
4099 }
4100
4101 switch (link_status & PCI_EXP_LNKSTA_CLS) {
4102 case PCI_EXP_LNKSTA_CLS_2_5GB:
4103 hw->bus.speed = i40e_bus_speed_2500;
4104 break;
4105 case PCI_EXP_LNKSTA_CLS_5_0GB:
4106 hw->bus.speed = i40e_bus_speed_5000;
4107 break;
4108 case PCI_EXP_LNKSTA_CLS_8_0GB:
4109 hw->bus.speed = i40e_bus_speed_8000;
4110 break;
4111 default:
4112 hw->bus.speed = i40e_bus_speed_unknown;
4113 break;
4114 }
4115}
4116
4117/**
4118 * i40e_aq_debug_dump
4119 * @hw: pointer to the hardware structure
4120 * @cluster_id: specific cluster to dump
4121 * @table_id: table id within cluster
4122 * @start_index: index of line in the block to read
4123 * @buff_size: dump buffer size
4124 * @buff: dump buffer
4125 * @ret_buff_size: actual buffer size returned
4126 * @ret_next_table: next block to read
4127 * @ret_next_index: next index to read
4128 *
4129 * Dump internal FW/HW data for debug purposes.
4130 *
4131 **/
4132i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4133 u8 table_id, u32 start_index, u16 buff_size,
4134 void *buff, u16 *ret_buff_size,
4135 u8 *ret_next_table, u32 *ret_next_index,
4136 struct i40e_asq_cmd_details *cmd_details)
4137{
4138 struct i40e_aq_desc desc;
4139 struct i40e_aqc_debug_dump_internals *cmd =
4140 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4141 struct i40e_aqc_debug_dump_internals *resp =
4142 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4143 i40e_status status;
4144
4145 if (buff_size == 0 || !buff)
4146 return I40E_ERR_PARAM;
4147
4148 i40e_fill_default_direct_cmd_desc(&desc,
4149 i40e_aqc_opc_debug_dump_internals);
4150 /* Indirect Command */
4151 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4152 if (buff_size > I40E_AQ_LARGE_BUF)
4153 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4154
4155 cmd->cluster_id = cluster_id;
4156 cmd->table_id = table_id;
4157 cmd->idx = cpu_to_le32(start_index);
4158
4159 desc.datalen = cpu_to_le16(buff_size);
4160
4161 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4162 if (!status) {
4163 if (ret_buff_size)
4164 *ret_buff_size = le16_to_cpu(desc.datalen);
4165 if (ret_next_table)
4166 *ret_next_table = resp->table_id;
4167 if (ret_next_index)
4168 *ret_next_index = le32_to_cpu(resp->idx);
4169 }
4170
4171 return status;
4172}
4173
4174/**
4175 * i40e_read_bw_from_alt_ram
4176 * @hw: pointer to the hardware structure
4177 * @max_bw: pointer for max_bw read
4178 * @min_bw: pointer for min_bw read
4179 * @min_valid: pointer for bool that is true if min_bw is a valid value
4180 * @max_valid: pointer for bool that is true if max_bw is a valid value
4181 *
4182 * Read bw from the alternate ram for the given pf
4183 **/
4184i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4185 u32 *max_bw, u32 *min_bw,
4186 bool *min_valid, bool *max_valid)
4187{
4188 i40e_status status;
4189 u32 max_bw_addr, min_bw_addr;
4190
4191 /* Calculate the address of the min/max bw registers */
4192 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4193 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4194 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4195 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4196 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4197 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4198
4199 /* Read the bandwidths from alt ram */
4200 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4201 min_bw_addr, min_bw);
4202
4203 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4204 *min_valid = true;
4205 else
4206 *min_valid = false;
4207
4208 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4209 *max_valid = true;
4210 else
4211 *max_valid = false;
4212
4213 return status;
4214}
4215
4216/**
4217 * i40e_aq_configure_partition_bw
4218 * @hw: pointer to the hardware structure
4219 * @bw_data: Buffer holding valid pfs and bw limits
4220 * @cmd_details: pointer to command details
4221 *
4222 * Configure partitions guaranteed/max bw
4223 **/
4224i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4225 struct i40e_aqc_configure_partition_bw_data *bw_data,
4226 struct i40e_asq_cmd_details *cmd_details)
4227{
4228 i40e_status status;
4229 struct i40e_aq_desc desc;
4230 u16 bwd_size = sizeof(*bw_data);
4231
4232 i40e_fill_default_direct_cmd_desc(&desc,
4233 i40e_aqc_opc_configure_partition_bw);
4234
4235 /* Indirect command */
4236 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4237 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4238
4239 if (bwd_size > I40E_AQ_LARGE_BUF)
4240 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4241
4242 desc.datalen = cpu_to_le16(bwd_size);
4243
4244 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4245 cmd_details);
4246
4247 return status;
4248}
4249
4250/**
4251 * i40e_read_phy_register
4252 * @hw: pointer to the HW structure
4253 * @page: registers page number
4254 * @reg: register address in the page
4255 * @phy_adr: PHY address on MDIO interface
4256 * @value: PHY register value
4257 *
4258 * Reads specified PHY register value
4259 **/
4260i40e_status i40e_read_phy_register(struct i40e_hw *hw,
4261 u8 page, u16 reg, u8 phy_addr,
4262 u16 *value)
4263{
4264 i40e_status status = I40E_ERR_TIMEOUT;
4265 u32 command = 0;
4266 u16 retry = 1000;
4267 u8 port_num = hw->func_caps.mdio_port_num;
4268
4269 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4270 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4271 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4272 (I40E_MDIO_OPCODE_ADDRESS) |
4273 (I40E_MDIO_STCODE) |
4274 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4275 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4276 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4277 do {
4278 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4279 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4280 status = 0;
4281 break;
4282 }
4283 usleep_range(10, 20);
4284 retry--;
4285 } while (retry);
4286
4287 if (status) {
4288 i40e_debug(hw, I40E_DEBUG_PHY,
4289 "PHY: Can't write command to external PHY.\n");
4290 goto phy_read_end;
4291 }
4292
4293 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4294 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4295 (I40E_MDIO_OPCODE_READ) |
4296 (I40E_MDIO_STCODE) |
4297 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4298 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4299 status = I40E_ERR_TIMEOUT;
4300 retry = 1000;
4301 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4302 do {
4303 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4304 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4305 status = 0;
4306 break;
4307 }
4308 usleep_range(10, 20);
4309 retry--;
4310 } while (retry);
4311
4312 if (!status) {
4313 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4314 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4315 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4316 } else {
4317 i40e_debug(hw, I40E_DEBUG_PHY,
4318 "PHY: Can't read register value from external PHY.\n");
4319 }
4320
4321phy_read_end:
4322 return status;
4323}
4324
4325/**
4326 * i40e_write_phy_register
4327 * @hw: pointer to the HW structure
4328 * @page: registers page number
4329 * @reg: register address in the page
4330 * @phy_adr: PHY address on MDIO interface
4331 * @value: PHY register value
4332 *
4333 * Writes value to specified PHY register
4334 **/
4335i40e_status i40e_write_phy_register(struct i40e_hw *hw,
4336 u8 page, u16 reg, u8 phy_addr,
4337 u16 value)
4338{
4339 i40e_status status = I40E_ERR_TIMEOUT;
4340 u32 command = 0;
4341 u16 retry = 1000;
4342 u8 port_num = hw->func_caps.mdio_port_num;
4343
4344 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4345 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4346 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4347 (I40E_MDIO_OPCODE_ADDRESS) |
4348 (I40E_MDIO_STCODE) |
4349 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4350 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4351 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4352 do {
4353 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4354 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4355 status = 0;
4356 break;
4357 }
4358 usleep_range(10, 20);
4359 retry--;
4360 } while (retry);
4361 if (status) {
4362 i40e_debug(hw, I40E_DEBUG_PHY,
4363 "PHY: Can't write command to external PHY.\n");
4364 goto phy_write_end;
4365 }
4366
4367 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4368 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4369
4370 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4371 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4372 (I40E_MDIO_OPCODE_WRITE) |
4373 (I40E_MDIO_STCODE) |
4374 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4375 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4376 status = I40E_ERR_TIMEOUT;
4377 retry = 1000;
4378 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4379 do {
4380 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4381 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4382 status = 0;
4383 break;
4384 }
4385 usleep_range(10, 20);
4386 retry--;
4387 } while (retry);
4388
4389phy_write_end:
4390 return status;
4391}
4392
4393/**
4394 * i40e_get_phy_address
4395 * @hw: pointer to the HW structure
4396 * @dev_num: PHY port num that address we want
4397 * @phy_addr: Returned PHY address
4398 *
4399 * Gets PHY address for current port
4400 **/
4401u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4402{
4403 u8 port_num = hw->func_caps.mdio_port_num;
4404 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4405
4406 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4407}
4408
4409/**
4410 * i40e_blink_phy_led
4411 * @hw: pointer to the HW structure
4412 * @time: time how long led will blinks in secs
4413 * @interval: gap between LED on and off in msecs
4414 *
4415 * Blinks PHY link LED
4416 **/
4417i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
4418 u32 time, u32 interval)
4419{
4420 i40e_status status = 0;
4421 u32 i;
4422 u16 led_ctl;
4423 u16 gpio_led_port;
4424 u16 led_reg;
4425 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
4426 u8 phy_addr = 0;
4427 u8 port_num;
4428
4429 i = rd32(hw, I40E_PFGEN_PORTNUM);
4430 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4431 phy_addr = i40e_get_phy_address(hw, port_num);
4432
4433 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4434 led_addr++) {
4435 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4436 led_addr, phy_addr, &led_reg);
4437 if (status)
4438 goto phy_blinking_end;
4439 led_ctl = led_reg;
4440 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4441 led_reg = 0;
4442 status = i40e_write_phy_register(hw,
4443 I40E_PHY_COM_REG_PAGE,
4444 led_addr, phy_addr,
4445 led_reg);
4446 if (status)
4447 goto phy_blinking_end;
4448 break;
4449 }
4450 }
4451
4452 if (time > 0 && interval > 0) {
4453 for (i = 0; i < time * 1000; i += interval) {
4454 status = i40e_read_phy_register(hw,
4455 I40E_PHY_COM_REG_PAGE,
4456 led_addr, phy_addr,
4457 &led_reg);
4458 if (status)
4459 goto restore_config;
4460 if (led_reg & I40E_PHY_LED_MANUAL_ON)
4461 led_reg = 0;
4462 else
4463 led_reg = I40E_PHY_LED_MANUAL_ON;
4464 status = i40e_write_phy_register(hw,
4465 I40E_PHY_COM_REG_PAGE,
4466 led_addr, phy_addr,
4467 led_reg);
4468 if (status)
4469 goto restore_config;
4470 msleep(interval);
4471 }
4472 }
4473
4474restore_config:
4475 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4476 phy_addr, led_ctl);
4477
4478phy_blinking_end:
4479 return status;
4480}
4481
4482/**
4483 * i40e_led_get_phy - return current on/off mode
4484 * @hw: pointer to the hw struct
4485 * @led_addr: address of led register to use
4486 * @val: original value of register to use
4487 *
4488 **/
4489i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
4490 u16 *val)
4491{
4492 i40e_status status = 0;
4493 u16 gpio_led_port;
4494 u8 phy_addr = 0;
4495 u16 reg_val;
4496 u16 temp_addr;
4497 u8 port_num;
4498 u32 i;
4499
4500 temp_addr = I40E_PHY_LED_PROV_REG_1;
4501 i = rd32(hw, I40E_PFGEN_PORTNUM);
4502 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4503 phy_addr = i40e_get_phy_address(hw, port_num);
4504
4505 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4506 temp_addr++) {
4507 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4508 temp_addr, phy_addr, ®_val);
4509 if (status)
4510 return status;
4511 *val = reg_val;
4512 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
4513 *led_addr = temp_addr;
4514 break;
4515 }
4516 }
4517 return status;
4518}
4519
4520/**
4521 * i40e_led_set_phy
4522 * @hw: pointer to the HW structure
4523 * @on: true or false
4524 * @mode: original val plus bit for set or ignore
4525 * Set led's on or off when controlled by the PHY
4526 *
4527 **/
4528i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
4529 u16 led_addr, u32 mode)
4530{
4531 i40e_status status = 0;
4532 u16 led_ctl = 0;
4533 u16 led_reg = 0;
4534 u8 phy_addr = 0;
4535 u8 port_num;
4536 u32 i;
4537
4538 i = rd32(hw, I40E_PFGEN_PORTNUM);
4539 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4540 phy_addr = i40e_get_phy_address(hw, port_num);
4541
4542 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4543 phy_addr, &led_reg);
4544 if (status)
4545 return status;
4546 led_ctl = led_reg;
4547 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4548 led_reg = 0;
4549 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4550 led_addr, phy_addr, led_reg);
4551 if (status)
4552 return status;
4553 }
4554 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4555 led_addr, phy_addr, &led_reg);
4556 if (status)
4557 goto restore_config;
4558 if (on)
4559 led_reg = I40E_PHY_LED_MANUAL_ON;
4560 else
4561 led_reg = 0;
4562 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4563 led_addr, phy_addr, led_reg);
4564 if (status)
4565 goto restore_config;
4566 if (mode & I40E_PHY_LED_MODE_ORIG) {
4567 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
4568 status = i40e_write_phy_register(hw,
4569 I40E_PHY_COM_REG_PAGE,
4570 led_addr, phy_addr, led_ctl);
4571 }
4572 return status;
4573restore_config:
4574 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4575 phy_addr, led_ctl);
4576 return status;
4577}
4578
4579/**
4580 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
4581 * @hw: pointer to the hw struct
4582 * @reg_addr: register address
4583 * @reg_val: ptr to register value
4584 * @cmd_details: pointer to command details structure or NULL
4585 *
4586 * Use the firmware to read the Rx control register,
4587 * especially useful if the Rx unit is under heavy pressure
4588 **/
4589i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
4590 u32 reg_addr, u32 *reg_val,
4591 struct i40e_asq_cmd_details *cmd_details)
4592{
4593 struct i40e_aq_desc desc;
4594 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
4595 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4596 i40e_status status;
4597
4598 if (!reg_val)
4599 return I40E_ERR_PARAM;
4600
4601 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
4602
4603 cmd_resp->address = cpu_to_le32(reg_addr);
4604
4605 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4606
4607 if (status == 0)
4608 *reg_val = le32_to_cpu(cmd_resp->value);
4609
4610 return status;
4611}
4612
4613/**
4614 * i40e_read_rx_ctl - read from an Rx control register
4615 * @hw: pointer to the hw struct
4616 * @reg_addr: register address
4617 **/
4618u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
4619{
4620 i40e_status status = 0;
4621 bool use_register;
4622 int retry = 5;
4623 u32 val = 0;
4624
4625 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
4626 if (!use_register) {
4627do_retry:
4628 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
4629 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
4630 usleep_range(1000, 2000);
4631 retry--;
4632 goto do_retry;
4633 }
4634 }
4635
4636 /* if the AQ access failed, try the old-fashioned way */
4637 if (status || use_register)
4638 val = rd32(hw, reg_addr);
4639
4640 return val;
4641}
4642
4643/**
4644 * i40e_aq_rx_ctl_write_register
4645 * @hw: pointer to the hw struct
4646 * @reg_addr: register address
4647 * @reg_val: register value
4648 * @cmd_details: pointer to command details structure or NULL
4649 *
4650 * Use the firmware to write to an Rx control register,
4651 * especially useful if the Rx unit is under heavy pressure
4652 **/
4653i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
4654 u32 reg_addr, u32 reg_val,
4655 struct i40e_asq_cmd_details *cmd_details)
4656{
4657 struct i40e_aq_desc desc;
4658 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
4659 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4660 i40e_status status;
4661
4662 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
4663
4664 cmd->address = cpu_to_le32(reg_addr);
4665 cmd->value = cpu_to_le32(reg_val);
4666
4667 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4668
4669 return status;
4670}
4671
4672/**
4673 * i40e_write_rx_ctl - write to an Rx control register
4674 * @hw: pointer to the hw struct
4675 * @reg_addr: register address
4676 * @reg_val: register value
4677 **/
4678void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
4679{
4680 i40e_status status = 0;
4681 bool use_register;
4682 int retry = 5;
4683
4684 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
4685 if (!use_register) {
4686do_retry:
4687 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
4688 reg_val, NULL);
4689 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
4690 usleep_range(1000, 2000);
4691 retry--;
4692 goto do_retry;
4693 }
4694 }
4695
4696 /* if the AQ access failed, try the old-fashioned way */
4697 if (status || use_register)
4698 wr32(hw, reg_addr, reg_val);
4699}