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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) Overkiz SAS 2012
4 *
5 * Author: Boris BREZILLON <b.brezillon@overkiz.com>
6 */
7
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/clocksource.h>
11#include <linux/clockchips.h>
12#include <linux/interrupt.h>
13#include <linux/irq.h>
14
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/ioport.h>
18#include <linux/io.h>
19#include <linux/mfd/syscon.h>
20#include <linux/platform_device.h>
21#include <linux/pwm.h>
22#include <linux/of.h>
23#include <linux/regmap.h>
24#include <linux/slab.h>
25#include <soc/at91/atmel_tcb.h>
26
27#define NPWM 2
28
29#define ATMEL_TC_ACMR_MASK (ATMEL_TC_ACPA | ATMEL_TC_ACPC | \
30 ATMEL_TC_AEEVT | ATMEL_TC_ASWTRG)
31
32#define ATMEL_TC_BCMR_MASK (ATMEL_TC_BCPB | ATMEL_TC_BCPC | \
33 ATMEL_TC_BEEVT | ATMEL_TC_BSWTRG)
34
35struct atmel_tcb_pwm_device {
36 unsigned div; /* PWM clock divider */
37 unsigned duty; /* PWM duty expressed in clk cycles */
38 unsigned period; /* PWM period expressed in clk cycles */
39};
40
41struct atmel_tcb_channel {
42 u32 enabled;
43 u32 cmr;
44 u32 ra;
45 u32 rb;
46 u32 rc;
47};
48
49struct atmel_tcb_pwm_chip {
50 spinlock_t lock;
51 u8 channel;
52 u8 width;
53 struct regmap *regmap;
54 struct clk *clk;
55 struct clk *gclk;
56 struct clk *slow_clk;
57 struct atmel_tcb_pwm_device pwms[NPWM];
58 struct atmel_tcb_channel bkup;
59};
60
61static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128, 0, };
62
63static inline struct atmel_tcb_pwm_chip *to_tcb_chip(struct pwm_chip *chip)
64{
65 return pwmchip_get_drvdata(chip);
66}
67
68static int atmel_tcb_pwm_request(struct pwm_chip *chip,
69 struct pwm_device *pwm)
70{
71 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
72 struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
73 unsigned cmr;
74 int ret;
75
76 ret = clk_prepare_enable(tcbpwmc->clk);
77 if (ret)
78 return ret;
79
80 tcbpwm->duty = 0;
81 tcbpwm->period = 0;
82 tcbpwm->div = 0;
83
84 guard(spinlock)(&tcbpwmc->lock);
85
86 regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
87 /*
88 * Get init config from Timer Counter registers if
89 * Timer Counter is already configured as a PWM generator.
90 */
91 if (cmr & ATMEL_TC_WAVE) {
92 if (pwm->hwpwm == 0)
93 regmap_read(tcbpwmc->regmap,
94 ATMEL_TC_REG(tcbpwmc->channel, RA),
95 &tcbpwm->duty);
96 else
97 regmap_read(tcbpwmc->regmap,
98 ATMEL_TC_REG(tcbpwmc->channel, RB),
99 &tcbpwm->duty);
100
101 tcbpwm->div = cmr & ATMEL_TC_TCCLKS;
102 regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
103 &tcbpwm->period);
104 cmr &= (ATMEL_TC_TCCLKS | ATMEL_TC_ACMR_MASK |
105 ATMEL_TC_BCMR_MASK);
106 } else
107 cmr = 0;
108
109 cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0;
110 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
111
112 return 0;
113}
114
115static void atmel_tcb_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
116{
117 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
118
119 clk_disable_unprepare(tcbpwmc->clk);
120}
121
122static void atmel_tcb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
123 enum pwm_polarity polarity)
124{
125 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
126 struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
127 unsigned cmr;
128
129 /*
130 * If duty is 0 the timer will be stopped and we have to
131 * configure the output correctly on software trigger:
132 * - set output to high if PWM_POLARITY_INVERSED
133 * - set output to low if PWM_POLARITY_NORMAL
134 *
135 * This is why we're reverting polarity in this case.
136 */
137 if (tcbpwm->duty == 0)
138 polarity = !polarity;
139
140 regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
141
142 /* flush old setting and set the new one */
143 if (pwm->hwpwm == 0) {
144 cmr &= ~ATMEL_TC_ACMR_MASK;
145 if (polarity == PWM_POLARITY_INVERSED)
146 cmr |= ATMEL_TC_ASWTRG_CLEAR;
147 else
148 cmr |= ATMEL_TC_ASWTRG_SET;
149 } else {
150 cmr &= ~ATMEL_TC_BCMR_MASK;
151 if (polarity == PWM_POLARITY_INVERSED)
152 cmr |= ATMEL_TC_BSWTRG_CLEAR;
153 else
154 cmr |= ATMEL_TC_BSWTRG_SET;
155 }
156
157 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
158
159 /*
160 * Use software trigger to apply the new setting.
161 * If both PWM devices in this group are disabled we stop the clock.
162 */
163 if (!(cmr & (ATMEL_TC_ACPC | ATMEL_TC_BCPC))) {
164 regmap_write(tcbpwmc->regmap,
165 ATMEL_TC_REG(tcbpwmc->channel, CCR),
166 ATMEL_TC_SWTRG | ATMEL_TC_CLKDIS);
167 tcbpwmc->bkup.enabled = 1;
168 } else {
169 regmap_write(tcbpwmc->regmap,
170 ATMEL_TC_REG(tcbpwmc->channel, CCR),
171 ATMEL_TC_SWTRG);
172 tcbpwmc->bkup.enabled = 0;
173 }
174}
175
176static int atmel_tcb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm,
177 enum pwm_polarity polarity)
178{
179 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
180 struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
181 u32 cmr;
182
183 /*
184 * If duty is 0 the timer will be stopped and we have to
185 * configure the output correctly on software trigger:
186 * - set output to high if PWM_POLARITY_INVERSED
187 * - set output to low if PWM_POLARITY_NORMAL
188 *
189 * This is why we're reverting polarity in this case.
190 */
191 if (tcbpwm->duty == 0)
192 polarity = !polarity;
193
194 regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
195
196 /* flush old setting and set the new one */
197 cmr &= ~ATMEL_TC_TCCLKS;
198
199 if (pwm->hwpwm == 0) {
200 cmr &= ~ATMEL_TC_ACMR_MASK;
201
202 /* Set CMR flags according to given polarity */
203 if (polarity == PWM_POLARITY_INVERSED)
204 cmr |= ATMEL_TC_ASWTRG_CLEAR;
205 else
206 cmr |= ATMEL_TC_ASWTRG_SET;
207 } else {
208 cmr &= ~ATMEL_TC_BCMR_MASK;
209 if (polarity == PWM_POLARITY_INVERSED)
210 cmr |= ATMEL_TC_BSWTRG_CLEAR;
211 else
212 cmr |= ATMEL_TC_BSWTRG_SET;
213 }
214
215 /*
216 * If duty is 0 or equal to period there's no need to register
217 * a specific action on RA/RB and RC compare.
218 * The output will be configured on software trigger and keep
219 * this config till next config call.
220 */
221 if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) {
222 if (pwm->hwpwm == 0) {
223 if (polarity == PWM_POLARITY_INVERSED)
224 cmr |= ATMEL_TC_ACPA_SET | ATMEL_TC_ACPC_CLEAR;
225 else
226 cmr |= ATMEL_TC_ACPA_CLEAR | ATMEL_TC_ACPC_SET;
227 } else {
228 if (polarity == PWM_POLARITY_INVERSED)
229 cmr |= ATMEL_TC_BCPB_SET | ATMEL_TC_BCPC_CLEAR;
230 else
231 cmr |= ATMEL_TC_BCPB_CLEAR | ATMEL_TC_BCPC_SET;
232 }
233 }
234
235 cmr |= (tcbpwm->div & ATMEL_TC_TCCLKS);
236
237 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
238
239 if (pwm->hwpwm == 0)
240 regmap_write(tcbpwmc->regmap,
241 ATMEL_TC_REG(tcbpwmc->channel, RA),
242 tcbpwm->duty);
243 else
244 regmap_write(tcbpwmc->regmap,
245 ATMEL_TC_REG(tcbpwmc->channel, RB),
246 tcbpwm->duty);
247
248 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
249 tcbpwm->period);
250
251 /* Use software trigger to apply the new setting */
252 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR),
253 ATMEL_TC_SWTRG | ATMEL_TC_CLKEN);
254 tcbpwmc->bkup.enabled = 1;
255 return 0;
256}
257
258static int atmel_tcb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
259 int duty_ns, int period_ns)
260{
261 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
262 struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm];
263 /* companion PWM sharing register values period and div */
264 struct atmel_tcb_pwm_device *atcbpwm = &tcbpwmc->pwms[pwm->hwpwm ^ 1];
265 int i = 0;
266 int slowclk = 0;
267 unsigned period;
268 unsigned duty;
269 unsigned rate = clk_get_rate(tcbpwmc->clk);
270 unsigned long long min;
271 unsigned long long max;
272
273 /*
274 * Find best clk divisor:
275 * the smallest divisor which can fulfill the period_ns requirements.
276 * If there is a gclk, the first divisor is actually the gclk selector
277 */
278 if (tcbpwmc->gclk)
279 i = 1;
280 for (; i < ARRAY_SIZE(atmel_tcb_divisors); ++i) {
281 if (atmel_tcb_divisors[i] == 0) {
282 slowclk = i;
283 continue;
284 }
285 min = div_u64((u64)NSEC_PER_SEC * atmel_tcb_divisors[i], rate);
286 max = min << tcbpwmc->width;
287 if (max >= period_ns)
288 break;
289 }
290
291 /*
292 * If none of the divisor are small enough to represent period_ns
293 * take slow clock (32KHz).
294 */
295 if (i == ARRAY_SIZE(atmel_tcb_divisors)) {
296 i = slowclk;
297 rate = clk_get_rate(tcbpwmc->slow_clk);
298 min = div_u64(NSEC_PER_SEC, rate);
299 max = min << tcbpwmc->width;
300
301 /* If period is too big return ERANGE error */
302 if (max < period_ns)
303 return -ERANGE;
304 }
305
306 duty = div_u64(duty_ns, min);
307 period = div_u64(period_ns, min);
308
309 /*
310 * PWM devices provided by the TCB driver are grouped by 2.
311 * PWM devices in a given group must be configured with the
312 * same period_ns.
313 *
314 * We're checking the period value of the second PWM device
315 * in this group before applying the new config.
316 */
317 if ((atcbpwm->duty > 0 && atcbpwm->duty != atcbpwm->period) &&
318 (atcbpwm->div != i || atcbpwm->period != period)) {
319 dev_err(pwmchip_parent(chip),
320 "failed to configure period_ns: PWM group already configured with a different value\n");
321 return -EINVAL;
322 }
323
324 tcbpwm->period = period;
325 tcbpwm->div = i;
326 tcbpwm->duty = duty;
327
328 return 0;
329}
330
331static int atmel_tcb_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
332 const struct pwm_state *state)
333{
334 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
335 int duty_cycle, period;
336 int ret;
337
338 guard(spinlock)(&tcbpwmc->lock);
339
340 if (!state->enabled) {
341 atmel_tcb_pwm_disable(chip, pwm, state->polarity);
342 return 0;
343 }
344
345 period = min(state->period, INT_MAX);
346 duty_cycle = min(state->duty_cycle, INT_MAX);
347
348 ret = atmel_tcb_pwm_config(chip, pwm, duty_cycle, period);
349 if (ret)
350 return ret;
351
352 return atmel_tcb_pwm_enable(chip, pwm, state->polarity);
353}
354
355static const struct pwm_ops atmel_tcb_pwm_ops = {
356 .request = atmel_tcb_pwm_request,
357 .free = atmel_tcb_pwm_free,
358 .apply = atmel_tcb_pwm_apply,
359};
360
361static struct atmel_tcb_config tcb_rm9200_config = {
362 .counter_width = 16,
363};
364
365static struct atmel_tcb_config tcb_sam9x5_config = {
366 .counter_width = 32,
367};
368
369static struct atmel_tcb_config tcb_sama5d2_config = {
370 .counter_width = 32,
371 .has_gclk = 1,
372};
373
374static const struct of_device_id atmel_tcb_of_match[] = {
375 { .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
376 { .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
377 { .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
378 { /* sentinel */ }
379};
380
381static int atmel_tcb_pwm_probe(struct platform_device *pdev)
382{
383 struct pwm_chip *chip;
384 const struct of_device_id *match;
385 struct atmel_tcb_pwm_chip *tcbpwmc;
386 const struct atmel_tcb_config *config;
387 struct device_node *np = pdev->dev.of_node;
388 char clk_name[] = "t0_clk";
389 int err;
390 int channel;
391
392 chip = devm_pwmchip_alloc(&pdev->dev, NPWM, sizeof(*tcbpwmc));
393 if (IS_ERR(chip))
394 return PTR_ERR(chip);
395 tcbpwmc = to_tcb_chip(chip);
396
397 err = of_property_read_u32(np, "reg", &channel);
398 if (err < 0) {
399 dev_err(&pdev->dev,
400 "failed to get Timer Counter Block channel from device tree (error: %d)\n",
401 err);
402 return err;
403 }
404
405 tcbpwmc->regmap = syscon_node_to_regmap(np->parent);
406 if (IS_ERR(tcbpwmc->regmap))
407 return PTR_ERR(tcbpwmc->regmap);
408
409 tcbpwmc->slow_clk = of_clk_get_by_name(np->parent, "slow_clk");
410 if (IS_ERR(tcbpwmc->slow_clk))
411 return PTR_ERR(tcbpwmc->slow_clk);
412
413 clk_name[1] += channel;
414 tcbpwmc->clk = of_clk_get_by_name(np->parent, clk_name);
415 if (IS_ERR(tcbpwmc->clk))
416 tcbpwmc->clk = of_clk_get_by_name(np->parent, "t0_clk");
417 if (IS_ERR(tcbpwmc->clk)) {
418 err = PTR_ERR(tcbpwmc->clk);
419 goto err_slow_clk;
420 }
421
422 match = of_match_node(atmel_tcb_of_match, np->parent);
423 config = match->data;
424
425 if (config->has_gclk) {
426 tcbpwmc->gclk = of_clk_get_by_name(np->parent, "gclk");
427 if (IS_ERR(tcbpwmc->gclk)) {
428 err = PTR_ERR(tcbpwmc->gclk);
429 goto err_clk;
430 }
431 }
432
433 chip->ops = &atmel_tcb_pwm_ops;
434 tcbpwmc->channel = channel;
435 tcbpwmc->width = config->counter_width;
436
437 err = clk_prepare_enable(tcbpwmc->slow_clk);
438 if (err)
439 goto err_gclk;
440
441 spin_lock_init(&tcbpwmc->lock);
442
443 err = pwmchip_add(chip);
444 if (err < 0)
445 goto err_disable_clk;
446
447 platform_set_drvdata(pdev, chip);
448
449 return 0;
450
451err_disable_clk:
452 clk_disable_unprepare(tcbpwmc->slow_clk);
453
454err_gclk:
455 clk_put(tcbpwmc->gclk);
456
457err_clk:
458 clk_put(tcbpwmc->clk);
459
460err_slow_clk:
461 clk_put(tcbpwmc->slow_clk);
462
463 return err;
464}
465
466static void atmel_tcb_pwm_remove(struct platform_device *pdev)
467{
468 struct pwm_chip *chip = platform_get_drvdata(pdev);
469 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
470
471 pwmchip_remove(chip);
472
473 clk_disable_unprepare(tcbpwmc->slow_clk);
474 clk_put(tcbpwmc->gclk);
475 clk_put(tcbpwmc->clk);
476 clk_put(tcbpwmc->slow_clk);
477}
478
479static const struct of_device_id atmel_tcb_pwm_dt_ids[] = {
480 { .compatible = "atmel,tcb-pwm", },
481 { /* sentinel */ }
482};
483MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids);
484
485static int atmel_tcb_pwm_suspend(struct device *dev)
486{
487 struct pwm_chip *chip = dev_get_drvdata(dev);
488 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
489 struct atmel_tcb_channel *chan = &tcbpwmc->bkup;
490 unsigned int channel = tcbpwmc->channel;
491
492 regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(channel, CMR), &chan->cmr);
493 regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(channel, RA), &chan->ra);
494 regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(channel, RB), &chan->rb);
495 regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(channel, RC), &chan->rc);
496
497 return 0;
498}
499
500static int atmel_tcb_pwm_resume(struct device *dev)
501{
502 struct pwm_chip *chip = dev_get_drvdata(dev);
503 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
504 struct atmel_tcb_channel *chan = &tcbpwmc->bkup;
505 unsigned int channel = tcbpwmc->channel;
506
507 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(channel, CMR), chan->cmr);
508 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(channel, RA), chan->ra);
509 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(channel, RB), chan->rb);
510 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(channel, RC), chan->rc);
511
512 if (chan->enabled)
513 regmap_write(tcbpwmc->regmap,
514 ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
515 ATMEL_TC_REG(channel, CCR));
516
517 return 0;
518}
519
520static DEFINE_SIMPLE_DEV_PM_OPS(atmel_tcb_pwm_pm_ops, atmel_tcb_pwm_suspend,
521 atmel_tcb_pwm_resume);
522
523static struct platform_driver atmel_tcb_pwm_driver = {
524 .driver = {
525 .name = "atmel-tcb-pwm",
526 .of_match_table = atmel_tcb_pwm_dt_ids,
527 .pm = pm_ptr(&atmel_tcb_pwm_pm_ops),
528 },
529 .probe = atmel_tcb_pwm_probe,
530 .remove = atmel_tcb_pwm_remove,
531};
532module_platform_driver(atmel_tcb_pwm_driver);
533
534MODULE_AUTHOR("Boris BREZILLON <b.brezillon@overkiz.com>");
535MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver");
536MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) Overkiz SAS 2012
4 *
5 * Author: Boris BREZILLON <b.brezillon@overkiz.com>
6 */
7
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/clocksource.h>
11#include <linux/clockchips.h>
12#include <linux/interrupt.h>
13#include <linux/irq.h>
14
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/ioport.h>
18#include <linux/io.h>
19#include <linux/platform_device.h>
20#include <linux/pwm.h>
21#include <linux/of_device.h>
22#include <linux/slab.h>
23#include <soc/at91/atmel_tcb.h>
24
25#define NPWM 6
26
27#define ATMEL_TC_ACMR_MASK (ATMEL_TC_ACPA | ATMEL_TC_ACPC | \
28 ATMEL_TC_AEEVT | ATMEL_TC_ASWTRG)
29
30#define ATMEL_TC_BCMR_MASK (ATMEL_TC_BCPB | ATMEL_TC_BCPC | \
31 ATMEL_TC_BEEVT | ATMEL_TC_BSWTRG)
32
33struct atmel_tcb_pwm_device {
34 enum pwm_polarity polarity; /* PWM polarity */
35 unsigned div; /* PWM clock divider */
36 unsigned duty; /* PWM duty expressed in clk cycles */
37 unsigned period; /* PWM period expressed in clk cycles */
38};
39
40struct atmel_tcb_channel {
41 u32 enabled;
42 u32 cmr;
43 u32 ra;
44 u32 rb;
45 u32 rc;
46};
47
48struct atmel_tcb_pwm_chip {
49 struct pwm_chip chip;
50 spinlock_t lock;
51 struct atmel_tc *tc;
52 struct atmel_tcb_pwm_device *pwms[NPWM];
53 struct atmel_tcb_channel bkup[NPWM / 2];
54};
55
56static inline struct atmel_tcb_pwm_chip *to_tcb_chip(struct pwm_chip *chip)
57{
58 return container_of(chip, struct atmel_tcb_pwm_chip, chip);
59}
60
61static int atmel_tcb_pwm_set_polarity(struct pwm_chip *chip,
62 struct pwm_device *pwm,
63 enum pwm_polarity polarity)
64{
65 struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
66
67 tcbpwm->polarity = polarity;
68
69 return 0;
70}
71
72static int atmel_tcb_pwm_request(struct pwm_chip *chip,
73 struct pwm_device *pwm)
74{
75 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
76 struct atmel_tcb_pwm_device *tcbpwm;
77 struct atmel_tc *tc = tcbpwmc->tc;
78 void __iomem *regs = tc->regs;
79 unsigned group = pwm->hwpwm / 2;
80 unsigned index = pwm->hwpwm % 2;
81 unsigned cmr;
82 int ret;
83
84 tcbpwm = devm_kzalloc(chip->dev, sizeof(*tcbpwm), GFP_KERNEL);
85 if (!tcbpwm)
86 return -ENOMEM;
87
88 ret = clk_prepare_enable(tc->clk[group]);
89 if (ret) {
90 devm_kfree(chip->dev, tcbpwm);
91 return ret;
92 }
93
94 pwm_set_chip_data(pwm, tcbpwm);
95 tcbpwm->polarity = PWM_POLARITY_NORMAL;
96 tcbpwm->duty = 0;
97 tcbpwm->period = 0;
98 tcbpwm->div = 0;
99
100 spin_lock(&tcbpwmc->lock);
101 cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR));
102 /*
103 * Get init config from Timer Counter registers if
104 * Timer Counter is already configured as a PWM generator.
105 */
106 if (cmr & ATMEL_TC_WAVE) {
107 if (index == 0)
108 tcbpwm->duty =
109 __raw_readl(regs + ATMEL_TC_REG(group, RA));
110 else
111 tcbpwm->duty =
112 __raw_readl(regs + ATMEL_TC_REG(group, RB));
113
114 tcbpwm->div = cmr & ATMEL_TC_TCCLKS;
115 tcbpwm->period = __raw_readl(regs + ATMEL_TC_REG(group, RC));
116 cmr &= (ATMEL_TC_TCCLKS | ATMEL_TC_ACMR_MASK |
117 ATMEL_TC_BCMR_MASK);
118 } else
119 cmr = 0;
120
121 cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0;
122 __raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR));
123 spin_unlock(&tcbpwmc->lock);
124
125 tcbpwmc->pwms[pwm->hwpwm] = tcbpwm;
126
127 return 0;
128}
129
130static void atmel_tcb_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
131{
132 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
133 struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
134 struct atmel_tc *tc = tcbpwmc->tc;
135
136 clk_disable_unprepare(tc->clk[pwm->hwpwm / 2]);
137 tcbpwmc->pwms[pwm->hwpwm] = NULL;
138 devm_kfree(chip->dev, tcbpwm);
139}
140
141static void atmel_tcb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
142{
143 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
144 struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
145 struct atmel_tc *tc = tcbpwmc->tc;
146 void __iomem *regs = tc->regs;
147 unsigned group = pwm->hwpwm / 2;
148 unsigned index = pwm->hwpwm % 2;
149 unsigned cmr;
150 enum pwm_polarity polarity = tcbpwm->polarity;
151
152 /*
153 * If duty is 0 the timer will be stopped and we have to
154 * configure the output correctly on software trigger:
155 * - set output to high if PWM_POLARITY_INVERSED
156 * - set output to low if PWM_POLARITY_NORMAL
157 *
158 * This is why we're reverting polarity in this case.
159 */
160 if (tcbpwm->duty == 0)
161 polarity = !polarity;
162
163 spin_lock(&tcbpwmc->lock);
164 cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR));
165
166 /* flush old setting and set the new one */
167 if (index == 0) {
168 cmr &= ~ATMEL_TC_ACMR_MASK;
169 if (polarity == PWM_POLARITY_INVERSED)
170 cmr |= ATMEL_TC_ASWTRG_CLEAR;
171 else
172 cmr |= ATMEL_TC_ASWTRG_SET;
173 } else {
174 cmr &= ~ATMEL_TC_BCMR_MASK;
175 if (polarity == PWM_POLARITY_INVERSED)
176 cmr |= ATMEL_TC_BSWTRG_CLEAR;
177 else
178 cmr |= ATMEL_TC_BSWTRG_SET;
179 }
180
181 __raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR));
182
183 /*
184 * Use software trigger to apply the new setting.
185 * If both PWM devices in this group are disabled we stop the clock.
186 */
187 if (!(cmr & (ATMEL_TC_ACPC | ATMEL_TC_BCPC))) {
188 __raw_writel(ATMEL_TC_SWTRG | ATMEL_TC_CLKDIS,
189 regs + ATMEL_TC_REG(group, CCR));
190 tcbpwmc->bkup[group].enabled = 1;
191 } else {
192 __raw_writel(ATMEL_TC_SWTRG, regs +
193 ATMEL_TC_REG(group, CCR));
194 tcbpwmc->bkup[group].enabled = 0;
195 }
196
197 spin_unlock(&tcbpwmc->lock);
198}
199
200static int atmel_tcb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
201{
202 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
203 struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
204 struct atmel_tc *tc = tcbpwmc->tc;
205 void __iomem *regs = tc->regs;
206 unsigned group = pwm->hwpwm / 2;
207 unsigned index = pwm->hwpwm % 2;
208 u32 cmr;
209 enum pwm_polarity polarity = tcbpwm->polarity;
210
211 /*
212 * If duty is 0 the timer will be stopped and we have to
213 * configure the output correctly on software trigger:
214 * - set output to high if PWM_POLARITY_INVERSED
215 * - set output to low if PWM_POLARITY_NORMAL
216 *
217 * This is why we're reverting polarity in this case.
218 */
219 if (tcbpwm->duty == 0)
220 polarity = !polarity;
221
222 spin_lock(&tcbpwmc->lock);
223 cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR));
224
225 /* flush old setting and set the new one */
226 cmr &= ~ATMEL_TC_TCCLKS;
227
228 if (index == 0) {
229 cmr &= ~ATMEL_TC_ACMR_MASK;
230
231 /* Set CMR flags according to given polarity */
232 if (polarity == PWM_POLARITY_INVERSED)
233 cmr |= ATMEL_TC_ASWTRG_CLEAR;
234 else
235 cmr |= ATMEL_TC_ASWTRG_SET;
236 } else {
237 cmr &= ~ATMEL_TC_BCMR_MASK;
238 if (polarity == PWM_POLARITY_INVERSED)
239 cmr |= ATMEL_TC_BSWTRG_CLEAR;
240 else
241 cmr |= ATMEL_TC_BSWTRG_SET;
242 }
243
244 /*
245 * If duty is 0 or equal to period there's no need to register
246 * a specific action on RA/RB and RC compare.
247 * The output will be configured on software trigger and keep
248 * this config till next config call.
249 */
250 if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) {
251 if (index == 0) {
252 if (polarity == PWM_POLARITY_INVERSED)
253 cmr |= ATMEL_TC_ACPA_SET | ATMEL_TC_ACPC_CLEAR;
254 else
255 cmr |= ATMEL_TC_ACPA_CLEAR | ATMEL_TC_ACPC_SET;
256 } else {
257 if (polarity == PWM_POLARITY_INVERSED)
258 cmr |= ATMEL_TC_BCPB_SET | ATMEL_TC_BCPC_CLEAR;
259 else
260 cmr |= ATMEL_TC_BCPB_CLEAR | ATMEL_TC_BCPC_SET;
261 }
262 }
263
264 cmr |= (tcbpwm->div & ATMEL_TC_TCCLKS);
265
266 __raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR));
267
268 if (index == 0)
269 __raw_writel(tcbpwm->duty, regs + ATMEL_TC_REG(group, RA));
270 else
271 __raw_writel(tcbpwm->duty, regs + ATMEL_TC_REG(group, RB));
272
273 __raw_writel(tcbpwm->period, regs + ATMEL_TC_REG(group, RC));
274
275 /* Use software trigger to apply the new setting */
276 __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
277 regs + ATMEL_TC_REG(group, CCR));
278 tcbpwmc->bkup[group].enabled = 1;
279 spin_unlock(&tcbpwmc->lock);
280 return 0;
281}
282
283static int atmel_tcb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
284 int duty_ns, int period_ns)
285{
286 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
287 struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
288 unsigned group = pwm->hwpwm / 2;
289 unsigned index = pwm->hwpwm % 2;
290 struct atmel_tcb_pwm_device *atcbpwm = NULL;
291 struct atmel_tc *tc = tcbpwmc->tc;
292 int i;
293 int slowclk = 0;
294 unsigned period;
295 unsigned duty;
296 unsigned rate = clk_get_rate(tc->clk[group]);
297 unsigned long long min;
298 unsigned long long max;
299
300 /*
301 * Find best clk divisor:
302 * the smallest divisor which can fulfill the period_ns requirements.
303 */
304 for (i = 0; i < 5; ++i) {
305 if (atmel_tc_divisors[i] == 0) {
306 slowclk = i;
307 continue;
308 }
309 min = div_u64((u64)NSEC_PER_SEC * atmel_tc_divisors[i], rate);
310 max = min << tc->tcb_config->counter_width;
311 if (max >= period_ns)
312 break;
313 }
314
315 /*
316 * If none of the divisor are small enough to represent period_ns
317 * take slow clock (32KHz).
318 */
319 if (i == 5) {
320 i = slowclk;
321 rate = clk_get_rate(tc->slow_clk);
322 min = div_u64(NSEC_PER_SEC, rate);
323 max = min << tc->tcb_config->counter_width;
324
325 /* If period is too big return ERANGE error */
326 if (max < period_ns)
327 return -ERANGE;
328 }
329
330 duty = div_u64(duty_ns, min);
331 period = div_u64(period_ns, min);
332
333 if (index == 0)
334 atcbpwm = tcbpwmc->pwms[pwm->hwpwm + 1];
335 else
336 atcbpwm = tcbpwmc->pwms[pwm->hwpwm - 1];
337
338 /*
339 * PWM devices provided by TCB driver are grouped by 2:
340 * - group 0: PWM 0 & 1
341 * - group 1: PWM 2 & 3
342 * - group 2: PWM 4 & 5
343 *
344 * PWM devices in a given group must be configured with the
345 * same period_ns.
346 *
347 * We're checking the period value of the second PWM device
348 * in this group before applying the new config.
349 */
350 if ((atcbpwm && atcbpwm->duty > 0 &&
351 atcbpwm->duty != atcbpwm->period) &&
352 (atcbpwm->div != i || atcbpwm->period != period)) {
353 dev_err(chip->dev,
354 "failed to configure period_ns: PWM group already configured with a different value\n");
355 return -EINVAL;
356 }
357
358 tcbpwm->period = period;
359 tcbpwm->div = i;
360 tcbpwm->duty = duty;
361
362 /* If the PWM is enabled, call enable to apply the new conf */
363 if (pwm_is_enabled(pwm))
364 atmel_tcb_pwm_enable(chip, pwm);
365
366 return 0;
367}
368
369static const struct pwm_ops atmel_tcb_pwm_ops = {
370 .request = atmel_tcb_pwm_request,
371 .free = atmel_tcb_pwm_free,
372 .config = atmel_tcb_pwm_config,
373 .set_polarity = atmel_tcb_pwm_set_polarity,
374 .enable = atmel_tcb_pwm_enable,
375 .disable = atmel_tcb_pwm_disable,
376 .owner = THIS_MODULE,
377};
378
379static int atmel_tcb_pwm_probe(struct platform_device *pdev)
380{
381 struct atmel_tcb_pwm_chip *tcbpwm;
382 struct device_node *np = pdev->dev.of_node;
383 struct atmel_tc *tc;
384 int err;
385 int tcblock;
386
387 err = of_property_read_u32(np, "tc-block", &tcblock);
388 if (err < 0) {
389 dev_err(&pdev->dev,
390 "failed to get Timer Counter Block number from device tree (error: %d)\n",
391 err);
392 return err;
393 }
394
395 tc = atmel_tc_alloc(tcblock);
396 if (tc == NULL) {
397 dev_err(&pdev->dev, "failed to allocate Timer Counter Block\n");
398 return -ENOMEM;
399 }
400
401 tcbpwm = devm_kzalloc(&pdev->dev, sizeof(*tcbpwm), GFP_KERNEL);
402 if (tcbpwm == NULL) {
403 err = -ENOMEM;
404 goto err_free_tc;
405 }
406
407 tcbpwm->chip.dev = &pdev->dev;
408 tcbpwm->chip.ops = &atmel_tcb_pwm_ops;
409 tcbpwm->chip.of_xlate = of_pwm_xlate_with_flags;
410 tcbpwm->chip.of_pwm_n_cells = 3;
411 tcbpwm->chip.base = -1;
412 tcbpwm->chip.npwm = NPWM;
413 tcbpwm->tc = tc;
414
415 err = clk_prepare_enable(tc->slow_clk);
416 if (err)
417 goto err_free_tc;
418
419 spin_lock_init(&tcbpwm->lock);
420
421 err = pwmchip_add(&tcbpwm->chip);
422 if (err < 0)
423 goto err_disable_clk;
424
425 platform_set_drvdata(pdev, tcbpwm);
426
427 return 0;
428
429err_disable_clk:
430 clk_disable_unprepare(tcbpwm->tc->slow_clk);
431
432err_free_tc:
433 atmel_tc_free(tc);
434
435 return err;
436}
437
438static int atmel_tcb_pwm_remove(struct platform_device *pdev)
439{
440 struct atmel_tcb_pwm_chip *tcbpwm = platform_get_drvdata(pdev);
441 int err;
442
443 clk_disable_unprepare(tcbpwm->tc->slow_clk);
444
445 err = pwmchip_remove(&tcbpwm->chip);
446 if (err < 0)
447 return err;
448
449 atmel_tc_free(tcbpwm->tc);
450
451 return 0;
452}
453
454static const struct of_device_id atmel_tcb_pwm_dt_ids[] = {
455 { .compatible = "atmel,tcb-pwm", },
456 { /* sentinel */ }
457};
458MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids);
459
460#ifdef CONFIG_PM_SLEEP
461static int atmel_tcb_pwm_suspend(struct device *dev)
462{
463 struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
464 void __iomem *base = tcbpwm->tc->regs;
465 int i;
466
467 for (i = 0; i < (NPWM / 2); i++) {
468 struct atmel_tcb_channel *chan = &tcbpwm->bkup[i];
469
470 chan->cmr = readl(base + ATMEL_TC_REG(i, CMR));
471 chan->ra = readl(base + ATMEL_TC_REG(i, RA));
472 chan->rb = readl(base + ATMEL_TC_REG(i, RB));
473 chan->rc = readl(base + ATMEL_TC_REG(i, RC));
474 }
475 return 0;
476}
477
478static int atmel_tcb_pwm_resume(struct device *dev)
479{
480 struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
481 void __iomem *base = tcbpwm->tc->regs;
482 int i;
483
484 for (i = 0; i < (NPWM / 2); i++) {
485 struct atmel_tcb_channel *chan = &tcbpwm->bkup[i];
486
487 writel(chan->cmr, base + ATMEL_TC_REG(i, CMR));
488 writel(chan->ra, base + ATMEL_TC_REG(i, RA));
489 writel(chan->rb, base + ATMEL_TC_REG(i, RB));
490 writel(chan->rc, base + ATMEL_TC_REG(i, RC));
491 if (chan->enabled) {
492 writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
493 base + ATMEL_TC_REG(i, CCR));
494 }
495 }
496 return 0;
497}
498#endif
499
500static SIMPLE_DEV_PM_OPS(atmel_tcb_pwm_pm_ops, atmel_tcb_pwm_suspend,
501 atmel_tcb_pwm_resume);
502
503static struct platform_driver atmel_tcb_pwm_driver = {
504 .driver = {
505 .name = "atmel-tcb-pwm",
506 .of_match_table = atmel_tcb_pwm_dt_ids,
507 .pm = &atmel_tcb_pwm_pm_ops,
508 },
509 .probe = atmel_tcb_pwm_probe,
510 .remove = atmel_tcb_pwm_remove,
511};
512module_platform_driver(atmel_tcb_pwm_driver);
513
514MODULE_AUTHOR("Boris BREZILLON <b.brezillon@overkiz.com>");
515MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver");
516MODULE_LICENSE("GPL v2");