1// SPDX-License-Identifier: GPL-2.0
   2/* Copyright(c) 1999 - 2018 Intel Corporation. */
   3
   4/* 82571EB Gigabit Ethernet Controller
   5 * 82571EB Gigabit Ethernet Controller (Copper)
   6 * 82571EB Gigabit Ethernet Controller (Fiber)
   7 * 82571EB Dual Port Gigabit Mezzanine Adapter
   8 * 82571EB Quad Port Gigabit Mezzanine Adapter
   9 * 82571PT Gigabit PT Quad Port Server ExpressModule
  10 * 82572EI Gigabit Ethernet Controller (Copper)
  11 * 82572EI Gigabit Ethernet Controller (Fiber)
  12 * 82572EI Gigabit Ethernet Controller
  13 * 82573V Gigabit Ethernet Controller (Copper)
  14 * 82573E Gigabit Ethernet Controller (Copper)
  15 * 82573L Gigabit Ethernet Controller
  16 * 82574L Gigabit Network Connection
  17 * 82583V Gigabit Network Connection
  18 */
  19
  20#include "e1000.h"
  21
  22static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
  23static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
  24static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  25static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  26static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  27				      u16 words, u16 *data);
  28static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  29static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  30static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  31static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  32static s32 e1000_led_on_82574(struct e1000_hw *hw);
  33static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
  34static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
  35static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
  36static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
  37static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
  38static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active);
  39static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active);
  40
  41/**
  42 *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  43 *  @hw: pointer to the HW structure
  44 **/
  45static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  46{
  47	struct e1000_phy_info *phy = &hw->phy;
  48	s32 ret_val;
  49
  50	if (hw->phy.media_type != e1000_media_type_copper) {
  51		phy->type = e1000_phy_none;
  52		return 0;
  53	}
  54
  55	phy->addr = 1;
  56	phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  57	phy->reset_delay_us = 100;
  58
  59	phy->ops.power_up = e1000_power_up_phy_copper;
  60	phy->ops.power_down = e1000_power_down_phy_copper_82571;
  61
  62	switch (hw->mac.type) {
  63	case e1000_82571:
  64	case e1000_82572:
  65		phy->type = e1000_phy_igp_2;
  66		break;
  67	case e1000_82573:
  68		phy->type = e1000_phy_m88;
  69		break;
  70	case e1000_82574:
  71	case e1000_82583:
  72		phy->type = e1000_phy_bm;
  73		phy->ops.acquire = e1000_get_hw_semaphore_82574;
  74		phy->ops.release = e1000_put_hw_semaphore_82574;
  75		phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
  76		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
  77		break;
  78	default:
  79		return -E1000_ERR_PHY;
  80	}
  81
  82	/* This can only be done after all function pointers are setup. */
  83	ret_val = e1000_get_phy_id_82571(hw);
  84	if (ret_val) {
  85		e_dbg("Error getting PHY ID\n");
  86		return ret_val;
  87	}
  88
  89	/* Verify phy id */
  90	switch (hw->mac.type) {
  91	case e1000_82571:
  92	case e1000_82572:
  93		if (phy->id != IGP01E1000_I_PHY_ID)
  94			ret_val = -E1000_ERR_PHY;
  95		break;
  96	case e1000_82573:
  97		if (phy->id != M88E1111_I_PHY_ID)
  98			ret_val = -E1000_ERR_PHY;
  99		break;
 100	case e1000_82574:
 101	case e1000_82583:
 102		if (phy->id != BME1000_E_PHY_ID_R2)
 103			ret_val = -E1000_ERR_PHY;
 104		break;
 105	default:
 106		ret_val = -E1000_ERR_PHY;
 107		break;
 108	}
 109
 110	if (ret_val)
 111		e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
 112
 113	return ret_val;
 114}
 115
 116/**
 117 *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 118 *  @hw: pointer to the HW structure
 119 **/
 120static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 121{
 122	struct e1000_nvm_info *nvm = &hw->nvm;
 123	u32 eecd = er32(EECD);
 124	u16 size;
 125
 126	nvm->opcode_bits = 8;
 127	nvm->delay_usec = 1;
 128	switch (nvm->override) {
 129	case e1000_nvm_override_spi_large:
 130		nvm->page_size = 32;
 131		nvm->address_bits = 16;
 132		break;
 133	case e1000_nvm_override_spi_small:
 134		nvm->page_size = 8;
 135		nvm->address_bits = 8;
 136		break;
 137	default:
 138		nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 139		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 140		break;
 141	}
 142
 143	switch (hw->mac.type) {
 144	case e1000_82573:
 145	case e1000_82574:
 146	case e1000_82583:
 147		if (((eecd >> 15) & 0x3) == 0x3) {
 148			nvm->type = e1000_nvm_flash_hw;
 149			nvm->word_size = 2048;
 150			/* Autonomous Flash update bit must be cleared due
 151			 * to Flash update issue.
 152			 */
 153			eecd &= ~E1000_EECD_AUPDEN;
 154			ew32(EECD, eecd);
 155			break;
 156		}
 157		fallthrough;
 158	default:
 159		nvm->type = e1000_nvm_eeprom_spi;
 160		size = (u16)FIELD_GET(E1000_EECD_SIZE_EX_MASK, eecd);
 
 161		/* Added to a constant, "size" becomes the left-shift value
 162		 * for setting word_size.
 163		 */
 164		size += NVM_WORD_SIZE_BASE_SHIFT;
 165
 166		/* EEPROM access above 16k is unsupported */
 167		if (size > 14)
 168			size = 14;
 169		nvm->word_size = BIT(size);
 170		break;
 171	}
 172
 173	/* Function Pointers */
 174	switch (hw->mac.type) {
 175	case e1000_82574:
 176	case e1000_82583:
 177		nvm->ops.acquire = e1000_get_hw_semaphore_82574;
 178		nvm->ops.release = e1000_put_hw_semaphore_82574;
 179		break;
 180	default:
 181		break;
 182	}
 183
 184	return 0;
 185}
 186
 187/**
 188 *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 189 *  @hw: pointer to the HW structure
 190 **/
 191static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 192{
 193	struct e1000_mac_info *mac = &hw->mac;
 194	u32 swsm = 0;
 195	u32 swsm2 = 0;
 196	bool force_clear_smbi = false;
 197
 198	/* Set media type and media-dependent function pointers */
 199	switch (hw->adapter->pdev->device) {
 200	case E1000_DEV_ID_82571EB_FIBER:
 201	case E1000_DEV_ID_82572EI_FIBER:
 202	case E1000_DEV_ID_82571EB_QUAD_FIBER:
 203		hw->phy.media_type = e1000_media_type_fiber;
 204		mac->ops.setup_physical_interface =
 205		    e1000_setup_fiber_serdes_link_82571;
 206		mac->ops.check_for_link = e1000e_check_for_fiber_link;
 207		mac->ops.get_link_up_info =
 208		    e1000e_get_speed_and_duplex_fiber_serdes;
 209		break;
 210	case E1000_DEV_ID_82571EB_SERDES:
 211	case E1000_DEV_ID_82571EB_SERDES_DUAL:
 212	case E1000_DEV_ID_82571EB_SERDES_QUAD:
 213	case E1000_DEV_ID_82572EI_SERDES:
 214		hw->phy.media_type = e1000_media_type_internal_serdes;
 215		mac->ops.setup_physical_interface =
 216		    e1000_setup_fiber_serdes_link_82571;
 217		mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
 218		mac->ops.get_link_up_info =
 219		    e1000e_get_speed_and_duplex_fiber_serdes;
 220		break;
 221	default:
 222		hw->phy.media_type = e1000_media_type_copper;
 223		mac->ops.setup_physical_interface =
 224		    e1000_setup_copper_link_82571;
 225		mac->ops.check_for_link = e1000e_check_for_copper_link;
 226		mac->ops.get_link_up_info = e1000e_get_speed_and_duplex_copper;
 227		break;
 228	}
 229
 230	/* Set mta register count */
 231	mac->mta_reg_count = 128;
 232	/* Set rar entry count */
 233	mac->rar_entry_count = E1000_RAR_ENTRIES;
 234	/* Adaptive IFS supported */
 235	mac->adaptive_ifs = true;
 236
 237	/* MAC-specific function pointers */
 238	switch (hw->mac.type) {
 239	case e1000_82573:
 240		mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 241		mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
 242		mac->ops.led_on = e1000e_led_on_generic;
 243		mac->ops.blink_led = e1000e_blink_led_generic;
 244
 245		/* FWSM register */
 246		mac->has_fwsm = true;
 247		/* ARC supported; valid only if manageability features are
 248		 * enabled.
 249		 */
 250		mac->arc_subsystem_valid = !!(er32(FWSM) &
 251					      E1000_FWSM_MODE_MASK);
 252		break;
 253	case e1000_82574:
 254	case e1000_82583:
 255		mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 256		mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
 257		mac->ops.led_on = e1000_led_on_82574;
 258		break;
 259	default:
 260		mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
 261		mac->ops.led_on = e1000e_led_on_generic;
 262		mac->ops.blink_led = e1000e_blink_led_generic;
 263
 264		/* FWSM register */
 265		mac->has_fwsm = true;
 266		break;
 267	}
 268
 269	/* Ensure that the inter-port SWSM.SMBI lock bit is clear before
 270	 * first NVM or PHY access. This should be done for single-port
 271	 * devices, and for one port only on dual-port devices so that
 272	 * for those devices we can still use the SMBI lock to synchronize
 273	 * inter-port accesses to the PHY & NVM.
 274	 */
 275	switch (hw->mac.type) {
 276	case e1000_82571:
 277	case e1000_82572:
 278		swsm2 = er32(SWSM2);
 279
 280		if (!(swsm2 & E1000_SWSM2_LOCK)) {
 281			/* Only do this for the first interface on this card */
 282			ew32(SWSM2, swsm2 | E1000_SWSM2_LOCK);
 283			force_clear_smbi = true;
 284		} else {
 285			force_clear_smbi = false;
 286		}
 287		break;
 288	default:
 289		force_clear_smbi = true;
 290		break;
 291	}
 292
 293	if (force_clear_smbi) {
 294		/* Make sure SWSM.SMBI is clear */
 295		swsm = er32(SWSM);
 296		if (swsm & E1000_SWSM_SMBI) {
 297			/* This bit should not be set on a first interface, and
 298			 * indicates that the bootagent or EFI code has
 299			 * improperly left this bit enabled
 300			 */
 301			e_dbg("Please update your 82571 Bootagent\n");
 302		}
 303		ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
 304	}
 305
 306	/* Initialize device specific counter of SMBI acquisition timeouts. */
 307	hw->dev_spec.e82571.smb_counter = 0;
 308
 309	return 0;
 310}
 311
 312static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
 313{
 314	struct e1000_hw *hw = &adapter->hw;
 315	static int global_quad_port_a;	/* global port a indication */
 316	struct pci_dev *pdev = adapter->pdev;
 317	int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
 318	s32 rc;
 319
 320	rc = e1000_init_mac_params_82571(hw);
 321	if (rc)
 322		return rc;
 323
 324	rc = e1000_init_nvm_params_82571(hw);
 325	if (rc)
 326		return rc;
 327
 328	rc = e1000_init_phy_params_82571(hw);
 329	if (rc)
 330		return rc;
 331
 332	/* tag quad port adapters first, it's used below */
 333	switch (pdev->device) {
 334	case E1000_DEV_ID_82571EB_QUAD_COPPER:
 335	case E1000_DEV_ID_82571EB_QUAD_FIBER:
 336	case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
 337	case E1000_DEV_ID_82571PT_QUAD_COPPER:
 338		adapter->flags |= FLAG_IS_QUAD_PORT;
 339		/* mark the first port */
 340		if (global_quad_port_a == 0)
 341			adapter->flags |= FLAG_IS_QUAD_PORT_A;
 342		/* Reset for multiple quad port adapters */
 343		global_quad_port_a++;
 344		if (global_quad_port_a == 4)
 345			global_quad_port_a = 0;
 346		break;
 347	default:
 348		break;
 349	}
 350
 351	switch (adapter->hw.mac.type) {
 352	case e1000_82571:
 353		/* these dual ports don't have WoL on port B at all */
 354		if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
 355		     (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
 356		     (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
 357		    (is_port_b))
 358			adapter->flags &= ~FLAG_HAS_WOL;
 359		/* quad ports only support WoL on port A */
 360		if (adapter->flags & FLAG_IS_QUAD_PORT &&
 361		    (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
 362			adapter->flags &= ~FLAG_HAS_WOL;
 363		/* Does not support WoL on any port */
 364		if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
 365			adapter->flags &= ~FLAG_HAS_WOL;
 366		break;
 367	case e1000_82573:
 368		if (pdev->device == E1000_DEV_ID_82573L) {
 369			adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
 370			adapter->max_hw_frame_size = DEFAULT_JUMBO;
 371		}
 372		break;
 373	default:
 374		break;
 375	}
 376
 377	return 0;
 378}
 379
 380/**
 381 *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 382 *  @hw: pointer to the HW structure
 383 *
 384 *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 385 *  revision in the hardware structure.
 386 **/
 387static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 388{
 389	struct e1000_phy_info *phy = &hw->phy;
 390	s32 ret_val;
 391	u16 phy_id = 0;
 392
 393	switch (hw->mac.type) {
 394	case e1000_82571:
 395	case e1000_82572:
 396		/* The 82571 firmware may still be configuring the PHY.
 397		 * In this case, we cannot access the PHY until the
 398		 * configuration is done.  So we explicitly set the
 399		 * PHY ID.
 400		 */
 401		phy->id = IGP01E1000_I_PHY_ID;
 402		break;
 403	case e1000_82573:
 404		return e1000e_get_phy_id(hw);
 405	case e1000_82574:
 406	case e1000_82583:
 407		ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
 408		if (ret_val)
 409			return ret_val;
 410
 411		phy->id = (u32)(phy_id << 16);
 412		usleep_range(20, 40);
 413		ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
 414		if (ret_val)
 415			return ret_val;
 416
 417		phy->id |= (u32)(phy_id);
 418		phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 419		break;
 420	default:
 421		return -E1000_ERR_PHY;
 422	}
 423
 424	return 0;
 425}
 426
 427/**
 428 *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 429 *  @hw: pointer to the HW structure
 430 *
 431 *  Acquire the HW semaphore to access the PHY or NVM
 432 **/
 433static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 434{
 435	u32 swsm;
 436	s32 sw_timeout = hw->nvm.word_size + 1;
 437	s32 fw_timeout = hw->nvm.word_size + 1;
 438	s32 i = 0;
 439
 440	/* If we have timedout 3 times on trying to acquire
 441	 * the inter-port SMBI semaphore, there is old code
 442	 * operating on the other port, and it is not
 443	 * releasing SMBI. Modify the number of times that
 444	 * we try for the semaphore to interwork with this
 445	 * older code.
 446	 */
 447	if (hw->dev_spec.e82571.smb_counter > 2)
 448		sw_timeout = 1;
 449
 450	/* Get the SW semaphore */
 451	while (i < sw_timeout) {
 452		swsm = er32(SWSM);
 453		if (!(swsm & E1000_SWSM_SMBI))
 454			break;
 455
 456		usleep_range(50, 100);
 457		i++;
 458	}
 459
 460	if (i == sw_timeout) {
 461		e_dbg("Driver can't access device - SMBI bit is set.\n");
 462		hw->dev_spec.e82571.smb_counter++;
 463	}
 464	/* Get the FW semaphore. */
 465	for (i = 0; i < fw_timeout; i++) {
 466		swsm = er32(SWSM);
 467		ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
 468
 469		/* Semaphore acquired if bit latched */
 470		if (er32(SWSM) & E1000_SWSM_SWESMBI)
 471			break;
 472
 473		usleep_range(50, 100);
 474	}
 475
 476	if (i == fw_timeout) {
 477		/* Release semaphores */
 478		e1000_put_hw_semaphore_82571(hw);
 479		e_dbg("Driver can't access the NVM\n");
 480		return -E1000_ERR_NVM;
 481	}
 482
 483	return 0;
 484}
 485
 486/**
 487 *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 488 *  @hw: pointer to the HW structure
 489 *
 490 *  Release hardware semaphore used to access the PHY or NVM
 491 **/
 492static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 493{
 494	u32 swsm;
 495
 496	swsm = er32(SWSM);
 497	swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 498	ew32(SWSM, swsm);
 499}
 500
 501/**
 502 *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
 503 *  @hw: pointer to the HW structure
 504 *
 505 *  Acquire the HW semaphore during reset.
 506 *
 507 **/
 508static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
 509{
 510	u32 extcnf_ctrl;
 511	s32 i = 0;
 512
 513	extcnf_ctrl = er32(EXTCNF_CTRL);
 514	do {
 515		extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 516		ew32(EXTCNF_CTRL, extcnf_ctrl);
 517		extcnf_ctrl = er32(EXTCNF_CTRL);
 518
 519		if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 520			break;
 521
 522		usleep_range(2000, 4000);
 523		i++;
 524	} while (i < MDIO_OWNERSHIP_TIMEOUT);
 525
 526	if (i == MDIO_OWNERSHIP_TIMEOUT) {
 527		/* Release semaphores */
 528		e1000_put_hw_semaphore_82573(hw);
 529		e_dbg("Driver can't access the PHY\n");
 530		return -E1000_ERR_PHY;
 531	}
 532
 533	return 0;
 534}
 535
 536/**
 537 *  e1000_put_hw_semaphore_82573 - Release hardware semaphore
 538 *  @hw: pointer to the HW structure
 539 *
 540 *  Release hardware semaphore used during reset.
 541 *
 542 **/
 543static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
 544{
 545	u32 extcnf_ctrl;
 546
 547	extcnf_ctrl = er32(EXTCNF_CTRL);
 548	extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 549	ew32(EXTCNF_CTRL, extcnf_ctrl);
 550}
 551
 552static DEFINE_MUTEX(swflag_mutex);
 553
 554/**
 555 *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
 556 *  @hw: pointer to the HW structure
 557 *
 558 *  Acquire the HW semaphore to access the PHY or NVM.
 559 *
 560 **/
 561static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
 562{
 563	s32 ret_val;
 564
 565	mutex_lock(&swflag_mutex);
 566	ret_val = e1000_get_hw_semaphore_82573(hw);
 567	if (ret_val)
 568		mutex_unlock(&swflag_mutex);
 569	return ret_val;
 570}
 571
 572/**
 573 *  e1000_put_hw_semaphore_82574 - Release hardware semaphore
 574 *  @hw: pointer to the HW structure
 575 *
 576 *  Release hardware semaphore used to access the PHY or NVM
 577 *
 578 **/
 579static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
 580{
 581	e1000_put_hw_semaphore_82573(hw);
 582	mutex_unlock(&swflag_mutex);
 583}
 584
 585/**
 586 *  e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
 587 *  @hw: pointer to the HW structure
 588 *  @active: true to enable LPLU, false to disable
 589 *
 590 *  Sets the LPLU D0 state according to the active flag.
 591 *  LPLU will not be activated unless the
 592 *  device autonegotiation advertisement meets standards of
 593 *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 594 *  This is a function pointer entry point only called by
 595 *  PHY setup routines.
 596 **/
 597static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
 598{
 599	u32 data = er32(POEMB);
 600
 601	if (active)
 602		data |= E1000_PHY_CTRL_D0A_LPLU;
 603	else
 604		data &= ~E1000_PHY_CTRL_D0A_LPLU;
 605
 606	ew32(POEMB, data);
 607	return 0;
 608}
 609
 610/**
 611 *  e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
 612 *  @hw: pointer to the HW structure
 613 *  @active: boolean used to enable/disable lplu
 614 *
 615 *  The low power link up (lplu) state is set to the power management level D3
 616 *  when active is true, else clear lplu for D3. LPLU
 617 *  is used during Dx states where the power conservation is most important.
 618 *  During driver activity, SmartSpeed should be enabled so performance is
 619 *  maintained.
 620 **/
 621static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
 622{
 623	u32 data = er32(POEMB);
 624
 625	if (!active) {
 626		data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
 627	} else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 628		   (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
 629		   (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
 630		data |= E1000_PHY_CTRL_NOND0A_LPLU;
 631	}
 632
 633	ew32(POEMB, data);
 634	return 0;
 635}
 636
 637/**
 638 *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 639 *  @hw: pointer to the HW structure
 640 *
 641 *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 642 *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 643 *  for EEPROM access grant bit.  If the access grant bit is not set, release
 644 *  hardware semaphore.
 645 **/
 646static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 647{
 648	s32 ret_val;
 649
 650	ret_val = e1000_get_hw_semaphore_82571(hw);
 651	if (ret_val)
 652		return ret_val;
 653
 654	switch (hw->mac.type) {
 655	case e1000_82573:
 656		break;
 657	default:
 658		ret_val = e1000e_acquire_nvm(hw);
 659		break;
 660	}
 661
 662	if (ret_val)
 663		e1000_put_hw_semaphore_82571(hw);
 664
 665	return ret_val;
 666}
 667
 668/**
 669 *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 670 *  @hw: pointer to the HW structure
 671 *
 672 *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 673 **/
 674static void e1000_release_nvm_82571(struct e1000_hw *hw)
 675{
 676	e1000e_release_nvm(hw);
 677	e1000_put_hw_semaphore_82571(hw);
 678}
 679
 680/**
 681 *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 682 *  @hw: pointer to the HW structure
 683 *  @offset: offset within the EEPROM to be written to
 684 *  @words: number of words to write
 685 *  @data: 16 bit word(s) to be written to the EEPROM
 686 *
 687 *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 688 *
 689 *  If e1000e_update_nvm_checksum is not called after this function, the
 690 *  EEPROM will most likely contain an invalid checksum.
 691 **/
 692static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 693				 u16 *data)
 694{
 695	s32 ret_val;
 696
 697	switch (hw->mac.type) {
 698	case e1000_82573:
 699	case e1000_82574:
 700	case e1000_82583:
 701		ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 702		break;
 703	case e1000_82571:
 704	case e1000_82572:
 705		ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
 706		break;
 707	default:
 708		ret_val = -E1000_ERR_NVM;
 709		break;
 710	}
 711
 712	return ret_val;
 713}
 714
 715/**
 716 *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 717 *  @hw: pointer to the HW structure
 718 *
 719 *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 720 *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 721 *  value to the EEPROM.
 722 **/
 723static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 724{
 725	u32 eecd;
 726	s32 ret_val;
 727	u16 i;
 728
 729	ret_val = e1000e_update_nvm_checksum_generic(hw);
 730	if (ret_val)
 731		return ret_val;
 732
 733	/* If our nvm is an EEPROM, then we're done
 734	 * otherwise, commit the checksum to the flash NVM.
 735	 */
 736	if (hw->nvm.type != e1000_nvm_flash_hw)
 737		return 0;
 738
 739	/* Check for pending operations. */
 740	for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 741		usleep_range(1000, 2000);
 742		if (!(er32(EECD) & E1000_EECD_FLUPD))
 743			break;
 744	}
 745
 746	if (i == E1000_FLASH_UPDATES)
 747		return -E1000_ERR_NVM;
 748
 749	/* Reset the firmware if using STM opcode. */
 750	if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 751		/* The enabling of and the actual reset must be done
 752		 * in two write cycles.
 753		 */
 754		ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
 755		e1e_flush();
 756		ew32(HICR, E1000_HICR_FW_RESET);
 757	}
 758
 759	/* Commit the write to flash */
 760	eecd = er32(EECD) | E1000_EECD_FLUPD;
 761	ew32(EECD, eecd);
 762
 763	for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 764		usleep_range(1000, 2000);
 765		if (!(er32(EECD) & E1000_EECD_FLUPD))
 766			break;
 767	}
 768
 769	if (i == E1000_FLASH_UPDATES)
 770		return -E1000_ERR_NVM;
 771
 772	return 0;
 773}
 774
 775/**
 776 *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 777 *  @hw: pointer to the HW structure
 778 *
 779 *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 780 *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 781 **/
 782static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 783{
 784	if (hw->nvm.type == e1000_nvm_flash_hw)
 785		e1000_fix_nvm_checksum_82571(hw);
 786
 787	return e1000e_validate_nvm_checksum_generic(hw);
 788}
 789
 790/**
 791 *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 792 *  @hw: pointer to the HW structure
 793 *  @offset: offset within the EEPROM to be written to
 794 *  @words: number of words to write
 795 *  @data: 16 bit word(s) to be written to the EEPROM
 796 *
 797 *  After checking for invalid values, poll the EEPROM to ensure the previous
 798 *  command has completed before trying to write the next word.  After write
 799 *  poll for completion.
 800 *
 801 *  If e1000e_update_nvm_checksum is not called after this function, the
 802 *  EEPROM will most likely contain an invalid checksum.
 803 **/
 804static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 805				      u16 words, u16 *data)
 806{
 807	struct e1000_nvm_info *nvm = &hw->nvm;
 808	u32 i, eewr = 0;
 809	s32 ret_val = 0;
 810
 811	/* A check for invalid values:  offset too large, too many words,
 812	 * and not enough words.
 813	 */
 814	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 815	    (words == 0)) {
 816		e_dbg("nvm parameter(s) out of bounds\n");
 817		return -E1000_ERR_NVM;
 818	}
 819
 820	for (i = 0; i < words; i++) {
 821		eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
 822			((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
 823			E1000_NVM_RW_REG_START);
 824
 825		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 826		if (ret_val)
 827			break;
 828
 829		ew32(EEWR, eewr);
 830
 831		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 832		if (ret_val)
 833			break;
 834	}
 835
 836	return ret_val;
 837}
 838
 839/**
 840 *  e1000_get_cfg_done_82571 - Poll for configuration done
 841 *  @hw: pointer to the HW structure
 842 *
 843 *  Reads the management control register for the config done bit to be set.
 844 **/
 845static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 846{
 847	s32 timeout = PHY_CFG_TIMEOUT;
 848
 849	while (timeout) {
 850		if (er32(EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0)
 851			break;
 852		usleep_range(1000, 2000);
 853		timeout--;
 854	}
 855	if (!timeout) {
 856		e_dbg("MNG configuration cycle has not completed.\n");
 857		return -E1000_ERR_RESET;
 858	}
 859
 860	return 0;
 861}
 862
 863/**
 864 *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 865 *  @hw: pointer to the HW structure
 866 *  @active: true to enable LPLU, false to disable
 867 *
 868 *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 869 *  this function also disables smart speed and vice versa.  LPLU will not be
 870 *  activated unless the device autonegotiation advertisement meets standards
 871 *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 872 *  pointer entry point only called by PHY setup routines.
 873 **/
 874static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 875{
 876	struct e1000_phy_info *phy = &hw->phy;
 877	s32 ret_val;
 878	u16 data;
 879
 880	ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 881	if (ret_val)
 882		return ret_val;
 883
 884	if (active) {
 885		data |= IGP02E1000_PM_D0_LPLU;
 886		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 887		if (ret_val)
 888			return ret_val;
 889
 890		/* When LPLU is enabled, we should disable SmartSpeed */
 891		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 892		if (ret_val)
 893			return ret_val;
 894		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 895		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 896		if (ret_val)
 897			return ret_val;
 898	} else {
 899		data &= ~IGP02E1000_PM_D0_LPLU;
 900		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 901		if (ret_val)
 902			return ret_val;
 903		/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 904		 * during Dx states where the power conservation is most
 905		 * important.  During driver activity we should enable
 906		 * SmartSpeed, so performance is maintained.
 907		 */
 908		if (phy->smart_speed == e1000_smart_speed_on) {
 909			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 910					   &data);
 911			if (ret_val)
 912				return ret_val;
 913
 914			data |= IGP01E1000_PSCFR_SMART_SPEED;
 915			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 916					   data);
 917			if (ret_val)
 918				return ret_val;
 919		} else if (phy->smart_speed == e1000_smart_speed_off) {
 920			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 921					   &data);
 922			if (ret_val)
 923				return ret_val;
 924
 925			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 926			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 927					   data);
 928			if (ret_val)
 929				return ret_val;
 930		}
 931	}
 932
 933	return 0;
 934}
 935
 936/**
 937 *  e1000_reset_hw_82571 - Reset hardware
 938 *  @hw: pointer to the HW structure
 939 *
 940 *  This resets the hardware into a known state.
 941 **/
 942static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
 943{
 944	u32 ctrl, ctrl_ext, eecd, tctl;
 945	s32 ret_val;
 946
 947	/* Prevent the PCI-E bus from sticking if there is no TLP connection
 948	 * on the last TLP read/write transaction when MAC is reset.
 949	 */
 950	ret_val = e1000e_disable_pcie_master(hw);
 951	if (ret_val)
 952		e_dbg("PCI-E Master disable polling has failed.\n");
 953
 954	e_dbg("Masking off all interrupts\n");
 955	ew32(IMC, 0xffffffff);
 956
 957	ew32(RCTL, 0);
 958	tctl = er32(TCTL);
 959	tctl &= ~E1000_TCTL_EN;
 960	ew32(TCTL, tctl);
 961	e1e_flush();
 962
 963	usleep_range(10000, 11000);
 964
 965	/* Must acquire the MDIO ownership before MAC reset.
 966	 * Ownership defaults to firmware after a reset.
 967	 */
 968	switch (hw->mac.type) {
 969	case e1000_82573:
 970		ret_val = e1000_get_hw_semaphore_82573(hw);
 971		break;
 972	case e1000_82574:
 973	case e1000_82583:
 974		ret_val = e1000_get_hw_semaphore_82574(hw);
 975		break;
 976	default:
 977		break;
 978	}
 979
 980	ctrl = er32(CTRL);
 981
 982	e_dbg("Issuing a global reset to MAC\n");
 983	ew32(CTRL, ctrl | E1000_CTRL_RST);
 984
 985	/* Must release MDIO ownership and mutex after MAC reset. */
 986	switch (hw->mac.type) {
 987	case e1000_82573:
 988		/* Release mutex only if the hw semaphore is acquired */
 989		if (!ret_val)
 990			e1000_put_hw_semaphore_82573(hw);
 991		break;
 992	case e1000_82574:
 993	case e1000_82583:
 994		/* Release mutex only if the hw semaphore is acquired */
 995		if (!ret_val)
 996			e1000_put_hw_semaphore_82574(hw);
 997		break;
 998	default:
 999		break;
1000	}
1001
1002	if (hw->nvm.type == e1000_nvm_flash_hw) {
1003		usleep_range(10, 20);
1004		ctrl_ext = er32(CTRL_EXT);
1005		ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1006		ew32(CTRL_EXT, ctrl_ext);
1007		e1e_flush();
1008	}
1009
1010	ret_val = e1000e_get_auto_rd_done(hw);
1011	if (ret_val)
1012		/* We don't want to continue accessing MAC registers. */
1013		return ret_val;
1014
1015	/* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1016	 * Need to wait for Phy configuration completion before accessing
1017	 * NVM and Phy.
1018	 */
1019
1020	switch (hw->mac.type) {
1021	case e1000_82571:
1022	case e1000_82572:
1023		/* REQ and GNT bits need to be cleared when using AUTO_RD
1024		 * to access the EEPROM.
1025		 */
1026		eecd = er32(EECD);
1027		eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1028		ew32(EECD, eecd);
1029		break;
1030	case e1000_82573:
1031	case e1000_82574:
1032	case e1000_82583:
1033		msleep(25);
1034		break;
1035	default:
1036		break;
1037	}
1038
1039	/* Clear any pending interrupt events. */
1040	ew32(IMC, 0xffffffff);
1041	er32(ICR);
1042
1043	if (hw->mac.type == e1000_82571) {
1044		/* Install any alternate MAC address into RAR0 */
1045		ret_val = e1000_check_alt_mac_addr_generic(hw);
1046		if (ret_val)
1047			return ret_val;
1048
1049		e1000e_set_laa_state_82571(hw, true);
1050	}
1051
1052	/* Reinitialize the 82571 serdes link state machine */
1053	if (hw->phy.media_type == e1000_media_type_internal_serdes)
1054		hw->mac.serdes_link_state = e1000_serdes_link_down;
1055
1056	return 0;
1057}
1058
1059/**
1060 *  e1000_init_hw_82571 - Initialize hardware
1061 *  @hw: pointer to the HW structure
1062 *
1063 *  This inits the hardware readying it for operation.
1064 **/
1065static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1066{
1067	struct e1000_mac_info *mac = &hw->mac;
1068	u32 reg_data;
1069	s32 ret_val;
1070	u16 i, rar_count = mac->rar_entry_count;
1071
1072	e1000_initialize_hw_bits_82571(hw);
1073
1074	/* Initialize identification LED */
1075	ret_val = mac->ops.id_led_init(hw);
1076	/* An error is not fatal and we should not stop init due to this */
1077	if (ret_val)
1078		e_dbg("Error initializing identification LED\n");
1079
1080	/* Disabling VLAN filtering */
1081	e_dbg("Initializing the IEEE VLAN\n");
1082	mac->ops.clear_vfta(hw);
1083
1084	/* Setup the receive address.
1085	 * If, however, a locally administered address was assigned to the
1086	 * 82571, we must reserve a RAR for it to work around an issue where
1087	 * resetting one port will reload the MAC on the other port.
1088	 */
1089	if (e1000e_get_laa_state_82571(hw))
1090		rar_count--;
1091	e1000e_init_rx_addrs(hw, rar_count);
1092
1093	/* Zero out the Multicast HASH table */
1094	e_dbg("Zeroing the MTA\n");
1095	for (i = 0; i < mac->mta_reg_count; i++)
1096		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1097
1098	/* Setup link and flow control */
1099	ret_val = mac->ops.setup_link(hw);
1100
1101	/* Set the transmit descriptor write-back policy */
1102	reg_data = er32(TXDCTL(0));
1103	reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1104		    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
1105	ew32(TXDCTL(0), reg_data);
1106
1107	/* ...for both queues. */
1108	switch (mac->type) {
1109	case e1000_82573:
1110		e1000e_enable_tx_pkt_filtering(hw);
1111		fallthrough;
1112	case e1000_82574:
1113	case e1000_82583:
1114		reg_data = er32(GCR);
1115		reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1116		ew32(GCR, reg_data);
1117		break;
1118	default:
1119		reg_data = er32(TXDCTL(1));
1120		reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1121			    E1000_TXDCTL_FULL_TX_DESC_WB |
1122			    E1000_TXDCTL_COUNT_DESC);
1123		ew32(TXDCTL(1), reg_data);
1124		break;
1125	}
1126
1127	/* Clear all of the statistics registers (clear on read).  It is
1128	 * important that we do this after we have tried to establish link
1129	 * because the symbol error count will increment wildly if there
1130	 * is no link.
1131	 */
1132	e1000_clear_hw_cntrs_82571(hw);
1133
1134	return ret_val;
1135}
1136
1137/**
1138 *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1139 *  @hw: pointer to the HW structure
1140 *
1141 *  Initializes required hardware-dependent bits needed for normal operation.
1142 **/
1143static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1144{
1145	u32 reg;
1146
1147	/* Transmit Descriptor Control 0 */
1148	reg = er32(TXDCTL(0));
1149	reg |= BIT(22);
1150	ew32(TXDCTL(0), reg);
1151
1152	/* Transmit Descriptor Control 1 */
1153	reg = er32(TXDCTL(1));
1154	reg |= BIT(22);
1155	ew32(TXDCTL(1), reg);
1156
1157	/* Transmit Arbitration Control 0 */
1158	reg = er32(TARC(0));
1159	reg &= ~(0xF << 27);	/* 30:27 */
1160	switch (hw->mac.type) {
1161	case e1000_82571:
1162	case e1000_82572:
1163		reg |= BIT(23) | BIT(24) | BIT(25) | BIT(26);
1164		break;
1165	case e1000_82574:
1166	case e1000_82583:
1167		reg |= BIT(26);
1168		break;
1169	default:
1170		break;
1171	}
1172	ew32(TARC(0), reg);
1173
1174	/* Transmit Arbitration Control 1 */
1175	reg = er32(TARC(1));
1176	switch (hw->mac.type) {
1177	case e1000_82571:
1178	case e1000_82572:
1179		reg &= ~(BIT(29) | BIT(30));
1180		reg |= BIT(22) | BIT(24) | BIT(25) | BIT(26);
1181		if (er32(TCTL) & E1000_TCTL_MULR)
1182			reg &= ~BIT(28);
1183		else
1184			reg |= BIT(28);
1185		ew32(TARC(1), reg);
1186		break;
1187	default:
1188		break;
1189	}
1190
1191	/* Device Control */
1192	switch (hw->mac.type) {
1193	case e1000_82573:
1194	case e1000_82574:
1195	case e1000_82583:
1196		reg = er32(CTRL);
1197		reg &= ~BIT(29);
1198		ew32(CTRL, reg);
1199		break;
1200	default:
1201		break;
1202	}
1203
1204	/* Extended Device Control */
1205	switch (hw->mac.type) {
1206	case e1000_82573:
1207	case e1000_82574:
1208	case e1000_82583:
1209		reg = er32(CTRL_EXT);
1210		reg &= ~BIT(23);
1211		reg |= BIT(22);
1212		ew32(CTRL_EXT, reg);
1213		break;
1214	default:
1215		break;
1216	}
1217
1218	if (hw->mac.type == e1000_82571) {
1219		reg = er32(PBA_ECC);
1220		reg |= E1000_PBA_ECC_CORR_EN;
1221		ew32(PBA_ECC, reg);
1222	}
1223
1224	/* Workaround for hardware errata.
1225	 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1226	 */
1227	if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) {
1228		reg = er32(CTRL_EXT);
1229		reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1230		ew32(CTRL_EXT, reg);
1231	}
1232
1233	/* Disable IPv6 extension header parsing because some malformed
1234	 * IPv6 headers can hang the Rx.
1235	 */
1236	if (hw->mac.type <= e1000_82573) {
1237		reg = er32(RFCTL);
1238		reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1239		ew32(RFCTL, reg);
1240	}
1241
1242	/* PCI-Ex Control Registers */
1243	switch (hw->mac.type) {
1244	case e1000_82574:
1245	case e1000_82583:
1246		reg = er32(GCR);
1247		reg |= BIT(22);
1248		ew32(GCR, reg);
1249
1250		/* Workaround for hardware errata.
1251		 * apply workaround for hardware errata documented in errata
1252		 * docs Fixes issue where some error prone or unreliable PCIe
1253		 * completions are occurring, particularly with ASPM enabled.
1254		 * Without fix, issue can cause Tx timeouts.
1255		 */
1256		reg = er32(GCR2);
1257		reg |= 1;
1258		ew32(GCR2, reg);
1259		break;
1260	default:
1261		break;
1262	}
1263}
1264
1265/**
1266 *  e1000_clear_vfta_82571 - Clear VLAN filter table
1267 *  @hw: pointer to the HW structure
1268 *
1269 *  Clears the register array which contains the VLAN filter table by
1270 *  setting all the values to 0.
1271 **/
1272static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1273{
1274	u32 offset;
1275	u32 vfta_value = 0;
1276	u32 vfta_offset = 0;
1277	u32 vfta_bit_in_reg = 0;
1278
1279	switch (hw->mac.type) {
1280	case e1000_82573:
1281	case e1000_82574:
1282	case e1000_82583:
1283		if (hw->mng_cookie.vlan_id != 0) {
1284			/* The VFTA is a 4096b bit-field, each identifying
1285			 * a single VLAN ID.  The following operations
1286			 * determine which 32b entry (i.e. offset) into the
1287			 * array we want to set the VLAN ID (i.e. bit) of
1288			 * the manageability unit.
1289			 */
1290			vfta_offset = (hw->mng_cookie.vlan_id >>
1291				       E1000_VFTA_ENTRY_SHIFT) &
1292			    E1000_VFTA_ENTRY_MASK;
1293			vfta_bit_in_reg =
1294			    BIT(hw->mng_cookie.vlan_id &
1295				E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1296		}
1297		break;
1298	default:
1299		break;
1300	}
1301	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1302		/* If the offset we want to clear is the same offset of the
1303		 * manageability VLAN ID, then clear all bits except that of
1304		 * the manageability unit.
1305		 */
1306		vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1307		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1308		e1e_flush();
1309	}
1310}
1311
1312/**
1313 *  e1000_check_mng_mode_82574 - Check manageability is enabled
1314 *  @hw: pointer to the HW structure
1315 *
1316 *  Reads the NVM Initialization Control Word 2 and returns true
1317 *  (>0) if any manageability is enabled, else false (0).
1318 **/
1319static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1320{
1321	u16 data;
1322
1323	e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1324	return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1325}
1326
1327/**
1328 *  e1000_led_on_82574 - Turn LED on
1329 *  @hw: pointer to the HW structure
1330 *
1331 *  Turn LED on.
1332 **/
1333static s32 e1000_led_on_82574(struct e1000_hw *hw)
1334{
1335	u32 ctrl;
1336	u32 i;
1337
1338	ctrl = hw->mac.ledctl_mode2;
1339	if (!(E1000_STATUS_LU & er32(STATUS))) {
1340		/* If no link, then turn LED on by setting the invert bit
1341		 * for each LED that's "on" (0x0E) in ledctl_mode2.
1342		 */
1343		for (i = 0; i < 4; i++)
1344			if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1345			    E1000_LEDCTL_MODE_LED_ON)
1346				ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1347	}
1348	ew32(LEDCTL, ctrl);
1349
1350	return 0;
1351}
1352
1353/**
1354 *  e1000_check_phy_82574 - check 82574 phy hung state
1355 *  @hw: pointer to the HW structure
1356 *
1357 *  Returns whether phy is hung or not
1358 **/
1359bool e1000_check_phy_82574(struct e1000_hw *hw)
1360{
1361	u16 status_1kbt = 0;
1362	u16 receive_errors = 0;
1363	s32 ret_val;
1364
1365	/* Read PHY Receive Error counter first, if its is max - all F's then
1366	 * read the Base1000T status register If both are max then PHY is hung.
1367	 */
1368	ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors);
1369	if (ret_val)
1370		return false;
1371	if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1372		ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt);
1373		if (ret_val)
1374			return false;
1375		if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1376		    E1000_IDLE_ERROR_COUNT_MASK)
1377			return true;
1378	}
1379
1380	return false;
1381}
1382
1383/**
1384 *  e1000_setup_link_82571 - Setup flow control and link settings
1385 *  @hw: pointer to the HW structure
1386 *
1387 *  Determines which flow control settings to use, then configures flow
1388 *  control.  Calls the appropriate media-specific link configuration
1389 *  function.  Assuming the adapter has a valid link partner, a valid link
1390 *  should be established.  Assumes the hardware has previously been reset
1391 *  and the transmitter and receiver are not enabled.
1392 **/
1393static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1394{
1395	/* 82573 does not have a word in the NVM to determine
1396	 * the default flow control setting, so we explicitly
1397	 * set it to full.
1398	 */
1399	switch (hw->mac.type) {
1400	case e1000_82573:
1401	case e1000_82574:
1402	case e1000_82583:
1403		if (hw->fc.requested_mode == e1000_fc_default)
1404			hw->fc.requested_mode = e1000_fc_full;
1405		break;
1406	default:
1407		break;
1408	}
1409
1410	return e1000e_setup_link_generic(hw);
1411}
1412
1413/**
1414 *  e1000_setup_copper_link_82571 - Configure copper link settings
1415 *  @hw: pointer to the HW structure
1416 *
1417 *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1418 *  for link, once link is established calls to configure collision distance
1419 *  and flow control are called.
1420 **/
1421static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1422{
1423	u32 ctrl;
1424	s32 ret_val;
1425
1426	ctrl = er32(CTRL);
1427	ctrl |= E1000_CTRL_SLU;
1428	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1429	ew32(CTRL, ctrl);
1430
1431	switch (hw->phy.type) {
1432	case e1000_phy_m88:
1433	case e1000_phy_bm:
1434		ret_val = e1000e_copper_link_setup_m88(hw);
1435		break;
1436	case e1000_phy_igp_2:
1437		ret_val = e1000e_copper_link_setup_igp(hw);
1438		break;
1439	default:
1440		return -E1000_ERR_PHY;
1441	}
1442
1443	if (ret_val)
1444		return ret_val;
1445
1446	return e1000e_setup_copper_link(hw);
1447}
1448
1449/**
1450 *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1451 *  @hw: pointer to the HW structure
1452 *
1453 *  Configures collision distance and flow control for fiber and serdes links.
1454 *  Upon successful setup, poll for link.
1455 **/
1456static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1457{
1458	switch (hw->mac.type) {
1459	case e1000_82571:
1460	case e1000_82572:
1461		/* If SerDes loopback mode is entered, there is no form
1462		 * of reset to take the adapter out of that mode.  So we
1463		 * have to explicitly take the adapter out of loopback
1464		 * mode.  This prevents drivers from twiddling their thumbs
1465		 * if another tool failed to take it out of loopback mode.
1466		 */
1467		ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1468		break;
1469	default:
1470		break;
1471	}
1472
1473	return e1000e_setup_fiber_serdes_link(hw);
1474}
1475
1476/**
1477 *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1478 *  @hw: pointer to the HW structure
1479 *
1480 *  Reports the link state as up or down.
1481 *
1482 *  If autonegotiation is supported by the link partner, the link state is
1483 *  determined by the result of autonegotiation. This is the most likely case.
1484 *  If autonegotiation is not supported by the link partner, and the link
1485 *  has a valid signal, force the link up.
1486 *
1487 *  The link state is represented internally here by 4 states:
1488 *
1489 *  1) down
1490 *  2) autoneg_progress
1491 *  3) autoneg_complete (the link successfully autonegotiated)
1492 *  4) forced_up (the link has been forced up, it did not autonegotiate)
1493 *
1494 **/
1495static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1496{
1497	struct e1000_mac_info *mac = &hw->mac;
1498	u32 rxcw;
1499	u32 ctrl;
1500	u32 status;
1501	u32 txcw;
1502	u32 i;
1503	s32 ret_val = 0;
1504
1505	ctrl = er32(CTRL);
1506	status = er32(STATUS);
1507	er32(RXCW);
1508	/* SYNCH bit and IV bit are sticky */
1509	usleep_range(10, 20);
1510	rxcw = er32(RXCW);
1511
1512	if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1513		/* Receiver is synchronized with no invalid bits.  */
1514		switch (mac->serdes_link_state) {
1515		case e1000_serdes_link_autoneg_complete:
1516			if (!(status & E1000_STATUS_LU)) {
1517				/* We have lost link, retry autoneg before
1518				 * reporting link failure
1519				 */
1520				mac->serdes_link_state =
1521				    e1000_serdes_link_autoneg_progress;
1522				mac->serdes_has_link = false;
1523				e_dbg("AN_UP     -> AN_PROG\n");
1524			} else {
1525				mac->serdes_has_link = true;
1526			}
1527			break;
1528
1529		case e1000_serdes_link_forced_up:
1530			/* If we are receiving /C/ ordered sets, re-enable
1531			 * auto-negotiation in the TXCW register and disable
1532			 * forced link in the Device Control register in an
1533			 * attempt to auto-negotiate with our link partner.
1534			 */
1535			if (rxcw & E1000_RXCW_C) {
1536				/* Enable autoneg, and unforce link up */
1537				ew32(TXCW, mac->txcw);
1538				ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1539				mac->serdes_link_state =
1540				    e1000_serdes_link_autoneg_progress;
1541				mac->serdes_has_link = false;
1542				e_dbg("FORCED_UP -> AN_PROG\n");
1543			} else {
1544				mac->serdes_has_link = true;
1545			}
1546			break;
1547
1548		case e1000_serdes_link_autoneg_progress:
1549			if (rxcw & E1000_RXCW_C) {
1550				/* We received /C/ ordered sets, meaning the
1551				 * link partner has autonegotiated, and we can
1552				 * trust the Link Up (LU) status bit.
1553				 */
1554				if (status & E1000_STATUS_LU) {
1555					mac->serdes_link_state =
1556					    e1000_serdes_link_autoneg_complete;
1557					e_dbg("AN_PROG   -> AN_UP\n");
1558					mac->serdes_has_link = true;
1559				} else {
1560					/* Autoneg completed, but failed. */
1561					mac->serdes_link_state =
1562					    e1000_serdes_link_down;
1563					e_dbg("AN_PROG   -> DOWN\n");
1564				}
1565			} else {
1566				/* The link partner did not autoneg.
1567				 * Force link up and full duplex, and change
1568				 * state to forced.
1569				 */
1570				ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1571				ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1572				ew32(CTRL, ctrl);
1573
1574				/* Configure Flow Control after link up. */
1575				ret_val = e1000e_config_fc_after_link_up(hw);
1576				if (ret_val) {
1577					e_dbg("Error config flow control\n");
1578					break;
1579				}
1580				mac->serdes_link_state =
1581				    e1000_serdes_link_forced_up;
1582				mac->serdes_has_link = true;
1583				e_dbg("AN_PROG   -> FORCED_UP\n");
1584			}
1585			break;
1586
1587		case e1000_serdes_link_down:
1588		default:
1589			/* The link was down but the receiver has now gained
1590			 * valid sync, so lets see if we can bring the link
1591			 * up.
1592			 */
1593			ew32(TXCW, mac->txcw);
1594			ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1595			mac->serdes_link_state =
1596			    e1000_serdes_link_autoneg_progress;
1597			mac->serdes_has_link = false;
1598			e_dbg("DOWN      -> AN_PROG\n");
1599			break;
1600		}
1601	} else {
1602		if (!(rxcw & E1000_RXCW_SYNCH)) {
1603			mac->serdes_has_link = false;
1604			mac->serdes_link_state = e1000_serdes_link_down;
1605			e_dbg("ANYSTATE  -> DOWN\n");
1606		} else {
1607			/* Check several times, if SYNCH bit and CONFIG
1608			 * bit both are consistently 1 then simply ignore
1609			 * the IV bit and restart Autoneg
1610			 */
1611			for (i = 0; i < AN_RETRY_COUNT; i++) {
1612				usleep_range(10, 20);
1613				rxcw = er32(RXCW);
1614				if ((rxcw & E1000_RXCW_SYNCH) &&
1615				    (rxcw & E1000_RXCW_C))
1616					continue;
1617
1618				if (rxcw & E1000_RXCW_IV) {
1619					mac->serdes_has_link = false;
1620					mac->serdes_link_state =
1621					    e1000_serdes_link_down;
1622					e_dbg("ANYSTATE  -> DOWN\n");
1623					break;
1624				}
1625			}
1626
1627			if (i == AN_RETRY_COUNT) {
1628				txcw = er32(TXCW);
1629				txcw |= E1000_TXCW_ANE;
1630				ew32(TXCW, txcw);
1631				mac->serdes_link_state =
1632				    e1000_serdes_link_autoneg_progress;
1633				mac->serdes_has_link = false;
1634				e_dbg("ANYSTATE  -> AN_PROG\n");
1635			}
1636		}
1637	}
1638
1639	return ret_val;
1640}
1641
1642/**
1643 *  e1000_valid_led_default_82571 - Verify a valid default LED config
1644 *  @hw: pointer to the HW structure
1645 *  @data: pointer to the NVM (EEPROM)
1646 *
1647 *  Read the EEPROM for the current default LED configuration.  If the
1648 *  LED configuration is not valid, set to a valid LED configuration.
1649 **/
1650static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1651{
1652	s32 ret_val;
1653
1654	ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1655	if (ret_val) {
1656		e_dbg("NVM Read Error\n");
1657		return ret_val;
1658	}
1659
1660	switch (hw->mac.type) {
1661	case e1000_82573:
1662	case e1000_82574:
1663	case e1000_82583:
1664		if (*data == ID_LED_RESERVED_F746)
1665			*data = ID_LED_DEFAULT_82573;
1666		break;
1667	default:
1668		if (*data == ID_LED_RESERVED_0000 ||
1669		    *data == ID_LED_RESERVED_FFFF)
1670			*data = ID_LED_DEFAULT;
1671		break;
1672	}
1673
1674	return 0;
1675}
1676
1677/**
1678 *  e1000e_get_laa_state_82571 - Get locally administered address state
1679 *  @hw: pointer to the HW structure
1680 *
1681 *  Retrieve and return the current locally administered address state.
1682 **/
1683bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1684{
1685	if (hw->mac.type != e1000_82571)
1686		return false;
1687
1688	return hw->dev_spec.e82571.laa_is_present;
1689}
1690
1691/**
1692 *  e1000e_set_laa_state_82571 - Set locally administered address state
1693 *  @hw: pointer to the HW structure
1694 *  @state: enable/disable locally administered address
1695 *
1696 *  Enable/Disable the current locally administered address state.
1697 **/
1698void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1699{
1700	if (hw->mac.type != e1000_82571)
1701		return;
1702
1703	hw->dev_spec.e82571.laa_is_present = state;
1704
1705	/* If workaround is activated... */
1706	if (state)
1707		/* Hold a copy of the LAA in RAR[14] This is done so that
1708		 * between the time RAR[0] gets clobbered and the time it
1709		 * gets fixed, the actual LAA is in one of the RARs and no
1710		 * incoming packets directed to this port are dropped.
1711		 * Eventually the LAA will be in RAR[0] and RAR[14].
1712		 */
1713		hw->mac.ops.rar_set(hw, hw->mac.addr,
1714				    hw->mac.rar_entry_count - 1);
1715}
1716
1717/**
1718 *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1719 *  @hw: pointer to the HW structure
1720 *
1721 *  Verifies that the EEPROM has completed the update.  After updating the
1722 *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1723 *  the checksum fix is not implemented, we need to set the bit and update
1724 *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1725 *  we need to return bad checksum.
1726 **/
1727static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1728{
1729	struct e1000_nvm_info *nvm = &hw->nvm;
1730	s32 ret_val;
1731	u16 data;
1732
1733	if (nvm->type != e1000_nvm_flash_hw)
1734		return 0;
1735
1736	/* Check bit 4 of word 10h.  If it is 0, firmware is done updating
1737	 * 10h-12h.  Checksum may need to be fixed.
1738	 */
1739	ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1740	if (ret_val)
1741		return ret_val;
1742
1743	if (!(data & 0x10)) {
1744		/* Read 0x23 and check bit 15.  This bit is a 1
1745		 * when the checksum has already been fixed.  If
1746		 * the checksum is still wrong and this bit is a
1747		 * 1, we need to return bad checksum.  Otherwise,
1748		 * we need to set this bit to a 1 and update the
1749		 * checksum.
1750		 */
1751		ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1752		if (ret_val)
1753			return ret_val;
1754
1755		if (!(data & 0x8000)) {
1756			data |= 0x8000;
1757			ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1758			if (ret_val)
1759				return ret_val;
1760			ret_val = e1000e_update_nvm_checksum(hw);
1761			if (ret_val)
1762				return ret_val;
1763		}
1764	}
1765
1766	return 0;
1767}
1768
1769/**
1770 *  e1000_read_mac_addr_82571 - Read device MAC address
1771 *  @hw: pointer to the HW structure
1772 **/
1773static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1774{
1775	if (hw->mac.type == e1000_82571) {
1776		s32 ret_val;
1777
1778		/* If there's an alternate MAC address place it in RAR0
1779		 * so that it will override the Si installed default perm
1780		 * address.
1781		 */
1782		ret_val = e1000_check_alt_mac_addr_generic(hw);
1783		if (ret_val)
1784			return ret_val;
1785	}
1786
1787	return e1000_read_mac_addr_generic(hw);
1788}
1789
1790/**
1791 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1792 * @hw: pointer to the HW structure
1793 *
1794 * In the case of a PHY power down to save power, or to turn off link during a
1795 * driver unload, or wake on lan is not enabled, remove the link.
1796 **/
1797static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1798{
1799	struct e1000_phy_info *phy = &hw->phy;
1800	struct e1000_mac_info *mac = &hw->mac;
1801
1802	if (!phy->ops.check_reset_block)
1803		return;
1804
1805	/* If the management interface is not enabled, then power down */
1806	if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1807		e1000_power_down_phy_copper(hw);
1808}
1809
1810/**
1811 *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1812 *  @hw: pointer to the HW structure
1813 *
1814 *  Clears the hardware counters by reading the counter registers.
1815 **/
1816static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1817{
1818	e1000e_clear_hw_cntrs_base(hw);
1819
1820	er32(PRC64);
1821	er32(PRC127);
1822	er32(PRC255);
1823	er32(PRC511);
1824	er32(PRC1023);
1825	er32(PRC1522);
1826	er32(PTC64);
1827	er32(PTC127);
1828	er32(PTC255);
1829	er32(PTC511);
1830	er32(PTC1023);
1831	er32(PTC1522);
1832
1833	er32(ALGNERRC);
1834	er32(RXERRC);
1835	er32(TNCRS);
1836	er32(CEXTERR);
1837	er32(TSCTC);
1838	er32(TSCTFC);
1839
1840	er32(MGTPRC);
1841	er32(MGTPDC);
1842	er32(MGTPTC);
1843
1844	er32(IAC);
1845	er32(ICRXOC);
1846
1847	er32(ICRXPTC);
1848	er32(ICRXATC);
1849	er32(ICTXPTC);
1850	er32(ICTXATC);
1851	er32(ICTXQEC);
1852	er32(ICTXQMTC);
1853	er32(ICRXDMTC);
1854}
1855
1856static const struct e1000_mac_operations e82571_mac_ops = {
1857	/* .check_mng_mode: mac type dependent */
1858	/* .check_for_link: media type dependent */
1859	.id_led_init		= e1000e_id_led_init_generic,
1860	.cleanup_led		= e1000e_cleanup_led_generic,
1861	.clear_hw_cntrs		= e1000_clear_hw_cntrs_82571,
1862	.get_bus_info		= e1000e_get_bus_info_pcie,
1863	.set_lan_id		= e1000_set_lan_id_multi_port_pcie,
1864	/* .get_link_up_info: media type dependent */
1865	/* .led_on: mac type dependent */
1866	.led_off		= e1000e_led_off_generic,
1867	.update_mc_addr_list	= e1000e_update_mc_addr_list_generic,
1868	.write_vfta		= e1000_write_vfta_generic,
1869	.clear_vfta		= e1000_clear_vfta_82571,
1870	.reset_hw		= e1000_reset_hw_82571,
1871	.init_hw		= e1000_init_hw_82571,
1872	.setup_link		= e1000_setup_link_82571,
1873	/* .setup_physical_interface: media type dependent */
1874	.setup_led		= e1000e_setup_led_generic,
1875	.config_collision_dist	= e1000e_config_collision_dist_generic,
1876	.read_mac_addr		= e1000_read_mac_addr_82571,
1877	.rar_set		= e1000e_rar_set_generic,
1878	.rar_get_count		= e1000e_rar_get_count_generic,
1879};
1880
1881static const struct e1000_phy_operations e82_phy_ops_igp = {
1882	.acquire		= e1000_get_hw_semaphore_82571,
1883	.check_polarity		= e1000_check_polarity_igp,
1884	.check_reset_block	= e1000e_check_reset_block_generic,
1885	.commit			= NULL,
1886	.force_speed_duplex	= e1000e_phy_force_speed_duplex_igp,
1887	.get_cfg_done		= e1000_get_cfg_done_82571,
1888	.get_cable_length	= e1000e_get_cable_length_igp_2,
1889	.get_info		= e1000e_get_phy_info_igp,
1890	.read_reg		= e1000e_read_phy_reg_igp,
1891	.release		= e1000_put_hw_semaphore_82571,
1892	.reset			= e1000e_phy_hw_reset_generic,
1893	.set_d0_lplu_state	= e1000_set_d0_lplu_state_82571,
1894	.set_d3_lplu_state	= e1000e_set_d3_lplu_state,
1895	.write_reg		= e1000e_write_phy_reg_igp,
1896	.cfg_on_link_up		= NULL,
1897};
1898
1899static const struct e1000_phy_operations e82_phy_ops_m88 = {
1900	.acquire		= e1000_get_hw_semaphore_82571,
1901	.check_polarity		= e1000_check_polarity_m88,
1902	.check_reset_block	= e1000e_check_reset_block_generic,
1903	.commit			= e1000e_phy_sw_reset,
1904	.force_speed_duplex	= e1000e_phy_force_speed_duplex_m88,
1905	.get_cfg_done		= e1000e_get_cfg_done_generic,
1906	.get_cable_length	= e1000e_get_cable_length_m88,
1907	.get_info		= e1000e_get_phy_info_m88,
1908	.read_reg		= e1000e_read_phy_reg_m88,
1909	.release		= e1000_put_hw_semaphore_82571,
1910	.reset			= e1000e_phy_hw_reset_generic,
1911	.set_d0_lplu_state	= e1000_set_d0_lplu_state_82571,
1912	.set_d3_lplu_state	= e1000e_set_d3_lplu_state,
1913	.write_reg		= e1000e_write_phy_reg_m88,
1914	.cfg_on_link_up		= NULL,
1915};
1916
1917static const struct e1000_phy_operations e82_phy_ops_bm = {
1918	.acquire		= e1000_get_hw_semaphore_82571,
1919	.check_polarity		= e1000_check_polarity_m88,
1920	.check_reset_block	= e1000e_check_reset_block_generic,
1921	.commit			= e1000e_phy_sw_reset,
1922	.force_speed_duplex	= e1000e_phy_force_speed_duplex_m88,
1923	.get_cfg_done		= e1000e_get_cfg_done_generic,
1924	.get_cable_length	= e1000e_get_cable_length_m88,
1925	.get_info		= e1000e_get_phy_info_m88,
1926	.read_reg		= e1000e_read_phy_reg_bm2,
1927	.release		= e1000_put_hw_semaphore_82571,
1928	.reset			= e1000e_phy_hw_reset_generic,
1929	.set_d0_lplu_state	= e1000_set_d0_lplu_state_82571,
1930	.set_d3_lplu_state	= e1000e_set_d3_lplu_state,
1931	.write_reg		= e1000e_write_phy_reg_bm2,
1932	.cfg_on_link_up		= NULL,
1933};
1934
1935static const struct e1000_nvm_operations e82571_nvm_ops = {
1936	.acquire		= e1000_acquire_nvm_82571,
1937	.read			= e1000e_read_nvm_eerd,
1938	.release		= e1000_release_nvm_82571,
1939	.reload			= e1000e_reload_nvm_generic,
1940	.update			= e1000_update_nvm_checksum_82571,
1941	.valid_led_default	= e1000_valid_led_default_82571,
1942	.validate		= e1000_validate_nvm_checksum_82571,
1943	.write			= e1000_write_nvm_82571,
1944};
1945
1946const struct e1000_info e1000_82571_info = {
1947	.mac			= e1000_82571,
1948	.flags			= FLAG_HAS_HW_VLAN_FILTER
1949				  | FLAG_HAS_JUMBO_FRAMES
1950				  | FLAG_HAS_WOL
1951				  | FLAG_APME_IN_CTRL3
1952				  | FLAG_HAS_CTRLEXT_ON_LOAD
1953				  | FLAG_HAS_SMART_POWER_DOWN
1954				  | FLAG_RESET_OVERWRITES_LAA /* errata */
1955				  | FLAG_TARC_SPEED_MODE_BIT /* errata */
1956				  | FLAG_APME_CHECK_PORT_B,
1957	.flags2			= FLAG2_DISABLE_ASPM_L1 /* errata 13 */
1958				  | FLAG2_DMA_BURST,
1959	.pba			= 38,
1960	.max_hw_frame_size	= DEFAULT_JUMBO,
1961	.get_variants		= e1000_get_variants_82571,
1962	.mac_ops		= &e82571_mac_ops,
1963	.phy_ops		= &e82_phy_ops_igp,
1964	.nvm_ops		= &e82571_nvm_ops,
1965};
1966
1967const struct e1000_info e1000_82572_info = {
1968	.mac			= e1000_82572,
1969	.flags			= FLAG_HAS_HW_VLAN_FILTER
1970				  | FLAG_HAS_JUMBO_FRAMES
1971				  | FLAG_HAS_WOL
1972				  | FLAG_APME_IN_CTRL3
1973				  | FLAG_HAS_CTRLEXT_ON_LOAD
1974				  | FLAG_TARC_SPEED_MODE_BIT, /* errata */
1975	.flags2			= FLAG2_DISABLE_ASPM_L1 /* errata 13 */
1976				  | FLAG2_DMA_BURST,
1977	.pba			= 38,
1978	.max_hw_frame_size	= DEFAULT_JUMBO,
1979	.get_variants		= e1000_get_variants_82571,
1980	.mac_ops		= &e82571_mac_ops,
1981	.phy_ops		= &e82_phy_ops_igp,
1982	.nvm_ops		= &e82571_nvm_ops,
1983};
1984
1985const struct e1000_info e1000_82573_info = {
1986	.mac			= e1000_82573,
1987	.flags			= FLAG_HAS_HW_VLAN_FILTER
1988				  | FLAG_HAS_WOL
1989				  | FLAG_APME_IN_CTRL3
1990				  | FLAG_HAS_SMART_POWER_DOWN
1991				  | FLAG_HAS_AMT
1992				  | FLAG_HAS_SWSM_ON_LOAD,
1993	.flags2			= FLAG2_DISABLE_ASPM_L1
1994				  | FLAG2_DISABLE_ASPM_L0S,
1995	.pba			= 20,
1996	.max_hw_frame_size	= VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
1997	.get_variants		= e1000_get_variants_82571,
1998	.mac_ops		= &e82571_mac_ops,
1999	.phy_ops		= &e82_phy_ops_m88,
2000	.nvm_ops		= &e82571_nvm_ops,
2001};
2002
2003const struct e1000_info e1000_82574_info = {
2004	.mac			= e1000_82574,
2005	.flags			= FLAG_HAS_HW_VLAN_FILTER
2006				  | FLAG_HAS_MSIX
2007				  | FLAG_HAS_JUMBO_FRAMES
2008				  | FLAG_HAS_WOL
2009				  | FLAG_HAS_HW_TIMESTAMP
2010				  | FLAG_APME_IN_CTRL3
2011				  | FLAG_HAS_SMART_POWER_DOWN
2012				  | FLAG_HAS_AMT
2013				  | FLAG_HAS_CTRLEXT_ON_LOAD,
2014	.flags2			 = FLAG2_CHECK_PHY_HANG
2015				  | FLAG2_DISABLE_ASPM_L0S
2016				  | FLAG2_DISABLE_ASPM_L1
2017				  | FLAG2_NO_DISABLE_RX
2018				  | FLAG2_DMA_BURST
2019				  | FLAG2_CHECK_SYSTIM_OVERFLOW,
2020	.pba			= 32,
2021	.max_hw_frame_size	= DEFAULT_JUMBO,
2022	.get_variants		= e1000_get_variants_82571,
2023	.mac_ops		= &e82571_mac_ops,
2024	.phy_ops		= &e82_phy_ops_bm,
2025	.nvm_ops		= &e82571_nvm_ops,
2026};
2027
2028const struct e1000_info e1000_82583_info = {
2029	.mac			= e1000_82583,
2030	.flags			= FLAG_HAS_HW_VLAN_FILTER
2031				  | FLAG_HAS_WOL
2032				  | FLAG_HAS_HW_TIMESTAMP
2033				  | FLAG_APME_IN_CTRL3
2034				  | FLAG_HAS_SMART_POWER_DOWN
2035				  | FLAG_HAS_AMT
2036				  | FLAG_HAS_JUMBO_FRAMES
2037				  | FLAG_HAS_CTRLEXT_ON_LOAD,
2038	.flags2			= FLAG2_DISABLE_ASPM_L0S
2039				  | FLAG2_DISABLE_ASPM_L1
2040				  | FLAG2_NO_DISABLE_RX
2041				  | FLAG2_CHECK_SYSTIM_OVERFLOW,
2042	.pba			= 32,
2043	.max_hw_frame_size	= DEFAULT_JUMBO,
2044	.get_variants		= e1000_get_variants_82571,
2045	.mac_ops		= &e82571_mac_ops,
2046	.phy_ops		= &e82_phy_ops_bm,
2047	.nvm_ops		= &e82571_nvm_ops,
2048};