ice_txrx.c - drivers/net/ethernet/intel/ice/ice_txrx.c - Linux diff v6.13.7

   1// SPDX-License-Identifier: GPL-2.0
   2/* Copyright (c) 2018, Intel Corporation. */
   3
   4/* The driver transmit and receive code */
   5
   6#include <linux/mm.h>
   7#include <linux/netdevice.h>
   8#include <linux/prefetch.h>
   9#include <linux/bpf_trace.h>
  10#include <net/dsfield.h>
  11#include <net/mpls.h>
  12#include <net/xdp.h>
  13#include "ice_txrx_lib.h"
  14#include "ice_lib.h"
  15#include "ice.h"
  16#include "ice_trace.h"
  17#include "ice_dcb_lib.h"
  18#include "ice_xsk.h"
  19#include "ice_eswitch.h"
  20
  21#define ICE_RX_HDR_SIZE		256
  22
  23#define FDIR_DESC_RXDID 0x40
  24#define ICE_FDIR_CLEAN_DELAY 10
  25
  26/**
  27 * ice_prgm_fdir_fltr - Program a Flow Director filter
  28 * @vsi: VSI to send dummy packet
  29 * @fdir_desc: flow director descriptor
  30 * @raw_packet: allocated buffer for flow director
  31 */
  32int
  33ice_prgm_fdir_fltr(struct ice_vsi *vsi, struct ice_fltr_desc *fdir_desc,
  34		   u8 *raw_packet)
  35{
  36	struct ice_tx_buf *tx_buf, *first;
  37	struct ice_fltr_desc *f_desc;
  38	struct ice_tx_desc *tx_desc;
  39	struct ice_tx_ring *tx_ring;
  40	struct device *dev;
  41	dma_addr_t dma;
  42	u32 td_cmd;
  43	u16 i;
  44
  45	/* VSI and Tx ring */
  46	if (!vsi)
  47		return -ENOENT;
  48	tx_ring = vsi->tx_rings[0];
  49	if (!tx_ring || !tx_ring->desc)
  50		return -ENOENT;
  51	dev = tx_ring->dev;
  52
  53	/* we are using two descriptors to add/del a filter and we can wait */
  54	for (i = ICE_FDIR_CLEAN_DELAY; ICE_DESC_UNUSED(tx_ring) < 2; i--) {
  55		if (!i)
  56			return -EAGAIN;
  57		msleep_interruptible(1);
  58	}
  59
  60	dma = dma_map_single(dev, raw_packet, ICE_FDIR_MAX_RAW_PKT_SIZE,
  61			     DMA_TO_DEVICE);
  62
  63	if (dma_mapping_error(dev, dma))
  64		return -EINVAL;
  65
  66	/* grab the next descriptor */
  67	i = tx_ring->next_to_use;
  68	first = &tx_ring->tx_buf[i];
  69	f_desc = ICE_TX_FDIRDESC(tx_ring, i);
  70	memcpy(f_desc, fdir_desc, sizeof(*f_desc));
  71
  72	i++;
  73	i = (i < tx_ring->count) ? i : 0;
  74	tx_desc = ICE_TX_DESC(tx_ring, i);
  75	tx_buf = &tx_ring->tx_buf[i];
  76
  77	i++;
  78	tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
  79
  80	memset(tx_buf, 0, sizeof(*tx_buf));
  81	dma_unmap_len_set(tx_buf, len, ICE_FDIR_MAX_RAW_PKT_SIZE);
  82	dma_unmap_addr_set(tx_buf, dma, dma);
  83
  84	tx_desc->buf_addr = cpu_to_le64(dma);
  85	td_cmd = ICE_TXD_LAST_DESC_CMD | ICE_TX_DESC_CMD_DUMMY |
  86		 ICE_TX_DESC_CMD_RE;
  87
  88	tx_buf->type = ICE_TX_BUF_DUMMY;
  89	tx_buf->raw_buf = raw_packet;
  90
  91	tx_desc->cmd_type_offset_bsz =
  92		ice_build_ctob(td_cmd, 0, ICE_FDIR_MAX_RAW_PKT_SIZE, 0);
  93
  94	/* Force memory write to complete before letting h/w know
  95	 * there are new descriptors to fetch.
  96	 */
  97	wmb();
  98
  99	/* mark the data descriptor to be watched */
 100	first->next_to_watch = tx_desc;
 101
 102	writel(tx_ring->next_to_use, tx_ring->tail);
 103
 104	return 0;
 105}
 106
 107/**
 108 * ice_unmap_and_free_tx_buf - Release a Tx buffer
 109 * @ring: the ring that owns the buffer
 110 * @tx_buf: the buffer to free
 111 */
 112static void
 113ice_unmap_and_free_tx_buf(struct ice_tx_ring *ring, struct ice_tx_buf *tx_buf)
 114{
 115	if (dma_unmap_len(tx_buf, len))
 
 
 
 
 
 
 
 116		dma_unmap_page(ring->dev,
 117			       dma_unmap_addr(tx_buf, dma),
 118			       dma_unmap_len(tx_buf, len),
 119			       DMA_TO_DEVICE);
 120
 121	switch (tx_buf->type) {
 122	case ICE_TX_BUF_DUMMY:
 123		devm_kfree(ring->dev, tx_buf->raw_buf);
 124		break;
 125	case ICE_TX_BUF_SKB:
 126		dev_kfree_skb_any(tx_buf->skb);
 127		break;
 128	case ICE_TX_BUF_XDP_TX:
 129		page_frag_free(tx_buf->raw_buf);
 130		break;
 131	case ICE_TX_BUF_XDP_XMIT:
 132		xdp_return_frame(tx_buf->xdpf);
 133		break;
 134	}
 135
 136	tx_buf->next_to_watch = NULL;
 137	tx_buf->type = ICE_TX_BUF_EMPTY;
 138	dma_unmap_len_set(tx_buf, len, 0);
 139	/* tx_buf must be completely set up in the transmit path */
 140}
 141
 142static struct netdev_queue *txring_txq(const struct ice_tx_ring *ring)
 143{
 144	return netdev_get_tx_queue(ring->netdev, ring->q_index);
 145}
 146
 147/**
 148 * ice_clean_tx_ring - Free any empty Tx buffers
 149 * @tx_ring: ring to be cleaned
 150 */
 151void ice_clean_tx_ring(struct ice_tx_ring *tx_ring)
 152{
 153	u32 size;
 154	u16 i;
 155
 156	if (ice_ring_is_xdp(tx_ring) && tx_ring->xsk_pool) {
 157		ice_xsk_clean_xdp_ring(tx_ring);
 158		goto tx_skip_free;
 159	}
 160
 161	/* ring already cleared, nothing to do */
 162	if (!tx_ring->tx_buf)
 163		return;
 164
 165	/* Free all the Tx ring sk_buffs */
 166	for (i = 0; i < tx_ring->count; i++)
 167		ice_unmap_and_free_tx_buf(tx_ring, &tx_ring->tx_buf[i]);
 168
 169tx_skip_free:
 170	memset(tx_ring->tx_buf, 0, sizeof(*tx_ring->tx_buf) * tx_ring->count);
 171
 172	size = ALIGN(tx_ring->count * sizeof(struct ice_tx_desc),
 173		     PAGE_SIZE);
 174	/* Zero out the descriptor ring */
 175	memset(tx_ring->desc, 0, size);
 176
 177	tx_ring->next_to_use = 0;
 178	tx_ring->next_to_clean = 0;
 179
 180	if (!tx_ring->netdev)
 181		return;
 182
 183	/* cleanup Tx queue statistics */
 184	netdev_tx_reset_queue(txring_txq(tx_ring));
 185}
 186
 187/**
 188 * ice_free_tx_ring - Free Tx resources per queue
 189 * @tx_ring: Tx descriptor ring for a specific queue
 190 *
 191 * Free all transmit software resources
 192 */
 193void ice_free_tx_ring(struct ice_tx_ring *tx_ring)
 194{
 195	u32 size;
 196
 197	ice_clean_tx_ring(tx_ring);
 198	devm_kfree(tx_ring->dev, tx_ring->tx_buf);
 199	tx_ring->tx_buf = NULL;
 200
 201	if (tx_ring->desc) {
 202		size = ALIGN(tx_ring->count * sizeof(struct ice_tx_desc),
 203			     PAGE_SIZE);
 204		dmam_free_coherent(tx_ring->dev, size,
 205				   tx_ring->desc, tx_ring->dma);
 206		tx_ring->desc = NULL;
 207	}
 208}
 209
 210/**
 211 * ice_clean_tx_irq - Reclaim resources after transmit completes
 212 * @tx_ring: Tx ring to clean
 213 * @napi_budget: Used to determine if we are in netpoll
 214 *
 215 * Returns true if there's any budget left (e.g. the clean is finished)
 216 */
 217static bool ice_clean_tx_irq(struct ice_tx_ring *tx_ring, int napi_budget)
 218{
 219	unsigned int total_bytes = 0, total_pkts = 0;
 220	unsigned int budget = ICE_DFLT_IRQ_WORK;
 221	struct ice_vsi *vsi = tx_ring->vsi;
 222	s16 i = tx_ring->next_to_clean;
 223	struct ice_tx_desc *tx_desc;
 224	struct ice_tx_buf *tx_buf;
 225
 226	/* get the bql data ready */
 227	netdev_txq_bql_complete_prefetchw(txring_txq(tx_ring));
 228
 229	tx_buf = &tx_ring->tx_buf[i];
 230	tx_desc = ICE_TX_DESC(tx_ring, i);
 231	i -= tx_ring->count;
 232
 233	prefetch(&vsi->state);
 234
 235	do {
 236		struct ice_tx_desc *eop_desc = tx_buf->next_to_watch;
 237
 238		/* if next_to_watch is not set then there is no work pending */
 239		if (!eop_desc)
 240			break;
 241
 242		/* follow the guidelines of other drivers */
 243		prefetchw(&tx_buf->skb->users);
 244
 245		smp_rmb();	/* prevent any other reads prior to eop_desc */
 246
 247		ice_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf);
 248		/* if the descriptor isn't done, no work yet to do */
 249		if (!(eop_desc->cmd_type_offset_bsz &
 250		      cpu_to_le64(ICE_TX_DESC_DTYPE_DESC_DONE)))
 251			break;
 252
 253		/* clear next_to_watch to prevent false hangs */
 254		tx_buf->next_to_watch = NULL;
 255
 256		/* update the statistics for this packet */
 257		total_bytes += tx_buf->bytecount;
 258		total_pkts += tx_buf->gso_segs;
 259
 260		/* free the skb */
 261		napi_consume_skb(tx_buf->skb, napi_budget);
 262
 263		/* unmap skb header data */
 264		dma_unmap_single(tx_ring->dev,
 265				 dma_unmap_addr(tx_buf, dma),
 266				 dma_unmap_len(tx_buf, len),
 267				 DMA_TO_DEVICE);
 268
 269		/* clear tx_buf data */
 270		tx_buf->type = ICE_TX_BUF_EMPTY;
 271		dma_unmap_len_set(tx_buf, len, 0);
 272
 273		/* unmap remaining buffers */
 274		while (tx_desc != eop_desc) {
 275			ice_trace(clean_tx_irq_unmap, tx_ring, tx_desc, tx_buf);
 276			tx_buf++;
 277			tx_desc++;
 278			i++;
 279			if (unlikely(!i)) {
 280				i -= tx_ring->count;
 281				tx_buf = tx_ring->tx_buf;
 282				tx_desc = ICE_TX_DESC(tx_ring, 0);
 283			}
 284
 285			/* unmap any remaining paged data */
 286			if (dma_unmap_len(tx_buf, len)) {
 287				dma_unmap_page(tx_ring->dev,
 288					       dma_unmap_addr(tx_buf, dma),
 289					       dma_unmap_len(tx_buf, len),
 290					       DMA_TO_DEVICE);
 291				dma_unmap_len_set(tx_buf, len, 0);
 292			}
 293		}
 294		ice_trace(clean_tx_irq_unmap_eop, tx_ring, tx_desc, tx_buf);
 295
 296		/* move us one more past the eop_desc for start of next pkt */
 297		tx_buf++;
 298		tx_desc++;
 299		i++;
 300		if (unlikely(!i)) {
 301			i -= tx_ring->count;
 302			tx_buf = tx_ring->tx_buf;
 303			tx_desc = ICE_TX_DESC(tx_ring, 0);
 304		}
 305
 306		prefetch(tx_desc);
 307
 308		/* update budget accounting */
 309		budget--;
 310	} while (likely(budget));
 311
 312	i += tx_ring->count;
 313	tx_ring->next_to_clean = i;
 
 
 
 
 
 
 314
 315	ice_update_tx_ring_stats(tx_ring, total_pkts, total_bytes);
 316	netdev_tx_completed_queue(txring_txq(tx_ring), total_pkts, total_bytes);
 317
 318#define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2))
 319	if (unlikely(total_pkts && netif_carrier_ok(tx_ring->netdev) &&
 320		     (ICE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 321		/* Make sure that anybody stopping the queue after this
 322		 * sees the new next_to_clean.
 323		 */
 324		smp_mb();
 325		if (netif_tx_queue_stopped(txring_txq(tx_ring)) &&
 326		    !test_bit(ICE_VSI_DOWN, vsi->state)) {
 327			netif_tx_wake_queue(txring_txq(tx_ring));
 328			++tx_ring->ring_stats->tx_stats.restart_q;
 
 
 329		}
 330	}
 331
 332	return !!budget;
 333}
 334
 335/**
 336 * ice_setup_tx_ring - Allocate the Tx descriptors
 337 * @tx_ring: the Tx ring to set up
 338 *
 339 * Return 0 on success, negative on error
 340 */
 341int ice_setup_tx_ring(struct ice_tx_ring *tx_ring)
 342{
 343	struct device *dev = tx_ring->dev;
 344	u32 size;
 345
 346	if (!dev)
 347		return -ENOMEM;
 348
 349	/* warn if we are about to overwrite the pointer */
 350	WARN_ON(tx_ring->tx_buf);
 351	tx_ring->tx_buf =
 352		devm_kcalloc(dev, sizeof(*tx_ring->tx_buf), tx_ring->count,
 353			     GFP_KERNEL);
 354	if (!tx_ring->tx_buf)
 355		return -ENOMEM;
 356
 357	/* round up to nearest page */
 358	size = ALIGN(tx_ring->count * sizeof(struct ice_tx_desc),
 359		     PAGE_SIZE);
 360	tx_ring->desc = dmam_alloc_coherent(dev, size, &tx_ring->dma,
 361					    GFP_KERNEL);
 362	if (!tx_ring->desc) {
 363		dev_err(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
 364			size);
 365		goto err;
 366	}
 367
 368	tx_ring->next_to_use = 0;
 369	tx_ring->next_to_clean = 0;
 370	tx_ring->ring_stats->tx_stats.prev_pkt = -1;
 371	return 0;
 372
 373err:
 374	devm_kfree(dev, tx_ring->tx_buf);
 375	tx_ring->tx_buf = NULL;
 376	return -ENOMEM;
 377}
 378
 379/**
 380 * ice_clean_rx_ring - Free Rx buffers
 381 * @rx_ring: ring to be cleaned
 382 */
 383void ice_clean_rx_ring(struct ice_rx_ring *rx_ring)
 384{
 385	struct xdp_buff *xdp = &rx_ring->xdp;
 386	struct device *dev = rx_ring->dev;
 387	u32 size;
 388	u16 i;
 389
 390	/* ring already cleared, nothing to do */
 391	if (!rx_ring->rx_buf)
 392		return;
 393
 394	if (rx_ring->xsk_pool) {
 395		ice_xsk_clean_rx_ring(rx_ring);
 396		goto rx_skip_free;
 397	}
 398
 399	if (xdp->data) {
 400		xdp_return_buff(xdp);
 401		xdp->data = NULL;
 402	}
 403
 404	/* Free all the Rx ring sk_buffs */
 405	for (i = 0; i < rx_ring->count; i++) {
 406		struct ice_rx_buf *rx_buf = &rx_ring->rx_buf[i];
 407
 
 
 
 
 408		if (!rx_buf->page)
 409			continue;
 410
 411		/* Invalidate cache lines that may have been written to by
 412		 * device so that we avoid corrupting memory.
 413		 */
 414		dma_sync_single_range_for_cpu(dev, rx_buf->dma,
 415					      rx_buf->page_offset,
 416					      rx_ring->rx_buf_len,
 417					      DMA_FROM_DEVICE);
 418
 419		/* free resources associated with mapping */
 420		dma_unmap_page_attrs(dev, rx_buf->dma, ice_rx_pg_size(rx_ring),
 421				     DMA_FROM_DEVICE, ICE_RX_DMA_ATTR);
 422		__page_frag_cache_drain(rx_buf->page, rx_buf->pagecnt_bias);
 423
 424		rx_buf->page = NULL;
 425		rx_buf->page_offset = 0;
 426	}
 427
 428rx_skip_free:
 429	if (rx_ring->xsk_pool)
 430		memset(rx_ring->xdp_buf, 0, array_size(rx_ring->count, sizeof(*rx_ring->xdp_buf)));
 431	else
 432		memset(rx_ring->rx_buf, 0, array_size(rx_ring->count, sizeof(*rx_ring->rx_buf)));
 433
 434	/* Zero out the descriptor ring */
 435	size = ALIGN(rx_ring->count * sizeof(union ice_32byte_rx_desc),
 436		     PAGE_SIZE);
 437	memset(rx_ring->desc, 0, size);
 438
 439	rx_ring->next_to_alloc = 0;
 440	rx_ring->next_to_clean = 0;
 441	rx_ring->first_desc = 0;
 442	rx_ring->next_to_use = 0;
 443}
 444
 445/**
 446 * ice_free_rx_ring - Free Rx resources
 447 * @rx_ring: ring to clean the resources from
 448 *
 449 * Free all receive software resources
 450 */
 451void ice_free_rx_ring(struct ice_rx_ring *rx_ring)
 452{
 453	u32 size;
 454
 455	ice_clean_rx_ring(rx_ring);
 456	if (rx_ring->vsi->type == ICE_VSI_PF)
 457		if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq))
 458			xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
 459	WRITE_ONCE(rx_ring->xdp_prog, NULL);
 460	if (rx_ring->xsk_pool) {
 461		kfree(rx_ring->xdp_buf);
 462		rx_ring->xdp_buf = NULL;
 463	} else {
 464		kfree(rx_ring->rx_buf);
 465		rx_ring->rx_buf = NULL;
 466	}
 467
 468	if (rx_ring->desc) {
 469		size = ALIGN(rx_ring->count * sizeof(union ice_32byte_rx_desc),
 470			     PAGE_SIZE);
 471		dmam_free_coherent(rx_ring->dev, size,
 472				   rx_ring->desc, rx_ring->dma);
 473		rx_ring->desc = NULL;
 474	}
 475}
 476
 477/**
 478 * ice_setup_rx_ring - Allocate the Rx descriptors
 479 * @rx_ring: the Rx ring to set up
 480 *
 481 * Return 0 on success, negative on error
 482 */
 483int ice_setup_rx_ring(struct ice_rx_ring *rx_ring)
 484{
 485	struct device *dev = rx_ring->dev;
 486	u32 size;
 487
 488	if (!dev)
 489		return -ENOMEM;
 490
 491	/* warn if we are about to overwrite the pointer */
 492	WARN_ON(rx_ring->rx_buf);
 493	rx_ring->rx_buf =
 494		kcalloc(rx_ring->count, sizeof(*rx_ring->rx_buf), GFP_KERNEL);
 
 495	if (!rx_ring->rx_buf)
 496		return -ENOMEM;
 497
 498	/* round up to nearest page */
 499	size = ALIGN(rx_ring->count * sizeof(union ice_32byte_rx_desc),
 500		     PAGE_SIZE);
 501	rx_ring->desc = dmam_alloc_coherent(dev, size, &rx_ring->dma,
 502					    GFP_KERNEL);
 503	if (!rx_ring->desc) {
 504		dev_err(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
 505			size);
 506		goto err;
 507	}
 508
 509	rx_ring->next_to_use = 0;
 510	rx_ring->next_to_clean = 0;
 511	rx_ring->first_desc = 0;
 512
 513	if (ice_is_xdp_ena_vsi(rx_ring->vsi))
 514		WRITE_ONCE(rx_ring->xdp_prog, rx_ring->vsi->xdp_prog);
 515
 516	return 0;
 517
 518err:
 519	kfree(rx_ring->rx_buf);
 520	rx_ring->rx_buf = NULL;
 521	return -ENOMEM;
 522}
 523
 524/**
 525 * ice_run_xdp - Executes an XDP program on initialized xdp_buff
 526 * @rx_ring: Rx ring
 527 * @xdp: xdp_buff used as input to the XDP program
 528 * @xdp_prog: XDP program to run
 529 * @xdp_ring: ring to be used for XDP_TX action
 530 * @eop_desc: Last descriptor in packet to read metadata from
 531 *
 532 * Returns any of ICE_XDP_{PASS, CONSUMED, TX, REDIR}
 533 */
 534static u32
 535ice_run_xdp(struct ice_rx_ring *rx_ring, struct xdp_buff *xdp,
 536	    struct bpf_prog *xdp_prog, struct ice_tx_ring *xdp_ring,
 537	    union ice_32b_rx_flex_desc *eop_desc)
 538{
 539	unsigned int ret = ICE_XDP_PASS;
 540	u32 act;
 541
 542	if (!xdp_prog)
 543		goto exit;
 544
 545	ice_xdp_meta_set_desc(xdp, eop_desc);
 546
 547	act = bpf_prog_run_xdp(xdp_prog, xdp);
 548	switch (act) {
 549	case XDP_PASS:
 550		break;
 551	case XDP_TX:
 552		if (static_branch_unlikely(&ice_xdp_locking_key))
 553			spin_lock(&xdp_ring->tx_lock);
 554		ret = __ice_xmit_xdp_ring(xdp, xdp_ring, false);
 555		if (static_branch_unlikely(&ice_xdp_locking_key))
 556			spin_unlock(&xdp_ring->tx_lock);
 557		if (ret == ICE_XDP_CONSUMED)
 558			goto out_failure;
 559		break;
 560	case XDP_REDIRECT:
 561		if (xdp_do_redirect(rx_ring->netdev, xdp, xdp_prog))
 562			goto out_failure;
 563		ret = ICE_XDP_REDIR;
 564		break;
 565	default:
 566		bpf_warn_invalid_xdp_action(rx_ring->netdev, xdp_prog, act);
 567		fallthrough;
 568	case XDP_ABORTED:
 569out_failure:
 570		trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
 571		fallthrough;
 572	case XDP_DROP:
 573		ret = ICE_XDP_CONSUMED;
 574	}
 575exit:
 576	return ret;
 577}
 578
 579/**
 580 * ice_xmit_xdp_ring - submit frame to XDP ring for transmission
 581 * @xdpf: XDP frame that will be converted to XDP buff
 582 * @xdp_ring: XDP ring for transmission
 583 */
 584static int ice_xmit_xdp_ring(const struct xdp_frame *xdpf,
 585			     struct ice_tx_ring *xdp_ring)
 586{
 587	struct xdp_buff xdp;
 588
 589	xdp.data_hard_start = (void *)xdpf;
 590	xdp.data = xdpf->data;
 591	xdp.data_end = xdp.data + xdpf->len;
 592	xdp.frame_sz = xdpf->frame_sz;
 593	xdp.flags = xdpf->flags;
 594
 595	return __ice_xmit_xdp_ring(&xdp, xdp_ring, true);
 596}
 597
 598/**
 599 * ice_xdp_xmit - submit packets to XDP ring for transmission
 600 * @dev: netdev
 601 * @n: number of XDP frames to be transmitted
 602 * @frames: XDP frames to be transmitted
 603 * @flags: transmit flags
 604 *
 605 * Returns number of frames successfully sent. Failed frames
 606 * will be free'ed by XDP core.
 607 * For error cases, a negative errno code is returned and no-frames
 608 * are transmitted (caller must handle freeing frames).
 609 */
 610int
 611ice_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
 612	     u32 flags)
 613{
 614	struct ice_netdev_priv *np = netdev_priv(dev);
 615	unsigned int queue_index = smp_processor_id();
 616	struct ice_vsi *vsi = np->vsi;
 617	struct ice_tx_ring *xdp_ring;
 618	struct ice_tx_buf *tx_buf;
 619	int nxmit = 0, i;
 620
 621	if (test_bit(ICE_VSI_DOWN, vsi->state))
 622		return -ENETDOWN;
 623
 624	if (!ice_is_xdp_ena_vsi(vsi))
 625		return -ENXIO;
 626
 627	if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
 628		return -EINVAL;
 629
 630	if (static_branch_unlikely(&ice_xdp_locking_key)) {
 631		queue_index %= vsi->num_xdp_txq;
 632		xdp_ring = vsi->xdp_rings[queue_index];
 633		spin_lock(&xdp_ring->tx_lock);
 634	} else {
 635		/* Generally, should not happen */
 636		if (unlikely(queue_index >= vsi->num_xdp_txq))
 637			return -ENXIO;
 638		xdp_ring = vsi->xdp_rings[queue_index];
 639	}
 640
 641	tx_buf = &xdp_ring->tx_buf[xdp_ring->next_to_use];
 642	for (i = 0; i < n; i++) {
 643		const struct xdp_frame *xdpf = frames[i];
 644		int err;
 645
 646		err = ice_xmit_xdp_ring(xdpf, xdp_ring);
 647		if (err != ICE_XDP_TX)
 648			break;
 649		nxmit++;
 650	}
 651
 652	tx_buf->rs_idx = ice_set_rs_bit(xdp_ring);
 653	if (unlikely(flags & XDP_XMIT_FLUSH))
 654		ice_xdp_ring_update_tail(xdp_ring);
 655
 656	if (static_branch_unlikely(&ice_xdp_locking_key))
 657		spin_unlock(&xdp_ring->tx_lock);
 658
 659	return nxmit;
 660}
 661
 662/**
 663 * ice_alloc_mapped_page - recycle or make a new page
 664 * @rx_ring: ring to use
 665 * @bi: rx_buf struct to modify
 666 *
 667 * Returns true if the page was successfully allocated or
 668 * reused.
 669 */
 670static bool
 671ice_alloc_mapped_page(struct ice_rx_ring *rx_ring, struct ice_rx_buf *bi)
 672{
 673	struct page *page = bi->page;
 674	dma_addr_t dma;
 675
 676	/* since we are recycling buffers we should seldom need to alloc */
 677	if (likely(page))
 
 678		return true;
 
 679
 680	/* alloc new page for storage */
 681	page = dev_alloc_pages(ice_rx_pg_order(rx_ring));
 682	if (unlikely(!page)) {
 683		rx_ring->ring_stats->rx_stats.alloc_page_failed++;
 684		return false;
 685	}
 686
 687	/* map page for use */
 688	dma = dma_map_page_attrs(rx_ring->dev, page, 0, ice_rx_pg_size(rx_ring),
 689				 DMA_FROM_DEVICE, ICE_RX_DMA_ATTR);
 690
 691	/* if mapping failed free memory back to system since
 692	 * there isn't much point in holding memory we can't use
 693	 */
 694	if (dma_mapping_error(rx_ring->dev, dma)) {
 695		__free_pages(page, ice_rx_pg_order(rx_ring));
 696		rx_ring->ring_stats->rx_stats.alloc_page_failed++;
 697		return false;
 698	}
 699
 700	bi->dma = dma;
 701	bi->page = page;
 702	bi->page_offset = rx_ring->rx_offset;
 703	page_ref_add(page, USHRT_MAX - 1);
 704	bi->pagecnt_bias = USHRT_MAX;
 705
 706	return true;
 707}
 708
 709/**
 710 * ice_alloc_rx_bufs - Replace used receive buffers
 711 * @rx_ring: ring to place buffers on
 712 * @cleaned_count: number of buffers to replace
 713 *
 714 * Returns false if all allocations were successful, true if any fail. Returning
 715 * true signals to the caller that we didn't replace cleaned_count buffers and
 716 * there is more work to do.
 717 *
 718 * First, try to clean "cleaned_count" Rx buffers. Then refill the cleaned Rx
 719 * buffers. Then bump tail at most one time. Grouping like this lets us avoid
 720 * multiple tail writes per call.
 721 */
 722bool ice_alloc_rx_bufs(struct ice_rx_ring *rx_ring, unsigned int cleaned_count)
 723{
 724	union ice_32b_rx_flex_desc *rx_desc;
 725	u16 ntu = rx_ring->next_to_use;
 726	struct ice_rx_buf *bi;
 727
 728	/* do nothing if no valid netdev defined */
 729	if ((!rx_ring->netdev && rx_ring->vsi->type != ICE_VSI_CTRL) ||
 730	    !cleaned_count)
 731		return false;
 732
 733	/* get the Rx descriptor and buffer based on next_to_use */
 734	rx_desc = ICE_RX_DESC(rx_ring, ntu);
 735	bi = &rx_ring->rx_buf[ntu];
 736
 737	do {
 738		/* if we fail here, we have work remaining */
 739		if (!ice_alloc_mapped_page(rx_ring, bi))
 740			break;
 741
 742		/* sync the buffer for use by the device */
 743		dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
 744						 bi->page_offset,
 745						 rx_ring->rx_buf_len,
 746						 DMA_FROM_DEVICE);
 747
 748		/* Refresh the desc even if buffer_addrs didn't change
 749		 * because each write-back erases this info.
 750		 */
 751		rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
 752
 753		rx_desc++;
 754		bi++;
 755		ntu++;
 756		if (unlikely(ntu == rx_ring->count)) {
 757			rx_desc = ICE_RX_DESC(rx_ring, 0);
 758			bi = rx_ring->rx_buf;
 759			ntu = 0;
 760		}
 761
 762		/* clear the status bits for the next_to_use descriptor */
 763		rx_desc->wb.status_error0 = 0;
 764
 765		cleaned_count--;
 766	} while (cleaned_count);
 767
 768	if (rx_ring->next_to_use != ntu)
 769		ice_release_rx_desc(rx_ring, ntu);
 770
 771	return !!cleaned_count;
 772}
 773
 774/**
 
 
 
 
 
 
 
 
 
 775 * ice_rx_buf_adjust_pg_offset - Prepare Rx buffer for reuse
 776 * @rx_buf: Rx buffer to adjust
 777 * @size: Size of adjustment
 778 *
 779 * Update the offset within page so that Rx buf will be ready to be reused.
 780 * For systems with PAGE_SIZE < 8192 this function will flip the page offset
 781 * so the second half of page assigned to Rx buffer will be used, otherwise
 782 * the offset is moved by "size" bytes
 783 */
 784static void
 785ice_rx_buf_adjust_pg_offset(struct ice_rx_buf *rx_buf, unsigned int size)
 786{
 787#if (PAGE_SIZE < 8192)
 788	/* flip page offset to other buffer */
 789	rx_buf->page_offset ^= size;
 790#else
 791	/* move offset up to the next cache line */
 792	rx_buf->page_offset += size;
 793#endif
 794}
 795
 796/**
 797 * ice_can_reuse_rx_page - Determine if page can be reused for another Rx
 798 * @rx_buf: buffer containing the page
 799 *
 800 * If page is reusable, we have a green light for calling ice_reuse_rx_page,
 801 * which will assign the current buffer to the buffer that next_to_alloc is
 802 * pointing to; otherwise, the DMA mapping needs to be destroyed and
 803 * page freed
 804 */
 805static bool
 806ice_can_reuse_rx_page(struct ice_rx_buf *rx_buf)
 807{
 
 
 
 808	unsigned int pagecnt_bias = rx_buf->pagecnt_bias;
 809	struct page *page = rx_buf->page;
 810
 811	/* avoid re-using remote and pfmemalloc pages */
 812	if (!dev_page_is_reusable(page))
 813		return false;
 814
 
 815	/* if we are only owner of page we can reuse it */
 816	if (unlikely(rx_buf->pgcnt - pagecnt_bias > 1))
 817		return false;
 818#if (PAGE_SIZE >= 8192)
 819#define ICE_LAST_OFFSET \
 820	(SKB_WITH_OVERHEAD(PAGE_SIZE) - ICE_RXBUF_3072)
 821	if (rx_buf->page_offset > ICE_LAST_OFFSET)
 822		return false;
 823#endif /* PAGE_SIZE >= 8192) */
 824
 825	/* If we have drained the page fragment pool we need to update
 826	 * the pagecnt_bias and page count so that we fully restock the
 827	 * number of references the driver holds.
 828	 */
 829	if (unlikely(pagecnt_bias == 1)) {
 830		page_ref_add(page, USHRT_MAX - 1);
 831		rx_buf->pagecnt_bias = USHRT_MAX;
 832	}
 833
 834	return true;
 835}
 836
 837/**
 838 * ice_add_xdp_frag - Add contents of Rx buffer to xdp buf as a frag
 839 * @rx_ring: Rx descriptor ring to transact packets on
 840 * @xdp: xdp buff to place the data into
 841 * @rx_buf: buffer containing page to add
 
 842 * @size: packet length from rx_desc
 843 *
 844 * This function will add the data contained in rx_buf->page to the xdp buf.
 845 * It will just attach the page as a frag.
 
 846 */
 847static int
 848ice_add_xdp_frag(struct ice_rx_ring *rx_ring, struct xdp_buff *xdp,
 849		 struct ice_rx_buf *rx_buf, const unsigned int size)
 850{
 851	struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp);
 
 
 
 
 852
 853	if (!size)
 854		return 0;
 855
 856	if (!xdp_buff_has_frags(xdp)) {
 857		sinfo->nr_frags = 0;
 858		sinfo->xdp_frags_size = 0;
 859		xdp_buff_set_frags_flag(xdp);
 860	}
 861
 862	if (unlikely(sinfo->nr_frags == MAX_SKB_FRAGS))
 863		return -ENOMEM;
 864
 865	__skb_fill_page_desc_noacc(sinfo, sinfo->nr_frags++, rx_buf->page,
 866				   rx_buf->page_offset, size);
 867	sinfo->xdp_frags_size += size;
 868	/* remember frag count before XDP prog execution; bpf_xdp_adjust_tail()
 869	 * can pop off frags but driver has to handle it on its own
 870	 */
 871	rx_ring->nr_frags = sinfo->nr_frags;
 872
 873	if (page_is_pfmemalloc(rx_buf->page))
 874		xdp_buff_set_frag_pfmemalloc(xdp);
 875
 876	return 0;
 
 877}
 878
 879/**
 880 * ice_reuse_rx_page - page flip buffer and store it back on the ring
 881 * @rx_ring: Rx descriptor ring to store buffers on
 882 * @old_buf: donor buffer to have page reused
 883 *
 884 * Synchronizes page for reuse by the adapter
 885 */
 886static void
 887ice_reuse_rx_page(struct ice_rx_ring *rx_ring, struct ice_rx_buf *old_buf)
 888{
 889	u16 nta = rx_ring->next_to_alloc;
 890	struct ice_rx_buf *new_buf;
 891
 892	new_buf = &rx_ring->rx_buf[nta];
 893
 894	/* update, and store next to alloc */
 895	nta++;
 896	rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
 897
 898	/* Transfer page from old buffer to new buffer.
 899	 * Move each member individually to avoid possible store
 900	 * forwarding stalls and unnecessary copy of skb.
 901	 */
 902	new_buf->dma = old_buf->dma;
 903	new_buf->page = old_buf->page;
 904	new_buf->page_offset = old_buf->page_offset;
 905	new_buf->pagecnt_bias = old_buf->pagecnt_bias;
 906}
 907
 908/**
 909 * ice_get_rx_buf - Fetch Rx buffer and synchronize data for use
 910 * @rx_ring: Rx descriptor ring to transact packets on
 
 911 * @size: size of buffer to add to skb
 912 * @ntc: index of next to clean element
 913 *
 914 * This function will pull an Rx buffer from the ring and synchronize it
 915 * for use by the CPU.
 916 */
 917static struct ice_rx_buf *
 918ice_get_rx_buf(struct ice_rx_ring *rx_ring, const unsigned int size,
 919	       const unsigned int ntc)
 920{
 921	struct ice_rx_buf *rx_buf;
 922
 923	rx_buf = &rx_ring->rx_buf[ntc];
 924	prefetchw(rx_buf->page);
 
 925
 926	if (!size)
 927		return rx_buf;
 928	/* we are reusing so sync this buffer for CPU use */
 929	dma_sync_single_range_for_cpu(rx_ring->dev, rx_buf->dma,
 930				      rx_buf->page_offset, size,
 931				      DMA_FROM_DEVICE);
 932
 933	/* We have pulled a buffer for use, so decrement pagecnt_bias */
 934	rx_buf->pagecnt_bias--;
 935
 936	return rx_buf;
 937}
 938
 939/**
 940 * ice_get_pgcnts - grab page_count() for gathered fragments
 941 * @rx_ring: Rx descriptor ring to store the page counts on
 942 *
 943 * This function is intended to be called right before running XDP
 944 * program so that the page recycling mechanism will be able to take
 945 * a correct decision regarding underlying pages; this is done in such
 946 * way as XDP program can change the refcount of page
 947 */
 948static void ice_get_pgcnts(struct ice_rx_ring *rx_ring)
 949{
 950	u32 nr_frags = rx_ring->nr_frags + 1;
 951	u32 idx = rx_ring->first_desc;
 952	struct ice_rx_buf *rx_buf;
 953	u32 cnt = rx_ring->count;
 954
 955	for (int i = 0; i < nr_frags; i++) {
 956		rx_buf = &rx_ring->rx_buf[idx];
 957		rx_buf->pgcnt = page_count(rx_buf->page);
 958
 959		if (++idx == cnt)
 960			idx = 0;
 961	}
 962}
 963
 964/**
 965 * ice_build_skb - Build skb around an existing buffer
 966 * @rx_ring: Rx descriptor ring to transact packets on
 967 * @xdp: xdp_buff pointing to the data
 968 *
 969 * This function builds an skb around an existing XDP buffer, taking care
 970 * to set up the skb correctly and avoid any memcpy overhead. Driver has
 971 * already combined frags (if any) to skb_shared_info.
 972 */
 973static struct sk_buff *
 974ice_build_skb(struct ice_rx_ring *rx_ring, struct xdp_buff *xdp)
 975{
 976	u8 metasize = xdp->data - xdp->data_meta;
 977	struct skb_shared_info *sinfo = NULL;
 978	unsigned int nr_frags;
 979	struct sk_buff *skb;
 980
 981	if (unlikely(xdp_buff_has_frags(xdp))) {
 982		sinfo = xdp_get_shared_info_from_buff(xdp);
 983		nr_frags = sinfo->nr_frags;
 984	}
 985
 986	/* Prefetch first cache line of first page. If xdp->data_meta
 987	 * is unused, this points exactly as xdp->data, otherwise we
 988	 * likely have a consumer accessing first few bytes of meta
 989	 * data, and then actual data.
 990	 */
 991	net_prefetch(xdp->data_meta);
 992	/* build an skb around the page buffer */
 993	skb = napi_build_skb(xdp->data_hard_start, xdp->frame_sz);
 994	if (unlikely(!skb))
 995		return NULL;
 996
 997	/* must to record Rx queue, otherwise OS features such as
 998	 * symmetric queue won't work
 999	 */
1000	skb_record_rx_queue(skb, rx_ring->q_index);
1001
1002	/* update pointers within the skb to store the data */
1003	skb_reserve(skb, xdp->data - xdp->data_hard_start);
1004	__skb_put(skb, xdp->data_end - xdp->data);
1005	if (metasize)
1006		skb_metadata_set(skb, metasize);
1007
1008	if (unlikely(xdp_buff_has_frags(xdp)))
1009		xdp_update_skb_shared_info(skb, nr_frags,
1010					   sinfo->xdp_frags_size,
1011					   nr_frags * xdp->frame_sz,
1012					   xdp_buff_is_frag_pfmemalloc(xdp));
1013
1014	return skb;
1015}
1016
1017/**
1018 * ice_construct_skb - Allocate skb and populate it
1019 * @rx_ring: Rx descriptor ring to transact packets on
1020 * @xdp: xdp_buff pointing to the data
 
1021 *
1022 * This function allocates an skb. It then populates it with the page
1023 * data from the current receive descriptor, taking care to set up the
1024 * skb correctly.
1025 */
1026static struct sk_buff *
1027ice_construct_skb(struct ice_rx_ring *rx_ring, struct xdp_buff *xdp)
 
1028{
1029	unsigned int size = xdp->data_end - xdp->data;
1030	struct skb_shared_info *sinfo = NULL;
1031	struct ice_rx_buf *rx_buf;
1032	unsigned int nr_frags = 0;
1033	unsigned int headlen;
1034	struct sk_buff *skb;
1035
1036	/* prefetch first cache line of first page */
1037	net_prefetch(xdp->data);
1038
1039	if (unlikely(xdp_buff_has_frags(xdp))) {
1040		sinfo = xdp_get_shared_info_from_buff(xdp);
1041		nr_frags = sinfo->nr_frags;
1042	}
1043
1044	/* allocate a skb to store the frags */
1045	skb = napi_alloc_skb(&rx_ring->q_vector->napi, ICE_RX_HDR_SIZE);
 
1046	if (unlikely(!skb))
1047		return NULL;
1048
1049	rx_buf = &rx_ring->rx_buf[rx_ring->first_desc];
1050	skb_record_rx_queue(skb, rx_ring->q_index);
1051	/* Determine available headroom for copy */
1052	headlen = size;
1053	if (headlen > ICE_RX_HDR_SIZE)
1054		headlen = eth_get_headlen(skb->dev, xdp->data, ICE_RX_HDR_SIZE);
1055
1056	/* align pull length to size of long to optimize memcpy performance */
1057	memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen,
1058							 sizeof(long)));
1059
1060	/* if we exhaust the linear part then add what is left as a frag */
1061	size -= headlen;
1062	if (size) {
1063		/* besides adding here a partial frag, we are going to add
1064		 * frags from xdp_buff, make sure there is enough space for
1065		 * them
1066		 */
1067		if (unlikely(nr_frags >= MAX_SKB_FRAGS - 1)) {
1068			dev_kfree_skb(skb);
1069			return NULL;
1070		}
1071		skb_add_rx_frag(skb, 0, rx_buf->page,
1072				rx_buf->page_offset + headlen, size,
1073				xdp->frame_sz);
 
1074	} else {
1075		/* buffer is unused, restore biased page count in Rx buffer;
1076		 * data was copied onto skb's linear part so there's no
1077		 * need for adjusting page offset and we can reuse this buffer
1078		 * as-is
1079		 */
1080		rx_buf->pagecnt_bias++;
1081	}
1082
1083	if (unlikely(xdp_buff_has_frags(xdp))) {
1084		struct skb_shared_info *skinfo = skb_shinfo(skb);
1085
1086		memcpy(&skinfo->frags[skinfo->nr_frags], &sinfo->frags[0],
1087		       sizeof(skb_frag_t) * nr_frags);
1088
1089		xdp_update_skb_shared_info(skb, skinfo->nr_frags + nr_frags,
1090					   sinfo->xdp_frags_size,
1091					   nr_frags * xdp->frame_sz,
1092					   xdp_buff_is_frag_pfmemalloc(xdp));
1093	}
1094
1095	return skb;
1096}
1097
1098/**
1099 * ice_put_rx_buf - Clean up used buffer and either recycle or free
1100 * @rx_ring: Rx descriptor ring to transact packets on
1101 * @rx_buf: Rx buffer to pull data from
1102 *
1103 * This function will clean up the contents of the rx_buf. It will either
1104 * recycle the buffer or unmap it and free the associated resources.
1105 */
1106static void
1107ice_put_rx_buf(struct ice_rx_ring *rx_ring, struct ice_rx_buf *rx_buf)
1108{
1109	if (!rx_buf)
1110		return;
1111
1112	if (ice_can_reuse_rx_page(rx_buf)) {
1113		/* hand second half of page back to the ring */
1114		ice_reuse_rx_page(rx_ring, rx_buf);
 
1115	} else {
1116		/* we are not reusing the buffer so unmap it */
1117		dma_unmap_page_attrs(rx_ring->dev, rx_buf->dma,
1118				     ice_rx_pg_size(rx_ring), DMA_FROM_DEVICE,
1119				     ICE_RX_DMA_ATTR);
1120		__page_frag_cache_drain(rx_buf->page, rx_buf->pagecnt_bias);
1121	}
1122
1123	/* clear contents of buffer_info */
1124	rx_buf->page = NULL;
 
1125}
1126
1127/**
1128 * ice_put_rx_mbuf - ice_put_rx_buf() caller, for all frame frags
1129 * @rx_ring: Rx ring with all the auxiliary data
1130 * @xdp: XDP buffer carrying linear + frags part
1131 * @xdp_xmit: XDP_TX/XDP_REDIRECT verdict storage
1132 * @ntc: a current next_to_clean value to be stored at rx_ring
1133 * @verdict: return code from XDP program execution
1134 *
1135 * Walk through gathered fragments and satisfy internal page
1136 * recycle mechanism; we take here an action related to verdict
1137 * returned by XDP program;
1138 */
1139static void ice_put_rx_mbuf(struct ice_rx_ring *rx_ring, struct xdp_buff *xdp,
1140			    u32 *xdp_xmit, u32 ntc, u32 verdict)
1141{
1142	u32 nr_frags = rx_ring->nr_frags + 1;
1143	u32 idx = rx_ring->first_desc;
1144	u32 cnt = rx_ring->count;
1145	u32 post_xdp_frags = 1;
1146	struct ice_rx_buf *buf;
1147	int i;
1148
1149	if (unlikely(xdp_buff_has_frags(xdp)))
1150		post_xdp_frags += xdp_get_shared_info_from_buff(xdp)->nr_frags;
1151
1152	for (i = 0; i < post_xdp_frags; i++) {
1153		buf = &rx_ring->rx_buf[idx];
1154
1155		if (verdict & (ICE_XDP_TX | ICE_XDP_REDIR)) {
1156			ice_rx_buf_adjust_pg_offset(buf, xdp->frame_sz);
1157			*xdp_xmit |= verdict;
1158		} else if (verdict & ICE_XDP_CONSUMED) {
1159			buf->pagecnt_bias++;
1160		} else if (verdict == ICE_XDP_PASS) {
1161			ice_rx_buf_adjust_pg_offset(buf, xdp->frame_sz);
1162		}
1163
1164		ice_put_rx_buf(rx_ring, buf);
 
1165
1166		if (++idx == cnt)
1167			idx = 0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1168	}
1169	/* handle buffers that represented frags released by XDP prog;
1170	 * for these we keep pagecnt_bias as-is; refcount from struct page
1171	 * has been decremented within XDP prog and we do not have to increase
1172	 * the biased refcnt
1173	 */
1174	for (; i < nr_frags; i++) {
1175		buf = &rx_ring->rx_buf[idx];
1176		ice_put_rx_buf(rx_ring, buf);
1177		if (++idx == cnt)
1178			idx = 0;
1179	}
1180
1181	xdp->data = NULL;
1182	rx_ring->first_desc = ntc;
1183	rx_ring->nr_frags = 0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1184}
1185
1186/**
1187 * ice_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1188 * @rx_ring: Rx descriptor ring to transact packets on
1189 * @budget: Total limit on number of packets to process
1190 *
1191 * This function provides a "bounce buffer" approach to Rx interrupt
1192 * processing. The advantage to this is that on systems that have
1193 * expensive overhead for IOMMU access this provides a means of avoiding
1194 * it by maintaining the mapping of the page to the system.
1195 *
1196 * Returns amount of work completed
1197 */
1198int ice_clean_rx_irq(struct ice_rx_ring *rx_ring, int budget)
1199{
1200	unsigned int total_rx_bytes = 0, total_rx_pkts = 0;
1201	unsigned int offset = rx_ring->rx_offset;
1202	struct xdp_buff *xdp = &rx_ring->xdp;
1203	struct ice_tx_ring *xdp_ring = NULL;
1204	struct bpf_prog *xdp_prog = NULL;
1205	u32 ntc = rx_ring->next_to_clean;
1206	u32 cached_ntu, xdp_verdict;
1207	u32 cnt = rx_ring->count;
1208	u32 xdp_xmit = 0;
1209	bool failure;
1210
1211	xdp_prog = READ_ONCE(rx_ring->xdp_prog);
1212	if (xdp_prog) {
1213		xdp_ring = rx_ring->xdp_ring;
1214		cached_ntu = xdp_ring->next_to_use;
1215	}
1216
1217	/* start the loop to process Rx packets bounded by 'budget' */
1218	while (likely(total_rx_pkts < (unsigned int)budget)) {
1219		union ice_32b_rx_flex_desc *rx_desc;
1220		struct ice_rx_buf *rx_buf;
1221		struct sk_buff *skb;
1222		unsigned int size;
1223		u16 stat_err_bits;
1224		u16 vlan_tci;
 
1225
1226		/* get the Rx desc from Rx ring based on 'next_to_clean' */
1227		rx_desc = ICE_RX_DESC(rx_ring, ntc);
1228
1229		/* status_error_len will always be zero for unused descriptors
1230		 * because it's cleared in cleanup, and overlaps with hdr_addr
1231		 * which is always zero because packet split isn't used, if the
1232		 * hardware wrote DD then it will be non-zero
1233		 */
1234		stat_err_bits = BIT(ICE_RX_FLEX_DESC_STATUS0_DD_S);
1235		if (!ice_test_staterr(rx_desc->wb.status_error0, stat_err_bits))
1236			break;
1237
1238		/* This memory barrier is needed to keep us from reading
1239		 * any other fields out of the rx_desc until we know the
1240		 * DD bit is set.
1241		 */
1242		dma_rmb();
1243
1244		ice_trace(clean_rx_irq, rx_ring, rx_desc);
1245		if (rx_desc->wb.rxdid == FDIR_DESC_RXDID || !rx_ring->netdev) {
1246			struct ice_vsi *ctrl_vsi = rx_ring->vsi;
1247
1248			if (rx_desc->wb.rxdid == FDIR_DESC_RXDID &&
1249			    ctrl_vsi->vf)
1250				ice_vc_fdir_irq_handler(ctrl_vsi, rx_desc);
1251			if (++ntc == cnt)
1252				ntc = 0;
1253			rx_ring->first_desc = ntc;
1254			continue;
1255		}
1256
1257		size = le16_to_cpu(rx_desc->wb.pkt_len) &
1258			ICE_RX_FLX_DESC_PKT_LEN_M;
1259
1260		/* retrieve a buffer from the ring */
1261		rx_buf = ice_get_rx_buf(rx_ring, size, ntc);
1262
1263		if (!xdp->data) {
1264			void *hard_start;
 
 
1265
1266			hard_start = page_address(rx_buf->page) + rx_buf->page_offset -
1267				     offset;
1268			xdp_prepare_buff(xdp, hard_start, offset, size, !!offset);
1269			xdp_buff_clear_frags_flag(xdp);
1270		} else if (ice_add_xdp_frag(rx_ring, xdp, rx_buf, size)) {
1271			ice_put_rx_mbuf(rx_ring, xdp, NULL, ntc, ICE_XDP_CONSUMED);
1272			break;
1273		}
1274		if (++ntc == cnt)
1275			ntc = 0;
 
1276
1277		/* skip if it is NOP desc */
1278		if (ice_is_non_eop(rx_ring, rx_desc))
1279			continue;
1280
1281		ice_get_pgcnts(rx_ring);
1282		xdp_verdict = ice_run_xdp(rx_ring, xdp, xdp_prog, xdp_ring, rx_desc);
1283		if (xdp_verdict == ICE_XDP_PASS)
1284			goto construct_skb;
1285		total_rx_bytes += xdp_get_buff_len(xdp);
1286		total_rx_pkts++;
1287
1288		ice_put_rx_mbuf(rx_ring, xdp, &xdp_xmit, ntc, xdp_verdict);
1289
1290		continue;
1291construct_skb:
1292		if (likely(ice_ring_uses_build_skb(rx_ring)))
1293			skb = ice_build_skb(rx_ring, xdp);
1294		else
1295			skb = ice_construct_skb(rx_ring, xdp);
1296		/* exit if we failed to retrieve a buffer */
1297		if (!skb) {
1298			rx_ring->ring_stats->rx_stats.alloc_page_failed++;
1299			xdp_verdict = ICE_XDP_CONSUMED;
1300		}
1301		ice_put_rx_mbuf(rx_ring, xdp, &xdp_xmit, ntc, xdp_verdict);
1302
1303		if (!skb)
1304			break;
1305
1306		stat_err_bits = BIT(ICE_RX_FLEX_DESC_STATUS0_RXE_S);
1307		if (unlikely(ice_test_staterr(rx_desc->wb.status_error0,
1308					      stat_err_bits))) {
1309			dev_kfree_skb_any(skb);
1310			continue;
1311		}
1312
1313		vlan_tci = ice_get_vlan_tci(rx_desc);
 
 
1314
1315		/* pad the skb if needed, to make a valid ethernet frame */
1316		if (eth_skb_pad(skb))
 
 
 
1317			continue;
 
1318
1319		/* probably a little skewed due to removing CRC */
1320		total_rx_bytes += skb->len;
1321
1322		/* populate checksum, VLAN, and protocol */
1323		ice_process_skb_fields(rx_ring, rx_desc, skb);
 
 
 
1324
1325		ice_trace(clean_rx_irq_indicate, rx_ring, rx_desc, skb);
1326		/* send completed skb up the stack */
1327		ice_receive_skb(rx_ring, skb, vlan_tci);
1328
1329		/* update budget accounting */
1330		total_rx_pkts++;
1331	}
1332
1333	rx_ring->next_to_clean = ntc;
1334	/* return up to cleaned_count buffers to hardware */
1335	failure = ice_alloc_rx_bufs(rx_ring, ICE_RX_DESC_UNUSED(rx_ring));
1336
1337	if (xdp_xmit)
1338		ice_finalize_xdp_rx(xdp_ring, xdp_xmit, cached_ntu);
1339
1340	if (rx_ring->ring_stats)
1341		ice_update_rx_ring_stats(rx_ring, total_rx_pkts,
1342					 total_rx_bytes);
 
1343
1344	/* guarantee a trip back through this routine if there was a failure */
1345	return failure ? budget : (int)total_rx_pkts;
1346}
1347
1348static void __ice_update_sample(struct ice_q_vector *q_vector,
1349				struct ice_ring_container *rc,
1350				struct dim_sample *sample,
1351				bool is_tx)
1352{
1353	u64 packets = 0, bytes = 0;
1354
1355	if (is_tx) {
1356		struct ice_tx_ring *tx_ring;
1357
1358		ice_for_each_tx_ring(tx_ring, *rc) {
1359			struct ice_ring_stats *ring_stats;
1360
1361			ring_stats = tx_ring->ring_stats;
1362			if (!ring_stats)
1363				continue;
1364			packets += ring_stats->stats.pkts;
1365			bytes += ring_stats->stats.bytes;
1366		}
1367	} else {
1368		struct ice_rx_ring *rx_ring;
1369
1370		ice_for_each_rx_ring(rx_ring, *rc) {
1371			struct ice_ring_stats *ring_stats;
1372
1373			ring_stats = rx_ring->ring_stats;
1374			if (!ring_stats)
1375				continue;
1376			packets += ring_stats->stats.pkts;
1377			bytes += ring_stats->stats.bytes;
1378		}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1379	}
1380
1381	dim_update_sample(q_vector->total_events, packets, bytes, sample);
1382	sample->comp_ctr = 0;
 
 
1383
1384	/* if dim settings get stale, like when not updated for 1
1385	 * second or longer, force it to start again. This addresses the
1386	 * frequent case of an idle queue being switched to by the
1387	 * scheduler. The 1,000 here means 1,000 milliseconds.
1388	 */
1389	if (ktime_ms_delta(sample->time, rc->dim.start_sample.time) >= 1000)
1390		rc->dim.state = DIM_START_MEASURE;
1391}
1392
1393/**
1394 * ice_net_dim - Update net DIM algorithm
1395 * @q_vector: the vector associated with the interrupt
1396 *
1397 * Create a DIM sample and notify net_dim() so that it can possibly decide
1398 * a new ITR value based on incoming packets, bytes, and interrupts.
1399 *
1400 * This function is a no-op if the ring is not configured to dynamic ITR.
 
 
 
 
 
 
1401 */
1402static void ice_net_dim(struct ice_q_vector *q_vector)
 
1403{
1404	struct ice_ring_container *tx = &q_vector->tx;
1405	struct ice_ring_container *rx = &q_vector->rx;
 
1406
1407	if (ITR_IS_DYNAMIC(tx)) {
1408		struct dim_sample dim_sample;
1409
1410		__ice_update_sample(q_vector, tx, &dim_sample, true);
1411		net_dim(&tx->dim, &dim_sample);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1412	}
1413
1414	if (ITR_IS_DYNAMIC(rx)) {
1415		struct dim_sample dim_sample;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1416
1417		__ice_update_sample(q_vector, rx, &dim_sample, false);
1418		net_dim(&rx->dim, &dim_sample);
1419	}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1420}
1421
1422/**
1423 * ice_buildreg_itr - build value for writing to the GLINT_DYN_CTL register
1424 * @itr_idx: interrupt throttling index
1425 * @itr: interrupt throttling value in usecs
1426 */
1427static u32 ice_buildreg_itr(u16 itr_idx, u16 itr)
1428{
1429	/* The ITR value is reported in microseconds, and the register value is
1430	 * recorded in 2 microsecond units. For this reason we only need to
1431	 * shift by the GLINT_DYN_CTL_INTERVAL_S - ICE_ITR_GRAN_S to apply this
1432	 * granularity as a shift instead of division. The mask makes sure the
1433	 * ITR value is never odd so we don't accidentally write into the field
1434	 * prior to the ITR field.
1435	 */
1436	itr &= ICE_ITR_MASK;
1437
1438	return GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
1439		(itr_idx << GLINT_DYN_CTL_ITR_INDX_S) |
1440		(itr << (GLINT_DYN_CTL_INTERVAL_S - ICE_ITR_GRAN_S));
1441}
1442
 
 
 
 
 
 
 
 
 
1443/**
1444 * ice_enable_interrupt - re-enable MSI-X interrupt
1445 * @q_vector: the vector associated with the interrupt to enable
1446 *
1447 * If the VSI is down, the interrupt will not be re-enabled. Also,
1448 * when enabling the interrupt always reset the wb_on_itr to false
1449 * and trigger a software interrupt to clean out internal state.
1450 */
1451static void ice_enable_interrupt(struct ice_q_vector *q_vector)
1452{
 
 
1453	struct ice_vsi *vsi = q_vector->vsi;
1454	bool wb_en = q_vector->wb_on_itr;
1455	u32 itr_val;
1456
1457	if (test_bit(ICE_DOWN, vsi->state))
 
 
 
 
 
 
 
 
 
 
 
 
 
1458		return;
 
1459
1460	/* trigger an ITR delayed software interrupt when exiting busy poll, to
1461	 * make sure to catch any pending cleanups that might have been missed
1462	 * due to interrupt state transition. If busy poll or poll isn't
1463	 * enabled, then don't update ITR, and just enable the interrupt.
1464	 */
1465	if (!wb_en) {
1466		itr_val = ice_buildreg_itr(ICE_ITR_NONE, 0);
1467	} else {
1468		q_vector->wb_on_itr = false;
1469
1470		/* do two things here with a single write. Set up the third ITR
1471		 * index to be used for software interrupt moderation, and then
1472		 * trigger a software interrupt with a rate limit of 20K on
1473		 * software interrupts, this will help avoid high interrupt
1474		 * loads due to frequently polling and exiting polling.
 
 
 
 
 
 
 
1475		 */
1476		itr_val = ice_buildreg_itr(ICE_IDX_ITR2, ICE_ITR_20K);
1477		itr_val |= GLINT_DYN_CTL_SWINT_TRIG_M |
1478			   ICE_IDX_ITR2 << GLINT_DYN_CTL_SW_ITR_INDX_S |
1479			   GLINT_DYN_CTL_SW_ITR_INDX_ENA_M;
 
 
 
 
 
 
 
 
 
1480	}
1481	wr32(&vsi->back->hw, GLINT_DYN_CTL(q_vector->reg_idx), itr_val);
 
 
 
 
1482}
1483
1484/**
1485 * ice_set_wb_on_itr - set WB_ON_ITR for this q_vector
1486 * @q_vector: q_vector to set WB_ON_ITR on
1487 *
1488 * We need to tell hardware to write-back completed descriptors even when
1489 * interrupts are disabled. Descriptors will be written back on cache line
1490 * boundaries without WB_ON_ITR enabled, but if we don't enable WB_ON_ITR
1491 * descriptors may not be written back if they don't fill a cache line until
1492 * the next interrupt.
1493 *
1494 * This sets the write-back frequency to whatever was set previously for the
1495 * ITR indices. Also, set the INTENA_MSK bit to make sure hardware knows we
1496 * aren't meddling with the INTENA_M bit.
1497 */
1498static void ice_set_wb_on_itr(struct ice_q_vector *q_vector)
1499{
1500	struct ice_vsi *vsi = q_vector->vsi;
1501
1502	/* already in wb_on_itr mode no need to change it */
1503	if (q_vector->wb_on_itr)
1504		return;
1505
1506	/* use previously set ITR values for all of the ITR indices by
1507	 * specifying ICE_ITR_NONE, which will vary in adaptive (AIM) mode and
1508	 * be static in non-adaptive mode (user configured)
1509	 */
1510	wr32(&vsi->back->hw, GLINT_DYN_CTL(q_vector->reg_idx),
1511	     FIELD_PREP(GLINT_DYN_CTL_ITR_INDX_M, ICE_ITR_NONE) |
1512	     FIELD_PREP(GLINT_DYN_CTL_INTENA_MSK_M, 1) |
1513	     FIELD_PREP(GLINT_DYN_CTL_WB_ON_ITR_M, 1));
 
1514
1515	q_vector->wb_on_itr = true;
1516}
1517
1518/**
1519 * ice_napi_poll - NAPI polling Rx/Tx cleanup routine
1520 * @napi: napi struct with our devices info in it
1521 * @budget: amount of work driver is allowed to do this pass, in packets
1522 *
1523 * This function will clean all queues associated with a q_vector.
1524 *
1525 * Returns the amount of work done
1526 */
1527int ice_napi_poll(struct napi_struct *napi, int budget)
1528{
1529	struct ice_q_vector *q_vector =
1530				container_of(napi, struct ice_q_vector, napi);
1531	struct ice_tx_ring *tx_ring;
1532	struct ice_rx_ring *rx_ring;
1533	bool clean_complete = true;
 
1534	int budget_per_ring;
1535	int work_done = 0;
1536
1537	/* Since the actual Tx work is minimal, we can give the Tx a larger
1538	 * budget and be more aggressive about cleaning up the Tx descriptors.
1539	 */
1540	ice_for_each_tx_ring(tx_ring, q_vector->tx) {
1541		struct xsk_buff_pool *xsk_pool = READ_ONCE(tx_ring->xsk_pool);
1542		bool wd;
1543
1544		if (xsk_pool)
1545			wd = ice_xmit_zc(tx_ring, xsk_pool);
1546		else if (ice_ring_is_xdp(tx_ring))
1547			wd = true;
1548		else
1549			wd = ice_clean_tx_irq(tx_ring, budget);
1550
1551		if (!wd)
1552			clean_complete = false;
1553	}
1554
1555	/* Handle case where we are called by netpoll with a budget of 0 */
1556	if (unlikely(budget <= 0))
1557		return budget;
1558
1559	/* normally we have 1 Rx ring per q_vector */
1560	if (unlikely(q_vector->num_ring_rx > 1))
1561		/* We attempt to distribute budget to each Rx queue fairly, but
1562		 * don't allow the budget to go below 1 because that would exit
1563		 * polling early.
1564		 */
1565		budget_per_ring = max_t(int, budget / q_vector->num_ring_rx, 1);
1566	else
1567		/* Max of 1 Rx ring in this q_vector so give it the budget */
1568		budget_per_ring = budget;
1569
1570	ice_for_each_rx_ring(rx_ring, q_vector->rx) {
1571		struct xsk_buff_pool *xsk_pool = READ_ONCE(rx_ring->xsk_pool);
1572		int cleaned;
1573
1574		/* A dedicated path for zero-copy allows making a single
1575		 * comparison in the irq context instead of many inside the
1576		 * ice_clean_rx_irq function and makes the codebase cleaner.
1577		 */
1578		cleaned = rx_ring->xsk_pool ?
1579			  ice_clean_rx_irq_zc(rx_ring, xsk_pool, budget_per_ring) :
1580			  ice_clean_rx_irq(rx_ring, budget_per_ring);
1581		work_done += cleaned;
1582		/* if we clean as many as budgeted, we must not be done */
1583		if (cleaned >= budget_per_ring)
1584			clean_complete = false;
1585	}
1586
1587	/* If work not completed, return budget and polling will return */
1588	if (!clean_complete) {
1589		/* Set the writeback on ITR so partial completions of
1590		 * cache-lines will still continue even if we're polling.
1591		 */
1592		ice_set_wb_on_itr(q_vector);
1593		return budget;
1594	}
1595
1596	/* Exit the polling mode, but don't re-enable interrupts if stack might
1597	 * poll us due to busy-polling
1598	 */
1599	if (napi_complete_done(napi, work_done)) {
1600		ice_net_dim(q_vector);
1601		ice_enable_interrupt(q_vector);
1602	} else {
1603		ice_set_wb_on_itr(q_vector);
1604	}
1605
1606	return min_t(int, work_done, budget - 1);
1607}
1608
 
 
 
 
 
 
 
 
 
 
 
1609/**
1610 * __ice_maybe_stop_tx - 2nd level check for Tx stop conditions
1611 * @tx_ring: the ring to be checked
1612 * @size: the size buffer we want to assure is available
1613 *
1614 * Returns -EBUSY if a stop is needed, else 0
1615 */
1616static int __ice_maybe_stop_tx(struct ice_tx_ring *tx_ring, unsigned int size)
1617{
1618	netif_tx_stop_queue(txring_txq(tx_ring));
1619	/* Memory barrier before checking head and tail */
1620	smp_mb();
1621
1622	/* Check again in a case another CPU has just made room available. */
1623	if (likely(ICE_DESC_UNUSED(tx_ring) < size))
1624		return -EBUSY;
1625
1626	/* A reprieve! - use start_queue because it doesn't call schedule */
1627	netif_tx_start_queue(txring_txq(tx_ring));
1628	++tx_ring->ring_stats->tx_stats.restart_q;
1629	return 0;
1630}
1631
1632/**
1633 * ice_maybe_stop_tx - 1st level check for Tx stop conditions
1634 * @tx_ring: the ring to be checked
1635 * @size:    the size buffer we want to assure is available
1636 *
1637 * Returns 0 if stop is not needed
1638 */
1639static int ice_maybe_stop_tx(struct ice_tx_ring *tx_ring, unsigned int size)
1640{
1641	if (likely(ICE_DESC_UNUSED(tx_ring) >= size))
1642		return 0;
1643
1644	return __ice_maybe_stop_tx(tx_ring, size);
1645}
1646
1647/**
1648 * ice_tx_map - Build the Tx descriptor
1649 * @tx_ring: ring to send buffer on
1650 * @first: first buffer info buffer to use
1651 * @off: pointer to struct that holds offload parameters
1652 *
1653 * This function loops over the skb data pointed to by *first
1654 * and gets a physical address for each memory location and programs
1655 * it and the length into the transmit descriptor.
1656 */
1657static void
1658ice_tx_map(struct ice_tx_ring *tx_ring, struct ice_tx_buf *first,
1659	   struct ice_tx_offload_params *off)
1660{
1661	u64 td_offset, td_tag, td_cmd;
1662	u16 i = tx_ring->next_to_use;
 
1663	unsigned int data_len, size;
1664	struct ice_tx_desc *tx_desc;
1665	struct ice_tx_buf *tx_buf;
1666	struct sk_buff *skb;
1667	skb_frag_t *frag;
1668	dma_addr_t dma;
1669	bool kick;
1670
1671	td_tag = off->td_l2tag1;
1672	td_cmd = off->td_cmd;
1673	td_offset = off->td_offset;
1674	skb = first->skb;
1675
1676	data_len = skb->data_len;
1677	size = skb_headlen(skb);
1678
1679	tx_desc = ICE_TX_DESC(tx_ring, i);
1680
1681	if (first->tx_flags & ICE_TX_FLAGS_HW_VLAN) {
1682		td_cmd |= (u64)ICE_TX_DESC_CMD_IL2TAG1;
1683		td_tag = first->vid;
 
1684	}
1685
1686	dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1687
1688	tx_buf = first;
1689
1690	for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1691		unsigned int max_data = ICE_MAX_DATA_PER_TXD_ALIGNED;
1692
1693		if (dma_mapping_error(tx_ring->dev, dma))
1694			goto dma_error;
1695
1696		/* record length, and DMA address */
1697		dma_unmap_len_set(tx_buf, len, size);
1698		dma_unmap_addr_set(tx_buf, dma, dma);
1699
1700		/* align size to end of page */
1701		max_data += -dma & (ICE_MAX_READ_REQ_SIZE - 1);
1702		tx_desc->buf_addr = cpu_to_le64(dma);
1703
1704		/* account for data chunks larger than the hardware
1705		 * can handle
1706		 */
1707		while (unlikely(size > ICE_MAX_DATA_PER_TXD)) {
1708			tx_desc->cmd_type_offset_bsz =
1709				ice_build_ctob(td_cmd, td_offset, max_data,
1710					       td_tag);
1711
1712			tx_desc++;
1713			i++;
1714
1715			if (i == tx_ring->count) {
1716				tx_desc = ICE_TX_DESC(tx_ring, 0);
1717				i = 0;
1718			}
1719
1720			dma += max_data;
1721			size -= max_data;
1722
1723			max_data = ICE_MAX_DATA_PER_TXD_ALIGNED;
1724			tx_desc->buf_addr = cpu_to_le64(dma);
1725		}
1726
1727		if (likely(!data_len))
1728			break;
1729
1730		tx_desc->cmd_type_offset_bsz = ice_build_ctob(td_cmd, td_offset,
1731							      size, td_tag);
1732
1733		tx_desc++;
1734		i++;
1735
1736		if (i == tx_ring->count) {
1737			tx_desc = ICE_TX_DESC(tx_ring, 0);
1738			i = 0;
1739		}
1740
1741		size = skb_frag_size(frag);
1742		data_len -= size;
1743
1744		dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1745				       DMA_TO_DEVICE);
1746
1747		tx_buf = &tx_ring->tx_buf[i];
1748		tx_buf->type = ICE_TX_BUF_FRAG;
1749	}
1750
 
 
 
1751	/* record SW timestamp if HW timestamp is not available */
1752	skb_tx_timestamp(first->skb);
1753
1754	i++;
1755	if (i == tx_ring->count)
1756		i = 0;
1757
1758	/* write last descriptor with RS and EOP bits */
1759	td_cmd |= (u64)ICE_TXD_LAST_DESC_CMD;
1760	tx_desc->cmd_type_offset_bsz =
1761			ice_build_ctob(td_cmd, td_offset, size, td_tag);
1762
1763	/* Force memory writes to complete before letting h/w know there
1764	 * are new descriptors to fetch.
1765	 *
1766	 * We also use this memory barrier to make certain all of the
1767	 * status bits have been updated before next_to_watch is written.
1768	 */
1769	wmb();
1770
1771	/* set next_to_watch value indicating a packet is present */
1772	first->next_to_watch = tx_desc;
1773
1774	tx_ring->next_to_use = i;
1775
1776	ice_maybe_stop_tx(tx_ring, DESC_NEEDED);
1777
1778	/* notify HW of packet */
1779	kick = __netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount,
1780				      netdev_xmit_more());
1781	if (kick)
1782		/* notify HW of packet */
1783		writel(i, tx_ring->tail);
 
1784
1785	return;
1786
1787dma_error:
1788	/* clear DMA mappings for failed tx_buf map */
1789	for (;;) {
1790		tx_buf = &tx_ring->tx_buf[i];
1791		ice_unmap_and_free_tx_buf(tx_ring, tx_buf);
1792		if (tx_buf == first)
1793			break;
1794		if (i == 0)
1795			i = tx_ring->count;
1796		i--;
1797	}
1798
1799	tx_ring->next_to_use = i;
1800}
1801
1802/**
1803 * ice_tx_csum - Enable Tx checksum offloads
1804 * @first: pointer to the first descriptor
1805 * @off: pointer to struct that holds offload parameters
1806 *
1807 * Returns 0 or error (negative) if checksum offload can't happen, 1 otherwise.
1808 */
1809static
1810int ice_tx_csum(struct ice_tx_buf *first, struct ice_tx_offload_params *off)
1811{
1812	u32 l4_len = 0, l3_len = 0, l2_len = 0;
1813	struct sk_buff *skb = first->skb;
1814	union {
1815		struct iphdr *v4;
1816		struct ipv6hdr *v6;
1817		unsigned char *hdr;
1818	} ip;
1819	union {
1820		struct tcphdr *tcp;
1821		unsigned char *hdr;
1822	} l4;
1823	__be16 frag_off, protocol;
1824	unsigned char *exthdr;
1825	u32 offset, cmd = 0;
1826	u8 l4_proto = 0;
1827
1828	if (skb->ip_summed != CHECKSUM_PARTIAL)
1829		return 0;
1830
1831	protocol = vlan_get_protocol(skb);
1832
1833	if (eth_p_mpls(protocol)) {
1834		ip.hdr = skb_inner_network_header(skb);
1835		l4.hdr = skb_checksum_start(skb);
1836	} else {
1837		ip.hdr = skb_network_header(skb);
1838		l4.hdr = skb_transport_header(skb);
1839	}
1840
1841	/* compute outer L2 header size */
1842	l2_len = ip.hdr - skb->data;
1843	offset = (l2_len / 2) << ICE_TX_DESC_LEN_MACLEN_S;
1844
1845	/* set the tx_flags to indicate the IP protocol type. this is
1846	 * required so that checksum header computation below is accurate.
1847	 */
1848	if (ip.v4->version == 4)
1849		first->tx_flags |= ICE_TX_FLAGS_IPV4;
1850	else if (ip.v6->version == 6)
1851		first->tx_flags |= ICE_TX_FLAGS_IPV6;
1852
1853	if (skb->encapsulation) {
1854		bool gso_ena = false;
1855		u32 tunnel = 0;
1856
1857		/* define outer network header type */
1858		if (first->tx_flags & ICE_TX_FLAGS_IPV4) {
1859			tunnel |= (first->tx_flags & ICE_TX_FLAGS_TSO) ?
1860				  ICE_TX_CTX_EIPT_IPV4 :
1861				  ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
1862			l4_proto = ip.v4->protocol;
1863		} else if (first->tx_flags & ICE_TX_FLAGS_IPV6) {
1864			int ret;
1865
1866			tunnel |= ICE_TX_CTX_EIPT_IPV6;
1867			exthdr = ip.hdr + sizeof(*ip.v6);
1868			l4_proto = ip.v6->nexthdr;
1869			ret = ipv6_skip_exthdr(skb, exthdr - skb->data,
1870					       &l4_proto, &frag_off);
1871			if (ret < 0)
1872				return -1;
1873		}
1874
1875		/* define outer transport */
1876		switch (l4_proto) {
1877		case IPPROTO_UDP:
1878			tunnel |= ICE_TXD_CTX_UDP_TUNNELING;
1879			first->tx_flags |= ICE_TX_FLAGS_TUNNEL;
1880			break;
1881		case IPPROTO_GRE:
1882			tunnel |= ICE_TXD_CTX_GRE_TUNNELING;
1883			first->tx_flags |= ICE_TX_FLAGS_TUNNEL;
1884			break;
1885		case IPPROTO_IPIP:
1886		case IPPROTO_IPV6:
1887			first->tx_flags |= ICE_TX_FLAGS_TUNNEL;
1888			l4.hdr = skb_inner_network_header(skb);
1889			break;
1890		default:
1891			if (first->tx_flags & ICE_TX_FLAGS_TSO)
1892				return -1;
1893
1894			skb_checksum_help(skb);
1895			return 0;
1896		}
1897
1898		/* compute outer L3 header size */
1899		tunnel |= ((l4.hdr - ip.hdr) / 4) <<
1900			  ICE_TXD_CTX_QW0_EIPLEN_S;
1901
1902		/* switch IP header pointer from outer to inner header */
1903		ip.hdr = skb_inner_network_header(skb);
1904
1905		/* compute tunnel header size */
1906		tunnel |= ((ip.hdr - l4.hdr) / 2) <<
1907			   ICE_TXD_CTX_QW0_NATLEN_S;
1908
1909		gso_ena = skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL;
1910		/* indicate if we need to offload outer UDP header */
1911		if ((first->tx_flags & ICE_TX_FLAGS_TSO) && !gso_ena &&
1912		    (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM))
1913			tunnel |= ICE_TXD_CTX_QW0_L4T_CS_M;
1914
1915		/* record tunnel offload values */
1916		off->cd_tunnel_params |= tunnel;
1917
1918		/* set DTYP=1 to indicate that it's an Tx context descriptor
1919		 * in IPsec tunnel mode with Tx offloads in Quad word 1
1920		 */
1921		off->cd_qw1 |= (u64)ICE_TX_DESC_DTYPE_CTX;
1922
1923		/* switch L4 header pointer from outer to inner */
1924		l4.hdr = skb_inner_transport_header(skb);
1925		l4_proto = 0;
1926
1927		/* reset type as we transition from outer to inner headers */
1928		first->tx_flags &= ~(ICE_TX_FLAGS_IPV4 | ICE_TX_FLAGS_IPV6);
1929		if (ip.v4->version == 4)
1930			first->tx_flags |= ICE_TX_FLAGS_IPV4;
1931		if (ip.v6->version == 6)
1932			first->tx_flags |= ICE_TX_FLAGS_IPV6;
1933	}
1934
1935	/* Enable IP checksum offloads */
1936	if (first->tx_flags & ICE_TX_FLAGS_IPV4) {
 
1937		l4_proto = ip.v4->protocol;
1938		/* the stack computes the IP header already, the only time we
1939		 * need the hardware to recompute it is in the case of TSO.
1940		 */
1941		if (first->tx_flags & ICE_TX_FLAGS_TSO)
1942			cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
1943		else
1944			cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
1945
1946	} else if (first->tx_flags & ICE_TX_FLAGS_IPV6) {
1947		cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
1948		exthdr = ip.hdr + sizeof(*ip.v6);
1949		l4_proto = ip.v6->nexthdr;
1950		if (l4.hdr != exthdr)
1951			ipv6_skip_exthdr(skb, exthdr - skb->data, &l4_proto,
1952					 &frag_off);
1953	} else {
1954		return -1;
1955	}
1956
1957	/* compute inner L3 header size */
1958	l3_len = l4.hdr - ip.hdr;
1959	offset |= (l3_len / 4) << ICE_TX_DESC_LEN_IPLEN_S;
1960
1961	/* Enable L4 checksum offloads */
1962	switch (l4_proto) {
1963	case IPPROTO_TCP:
1964		/* enable checksum offloads */
1965		cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1966		l4_len = l4.tcp->doff;
1967		offset |= l4_len << ICE_TX_DESC_LEN_L4_LEN_S;
1968		break;
1969	case IPPROTO_UDP:
1970		/* enable UDP checksum offload */
1971		cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
1972		l4_len = (sizeof(struct udphdr) >> 2);
1973		offset |= l4_len << ICE_TX_DESC_LEN_L4_LEN_S;
1974		break;
1975	case IPPROTO_SCTP:
1976		/* enable SCTP checksum offload */
1977		cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
1978		l4_len = sizeof(struct sctphdr) >> 2;
1979		offset |= l4_len << ICE_TX_DESC_LEN_L4_LEN_S;
1980		break;
1981
1982	default:
1983		if (first->tx_flags & ICE_TX_FLAGS_TSO)
1984			return -1;
1985		skb_checksum_help(skb);
1986		return 0;
1987	}
1988
1989	off->td_cmd |= cmd;
1990	off->td_offset |= offset;
1991	return 1;
1992}
1993
1994/**
1995 * ice_tx_prepare_vlan_flags - prepare generic Tx VLAN tagging flags for HW
1996 * @tx_ring: ring to send buffer on
1997 * @first: pointer to struct ice_tx_buf
1998 *
1999 * Checks the skb and set up correspondingly several generic transmit flags
2000 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
 
 
 
2001 */
2002static void
2003ice_tx_prepare_vlan_flags(struct ice_tx_ring *tx_ring, struct ice_tx_buf *first)
2004{
2005	struct sk_buff *skb = first->skb;
 
2006
2007	/* nothing left to do, software offloaded VLAN */
2008	if (!skb_vlan_tag_present(skb) && eth_type_vlan(skb->protocol))
2009		return;
 
 
 
 
 
 
 
 
 
2010
2011	/* the VLAN ethertype/tpid is determined by VSI configuration and netdev
2012	 * feature flags, which the driver only allows either 802.1Q or 802.1ad
2013	 * VLAN offloads exclusively so we only care about the VLAN ID here
2014	 */
2015	if (skb_vlan_tag_present(skb)) {
2016		first->vid = skb_vlan_tag_get(skb);
2017		if (tx_ring->flags & ICE_TX_FLAGS_RING_VLAN_L2TAG2)
2018			first->tx_flags |= ICE_TX_FLAGS_HW_OUTER_SINGLE_VLAN;
2019		else
2020			first->tx_flags |= ICE_TX_FLAGS_HW_VLAN;
 
 
 
 
 
 
 
 
 
 
2021	}
2022
2023	ice_tx_prepare_vlan_flags_dcb(tx_ring, first);
2024}
2025
2026/**
2027 * ice_tso - computes mss and TSO length to prepare for TSO
2028 * @first: pointer to struct ice_tx_buf
2029 * @off: pointer to struct that holds offload parameters
2030 *
2031 * Returns 0 or error (negative) if TSO can't happen, 1 otherwise.
2032 */
2033static
2034int ice_tso(struct ice_tx_buf *first, struct ice_tx_offload_params *off)
2035{
2036	struct sk_buff *skb = first->skb;
2037	union {
2038		struct iphdr *v4;
2039		struct ipv6hdr *v6;
2040		unsigned char *hdr;
2041	} ip;
2042	union {
2043		struct tcphdr *tcp;
2044		struct udphdr *udp;
2045		unsigned char *hdr;
2046	} l4;
2047	u64 cd_mss, cd_tso_len;
2048	__be16 protocol;
2049	u32 paylen;
2050	u8 l4_start;
2051	int err;
2052
2053	if (skb->ip_summed != CHECKSUM_PARTIAL)
2054		return 0;
2055
2056	if (!skb_is_gso(skb))
2057		return 0;
2058
2059	err = skb_cow_head(skb, 0);
2060	if (err < 0)
2061		return err;
2062
2063	protocol = vlan_get_protocol(skb);
2064
2065	if (eth_p_mpls(protocol))
2066		ip.hdr = skb_inner_network_header(skb);
2067	else
2068		ip.hdr = skb_network_header(skb);
2069	l4.hdr = skb_checksum_start(skb);
2070
2071	/* initialize outer IP header fields */
2072	if (ip.v4->version == 4) {
2073		ip.v4->tot_len = 0;
2074		ip.v4->check = 0;
2075	} else {
2076		ip.v6->payload_len = 0;
2077	}
2078
2079	if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
2080					 SKB_GSO_GRE_CSUM |
2081					 SKB_GSO_IPXIP4 |
2082					 SKB_GSO_IPXIP6 |
2083					 SKB_GSO_UDP_TUNNEL |
2084					 SKB_GSO_UDP_TUNNEL_CSUM)) {
2085		if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
2086		    (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) {
2087			l4.udp->len = 0;
2088
2089			/* determine offset of outer transport header */
2090			l4_start = (u8)(l4.hdr - skb->data);
2091
2092			/* remove payload length from outer checksum */
2093			paylen = skb->len - l4_start;
2094			csum_replace_by_diff(&l4.udp->check,
2095					     (__force __wsum)htonl(paylen));
2096		}
2097
2098		/* reset pointers to inner headers */
2099		ip.hdr = skb_inner_network_header(skb);
2100		l4.hdr = skb_inner_transport_header(skb);
2101
2102		/* initialize inner IP header fields */
2103		if (ip.v4->version == 4) {
2104			ip.v4->tot_len = 0;
2105			ip.v4->check = 0;
2106		} else {
2107			ip.v6->payload_len = 0;
2108		}
2109	}
2110
2111	/* determine offset of transport header */
2112	l4_start = (u8)(l4.hdr - skb->data);
2113
2114	/* remove payload length from checksum */
2115	paylen = skb->len - l4_start;
 
2116
2117	if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
2118		csum_replace_by_diff(&l4.udp->check,
2119				     (__force __wsum)htonl(paylen));
2120		/* compute length of UDP segmentation header */
2121		off->header_len = (u8)sizeof(l4.udp) + l4_start;
2122	} else {
2123		csum_replace_by_diff(&l4.tcp->check,
2124				     (__force __wsum)htonl(paylen));
2125		/* compute length of TCP segmentation header */
2126		off->header_len = (u8)((l4.tcp->doff * 4) + l4_start);
2127	}
2128
2129	/* update gso_segs and bytecount */
2130	first->gso_segs = skb_shinfo(skb)->gso_segs;
2131	first->bytecount += (first->gso_segs - 1) * off->header_len;
2132
2133	cd_tso_len = skb->len - off->header_len;
2134	cd_mss = skb_shinfo(skb)->gso_size;
2135
2136	/* record cdesc_qw1 with TSO parameters */
2137	off->cd_qw1 |= (u64)(ICE_TX_DESC_DTYPE_CTX |
2138			     (ICE_TX_CTX_DESC_TSO << ICE_TXD_CTX_QW1_CMD_S) |
2139			     (cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
2140			     (cd_mss << ICE_TXD_CTX_QW1_MSS_S));
2141	first->tx_flags |= ICE_TX_FLAGS_TSO;
2142	return 1;
2143}
2144
2145/**
2146 * ice_txd_use_count  - estimate the number of descriptors needed for Tx
2147 * @size: transmit request size in bytes
2148 *
2149 * Due to hardware alignment restrictions (4K alignment), we need to
2150 * assume that we can have no more than 12K of data per descriptor, even
2151 * though each descriptor can take up to 16K - 1 bytes of aligned memory.
2152 * Thus, we need to divide by 12K. But division is slow! Instead,
2153 * we decompose the operation into shifts and one relatively cheap
2154 * multiply operation.
2155 *
2156 * To divide by 12K, we first divide by 4K, then divide by 3:
2157 *     To divide by 4K, shift right by 12 bits
2158 *     To divide by 3, multiply by 85, then divide by 256
2159 *     (Divide by 256 is done by shifting right by 8 bits)
2160 * Finally, we add one to round up. Because 256 isn't an exact multiple of
2161 * 3, we'll underestimate near each multiple of 12K. This is actually more
2162 * accurate as we have 4K - 1 of wiggle room that we can fit into the last
2163 * segment. For our purposes this is accurate out to 1M which is orders of
2164 * magnitude greater than our largest possible GSO size.
2165 *
2166 * This would then be implemented as:
2167 *     return (((size >> 12) * 85) >> 8) + ICE_DESCS_FOR_SKB_DATA_PTR;
2168 *
2169 * Since multiplication and division are commutative, we can reorder
2170 * operations into:
2171 *     return ((size * 85) >> 20) + ICE_DESCS_FOR_SKB_DATA_PTR;
2172 */
2173static unsigned int ice_txd_use_count(unsigned int size)
2174{
2175	return ((size * 85) >> 20) + ICE_DESCS_FOR_SKB_DATA_PTR;
2176}
2177
2178/**
2179 * ice_xmit_desc_count - calculate number of Tx descriptors needed
2180 * @skb: send buffer
2181 *
2182 * Returns number of data descriptors needed for this skb.
2183 */
2184static unsigned int ice_xmit_desc_count(struct sk_buff *skb)
2185{
2186	const skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
2187	unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
2188	unsigned int count = 0, size = skb_headlen(skb);
2189
2190	for (;;) {
2191		count += ice_txd_use_count(size);
2192
2193		if (!nr_frags--)
2194			break;
2195
2196		size = skb_frag_size(frag++);
2197	}
2198
2199	return count;
2200}
2201
2202/**
2203 * __ice_chk_linearize - Check if there are more than 8 buffers per packet
2204 * @skb: send buffer
2205 *
2206 * Note: This HW can't DMA more than 8 buffers to build a packet on the wire
2207 * and so we need to figure out the cases where we need to linearize the skb.
2208 *
2209 * For TSO we need to count the TSO header and segment payload separately.
2210 * As such we need to check cases where we have 7 fragments or more as we
2211 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
2212 * the segment payload in the first descriptor, and another 7 for the
2213 * fragments.
2214 */
2215static bool __ice_chk_linearize(struct sk_buff *skb)
2216{
2217	const skb_frag_t *frag, *stale;
2218	int nr_frags, sum;
2219
2220	/* no need to check if number of frags is less than 7 */
2221	nr_frags = skb_shinfo(skb)->nr_frags;
2222	if (nr_frags < (ICE_MAX_BUF_TXD - 1))
2223		return false;
2224
2225	/* We need to walk through the list and validate that each group
2226	 * of 6 fragments totals at least gso_size.
2227	 */
2228	nr_frags -= ICE_MAX_BUF_TXD - 2;
2229	frag = &skb_shinfo(skb)->frags[0];
2230
2231	/* Initialize size to the negative value of gso_size minus 1. We
2232	 * use this as the worst case scenario in which the frag ahead
2233	 * of us only provides one byte which is why we are limited to 6
2234	 * descriptors for a single transmit as the header and previous
2235	 * fragment are already consuming 2 descriptors.
2236	 */
2237	sum = 1 - skb_shinfo(skb)->gso_size;
2238
2239	/* Add size of frags 0 through 4 to create our initial sum */
2240	sum += skb_frag_size(frag++);
2241	sum += skb_frag_size(frag++);
2242	sum += skb_frag_size(frag++);
2243	sum += skb_frag_size(frag++);
2244	sum += skb_frag_size(frag++);
2245
2246	/* Walk through fragments adding latest fragment, testing it, and
2247	 * then removing stale fragments from the sum.
2248	 */
2249	for (stale = &skb_shinfo(skb)->frags[0];; stale++) {
2250		int stale_size = skb_frag_size(stale);
2251
2252		sum += skb_frag_size(frag++);
2253
2254		/* The stale fragment may present us with a smaller
2255		 * descriptor than the actual fragment size. To account
2256		 * for that we need to remove all the data on the front and
2257		 * figure out what the remainder would be in the last
2258		 * descriptor associated with the fragment.
2259		 */
2260		if (stale_size > ICE_MAX_DATA_PER_TXD) {
2261			int align_pad = -(skb_frag_off(stale)) &
2262					(ICE_MAX_READ_REQ_SIZE - 1);
2263
2264			sum -= align_pad;
2265			stale_size -= align_pad;
2266
2267			do {
2268				sum -= ICE_MAX_DATA_PER_TXD_ALIGNED;
2269				stale_size -= ICE_MAX_DATA_PER_TXD_ALIGNED;
2270			} while (stale_size > ICE_MAX_DATA_PER_TXD);
2271		}
2272
2273		/* if sum is negative we failed to make sufficient progress */
2274		if (sum < 0)
2275			return true;
2276
2277		if (!nr_frags--)
2278			break;
2279
2280		sum -= stale_size;
2281	}
2282
2283	return false;
2284}
2285
2286/**
2287 * ice_chk_linearize - Check if there are more than 8 fragments per packet
2288 * @skb:      send buffer
2289 * @count:    number of buffers used
2290 *
2291 * Note: Our HW can't scatter-gather more than 8 fragments to build
2292 * a packet on the wire and so we need to figure out the cases where we
2293 * need to linearize the skb.
2294 */
2295static bool ice_chk_linearize(struct sk_buff *skb, unsigned int count)
2296{
2297	/* Both TSO and single send will work if count is less than 8 */
2298	if (likely(count < ICE_MAX_BUF_TXD))
2299		return false;
2300
2301	if (skb_is_gso(skb))
2302		return __ice_chk_linearize(skb);
2303
2304	/* we can support up to 8 data buffers for a single send */
2305	return count != ICE_MAX_BUF_TXD;
2306}
2307
2308/**
2309 * ice_tstamp - set up context descriptor for hardware timestamp
2310 * @tx_ring: pointer to the Tx ring to send buffer on
2311 * @skb: pointer to the SKB we're sending
2312 * @first: Tx buffer
2313 * @off: Tx offload parameters
2314 */
2315static void
2316ice_tstamp(struct ice_tx_ring *tx_ring, struct sk_buff *skb,
2317	   struct ice_tx_buf *first, struct ice_tx_offload_params *off)
2318{
2319	s8 idx;
2320
2321	/* only timestamp the outbound packet if the user has requested it */
2322	if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
2323		return;
2324
2325	/* Tx timestamps cannot be sampled when doing TSO */
2326	if (first->tx_flags & ICE_TX_FLAGS_TSO)
2327		return;
2328
2329	/* Grab an open timestamp slot */
2330	idx = ice_ptp_request_ts(tx_ring->tx_tstamps, skb);
2331	if (idx < 0) {
2332		tx_ring->vsi->back->ptp.tx_hwtstamp_skipped++;
2333		return;
2334	}
2335
2336	off->cd_qw1 |= (u64)(ICE_TX_DESC_DTYPE_CTX |
2337			     (ICE_TX_CTX_DESC_TSYN << ICE_TXD_CTX_QW1_CMD_S) |
2338			     ((u64)idx << ICE_TXD_CTX_QW1_TSO_LEN_S));
2339	first->tx_flags |= ICE_TX_FLAGS_TSYN;
2340}
2341
2342/**
2343 * ice_xmit_frame_ring - Sends buffer on Tx ring
2344 * @skb: send buffer
2345 * @tx_ring: ring to send buffer on
2346 *
2347 * Returns NETDEV_TX_OK if sent, else an error code
2348 */
2349static netdev_tx_t
2350ice_xmit_frame_ring(struct sk_buff *skb, struct ice_tx_ring *tx_ring)
2351{
2352	struct ice_tx_offload_params offload = { 0 };
2353	struct ice_vsi *vsi = tx_ring->vsi;
2354	struct ice_tx_buf *first;
2355	struct ethhdr *eth;
2356	unsigned int count;
2357	int tso, csum;
2358
2359	ice_trace(xmit_frame_ring, tx_ring, skb);
2360
2361	if (unlikely(ipv6_hopopt_jumbo_remove(skb)))
2362		goto out_drop;
2363
2364	count = ice_xmit_desc_count(skb);
2365	if (ice_chk_linearize(skb, count)) {
2366		if (__skb_linearize(skb))
2367			goto out_drop;
2368		count = ice_txd_use_count(skb->len);
2369		tx_ring->ring_stats->tx_stats.tx_linearize++;
2370	}
2371
2372	/* need: 1 descriptor per page * PAGE_SIZE/ICE_MAX_DATA_PER_TXD,
2373	 *       + 1 desc for skb_head_len/ICE_MAX_DATA_PER_TXD,
2374	 *       + 4 desc gap to avoid the cache line where head is,
2375	 *       + 1 desc for context descriptor,
2376	 * otherwise try next time
2377	 */
2378	if (ice_maybe_stop_tx(tx_ring, count + ICE_DESCS_PER_CACHE_LINE +
2379			      ICE_DESCS_FOR_CTX_DESC)) {
2380		tx_ring->ring_stats->tx_stats.tx_busy++;
2381		return NETDEV_TX_BUSY;
2382	}
2383
2384	/* prefetch for bql data which is infrequently used */
2385	netdev_txq_bql_enqueue_prefetchw(txring_txq(tx_ring));
2386
2387	offload.tx_ring = tx_ring;
2388
2389	/* record the location of the first descriptor for this packet */
2390	first = &tx_ring->tx_buf[tx_ring->next_to_use];
2391	first->skb = skb;
2392	first->type = ICE_TX_BUF_SKB;
2393	first->bytecount = max_t(unsigned int, skb->len, ETH_ZLEN);
2394	first->gso_segs = 1;
2395	first->tx_flags = 0;
2396
2397	/* prepare the VLAN tagging flags for Tx */
2398	ice_tx_prepare_vlan_flags(tx_ring, first);
2399	if (first->tx_flags & ICE_TX_FLAGS_HW_OUTER_SINGLE_VLAN) {
2400		offload.cd_qw1 |= (u64)(ICE_TX_DESC_DTYPE_CTX |
2401					(ICE_TX_CTX_DESC_IL2TAG2 <<
2402					ICE_TXD_CTX_QW1_CMD_S));
2403		offload.cd_l2tag2 = first->vid;
2404	}
2405
2406	/* set up TSO offload */
2407	tso = ice_tso(first, &offload);
2408	if (tso < 0)
2409		goto out_drop;
2410
2411	/* always set up Tx checksum offload */
2412	csum = ice_tx_csum(first, &offload);
2413	if (csum < 0)
2414		goto out_drop;
2415
2416	/* allow CONTROL frames egress from main VSI if FW LLDP disabled */
2417	eth = (struct ethhdr *)skb_mac_header(skb);
2418	if (unlikely((skb->priority == TC_PRIO_CONTROL ||
2419		      eth->h_proto == htons(ETH_P_LLDP)) &&
2420		     vsi->type == ICE_VSI_PF &&
2421		     vsi->port_info->qos_cfg.is_sw_lldp))
2422		offload.cd_qw1 |= (u64)(ICE_TX_DESC_DTYPE_CTX |
2423					ICE_TX_CTX_DESC_SWTCH_UPLINK <<
2424					ICE_TXD_CTX_QW1_CMD_S);
2425
2426	ice_tstamp(tx_ring, skb, first, &offload);
2427	if (ice_is_switchdev_running(vsi->back) && vsi->type != ICE_VSI_SF)
2428		ice_eswitch_set_target_vsi(skb, &offload);
2429
2430	if (offload.cd_qw1 & ICE_TX_DESC_DTYPE_CTX) {
2431		struct ice_tx_ctx_desc *cdesc;
2432		u16 i = tx_ring->next_to_use;
2433
2434		/* grab the next descriptor */
2435		cdesc = ICE_TX_CTX_DESC(tx_ring, i);
2436		i++;
2437		tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2438
2439		/* setup context descriptor */
2440		cdesc->tunneling_params = cpu_to_le32(offload.cd_tunnel_params);
2441		cdesc->l2tag2 = cpu_to_le16(offload.cd_l2tag2);
2442		cdesc->rsvd = cpu_to_le16(0);
2443		cdesc->qw1 = cpu_to_le64(offload.cd_qw1);
2444	}
2445
2446	ice_tx_map(tx_ring, first, &offload);
2447	return NETDEV_TX_OK;
2448
2449out_drop:
2450	ice_trace(xmit_frame_ring_drop, tx_ring, skb);
2451	dev_kfree_skb_any(skb);
2452	return NETDEV_TX_OK;
2453}
2454
2455/**
2456 * ice_start_xmit - Selects the correct VSI and Tx queue to send buffer
2457 * @skb: send buffer
2458 * @netdev: network interface device structure
2459 *
2460 * Returns NETDEV_TX_OK if sent, else an error code
2461 */
2462netdev_tx_t ice_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2463{
2464	struct ice_netdev_priv *np = netdev_priv(netdev);
2465	struct ice_vsi *vsi = np->vsi;
2466	struct ice_tx_ring *tx_ring;
2467
2468	tx_ring = vsi->tx_rings[skb->queue_mapping];
2469
2470	/* hardware can't handle really short frames, hardware padding works
2471	 * beyond this point
2472	 */
2473	if (skb_put_padto(skb, ICE_MIN_TX_LEN))
2474		return NETDEV_TX_OK;
2475
2476	return ice_xmit_frame_ring(skb, tx_ring);
2477}
2478
2479/**
2480 * ice_get_dscp_up - return the UP/TC value for a SKB
2481 * @dcbcfg: DCB config that contains DSCP to UP/TC mapping
2482 * @skb: SKB to query for info to determine UP/TC
2483 *
2484 * This function is to only be called when the PF is in L3 DSCP PFC mode
2485 */
2486static u8 ice_get_dscp_up(struct ice_dcbx_cfg *dcbcfg, struct sk_buff *skb)
2487{
2488	u8 dscp = 0;
2489
2490	if (skb->protocol == htons(ETH_P_IP))
2491		dscp = ipv4_get_dsfield(ip_hdr(skb)) >> 2;
2492	else if (skb->protocol == htons(ETH_P_IPV6))
2493		dscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> 2;
2494
2495	return dcbcfg->dscp_map[dscp];
2496}
2497
2498u16
2499ice_select_queue(struct net_device *netdev, struct sk_buff *skb,
2500		 struct net_device *sb_dev)
2501{
2502	struct ice_pf *pf = ice_netdev_to_pf(netdev);
2503	struct ice_dcbx_cfg *dcbcfg;
2504
2505	dcbcfg = &pf->hw.port_info->qos_cfg.local_dcbx_cfg;
2506	if (dcbcfg->pfc_mode == ICE_QOS_MODE_DSCP)
2507		skb->priority = ice_get_dscp_up(dcbcfg, skb);
2508
2509	return netdev_pick_tx(netdev, skb, sb_dev);
2510}
2511
2512/**
2513 * ice_clean_ctrl_tx_irq - interrupt handler for flow director Tx queue
2514 * @tx_ring: tx_ring to clean
2515 */
2516void ice_clean_ctrl_tx_irq(struct ice_tx_ring *tx_ring)
2517{
2518	struct ice_vsi *vsi = tx_ring->vsi;
2519	s16 i = tx_ring->next_to_clean;
2520	int budget = ICE_DFLT_IRQ_WORK;
2521	struct ice_tx_desc *tx_desc;
2522	struct ice_tx_buf *tx_buf;
2523
2524	tx_buf = &tx_ring->tx_buf[i];
2525	tx_desc = ICE_TX_DESC(tx_ring, i);
2526	i -= tx_ring->count;
2527
2528	do {
2529		struct ice_tx_desc *eop_desc = tx_buf->next_to_watch;
2530
2531		/* if next_to_watch is not set then there is no pending work */
2532		if (!eop_desc)
2533			break;
2534
2535		/* prevent any other reads prior to eop_desc */
2536		smp_rmb();
2537
2538		/* if the descriptor isn't done, no work to do */
2539		if (!(eop_desc->cmd_type_offset_bsz &
2540		      cpu_to_le64(ICE_TX_DESC_DTYPE_DESC_DONE)))
2541			break;
2542
2543		/* clear next_to_watch to prevent false hangs */
2544		tx_buf->next_to_watch = NULL;
2545		tx_desc->buf_addr = 0;
2546		tx_desc->cmd_type_offset_bsz = 0;
2547
2548		/* move past filter desc */
2549		tx_buf++;
2550		tx_desc++;
2551		i++;
2552		if (unlikely(!i)) {
2553			i -= tx_ring->count;
2554			tx_buf = tx_ring->tx_buf;
2555			tx_desc = ICE_TX_DESC(tx_ring, 0);
2556		}
2557
2558		/* unmap the data header */
2559		if (dma_unmap_len(tx_buf, len))
2560			dma_unmap_single(tx_ring->dev,
2561					 dma_unmap_addr(tx_buf, dma),
2562					 dma_unmap_len(tx_buf, len),
2563					 DMA_TO_DEVICE);
2564		if (tx_buf->type == ICE_TX_BUF_DUMMY)
2565			devm_kfree(tx_ring->dev, tx_buf->raw_buf);
2566
2567		/* clear next_to_watch to prevent false hangs */
2568		tx_buf->type = ICE_TX_BUF_EMPTY;
2569		tx_buf->tx_flags = 0;
2570		tx_buf->next_to_watch = NULL;
2571		dma_unmap_len_set(tx_buf, len, 0);
2572		tx_desc->buf_addr = 0;
2573		tx_desc->cmd_type_offset_bsz = 0;
2574
2575		/* move past eop_desc for start of next FD desc */
2576		tx_buf++;
2577		tx_desc++;
2578		i++;
2579		if (unlikely(!i)) {
2580			i -= tx_ring->count;
2581			tx_buf = tx_ring->tx_buf;
2582			tx_desc = ICE_TX_DESC(tx_ring, 0);
2583		}
2584
2585		budget--;
2586	} while (likely(budget));
2587
2588	i += tx_ring->count;
2589	tx_ring->next_to_clean = i;
2590
2591	/* re-enable interrupt if needed */
2592	ice_irq_dynamic_ena(&vsi->back->hw, vsi, vsi->q_vectors[0]);
2593}

   1// SPDX-License-Identifier: GPL-2.0
   2/* Copyright (c) 2018, Intel Corporation. */
   3
   4/* The driver transmit and receive code */
   5
 
 
   6#include <linux/prefetch.h>
   7#include <linux/mm.h>
 
 
 
 
 
   8#include "ice.h"
 
   9#include "ice_dcb_lib.h"
 
 
  10
  11#define ICE_RX_HDR_SIZE		256
  12
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  13/**
  14 * ice_unmap_and_free_tx_buf - Release a Tx buffer
  15 * @ring: the ring that owns the buffer
  16 * @tx_buf: the buffer to free
  17 */
  18static void
  19ice_unmap_and_free_tx_buf(struct ice_ring *ring, struct ice_tx_buf *tx_buf)
  20{
  21	if (tx_buf->skb) {
  22		dev_kfree_skb_any(tx_buf->skb);
  23		if (dma_unmap_len(tx_buf, len))
  24			dma_unmap_single(ring->dev,
  25					 dma_unmap_addr(tx_buf, dma),
  26					 dma_unmap_len(tx_buf, len),
  27					 DMA_TO_DEVICE);
  28	} else if (dma_unmap_len(tx_buf, len)) {
  29		dma_unmap_page(ring->dev,
  30			       dma_unmap_addr(tx_buf, dma),
  31			       dma_unmap_len(tx_buf, len),
  32			       DMA_TO_DEVICE);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  33	}
  34
  35	tx_buf->next_to_watch = NULL;
  36	tx_buf->skb = NULL;
  37	dma_unmap_len_set(tx_buf, len, 0);
  38	/* tx_buf must be completely set up in the transmit path */
  39}
  40
  41static struct netdev_queue *txring_txq(const struct ice_ring *ring)
  42{
  43	return netdev_get_tx_queue(ring->netdev, ring->q_index);
  44}
  45
  46/**
  47 * ice_clean_tx_ring - Free any empty Tx buffers
  48 * @tx_ring: ring to be cleaned
  49 */
  50void ice_clean_tx_ring(struct ice_ring *tx_ring)
  51{
 
  52	u16 i;
  53
 
 
 
 
 
  54	/* ring already cleared, nothing to do */
  55	if (!tx_ring->tx_buf)
  56		return;
  57
  58	/* Free all the Tx ring sk_buffs */
  59	for (i = 0; i < tx_ring->count; i++)
  60		ice_unmap_and_free_tx_buf(tx_ring, &tx_ring->tx_buf[i]);
  61
 
  62	memset(tx_ring->tx_buf, 0, sizeof(*tx_ring->tx_buf) * tx_ring->count);
  63
 
 
  64	/* Zero out the descriptor ring */
  65	memset(tx_ring->desc, 0, tx_ring->size);
  66
  67	tx_ring->next_to_use = 0;
  68	tx_ring->next_to_clean = 0;
  69
  70	if (!tx_ring->netdev)
  71		return;
  72
  73	/* cleanup Tx queue statistics */
  74	netdev_tx_reset_queue(txring_txq(tx_ring));
  75}
  76
  77/**
  78 * ice_free_tx_ring - Free Tx resources per queue
  79 * @tx_ring: Tx descriptor ring for a specific queue
  80 *
  81 * Free all transmit software resources
  82 */
  83void ice_free_tx_ring(struct ice_ring *tx_ring)
  84{
 
 
  85	ice_clean_tx_ring(tx_ring);
  86	devm_kfree(tx_ring->dev, tx_ring->tx_buf);
  87	tx_ring->tx_buf = NULL;
  88
  89	if (tx_ring->desc) {
  90		dmam_free_coherent(tx_ring->dev, tx_ring->size,
 
 
  91				   tx_ring->desc, tx_ring->dma);
  92		tx_ring->desc = NULL;
  93	}
  94}
  95
  96/**
  97 * ice_clean_tx_irq - Reclaim resources after transmit completes
  98 * @tx_ring: Tx ring to clean
  99 * @napi_budget: Used to determine if we are in netpoll
 100 *
 101 * Returns true if there's any budget left (e.g. the clean is finished)
 102 */
 103static bool ice_clean_tx_irq(struct ice_ring *tx_ring, int napi_budget)
 104{
 105	unsigned int total_bytes = 0, total_pkts = 0;
 106	unsigned int budget = ICE_DFLT_IRQ_WORK;
 107	struct ice_vsi *vsi = tx_ring->vsi;
 108	s16 i = tx_ring->next_to_clean;
 109	struct ice_tx_desc *tx_desc;
 110	struct ice_tx_buf *tx_buf;
 111
 
 
 
 112	tx_buf = &tx_ring->tx_buf[i];
 113	tx_desc = ICE_TX_DESC(tx_ring, i);
 114	i -= tx_ring->count;
 115
 116	prefetch(&vsi->state);
 117
 118	do {
 119		struct ice_tx_desc *eop_desc = tx_buf->next_to_watch;
 120
 121		/* if next_to_watch is not set then there is no work pending */
 122		if (!eop_desc)
 123			break;
 124
 
 
 
 125		smp_rmb();	/* prevent any other reads prior to eop_desc */
 126
 
 127		/* if the descriptor isn't done, no work yet to do */
 128		if (!(eop_desc->cmd_type_offset_bsz &
 129		      cpu_to_le64(ICE_TX_DESC_DTYPE_DESC_DONE)))
 130			break;
 131
 132		/* clear next_to_watch to prevent false hangs */
 133		tx_buf->next_to_watch = NULL;
 134
 135		/* update the statistics for this packet */
 136		total_bytes += tx_buf->bytecount;
 137		total_pkts += tx_buf->gso_segs;
 138
 139		/* free the skb */
 140		napi_consume_skb(tx_buf->skb, napi_budget);
 141
 142		/* unmap skb header data */
 143		dma_unmap_single(tx_ring->dev,
 144				 dma_unmap_addr(tx_buf, dma),
 145				 dma_unmap_len(tx_buf, len),
 146				 DMA_TO_DEVICE);
 147
 148		/* clear tx_buf data */
 149		tx_buf->skb = NULL;
 150		dma_unmap_len_set(tx_buf, len, 0);
 151
 152		/* unmap remaining buffers */
 153		while (tx_desc != eop_desc) {
 
 154			tx_buf++;
 155			tx_desc++;
 156			i++;
 157			if (unlikely(!i)) {
 158				i -= tx_ring->count;
 159				tx_buf = tx_ring->tx_buf;
 160				tx_desc = ICE_TX_DESC(tx_ring, 0);
 161			}
 162
 163			/* unmap any remaining paged data */
 164			if (dma_unmap_len(tx_buf, len)) {
 165				dma_unmap_page(tx_ring->dev,
 166					       dma_unmap_addr(tx_buf, dma),
 167					       dma_unmap_len(tx_buf, len),
 168					       DMA_TO_DEVICE);
 169				dma_unmap_len_set(tx_buf, len, 0);
 170			}
 171		}
 
 172
 173		/* move us one more past the eop_desc for start of next pkt */
 174		tx_buf++;
 175		tx_desc++;
 176		i++;
 177		if (unlikely(!i)) {
 178			i -= tx_ring->count;
 179			tx_buf = tx_ring->tx_buf;
 180			tx_desc = ICE_TX_DESC(tx_ring, 0);
 181		}
 182
 183		prefetch(tx_desc);
 184
 185		/* update budget accounting */
 186		budget--;
 187	} while (likely(budget));
 188
 189	i += tx_ring->count;
 190	tx_ring->next_to_clean = i;
 191	u64_stats_update_begin(&tx_ring->syncp);
 192	tx_ring->stats.bytes += total_bytes;
 193	tx_ring->stats.pkts += total_pkts;
 194	u64_stats_update_end(&tx_ring->syncp);
 195	tx_ring->q_vector->tx.total_bytes += total_bytes;
 196	tx_ring->q_vector->tx.total_pkts += total_pkts;
 197
 198	netdev_tx_completed_queue(txring_txq(tx_ring), total_pkts,
 199				  total_bytes);
 200
 201#define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2))
 202	if (unlikely(total_pkts && netif_carrier_ok(tx_ring->netdev) &&
 203		     (ICE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 204		/* Make sure that anybody stopping the queue after this
 205		 * sees the new next_to_clean.
 206		 */
 207		smp_mb();
 208		if (__netif_subqueue_stopped(tx_ring->netdev,
 209					     tx_ring->q_index) &&
 210		    !test_bit(__ICE_DOWN, vsi->state)) {
 211			netif_wake_subqueue(tx_ring->netdev,
 212					    tx_ring->q_index);
 213			++tx_ring->tx_stats.restart_q;
 214		}
 215	}
 216
 217	return !!budget;
 218}
 219
 220/**
 221 * ice_setup_tx_ring - Allocate the Tx descriptors
 222 * @tx_ring: the Tx ring to set up
 223 *
 224 * Return 0 on success, negative on error
 225 */
 226int ice_setup_tx_ring(struct ice_ring *tx_ring)
 227{
 228	struct device *dev = tx_ring->dev;
 
 229
 230	if (!dev)
 231		return -ENOMEM;
 232
 233	/* warn if we are about to overwrite the pointer */
 234	WARN_ON(tx_ring->tx_buf);
 235	tx_ring->tx_buf =
 236		devm_kzalloc(dev, sizeof(*tx_ring->tx_buf) * tx_ring->count,
 237			     GFP_KERNEL);
 238	if (!tx_ring->tx_buf)
 239		return -ENOMEM;
 240
 241	/* round up to nearest page */
 242	tx_ring->size = ALIGN(tx_ring->count * sizeof(struct ice_tx_desc),
 243			      PAGE_SIZE);
 244	tx_ring->desc = dmam_alloc_coherent(dev, tx_ring->size, &tx_ring->dma,
 245					    GFP_KERNEL);
 246	if (!tx_ring->desc) {
 247		dev_err(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
 248			tx_ring->size);
 249		goto err;
 250	}
 251
 252	tx_ring->next_to_use = 0;
 253	tx_ring->next_to_clean = 0;
 254	tx_ring->tx_stats.prev_pkt = -1;
 255	return 0;
 256
 257err:
 258	devm_kfree(dev, tx_ring->tx_buf);
 259	tx_ring->tx_buf = NULL;
 260	return -ENOMEM;
 261}
 262
 263/**
 264 * ice_clean_rx_ring - Free Rx buffers
 265 * @rx_ring: ring to be cleaned
 266 */
 267void ice_clean_rx_ring(struct ice_ring *rx_ring)
 268{
 
 269	struct device *dev = rx_ring->dev;
 
 270	u16 i;
 271
 272	/* ring already cleared, nothing to do */
 273	if (!rx_ring->rx_buf)
 274		return;
 275
 
 
 
 
 
 
 
 
 
 
 276	/* Free all the Rx ring sk_buffs */
 277	for (i = 0; i < rx_ring->count; i++) {
 278		struct ice_rx_buf *rx_buf = &rx_ring->rx_buf[i];
 279
 280		if (rx_buf->skb) {
 281			dev_kfree_skb(rx_buf->skb);
 282			rx_buf->skb = NULL;
 283		}
 284		if (!rx_buf->page)
 285			continue;
 286
 287		/* Invalidate cache lines that may have been written to by
 288		 * device so that we avoid corrupting memory.
 289		 */
 290		dma_sync_single_range_for_cpu(dev, rx_buf->dma,
 291					      rx_buf->page_offset,
 292					      ICE_RXBUF_2048, DMA_FROM_DEVICE);
 
 293
 294		/* free resources associated with mapping */
 295		dma_unmap_page_attrs(dev, rx_buf->dma, PAGE_SIZE,
 296				     DMA_FROM_DEVICE, ICE_RX_DMA_ATTR);
 297		__page_frag_cache_drain(rx_buf->page, rx_buf->pagecnt_bias);
 298
 299		rx_buf->page = NULL;
 300		rx_buf->page_offset = 0;
 301	}
 302
 303	memset(rx_ring->rx_buf, 0, sizeof(*rx_ring->rx_buf) * rx_ring->count);
 
 
 
 
 304
 305	/* Zero out the descriptor ring */
 306	memset(rx_ring->desc, 0, rx_ring->size);
 
 
 307
 308	rx_ring->next_to_alloc = 0;
 309	rx_ring->next_to_clean = 0;
 
 310	rx_ring->next_to_use = 0;
 311}
 312
 313/**
 314 * ice_free_rx_ring - Free Rx resources
 315 * @rx_ring: ring to clean the resources from
 316 *
 317 * Free all receive software resources
 318 */
 319void ice_free_rx_ring(struct ice_ring *rx_ring)
 320{
 
 
 321	ice_clean_rx_ring(rx_ring);
 322	devm_kfree(rx_ring->dev, rx_ring->rx_buf);
 323	rx_ring->rx_buf = NULL;
 
 
 
 
 
 
 
 
 
 324
 325	if (rx_ring->desc) {
 326		dmam_free_coherent(rx_ring->dev, rx_ring->size,
 
 
 327				   rx_ring->desc, rx_ring->dma);
 328		rx_ring->desc = NULL;
 329	}
 330}
 331
 332/**
 333 * ice_setup_rx_ring - Allocate the Rx descriptors
 334 * @rx_ring: the Rx ring to set up
 335 *
 336 * Return 0 on success, negative on error
 337 */
 338int ice_setup_rx_ring(struct ice_ring *rx_ring)
 339{
 340	struct device *dev = rx_ring->dev;
 
 341
 342	if (!dev)
 343		return -ENOMEM;
 344
 345	/* warn if we are about to overwrite the pointer */
 346	WARN_ON(rx_ring->rx_buf);
 347	rx_ring->rx_buf =
 348		devm_kzalloc(dev, sizeof(*rx_ring->rx_buf) * rx_ring->count,
 349			     GFP_KERNEL);
 350	if (!rx_ring->rx_buf)
 351		return -ENOMEM;
 352
 353	/* round up to nearest page */
 354	rx_ring->size = ALIGN(rx_ring->count * sizeof(union ice_32byte_rx_desc),
 355			      PAGE_SIZE);
 356	rx_ring->desc = dmam_alloc_coherent(dev, rx_ring->size, &rx_ring->dma,
 357					    GFP_KERNEL);
 358	if (!rx_ring->desc) {
 359		dev_err(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
 360			rx_ring->size);
 361		goto err;
 362	}
 363
 364	rx_ring->next_to_use = 0;
 365	rx_ring->next_to_clean = 0;
 
 
 
 
 
 366	return 0;
 367
 368err:
 369	devm_kfree(dev, rx_ring->rx_buf);
 370	rx_ring->rx_buf = NULL;
 371	return -ENOMEM;
 372}
 373
 374/**
 375 * ice_release_rx_desc - Store the new tail and head values
 376 * @rx_ring: ring to bump
 377 * @val: new head index
 378 */
 379static void ice_release_rx_desc(struct ice_ring *rx_ring, u32 val)
 380{
 381	u16 prev_ntu = rx_ring->next_to_use;
 382
 383	rx_ring->next_to_use = val;
 384
 385	/* update next to alloc since we have filled the ring */
 386	rx_ring->next_to_alloc = val;
 387
 388	/* QRX_TAIL will be updated with any tail value, but hardware ignores
 389	 * the lower 3 bits. This makes it so we only bump tail on meaningful
 390	 * boundaries. Also, this allows us to bump tail on intervals of 8 up to
 391	 * the budget depending on the current traffic load.
 392	 */
 393	val &= ~0x7;
 394	if (prev_ntu != val) {
 395		/* Force memory writes to complete before letting h/w
 396		 * know there are new descriptors to fetch. (Only
 397		 * applicable for weak-ordered memory model archs,
 398		 * such as IA-64).
 399		 */
 400		wmb();
 401		writel(val, rx_ring->tail);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 402	}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 403}
 404
 405/**
 406 * ice_alloc_mapped_page - recycle or make a new page
 407 * @rx_ring: ring to use
 408 * @bi: rx_buf struct to modify
 409 *
 410 * Returns true if the page was successfully allocated or
 411 * reused.
 412 */
 413static bool
 414ice_alloc_mapped_page(struct ice_ring *rx_ring, struct ice_rx_buf *bi)
 415{
 416	struct page *page = bi->page;
 417	dma_addr_t dma;
 418
 419	/* since we are recycling buffers we should seldom need to alloc */
 420	if (likely(page)) {
 421		rx_ring->rx_stats.page_reuse_count++;
 422		return true;
 423	}
 424
 425	/* alloc new page for storage */
 426	page = alloc_page(GFP_ATOMIC | __GFP_NOWARN);
 427	if (unlikely(!page)) {
 428		rx_ring->rx_stats.alloc_page_failed++;
 429		return false;
 430	}
 431
 432	/* map page for use */
 433	dma = dma_map_page_attrs(rx_ring->dev, page, 0, PAGE_SIZE,
 434				 DMA_FROM_DEVICE, ICE_RX_DMA_ATTR);
 435
 436	/* if mapping failed free memory back to system since
 437	 * there isn't much point in holding memory we can't use
 438	 */
 439	if (dma_mapping_error(rx_ring->dev, dma)) {
 440		__free_pages(page, 0);
 441		rx_ring->rx_stats.alloc_page_failed++;
 442		return false;
 443	}
 444
 445	bi->dma = dma;
 446	bi->page = page;
 447	bi->page_offset = 0;
 448	page_ref_add(page, USHRT_MAX - 1);
 449	bi->pagecnt_bias = USHRT_MAX;
 450
 451	return true;
 452}
 453
 454/**
 455 * ice_alloc_rx_bufs - Replace used receive buffers
 456 * @rx_ring: ring to place buffers on
 457 * @cleaned_count: number of buffers to replace
 458 *
 459 * Returns false if all allocations were successful, true if any fail. Returning
 460 * true signals to the caller that we didn't replace cleaned_count buffers and
 461 * there is more work to do.
 462 *
 463 * First, try to clean "cleaned_count" Rx buffers. Then refill the cleaned Rx
 464 * buffers. Then bump tail at most one time. Grouping like this lets us avoid
 465 * multiple tail writes per call.
 466 */
 467bool ice_alloc_rx_bufs(struct ice_ring *rx_ring, u16 cleaned_count)
 468{
 469	union ice_32b_rx_flex_desc *rx_desc;
 470	u16 ntu = rx_ring->next_to_use;
 471	struct ice_rx_buf *bi;
 472
 473	/* do nothing if no valid netdev defined */
 474	if (!rx_ring->netdev || !cleaned_count)
 
 475		return false;
 476
 477	/* get the Rx descriptor and buffer based on next_to_use */
 478	rx_desc = ICE_RX_DESC(rx_ring, ntu);
 479	bi = &rx_ring->rx_buf[ntu];
 480
 481	do {
 482		/* if we fail here, we have work remaining */
 483		if (!ice_alloc_mapped_page(rx_ring, bi))
 484			break;
 485
 486		/* sync the buffer for use by the device */
 487		dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
 488						 bi->page_offset,
 489						 ICE_RXBUF_2048,
 490						 DMA_FROM_DEVICE);
 491
 492		/* Refresh the desc even if buffer_addrs didn't change
 493		 * because each write-back erases this info.
 494		 */
 495		rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
 496
 497		rx_desc++;
 498		bi++;
 499		ntu++;
 500		if (unlikely(ntu == rx_ring->count)) {
 501			rx_desc = ICE_RX_DESC(rx_ring, 0);
 502			bi = rx_ring->rx_buf;
 503			ntu = 0;
 504		}
 505
 506		/* clear the status bits for the next_to_use descriptor */
 507		rx_desc->wb.status_error0 = 0;
 508
 509		cleaned_count--;
 510	} while (cleaned_count);
 511
 512	if (rx_ring->next_to_use != ntu)
 513		ice_release_rx_desc(rx_ring, ntu);
 514
 515	return !!cleaned_count;
 516}
 517
 518/**
 519 * ice_page_is_reserved - check if reuse is possible
 520 * @page: page struct to check
 521 */
 522static bool ice_page_is_reserved(struct page *page)
 523{
 524	return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
 525}
 526
 527/**
 528 * ice_rx_buf_adjust_pg_offset - Prepare Rx buffer for reuse
 529 * @rx_buf: Rx buffer to adjust
 530 * @size: Size of adjustment
 531 *
 532 * Update the offset within page so that Rx buf will be ready to be reused.
 533 * For systems with PAGE_SIZE < 8192 this function will flip the page offset
 534 * so the second half of page assigned to Rx buffer will be used, otherwise
 535 * the offset is moved by the @size bytes
 536 */
 537static void
 538ice_rx_buf_adjust_pg_offset(struct ice_rx_buf *rx_buf, unsigned int size)
 539{
 540#if (PAGE_SIZE < 8192)
 541	/* flip page offset to other buffer */
 542	rx_buf->page_offset ^= size;
 543#else
 544	/* move offset up to the next cache line */
 545	rx_buf->page_offset += size;
 546#endif
 547}
 548
 549/**
 550 * ice_can_reuse_rx_page - Determine if page can be reused for another Rx
 551 * @rx_buf: buffer containing the page
 552 *
 553 * If page is reusable, we have a green light for calling ice_reuse_rx_page,
 554 * which will assign the current buffer to the buffer that next_to_alloc is
 555 * pointing to; otherwise, the DMA mapping needs to be destroyed and
 556 * page freed
 557 */
 558static bool ice_can_reuse_rx_page(struct ice_rx_buf *rx_buf)
 
 559{
 560#if (PAGE_SIZE >= 8192)
 561	unsigned int last_offset = PAGE_SIZE - ICE_RXBUF_2048;
 562#endif
 563	unsigned int pagecnt_bias = rx_buf->pagecnt_bias;
 564	struct page *page = rx_buf->page;
 565
 566	/* avoid re-using remote pages */
 567	if (unlikely(ice_page_is_reserved(page)))
 568		return false;
 569
 570#if (PAGE_SIZE < 8192)
 571	/* if we are only owner of page we can reuse it */
 572	if (unlikely((page_count(page) - pagecnt_bias) > 1))
 573		return false;
 574#else
 575	if (rx_buf->page_offset > last_offset)
 
 
 576		return false;
 577#endif /* PAGE_SIZE < 8192) */
 578
 579	/* If we have drained the page fragment pool we need to update
 580	 * the pagecnt_bias and page count so that we fully restock the
 581	 * number of references the driver holds.
 582	 */
 583	if (unlikely(pagecnt_bias == 1)) {
 584		page_ref_add(page, USHRT_MAX - 1);
 585		rx_buf->pagecnt_bias = USHRT_MAX;
 586	}
 587
 588	return true;
 589}
 590
 591/**
 592 * ice_add_rx_frag - Add contents of Rx buffer to sk_buff as a frag
 
 
 593 * @rx_buf: buffer containing page to add
 594 * @skb: sk_buff to place the data into
 595 * @size: packet length from rx_desc
 596 *
 597 * This function will add the data contained in rx_buf->page to the skb.
 598 * It will just attach the page as a frag to the skb.
 599 * The function will then update the page offset.
 600 */
 601static void
 602ice_add_rx_frag(struct ice_rx_buf *rx_buf, struct sk_buff *skb,
 603		unsigned int size)
 604{
 605#if (PAGE_SIZE >= 8192)
 606	unsigned int truesize = SKB_DATA_ALIGN(size);
 607#else
 608	unsigned int truesize = ICE_RXBUF_2048;
 609#endif
 610
 611	if (!size)
 612		return;
 613	skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buf->page,
 614			rx_buf->page_offset, size, truesize);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 615
 616	/* page is being used so we must update the page offset */
 617	ice_rx_buf_adjust_pg_offset(rx_buf, truesize);
 618}
 619
 620/**
 621 * ice_reuse_rx_page - page flip buffer and store it back on the ring
 622 * @rx_ring: Rx descriptor ring to store buffers on
 623 * @old_buf: donor buffer to have page reused
 624 *
 625 * Synchronizes page for reuse by the adapter
 626 */
 627static void
 628ice_reuse_rx_page(struct ice_ring *rx_ring, struct ice_rx_buf *old_buf)
 629{
 630	u16 nta = rx_ring->next_to_alloc;
 631	struct ice_rx_buf *new_buf;
 632
 633	new_buf = &rx_ring->rx_buf[nta];
 634
 635	/* update, and store next to alloc */
 636	nta++;
 637	rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
 638
 639	/* Transfer page from old buffer to new buffer.
 640	 * Move each member individually to avoid possible store
 641	 * forwarding stalls and unnecessary copy of skb.
 642	 */
 643	new_buf->dma = old_buf->dma;
 644	new_buf->page = old_buf->page;
 645	new_buf->page_offset = old_buf->page_offset;
 646	new_buf->pagecnt_bias = old_buf->pagecnt_bias;
 647}
 648
 649/**
 650 * ice_get_rx_buf - Fetch Rx buffer and synchronize data for use
 651 * @rx_ring: Rx descriptor ring to transact packets on
 652 * @skb: skb to be used
 653 * @size: size of buffer to add to skb
 
 654 *
 655 * This function will pull an Rx buffer from the ring and synchronize it
 656 * for use by the CPU.
 657 */
 658static struct ice_rx_buf *
 659ice_get_rx_buf(struct ice_ring *rx_ring, struct sk_buff **skb,
 660	       const unsigned int size)
 661{
 662	struct ice_rx_buf *rx_buf;
 663
 664	rx_buf = &rx_ring->rx_buf[rx_ring->next_to_clean];
 665	prefetchw(rx_buf->page);
 666	*skb = rx_buf->skb;
 667
 668	if (!size)
 669		return rx_buf;
 670	/* we are reusing so sync this buffer for CPU use */
 671	dma_sync_single_range_for_cpu(rx_ring->dev, rx_buf->dma,
 672				      rx_buf->page_offset, size,
 673				      DMA_FROM_DEVICE);
 674
 675	/* We have pulled a buffer for use, so decrement pagecnt_bias */
 676	rx_buf->pagecnt_bias--;
 677
 678	return rx_buf;
 679}
 680
 681/**
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 682 * ice_construct_skb - Allocate skb and populate it
 683 * @rx_ring: Rx descriptor ring to transact packets on
 684 * @rx_buf: Rx buffer to pull data from
 685 * @size: the length of the packet
 686 *
 687 * This function allocates an skb. It then populates it with the page
 688 * data from the current receive descriptor, taking care to set up the
 689 * skb correctly.
 690 */
 691static struct sk_buff *
 692ice_construct_skb(struct ice_ring *rx_ring, struct ice_rx_buf *rx_buf,
 693		  unsigned int size)
 694{
 695	void *va = page_address(rx_buf->page) + rx_buf->page_offset;
 
 
 
 696	unsigned int headlen;
 697	struct sk_buff *skb;
 698
 699	/* prefetch first cache line of first page */
 700	prefetch(va);
 701#if L1_CACHE_BYTES < 128
 702	prefetch((u8 *)va + L1_CACHE_BYTES);
 703#endif /* L1_CACHE_BYTES */
 
 
 704
 705	/* allocate a skb to store the frags */
 706	skb = __napi_alloc_skb(&rx_ring->q_vector->napi, ICE_RX_HDR_SIZE,
 707			       GFP_ATOMIC | __GFP_NOWARN);
 708	if (unlikely(!skb))
 709		return NULL;
 710
 
 711	skb_record_rx_queue(skb, rx_ring->q_index);
 712	/* Determine available headroom for copy */
 713	headlen = size;
 714	if (headlen > ICE_RX_HDR_SIZE)
 715		headlen = eth_get_headlen(skb->dev, va, ICE_RX_HDR_SIZE);
 716
 717	/* align pull length to size of long to optimize memcpy performance */
 718	memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long)));
 
 719
 720	/* if we exhaust the linear part then add what is left as a frag */
 721	size -= headlen;
 722	if (size) {
 723#if (PAGE_SIZE >= 8192)
 724		unsigned int truesize = SKB_DATA_ALIGN(size);
 725#else
 726		unsigned int truesize = ICE_RXBUF_2048;
 727#endif
 
 
 
 728		skb_add_rx_frag(skb, 0, rx_buf->page,
 729				rx_buf->page_offset + headlen, size, truesize);
 730		/* buffer is used by skb, update page_offset */
 731		ice_rx_buf_adjust_pg_offset(rx_buf, truesize);
 732	} else {
 733		/* buffer is unused, reset bias back to rx_buf; data was copied
 734		 * onto skb's linear part so there's no need for adjusting
 735		 * page offset and we can reuse this buffer as-is
 
 736		 */
 737		rx_buf->pagecnt_bias++;
 738	}
 739
 
 
 
 
 
 
 
 
 
 
 
 
 740	return skb;
 741}
 742
 743/**
 744 * ice_put_rx_buf - Clean up used buffer and either recycle or free
 745 * @rx_ring: Rx descriptor ring to transact packets on
 746 * @rx_buf: Rx buffer to pull data from
 747 *
 748 * This function will  clean up the contents of the rx_buf. It will
 749 * either recycle the buffer or unmap it and free the associated resources.
 750 */
 751static void ice_put_rx_buf(struct ice_ring *rx_ring, struct ice_rx_buf *rx_buf)
 
 752{
 753	if (!rx_buf)
 754		return;
 755
 756	if (ice_can_reuse_rx_page(rx_buf)) {
 757		/* hand second half of page back to the ring */
 758		ice_reuse_rx_page(rx_ring, rx_buf);
 759		rx_ring->rx_stats.page_reuse_count++;
 760	} else {
 761		/* we are not reusing the buffer so unmap it */
 762		dma_unmap_page_attrs(rx_ring->dev, rx_buf->dma, PAGE_SIZE,
 763				     DMA_FROM_DEVICE, ICE_RX_DMA_ATTR);
 
 764		__page_frag_cache_drain(rx_buf->page, rx_buf->pagecnt_bias);
 765	}
 766
 767	/* clear contents of buffer_info */
 768	rx_buf->page = NULL;
 769	rx_buf->skb = NULL;
 770}
 771
 772/**
 773 * ice_cleanup_headers - Correct empty headers
 774 * @skb: pointer to current skb being fixed
 775 *
 776 * Also address the case where we are pulling data in on pages only
 777 * and as such no data is present in the skb header.
 778 *
 779 * In addition if skb is not at least 60 bytes we need to pad it so that
 780 * it is large enough to qualify as a valid Ethernet frame.
 781 *
 782 * Returns true if an error was encountered and skb was freed.
 783 */
 784static bool ice_cleanup_headers(struct sk_buff *skb)
 785{
 786	/* if eth_skb_pad returns an error the skb was freed */
 787	if (eth_skb_pad(skb))
 788		return true;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 789
 790	return false;
 791}
 792
 793/**
 794 * ice_test_staterr - tests bits in Rx descriptor status and error fields
 795 * @rx_desc: pointer to receive descriptor (in le64 format)
 796 * @stat_err_bits: value to mask
 797 *
 798 * This function does some fast chicanery in order to return the
 799 * value of the mask which is really only used for boolean tests.
 800 * The status_error_len doesn't need to be shifted because it begins
 801 * at offset zero.
 802 */
 803static bool
 804ice_test_staterr(union ice_32b_rx_flex_desc *rx_desc, const u16 stat_err_bits)
 805{
 806	return !!(rx_desc->wb.status_error0 &
 807		  cpu_to_le16(stat_err_bits));
 808}
 809
 810/**
 811 * ice_is_non_eop - process handling of non-EOP buffers
 812 * @rx_ring: Rx ring being processed
 813 * @rx_desc: Rx descriptor for current buffer
 814 * @skb: Current socket buffer containing buffer in progress
 815 *
 816 * This function updates next to clean. If the buffer is an EOP buffer
 817 * this function exits returning false, otherwise it will place the
 818 * sk_buff in the next buffer to be chained and return true indicating
 819 * that this is in fact a non-EOP buffer.
 820 */
 821static bool
 822ice_is_non_eop(struct ice_ring *rx_ring, union ice_32b_rx_flex_desc *rx_desc,
 823	       struct sk_buff *skb)
 824{
 825	u32 ntc = rx_ring->next_to_clean + 1;
 826
 827	/* fetch, update, and store next to clean */
 828	ntc = (ntc < rx_ring->count) ? ntc : 0;
 829	rx_ring->next_to_clean = ntc;
 830
 831	prefetch(ICE_RX_DESC(rx_ring, ntc));
 832
 833	/* if we are the last buffer then there is nothing else to do */
 834#define ICE_RXD_EOF BIT(ICE_RX_FLEX_DESC_STATUS0_EOF_S)
 835	if (likely(ice_test_staterr(rx_desc, ICE_RXD_EOF)))
 836		return false;
 837
 838	/* place skb in next buffer to be received */
 839	rx_ring->rx_buf[ntc].skb = skb;
 840	rx_ring->rx_stats.non_eop_descs++;
 841
 842	return true;
 843}
 844
 845/**
 846 * ice_ptype_to_htype - get a hash type
 847 * @ptype: the ptype value from the descriptor
 848 *
 849 * Returns a hash type to be used by skb_set_hash
 850 */
 851static enum pkt_hash_types ice_ptype_to_htype(u8 __always_unused ptype)
 852{
 853	return PKT_HASH_TYPE_NONE;
 854}
 855
 856/**
 857 * ice_rx_hash - set the hash value in the skb
 858 * @rx_ring: descriptor ring
 859 * @rx_desc: specific descriptor
 860 * @skb: pointer to current skb
 861 * @rx_ptype: the ptype value from the descriptor
 862 */
 863static void
 864ice_rx_hash(struct ice_ring *rx_ring, union ice_32b_rx_flex_desc *rx_desc,
 865	    struct sk_buff *skb, u8 rx_ptype)
 866{
 867	struct ice_32b_rx_flex_desc_nic *nic_mdid;
 868	u32 hash;
 869
 870	if (!(rx_ring->netdev->features & NETIF_F_RXHASH))
 871		return;
 872
 873	if (rx_desc->wb.rxdid != ICE_RXDID_FLEX_NIC)
 874		return;
 875
 876	nic_mdid = (struct ice_32b_rx_flex_desc_nic *)rx_desc;
 877	hash = le32_to_cpu(nic_mdid->rss_hash);
 878	skb_set_hash(skb, hash, ice_ptype_to_htype(rx_ptype));
 879}
 880
 881/**
 882 * ice_rx_csum - Indicate in skb if checksum is good
 883 * @ring: the ring we care about
 884 * @skb: skb currently being received and modified
 885 * @rx_desc: the receive descriptor
 886 * @ptype: the packet type decoded by hardware
 887 *
 888 * skb->protocol must be set before this function is called
 889 */
 890static void
 891ice_rx_csum(struct ice_ring *ring, struct sk_buff *skb,
 892	    union ice_32b_rx_flex_desc *rx_desc, u8 ptype)
 893{
 894	struct ice_rx_ptype_decoded decoded;
 895	u32 rx_error, rx_status;
 896	bool ipv4, ipv6;
 897
 898	rx_status = le16_to_cpu(rx_desc->wb.status_error0);
 899	rx_error = rx_status;
 900
 901	decoded = ice_decode_rx_desc_ptype(ptype);
 902
 903	/* Start with CHECKSUM_NONE and by default csum_level = 0 */
 904	skb->ip_summed = CHECKSUM_NONE;
 905	skb_checksum_none_assert(skb);
 906
 907	/* check if Rx checksum is enabled */
 908	if (!(ring->netdev->features & NETIF_F_RXCSUM))
 909		return;
 910
 911	/* check if HW has decoded the packet and checksum */
 912	if (!(rx_status & BIT(ICE_RX_FLEX_DESC_STATUS0_L3L4P_S)))
 913		return;
 914
 915	if (!(decoded.known && decoded.outer_ip))
 916		return;
 917
 918	ipv4 = (decoded.outer_ip == ICE_RX_PTYPE_OUTER_IP) &&
 919	       (decoded.outer_ip_ver == ICE_RX_PTYPE_OUTER_IPV4);
 920	ipv6 = (decoded.outer_ip == ICE_RX_PTYPE_OUTER_IP) &&
 921	       (decoded.outer_ip_ver == ICE_RX_PTYPE_OUTER_IPV6);
 922
 923	if (ipv4 && (rx_error & (BIT(ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |
 924				 BIT(ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S))))
 925		goto checksum_fail;
 926	else if (ipv6 && (rx_status &
 927		 (BIT(ICE_RX_FLEX_DESC_STATUS0_IPV6EXADD_S))))
 928		goto checksum_fail;
 929
 930	/* check for L4 errors and handle packets that were not able to be
 931	 * checksummed due to arrival speed
 932	 */
 933	if (rx_error & BIT(ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S))
 934		goto checksum_fail;
 935
 936	/* Only report checksum unnecessary for TCP, UDP, or SCTP */
 937	switch (decoded.inner_prot) {
 938	case ICE_RX_PTYPE_INNER_PROT_TCP:
 939	case ICE_RX_PTYPE_INNER_PROT_UDP:
 940	case ICE_RX_PTYPE_INNER_PROT_SCTP:
 941		skb->ip_summed = CHECKSUM_UNNECESSARY;
 942	default:
 943		break;
 944	}
 945	return;
 946
 947checksum_fail:
 948	ring->vsi->back->hw_csum_rx_error++;
 949}
 950
 951/**
 952 * ice_process_skb_fields - Populate skb header fields from Rx descriptor
 953 * @rx_ring: Rx descriptor ring packet is being transacted on
 954 * @rx_desc: pointer to the EOP Rx descriptor
 955 * @skb: pointer to current skb being populated
 956 * @ptype: the packet type decoded by hardware
 957 *
 958 * This function checks the ring, descriptor, and packet information in
 959 * order to populate the hash, checksum, VLAN, protocol, and
 960 * other fields within the skb.
 961 */
 962static void
 963ice_process_skb_fields(struct ice_ring *rx_ring,
 964		       union ice_32b_rx_flex_desc *rx_desc,
 965		       struct sk_buff *skb, u8 ptype)
 966{
 967	ice_rx_hash(rx_ring, rx_desc, skb, ptype);
 968
 969	/* modifies the skb - consumes the enet header */
 970	skb->protocol = eth_type_trans(skb, rx_ring->netdev);
 971
 972	ice_rx_csum(rx_ring, skb, rx_desc, ptype);
 973}
 974
 975/**
 976 * ice_receive_skb - Send a completed packet up the stack
 977 * @rx_ring: Rx ring in play
 978 * @skb: packet to send up
 979 * @vlan_tag: VLAN tag for packet
 980 *
 981 * This function sends the completed packet (via. skb) up the stack using
 982 * gro receive functions (with/without VLAN tag)
 983 */
 984static void
 985ice_receive_skb(struct ice_ring *rx_ring, struct sk_buff *skb, u16 vlan_tag)
 986{
 987	if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
 988	    (vlan_tag & VLAN_VID_MASK))
 989		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
 990	napi_gro_receive(&rx_ring->q_vector->napi, skb);
 991}
 992
 993/**
 994 * ice_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
 995 * @rx_ring: Rx descriptor ring to transact packets on
 996 * @budget: Total limit on number of packets to process
 997 *
 998 * This function provides a "bounce buffer" approach to Rx interrupt
 999 * processing. The advantage to this is that on systems that have
1000 * expensive overhead for IOMMU access this provides a means of avoiding
1001 * it by maintaining the mapping of the page to the system.
1002 *
1003 * Returns amount of work completed
1004 */
1005static int ice_clean_rx_irq(struct ice_ring *rx_ring, int budget)
1006{
1007	unsigned int total_rx_bytes = 0, total_rx_pkts = 0;
1008	u16 cleaned_count = ICE_DESC_UNUSED(rx_ring);
 
 
 
 
 
 
 
1009	bool failure;
1010
 
 
 
 
 
 
1011	/* start the loop to process Rx packets bounded by 'budget' */
1012	while (likely(total_rx_pkts < (unsigned int)budget)) {
1013		union ice_32b_rx_flex_desc *rx_desc;
1014		struct ice_rx_buf *rx_buf;
1015		struct sk_buff *skb;
1016		unsigned int size;
1017		u16 stat_err_bits;
1018		u16 vlan_tag = 0;
1019		u8 rx_ptype;
1020
1021		/* get the Rx desc from Rx ring based on 'next_to_clean' */
1022		rx_desc = ICE_RX_DESC(rx_ring, rx_ring->next_to_clean);
1023
1024		/* status_error_len will always be zero for unused descriptors
1025		 * because it's cleared in cleanup, and overlaps with hdr_addr
1026		 * which is always zero because packet split isn't used, if the
1027		 * hardware wrote DD then it will be non-zero
1028		 */
1029		stat_err_bits = BIT(ICE_RX_FLEX_DESC_STATUS0_DD_S);
1030		if (!ice_test_staterr(rx_desc, stat_err_bits))
1031			break;
1032
1033		/* This memory barrier is needed to keep us from reading
1034		 * any other fields out of the rx_desc until we know the
1035		 * DD bit is set.
1036		 */
1037		dma_rmb();
1038
 
 
 
 
 
 
 
 
 
 
 
 
 
1039		size = le16_to_cpu(rx_desc->wb.pkt_len) &
1040			ICE_RX_FLX_DESC_PKT_LEN_M;
1041
1042		/* retrieve a buffer from the ring */
1043		rx_buf = ice_get_rx_buf(rx_ring, &skb, size);
1044
1045		if (skb)
1046			ice_add_rx_frag(rx_buf, skb, size);
1047		else
1048			skb = ice_construct_skb(rx_ring, rx_buf, size);
1049
1050		/* exit if we failed to retrieve a buffer */
1051		if (!skb) {
1052			rx_ring->rx_stats.alloc_buf_failed++;
1053			if (rx_buf)
1054				rx_buf->pagecnt_bias++;
 
1055			break;
1056		}
1057
1058		ice_put_rx_buf(rx_ring, rx_buf);
1059		cleaned_count++;
1060
1061		/* skip if it is NOP desc */
1062		if (ice_is_non_eop(rx_ring, rx_desc, skb))
1063			continue;
1064
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1065		stat_err_bits = BIT(ICE_RX_FLEX_DESC_STATUS0_RXE_S);
1066		if (unlikely(ice_test_staterr(rx_desc, stat_err_bits))) {
 
1067			dev_kfree_skb_any(skb);
1068			continue;
1069		}
1070
1071		stat_err_bits = BIT(ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S);
1072		if (ice_test_staterr(rx_desc, stat_err_bits))
1073			vlan_tag = le16_to_cpu(rx_desc->wb.l2tag1);
1074
1075		/* correct empty headers and pad skb if needed (to make valid
1076		 * ethernet frame
1077		 */
1078		if (ice_cleanup_headers(skb)) {
1079			skb = NULL;
1080			continue;
1081		}
1082
1083		/* probably a little skewed due to removing CRC */
1084		total_rx_bytes += skb->len;
1085
1086		/* populate checksum, VLAN, and protocol */
1087		rx_ptype = le16_to_cpu(rx_desc->wb.ptype_flex_flags0) &
1088			ICE_RX_FLEX_DESC_PTYPE_M;
1089
1090		ice_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype);
1091
 
1092		/* send completed skb up the stack */
1093		ice_receive_skb(rx_ring, skb, vlan_tag);
1094
1095		/* update budget accounting */
1096		total_rx_pkts++;
1097	}
1098
 
1099	/* return up to cleaned_count buffers to hardware */
1100	failure = ice_alloc_rx_bufs(rx_ring, cleaned_count);
1101
1102	/* update queue and vector specific stats */
1103	u64_stats_update_begin(&rx_ring->syncp);
1104	rx_ring->stats.pkts += total_rx_pkts;
1105	rx_ring->stats.bytes += total_rx_bytes;
1106	u64_stats_update_end(&rx_ring->syncp);
1107	rx_ring->q_vector->rx.total_pkts += total_rx_pkts;
1108	rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1109
1110	/* guarantee a trip back through this routine if there was a failure */
1111	return failure ? budget : (int)total_rx_pkts;
1112}
1113
1114/**
1115 * ice_adjust_itr_by_size_and_speed - Adjust ITR based on current traffic
1116 * @port_info: port_info structure containing the current link speed
1117 * @avg_pkt_size: average size of Tx or Rx packets based on clean routine
1118 * @itr: ITR value to update
1119 *
1120 * Calculate how big of an increment should be applied to the ITR value passed
1121 * in based on wmem_default, SKB overhead, Ethernet overhead, and the current
1122 * link speed.
1123 *
1124 * The following is a calculation derived from:
1125 *  wmem_default / (size + overhead) = desired_pkts_per_int
1126 *  rate / bits_per_byte / (size + Ethernet overhead) = pkt_rate
1127 *  (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
1128 *
1129 * Assuming wmem_default is 212992 and overhead is 640 bytes per
1130 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
1131 * formula down to:
1132 *
1133 *	 wmem_default * bits_per_byte * usecs_per_sec   pkt_size + 24
1134 * ITR = -------------------------------------------- * --------------
1135 *			     rate			pkt_size + 640
1136 */
1137static unsigned int
1138ice_adjust_itr_by_size_and_speed(struct ice_port_info *port_info,
1139				 unsigned int avg_pkt_size,
1140				 unsigned int itr)
1141{
1142	switch (port_info->phy.link_info.link_speed) {
1143	case ICE_AQ_LINK_SPEED_100GB:
1144		itr += DIV_ROUND_UP(17 * (avg_pkt_size + 24),
1145				    avg_pkt_size + 640);
1146		break;
1147	case ICE_AQ_LINK_SPEED_50GB:
1148		itr += DIV_ROUND_UP(34 * (avg_pkt_size + 24),
1149				    avg_pkt_size + 640);
1150		break;
1151	case ICE_AQ_LINK_SPEED_40GB:
1152		itr += DIV_ROUND_UP(43 * (avg_pkt_size + 24),
1153				    avg_pkt_size + 640);
1154		break;
1155	case ICE_AQ_LINK_SPEED_25GB:
1156		itr += DIV_ROUND_UP(68 * (avg_pkt_size + 24),
1157				    avg_pkt_size + 640);
1158		break;
1159	case ICE_AQ_LINK_SPEED_20GB:
1160		itr += DIV_ROUND_UP(85 * (avg_pkt_size + 24),
1161				    avg_pkt_size + 640);
1162		break;
1163	case ICE_AQ_LINK_SPEED_10GB:
1164		/* fall through */
1165	default:
1166		itr += DIV_ROUND_UP(170 * (avg_pkt_size + 24),
1167				    avg_pkt_size + 640);
1168		break;
1169	}
1170
1171	if ((itr & ICE_ITR_MASK) > ICE_ITR_ADAPTIVE_MAX_USECS) {
1172		itr &= ICE_ITR_ADAPTIVE_LATENCY;
1173		itr += ICE_ITR_ADAPTIVE_MAX_USECS;
1174	}
1175
1176	return itr;
 
 
 
 
 
 
1177}
1178
1179/**
1180 * ice_update_itr - update the adaptive ITR value based on statistics
1181 * @q_vector: structure containing interrupt and ring information
1182 * @rc: structure containing ring performance data
 
 
1183 *
1184 * Stores a new ITR value based on packets and byte
1185 * counts during the last interrupt.  The advantage of per interrupt
1186 * computation is faster updates and more accurate ITR for the current
1187 * traffic pattern.  Constants in this function were computed
1188 * based on theoretical maximum wire speed and thresholds were set based
1189 * on testing data as well as attempting to minimize response time
1190 * while increasing bulk throughput.
1191 */
1192static void
1193ice_update_itr(struct ice_q_vector *q_vector, struct ice_ring_container *rc)
1194{
1195	unsigned long next_update = jiffies;
1196	unsigned int packets, bytes, itr;
1197	bool container_is_rx;
1198
1199	if (!rc->ring || !ITR_IS_DYNAMIC(rc->itr_setting))
1200		return;
1201
1202	/* If itr_countdown is set it means we programmed an ITR within
1203	 * the last 4 interrupt cycles. This has a side effect of us
1204	 * potentially firing an early interrupt. In order to work around
1205	 * this we need to throw out any data received for a few
1206	 * interrupts following the update.
1207	 */
1208	if (q_vector->itr_countdown) {
1209		itr = rc->target_itr;
1210		goto clear_counts;
1211	}
1212
1213	container_is_rx = (&q_vector->rx == rc);
1214	/* For Rx we want to push the delay up and default to low latency.
1215	 * for Tx we want to pull the delay down and default to high latency.
1216	 */
1217	itr = container_is_rx ?
1218		ICE_ITR_ADAPTIVE_MIN_USECS | ICE_ITR_ADAPTIVE_LATENCY :
1219		ICE_ITR_ADAPTIVE_MAX_USECS | ICE_ITR_ADAPTIVE_LATENCY;
1220
1221	/* If we didn't update within up to 1 - 2 jiffies we can assume
1222	 * that either packets are coming in so slow there hasn't been
1223	 * any work, or that there is so much work that NAPI is dealing
1224	 * with interrupt moderation and we don't need to do anything.
1225	 */
1226	if (time_after(next_update, rc->next_update))
1227		goto clear_counts;
1228
1229	prefetch(q_vector->vsi->port_info);
1230
1231	packets = rc->total_pkts;
1232	bytes = rc->total_bytes;
1233
1234	if (container_is_rx) {
1235		/* If Rx there are 1 to 4 packets and bytes are less than
1236		 * 9000 assume insufficient data to use bulk rate limiting
1237		 * approach unless Tx is already in bulk rate limiting. We
1238		 * are likely latency driven.
1239		 */
1240		if (packets && packets < 4 && bytes < 9000 &&
1241		    (q_vector->tx.target_itr & ICE_ITR_ADAPTIVE_LATENCY)) {
1242			itr = ICE_ITR_ADAPTIVE_LATENCY;
1243			goto adjust_by_size_and_speed;
1244		}
1245	} else if (packets < 4) {
1246		/* If we have Tx and Rx ITR maxed and Tx ITR is running in
1247		 * bulk mode and we are receiving 4 or fewer packets just
1248		 * reset the ITR_ADAPTIVE_LATENCY bit for latency mode so
1249		 * that the Rx can relax.
1250		 */
1251		if (rc->target_itr == ICE_ITR_ADAPTIVE_MAX_USECS &&
1252		    (q_vector->rx.target_itr & ICE_ITR_MASK) ==
1253		    ICE_ITR_ADAPTIVE_MAX_USECS)
1254			goto clear_counts;
1255	} else if (packets > 32) {
1256		/* If we have processed over 32 packets in a single interrupt
1257		 * for Tx assume we need to switch over to "bulk" mode.
1258		 */
1259		rc->target_itr &= ~ICE_ITR_ADAPTIVE_LATENCY;
1260	}
1261
1262	/* We have no packets to actually measure against. This means
1263	 * either one of the other queues on this vector is active or
1264	 * we are a Tx queue doing TSO with too high of an interrupt rate.
1265	 *
1266	 * Between 4 and 56 we can assume that our current interrupt delay
1267	 * is only slightly too low. As such we should increase it by a small
1268	 * fixed amount.
1269	 */
1270	if (packets < 56) {
1271		itr = rc->target_itr + ICE_ITR_ADAPTIVE_MIN_INC;
1272		if ((itr & ICE_ITR_MASK) > ICE_ITR_ADAPTIVE_MAX_USECS) {
1273			itr &= ICE_ITR_ADAPTIVE_LATENCY;
1274			itr += ICE_ITR_ADAPTIVE_MAX_USECS;
1275		}
1276		goto clear_counts;
1277	}
1278
1279	if (packets <= 256) {
1280		itr = min(q_vector->tx.current_itr, q_vector->rx.current_itr);
1281		itr &= ICE_ITR_MASK;
1282
1283		/* Between 56 and 112 is our "goldilocks" zone where we are
1284		 * working out "just right". Just report that our current
1285		 * ITR is good for us.
1286		 */
1287		if (packets <= 112)
1288			goto clear_counts;
1289
1290		/* If packet count is 128 or greater we are likely looking
1291		 * at a slight overrun of the delay we want. Try halving
1292		 * our delay to see if that will cut the number of packets
1293		 * in half per interrupt.
1294		 */
1295		itr >>= 1;
1296		itr &= ICE_ITR_MASK;
1297		if (itr < ICE_ITR_ADAPTIVE_MIN_USECS)
1298			itr = ICE_ITR_ADAPTIVE_MIN_USECS;
1299
1300		goto clear_counts;
 
1301	}
1302
1303	/* The paths below assume we are dealing with a bulk ITR since
1304	 * number of packets is greater than 256. We are just going to have
1305	 * to compute a value and try to bring the count under control,
1306	 * though for smaller packet sizes there isn't much we can do as
1307	 * NAPI polling will likely be kicking in sooner rather than later.
1308	 */
1309	itr = ICE_ITR_ADAPTIVE_BULK;
1310
1311adjust_by_size_and_speed:
1312
1313	/* based on checks above packets cannot be 0 so division is safe */
1314	itr = ice_adjust_itr_by_size_and_speed(q_vector->vsi->port_info,
1315					       bytes / packets, itr);
1316
1317clear_counts:
1318	/* write back value */
1319	rc->target_itr = itr;
1320
1321	/* next update should occur within next jiffy */
1322	rc->next_update = next_update + 1;
1323
1324	rc->total_bytes = 0;
1325	rc->total_pkts = 0;
1326}
1327
1328/**
1329 * ice_buildreg_itr - build value for writing to the GLINT_DYN_CTL register
1330 * @itr_idx: interrupt throttling index
1331 * @itr: interrupt throttling value in usecs
1332 */
1333static u32 ice_buildreg_itr(u16 itr_idx, u16 itr)
1334{
1335	/* The ITR value is reported in microseconds, and the register value is
1336	 * recorded in 2 microsecond units. For this reason we only need to
1337	 * shift by the GLINT_DYN_CTL_INTERVAL_S - ICE_ITR_GRAN_S to apply this
1338	 * granularity as a shift instead of division. The mask makes sure the
1339	 * ITR value is never odd so we don't accidentally write into the field
1340	 * prior to the ITR field.
1341	 */
1342	itr &= ICE_ITR_MASK;
1343
1344	return GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
1345		(itr_idx << GLINT_DYN_CTL_ITR_INDX_S) |
1346		(itr << (GLINT_DYN_CTL_INTERVAL_S - ICE_ITR_GRAN_S));
1347}
1348
1349/* The act of updating the ITR will cause it to immediately trigger. In order
1350 * to prevent this from throwing off adaptive update statistics we defer the
1351 * update so that it can only happen so often. So after either Tx or Rx are
1352 * updated we make the adaptive scheme wait until either the ITR completely
1353 * expires via the next_update expiration or we have been through at least
1354 * 3 interrupts.
1355 */
1356#define ITR_COUNTDOWN_START 3
1357
1358/**
1359 * ice_update_ena_itr - Update ITR and re-enable MSIX interrupt
1360 * @q_vector: q_vector for which ITR is being updated and interrupt enabled
 
 
 
 
1361 */
1362static void ice_update_ena_itr(struct ice_q_vector *q_vector)
1363{
1364	struct ice_ring_container *tx = &q_vector->tx;
1365	struct ice_ring_container *rx = &q_vector->rx;
1366	struct ice_vsi *vsi = q_vector->vsi;
 
1367	u32 itr_val;
1368
1369	/* when exiting WB_ON_ITR lets set a low ITR value and trigger
1370	 * interrupts to expire right away in case we have more work ready to go
1371	 * already
1372	 */
1373	if (q_vector->itr_countdown == ICE_IN_WB_ON_ITR_MODE) {
1374		itr_val = ice_buildreg_itr(rx->itr_idx, ICE_WB_ON_ITR_USECS);
1375		wr32(&vsi->back->hw, GLINT_DYN_CTL(q_vector->reg_idx), itr_val);
1376		/* set target back to last user set value */
1377		rx->target_itr = rx->itr_setting;
1378		/* set current to what we just wrote and dynamic if needed */
1379		rx->current_itr = ICE_WB_ON_ITR_USECS |
1380			(rx->itr_setting & ICE_ITR_DYNAMIC);
1381		/* allow normal interrupt flow to start */
1382		q_vector->itr_countdown = 0;
1383		return;
1384	}
1385
1386	/* This will do nothing if dynamic updates are not enabled */
1387	ice_update_itr(q_vector, tx);
1388	ice_update_itr(q_vector, rx);
1389
1390	/* This block of logic allows us to get away with only updating
1391	 * one ITR value with each interrupt. The idea is to perform a
1392	 * pseudo-lazy update with the following criteria.
1393	 *
1394	 * 1. Rx is given higher priority than Tx if both are in same state
1395	 * 2. If we must reduce an ITR that is given highest priority.
1396	 * 3. We then give priority to increasing ITR based on amount.
1397	 */
1398	if (rx->target_itr < rx->current_itr) {
1399		/* Rx ITR needs to be reduced, this is highest priority */
1400		itr_val = ice_buildreg_itr(rx->itr_idx, rx->target_itr);
1401		rx->current_itr = rx->target_itr;
1402		q_vector->itr_countdown = ITR_COUNTDOWN_START;
1403	} else if ((tx->target_itr < tx->current_itr) ||
1404		   ((rx->target_itr - rx->current_itr) <
1405		    (tx->target_itr - tx->current_itr))) {
1406		/* Tx ITR needs to be reduced, this is second priority
1407		 * Tx ITR needs to be increased more than Rx, fourth priority
1408		 */
1409		itr_val = ice_buildreg_itr(tx->itr_idx, tx->target_itr);
1410		tx->current_itr = tx->target_itr;
1411		q_vector->itr_countdown = ITR_COUNTDOWN_START;
1412	} else if (rx->current_itr != rx->target_itr) {
1413		/* Rx ITR needs to be increased, third priority */
1414		itr_val = ice_buildreg_itr(rx->itr_idx, rx->target_itr);
1415		rx->current_itr = rx->target_itr;
1416		q_vector->itr_countdown = ITR_COUNTDOWN_START;
1417	} else {
1418		/* Still have to re-enable the interrupts */
1419		itr_val = ice_buildreg_itr(ICE_ITR_NONE, 0);
1420		if (q_vector->itr_countdown)
1421			q_vector->itr_countdown--;
1422	}
1423
1424	if (!test_bit(__ICE_DOWN, q_vector->vsi->state))
1425		wr32(&q_vector->vsi->back->hw,
1426		     GLINT_DYN_CTL(q_vector->reg_idx),
1427		     itr_val);
1428}
1429
1430/**
1431 * ice_set_wb_on_itr - set WB_ON_ITR for this q_vector
1432 * @q_vector: q_vector to set WB_ON_ITR on
1433 *
1434 * We need to tell hardware to write-back completed descriptors even when
1435 * interrupts are disabled. Descriptors will be written back on cache line
1436 * boundaries without WB_ON_ITR enabled, but if we don't enable WB_ON_ITR
1437 * descriptors may not be written back if they don't fill a cache line until the
1438 * next interrupt.
1439 *
1440 * This sets the write-back frequency to 2 microseconds as that is the minimum
1441 * value that's not 0 due to ITR granularity. Also, set the INTENA_MSK bit to
1442 * make sure hardware knows we aren't meddling with the INTENA_M bit.
1443 */
1444static void ice_set_wb_on_itr(struct ice_q_vector *q_vector)
1445{
1446	struct ice_vsi *vsi = q_vector->vsi;
1447
1448	/* already in WB_ON_ITR mode no need to change it */
1449	if (q_vector->itr_countdown == ICE_IN_WB_ON_ITR_MODE)
1450		return;
1451
1452	if (q_vector->num_ring_rx)
1453		wr32(&vsi->back->hw, GLINT_DYN_CTL(q_vector->reg_idx),
1454		     ICE_GLINT_DYN_CTL_WB_ON_ITR(ICE_WB_ON_ITR_USECS,
1455						 ICE_RX_ITR));
1456
1457	if (q_vector->num_ring_tx)
1458		wr32(&vsi->back->hw, GLINT_DYN_CTL(q_vector->reg_idx),
1459		     ICE_GLINT_DYN_CTL_WB_ON_ITR(ICE_WB_ON_ITR_USECS,
1460						 ICE_TX_ITR));
1461
1462	q_vector->itr_countdown = ICE_IN_WB_ON_ITR_MODE;
1463}
1464
1465/**
1466 * ice_napi_poll - NAPI polling Rx/Tx cleanup routine
1467 * @napi: napi struct with our devices info in it
1468 * @budget: amount of work driver is allowed to do this pass, in packets
1469 *
1470 * This function will clean all queues associated with a q_vector.
1471 *
1472 * Returns the amount of work done
1473 */
1474int ice_napi_poll(struct napi_struct *napi, int budget)
1475{
1476	struct ice_q_vector *q_vector =
1477				container_of(napi, struct ice_q_vector, napi);
 
 
1478	bool clean_complete = true;
1479	struct ice_ring *ring;
1480	int budget_per_ring;
1481	int work_done = 0;
1482
1483	/* Since the actual Tx work is minimal, we can give the Tx a larger
1484	 * budget and be more aggressive about cleaning up the Tx descriptors.
1485	 */
1486	ice_for_each_ring(ring, q_vector->tx)
1487		if (!ice_clean_tx_irq(ring, budget))
 
 
 
 
 
 
 
 
 
 
1488			clean_complete = false;
 
1489
1490	/* Handle case where we are called by netpoll with a budget of 0 */
1491	if (unlikely(budget <= 0))
1492		return budget;
1493
1494	/* normally we have 1 Rx ring per q_vector */
1495	if (unlikely(q_vector->num_ring_rx > 1))
1496		/* We attempt to distribute budget to each Rx queue fairly, but
1497		 * don't allow the budget to go below 1 because that would exit
1498		 * polling early.
1499		 */
1500		budget_per_ring = max(budget / q_vector->num_ring_rx, 1);
1501	else
1502		/* Max of 1 Rx ring in this q_vector so give it the budget */
1503		budget_per_ring = budget;
1504
1505	ice_for_each_ring(ring, q_vector->rx) {
 
1506		int cleaned;
1507
1508		cleaned = ice_clean_rx_irq(ring, budget_per_ring);
 
 
 
 
 
 
1509		work_done += cleaned;
1510		/* if we clean as many as budgeted, we must not be done */
1511		if (cleaned >= budget_per_ring)
1512			clean_complete = false;
1513	}
1514
1515	/* If work not completed, return budget and polling will return */
1516	if (!clean_complete)
 
 
 
 
1517		return budget;
 
1518
1519	/* Exit the polling mode, but don't re-enable interrupts if stack might
1520	 * poll us due to busy-polling
1521	 */
1522	if (likely(napi_complete_done(napi, work_done)))
1523		ice_update_ena_itr(q_vector);
1524	else
 
1525		ice_set_wb_on_itr(q_vector);
 
1526
1527	return min_t(int, work_done, budget - 1);
1528}
1529
1530/* helper function for building cmd/type/offset */
1531static __le64
1532build_ctob(u64 td_cmd, u64 td_offset, unsigned int size, u64 td_tag)
1533{
1534	return cpu_to_le64(ICE_TX_DESC_DTYPE_DATA |
1535			   (td_cmd    << ICE_TXD_QW1_CMD_S) |
1536			   (td_offset << ICE_TXD_QW1_OFFSET_S) |
1537			   ((u64)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
1538			   (td_tag    << ICE_TXD_QW1_L2TAG1_S));
1539}
1540
1541/**
1542 * __ice_maybe_stop_tx - 2nd level check for Tx stop conditions
1543 * @tx_ring: the ring to be checked
1544 * @size: the size buffer we want to assure is available
1545 *
1546 * Returns -EBUSY if a stop is needed, else 0
1547 */
1548static int __ice_maybe_stop_tx(struct ice_ring *tx_ring, unsigned int size)
1549{
1550	netif_stop_subqueue(tx_ring->netdev, tx_ring->q_index);
1551	/* Memory barrier before checking head and tail */
1552	smp_mb();
1553
1554	/* Check again in a case another CPU has just made room available. */
1555	if (likely(ICE_DESC_UNUSED(tx_ring) < size))
1556		return -EBUSY;
1557
1558	/* A reprieve! - use start_subqueue because it doesn't call schedule */
1559	netif_start_subqueue(tx_ring->netdev, tx_ring->q_index);
1560	++tx_ring->tx_stats.restart_q;
1561	return 0;
1562}
1563
1564/**
1565 * ice_maybe_stop_tx - 1st level check for Tx stop conditions
1566 * @tx_ring: the ring to be checked
1567 * @size:    the size buffer we want to assure is available
1568 *
1569 * Returns 0 if stop is not needed
1570 */
1571static int ice_maybe_stop_tx(struct ice_ring *tx_ring, unsigned int size)
1572{
1573	if (likely(ICE_DESC_UNUSED(tx_ring) >= size))
1574		return 0;
1575
1576	return __ice_maybe_stop_tx(tx_ring, size);
1577}
1578
1579/**
1580 * ice_tx_map - Build the Tx descriptor
1581 * @tx_ring: ring to send buffer on
1582 * @first: first buffer info buffer to use
1583 * @off: pointer to struct that holds offload parameters
1584 *
1585 * This function loops over the skb data pointed to by *first
1586 * and gets a physical address for each memory location and programs
1587 * it and the length into the transmit descriptor.
1588 */
1589static void
1590ice_tx_map(struct ice_ring *tx_ring, struct ice_tx_buf *first,
1591	   struct ice_tx_offload_params *off)
1592{
1593	u64 td_offset, td_tag, td_cmd;
1594	u16 i = tx_ring->next_to_use;
1595	skb_frag_t *frag;
1596	unsigned int data_len, size;
1597	struct ice_tx_desc *tx_desc;
1598	struct ice_tx_buf *tx_buf;
1599	struct sk_buff *skb;
 
1600	dma_addr_t dma;
 
1601
1602	td_tag = off->td_l2tag1;
1603	td_cmd = off->td_cmd;
1604	td_offset = off->td_offset;
1605	skb = first->skb;
1606
1607	data_len = skb->data_len;
1608	size = skb_headlen(skb);
1609
1610	tx_desc = ICE_TX_DESC(tx_ring, i);
1611
1612	if (first->tx_flags & ICE_TX_FLAGS_HW_VLAN) {
1613		td_cmd |= (u64)ICE_TX_DESC_CMD_IL2TAG1;
1614		td_tag = (first->tx_flags & ICE_TX_FLAGS_VLAN_M) >>
1615			  ICE_TX_FLAGS_VLAN_S;
1616	}
1617
1618	dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1619
1620	tx_buf = first;
1621
1622	for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1623		unsigned int max_data = ICE_MAX_DATA_PER_TXD_ALIGNED;
1624
1625		if (dma_mapping_error(tx_ring->dev, dma))
1626			goto dma_error;
1627
1628		/* record length, and DMA address */
1629		dma_unmap_len_set(tx_buf, len, size);
1630		dma_unmap_addr_set(tx_buf, dma, dma);
1631
1632		/* align size to end of page */
1633		max_data += -dma & (ICE_MAX_READ_REQ_SIZE - 1);
1634		tx_desc->buf_addr = cpu_to_le64(dma);
1635
1636		/* account for data chunks larger than the hardware
1637		 * can handle
1638		 */
1639		while (unlikely(size > ICE_MAX_DATA_PER_TXD)) {
1640			tx_desc->cmd_type_offset_bsz =
1641				build_ctob(td_cmd, td_offset, max_data, td_tag);
 
1642
1643			tx_desc++;
1644			i++;
1645
1646			if (i == tx_ring->count) {
1647				tx_desc = ICE_TX_DESC(tx_ring, 0);
1648				i = 0;
1649			}
1650
1651			dma += max_data;
1652			size -= max_data;
1653
1654			max_data = ICE_MAX_DATA_PER_TXD_ALIGNED;
1655			tx_desc->buf_addr = cpu_to_le64(dma);
1656		}
1657
1658		if (likely(!data_len))
1659			break;
1660
1661		tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1662							  size, td_tag);
1663
1664		tx_desc++;
1665		i++;
1666
1667		if (i == tx_ring->count) {
1668			tx_desc = ICE_TX_DESC(tx_ring, 0);
1669			i = 0;
1670		}
1671
1672		size = skb_frag_size(frag);
1673		data_len -= size;
1674
1675		dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1676				       DMA_TO_DEVICE);
1677
1678		tx_buf = &tx_ring->tx_buf[i];
 
1679	}
1680
1681	/* record bytecount for BQL */
1682	netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
1683
1684	/* record SW timestamp if HW timestamp is not available */
1685	skb_tx_timestamp(first->skb);
1686
1687	i++;
1688	if (i == tx_ring->count)
1689		i = 0;
1690
1691	/* write last descriptor with RS and EOP bits */
1692	td_cmd |= (u64)(ICE_TX_DESC_CMD_EOP | ICE_TX_DESC_CMD_RS);
1693	tx_desc->cmd_type_offset_bsz =
1694			build_ctob(td_cmd, td_offset, size, td_tag);
1695
1696	/* Force memory writes to complete before letting h/w know there
1697	 * are new descriptors to fetch.
1698	 *
1699	 * We also use this memory barrier to make certain all of the
1700	 * status bits have been updated before next_to_watch is written.
1701	 */
1702	wmb();
1703
1704	/* set next_to_watch value indicating a packet is present */
1705	first->next_to_watch = tx_desc;
1706
1707	tx_ring->next_to_use = i;
1708
1709	ice_maybe_stop_tx(tx_ring, DESC_NEEDED);
1710
1711	/* notify HW of packet */
1712	if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
 
 
 
1713		writel(i, tx_ring->tail);
1714	}
1715
1716	return;
1717
1718dma_error:
1719	/* clear DMA mappings for failed tx_buf map */
1720	for (;;) {
1721		tx_buf = &tx_ring->tx_buf[i];
1722		ice_unmap_and_free_tx_buf(tx_ring, tx_buf);
1723		if (tx_buf == first)
1724			break;
1725		if (i == 0)
1726			i = tx_ring->count;
1727		i--;
1728	}
1729
1730	tx_ring->next_to_use = i;
1731}
1732
1733/**
1734 * ice_tx_csum - Enable Tx checksum offloads
1735 * @first: pointer to the first descriptor
1736 * @off: pointer to struct that holds offload parameters
1737 *
1738 * Returns 0 or error (negative) if checksum offload can't happen, 1 otherwise.
1739 */
1740static
1741int ice_tx_csum(struct ice_tx_buf *first, struct ice_tx_offload_params *off)
1742{
1743	u32 l4_len = 0, l3_len = 0, l2_len = 0;
1744	struct sk_buff *skb = first->skb;
1745	union {
1746		struct iphdr *v4;
1747		struct ipv6hdr *v6;
1748		unsigned char *hdr;
1749	} ip;
1750	union {
1751		struct tcphdr *tcp;
1752		unsigned char *hdr;
1753	} l4;
1754	__be16 frag_off, protocol;
1755	unsigned char *exthdr;
1756	u32 offset, cmd = 0;
1757	u8 l4_proto = 0;
1758
1759	if (skb->ip_summed != CHECKSUM_PARTIAL)
1760		return 0;
1761
1762	ip.hdr = skb_network_header(skb);
1763	l4.hdr = skb_transport_header(skb);
 
 
 
 
 
 
 
1764
1765	/* compute outer L2 header size */
1766	l2_len = ip.hdr - skb->data;
1767	offset = (l2_len / 2) << ICE_TX_DESC_LEN_MACLEN_S;
1768
1769	if (skb->encapsulation)
1770		return -1;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1771
1772	/* Enable IP checksum offloads */
1773	protocol = vlan_get_protocol(skb);
1774	if (protocol == htons(ETH_P_IP)) {
1775		l4_proto = ip.v4->protocol;
1776		/* the stack computes the IP header already, the only time we
1777		 * need the hardware to recompute it is in the case of TSO.
1778		 */
1779		if (first->tx_flags & ICE_TX_FLAGS_TSO)
1780			cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
1781		else
1782			cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
1783
1784	} else if (protocol == htons(ETH_P_IPV6)) {
1785		cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
1786		exthdr = ip.hdr + sizeof(*ip.v6);
1787		l4_proto = ip.v6->nexthdr;
1788		if (l4.hdr != exthdr)
1789			ipv6_skip_exthdr(skb, exthdr - skb->data, &l4_proto,
1790					 &frag_off);
1791	} else {
1792		return -1;
1793	}
1794
1795	/* compute inner L3 header size */
1796	l3_len = l4.hdr - ip.hdr;
1797	offset |= (l3_len / 4) << ICE_TX_DESC_LEN_IPLEN_S;
1798
1799	/* Enable L4 checksum offloads */
1800	switch (l4_proto) {
1801	case IPPROTO_TCP:
1802		/* enable checksum offloads */
1803		cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1804		l4_len = l4.tcp->doff;
1805		offset |= l4_len << ICE_TX_DESC_LEN_L4_LEN_S;
1806		break;
1807	case IPPROTO_UDP:
1808		/* enable UDP checksum offload */
1809		cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
1810		l4_len = (sizeof(struct udphdr) >> 2);
1811		offset |= l4_len << ICE_TX_DESC_LEN_L4_LEN_S;
1812		break;
1813	case IPPROTO_SCTP:
1814		/* enable SCTP checksum offload */
1815		cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
1816		l4_len = sizeof(struct sctphdr) >> 2;
1817		offset |= l4_len << ICE_TX_DESC_LEN_L4_LEN_S;
1818		break;
1819
1820	default:
1821		if (first->tx_flags & ICE_TX_FLAGS_TSO)
1822			return -1;
1823		skb_checksum_help(skb);
1824		return 0;
1825	}
1826
1827	off->td_cmd |= cmd;
1828	off->td_offset |= offset;
1829	return 1;
1830}
1831
1832/**
1833 * ice_tx_prepare_vlan_flags - prepare generic Tx VLAN tagging flags for HW
1834 * @tx_ring: ring to send buffer on
1835 * @first: pointer to struct ice_tx_buf
1836 *
1837 * Checks the skb and set up correspondingly several generic transmit flags
1838 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1839 *
1840 * Returns error code indicate the frame should be dropped upon error and the
1841 * otherwise returns 0 to indicate the flags has been set properly.
1842 */
1843static int
1844ice_tx_prepare_vlan_flags(struct ice_ring *tx_ring, struct ice_tx_buf *first)
1845{
1846	struct sk_buff *skb = first->skb;
1847	__be16 protocol = skb->protocol;
1848
1849	if (protocol == htons(ETH_P_8021Q) &&
1850	    !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1851		/* when HW VLAN acceleration is turned off by the user the
1852		 * stack sets the protocol to 8021q so that the driver
1853		 * can take any steps required to support the SW only
1854		 * VLAN handling. In our case the driver doesn't need
1855		 * to take any further steps so just set the protocol
1856		 * to the encapsulated ethertype.
1857		 */
1858		skb->protocol = vlan_get_protocol(skb);
1859		return 0;
1860	}
1861
1862	/* if we have a HW VLAN tag being added, default to the HW one */
 
 
 
1863	if (skb_vlan_tag_present(skb)) {
1864		first->tx_flags |= skb_vlan_tag_get(skb) << ICE_TX_FLAGS_VLAN_S;
1865		first->tx_flags |= ICE_TX_FLAGS_HW_VLAN;
1866	} else if (protocol == htons(ETH_P_8021Q)) {
1867		struct vlan_hdr *vhdr, _vhdr;
1868
1869		/* for SW VLAN, check the next protocol and store the tag */
1870		vhdr = (struct vlan_hdr *)skb_header_pointer(skb, ETH_HLEN,
1871							     sizeof(_vhdr),
1872							     &_vhdr);
1873		if (!vhdr)
1874			return -EINVAL;
1875
1876		first->tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
1877				   ICE_TX_FLAGS_VLAN_S;
1878		first->tx_flags |= ICE_TX_FLAGS_SW_VLAN;
1879	}
1880
1881	return ice_tx_prepare_vlan_flags_dcb(tx_ring, first);
1882}
1883
1884/**
1885 * ice_tso - computes mss and TSO length to prepare for TSO
1886 * @first: pointer to struct ice_tx_buf
1887 * @off: pointer to struct that holds offload parameters
1888 *
1889 * Returns 0 or error (negative) if TSO can't happen, 1 otherwise.
1890 */
1891static
1892int ice_tso(struct ice_tx_buf *first, struct ice_tx_offload_params *off)
1893{
1894	struct sk_buff *skb = first->skb;
1895	union {
1896		struct iphdr *v4;
1897		struct ipv6hdr *v6;
1898		unsigned char *hdr;
1899	} ip;
1900	union {
1901		struct tcphdr *tcp;
 
1902		unsigned char *hdr;
1903	} l4;
1904	u64 cd_mss, cd_tso_len;
1905	u32 paylen, l4_start;
 
 
1906	int err;
1907
1908	if (skb->ip_summed != CHECKSUM_PARTIAL)
1909		return 0;
1910
1911	if (!skb_is_gso(skb))
1912		return 0;
1913
1914	err = skb_cow_head(skb, 0);
1915	if (err < 0)
1916		return err;
1917
1918	/* cppcheck-suppress unreadVariable */
1919	ip.hdr = skb_network_header(skb);
1920	l4.hdr = skb_transport_header(skb);
 
 
 
 
1921
1922	/* initialize outer IP header fields */
1923	if (ip.v4->version == 4) {
1924		ip.v4->tot_len = 0;
1925		ip.v4->check = 0;
1926	} else {
1927		ip.v6->payload_len = 0;
1928	}
1929
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1930	/* determine offset of transport header */
1931	l4_start = l4.hdr - skb->data;
1932
1933	/* remove payload length from checksum */
1934	paylen = skb->len - l4_start;
1935	csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen));
1936
1937	/* compute length of segmentation header */
1938	off->header_len = (l4.tcp->doff * 4) + l4_start;
 
 
 
 
 
 
 
 
 
1939
1940	/* update gso_segs and bytecount */
1941	first->gso_segs = skb_shinfo(skb)->gso_segs;
1942	first->bytecount += (first->gso_segs - 1) * off->header_len;
1943
1944	cd_tso_len = skb->len - off->header_len;
1945	cd_mss = skb_shinfo(skb)->gso_size;
1946
1947	/* record cdesc_qw1 with TSO parameters */
1948	off->cd_qw1 |= (u64)(ICE_TX_DESC_DTYPE_CTX |
1949			     (ICE_TX_CTX_DESC_TSO << ICE_TXD_CTX_QW1_CMD_S) |
1950			     (cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
1951			     (cd_mss << ICE_TXD_CTX_QW1_MSS_S));
1952	first->tx_flags |= ICE_TX_FLAGS_TSO;
1953	return 1;
1954}
1955
1956/**
1957 * ice_txd_use_count  - estimate the number of descriptors needed for Tx
1958 * @size: transmit request size in bytes
1959 *
1960 * Due to hardware alignment restrictions (4K alignment), we need to
1961 * assume that we can have no more than 12K of data per descriptor, even
1962 * though each descriptor can take up to 16K - 1 bytes of aligned memory.
1963 * Thus, we need to divide by 12K. But division is slow! Instead,
1964 * we decompose the operation into shifts and one relatively cheap
1965 * multiply operation.
1966 *
1967 * To divide by 12K, we first divide by 4K, then divide by 3:
1968 *     To divide by 4K, shift right by 12 bits
1969 *     To divide by 3, multiply by 85, then divide by 256
1970 *     (Divide by 256 is done by shifting right by 8 bits)
1971 * Finally, we add one to round up. Because 256 isn't an exact multiple of
1972 * 3, we'll underestimate near each multiple of 12K. This is actually more
1973 * accurate as we have 4K - 1 of wiggle room that we can fit into the last
1974 * segment. For our purposes this is accurate out to 1M which is orders of
1975 * magnitude greater than our largest possible GSO size.
1976 *
1977 * This would then be implemented as:
1978 *     return (((size >> 12) * 85) >> 8) + ICE_DESCS_FOR_SKB_DATA_PTR;
1979 *
1980 * Since multiplication and division are commutative, we can reorder
1981 * operations into:
1982 *     return ((size * 85) >> 20) + ICE_DESCS_FOR_SKB_DATA_PTR;
1983 */
1984static unsigned int ice_txd_use_count(unsigned int size)
1985{
1986	return ((size * 85) >> 20) + ICE_DESCS_FOR_SKB_DATA_PTR;
1987}
1988
1989/**
1990 * ice_xmit_desc_count - calculate number of Tx descriptors needed
1991 * @skb: send buffer
1992 *
1993 * Returns number of data descriptors needed for this skb.
1994 */
1995static unsigned int ice_xmit_desc_count(struct sk_buff *skb)
1996{
1997	const skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
1998	unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
1999	unsigned int count = 0, size = skb_headlen(skb);
2000
2001	for (;;) {
2002		count += ice_txd_use_count(size);
2003
2004		if (!nr_frags--)
2005			break;
2006
2007		size = skb_frag_size(frag++);
2008	}
2009
2010	return count;
2011}
2012
2013/**
2014 * __ice_chk_linearize - Check if there are more than 8 buffers per packet
2015 * @skb: send buffer
2016 *
2017 * Note: This HW can't DMA more than 8 buffers to build a packet on the wire
2018 * and so we need to figure out the cases where we need to linearize the skb.
2019 *
2020 * For TSO we need to count the TSO header and segment payload separately.
2021 * As such we need to check cases where we have 7 fragments or more as we
2022 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
2023 * the segment payload in the first descriptor, and another 7 for the
2024 * fragments.
2025 */
2026static bool __ice_chk_linearize(struct sk_buff *skb)
2027{
2028	const skb_frag_t *frag, *stale;
2029	int nr_frags, sum;
2030
2031	/* no need to check if number of frags is less than 7 */
2032	nr_frags = skb_shinfo(skb)->nr_frags;
2033	if (nr_frags < (ICE_MAX_BUF_TXD - 1))
2034		return false;
2035
2036	/* We need to walk through the list and validate that each group
2037	 * of 6 fragments totals at least gso_size.
2038	 */
2039	nr_frags -= ICE_MAX_BUF_TXD - 2;
2040	frag = &skb_shinfo(skb)->frags[0];
2041
2042	/* Initialize size to the negative value of gso_size minus 1. We
2043	 * use this as the worst case scenerio in which the frag ahead
2044	 * of us only provides one byte which is why we are limited to 6
2045	 * descriptors for a single transmit as the header and previous
2046	 * fragment are already consuming 2 descriptors.
2047	 */
2048	sum = 1 - skb_shinfo(skb)->gso_size;
2049
2050	/* Add size of frags 0 through 4 to create our initial sum */
2051	sum += skb_frag_size(frag++);
2052	sum += skb_frag_size(frag++);
2053	sum += skb_frag_size(frag++);
2054	sum += skb_frag_size(frag++);
2055	sum += skb_frag_size(frag++);
2056
2057	/* Walk through fragments adding latest fragment, testing it, and
2058	 * then removing stale fragments from the sum.
2059	 */
2060	stale = &skb_shinfo(skb)->frags[0];
2061	for (;;) {
 
2062		sum += skb_frag_size(frag++);
2063
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2064		/* if sum is negative we failed to make sufficient progress */
2065		if (sum < 0)
2066			return true;
2067
2068		if (!nr_frags--)
2069			break;
2070
2071		sum -= skb_frag_size(stale++);
2072	}
2073
2074	return false;
2075}
2076
2077/**
2078 * ice_chk_linearize - Check if there are more than 8 fragments per packet
2079 * @skb:      send buffer
2080 * @count:    number of buffers used
2081 *
2082 * Note: Our HW can't scatter-gather more than 8 fragments to build
2083 * a packet on the wire and so we need to figure out the cases where we
2084 * need to linearize the skb.
2085 */
2086static bool ice_chk_linearize(struct sk_buff *skb, unsigned int count)
2087{
2088	/* Both TSO and single send will work if count is less than 8 */
2089	if (likely(count < ICE_MAX_BUF_TXD))
2090		return false;
2091
2092	if (skb_is_gso(skb))
2093		return __ice_chk_linearize(skb);
2094
2095	/* we can support up to 8 data buffers for a single send */
2096	return count != ICE_MAX_BUF_TXD;
2097}
2098
2099/**
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2100 * ice_xmit_frame_ring - Sends buffer on Tx ring
2101 * @skb: send buffer
2102 * @tx_ring: ring to send buffer on
2103 *
2104 * Returns NETDEV_TX_OK if sent, else an error code
2105 */
2106static netdev_tx_t
2107ice_xmit_frame_ring(struct sk_buff *skb, struct ice_ring *tx_ring)
2108{
2109	struct ice_tx_offload_params offload = { 0 };
2110	struct ice_vsi *vsi = tx_ring->vsi;
2111	struct ice_tx_buf *first;
 
2112	unsigned int count;
2113	int tso, csum;
2114
 
 
 
 
 
2115	count = ice_xmit_desc_count(skb);
2116	if (ice_chk_linearize(skb, count)) {
2117		if (__skb_linearize(skb))
2118			goto out_drop;
2119		count = ice_txd_use_count(skb->len);
2120		tx_ring->tx_stats.tx_linearize++;
2121	}
2122
2123	/* need: 1 descriptor per page * PAGE_SIZE/ICE_MAX_DATA_PER_TXD,
2124	 *       + 1 desc for skb_head_len/ICE_MAX_DATA_PER_TXD,
2125	 *       + 4 desc gap to avoid the cache line where head is,
2126	 *       + 1 desc for context descriptor,
2127	 * otherwise try next time
2128	 */
2129	if (ice_maybe_stop_tx(tx_ring, count + ICE_DESCS_PER_CACHE_LINE +
2130			      ICE_DESCS_FOR_CTX_DESC)) {
2131		tx_ring->tx_stats.tx_busy++;
2132		return NETDEV_TX_BUSY;
2133	}
2134
 
 
 
2135	offload.tx_ring = tx_ring;
2136
2137	/* record the location of the first descriptor for this packet */
2138	first = &tx_ring->tx_buf[tx_ring->next_to_use];
2139	first->skb = skb;
 
2140	first->bytecount = max_t(unsigned int, skb->len, ETH_ZLEN);
2141	first->gso_segs = 1;
2142	first->tx_flags = 0;
2143
2144	/* prepare the VLAN tagging flags for Tx */
2145	if (ice_tx_prepare_vlan_flags(tx_ring, first))
2146		goto out_drop;
 
 
 
 
 
2147
2148	/* set up TSO offload */
2149	tso = ice_tso(first, &offload);
2150	if (tso < 0)
2151		goto out_drop;
2152
2153	/* always set up Tx checksum offload */
2154	csum = ice_tx_csum(first, &offload);
2155	if (csum < 0)
2156		goto out_drop;
2157
2158	/* allow CONTROL frames egress from main VSI if FW LLDP disabled */
2159	if (unlikely(skb->priority == TC_PRIO_CONTROL &&
 
 
2160		     vsi->type == ICE_VSI_PF &&
2161		     vsi->port_info->is_sw_lldp))
2162		offload.cd_qw1 |= (u64)(ICE_TX_DESC_DTYPE_CTX |
2163					ICE_TX_CTX_DESC_SWTCH_UPLINK <<
2164					ICE_TXD_CTX_QW1_CMD_S);
2165
 
 
 
 
2166	if (offload.cd_qw1 & ICE_TX_DESC_DTYPE_CTX) {
2167		struct ice_tx_ctx_desc *cdesc;
2168		int i = tx_ring->next_to_use;
2169
2170		/* grab the next descriptor */
2171		cdesc = ICE_TX_CTX_DESC(tx_ring, i);
2172		i++;
2173		tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2174
2175		/* setup context descriptor */
2176		cdesc->tunneling_params = cpu_to_le32(offload.cd_tunnel_params);
2177		cdesc->l2tag2 = cpu_to_le16(offload.cd_l2tag2);
2178		cdesc->rsvd = cpu_to_le16(0);
2179		cdesc->qw1 = cpu_to_le64(offload.cd_qw1);
2180	}
2181
2182	ice_tx_map(tx_ring, first, &offload);
2183	return NETDEV_TX_OK;
2184
2185out_drop:
 
2186	dev_kfree_skb_any(skb);
2187	return NETDEV_TX_OK;
2188}
2189
2190/**
2191 * ice_start_xmit - Selects the correct VSI and Tx queue to send buffer
2192 * @skb: send buffer
2193 * @netdev: network interface device structure
2194 *
2195 * Returns NETDEV_TX_OK if sent, else an error code
2196 */
2197netdev_tx_t ice_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2198{
2199	struct ice_netdev_priv *np = netdev_priv(netdev);
2200	struct ice_vsi *vsi = np->vsi;
2201	struct ice_ring *tx_ring;
2202
2203	tx_ring = vsi->tx_rings[skb->queue_mapping];
2204
2205	/* hardware can't handle really short frames, hardware padding works
2206	 * beyond this point
2207	 */
2208	if (skb_put_padto(skb, ICE_MIN_TX_LEN))
2209		return NETDEV_TX_OK;
2210
2211	return ice_xmit_frame_ring(skb, tx_ring);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2212}