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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
7 */
8
9/**
10 * DOC: VC4 Falcon HDMI module
11 *
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
15 *
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
18 *
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
23 * blank regions.
24 *
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
29 *
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
32 */
33
34#include <drm/display/drm_hdmi_helper.h>
35#include <drm/display/drm_hdmi_state_helper.h>
36#include <drm/display/drm_scdc_helper.h>
37#include <drm/drm_atomic_helper.h>
38#include <drm/drm_drv.h>
39#include <drm/drm_edid.h>
40#include <drm/drm_probe_helper.h>
41#include <drm/drm_simple_kms_helper.h>
42#include <linux/clk.h>
43#include <linux/component.h>
44#include <linux/gpio/consumer.h>
45#include <linux/i2c.h>
46#include <linux/of.h>
47#include <linux/of_address.h>
48#include <linux/pm_runtime.h>
49#include <linux/rational.h>
50#include <linux/reset.h>
51#include <sound/dmaengine_pcm.h>
52#include <sound/hdmi-codec.h>
53#include <sound/pcm_drm_eld.h>
54#include <sound/pcm_params.h>
55#include <sound/soc.h>
56#include "media/cec.h"
57#include "vc4_drv.h"
58#include "vc4_hdmi.h"
59#include "vc4_hdmi_regs.h"
60#include "vc4_regs.h"
61
62#define VC5_HDMI_HORZA_HFP_SHIFT 16
63#define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
64#define VC5_HDMI_HORZA_VPOS BIT(15)
65#define VC5_HDMI_HORZA_HPOS BIT(14)
66#define VC5_HDMI_HORZA_HAP_SHIFT 0
67#define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
68
69#define VC5_HDMI_HORZB_HBP_SHIFT 16
70#define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
71#define VC5_HDMI_HORZB_HSP_SHIFT 0
72#define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
73
74#define VC5_HDMI_VERTA_VSP_SHIFT 24
75#define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
76#define VC5_HDMI_VERTA_VFP_SHIFT 16
77#define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
78#define VC5_HDMI_VERTA_VAL_SHIFT 0
79#define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
80
81#define VC5_HDMI_VERTB_VSPO_SHIFT 16
82#define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
83
84#define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
85#define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
86#define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
87#define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
88
89#define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
90
91#define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
92#define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
93
94#define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0
95#define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0)
96
97#define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31)
98
99#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8
100#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)
101
102#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK VC4_MASK(7, 0)
103#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE BIT(0)
104#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE BIT(4)
105
106# define VC4_HD_M_SW_RST BIT(2)
107# define VC4_HD_M_ENABLE BIT(0)
108
109#define HSM_MIN_CLOCK_FREQ 120000000
110#define CEC_CLOCK_FREQ 40000
111
112#define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
113
114static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi)
115{
116 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
117
118 lockdep_assert_held(&vc4_hdmi->mutex);
119
120 if (!display->is_hdmi)
121 return false;
122
123 if (!display->hdmi.scdc.supported ||
124 !display->hdmi.scdc.scrambling.supported)
125 return false;
126
127 return true;
128}
129
130static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
131 unsigned int bpc,
132 enum hdmi_colorspace fmt)
133{
134 unsigned long long clock = drm_hdmi_compute_mode_clock(mode, bpc, fmt);
135
136 return clock > HDMI_14_MAX_TMDS_CLK;
137}
138
139static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
140{
141 struct drm_debugfs_entry *entry = m->private;
142 struct vc4_hdmi *vc4_hdmi = entry->file.data;
143 struct drm_device *drm = vc4_hdmi->connector.dev;
144 struct drm_printer p = drm_seq_file_printer(m);
145 int idx;
146
147 if (!drm_dev_enter(drm, &idx))
148 return -ENODEV;
149
150 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
151
152 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
153 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
154 drm_print_regset32(&p, &vc4_hdmi->cec_regset);
155 drm_print_regset32(&p, &vc4_hdmi->csc_regset);
156 drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
157 drm_print_regset32(&p, &vc4_hdmi->phy_regset);
158 drm_print_regset32(&p, &vc4_hdmi->ram_regset);
159 drm_print_regset32(&p, &vc4_hdmi->rm_regset);
160
161 pm_runtime_put(&vc4_hdmi->pdev->dev);
162
163 drm_dev_exit(idx);
164
165 return 0;
166}
167
168static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
169{
170 struct drm_device *drm = vc4_hdmi->connector.dev;
171 unsigned long flags;
172 int idx;
173
174 /*
175 * We can be called by our bind callback, when the
176 * connector->dev pointer might not be initialised yet.
177 */
178 if (drm && !drm_dev_enter(drm, &idx))
179 return;
180
181 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
182
183 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
184 udelay(1);
185 HDMI_WRITE(HDMI_M_CTL, 0);
186
187 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
188
189 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
190 VC4_HDMI_SW_RESET_HDMI |
191 VC4_HDMI_SW_RESET_FORMAT_DETECT);
192
193 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
194
195 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
196
197 if (drm)
198 drm_dev_exit(idx);
199}
200
201static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
202{
203 struct drm_device *drm = vc4_hdmi->connector.dev;
204 unsigned long flags;
205 int idx;
206
207 /*
208 * We can be called by our bind callback, when the
209 * connector->dev pointer might not be initialised yet.
210 */
211 if (drm && !drm_dev_enter(drm, &idx))
212 return;
213
214 reset_control_reset(vc4_hdmi->reset);
215
216 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
217
218 HDMI_WRITE(HDMI_DVP_CTL, 0);
219
220 HDMI_WRITE(HDMI_CLOCK_STOP,
221 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
222
223 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
224
225 if (drm)
226 drm_dev_exit(idx);
227}
228
229#ifdef CONFIG_DRM_VC4_HDMI_CEC
230static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
231{
232 struct drm_device *drm = vc4_hdmi->connector.dev;
233 unsigned long cec_rate;
234 unsigned long flags;
235 u16 clk_cnt;
236 u32 value;
237 int idx;
238
239 /*
240 * This function is called by our runtime_resume implementation
241 * and thus at bind time, when we haven't registered our
242 * connector yet and thus don't have a pointer to the DRM
243 * device.
244 */
245 if (drm && !drm_dev_enter(drm, &idx))
246 return;
247
248 cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
249
250 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
251
252 value = HDMI_READ(HDMI_CEC_CNTRL_1);
253 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
254
255 /*
256 * Set the clock divider: the hsm_clock rate and this divider
257 * setting will give a 40 kHz CEC clock.
258 */
259 clk_cnt = cec_rate / CEC_CLOCK_FREQ;
260 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
261 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
262
263 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
264
265 if (drm)
266 drm_dev_exit(idx);
267}
268#else
269static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
270#endif
271
272static int reset_pipe(struct drm_crtc *crtc,
273 struct drm_modeset_acquire_ctx *ctx)
274{
275 struct drm_atomic_state *state;
276 struct drm_crtc_state *crtc_state;
277 int ret;
278
279 state = drm_atomic_state_alloc(crtc->dev);
280 if (!state)
281 return -ENOMEM;
282
283 state->acquire_ctx = ctx;
284
285 crtc_state = drm_atomic_get_crtc_state(state, crtc);
286 if (IS_ERR(crtc_state)) {
287 ret = PTR_ERR(crtc_state);
288 goto out;
289 }
290
291 crtc_state->connectors_changed = true;
292
293 ret = drm_atomic_commit(state);
294out:
295 drm_atomic_state_put(state);
296
297 return ret;
298}
299
300static int vc4_hdmi_reset_link(struct drm_connector *connector,
301 struct drm_modeset_acquire_ctx *ctx)
302{
303 struct drm_device *drm;
304 struct vc4_hdmi *vc4_hdmi;
305 struct drm_connector_state *conn_state;
306 struct drm_crtc_state *crtc_state;
307 struct drm_crtc *crtc;
308 bool scrambling_needed;
309 u8 config;
310 int ret;
311
312 if (!connector)
313 return 0;
314
315 drm = connector->dev;
316 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx);
317 if (ret)
318 return ret;
319
320 conn_state = connector->state;
321 crtc = conn_state->crtc;
322 if (!crtc)
323 return 0;
324
325 ret = drm_modeset_lock(&crtc->mutex, ctx);
326 if (ret)
327 return ret;
328
329 crtc_state = crtc->state;
330 if (!crtc_state->active)
331 return 0;
332
333 vc4_hdmi = connector_to_vc4_hdmi(connector);
334 mutex_lock(&vc4_hdmi->mutex);
335
336 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) {
337 mutex_unlock(&vc4_hdmi->mutex);
338 return 0;
339 }
340
341 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode,
342 vc4_hdmi->output_bpc,
343 vc4_hdmi->output_format);
344 if (!scrambling_needed) {
345 mutex_unlock(&vc4_hdmi->mutex);
346 return 0;
347 }
348
349 if (conn_state->commit &&
350 !try_wait_for_completion(&conn_state->commit->hw_done)) {
351 mutex_unlock(&vc4_hdmi->mutex);
352 return 0;
353 }
354
355 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
356 if (ret < 0) {
357 drm_err(drm, "Failed to read TMDS config: %d\n", ret);
358 mutex_unlock(&vc4_hdmi->mutex);
359 return 0;
360 }
361
362 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) {
363 mutex_unlock(&vc4_hdmi->mutex);
364 return 0;
365 }
366
367 mutex_unlock(&vc4_hdmi->mutex);
368
369 /*
370 * HDMI 2.0 says that one should not send scrambled data
371 * prior to configuring the sink scrambling, and that
372 * TMDS clock/data transmission should be suspended when
373 * changing the TMDS clock rate in the sink. So let's
374 * just do a full modeset here, even though some sinks
375 * would be perfectly happy if were to just reconfigure
376 * the SCDC settings on the fly.
377 */
378 return reset_pipe(crtc, ctx);
379}
380
381static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi,
382 struct drm_modeset_acquire_ctx *ctx,
383 enum drm_connector_status status)
384{
385 struct drm_connector *connector = &vc4_hdmi->connector;
386 const struct drm_edid *drm_edid;
387 int ret;
388
389 /*
390 * NOTE: This function should really be called with vc4_hdmi->mutex
391 * held, but doing so results in reentrancy issues since
392 * cec_s_phys_addr() might call .adap_enable, which leads to that
393 * funtion being called with our mutex held.
394 *
395 * A similar situation occurs with vc4_hdmi_reset_link() that
396 * will call into our KMS hooks if the scrambling was enabled.
397 *
398 * Concurrency isn't an issue at the moment since we don't share
399 * any state with any of the other frameworks so we can ignore
400 * the lock for now.
401 */
402
403 if (status == connector_status_disconnected) {
404 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
405 return;
406 }
407
408 drm_edid = drm_edid_read_ddc(connector, vc4_hdmi->ddc);
409
410 drm_edid_connector_update(connector, drm_edid);
411 cec_s_phys_addr(vc4_hdmi->cec_adap,
412 connector->display_info.source_physical_address, false);
413
414 if (!drm_edid)
415 return;
416
417 drm_edid_free(drm_edid);
418
419 for (;;) {
420 ret = vc4_hdmi_reset_link(connector, ctx);
421 if (ret == -EDEADLK) {
422 drm_modeset_backoff(ctx);
423 continue;
424 }
425
426 break;
427 }
428}
429
430static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector,
431 struct drm_modeset_acquire_ctx *ctx,
432 bool force)
433{
434 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
435 enum drm_connector_status status = connector_status_disconnected;
436 int ret;
437
438 /*
439 * NOTE: This function should really take vc4_hdmi->mutex, but
440 * doing so results in reentrancy issues since
441 * vc4_hdmi_handle_hotplug() can call into other functions that
442 * would take the mutex while it's held here.
443 *
444 * Concurrency isn't an issue at the moment since we don't share
445 * any state with any of the other frameworks so we can ignore
446 * the lock for now.
447 */
448
449 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
450 if (ret) {
451 drm_err_once(connector->dev, "Failed to retain HDMI power domain: %d\n",
452 ret);
453 return connector_status_unknown;
454 }
455
456 if (vc4_hdmi->hpd_gpio) {
457 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
458 status = connector_status_connected;
459 } else {
460 if (vc4_hdmi->variant->hp_detect &&
461 vc4_hdmi->variant->hp_detect(vc4_hdmi))
462 status = connector_status_connected;
463 }
464
465 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status);
466 pm_runtime_put(&vc4_hdmi->pdev->dev);
467
468 return status;
469}
470
471static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
472{
473 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
474 struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
475 const struct drm_edid *drm_edid;
476 int ret = 0;
477
478 /*
479 * NOTE: This function should really take vc4_hdmi->mutex, but doing so
480 * results in reentrancy issues since cec_s_phys_addr() might call
481 * .adap_enable, which leads to that funtion being called with our mutex
482 * held.
483 *
484 * Concurrency isn't an issue at the moment since we don't share
485 * any state with any of the other frameworks so we can ignore
486 * the lock for now.
487 */
488
489 drm_edid = drm_edid_read_ddc(connector, vc4_hdmi->ddc);
490 drm_edid_connector_update(connector, drm_edid);
491 cec_s_phys_addr(vc4_hdmi->cec_adap,
492 connector->display_info.source_physical_address, false);
493 if (!drm_edid)
494 return 0;
495
496 ret = drm_edid_connector_add_modes(connector);
497 drm_edid_free(drm_edid);
498
499 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) {
500 struct drm_device *drm = connector->dev;
501 const struct drm_display_mode *mode;
502
503 list_for_each_entry(mode, &connector->probed_modes, head) {
504 if (vc4_hdmi_mode_needs_scrambling(mode, 8, HDMI_COLORSPACE_RGB)) {
505 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
506 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
507 }
508 }
509 }
510
511 return ret;
512}
513
514static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
515 struct drm_atomic_state *state)
516{
517 struct drm_connector_state *old_state =
518 drm_atomic_get_old_connector_state(state, connector);
519 struct drm_connector_state *new_state =
520 drm_atomic_get_new_connector_state(state, connector);
521 struct drm_crtc *crtc = new_state->crtc;
522
523 if (!crtc)
524 return 0;
525
526 if (old_state->tv.margins.left != new_state->tv.margins.left ||
527 old_state->tv.margins.right != new_state->tv.margins.right ||
528 old_state->tv.margins.top != new_state->tv.margins.top ||
529 old_state->tv.margins.bottom != new_state->tv.margins.bottom) {
530 struct drm_crtc_state *crtc_state;
531 int ret;
532
533 crtc_state = drm_atomic_get_crtc_state(state, crtc);
534 if (IS_ERR(crtc_state))
535 return PTR_ERR(crtc_state);
536
537 /*
538 * Strictly speaking, we should be calling
539 * drm_atomic_helper_check_planes() after our call to
540 * drm_atomic_add_affected_planes(). However, the
541 * connector atomic_check is called as part of
542 * drm_atomic_helper_check_modeset() that already
543 * happens before a call to
544 * drm_atomic_helper_check_planes() in
545 * drm_atomic_helper_check().
546 */
547 ret = drm_atomic_add_affected_planes(state, crtc);
548 if (ret)
549 return ret;
550 }
551
552 if (old_state->colorspace != new_state->colorspace) {
553 struct drm_crtc_state *crtc_state;
554
555 crtc_state = drm_atomic_get_crtc_state(state, crtc);
556 if (IS_ERR(crtc_state))
557 return PTR_ERR(crtc_state);
558
559 crtc_state->mode_changed = true;
560 }
561
562 return drm_atomic_helper_connector_hdmi_check(connector, state);
563}
564
565static void vc4_hdmi_connector_reset(struct drm_connector *connector)
566{
567 drm_atomic_helper_connector_reset(connector);
568 __drm_atomic_helper_connector_hdmi_reset(connector, connector->state);
569 drm_atomic_helper_connector_tv_margins_reset(connector);
570}
571
572static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
573 .fill_modes = drm_helper_probe_single_connector_modes,
574 .reset = vc4_hdmi_connector_reset,
575 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
576 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
577};
578
579static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
580 .detect_ctx = vc4_hdmi_connector_detect_ctx,
581 .get_modes = vc4_hdmi_connector_get_modes,
582 .atomic_check = vc4_hdmi_connector_atomic_check,
583};
584
585static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs;
586
587static int vc4_hdmi_connector_init(struct drm_device *dev,
588 struct vc4_hdmi *vc4_hdmi)
589{
590 struct drm_connector *connector = &vc4_hdmi->connector;
591 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
592 unsigned int max_bpc = 8;
593 int ret;
594
595 if (vc4_hdmi->variant->supports_hdr)
596 max_bpc = 12;
597
598 ret = drmm_connector_hdmi_init(dev, connector,
599 "Broadcom", "Videocore",
600 &vc4_hdmi_connector_funcs,
601 &vc4_hdmi_hdmi_connector_funcs,
602 DRM_MODE_CONNECTOR_HDMIA,
603 vc4_hdmi->ddc,
604 BIT(HDMI_COLORSPACE_RGB) |
605 BIT(HDMI_COLORSPACE_YUV422) |
606 BIT(HDMI_COLORSPACE_YUV444),
607 max_bpc);
608 if (ret)
609 return ret;
610
611 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
612
613 /*
614 * Some of the properties below require access to state, like bpc.
615 * Allocate some default initial connector state with our reset helper.
616 */
617 if (connector->funcs->reset)
618 connector->funcs->reset(connector);
619
620 /* Create and attach TV margin props to this connector. */
621 ret = drm_mode_create_tv_margin_properties(dev);
622 if (ret)
623 return ret;
624
625 ret = drm_mode_create_hdmi_colorspace_property(connector, 0);
626 if (ret)
627 return ret;
628
629 drm_connector_attach_colorspace_property(connector);
630 drm_connector_attach_tv_margin_properties(connector);
631
632 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
633 DRM_CONNECTOR_POLL_DISCONNECT);
634
635 connector->interlace_allowed = 1;
636 connector->doublescan_allowed = 0;
637 connector->stereo_allowed = 1;
638
639 ret = drm_connector_attach_broadcast_rgb_property(connector);
640 if (ret)
641 return ret;
642
643 drm_connector_attach_encoder(connector, encoder);
644
645 return 0;
646}
647
648static int vc4_hdmi_stop_packet(struct vc4_hdmi *vc4_hdmi,
649 enum hdmi_infoframe_type type,
650 bool poll)
651{
652 struct drm_device *drm = vc4_hdmi->connector.dev;
653 u32 packet_id = type - 0x80;
654 unsigned long flags;
655 int ret = 0;
656 int idx;
657
658 if (!drm_dev_enter(drm, &idx))
659 return -ENODEV;
660
661 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
662 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
663 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
664 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
665
666 if (poll) {
667 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
668 BIT(packet_id)), 100);
669 }
670
671 drm_dev_exit(idx);
672 return ret;
673}
674
675static int vc4_hdmi_write_infoframe(struct drm_connector *connector,
676 enum hdmi_infoframe_type type,
677 const u8 *infoframe, size_t len)
678{
679 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
680 struct drm_device *drm = connector->dev;
681 u32 packet_id = type - 0x80;
682 const struct vc4_hdmi_register *ram_packet_start =
683 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
684 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
685 u32 packet_reg_next = ram_packet_start->offset +
686 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
687 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
688 ram_packet_start->reg);
689 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
690 unsigned long flags;
691 ssize_t i;
692 int ret;
693 int idx;
694
695 if (!drm_dev_enter(drm, &idx))
696 return 0;
697
698 if (len > sizeof(buffer)) {
699 ret = -ENOMEM;
700 goto out;
701 }
702
703 memcpy(buffer, infoframe, len);
704
705 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
706 VC4_HDMI_RAM_PACKET_ENABLE),
707 "Packet RAM has to be on to store the packet.");
708
709 ret = vc4_hdmi_stop_packet(vc4_hdmi, type, true);
710 if (ret) {
711 drm_err(drm, "Failed to wait for infoframe to go idle: %d\n", ret);
712 goto out;
713 }
714
715 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
716
717 for (i = 0; i < len; i += 7) {
718 writel(buffer[i + 0] << 0 |
719 buffer[i + 1] << 8 |
720 buffer[i + 2] << 16,
721 base + packet_reg);
722 packet_reg += 4;
723
724 writel(buffer[i + 3] << 0 |
725 buffer[i + 4] << 8 |
726 buffer[i + 5] << 16 |
727 buffer[i + 6] << 24,
728 base + packet_reg);
729 packet_reg += 4;
730 }
731
732 /*
733 * clear remainder of packet ram as it's included in the
734 * infoframe and triggers a checksum error on hdmi analyser
735 */
736 for (; packet_reg < packet_reg_next; packet_reg += 4)
737 writel(0, base + packet_reg);
738
739 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
740 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
741
742 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
743
744 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
745 BIT(packet_id)), 100);
746 if (ret)
747 drm_err(drm, "Failed to wait for infoframe to start: %d\n", ret);
748
749out:
750 drm_dev_exit(idx);
751 return ret;
752}
753
754#define SCRAMBLING_POLLING_DELAY_MS 1000
755
756static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
757{
758 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
759 struct drm_connector *connector = &vc4_hdmi->connector;
760 struct drm_device *drm = connector->dev;
761 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
762 unsigned long flags;
763 int idx;
764
765 lockdep_assert_held(&vc4_hdmi->mutex);
766
767 if (!vc4_hdmi_supports_scrambling(vc4_hdmi))
768 return;
769
770 if (!vc4_hdmi_mode_needs_scrambling(mode,
771 vc4_hdmi->output_bpc,
772 vc4_hdmi->output_format))
773 return;
774
775 if (!drm_dev_enter(drm, &idx))
776 return;
777
778 drm_scdc_set_high_tmds_clock_ratio(connector, true);
779 drm_scdc_set_scrambling(connector, true);
780
781 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
782 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
783 VC5_HDMI_SCRAMBLER_CTL_ENABLE);
784 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
785
786 drm_dev_exit(idx);
787
788 vc4_hdmi->scdc_enabled = true;
789
790 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
791 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
792}
793
794static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
795{
796 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
797 struct drm_connector *connector = &vc4_hdmi->connector;
798 struct drm_device *drm = connector->dev;
799 unsigned long flags;
800 int idx;
801
802 lockdep_assert_held(&vc4_hdmi->mutex);
803
804 if (!vc4_hdmi->scdc_enabled)
805 return;
806
807 vc4_hdmi->scdc_enabled = false;
808
809 if (delayed_work_pending(&vc4_hdmi->scrambling_work))
810 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
811
812 if (!drm_dev_enter(drm, &idx))
813 return;
814
815 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
816 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
817 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
818 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
819
820 drm_scdc_set_scrambling(connector, false);
821 drm_scdc_set_high_tmds_clock_ratio(connector, false);
822
823 drm_dev_exit(idx);
824}
825
826static void vc4_hdmi_scrambling_wq(struct work_struct *work)
827{
828 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
829 struct vc4_hdmi,
830 scrambling_work);
831 struct drm_connector *connector = &vc4_hdmi->connector;
832
833 if (drm_scdc_get_scrambling_status(connector))
834 return;
835
836 drm_scdc_set_high_tmds_clock_ratio(connector, true);
837 drm_scdc_set_scrambling(connector, true);
838
839 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
840 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
841}
842
843static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
844 struct drm_atomic_state *state)
845{
846 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
847 struct drm_device *drm = vc4_hdmi->connector.dev;
848 unsigned long flags;
849 int idx;
850
851 mutex_lock(&vc4_hdmi->mutex);
852
853 vc4_hdmi->packet_ram_enabled = false;
854
855 if (!drm_dev_enter(drm, &idx))
856 goto out;
857
858 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
859
860 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
861
862 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
863
864 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
865
866 mdelay(1);
867
868 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
869 HDMI_WRITE(HDMI_VID_CTL,
870 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
871 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
872
873 vc4_hdmi_disable_scrambling(encoder);
874
875 drm_dev_exit(idx);
876
877out:
878 mutex_unlock(&vc4_hdmi->mutex);
879}
880
881static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
882 struct drm_atomic_state *state)
883{
884 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
885 struct drm_device *drm = vc4_hdmi->connector.dev;
886 unsigned long flags;
887 int ret;
888 int idx;
889
890 mutex_lock(&vc4_hdmi->mutex);
891
892 if (!drm_dev_enter(drm, &idx))
893 goto out;
894
895 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
896 HDMI_WRITE(HDMI_VID_CTL,
897 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
898 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
899
900 if (vc4_hdmi->variant->phy_disable)
901 vc4_hdmi->variant->phy_disable(vc4_hdmi);
902
903 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
904 clk_disable_unprepare(vc4_hdmi->pixel_clock);
905
906 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
907 if (ret < 0)
908 drm_err(drm, "Failed to release power domain: %d\n", ret);
909
910 drm_dev_exit(idx);
911
912out:
913 mutex_unlock(&vc4_hdmi->mutex);
914}
915
916static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
917 struct drm_connector_state *state,
918 const struct drm_display_mode *mode)
919{
920 struct drm_device *drm = vc4_hdmi->connector.dev;
921 unsigned long flags;
922 u32 csc_ctl;
923 int idx;
924
925 if (!drm_dev_enter(drm, &idx))
926 return;
927
928 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
929
930 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
931 VC4_HD_CSC_CTL_ORDER);
932
933 if (state->hdmi.is_limited_range) {
934 /* CEA VICs other than #1 requre limited range RGB
935 * output unless overridden by an AVI infoframe.
936 * Apply a colorspace conversion to squash 0-255 down
937 * to 16-235. The matrix here is:
938 *
939 * [ 0 0 0.8594 16]
940 * [ 0 0.8594 0 16]
941 * [ 0.8594 0 0 16]
942 * [ 0 0 0 1]
943 */
944 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
945 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
946 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
947 VC4_HD_CSC_CTL_MODE);
948
949 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
950 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
951 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
952 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
953 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
954 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
955 }
956
957 /* The RGB order applies even when CSC is disabled. */
958 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
959
960 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
961
962 drm_dev_exit(idx);
963}
964
965/*
966 * Matrices for (internal) RGB to RGB output.
967 *
968 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
969 */
970static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = {
971 {
972 /*
973 * Full range - unity
974 *
975 * [ 1 0 0 0]
976 * [ 0 1 0 0]
977 * [ 0 0 1 0]
978 */
979 { 0x2000, 0x0000, 0x0000, 0x0000 },
980 { 0x0000, 0x2000, 0x0000, 0x0000 },
981 { 0x0000, 0x0000, 0x2000, 0x0000 },
982 },
983 {
984 /*
985 * Limited range
986 *
987 * CEA VICs other than #1 require limited range RGB
988 * output unless overridden by an AVI infoframe. Apply a
989 * colorspace conversion to squash 0-255 down to 16-235.
990 * The matrix here is:
991 *
992 * [ 0.8594 0 0 16]
993 * [ 0 0.8594 0 16]
994 * [ 0 0 0.8594 16]
995 */
996 { 0x1b80, 0x0000, 0x0000, 0x0400 },
997 { 0x0000, 0x1b80, 0x0000, 0x0400 },
998 { 0x0000, 0x0000, 0x1b80, 0x0400 },
999 },
1000};
1001
1002/*
1003 * Conversion between Full Range RGB and YUV using the BT.601 Colorspace
1004 *
1005 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1006 */
1007static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = {
1008 {
1009 /*
1010 * Full Range
1011 *
1012 * [ 0.299000 0.587000 0.114000 0 ]
1013 * [ -0.168736 -0.331264 0.500000 128 ]
1014 * [ 0.500000 -0.418688 -0.081312 128 ]
1015 */
1016 { 0x0991, 0x12c9, 0x03a6, 0x0000 },
1017 { 0xfa9b, 0xf567, 0x1000, 0x2000 },
1018 { 0x1000, 0xf29b, 0xfd67, 0x2000 },
1019 },
1020 {
1021 /* Limited Range
1022 *
1023 * [ 0.255785 0.502160 0.097523 16 ]
1024 * [ -0.147644 -0.289856 0.437500 128 ]
1025 * [ 0.437500 -0.366352 -0.071148 128 ]
1026 */
1027 { 0x082f, 0x1012, 0x031f, 0x0400 },
1028 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1029 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1030 },
1031};
1032
1033/*
1034 * Conversion between Full Range RGB and YUV using the BT.709 Colorspace
1035 *
1036 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1037 */
1038static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = {
1039 {
1040 /*
1041 * Full Range
1042 *
1043 * [ 0.212600 0.715200 0.072200 0 ]
1044 * [ -0.114572 -0.385428 0.500000 128 ]
1045 * [ 0.500000 -0.454153 -0.045847 128 ]
1046 */
1047 { 0x06ce, 0x16e3, 0x024f, 0x0000 },
1048 { 0xfc56, 0xf3ac, 0x1000, 0x2000 },
1049 { 0x1000, 0xf179, 0xfe89, 0x2000 },
1050 },
1051 {
1052 /*
1053 * Limited Range
1054 *
1055 * [ 0.181906 0.611804 0.061758 16 ]
1056 * [ -0.100268 -0.337232 0.437500 128 ]
1057 * [ 0.437500 -0.397386 -0.040114 128 ]
1058 */
1059 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1060 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1061 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1062 },
1063};
1064
1065/*
1066 * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace
1067 *
1068 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1069 */
1070static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = {
1071 {
1072 /*
1073 * Full Range
1074 *
1075 * [ 0.262700 0.678000 0.059300 0 ]
1076 * [ -0.139630 -0.360370 0.500000 128 ]
1077 * [ 0.500000 -0.459786 -0.040214 128 ]
1078 */
1079 { 0x0868, 0x15b2, 0x01e6, 0x0000 },
1080 { 0xfb89, 0xf479, 0x1000, 0x2000 },
1081 { 0x1000, 0xf14a, 0xfeb8, 0x2000 },
1082 },
1083 {
1084 /* Limited Range
1085 *
1086 * [ 0.224732 0.580008 0.050729 16 ]
1087 * [ -0.122176 -0.315324 0.437500 128 ]
1088 * [ 0.437500 -0.402312 -0.035188 128 ]
1089 */
1090 { 0x082f, 0x1012, 0x031f, 0x0400 },
1091 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1092 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1093 },
1094};
1095
1096static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
1097 const u16 coeffs[3][4])
1098{
1099 lockdep_assert_held(&vc4_hdmi->hw_lock);
1100
1101 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
1102 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
1103 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
1104 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
1105 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
1106 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
1107}
1108
1109static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi,
1110 const u16 coeffs[3][4])
1111{
1112 lockdep_assert_held(&vc4_hdmi->hw_lock);
1113
1114 /* YUV444 needs the CSC matrices using the channels in a different order */
1115 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[1][1] << 16) | coeffs[1][0]);
1116 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[1][3] << 16) | coeffs[1][2]);
1117 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[2][1] << 16) | coeffs[2][0]);
1118 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[2][3] << 16) | coeffs[2][2]);
1119 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[0][1] << 16) | coeffs[0][0]);
1120 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[0][3] << 16) | coeffs[0][2]);
1121}
1122
1123static const u16
1124(*vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi *vc4_hdmi, u32 colorspace, bool limited))[4]
1125{
1126 switch (colorspace) {
1127 case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC:
1128 case DRM_MODE_COLORIMETRY_XVYCC_601:
1129 case DRM_MODE_COLORIMETRY_SYCC_601:
1130 case DRM_MODE_COLORIMETRY_OPYCC_601:
1131 case DRM_MODE_COLORIMETRY_BT601_YCC:
1132 return vc5_hdmi_csc_full_rgb_to_yuv_bt601[limited];
1133
1134 default:
1135 case DRM_MODE_COLORIMETRY_NO_DATA:
1136 case DRM_MODE_COLORIMETRY_BT709_YCC:
1137 case DRM_MODE_COLORIMETRY_XVYCC_709:
1138 case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED:
1139 case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT:
1140 return vc5_hdmi_csc_full_rgb_to_yuv_bt709[limited];
1141
1142 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1143 case DRM_MODE_COLORIMETRY_BT2020_YCC:
1144 case DRM_MODE_COLORIMETRY_BT2020_RGB:
1145 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1146 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1147 return vc5_hdmi_csc_full_rgb_to_yuv_bt2020[limited];
1148 }
1149}
1150
1151static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1152 struct drm_connector_state *state,
1153 const struct drm_display_mode *mode)
1154{
1155 struct drm_device *drm = vc4_hdmi->connector.dev;
1156 unsigned int lim_range = state->hdmi.is_limited_range ? 1 : 0;
1157 unsigned long flags;
1158 const u16 (*csc)[4];
1159 u32 if_cfg = 0;
1160 u32 if_xbar = 0x543210;
1161 u32 csc_chan_ctl = 0;
1162 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1163 VC5_MT_CP_CSC_CTL_MODE);
1164 int idx;
1165
1166 if (!drm_dev_enter(drm, &idx))
1167 return;
1168
1169 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1170
1171 switch (state->hdmi.output_format) {
1172 case HDMI_COLORSPACE_YUV444:
1173 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range);
1174
1175 vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc);
1176 break;
1177
1178 case HDMI_COLORSPACE_YUV422:
1179 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range);
1180
1181 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1182 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
1183 VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
1184 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
1185
1186 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1187 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
1188
1189 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1190 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
1191
1192 vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc);
1193 break;
1194
1195 case HDMI_COLORSPACE_RGB:
1196 if_xbar = 0x354021;
1197
1198 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_rgb[lim_range]);
1199 break;
1200
1201 default:
1202 break;
1203 }
1204
1205 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
1206 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
1207 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
1208 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1209
1210 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1211
1212 drm_dev_exit(idx);
1213}
1214
1215static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1216 struct drm_connector_state *state,
1217 const struct drm_display_mode *mode)
1218{
1219 struct drm_device *drm = vc4_hdmi->connector.dev;
1220 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1221 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1222 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1223 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1224 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1225 VC4_HDMI_VERTA_VSP) |
1226 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1227 VC4_HDMI_VERTA_VFP) |
1228 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1229 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1230 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1231 interlaced,
1232 VC4_HDMI_VERTB_VBP));
1233 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1234 VC4_SET_FIELD(mode->crtc_vtotal -
1235 mode->crtc_vsync_end,
1236 VC4_HDMI_VERTB_VBP));
1237 unsigned long flags;
1238 u32 reg;
1239 int idx;
1240
1241 if (!drm_dev_enter(drm, &idx))
1242 return;
1243
1244 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1245
1246 HDMI_WRITE(HDMI_HORZA,
1247 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1248 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1249 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1250 VC4_HDMI_HORZA_HAP));
1251
1252 HDMI_WRITE(HDMI_HORZB,
1253 VC4_SET_FIELD((mode->htotal -
1254 mode->hsync_end) * pixel_rep,
1255 VC4_HDMI_HORZB_HBP) |
1256 VC4_SET_FIELD((mode->hsync_end -
1257 mode->hsync_start) * pixel_rep,
1258 VC4_HDMI_HORZB_HSP) |
1259 VC4_SET_FIELD((mode->hsync_start -
1260 mode->hdisplay) * pixel_rep,
1261 VC4_HDMI_HORZB_HFP));
1262
1263 HDMI_WRITE(HDMI_VERTA0, verta);
1264 HDMI_WRITE(HDMI_VERTA1, verta);
1265
1266 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1267 HDMI_WRITE(HDMI_VERTB1, vertb);
1268
1269 reg = HDMI_READ(HDMI_MISC_CONTROL);
1270 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1271 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1272 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1273
1274 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1275
1276 drm_dev_exit(idx);
1277}
1278
1279static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1280 struct drm_connector_state *state,
1281 const struct drm_display_mode *mode)
1282{
1283 struct drm_device *drm = vc4_hdmi->connector.dev;
1284 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1285 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1286 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1287 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1288 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1289 VC5_HDMI_VERTA_VSP) |
1290 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1291 VC5_HDMI_VERTA_VFP) |
1292 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1293 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1294 VC5_HDMI_VERTB_VSPO) |
1295 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1296 interlaced,
1297 VC4_HDMI_VERTB_VBP));
1298 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1299 VC4_SET_FIELD(mode->crtc_vtotal -
1300 mode->crtc_vsync_end,
1301 VC4_HDMI_VERTB_VBP));
1302 unsigned long flags;
1303 unsigned char gcp;
1304 u32 reg;
1305 int idx;
1306
1307 if (!drm_dev_enter(drm, &idx))
1308 return;
1309
1310 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1311
1312 HDMI_WRITE(HDMI_HORZA,
1313 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1314 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1315 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1316 VC5_HDMI_HORZA_HAP) |
1317 VC4_SET_FIELD((mode->hsync_start -
1318 mode->hdisplay) * pixel_rep,
1319 VC5_HDMI_HORZA_HFP));
1320
1321 HDMI_WRITE(HDMI_HORZB,
1322 VC4_SET_FIELD((mode->htotal -
1323 mode->hsync_end) * pixel_rep,
1324 VC5_HDMI_HORZB_HBP) |
1325 VC4_SET_FIELD((mode->hsync_end -
1326 mode->hsync_start) * pixel_rep,
1327 VC5_HDMI_HORZB_HSP));
1328
1329 HDMI_WRITE(HDMI_VERTA0, verta);
1330 HDMI_WRITE(HDMI_VERTA1, verta);
1331
1332 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1333 HDMI_WRITE(HDMI_VERTB1, vertb);
1334
1335 switch (state->hdmi.output_bpc) {
1336 case 12:
1337 gcp = 6;
1338 break;
1339 case 10:
1340 gcp = 5;
1341 break;
1342 case 8:
1343 default:
1344 gcp = 0;
1345 break;
1346 }
1347
1348 /*
1349 * YCC422 is always 36-bit and not considered deep colour so
1350 * doesn't signal in GCP.
1351 */
1352 if (state->hdmi.output_format == HDMI_COLORSPACE_YUV422) {
1353 gcp = 0;
1354 }
1355
1356 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1357 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1358 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1359 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1360 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1361 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1362
1363 reg = HDMI_READ(HDMI_GCP_WORD_1);
1364 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1365 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1366 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK;
1367 reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE;
1368 HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1369
1370 reg = HDMI_READ(HDMI_GCP_CONFIG);
1371 reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1372 HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1373
1374 reg = HDMI_READ(HDMI_MISC_CONTROL);
1375 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1376 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1377 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1378
1379 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1380
1381 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1382
1383 drm_dev_exit(idx);
1384}
1385
1386static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1387{
1388 struct drm_device *drm = vc4_hdmi->connector.dev;
1389 unsigned long flags;
1390 u32 drift;
1391 int ret;
1392 int idx;
1393
1394 if (!drm_dev_enter(drm, &idx))
1395 return;
1396
1397 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1398
1399 drift = HDMI_READ(HDMI_FIFO_CTL);
1400 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1401
1402 HDMI_WRITE(HDMI_FIFO_CTL,
1403 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1404 HDMI_WRITE(HDMI_FIFO_CTL,
1405 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1406
1407 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1408
1409 usleep_range(1000, 1100);
1410
1411 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1412
1413 HDMI_WRITE(HDMI_FIFO_CTL,
1414 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1415 HDMI_WRITE(HDMI_FIFO_CTL,
1416 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1417
1418 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1419
1420 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1421 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1422 WARN_ONCE(ret, "Timeout waiting for "
1423 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1424
1425 drm_dev_exit(idx);
1426}
1427
1428static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1429 struct drm_atomic_state *state)
1430{
1431 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1432 struct drm_device *drm = vc4_hdmi->connector.dev;
1433 struct drm_connector *connector = &vc4_hdmi->connector;
1434 struct drm_connector_state *conn_state =
1435 drm_atomic_get_new_connector_state(state, connector);
1436 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1437 unsigned long long tmds_char_rate = conn_state->hdmi.tmds_char_rate;
1438 unsigned long bvb_rate, hsm_rate;
1439 unsigned long flags;
1440 int ret;
1441 int idx;
1442
1443 mutex_lock(&vc4_hdmi->mutex);
1444
1445 if (!drm_dev_enter(drm, &idx))
1446 goto out;
1447
1448 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1449 if (ret < 0) {
1450 drm_err(drm, "Failed to retain power domain: %d\n", ret);
1451 goto err_dev_exit;
1452 }
1453
1454 /*
1455 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1456 * be faster than pixel clock, infinitesimally faster, tested in
1457 * simulation. Otherwise, exact value is unimportant for HDMI
1458 * operation." This conflicts with bcm2835's vc4 documentation, which
1459 * states HSM's clock has to be at least 108% of the pixel clock.
1460 *
1461 * Real life tests reveal that vc4's firmware statement holds up, and
1462 * users are able to use pixel clocks closer to HSM's, namely for
1463 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1464 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1465 * 162MHz.
1466 *
1467 * Additionally, the AXI clock needs to be at least 25% of
1468 * pixel clock, but HSM ends up being the limiting factor.
1469 */
1470 hsm_rate = max_t(unsigned long,
1471 HSM_MIN_CLOCK_FREQ,
1472 div_u64(tmds_char_rate, 100) * 101);
1473 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1474 if (ret) {
1475 drm_err(drm, "Failed to set HSM clock rate: %d\n", ret);
1476 goto err_put_runtime_pm;
1477 }
1478
1479 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1480 if (ret) {
1481 drm_err(drm, "Failed to set pixel clock rate: %d\n", ret);
1482 goto err_put_runtime_pm;
1483 }
1484
1485 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1486 if (ret) {
1487 drm_err(drm, "Failed to turn on pixel clock: %d\n", ret);
1488 goto err_put_runtime_pm;
1489 }
1490
1491
1492 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1493
1494 if (tmds_char_rate > 297000000)
1495 bvb_rate = 300000000;
1496 else if (tmds_char_rate > 148500000)
1497 bvb_rate = 150000000;
1498 else
1499 bvb_rate = 75000000;
1500
1501 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1502 if (ret) {
1503 drm_err(drm, "Failed to set pixel bvb clock rate: %d\n", ret);
1504 goto err_disable_pixel_clock;
1505 }
1506
1507 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1508 if (ret) {
1509 drm_err(drm, "Failed to turn on pixel bvb clock: %d\n", ret);
1510 goto err_disable_pixel_clock;
1511 }
1512
1513 if (vc4_hdmi->variant->phy_init)
1514 vc4_hdmi->variant->phy_init(vc4_hdmi, conn_state);
1515
1516 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1517
1518 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1519 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1520 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1521 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1522
1523 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1524
1525 if (vc4_hdmi->variant->set_timings)
1526 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1527
1528 drm_dev_exit(idx);
1529
1530 mutex_unlock(&vc4_hdmi->mutex);
1531
1532 return;
1533
1534err_disable_pixel_clock:
1535 clk_disable_unprepare(vc4_hdmi->pixel_clock);
1536err_put_runtime_pm:
1537 pm_runtime_put(&vc4_hdmi->pdev->dev);
1538err_dev_exit:
1539 drm_dev_exit(idx);
1540out:
1541 mutex_unlock(&vc4_hdmi->mutex);
1542 return;
1543}
1544
1545static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1546 struct drm_atomic_state *state)
1547{
1548 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1549 struct drm_device *drm = vc4_hdmi->connector.dev;
1550 struct drm_connector *connector = &vc4_hdmi->connector;
1551 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1552 struct drm_connector_state *conn_state =
1553 drm_atomic_get_new_connector_state(state, connector);
1554 unsigned long flags;
1555 int idx;
1556
1557 mutex_lock(&vc4_hdmi->mutex);
1558
1559 if (!drm_dev_enter(drm, &idx))
1560 goto out;
1561
1562 if (vc4_hdmi->variant->csc_setup)
1563 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1564
1565 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1566 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1567 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1568
1569 drm_dev_exit(idx);
1570
1571out:
1572 mutex_unlock(&vc4_hdmi->mutex);
1573}
1574
1575static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1576 struct drm_atomic_state *state)
1577{
1578 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1579 struct drm_connector *connector = &vc4_hdmi->connector;
1580 struct drm_device *drm = connector->dev;
1581 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1582 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1583 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1584 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1585 unsigned long flags;
1586 int ret;
1587 int idx;
1588
1589 mutex_lock(&vc4_hdmi->mutex);
1590
1591 if (!drm_dev_enter(drm, &idx))
1592 goto out;
1593
1594 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1595
1596 HDMI_WRITE(HDMI_VID_CTL,
1597 VC4_HD_VID_CTL_ENABLE |
1598 VC4_HD_VID_CTL_CLRRGB |
1599 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1600 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1601 VC4_HD_VID_CTL_BLANK_INSERT_EN |
1602 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1603 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1604
1605 HDMI_WRITE(HDMI_VID_CTL,
1606 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1607
1608 if (display->is_hdmi) {
1609 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1610 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1611 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1612
1613 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1614
1615 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1616 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1617 WARN_ONCE(ret, "Timeout waiting for "
1618 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1619 } else {
1620 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1621 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1622 ~(VC4_HDMI_RAM_PACKET_ENABLE));
1623 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1624 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1625 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1626
1627 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1628
1629 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1630 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1631 WARN_ONCE(ret, "Timeout waiting for "
1632 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1633 }
1634
1635 if (display->is_hdmi) {
1636 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1637
1638 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1639 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1640
1641 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1642 VC4_HDMI_RAM_PACKET_ENABLE);
1643
1644 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1645 vc4_hdmi->packet_ram_enabled = true;
1646
1647 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state);
1648 }
1649
1650 vc4_hdmi_recenter_fifo(vc4_hdmi);
1651 vc4_hdmi_enable_scrambling(encoder);
1652
1653 drm_dev_exit(idx);
1654
1655out:
1656 mutex_unlock(&vc4_hdmi->mutex);
1657}
1658
1659static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1660 struct drm_crtc_state *crtc_state,
1661 struct drm_connector_state *conn_state)
1662{
1663 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1664
1665 mutex_lock(&vc4_hdmi->mutex);
1666 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1667 &crtc_state->adjusted_mode);
1668 vc4_hdmi->output_bpc = conn_state->hdmi.output_bpc;
1669 vc4_hdmi->output_format = conn_state->hdmi.output_format;
1670 mutex_unlock(&vc4_hdmi->mutex);
1671}
1672
1673static enum drm_mode_status
1674vc4_hdmi_connector_clock_valid(const struct drm_connector *connector,
1675 const struct drm_display_mode *mode,
1676 unsigned long long clock)
1677{
1678 const struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
1679 struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
1680
1681 if (clock > vc4_hdmi->variant->max_pixel_clock)
1682 return MODE_CLOCK_HIGH;
1683
1684 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK)
1685 return MODE_CLOCK_HIGH;
1686
1687 /* 4096x2160@60 is not reliable without overclocking core */
1688 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 &&
1689 mode->hdisplay > 3840 && mode->vdisplay >= 2160 &&
1690 drm_mode_vrefresh(mode) >= 50)
1691 return MODE_CLOCK_HIGH;
1692
1693 return MODE_OK;
1694}
1695
1696static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs = {
1697 .tmds_char_rate_valid = vc4_hdmi_connector_clock_valid,
1698 .write_infoframe = vc4_hdmi_write_infoframe,
1699};
1700
1701#define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
1702#define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
1703
1704static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1705 struct drm_crtc_state *crtc_state,
1706 struct drm_connector_state *conn_state)
1707{
1708 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1709 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1710 unsigned long long tmds_char_rate = mode->clock * 1000;
1711 unsigned long long tmds_bit_rate;
1712
1713 if (vc4_hdmi->variant->unsupported_odd_h_timings) {
1714 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1715 /* Only try to fixup DBLCLK modes to get 480i and 576i
1716 * working.
1717 * A generic solution for all modes with odd horizontal
1718 * timing values seems impossible based on trying to
1719 * solve it for 1366x768 monitors.
1720 */
1721 if ((mode->hsync_start - mode->hdisplay) & 1)
1722 mode->hsync_start--;
1723 if ((mode->hsync_end - mode->hsync_start) & 1)
1724 mode->hsync_end--;
1725 }
1726
1727 /* Now check whether we still have odd values remaining */
1728 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1729 (mode->hsync_end % 2) || (mode->htotal % 2))
1730 return -EINVAL;
1731 }
1732
1733 /*
1734 * The 1440p@60 pixel rate is in the same range than the first
1735 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1736 * bandwidth). Slightly lower the frequency to bring it out of
1737 * the WiFi range.
1738 */
1739 tmds_bit_rate = tmds_char_rate * 10;
1740 if (vc4_hdmi->disable_wifi_frequencies &&
1741 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1742 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1743 mode->clock = 238560;
1744 tmds_char_rate = mode->clock * 1000;
1745 }
1746
1747 return 0;
1748}
1749
1750static enum drm_mode_status
1751vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1752 const struct drm_display_mode *mode)
1753{
1754 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1755 unsigned long long rate;
1756
1757 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1758 !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1759 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1760 (mode->hsync_end % 2) || (mode->htotal % 2)))
1761 return MODE_H_ILLEGAL;
1762
1763 rate = drm_hdmi_compute_mode_clock(mode, 8, HDMI_COLORSPACE_RGB);
1764 return vc4_hdmi_connector_clock_valid(&vc4_hdmi->connector, mode, rate);
1765}
1766
1767static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1768 .atomic_check = vc4_hdmi_encoder_atomic_check,
1769 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
1770 .mode_valid = vc4_hdmi_encoder_mode_valid,
1771};
1772
1773static int vc4_hdmi_late_register(struct drm_encoder *encoder)
1774{
1775 struct drm_device *drm = encoder->dev;
1776 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1777 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1778
1779 drm_debugfs_add_file(drm, variant->debugfs_name,
1780 vc4_hdmi_debugfs_regs, vc4_hdmi);
1781
1782 return 0;
1783}
1784
1785static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
1786 .late_register = vc4_hdmi_late_register,
1787};
1788
1789static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1790{
1791 int i;
1792 u32 channel_map = 0;
1793
1794 for (i = 0; i < 8; i++) {
1795 if (channel_mask & BIT(i))
1796 channel_map |= i << (3 * i);
1797 }
1798 return channel_map;
1799}
1800
1801static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1802{
1803 int i;
1804 u32 channel_map = 0;
1805
1806 for (i = 0; i < 8; i++) {
1807 if (channel_mask & BIT(i))
1808 channel_map |= i << (4 * i);
1809 }
1810 return channel_map;
1811}
1812
1813static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
1814{
1815 struct drm_device *drm = vc4_hdmi->connector.dev;
1816 unsigned long flags;
1817 u32 hotplug;
1818 int idx;
1819
1820 if (!drm_dev_enter(drm, &idx))
1821 return false;
1822
1823 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1824 hotplug = HDMI_READ(HDMI_HOTPLUG);
1825 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1826
1827 drm_dev_exit(idx);
1828
1829 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
1830}
1831
1832/* HDMI audio codec callbacks */
1833static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1834 unsigned int samplerate)
1835{
1836 struct drm_device *drm = vc4_hdmi->connector.dev;
1837 u32 hsm_clock;
1838 unsigned long flags;
1839 unsigned long n, m;
1840 int idx;
1841
1842 if (!drm_dev_enter(drm, &idx))
1843 return;
1844
1845 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1846 rational_best_approximation(hsm_clock, samplerate,
1847 VC4_HD_MAI_SMP_N_MASK >>
1848 VC4_HD_MAI_SMP_N_SHIFT,
1849 (VC4_HD_MAI_SMP_M_MASK >>
1850 VC4_HD_MAI_SMP_M_SHIFT) + 1,
1851 &n, &m);
1852
1853 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1854 HDMI_WRITE(HDMI_MAI_SMP,
1855 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1856 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1857 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1858
1859 drm_dev_exit(idx);
1860}
1861
1862static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1863{
1864 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1865 u32 n, cts;
1866 u64 tmp;
1867
1868 lockdep_assert_held(&vc4_hdmi->mutex);
1869 lockdep_assert_held(&vc4_hdmi->hw_lock);
1870
1871 n = 128 * samplerate / 1000;
1872 tmp = (u64)(mode->clock * 1000) * n;
1873 do_div(tmp, 128 * samplerate);
1874 cts = tmp;
1875
1876 HDMI_WRITE(HDMI_CRP_CFG,
1877 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1878 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1879
1880 /*
1881 * We could get slightly more accurate clocks in some cases by
1882 * providing a CTS_1 value. The two CTS values are alternated
1883 * between based on the period fields
1884 */
1885 HDMI_WRITE(HDMI_CTS_0, cts);
1886 HDMI_WRITE(HDMI_CTS_1, cts);
1887}
1888
1889static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1890{
1891 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1892
1893 return snd_soc_card_get_drvdata(card);
1894}
1895
1896static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
1897{
1898 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1899
1900 lockdep_assert_held(&vc4_hdmi->mutex);
1901
1902 /*
1903 * If the encoder is currently in DVI mode, treat the codec DAI
1904 * as missing.
1905 */
1906 if (!display->is_hdmi)
1907 return false;
1908
1909 return true;
1910}
1911
1912static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1913{
1914 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1915 struct drm_device *drm = vc4_hdmi->connector.dev;
1916 unsigned long flags;
1917 int ret = 0;
1918 int idx;
1919
1920 mutex_lock(&vc4_hdmi->mutex);
1921
1922 if (!drm_dev_enter(drm, &idx)) {
1923 ret = -ENODEV;
1924 goto out;
1925 }
1926
1927 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1928 ret = -ENOTSUPP;
1929 goto out_dev_exit;
1930 }
1931
1932 vc4_hdmi->audio.streaming = true;
1933
1934 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1935 HDMI_WRITE(HDMI_MAI_CTL,
1936 VC4_HD_MAI_CTL_RESET |
1937 VC4_HD_MAI_CTL_FLUSH |
1938 VC4_HD_MAI_CTL_DLATE |
1939 VC4_HD_MAI_CTL_ERRORE |
1940 VC4_HD_MAI_CTL_ERRORF);
1941 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1942
1943 if (vc4_hdmi->variant->phy_rng_enable)
1944 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1945
1946out_dev_exit:
1947 drm_dev_exit(idx);
1948out:
1949 mutex_unlock(&vc4_hdmi->mutex);
1950
1951 return ret;
1952}
1953
1954static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1955{
1956 struct device *dev = &vc4_hdmi->pdev->dev;
1957 unsigned long flags;
1958 int ret;
1959
1960 lockdep_assert_held(&vc4_hdmi->mutex);
1961
1962 vc4_hdmi->audio.streaming = false;
1963 ret = vc4_hdmi_stop_packet(vc4_hdmi, HDMI_INFOFRAME_TYPE_AUDIO, false);
1964 if (ret)
1965 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1966
1967 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1968
1969 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1970 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1971 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1972
1973 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1974}
1975
1976static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1977{
1978 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1979 struct drm_device *drm = vc4_hdmi->connector.dev;
1980 unsigned long flags;
1981 int idx;
1982
1983 mutex_lock(&vc4_hdmi->mutex);
1984
1985 if (!drm_dev_enter(drm, &idx))
1986 goto out;
1987
1988 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1989
1990 HDMI_WRITE(HDMI_MAI_CTL,
1991 VC4_HD_MAI_CTL_DLATE |
1992 VC4_HD_MAI_CTL_ERRORE |
1993 VC4_HD_MAI_CTL_ERRORF);
1994
1995 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1996
1997 if (vc4_hdmi->variant->phy_rng_disable)
1998 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1999
2000 vc4_hdmi->audio.streaming = false;
2001 vc4_hdmi_audio_reset(vc4_hdmi);
2002
2003 drm_dev_exit(idx);
2004
2005out:
2006 mutex_unlock(&vc4_hdmi->mutex);
2007}
2008
2009static int sample_rate_to_mai_fmt(int samplerate)
2010{
2011 switch (samplerate) {
2012 case 8000:
2013 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
2014 case 11025:
2015 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
2016 case 12000:
2017 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
2018 case 16000:
2019 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
2020 case 22050:
2021 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
2022 case 24000:
2023 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
2024 case 32000:
2025 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
2026 case 44100:
2027 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
2028 case 48000:
2029 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
2030 case 64000:
2031 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
2032 case 88200:
2033 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
2034 case 96000:
2035 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
2036 case 128000:
2037 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
2038 case 176400:
2039 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
2040 case 192000:
2041 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
2042 default:
2043 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
2044 }
2045}
2046
2047/* HDMI audio codec callbacks */
2048static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
2049 struct hdmi_codec_daifmt *daifmt,
2050 struct hdmi_codec_params *params)
2051{
2052 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2053 struct drm_device *drm = vc4_hdmi->connector.dev;
2054 struct drm_connector *connector = &vc4_hdmi->connector;
2055 struct vc4_dev *vc4 = to_vc4_dev(drm);
2056 unsigned int sample_rate = params->sample_rate;
2057 unsigned int channels = params->channels;
2058 unsigned long flags;
2059 u32 audio_packet_config, channel_mask;
2060 u32 channel_map;
2061 u32 mai_audio_format;
2062 u32 mai_sample_rate;
2063 int ret = 0;
2064 int idx;
2065
2066 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
2067 sample_rate, params->sample_width, channels);
2068
2069 mutex_lock(&vc4_hdmi->mutex);
2070
2071 if (!drm_dev_enter(drm, &idx)) {
2072 ret = -ENODEV;
2073 goto out;
2074 }
2075
2076 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2077 ret = -EINVAL;
2078 goto out_dev_exit;
2079 }
2080
2081 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
2082
2083 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2084 HDMI_WRITE(HDMI_MAI_CTL,
2085 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
2086 VC4_HD_MAI_CTL_WHOLSMP |
2087 VC4_HD_MAI_CTL_CHALIGN |
2088 VC4_HD_MAI_CTL_ENABLE);
2089
2090 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
2091 if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
2092 params->channels == 8)
2093 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
2094 else
2095 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
2096 HDMI_WRITE(HDMI_MAI_FMT,
2097 VC4_SET_FIELD(mai_sample_rate,
2098 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
2099 VC4_SET_FIELD(mai_audio_format,
2100 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
2101
2102 /* The B frame identifier should match the value used by alsa-lib (8) */
2103 audio_packet_config =
2104 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
2105 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
2106 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
2107
2108 channel_mask = GENMASK(channels - 1, 0);
2109 audio_packet_config |= VC4_SET_FIELD(channel_mask,
2110 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
2111
2112 /* Set the MAI threshold */
2113 if (vc4->gen >= VC4_GEN_5)
2114 HDMI_WRITE(HDMI_MAI_THR,
2115 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
2116 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
2117 VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQHIGH) |
2118 VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQLOW));
2119 else
2120 HDMI_WRITE(HDMI_MAI_THR,
2121 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICHIGH) |
2122 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICLOW) |
2123 VC4_SET_FIELD(0x6, VC4_HD_MAI_THR_DREQHIGH) |
2124 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_DREQLOW));
2125
2126 HDMI_WRITE(HDMI_MAI_CONFIG,
2127 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
2128 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
2129 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
2130
2131 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
2132 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
2133 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
2134
2135 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
2136
2137 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2138
2139 ret = drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector,
2140 ¶ms->cea);
2141 if (ret)
2142 goto out_dev_exit;
2143
2144out_dev_exit:
2145 drm_dev_exit(idx);
2146out:
2147 mutex_unlock(&vc4_hdmi->mutex);
2148
2149 return ret;
2150}
2151
2152static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2153 .name = "vc4-hdmi-cpu-dai-component",
2154 .legacy_dai_naming = 1,
2155};
2156
2157static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2158{
2159 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2160
2161 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2162
2163 return 0;
2164}
2165
2166static const struct snd_soc_dai_ops vc4_snd_dai_ops = {
2167 .probe = vc4_hdmi_audio_cpu_dai_probe,
2168};
2169
2170static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2171 .name = "vc4-hdmi-cpu-dai",
2172 .ops = &vc4_snd_dai_ops,
2173 .playback = {
2174 .stream_name = "Playback",
2175 .channels_min = 1,
2176 .channels_max = 8,
2177 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2178 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2179 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2180 SNDRV_PCM_RATE_192000,
2181 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2182 },
2183};
2184
2185static const struct snd_dmaengine_pcm_config pcm_conf = {
2186 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2187 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2188};
2189
2190static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
2191 uint8_t *buf, size_t len)
2192{
2193 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2194 struct drm_connector *connector = &vc4_hdmi->connector;
2195
2196 mutex_lock(&connector->eld_mutex);
2197 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2198 mutex_unlock(&connector->eld_mutex);
2199
2200 return 0;
2201}
2202
2203static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
2204 .get_eld = vc4_hdmi_audio_get_eld,
2205 .prepare = vc4_hdmi_audio_prepare,
2206 .audio_shutdown = vc4_hdmi_audio_shutdown,
2207 .audio_startup = vc4_hdmi_audio_startup,
2208};
2209
2210static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
2211 .ops = &vc4_hdmi_codec_ops,
2212 .max_i2s_channels = 8,
2213 .i2s = 1,
2214};
2215
2216static void vc4_hdmi_audio_codec_release(void *ptr)
2217{
2218 struct vc4_hdmi *vc4_hdmi = ptr;
2219
2220 platform_device_unregister(vc4_hdmi->audio.codec_pdev);
2221 vc4_hdmi->audio.codec_pdev = NULL;
2222}
2223
2224static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2225{
2226 const struct vc4_hdmi_register *mai_data =
2227 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2228 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2229 struct snd_soc_card *card = &vc4_hdmi->audio.card;
2230 struct device *dev = &vc4_hdmi->pdev->dev;
2231 struct platform_device *codec_pdev;
2232 const __be32 *addr;
2233 int index, len;
2234 int ret;
2235
2236 /*
2237 * ASoC makes it a bit hard to retrieve a pointer to the
2238 * vc4_hdmi structure. Registering the card will overwrite our
2239 * device drvdata with a pointer to the snd_soc_card structure,
2240 * which can then be used to retrieve whatever drvdata we want
2241 * to associate.
2242 *
2243 * However, that doesn't fly in the case where we wouldn't
2244 * register an ASoC card (because of an old DT that is missing
2245 * the dmas properties for example), then the card isn't
2246 * registered and the device drvdata wouldn't be set.
2247 *
2248 * We can deal with both cases by making sure a snd_soc_card
2249 * pointer and a vc4_hdmi structure are pointing to the same
2250 * memory address, so we can treat them indistinctly without any
2251 * issue.
2252 */
2253 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2254 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2255
2256 if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
2257 dev_warn(dev,
2258 "'dmas' DT property is missing or empty, no HDMI audio\n");
2259 return 0;
2260 }
2261
2262 if (mai_data->reg != VC4_HD) {
2263 WARN_ONCE(true, "MAI isn't in the HD block\n");
2264 return -EINVAL;
2265 }
2266
2267 /*
2268 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2269 * the bus address specified in the DT, because the physical address
2270 * (the one returned by platform_get_resource()) is not appropriate
2271 * for DMA transfers.
2272 * This VC/MMU should probably be exposed to avoid this kind of hacks.
2273 */
2274 index = of_property_match_string(dev->of_node, "reg-names", "hd");
2275 /* Before BCM2711, we don't have a named register range */
2276 if (index < 0)
2277 index = 1;
2278
2279 addr = of_get_address(dev->of_node, index, NULL, NULL);
2280 if (!addr)
2281 return -EINVAL;
2282
2283 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2284 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2285 vc4_hdmi->audio.dma_data.maxburst = 2;
2286
2287 /*
2288 * NOTE: Strictly speaking, we should probably use a DRM-managed
2289 * registration there to avoid removing all the audio components
2290 * by the time the driver doesn't have any user anymore.
2291 *
2292 * However, the ASoC core uses a number of devm_kzalloc calls
2293 * when registering, even when using non-device-managed
2294 * functions (such as in snd_soc_register_component()).
2295 *
2296 * If we call snd_soc_unregister_component() in a DRM-managed
2297 * action, the device-managed actions have already been executed
2298 * and thus we would access memory that has been freed.
2299 *
2300 * Using device-managed hooks here probably leaves us open to a
2301 * bunch of issues if userspace still has a handle on the ALSA
2302 * device when the device is removed. However, this is mitigated
2303 * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2304 * path to prevent the access to the device resources if it
2305 * isn't there anymore.
2306 *
2307 * Then, the vc4_hdmi structure is DRM-managed and thus only
2308 * freed whenever the last user has closed the DRM device file.
2309 * It should thus outlive ALSA in most situations.
2310 */
2311 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2312 if (ret) {
2313 dev_err(dev, "Could not register PCM component: %d\n", ret);
2314 return ret;
2315 }
2316
2317 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2318 &vc4_hdmi_audio_cpu_dai_drv, 1);
2319 if (ret) {
2320 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2321 return ret;
2322 }
2323
2324 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
2325 PLATFORM_DEVID_AUTO,
2326 &vc4_hdmi_codec_pdata,
2327 sizeof(vc4_hdmi_codec_pdata));
2328 if (IS_ERR(codec_pdev)) {
2329 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
2330 return PTR_ERR(codec_pdev);
2331 }
2332 vc4_hdmi->audio.codec_pdev = codec_pdev;
2333
2334 ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi);
2335 if (ret)
2336 return ret;
2337
2338 dai_link->cpus = &vc4_hdmi->audio.cpu;
2339 dai_link->codecs = &vc4_hdmi->audio.codec;
2340 dai_link->platforms = &vc4_hdmi->audio.platform;
2341
2342 dai_link->num_cpus = 1;
2343 dai_link->num_codecs = 1;
2344 dai_link->num_platforms = 1;
2345
2346 dai_link->name = "MAI";
2347 dai_link->stream_name = "MAI PCM";
2348 dai_link->codecs->dai_name = "i2s-hifi";
2349 dai_link->cpus->dai_name = dev_name(dev);
2350 dai_link->codecs->name = dev_name(&codec_pdev->dev);
2351 dai_link->platforms->name = dev_name(dev);
2352
2353 card->dai_link = dai_link;
2354 card->num_links = 1;
2355 card->name = vc4_hdmi->variant->card_name;
2356 card->driver_name = "vc4-hdmi";
2357 card->dev = dev;
2358 card->owner = THIS_MODULE;
2359
2360 /*
2361 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2362 * stores a pointer to the snd card object in dev->driver_data. This
2363 * means we cannot use it for something else. The hdmi back-pointer is
2364 * now stored in card->drvdata and should be retrieved with
2365 * snd_soc_card_get_drvdata() if needed.
2366 */
2367 snd_soc_card_set_drvdata(card, vc4_hdmi);
2368 ret = devm_snd_soc_register_card(dev, card);
2369 if (ret)
2370 dev_err_probe(dev, ret, "Could not register sound card\n");
2371
2372 return ret;
2373
2374}
2375
2376static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2377{
2378 struct vc4_hdmi *vc4_hdmi = priv;
2379 struct drm_connector *connector = &vc4_hdmi->connector;
2380 struct drm_device *dev = connector->dev;
2381
2382 if (dev && dev->registered)
2383 drm_connector_helper_hpd_irq_event(connector);
2384
2385 return IRQ_HANDLED;
2386}
2387
2388static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2389{
2390 struct drm_connector *connector = &vc4_hdmi->connector;
2391 struct platform_device *pdev = vc4_hdmi->pdev;
2392 int ret;
2393
2394 if (vc4_hdmi->variant->external_irq_controller) {
2395 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2396 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2397
2398 ret = devm_request_threaded_irq(&pdev->dev, hpd_con,
2399 NULL,
2400 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2401 "vc4 hdmi hpd connected", vc4_hdmi);
2402 if (ret)
2403 return ret;
2404
2405 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm,
2406 NULL,
2407 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2408 "vc4 hdmi hpd disconnected", vc4_hdmi);
2409 if (ret)
2410 return ret;
2411
2412 connector->polled = DRM_CONNECTOR_POLL_HPD;
2413 }
2414
2415 return 0;
2416}
2417
2418#ifdef CONFIG_DRM_VC4_HDMI_CEC
2419static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2420{
2421 struct vc4_hdmi *vc4_hdmi = priv;
2422
2423 if (vc4_hdmi->cec_rx_msg.len)
2424 cec_received_msg(vc4_hdmi->cec_adap,
2425 &vc4_hdmi->cec_rx_msg);
2426
2427 return IRQ_HANDLED;
2428}
2429
2430static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2431{
2432 struct vc4_hdmi *vc4_hdmi = priv;
2433
2434 if (vc4_hdmi->cec_tx_ok) {
2435 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2436 0, 0, 0, 0);
2437 } else {
2438 /*
2439 * This CEC implementation makes 1 retry, so if we
2440 * get a NACK, then that means it made 2 attempts.
2441 */
2442 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2443 0, 2, 0, 0);
2444 }
2445 return IRQ_HANDLED;
2446}
2447
2448static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2449{
2450 struct vc4_hdmi *vc4_hdmi = priv;
2451 irqreturn_t ret;
2452
2453 if (vc4_hdmi->cec_irq_was_rx)
2454 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2455 else
2456 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2457
2458 return ret;
2459}
2460
2461static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2462{
2463 struct drm_device *dev = vc4_hdmi->connector.dev;
2464 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2465 unsigned int i;
2466
2467 lockdep_assert_held(&vc4_hdmi->hw_lock);
2468
2469 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2470 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2471
2472 if (msg->len > 16) {
2473 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2474 return;
2475 }
2476
2477 for (i = 0; i < msg->len; i += 4) {
2478 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2479
2480 msg->msg[i] = val & 0xff;
2481 msg->msg[i + 1] = (val >> 8) & 0xff;
2482 msg->msg[i + 2] = (val >> 16) & 0xff;
2483 msg->msg[i + 3] = (val >> 24) & 0xff;
2484 }
2485}
2486
2487static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2488{
2489 u32 cntrl1;
2490
2491 /*
2492 * We don't need to protect the register access using
2493 * drm_dev_enter() there because the interrupt handler lifetime
2494 * is tied to the device itself, and not to the DRM device.
2495 *
2496 * So when the device will be gone, one of the first thing we
2497 * will be doing will be to unregister the interrupt handler,
2498 * and then unregister the DRM device. drm_dev_enter() would
2499 * thus always succeed if we are here.
2500 */
2501
2502 lockdep_assert_held(&vc4_hdmi->hw_lock);
2503
2504 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2505 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2506 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2507 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2508
2509 return IRQ_WAKE_THREAD;
2510}
2511
2512static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2513{
2514 struct vc4_hdmi *vc4_hdmi = priv;
2515 irqreturn_t ret;
2516
2517 spin_lock(&vc4_hdmi->hw_lock);
2518 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2519 spin_unlock(&vc4_hdmi->hw_lock);
2520
2521 return ret;
2522}
2523
2524static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2525{
2526 u32 cntrl1;
2527
2528 lockdep_assert_held(&vc4_hdmi->hw_lock);
2529
2530 /*
2531 * We don't need to protect the register access using
2532 * drm_dev_enter() there because the interrupt handler lifetime
2533 * is tied to the device itself, and not to the DRM device.
2534 *
2535 * So when the device will be gone, one of the first thing we
2536 * will be doing will be to unregister the interrupt handler,
2537 * and then unregister the DRM device. drm_dev_enter() would
2538 * thus always succeed if we are here.
2539 */
2540
2541 vc4_hdmi->cec_rx_msg.len = 0;
2542 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2543 vc4_cec_read_msg(vc4_hdmi, cntrl1);
2544 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2545 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2546 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2547
2548 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2549
2550 return IRQ_WAKE_THREAD;
2551}
2552
2553static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
2554{
2555 struct vc4_hdmi *vc4_hdmi = priv;
2556 irqreturn_t ret;
2557
2558 spin_lock(&vc4_hdmi->hw_lock);
2559 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2560 spin_unlock(&vc4_hdmi->hw_lock);
2561
2562 return ret;
2563}
2564
2565static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
2566{
2567 struct vc4_hdmi *vc4_hdmi = priv;
2568 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
2569 irqreturn_t ret;
2570 u32 cntrl5;
2571
2572 /*
2573 * We don't need to protect the register access using
2574 * drm_dev_enter() there because the interrupt handler lifetime
2575 * is tied to the device itself, and not to the DRM device.
2576 *
2577 * So when the device will be gone, one of the first thing we
2578 * will be doing will be to unregister the interrupt handler,
2579 * and then unregister the DRM device. drm_dev_enter() would
2580 * thus always succeed if we are here.
2581 */
2582
2583 if (!(stat & VC4_HDMI_CPU_CEC))
2584 return IRQ_NONE;
2585
2586 spin_lock(&vc4_hdmi->hw_lock);
2587 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
2588 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
2589 if (vc4_hdmi->cec_irq_was_rx)
2590 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2591 else
2592 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2593
2594 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2595 spin_unlock(&vc4_hdmi->hw_lock);
2596
2597 return ret;
2598}
2599
2600static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2601{
2602 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2603 struct drm_device *drm = vc4_hdmi->connector.dev;
2604 /* clock period in microseconds */
2605 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2606 unsigned long flags;
2607 u32 val;
2608 int ret;
2609 int idx;
2610
2611 if (!drm_dev_enter(drm, &idx))
2612 /*
2613 * We can't return an error code, because the CEC
2614 * framework will emit WARN_ON messages at unbind
2615 * otherwise.
2616 */
2617 return 0;
2618
2619 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2620 if (ret) {
2621 drm_dev_exit(idx);
2622 return ret;
2623 }
2624
2625 mutex_lock(&vc4_hdmi->mutex);
2626
2627 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2628
2629 val = HDMI_READ(HDMI_CEC_CNTRL_5);
2630 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2631 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2632 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2633 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2634 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2635
2636 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2637 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2638 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2639 HDMI_WRITE(HDMI_CEC_CNTRL_2,
2640 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2641 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2642 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2643 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2644 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2645 HDMI_WRITE(HDMI_CEC_CNTRL_3,
2646 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2647 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2648 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2649 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2650 HDMI_WRITE(HDMI_CEC_CNTRL_4,
2651 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2652 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2653 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2654 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2655
2656 if (!vc4_hdmi->variant->external_irq_controller)
2657 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2658
2659 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2660
2661 mutex_unlock(&vc4_hdmi->mutex);
2662 drm_dev_exit(idx);
2663
2664 return 0;
2665}
2666
2667static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2668{
2669 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2670 struct drm_device *drm = vc4_hdmi->connector.dev;
2671 unsigned long flags;
2672 int idx;
2673
2674 if (!drm_dev_enter(drm, &idx))
2675 /*
2676 * We can't return an error code, because the CEC
2677 * framework will emit WARN_ON messages at unbind
2678 * otherwise.
2679 */
2680 return 0;
2681
2682 mutex_lock(&vc4_hdmi->mutex);
2683
2684 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2685
2686 if (!vc4_hdmi->variant->external_irq_controller)
2687 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2688
2689 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2690 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2691
2692 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2693
2694 mutex_unlock(&vc4_hdmi->mutex);
2695
2696 pm_runtime_put(&vc4_hdmi->pdev->dev);
2697
2698 drm_dev_exit(idx);
2699
2700 return 0;
2701}
2702
2703static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2704{
2705 if (enable)
2706 return vc4_hdmi_cec_enable(adap);
2707 else
2708 return vc4_hdmi_cec_disable(adap);
2709}
2710
2711static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2712{
2713 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2714 struct drm_device *drm = vc4_hdmi->connector.dev;
2715 unsigned long flags;
2716 int idx;
2717
2718 if (!drm_dev_enter(drm, &idx))
2719 /*
2720 * We can't return an error code, because the CEC
2721 * framework will emit WARN_ON messages at unbind
2722 * otherwise.
2723 */
2724 return 0;
2725
2726 mutex_lock(&vc4_hdmi->mutex);
2727 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2728 HDMI_WRITE(HDMI_CEC_CNTRL_1,
2729 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2730 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2731 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2732 mutex_unlock(&vc4_hdmi->mutex);
2733
2734 drm_dev_exit(idx);
2735
2736 return 0;
2737}
2738
2739static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2740 u32 signal_free_time, struct cec_msg *msg)
2741{
2742 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2743 struct drm_device *dev = vc4_hdmi->connector.dev;
2744 unsigned long flags;
2745 u32 val;
2746 unsigned int i;
2747 int idx;
2748
2749 if (!drm_dev_enter(dev, &idx))
2750 return -ENODEV;
2751
2752 if (msg->len > 16) {
2753 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2754 drm_dev_exit(idx);
2755 return -ENOMEM;
2756 }
2757
2758 mutex_lock(&vc4_hdmi->mutex);
2759
2760 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2761
2762 for (i = 0; i < msg->len; i += 4)
2763 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2764 (msg->msg[i]) |
2765 (msg->msg[i + 1] << 8) |
2766 (msg->msg[i + 2] << 16) |
2767 (msg->msg[i + 3] << 24));
2768
2769 val = HDMI_READ(HDMI_CEC_CNTRL_1);
2770 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2771 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2772 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2773 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2774 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2775
2776 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2777
2778 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2779 mutex_unlock(&vc4_hdmi->mutex);
2780 drm_dev_exit(idx);
2781
2782 return 0;
2783}
2784
2785static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2786 .adap_enable = vc4_hdmi_cec_adap_enable,
2787 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2788 .adap_transmit = vc4_hdmi_cec_adap_transmit,
2789};
2790
2791static void vc4_hdmi_cec_release(void *ptr)
2792{
2793 struct vc4_hdmi *vc4_hdmi = ptr;
2794
2795 cec_unregister_adapter(vc4_hdmi->cec_adap);
2796 vc4_hdmi->cec_adap = NULL;
2797}
2798
2799static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2800{
2801 struct cec_connector_info conn_info;
2802 struct platform_device *pdev = vc4_hdmi->pdev;
2803 struct device *dev = &pdev->dev;
2804 int ret;
2805
2806 if (!of_property_present(dev->of_node, "interrupts")) {
2807 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
2808 return 0;
2809 }
2810
2811 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
2812 vc4_hdmi,
2813 vc4_hdmi->variant->card_name,
2814 CEC_CAP_DEFAULTS |
2815 CEC_CAP_CONNECTOR_INFO, 1);
2816 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
2817 if (ret < 0)
2818 return ret;
2819
2820 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
2821 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
2822
2823 if (vc4_hdmi->variant->external_irq_controller) {
2824 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
2825 vc4_cec_irq_handler_rx_bare,
2826 vc4_cec_irq_handler_rx_thread, 0,
2827 "vc4 hdmi cec rx", vc4_hdmi);
2828 if (ret)
2829 goto err_delete_cec_adap;
2830
2831 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
2832 vc4_cec_irq_handler_tx_bare,
2833 vc4_cec_irq_handler_tx_thread, 0,
2834 "vc4 hdmi cec tx", vc4_hdmi);
2835 if (ret)
2836 goto err_delete_cec_adap;
2837 } else {
2838 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
2839 vc4_cec_irq_handler,
2840 vc4_cec_irq_handler_thread, 0,
2841 "vc4 hdmi cec", vc4_hdmi);
2842 if (ret)
2843 goto err_delete_cec_adap;
2844 }
2845
2846 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
2847 if (ret < 0)
2848 goto err_delete_cec_adap;
2849
2850 /*
2851 * NOTE: Strictly speaking, we should probably use a DRM-managed
2852 * registration there to avoid removing the CEC adapter by the
2853 * time the DRM driver doesn't have any user anymore.
2854 *
2855 * However, the CEC framework already cleans up the CEC adapter
2856 * only when the last user has closed its file descriptor, so we
2857 * don't need to handle it in DRM.
2858 *
2859 * By the time the device-managed hook is executed, we will give
2860 * up our reference to the CEC adapter and therefore don't
2861 * really care when it's actually freed.
2862 *
2863 * There's still a problematic sequence: if we unregister our
2864 * CEC adapter, but the userspace keeps a handle on the CEC
2865 * adapter but not the DRM device for some reason. In such a
2866 * case, our vc4_hdmi structure will be freed, but the
2867 * cec_adapter structure will have a dangling pointer to what
2868 * used to be our HDMI controller. If we get a CEC call at that
2869 * moment, we could end up with a use-after-free. Fortunately,
2870 * the CEC framework already handles this too, by calling
2871 * cec_is_registered() in cec_ioctl() and cec_poll().
2872 */
2873 ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
2874 if (ret)
2875 return ret;
2876
2877 return 0;
2878
2879err_delete_cec_adap:
2880 cec_delete_adapter(vc4_hdmi->cec_adap);
2881
2882 return ret;
2883}
2884#else
2885static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2886{
2887 return 0;
2888}
2889#endif
2890
2891static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr)
2892{
2893 struct debugfs_reg32 *regs = ptr;
2894
2895 kfree(regs);
2896}
2897
2898static int vc4_hdmi_build_regset(struct drm_device *drm,
2899 struct vc4_hdmi *vc4_hdmi,
2900 struct debugfs_regset32 *regset,
2901 enum vc4_hdmi_regs reg)
2902{
2903 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2904 struct debugfs_reg32 *regs, *new_regs;
2905 unsigned int count = 0;
2906 unsigned int i;
2907 int ret;
2908
2909 regs = kcalloc(variant->num_registers, sizeof(*regs),
2910 GFP_KERNEL);
2911 if (!regs)
2912 return -ENOMEM;
2913
2914 for (i = 0; i < variant->num_registers; i++) {
2915 const struct vc4_hdmi_register *field = &variant->registers[i];
2916
2917 if (field->reg != reg)
2918 continue;
2919
2920 regs[count].name = field->name;
2921 regs[count].offset = field->offset;
2922 count++;
2923 }
2924
2925 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
2926 if (!new_regs)
2927 return -ENOMEM;
2928
2929 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
2930 regset->regs = new_regs;
2931 regset->nregs = count;
2932
2933 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
2934 if (ret)
2935 return ret;
2936
2937 return 0;
2938}
2939
2940static int vc4_hdmi_init_resources(struct drm_device *drm,
2941 struct vc4_hdmi *vc4_hdmi)
2942{
2943 struct platform_device *pdev = vc4_hdmi->pdev;
2944 struct device *dev = &pdev->dev;
2945 int ret;
2946
2947 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
2948 if (IS_ERR(vc4_hdmi->hdmicore_regs))
2949 return PTR_ERR(vc4_hdmi->hdmicore_regs);
2950
2951 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
2952 if (IS_ERR(vc4_hdmi->hd_regs))
2953 return PTR_ERR(vc4_hdmi->hd_regs);
2954
2955 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2956 if (ret)
2957 return ret;
2958
2959 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2960 if (ret)
2961 return ret;
2962
2963 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
2964 if (IS_ERR(vc4_hdmi->pixel_clock)) {
2965 ret = PTR_ERR(vc4_hdmi->pixel_clock);
2966 if (ret != -EPROBE_DEFER)
2967 drm_err(drm, "Failed to get pixel clock\n");
2968 return ret;
2969 }
2970
2971 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2972 if (IS_ERR(vc4_hdmi->hsm_clock)) {
2973 drm_err(drm, "Failed to get HDMI state machine clock\n");
2974 return PTR_ERR(vc4_hdmi->hsm_clock);
2975 }
2976 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2977 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2978
2979 return 0;
2980}
2981
2982static int vc5_hdmi_init_resources(struct drm_device *drm,
2983 struct vc4_hdmi *vc4_hdmi)
2984{
2985 struct platform_device *pdev = vc4_hdmi->pdev;
2986 struct device *dev = &pdev->dev;
2987 struct resource *res;
2988 int ret;
2989
2990 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2991 if (!res)
2992 return -ENODEV;
2993
2994 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2995 resource_size(res));
2996 if (!vc4_hdmi->hdmicore_regs)
2997 return -ENOMEM;
2998
2999 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
3000 if (!res)
3001 return -ENODEV;
3002
3003 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
3004 if (!vc4_hdmi->hd_regs)
3005 return -ENOMEM;
3006
3007 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
3008 if (!res)
3009 return -ENODEV;
3010
3011 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
3012 if (!vc4_hdmi->cec_regs)
3013 return -ENOMEM;
3014
3015 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
3016 if (!res)
3017 return -ENODEV;
3018
3019 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
3020 if (!vc4_hdmi->csc_regs)
3021 return -ENOMEM;
3022
3023 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
3024 if (!res)
3025 return -ENODEV;
3026
3027 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
3028 if (!vc4_hdmi->dvp_regs)
3029 return -ENOMEM;
3030
3031 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
3032 if (!res)
3033 return -ENODEV;
3034
3035 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
3036 if (!vc4_hdmi->phy_regs)
3037 return -ENOMEM;
3038
3039 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
3040 if (!res)
3041 return -ENODEV;
3042
3043 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
3044 if (!vc4_hdmi->ram_regs)
3045 return -ENOMEM;
3046
3047 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
3048 if (!res)
3049 return -ENODEV;
3050
3051 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
3052 if (!vc4_hdmi->rm_regs)
3053 return -ENOMEM;
3054
3055 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3056 if (IS_ERR(vc4_hdmi->hsm_clock)) {
3057 drm_err(drm, "Failed to get HDMI state machine clock\n");
3058 return PTR_ERR(vc4_hdmi->hsm_clock);
3059 }
3060
3061 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3062 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3063 drm_err(drm, "Failed to get pixel bvb clock\n");
3064 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
3065 }
3066
3067 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
3068 if (IS_ERR(vc4_hdmi->audio_clock)) {
3069 drm_err(drm, "Failed to get audio clock\n");
3070 return PTR_ERR(vc4_hdmi->audio_clock);
3071 }
3072
3073 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
3074 if (IS_ERR(vc4_hdmi->cec_clock)) {
3075 drm_err(drm, "Failed to get CEC clock\n");
3076 return PTR_ERR(vc4_hdmi->cec_clock);
3077 }
3078
3079 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3080 if (IS_ERR(vc4_hdmi->reset)) {
3081 drm_err(drm, "Failed to get HDMI reset line\n");
3082 return PTR_ERR(vc4_hdmi->reset);
3083 }
3084
3085 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3086 if (ret)
3087 return ret;
3088
3089 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3090 if (ret)
3091 return ret;
3092
3093 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
3094 if (ret)
3095 return ret;
3096
3097 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
3098 if (ret)
3099 return ret;
3100
3101 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
3102 if (ret)
3103 return ret;
3104
3105 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
3106 if (ret)
3107 return ret;
3108
3109 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
3110 if (ret)
3111 return ret;
3112
3113 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
3114 if (ret)
3115 return ret;
3116
3117 return 0;
3118}
3119
3120static int vc4_hdmi_runtime_suspend(struct device *dev)
3121{
3122 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3123
3124 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3125
3126 return 0;
3127}
3128
3129static int vc4_hdmi_runtime_resume(struct device *dev)
3130{
3131 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3132 unsigned long __maybe_unused flags;
3133 u32 __maybe_unused value;
3134 unsigned long rate;
3135 int ret;
3136
3137 ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
3138 if (ret)
3139 return ret;
3140
3141 /*
3142 * Whenever the RaspberryPi boots without an HDMI monitor
3143 * plugged in, the firmware won't have initialized the HSM clock
3144 * rate and it will be reported as 0.
3145 *
3146 * If we try to access a register of the controller in such a
3147 * case, it will lead to a silent CPU stall. Let's make sure we
3148 * prevent such a case.
3149 */
3150 rate = clk_get_rate(vc4_hdmi->hsm_clock);
3151 if (!rate) {
3152 ret = -EINVAL;
3153 goto err_disable_clk;
3154 }
3155
3156 if (vc4_hdmi->variant->reset)
3157 vc4_hdmi->variant->reset(vc4_hdmi);
3158
3159#ifdef CONFIG_DRM_VC4_HDMI_CEC
3160 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3161 value = HDMI_READ(HDMI_CEC_CNTRL_1);
3162 /* Set the logical address to Unregistered */
3163 value |= VC4_HDMI_CEC_ADDR_MASK;
3164 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
3165 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3166
3167 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
3168
3169 if (!vc4_hdmi->variant->external_irq_controller) {
3170 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3171 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3172 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3173 }
3174#endif
3175
3176 return 0;
3177
3178err_disable_clk:
3179 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3180 return ret;
3181}
3182
3183static void vc4_hdmi_put_ddc_device(void *ptr)
3184{
3185 struct vc4_hdmi *vc4_hdmi = ptr;
3186
3187 put_device(&vc4_hdmi->ddc->dev);
3188}
3189
3190static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
3191{
3192 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
3193 struct platform_device *pdev = to_platform_device(dev);
3194 struct drm_device *drm = dev_get_drvdata(master);
3195 struct vc4_hdmi *vc4_hdmi;
3196 struct drm_encoder *encoder;
3197 struct device_node *ddc_node;
3198 int ret;
3199
3200 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
3201 if (!vc4_hdmi)
3202 return -ENOMEM;
3203
3204 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex);
3205 if (ret)
3206 return ret;
3207
3208 spin_lock_init(&vc4_hdmi->hw_lock);
3209 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
3210
3211 dev_set_drvdata(dev, vc4_hdmi);
3212 encoder = &vc4_hdmi->encoder.base;
3213 vc4_hdmi->encoder.type = variant->encoder_type;
3214 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
3215 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
3216 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
3217 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
3218 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
3219 vc4_hdmi->pdev = pdev;
3220 vc4_hdmi->variant = variant;
3221
3222 /*
3223 * Since we don't know the state of the controller and its
3224 * display (if any), let's assume it's always enabled.
3225 * vc4_hdmi_disable_scrambling() will thus run at boot, make
3226 * sure it's disabled, and avoid any inconsistency.
3227 */
3228 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
3229 vc4_hdmi->scdc_enabled = true;
3230
3231 ret = variant->init_resources(drm, vc4_hdmi);
3232 if (ret)
3233 return ret;
3234
3235 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3236 if (!ddc_node) {
3237 drm_err(drm, "Failed to find ddc node in device tree\n");
3238 return -ENODEV;
3239 }
3240
3241 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3242 of_node_put(ddc_node);
3243 if (!vc4_hdmi->ddc) {
3244 drm_err(drm, "Failed to get ddc i2c adapter by node\n");
3245 return -EPROBE_DEFER;
3246 }
3247
3248 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
3249 if (ret)
3250 return ret;
3251
3252 /* Only use the GPIO HPD pin if present in the DT, otherwise
3253 * we'll use the HDMI core's register.
3254 */
3255 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3256 if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3257 return PTR_ERR(vc4_hdmi->hpd_gpio);
3258 }
3259
3260 vc4_hdmi->disable_wifi_frequencies =
3261 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3262
3263 ret = devm_pm_runtime_enable(dev);
3264 if (ret)
3265 return ret;
3266
3267 /*
3268 * We need to have the device powered up at this point to call
3269 * our reset hook and for the CEC init.
3270 */
3271 ret = pm_runtime_resume_and_get(dev);
3272 if (ret)
3273 return ret;
3274
3275 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3276 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
3277 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3278 clk_prepare_enable(vc4_hdmi->pixel_clock);
3279 clk_prepare_enable(vc4_hdmi->hsm_clock);
3280 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3281 }
3282
3283 ret = drmm_encoder_init(drm, encoder,
3284 &vc4_hdmi_encoder_funcs,
3285 DRM_MODE_ENCODER_TMDS,
3286 NULL);
3287 if (ret)
3288 goto err_put_runtime_pm;
3289
3290 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3291
3292 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3293 if (ret)
3294 goto err_put_runtime_pm;
3295
3296 ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3297 if (ret)
3298 goto err_put_runtime_pm;
3299
3300 ret = vc4_hdmi_cec_init(vc4_hdmi);
3301 if (ret)
3302 goto err_put_runtime_pm;
3303
3304 ret = vc4_hdmi_audio_init(vc4_hdmi);
3305 if (ret)
3306 goto err_put_runtime_pm;
3307
3308 pm_runtime_put_sync(dev);
3309
3310 return 0;
3311
3312err_put_runtime_pm:
3313 pm_runtime_put_sync(dev);
3314
3315 return ret;
3316}
3317
3318static const struct component_ops vc4_hdmi_ops = {
3319 .bind = vc4_hdmi_bind,
3320};
3321
3322static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3323{
3324 return component_add(&pdev->dev, &vc4_hdmi_ops);
3325}
3326
3327static void vc4_hdmi_dev_remove(struct platform_device *pdev)
3328{
3329 component_del(&pdev->dev, &vc4_hdmi_ops);
3330}
3331
3332static const struct vc4_hdmi_variant bcm2835_variant = {
3333 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3334 .debugfs_name = "hdmi_regs",
3335 .card_name = "vc4-hdmi",
3336 .max_pixel_clock = 162000000,
3337 .registers = vc4_hdmi_fields,
3338 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
3339
3340 .init_resources = vc4_hdmi_init_resources,
3341 .csc_setup = vc4_hdmi_csc_setup,
3342 .reset = vc4_hdmi_reset,
3343 .set_timings = vc4_hdmi_set_timings,
3344 .phy_init = vc4_hdmi_phy_init,
3345 .phy_disable = vc4_hdmi_phy_disable,
3346 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
3347 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
3348 .channel_map = vc4_hdmi_channel_map,
3349 .supports_hdr = false,
3350};
3351
3352static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3353 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3354 .debugfs_name = "hdmi0_regs",
3355 .card_name = "vc4-hdmi-0",
3356 .max_pixel_clock = 600000000,
3357 .registers = vc5_hdmi_hdmi0_fields,
3358 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3359 .phy_lane_mapping = {
3360 PHY_LANE_0,
3361 PHY_LANE_1,
3362 PHY_LANE_2,
3363 PHY_LANE_CK,
3364 },
3365 .unsupported_odd_h_timings = true,
3366 .external_irq_controller = true,
3367
3368 .init_resources = vc5_hdmi_init_resources,
3369 .csc_setup = vc5_hdmi_csc_setup,
3370 .reset = vc5_hdmi_reset,
3371 .set_timings = vc5_hdmi_set_timings,
3372 .phy_init = vc5_hdmi_phy_init,
3373 .phy_disable = vc5_hdmi_phy_disable,
3374 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3375 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3376 .channel_map = vc5_hdmi_channel_map,
3377 .supports_hdr = true,
3378 .hp_detect = vc5_hdmi_hp_detect,
3379};
3380
3381static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3382 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
3383 .debugfs_name = "hdmi1_regs",
3384 .card_name = "vc4-hdmi-1",
3385 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
3386 .registers = vc5_hdmi_hdmi1_fields,
3387 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3388 .phy_lane_mapping = {
3389 PHY_LANE_1,
3390 PHY_LANE_0,
3391 PHY_LANE_CK,
3392 PHY_LANE_2,
3393 },
3394 .unsupported_odd_h_timings = true,
3395 .external_irq_controller = true,
3396
3397 .init_resources = vc5_hdmi_init_resources,
3398 .csc_setup = vc5_hdmi_csc_setup,
3399 .reset = vc5_hdmi_reset,
3400 .set_timings = vc5_hdmi_set_timings,
3401 .phy_init = vc5_hdmi_phy_init,
3402 .phy_disable = vc5_hdmi_phy_disable,
3403 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3404 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3405 .channel_map = vc5_hdmi_channel_map,
3406 .supports_hdr = true,
3407 .hp_detect = vc5_hdmi_hp_detect,
3408};
3409
3410static const struct of_device_id vc4_hdmi_dt_match[] = {
3411 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3412 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3413 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3414 {}
3415};
3416
3417static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3418 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3419 vc4_hdmi_runtime_resume,
3420 NULL)
3421};
3422
3423struct platform_driver vc4_hdmi_driver = {
3424 .probe = vc4_hdmi_dev_probe,
3425 .remove = vc4_hdmi_dev_remove,
3426 .driver = {
3427 .name = "vc4_hdmi",
3428 .of_match_table = vc4_hdmi_dt_match,
3429 .pm = &vc4_hdmi_pm_ops,
3430 },
3431};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
7 */
8
9/**
10 * DOC: VC4 Falcon HDMI module
11 *
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
15 *
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
18 *
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
23 * blank regions.
24 *
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
29 *
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
32 */
33
34#include <drm/drm_atomic_helper.h>
35#include <drm/drm_edid.h>
36#include <drm/drm_probe_helper.h>
37#include <linux/clk.h>
38#include <linux/component.h>
39#include <linux/i2c.h>
40#include <linux/of_address.h>
41#include <linux/of_gpio.h>
42#include <linux/of_platform.h>
43#include <linux/pm_runtime.h>
44#include <linux/rational.h>
45#include <sound/dmaengine_pcm.h>
46#include <sound/pcm_drm_eld.h>
47#include <sound/pcm_params.h>
48#include <sound/soc.h>
49#include "media/cec.h"
50#include "vc4_drv.h"
51#include "vc4_regs.h"
52
53#define HSM_CLOCK_FREQ 163682864
54#define CEC_CLOCK_FREQ 40000
55#define CEC_CLOCK_DIV (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ)
56
57/* HDMI audio information */
58struct vc4_hdmi_audio {
59 struct snd_soc_card card;
60 struct snd_soc_dai_link link;
61 struct snd_soc_dai_link_component cpu;
62 struct snd_soc_dai_link_component codec;
63 struct snd_soc_dai_link_component platform;
64 int samplerate;
65 int channels;
66 struct snd_dmaengine_dai_dma_data dma_data;
67 struct snd_pcm_substream *substream;
68};
69
70/* General HDMI hardware state. */
71struct vc4_hdmi {
72 struct platform_device *pdev;
73
74 struct drm_encoder *encoder;
75 struct drm_connector *connector;
76
77 struct vc4_hdmi_audio audio;
78
79 struct i2c_adapter *ddc;
80 void __iomem *hdmicore_regs;
81 void __iomem *hd_regs;
82 int hpd_gpio;
83 bool hpd_active_low;
84
85 struct cec_adapter *cec_adap;
86 struct cec_msg cec_rx_msg;
87 bool cec_tx_ok;
88 bool cec_irq_was_rx;
89
90 struct clk *pixel_clock;
91 struct clk *hsm_clock;
92
93 struct debugfs_regset32 hdmi_regset;
94 struct debugfs_regset32 hd_regset;
95};
96
97#define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
98#define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
99#define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
100#define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)
101
102/* VC4 HDMI encoder KMS struct */
103struct vc4_hdmi_encoder {
104 struct vc4_encoder base;
105 bool hdmi_monitor;
106 bool limited_rgb_range;
107};
108
109static inline struct vc4_hdmi_encoder *
110to_vc4_hdmi_encoder(struct drm_encoder *encoder)
111{
112 return container_of(encoder, struct vc4_hdmi_encoder, base.base);
113}
114
115/* VC4 HDMI connector KMS struct */
116struct vc4_hdmi_connector {
117 struct drm_connector base;
118
119 /* Since the connector is attached to just the one encoder,
120 * this is the reference to it so we can do the best_encoder()
121 * hook.
122 */
123 struct drm_encoder *encoder;
124};
125
126static inline struct vc4_hdmi_connector *
127to_vc4_hdmi_connector(struct drm_connector *connector)
128{
129 return container_of(connector, struct vc4_hdmi_connector, base);
130}
131
132static const struct debugfs_reg32 hdmi_regs[] = {
133 VC4_REG32(VC4_HDMI_CORE_REV),
134 VC4_REG32(VC4_HDMI_SW_RESET_CONTROL),
135 VC4_REG32(VC4_HDMI_HOTPLUG_INT),
136 VC4_REG32(VC4_HDMI_HOTPLUG),
137 VC4_REG32(VC4_HDMI_MAI_CHANNEL_MAP),
138 VC4_REG32(VC4_HDMI_MAI_CONFIG),
139 VC4_REG32(VC4_HDMI_MAI_FORMAT),
140 VC4_REG32(VC4_HDMI_AUDIO_PACKET_CONFIG),
141 VC4_REG32(VC4_HDMI_RAM_PACKET_CONFIG),
142 VC4_REG32(VC4_HDMI_HORZA),
143 VC4_REG32(VC4_HDMI_HORZB),
144 VC4_REG32(VC4_HDMI_FIFO_CTL),
145 VC4_REG32(VC4_HDMI_SCHEDULER_CONTROL),
146 VC4_REG32(VC4_HDMI_VERTA0),
147 VC4_REG32(VC4_HDMI_VERTA1),
148 VC4_REG32(VC4_HDMI_VERTB0),
149 VC4_REG32(VC4_HDMI_VERTB1),
150 VC4_REG32(VC4_HDMI_TX_PHY_RESET_CTL),
151 VC4_REG32(VC4_HDMI_TX_PHY_CTL0),
152
153 VC4_REG32(VC4_HDMI_CEC_CNTRL_1),
154 VC4_REG32(VC4_HDMI_CEC_CNTRL_2),
155 VC4_REG32(VC4_HDMI_CEC_CNTRL_3),
156 VC4_REG32(VC4_HDMI_CEC_CNTRL_4),
157 VC4_REG32(VC4_HDMI_CEC_CNTRL_5),
158 VC4_REG32(VC4_HDMI_CPU_STATUS),
159 VC4_REG32(VC4_HDMI_CPU_MASK_STATUS),
160
161 VC4_REG32(VC4_HDMI_CEC_RX_DATA_1),
162 VC4_REG32(VC4_HDMI_CEC_RX_DATA_2),
163 VC4_REG32(VC4_HDMI_CEC_RX_DATA_3),
164 VC4_REG32(VC4_HDMI_CEC_RX_DATA_4),
165 VC4_REG32(VC4_HDMI_CEC_TX_DATA_1),
166 VC4_REG32(VC4_HDMI_CEC_TX_DATA_2),
167 VC4_REG32(VC4_HDMI_CEC_TX_DATA_3),
168 VC4_REG32(VC4_HDMI_CEC_TX_DATA_4),
169};
170
171static const struct debugfs_reg32 hd_regs[] = {
172 VC4_REG32(VC4_HD_M_CTL),
173 VC4_REG32(VC4_HD_MAI_CTL),
174 VC4_REG32(VC4_HD_MAI_THR),
175 VC4_REG32(VC4_HD_MAI_FMT),
176 VC4_REG32(VC4_HD_MAI_SMP),
177 VC4_REG32(VC4_HD_VID_CTL),
178 VC4_REG32(VC4_HD_CSC_CTL),
179 VC4_REG32(VC4_HD_FRAME_COUNT),
180};
181
182static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
183{
184 struct drm_info_node *node = (struct drm_info_node *)m->private;
185 struct drm_device *dev = node->minor->dev;
186 struct vc4_dev *vc4 = to_vc4_dev(dev);
187 struct vc4_hdmi *hdmi = vc4->hdmi;
188 struct drm_printer p = drm_seq_file_printer(m);
189
190 drm_print_regset32(&p, &hdmi->hdmi_regset);
191 drm_print_regset32(&p, &hdmi->hd_regset);
192
193 return 0;
194}
195
196static enum drm_connector_status
197vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
198{
199 struct drm_device *dev = connector->dev;
200 struct vc4_dev *vc4 = to_vc4_dev(dev);
201
202 if (vc4->hdmi->hpd_gpio) {
203 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^
204 vc4->hdmi->hpd_active_low)
205 return connector_status_connected;
206 cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
207 return connector_status_disconnected;
208 }
209
210 if (drm_probe_ddc(vc4->hdmi->ddc))
211 return connector_status_connected;
212
213 if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
214 return connector_status_connected;
215 cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
216 return connector_status_disconnected;
217}
218
219static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
220{
221 drm_connector_unregister(connector);
222 drm_connector_cleanup(connector);
223}
224
225static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
226{
227 struct vc4_hdmi_connector *vc4_connector =
228 to_vc4_hdmi_connector(connector);
229 struct drm_encoder *encoder = vc4_connector->encoder;
230 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
231 struct drm_device *dev = connector->dev;
232 struct vc4_dev *vc4 = to_vc4_dev(dev);
233 int ret = 0;
234 struct edid *edid;
235
236 edid = drm_get_edid(connector, vc4->hdmi->ddc);
237 cec_s_phys_addr_from_edid(vc4->hdmi->cec_adap, edid);
238 if (!edid)
239 return -ENODEV;
240
241 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
242
243 drm_connector_update_edid_property(connector, edid);
244 ret = drm_add_edid_modes(connector, edid);
245 kfree(edid);
246
247 return ret;
248}
249
250static void vc4_hdmi_connector_reset(struct drm_connector *connector)
251{
252 drm_atomic_helper_connector_reset(connector);
253 drm_atomic_helper_connector_tv_reset(connector);
254}
255
256static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
257 .detect = vc4_hdmi_connector_detect,
258 .fill_modes = drm_helper_probe_single_connector_modes,
259 .destroy = vc4_hdmi_connector_destroy,
260 .reset = vc4_hdmi_connector_reset,
261 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
262 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
263};
264
265static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
266 .get_modes = vc4_hdmi_connector_get_modes,
267};
268
269static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
270 struct drm_encoder *encoder)
271{
272 struct drm_connector *connector;
273 struct vc4_hdmi_connector *hdmi_connector;
274 int ret;
275
276 hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector),
277 GFP_KERNEL);
278 if (!hdmi_connector)
279 return ERR_PTR(-ENOMEM);
280 connector = &hdmi_connector->base;
281
282 hdmi_connector->encoder = encoder;
283
284 drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs,
285 DRM_MODE_CONNECTOR_HDMIA);
286 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
287
288 /* Create and attach TV margin props to this connector. */
289 ret = drm_mode_create_tv_margin_properties(dev);
290 if (ret)
291 return ERR_PTR(ret);
292
293 drm_connector_attach_tv_margin_properties(connector);
294
295 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
296 DRM_CONNECTOR_POLL_DISCONNECT);
297
298 connector->interlace_allowed = 1;
299 connector->doublescan_allowed = 0;
300
301 drm_connector_attach_encoder(connector, encoder);
302
303 return connector;
304}
305
306static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder)
307{
308 drm_encoder_cleanup(encoder);
309}
310
311static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
312 .destroy = vc4_hdmi_encoder_destroy,
313};
314
315static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
316 enum hdmi_infoframe_type type)
317{
318 struct drm_device *dev = encoder->dev;
319 struct vc4_dev *vc4 = to_vc4_dev(dev);
320 u32 packet_id = type - 0x80;
321
322 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
323 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
324
325 return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
326 BIT(packet_id)), 100);
327}
328
329static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
330 union hdmi_infoframe *frame)
331{
332 struct drm_device *dev = encoder->dev;
333 struct vc4_dev *vc4 = to_vc4_dev(dev);
334 u32 packet_id = frame->any.type - 0x80;
335 u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id);
336 uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
337 ssize_t len, i;
338 int ret;
339
340 WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
341 VC4_HDMI_RAM_PACKET_ENABLE),
342 "Packet RAM has to be on to store the packet.");
343
344 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
345 if (len < 0)
346 return;
347
348 ret = vc4_hdmi_stop_packet(encoder, frame->any.type);
349 if (ret) {
350 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
351 return;
352 }
353
354 for (i = 0; i < len; i += 7) {
355 HDMI_WRITE(packet_reg,
356 buffer[i + 0] << 0 |
357 buffer[i + 1] << 8 |
358 buffer[i + 2] << 16);
359 packet_reg += 4;
360
361 HDMI_WRITE(packet_reg,
362 buffer[i + 3] << 0 |
363 buffer[i + 4] << 8 |
364 buffer[i + 5] << 16 |
365 buffer[i + 6] << 24);
366 packet_reg += 4;
367 }
368
369 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
370 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
371 ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
372 BIT(packet_id)), 100);
373 if (ret)
374 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
375}
376
377static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
378{
379 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
380 struct vc4_dev *vc4 = encoder->dev->dev_private;
381 struct vc4_hdmi *hdmi = vc4->hdmi;
382 struct drm_connector_state *cstate = hdmi->connector->state;
383 struct drm_crtc *crtc = encoder->crtc;
384 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
385 union hdmi_infoframe frame;
386 int ret;
387
388 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
389 hdmi->connector, mode);
390 if (ret < 0) {
391 DRM_ERROR("couldn't fill AVI infoframe\n");
392 return;
393 }
394
395 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
396 hdmi->connector, mode,
397 vc4_encoder->limited_rgb_range ?
398 HDMI_QUANTIZATION_RANGE_LIMITED :
399 HDMI_QUANTIZATION_RANGE_FULL);
400
401 frame.avi.right_bar = cstate->tv.margins.right;
402 frame.avi.left_bar = cstate->tv.margins.left;
403 frame.avi.top_bar = cstate->tv.margins.top;
404 frame.avi.bottom_bar = cstate->tv.margins.bottom;
405
406 vc4_hdmi_write_infoframe(encoder, &frame);
407}
408
409static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
410{
411 union hdmi_infoframe frame;
412 int ret;
413
414 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
415 if (ret < 0) {
416 DRM_ERROR("couldn't fill SPD infoframe\n");
417 return;
418 }
419
420 frame.spd.sdi = HDMI_SPD_SDI_PC;
421
422 vc4_hdmi_write_infoframe(encoder, &frame);
423}
424
425static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
426{
427 struct drm_device *drm = encoder->dev;
428 struct vc4_dev *vc4 = drm->dev_private;
429 struct vc4_hdmi *hdmi = vc4->hdmi;
430 union hdmi_infoframe frame;
431 int ret;
432
433 ret = hdmi_audio_infoframe_init(&frame.audio);
434
435 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
436 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
437 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
438 frame.audio.channels = hdmi->audio.channels;
439
440 vc4_hdmi_write_infoframe(encoder, &frame);
441}
442
443static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
444{
445 vc4_hdmi_set_avi_infoframe(encoder);
446 vc4_hdmi_set_spd_infoframe(encoder);
447}
448
449static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
450{
451 struct drm_device *dev = encoder->dev;
452 struct vc4_dev *vc4 = to_vc4_dev(dev);
453 struct vc4_hdmi *hdmi = vc4->hdmi;
454 int ret;
455
456 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0);
457
458 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
459 HD_WRITE(VC4_HD_VID_CTL,
460 HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
461
462 clk_disable_unprepare(hdmi->pixel_clock);
463
464 ret = pm_runtime_put(&hdmi->pdev->dev);
465 if (ret < 0)
466 DRM_ERROR("Failed to release power domain: %d\n", ret);
467}
468
469static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
470{
471 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
472 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
473 struct drm_device *dev = encoder->dev;
474 struct vc4_dev *vc4 = to_vc4_dev(dev);
475 struct vc4_hdmi *hdmi = vc4->hdmi;
476 bool debug_dump_regs = false;
477 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
478 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
479 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
480 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
481 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
482 VC4_HDMI_VERTA_VSP) |
483 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
484 VC4_HDMI_VERTA_VFP) |
485 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
486 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
487 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
488 VC4_HDMI_VERTB_VBP));
489 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
490 VC4_SET_FIELD(mode->crtc_vtotal -
491 mode->crtc_vsync_end -
492 interlaced,
493 VC4_HDMI_VERTB_VBP));
494 u32 csc_ctl;
495 int ret;
496
497 ret = pm_runtime_get_sync(&hdmi->pdev->dev);
498 if (ret < 0) {
499 DRM_ERROR("Failed to retain power domain: %d\n", ret);
500 return;
501 }
502
503 ret = clk_set_rate(hdmi->pixel_clock,
504 mode->clock * 1000 *
505 ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1));
506 if (ret) {
507 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
508 return;
509 }
510
511 ret = clk_prepare_enable(hdmi->pixel_clock);
512 if (ret) {
513 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
514 return;
515 }
516
517 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,
518 VC4_HDMI_SW_RESET_HDMI |
519 VC4_HDMI_SW_RESET_FORMAT_DETECT);
520
521 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);
522
523 /* PHY should be in reset, like
524 * vc4_hdmi_encoder_disable() does.
525 */
526 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
527
528 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0);
529
530 if (debug_dump_regs) {
531 struct drm_printer p = drm_info_printer(&hdmi->pdev->dev);
532
533 dev_info(&hdmi->pdev->dev, "HDMI regs before:\n");
534 drm_print_regset32(&p, &hdmi->hdmi_regset);
535 drm_print_regset32(&p, &hdmi->hd_regset);
536 }
537
538 HD_WRITE(VC4_HD_VID_CTL, 0);
539
540 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
541 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
542 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
543 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
544
545 HDMI_WRITE(VC4_HDMI_HORZA,
546 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
547 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
548 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
549 VC4_HDMI_HORZA_HAP));
550
551 HDMI_WRITE(VC4_HDMI_HORZB,
552 VC4_SET_FIELD((mode->htotal -
553 mode->hsync_end) * pixel_rep,
554 VC4_HDMI_HORZB_HBP) |
555 VC4_SET_FIELD((mode->hsync_end -
556 mode->hsync_start) * pixel_rep,
557 VC4_HDMI_HORZB_HSP) |
558 VC4_SET_FIELD((mode->hsync_start -
559 mode->hdisplay) * pixel_rep,
560 VC4_HDMI_HORZB_HFP));
561
562 HDMI_WRITE(VC4_HDMI_VERTA0, verta);
563 HDMI_WRITE(VC4_HDMI_VERTA1, verta);
564
565 HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even);
566 HDMI_WRITE(VC4_HDMI_VERTB1, vertb);
567
568 HD_WRITE(VC4_HD_VID_CTL,
569 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
570 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
571
572 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
573 VC4_HD_CSC_CTL_ORDER);
574
575 if (vc4_encoder->hdmi_monitor &&
576 drm_default_rgb_quant_range(mode) ==
577 HDMI_QUANTIZATION_RANGE_LIMITED) {
578 /* CEA VICs other than #1 requre limited range RGB
579 * output unless overridden by an AVI infoframe.
580 * Apply a colorspace conversion to squash 0-255 down
581 * to 16-235. The matrix here is:
582 *
583 * [ 0 0 0.8594 16]
584 * [ 0 0.8594 0 16]
585 * [ 0.8594 0 0 16]
586 * [ 0 0 0 1]
587 */
588 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
589 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
590 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
591 VC4_HD_CSC_CTL_MODE);
592
593 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000);
594 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0);
595 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000);
596 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000);
597 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0);
598 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000);
599 vc4_encoder->limited_rgb_range = true;
600 } else {
601 vc4_encoder->limited_rgb_range = false;
602 }
603
604 /* The RGB order applies even when CSC is disabled. */
605 HD_WRITE(VC4_HD_CSC_CTL, csc_ctl);
606
607 HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
608
609 if (debug_dump_regs) {
610 struct drm_printer p = drm_info_printer(&hdmi->pdev->dev);
611
612 dev_info(&hdmi->pdev->dev, "HDMI regs after:\n");
613 drm_print_regset32(&p, &hdmi->hdmi_regset);
614 drm_print_regset32(&p, &hdmi->hd_regset);
615 }
616
617 HD_WRITE(VC4_HD_VID_CTL,
618 HD_READ(VC4_HD_VID_CTL) |
619 VC4_HD_VID_CTL_ENABLE |
620 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
621 VC4_HD_VID_CTL_FRAME_COUNTER_RESET);
622
623 if (vc4_encoder->hdmi_monitor) {
624 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
625 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
626 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
627
628 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
629 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
630 WARN_ONCE(ret, "Timeout waiting for "
631 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
632 } else {
633 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
634 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
635 ~(VC4_HDMI_RAM_PACKET_ENABLE));
636 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
637 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
638 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
639
640 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
641 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
642 WARN_ONCE(ret, "Timeout waiting for "
643 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
644 }
645
646 if (vc4_encoder->hdmi_monitor) {
647 u32 drift;
648
649 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
650 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
651 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
652 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
653 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
654
655 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
656 VC4_HDMI_RAM_PACKET_ENABLE);
657
658 vc4_hdmi_set_infoframes(encoder);
659
660 drift = HDMI_READ(VC4_HDMI_FIFO_CTL);
661 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
662
663 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
664 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
665 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
666 drift | VC4_HDMI_FIFO_CTL_RECENTER);
667 usleep_range(1000, 1100);
668 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
669 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
670 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
671 drift | VC4_HDMI_FIFO_CTL_RECENTER);
672
673 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) &
674 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
675 WARN_ONCE(ret, "Timeout waiting for "
676 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
677 }
678}
679
680static enum drm_mode_status
681vc4_hdmi_encoder_mode_valid(struct drm_encoder *crtc,
682 const struct drm_display_mode *mode)
683{
684 /* HSM clock must be 108% of the pixel clock. Additionally,
685 * the AXI clock needs to be at least 25% of pixel clock, but
686 * HSM ends up being the limiting factor.
687 */
688 if (mode->clock > HSM_CLOCK_FREQ / (1000 * 108 / 100))
689 return MODE_CLOCK_HIGH;
690
691 return MODE_OK;
692}
693
694static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
695 .mode_valid = vc4_hdmi_encoder_mode_valid,
696 .disable = vc4_hdmi_encoder_disable,
697 .enable = vc4_hdmi_encoder_enable,
698};
699
700/* HDMI audio codec callbacks */
701static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *hdmi)
702{
703 struct drm_device *drm = hdmi->encoder->dev;
704 struct vc4_dev *vc4 = to_vc4_dev(drm);
705 u32 hsm_clock = clk_get_rate(hdmi->hsm_clock);
706 unsigned long n, m;
707
708 rational_best_approximation(hsm_clock, hdmi->audio.samplerate,
709 VC4_HD_MAI_SMP_N_MASK >>
710 VC4_HD_MAI_SMP_N_SHIFT,
711 (VC4_HD_MAI_SMP_M_MASK >>
712 VC4_HD_MAI_SMP_M_SHIFT) + 1,
713 &n, &m);
714
715 HD_WRITE(VC4_HD_MAI_SMP,
716 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
717 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
718}
719
720static void vc4_hdmi_set_n_cts(struct vc4_hdmi *hdmi)
721{
722 struct drm_encoder *encoder = hdmi->encoder;
723 struct drm_crtc *crtc = encoder->crtc;
724 struct drm_device *drm = encoder->dev;
725 struct vc4_dev *vc4 = to_vc4_dev(drm);
726 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
727 u32 samplerate = hdmi->audio.samplerate;
728 u32 n, cts;
729 u64 tmp;
730
731 n = 128 * samplerate / 1000;
732 tmp = (u64)(mode->clock * 1000) * n;
733 do_div(tmp, 128 * samplerate);
734 cts = tmp;
735
736 HDMI_WRITE(VC4_HDMI_CRP_CFG,
737 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
738 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
739
740 /*
741 * We could get slightly more accurate clocks in some cases by
742 * providing a CTS_1 value. The two CTS values are alternated
743 * between based on the period fields
744 */
745 HDMI_WRITE(VC4_HDMI_CTS_0, cts);
746 HDMI_WRITE(VC4_HDMI_CTS_1, cts);
747}
748
749static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
750{
751 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
752
753 return snd_soc_card_get_drvdata(card);
754}
755
756static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,
757 struct snd_soc_dai *dai)
758{
759 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
760 struct drm_encoder *encoder = hdmi->encoder;
761 struct vc4_dev *vc4 = to_vc4_dev(encoder->dev);
762 int ret;
763
764 if (hdmi->audio.substream && hdmi->audio.substream != substream)
765 return -EINVAL;
766
767 hdmi->audio.substream = substream;
768
769 /*
770 * If the HDMI encoder hasn't probed, or the encoder is
771 * currently in DVI mode, treat the codec dai as missing.
772 */
773 if (!encoder->crtc || !(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
774 VC4_HDMI_RAM_PACKET_ENABLE))
775 return -ENODEV;
776
777 ret = snd_pcm_hw_constraint_eld(substream->runtime,
778 hdmi->connector->eld);
779 if (ret)
780 return ret;
781
782 return 0;
783}
784
785static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
786{
787 return 0;
788}
789
790static void vc4_hdmi_audio_reset(struct vc4_hdmi *hdmi)
791{
792 struct drm_encoder *encoder = hdmi->encoder;
793 struct drm_device *drm = encoder->dev;
794 struct device *dev = &hdmi->pdev->dev;
795 struct vc4_dev *vc4 = to_vc4_dev(drm);
796 int ret;
797
798 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO);
799 if (ret)
800 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
801
802 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_RESET);
803 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
804 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
805}
806
807static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
808 struct snd_soc_dai *dai)
809{
810 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
811
812 if (substream != hdmi->audio.substream)
813 return;
814
815 vc4_hdmi_audio_reset(hdmi);
816
817 hdmi->audio.substream = NULL;
818}
819
820/* HDMI audio codec callbacks */
821static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
822 struct snd_pcm_hw_params *params,
823 struct snd_soc_dai *dai)
824{
825 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
826 struct drm_encoder *encoder = hdmi->encoder;
827 struct drm_device *drm = encoder->dev;
828 struct device *dev = &hdmi->pdev->dev;
829 struct vc4_dev *vc4 = to_vc4_dev(drm);
830 u32 audio_packet_config, channel_mask;
831 u32 channel_map, i;
832
833 if (substream != hdmi->audio.substream)
834 return -EINVAL;
835
836 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
837 params_rate(params), params_width(params),
838 params_channels(params));
839
840 hdmi->audio.channels = params_channels(params);
841 hdmi->audio.samplerate = params_rate(params);
842
843 HD_WRITE(VC4_HD_MAI_CTL,
844 VC4_HD_MAI_CTL_RESET |
845 VC4_HD_MAI_CTL_FLUSH |
846 VC4_HD_MAI_CTL_DLATE |
847 VC4_HD_MAI_CTL_ERRORE |
848 VC4_HD_MAI_CTL_ERRORF);
849
850 vc4_hdmi_audio_set_mai_clock(hdmi);
851
852 audio_packet_config =
853 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
854 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
855 VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
856
857 channel_mask = GENMASK(hdmi->audio.channels - 1, 0);
858 audio_packet_config |= VC4_SET_FIELD(channel_mask,
859 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
860
861 /* Set the MAI threshold. This logic mimics the firmware's. */
862 if (hdmi->audio.samplerate > 96000) {
863 HD_WRITE(VC4_HD_MAI_THR,
864 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |
865 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
866 } else if (hdmi->audio.samplerate > 48000) {
867 HD_WRITE(VC4_HD_MAI_THR,
868 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |
869 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
870 } else {
871 HD_WRITE(VC4_HD_MAI_THR,
872 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
873 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
874 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
875 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
876 }
877
878 HDMI_WRITE(VC4_HDMI_MAI_CONFIG,
879 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
880 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
881
882 channel_map = 0;
883 for (i = 0; i < 8; i++) {
884 if (channel_mask & BIT(i))
885 channel_map |= i << (3 * i);
886 }
887
888 HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP, channel_map);
889 HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
890 vc4_hdmi_set_n_cts(hdmi);
891
892 return 0;
893}
894
895static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
896 struct snd_soc_dai *dai)
897{
898 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
899 struct drm_encoder *encoder = hdmi->encoder;
900 struct drm_device *drm = encoder->dev;
901 struct vc4_dev *vc4 = to_vc4_dev(drm);
902
903 switch (cmd) {
904 case SNDRV_PCM_TRIGGER_START:
905 vc4_hdmi_set_audio_infoframe(encoder);
906 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,
907 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) &
908 ~VC4_HDMI_TX_PHY_RNG_PWRDN);
909 HD_WRITE(VC4_HD_MAI_CTL,
910 VC4_SET_FIELD(hdmi->audio.channels,
911 VC4_HD_MAI_CTL_CHNUM) |
912 VC4_HD_MAI_CTL_ENABLE);
913 break;
914 case SNDRV_PCM_TRIGGER_STOP:
915 HD_WRITE(VC4_HD_MAI_CTL,
916 VC4_HD_MAI_CTL_DLATE |
917 VC4_HD_MAI_CTL_ERRORE |
918 VC4_HD_MAI_CTL_ERRORF);
919 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0,
920 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) |
921 VC4_HDMI_TX_PHY_RNG_PWRDN);
922 break;
923 default:
924 break;
925 }
926
927 return 0;
928}
929
930static inline struct vc4_hdmi *
931snd_component_to_hdmi(struct snd_soc_component *component)
932{
933 struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
934
935 return snd_soc_card_get_drvdata(card);
936}
937
938static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,
939 struct snd_ctl_elem_info *uinfo)
940{
941 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
942 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component);
943
944 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
945 uinfo->count = sizeof(hdmi->connector->eld);
946
947 return 0;
948}
949
950static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,
951 struct snd_ctl_elem_value *ucontrol)
952{
953 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
954 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component);
955
956 memcpy(ucontrol->value.bytes.data, hdmi->connector->eld,
957 sizeof(hdmi->connector->eld));
958
959 return 0;
960}
961
962static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {
963 {
964 .access = SNDRV_CTL_ELEM_ACCESS_READ |
965 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
966 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
967 .name = "ELD",
968 .info = vc4_hdmi_audio_eld_ctl_info,
969 .get = vc4_hdmi_audio_eld_ctl_get,
970 },
971};
972
973static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
974 SND_SOC_DAPM_OUTPUT("TX"),
975};
976
977static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
978 { "TX", NULL, "Playback" },
979};
980
981static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = {
982 .controls = vc4_hdmi_audio_controls,
983 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls),
984 .dapm_widgets = vc4_hdmi_audio_widgets,
985 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets),
986 .dapm_routes = vc4_hdmi_audio_routes,
987 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes),
988 .idle_bias_on = 1,
989 .use_pmdown_time = 1,
990 .endianness = 1,
991 .non_legacy_dai_naming = 1,
992};
993
994static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {
995 .startup = vc4_hdmi_audio_startup,
996 .shutdown = vc4_hdmi_audio_shutdown,
997 .hw_params = vc4_hdmi_audio_hw_params,
998 .set_fmt = vc4_hdmi_audio_set_fmt,
999 .trigger = vc4_hdmi_audio_trigger,
1000};
1001
1002static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {
1003 .name = "vc4-hdmi-hifi",
1004 .playback = {
1005 .stream_name = "Playback",
1006 .channels_min = 2,
1007 .channels_max = 8,
1008 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1009 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1010 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1011 SNDRV_PCM_RATE_192000,
1012 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1013 },
1014};
1015
1016static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1017 .name = "vc4-hdmi-cpu-dai-component",
1018};
1019
1020static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1021{
1022 struct vc4_hdmi *hdmi = dai_to_hdmi(dai);
1023
1024 snd_soc_dai_init_dma_data(dai, &hdmi->audio.dma_data, NULL);
1025
1026 return 0;
1027}
1028
1029static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1030 .name = "vc4-hdmi-cpu-dai",
1031 .probe = vc4_hdmi_audio_cpu_dai_probe,
1032 .playback = {
1033 .stream_name = "Playback",
1034 .channels_min = 1,
1035 .channels_max = 8,
1036 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1037 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1038 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1039 SNDRV_PCM_RATE_192000,
1040 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1041 },
1042 .ops = &vc4_hdmi_audio_dai_ops,
1043};
1044
1045static const struct snd_dmaengine_pcm_config pcm_conf = {
1046 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1047 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1048};
1049
1050static int vc4_hdmi_audio_init(struct vc4_hdmi *hdmi)
1051{
1052 struct snd_soc_dai_link *dai_link = &hdmi->audio.link;
1053 struct snd_soc_card *card = &hdmi->audio.card;
1054 struct device *dev = &hdmi->pdev->dev;
1055 const __be32 *addr;
1056 int ret;
1057
1058 if (!of_find_property(dev->of_node, "dmas", NULL)) {
1059 dev_warn(dev,
1060 "'dmas' DT property is missing, no HDMI audio\n");
1061 return 0;
1062 }
1063
1064 /*
1065 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1066 * the bus address specified in the DT, because the physical address
1067 * (the one returned by platform_get_resource()) is not appropriate
1068 * for DMA transfers.
1069 * This VC/MMU should probably be exposed to avoid this kind of hacks.
1070 */
1071 addr = of_get_address(dev->of_node, 1, NULL, NULL);
1072 hdmi->audio.dma_data.addr = be32_to_cpup(addr) + VC4_HD_MAI_DATA;
1073 hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1074 hdmi->audio.dma_data.maxburst = 2;
1075
1076 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1077 if (ret) {
1078 dev_err(dev, "Could not register PCM component: %d\n", ret);
1079 return ret;
1080 }
1081
1082 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1083 &vc4_hdmi_audio_cpu_dai_drv, 1);
1084 if (ret) {
1085 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1086 return ret;
1087 }
1088
1089 /* register component and codec dai */
1090 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv,
1091 &vc4_hdmi_audio_codec_dai_drv, 1);
1092 if (ret) {
1093 dev_err(dev, "Could not register component: %d\n", ret);
1094 return ret;
1095 }
1096
1097 dai_link->cpus = &hdmi->audio.cpu;
1098 dai_link->codecs = &hdmi->audio.codec;
1099 dai_link->platforms = &hdmi->audio.platform;
1100
1101 dai_link->num_cpus = 1;
1102 dai_link->num_codecs = 1;
1103 dai_link->num_platforms = 1;
1104
1105 dai_link->name = "MAI";
1106 dai_link->stream_name = "MAI PCM";
1107 dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name;
1108 dai_link->cpus->dai_name = dev_name(dev);
1109 dai_link->codecs->name = dev_name(dev);
1110 dai_link->platforms->name = dev_name(dev);
1111
1112 card->dai_link = dai_link;
1113 card->num_links = 1;
1114 card->name = "vc4-hdmi";
1115 card->dev = dev;
1116
1117 /*
1118 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1119 * stores a pointer to the snd card object in dev->driver_data. This
1120 * means we cannot use it for something else. The hdmi back-pointer is
1121 * now stored in card->drvdata and should be retrieved with
1122 * snd_soc_card_get_drvdata() if needed.
1123 */
1124 snd_soc_card_set_drvdata(card, hdmi);
1125 ret = devm_snd_soc_register_card(dev, card);
1126 if (ret)
1127 dev_err(dev, "Could not register sound card: %d\n", ret);
1128
1129 return ret;
1130
1131}
1132
1133#ifdef CONFIG_DRM_VC4_HDMI_CEC
1134static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1135{
1136 struct vc4_dev *vc4 = priv;
1137 struct vc4_hdmi *hdmi = vc4->hdmi;
1138
1139 if (hdmi->cec_irq_was_rx) {
1140 if (hdmi->cec_rx_msg.len)
1141 cec_received_msg(hdmi->cec_adap, &hdmi->cec_rx_msg);
1142 } else if (hdmi->cec_tx_ok) {
1143 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_OK,
1144 0, 0, 0, 0);
1145 } else {
1146 /*
1147 * This CEC implementation makes 1 retry, so if we
1148 * get a NACK, then that means it made 2 attempts.
1149 */
1150 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_NACK,
1151 0, 2, 0, 0);
1152 }
1153 return IRQ_HANDLED;
1154}
1155
1156static void vc4_cec_read_msg(struct vc4_dev *vc4, u32 cntrl1)
1157{
1158 struct cec_msg *msg = &vc4->hdmi->cec_rx_msg;
1159 unsigned int i;
1160
1161 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1162 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1163 for (i = 0; i < msg->len; i += 4) {
1164 u32 val = HDMI_READ(VC4_HDMI_CEC_RX_DATA_1 + i);
1165
1166 msg->msg[i] = val & 0xff;
1167 msg->msg[i + 1] = (val >> 8) & 0xff;
1168 msg->msg[i + 2] = (val >> 16) & 0xff;
1169 msg->msg[i + 3] = (val >> 24) & 0xff;
1170 }
1171}
1172
1173static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1174{
1175 struct vc4_dev *vc4 = priv;
1176 struct vc4_hdmi *hdmi = vc4->hdmi;
1177 u32 stat = HDMI_READ(VC4_HDMI_CPU_STATUS);
1178 u32 cntrl1, cntrl5;
1179
1180 if (!(stat & VC4_HDMI_CPU_CEC))
1181 return IRQ_NONE;
1182 hdmi->cec_rx_msg.len = 0;
1183 cntrl1 = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1184 cntrl5 = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
1185 hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1186 if (hdmi->cec_irq_was_rx) {
1187 vc4_cec_read_msg(vc4, cntrl1);
1188 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1189 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
1190 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1191 } else {
1192 hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1193 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1194 }
1195 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
1196 HDMI_WRITE(VC4_HDMI_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1197
1198 return IRQ_WAKE_THREAD;
1199}
1200
1201static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1202{
1203 struct vc4_dev *vc4 = cec_get_drvdata(adap);
1204 /* clock period in microseconds */
1205 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1206 u32 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
1207
1208 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1209 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1210 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1211 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1212 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1213
1214 if (enable) {
1215 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |
1216 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1217 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val);
1218 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_2,
1219 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1220 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1221 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1222 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1223 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1224 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_3,
1225 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1226 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1227 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1228 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1229 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_4,
1230 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1231 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1232 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1233 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1234
1235 HDMI_WRITE(VC4_HDMI_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1236 } else {
1237 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1238 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |
1239 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1240 }
1241 return 0;
1242}
1243
1244static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1245{
1246 struct vc4_dev *vc4 = cec_get_drvdata(adap);
1247
1248 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1,
1249 (HDMI_READ(VC4_HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1250 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1251 return 0;
1252}
1253
1254static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1255 u32 signal_free_time, struct cec_msg *msg)
1256{
1257 struct vc4_dev *vc4 = cec_get_drvdata(adap);
1258 u32 val;
1259 unsigned int i;
1260
1261 for (i = 0; i < msg->len; i += 4)
1262 HDMI_WRITE(VC4_HDMI_CEC_TX_DATA_1 + i,
1263 (msg->msg[i]) |
1264 (msg->msg[i + 1] << 8) |
1265 (msg->msg[i + 2] << 16) |
1266 (msg->msg[i + 3] << 24));
1267
1268 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1269 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1270 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);
1271 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1272 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1273 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1274
1275 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);
1276 return 0;
1277}
1278
1279static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1280 .adap_enable = vc4_hdmi_cec_adap_enable,
1281 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1282 .adap_transmit = vc4_hdmi_cec_adap_transmit,
1283};
1284#endif
1285
1286static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
1287{
1288 struct platform_device *pdev = to_platform_device(dev);
1289 struct drm_device *drm = dev_get_drvdata(master);
1290 struct vc4_dev *vc4 = drm->dev_private;
1291 struct vc4_hdmi *hdmi;
1292 struct vc4_hdmi_encoder *vc4_hdmi_encoder;
1293 struct device_node *ddc_node;
1294 u32 value;
1295 int ret;
1296
1297 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1298 if (!hdmi)
1299 return -ENOMEM;
1300
1301 vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder),
1302 GFP_KERNEL);
1303 if (!vc4_hdmi_encoder)
1304 return -ENOMEM;
1305 vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI;
1306 hdmi->encoder = &vc4_hdmi_encoder->base.base;
1307
1308 hdmi->pdev = pdev;
1309 hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1310 if (IS_ERR(hdmi->hdmicore_regs))
1311 return PTR_ERR(hdmi->hdmicore_regs);
1312
1313 hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1314 if (IS_ERR(hdmi->hd_regs))
1315 return PTR_ERR(hdmi->hd_regs);
1316
1317 hdmi->hdmi_regset.base = hdmi->hdmicore_regs;
1318 hdmi->hdmi_regset.regs = hdmi_regs;
1319 hdmi->hdmi_regset.nregs = ARRAY_SIZE(hdmi_regs);
1320 hdmi->hd_regset.base = hdmi->hd_regs;
1321 hdmi->hd_regset.regs = hd_regs;
1322 hdmi->hd_regset.nregs = ARRAY_SIZE(hd_regs);
1323
1324 hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1325 if (IS_ERR(hdmi->pixel_clock)) {
1326 DRM_ERROR("Failed to get pixel clock\n");
1327 return PTR_ERR(hdmi->pixel_clock);
1328 }
1329 hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1330 if (IS_ERR(hdmi->hsm_clock)) {
1331 DRM_ERROR("Failed to get HDMI state machine clock\n");
1332 return PTR_ERR(hdmi->hsm_clock);
1333 }
1334
1335 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
1336 if (!ddc_node) {
1337 DRM_ERROR("Failed to find ddc node in device tree\n");
1338 return -ENODEV;
1339 }
1340
1341 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1342 of_node_put(ddc_node);
1343 if (!hdmi->ddc) {
1344 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
1345 return -EPROBE_DEFER;
1346 }
1347
1348 /* This is the rate that is set by the firmware. The number
1349 * needs to be a bit higher than the pixel clock rate
1350 * (generally 148.5Mhz).
1351 */
1352 ret = clk_set_rate(hdmi->hsm_clock, HSM_CLOCK_FREQ);
1353 if (ret) {
1354 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1355 goto err_put_i2c;
1356 }
1357
1358 ret = clk_prepare_enable(hdmi->hsm_clock);
1359 if (ret) {
1360 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
1361 ret);
1362 goto err_put_i2c;
1363 }
1364
1365 /* Only use the GPIO HPD pin if present in the DT, otherwise
1366 * we'll use the HDMI core's register.
1367 */
1368 if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
1369 enum of_gpio_flags hpd_gpio_flags;
1370
1371 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
1372 "hpd-gpios", 0,
1373 &hpd_gpio_flags);
1374 if (hdmi->hpd_gpio < 0) {
1375 ret = hdmi->hpd_gpio;
1376 goto err_unprepare_hsm;
1377 }
1378
1379 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
1380 }
1381
1382 vc4->hdmi = hdmi;
1383
1384 /* HDMI core must be enabled. */
1385 if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
1386 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
1387 udelay(1);
1388 HD_WRITE(VC4_HD_M_CTL, 0);
1389
1390 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);
1391 }
1392 pm_runtime_enable(dev);
1393
1394 drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,
1395 DRM_MODE_ENCODER_TMDS, NULL);
1396 drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs);
1397
1398 hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder);
1399 if (IS_ERR(hdmi->connector)) {
1400 ret = PTR_ERR(hdmi->connector);
1401 goto err_destroy_encoder;
1402 }
1403#ifdef CONFIG_DRM_VC4_HDMI_CEC
1404 hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1405 vc4, "vc4",
1406 CEC_CAP_TRANSMIT |
1407 CEC_CAP_LOG_ADDRS |
1408 CEC_CAP_PASSTHROUGH |
1409 CEC_CAP_RC, 1);
1410 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
1411 if (ret < 0)
1412 goto err_destroy_conn;
1413 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, 0xffffffff);
1414 value = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
1415 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
1416 /*
1417 * Set the logical address to Unregistered and set the clock
1418 * divider: the hsm_clock rate and this divider setting will
1419 * give a 40 kHz CEC clock.
1420 */
1421 value |= VC4_HDMI_CEC_ADDR_MASK |
1422 (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
1423 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, value);
1424 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
1425 vc4_cec_irq_handler,
1426 vc4_cec_irq_handler_thread, 0,
1427 "vc4 hdmi cec", vc4);
1428 if (ret)
1429 goto err_delete_cec_adap;
1430 ret = cec_register_adapter(hdmi->cec_adap, dev);
1431 if (ret < 0)
1432 goto err_delete_cec_adap;
1433#endif
1434
1435 ret = vc4_hdmi_audio_init(hdmi);
1436 if (ret)
1437 goto err_destroy_encoder;
1438
1439 vc4_debugfs_add_file(drm, "hdmi_regs", vc4_hdmi_debugfs_regs, hdmi);
1440
1441 return 0;
1442
1443#ifdef CONFIG_DRM_VC4_HDMI_CEC
1444err_delete_cec_adap:
1445 cec_delete_adapter(hdmi->cec_adap);
1446err_destroy_conn:
1447 vc4_hdmi_connector_destroy(hdmi->connector);
1448#endif
1449err_destroy_encoder:
1450 vc4_hdmi_encoder_destroy(hdmi->encoder);
1451err_unprepare_hsm:
1452 clk_disable_unprepare(hdmi->hsm_clock);
1453 pm_runtime_disable(dev);
1454err_put_i2c:
1455 put_device(&hdmi->ddc->dev);
1456
1457 return ret;
1458}
1459
1460static void vc4_hdmi_unbind(struct device *dev, struct device *master,
1461 void *data)
1462{
1463 struct drm_device *drm = dev_get_drvdata(master);
1464 struct vc4_dev *vc4 = drm->dev_private;
1465 struct vc4_hdmi *hdmi = vc4->hdmi;
1466
1467 cec_unregister_adapter(hdmi->cec_adap);
1468 vc4_hdmi_connector_destroy(hdmi->connector);
1469 vc4_hdmi_encoder_destroy(hdmi->encoder);
1470
1471 clk_disable_unprepare(hdmi->hsm_clock);
1472 pm_runtime_disable(dev);
1473
1474 put_device(&hdmi->ddc->dev);
1475
1476 vc4->hdmi = NULL;
1477}
1478
1479static const struct component_ops vc4_hdmi_ops = {
1480 .bind = vc4_hdmi_bind,
1481 .unbind = vc4_hdmi_unbind,
1482};
1483
1484static int vc4_hdmi_dev_probe(struct platform_device *pdev)
1485{
1486 return component_add(&pdev->dev, &vc4_hdmi_ops);
1487}
1488
1489static int vc4_hdmi_dev_remove(struct platform_device *pdev)
1490{
1491 component_del(&pdev->dev, &vc4_hdmi_ops);
1492 return 0;
1493}
1494
1495static const struct of_device_id vc4_hdmi_dt_match[] = {
1496 { .compatible = "brcm,bcm2835-hdmi" },
1497 {}
1498};
1499
1500struct platform_driver vc4_hdmi_driver = {
1501 .probe = vc4_hdmi_dev_probe,
1502 .remove = vc4_hdmi_dev_remove,
1503 .driver = {
1504 .name = "vc4_hdmi",
1505 .of_match_table = vc4_hdmi_dt_match,
1506 },
1507};