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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
7 */
8
9/**
10 * DOC: VC4 Falcon HDMI module
11 *
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
15 *
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
18 *
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
23 * blank regions.
24 *
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
29 *
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
32 */
33
34#include <drm/display/drm_hdmi_helper.h>
35#include <drm/display/drm_hdmi_state_helper.h>
36#include <drm/display/drm_scdc_helper.h>
37#include <drm/drm_atomic_helper.h>
38#include <drm/drm_drv.h>
39#include <drm/drm_edid.h>
40#include <drm/drm_probe_helper.h>
41#include <drm/drm_simple_kms_helper.h>
42#include <linux/clk.h>
43#include <linux/component.h>
44#include <linux/gpio/consumer.h>
45#include <linux/i2c.h>
46#include <linux/of.h>
47#include <linux/of_address.h>
48#include <linux/pm_runtime.h>
49#include <linux/rational.h>
50#include <linux/reset.h>
51#include <sound/dmaengine_pcm.h>
52#include <sound/hdmi-codec.h>
53#include <sound/pcm_drm_eld.h>
54#include <sound/pcm_params.h>
55#include <sound/soc.h>
56#include "media/cec.h"
57#include "vc4_drv.h"
58#include "vc4_hdmi.h"
59#include "vc4_hdmi_regs.h"
60#include "vc4_regs.h"
61
62#define VC5_HDMI_HORZA_HFP_SHIFT 16
63#define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
64#define VC5_HDMI_HORZA_VPOS BIT(15)
65#define VC5_HDMI_HORZA_HPOS BIT(14)
66#define VC5_HDMI_HORZA_HAP_SHIFT 0
67#define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
68
69#define VC5_HDMI_HORZB_HBP_SHIFT 16
70#define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
71#define VC5_HDMI_HORZB_HSP_SHIFT 0
72#define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
73
74#define VC5_HDMI_VERTA_VSP_SHIFT 24
75#define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
76#define VC5_HDMI_VERTA_VFP_SHIFT 16
77#define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
78#define VC5_HDMI_VERTA_VAL_SHIFT 0
79#define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
80
81#define VC5_HDMI_VERTB_VSPO_SHIFT 16
82#define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
83
84#define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
85#define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
86#define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
87#define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
88
89#define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
90
91#define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
92#define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
93
94#define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0
95#define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0)
96
97#define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31)
98
99#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8
100#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)
101
102#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK VC4_MASK(7, 0)
103#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE BIT(0)
104#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE BIT(4)
105
106# define VC4_HD_M_SW_RST BIT(2)
107# define VC4_HD_M_ENABLE BIT(0)
108
109#define HSM_MIN_CLOCK_FREQ 120000000
110#define CEC_CLOCK_FREQ 40000
111
112#define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
113
114static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi)
115{
116 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
117
118 lockdep_assert_held(&vc4_hdmi->mutex);
119
120 if (!display->is_hdmi)
121 return false;
122
123 if (!display->hdmi.scdc.supported ||
124 !display->hdmi.scdc.scrambling.supported)
125 return false;
126
127 return true;
128}
129
130static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
131 unsigned int bpc,
132 enum hdmi_colorspace fmt)
133{
134 unsigned long long clock = drm_hdmi_compute_mode_clock(mode, bpc, fmt);
135
136 return clock > HDMI_14_MAX_TMDS_CLK;
137}
138
139static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
140{
141 struct drm_debugfs_entry *entry = m->private;
142 struct vc4_hdmi *vc4_hdmi = entry->file.data;
143 struct drm_device *drm = vc4_hdmi->connector.dev;
144 struct drm_printer p = drm_seq_file_printer(m);
145 int idx;
146
147 if (!drm_dev_enter(drm, &idx))
148 return -ENODEV;
149
150 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
151
152 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
153 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
154 drm_print_regset32(&p, &vc4_hdmi->cec_regset);
155 drm_print_regset32(&p, &vc4_hdmi->csc_regset);
156 drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
157 drm_print_regset32(&p, &vc4_hdmi->phy_regset);
158 drm_print_regset32(&p, &vc4_hdmi->ram_regset);
159 drm_print_regset32(&p, &vc4_hdmi->rm_regset);
160
161 pm_runtime_put(&vc4_hdmi->pdev->dev);
162
163 drm_dev_exit(idx);
164
165 return 0;
166}
167
168static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
169{
170 struct drm_device *drm = vc4_hdmi->connector.dev;
171 unsigned long flags;
172 int idx;
173
174 /*
175 * We can be called by our bind callback, when the
176 * connector->dev pointer might not be initialised yet.
177 */
178 if (drm && !drm_dev_enter(drm, &idx))
179 return;
180
181 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
182
183 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
184 udelay(1);
185 HDMI_WRITE(HDMI_M_CTL, 0);
186
187 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
188
189 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
190 VC4_HDMI_SW_RESET_HDMI |
191 VC4_HDMI_SW_RESET_FORMAT_DETECT);
192
193 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
194
195 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
196
197 if (drm)
198 drm_dev_exit(idx);
199}
200
201static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
202{
203 struct drm_device *drm = vc4_hdmi->connector.dev;
204 unsigned long flags;
205 int idx;
206
207 /*
208 * We can be called by our bind callback, when the
209 * connector->dev pointer might not be initialised yet.
210 */
211 if (drm && !drm_dev_enter(drm, &idx))
212 return;
213
214 reset_control_reset(vc4_hdmi->reset);
215
216 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
217
218 HDMI_WRITE(HDMI_DVP_CTL, 0);
219
220 HDMI_WRITE(HDMI_CLOCK_STOP,
221 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
222
223 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
224
225 if (drm)
226 drm_dev_exit(idx);
227}
228
229#ifdef CONFIG_DRM_VC4_HDMI_CEC
230static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
231{
232 struct drm_device *drm = vc4_hdmi->connector.dev;
233 unsigned long cec_rate;
234 unsigned long flags;
235 u16 clk_cnt;
236 u32 value;
237 int idx;
238
239 /*
240 * This function is called by our runtime_resume implementation
241 * and thus at bind time, when we haven't registered our
242 * connector yet and thus don't have a pointer to the DRM
243 * device.
244 */
245 if (drm && !drm_dev_enter(drm, &idx))
246 return;
247
248 cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
249
250 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
251
252 value = HDMI_READ(HDMI_CEC_CNTRL_1);
253 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
254
255 /*
256 * Set the clock divider: the hsm_clock rate and this divider
257 * setting will give a 40 kHz CEC clock.
258 */
259 clk_cnt = cec_rate / CEC_CLOCK_FREQ;
260 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
261 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
262
263 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
264
265 if (drm)
266 drm_dev_exit(idx);
267}
268#else
269static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
270#endif
271
272static int reset_pipe(struct drm_crtc *crtc,
273 struct drm_modeset_acquire_ctx *ctx)
274{
275 struct drm_atomic_state *state;
276 struct drm_crtc_state *crtc_state;
277 int ret;
278
279 state = drm_atomic_state_alloc(crtc->dev);
280 if (!state)
281 return -ENOMEM;
282
283 state->acquire_ctx = ctx;
284
285 crtc_state = drm_atomic_get_crtc_state(state, crtc);
286 if (IS_ERR(crtc_state)) {
287 ret = PTR_ERR(crtc_state);
288 goto out;
289 }
290
291 crtc_state->connectors_changed = true;
292
293 ret = drm_atomic_commit(state);
294out:
295 drm_atomic_state_put(state);
296
297 return ret;
298}
299
300static int vc4_hdmi_reset_link(struct drm_connector *connector,
301 struct drm_modeset_acquire_ctx *ctx)
302{
303 struct drm_device *drm;
304 struct vc4_hdmi *vc4_hdmi;
305 struct drm_connector_state *conn_state;
306 struct drm_crtc_state *crtc_state;
307 struct drm_crtc *crtc;
308 bool scrambling_needed;
309 u8 config;
310 int ret;
311
312 if (!connector)
313 return 0;
314
315 drm = connector->dev;
316 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx);
317 if (ret)
318 return ret;
319
320 conn_state = connector->state;
321 crtc = conn_state->crtc;
322 if (!crtc)
323 return 0;
324
325 ret = drm_modeset_lock(&crtc->mutex, ctx);
326 if (ret)
327 return ret;
328
329 crtc_state = crtc->state;
330 if (!crtc_state->active)
331 return 0;
332
333 vc4_hdmi = connector_to_vc4_hdmi(connector);
334 mutex_lock(&vc4_hdmi->mutex);
335
336 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) {
337 mutex_unlock(&vc4_hdmi->mutex);
338 return 0;
339 }
340
341 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode,
342 vc4_hdmi->output_bpc,
343 vc4_hdmi->output_format);
344 if (!scrambling_needed) {
345 mutex_unlock(&vc4_hdmi->mutex);
346 return 0;
347 }
348
349 if (conn_state->commit &&
350 !try_wait_for_completion(&conn_state->commit->hw_done)) {
351 mutex_unlock(&vc4_hdmi->mutex);
352 return 0;
353 }
354
355 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
356 if (ret < 0) {
357 drm_err(drm, "Failed to read TMDS config: %d\n", ret);
358 mutex_unlock(&vc4_hdmi->mutex);
359 return 0;
360 }
361
362 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) {
363 mutex_unlock(&vc4_hdmi->mutex);
364 return 0;
365 }
366
367 mutex_unlock(&vc4_hdmi->mutex);
368
369 /*
370 * HDMI 2.0 says that one should not send scrambled data
371 * prior to configuring the sink scrambling, and that
372 * TMDS clock/data transmission should be suspended when
373 * changing the TMDS clock rate in the sink. So let's
374 * just do a full modeset here, even though some sinks
375 * would be perfectly happy if were to just reconfigure
376 * the SCDC settings on the fly.
377 */
378 return reset_pipe(crtc, ctx);
379}
380
381static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi,
382 struct drm_modeset_acquire_ctx *ctx,
383 enum drm_connector_status status)
384{
385 struct drm_connector *connector = &vc4_hdmi->connector;
386 const struct drm_edid *drm_edid;
387 int ret;
388
389 /*
390 * NOTE: This function should really be called with vc4_hdmi->mutex
391 * held, but doing so results in reentrancy issues since
392 * cec_s_phys_addr() might call .adap_enable, which leads to that
393 * funtion being called with our mutex held.
394 *
395 * A similar situation occurs with vc4_hdmi_reset_link() that
396 * will call into our KMS hooks if the scrambling was enabled.
397 *
398 * Concurrency isn't an issue at the moment since we don't share
399 * any state with any of the other frameworks so we can ignore
400 * the lock for now.
401 */
402
403 if (status == connector_status_disconnected) {
404 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
405 return;
406 }
407
408 drm_edid = drm_edid_read_ddc(connector, vc4_hdmi->ddc);
409
410 drm_edid_connector_update(connector, drm_edid);
411 cec_s_phys_addr(vc4_hdmi->cec_adap,
412 connector->display_info.source_physical_address, false);
413
414 if (!drm_edid)
415 return;
416
417 drm_edid_free(drm_edid);
418
419 for (;;) {
420 ret = vc4_hdmi_reset_link(connector, ctx);
421 if (ret == -EDEADLK) {
422 drm_modeset_backoff(ctx);
423 continue;
424 }
425
426 break;
427 }
428}
429
430static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector,
431 struct drm_modeset_acquire_ctx *ctx,
432 bool force)
433{
434 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
435 enum drm_connector_status status = connector_status_disconnected;
436 int ret;
437
438 /*
439 * NOTE: This function should really take vc4_hdmi->mutex, but
440 * doing so results in reentrancy issues since
441 * vc4_hdmi_handle_hotplug() can call into other functions that
442 * would take the mutex while it's held here.
443 *
444 * Concurrency isn't an issue at the moment since we don't share
445 * any state with any of the other frameworks so we can ignore
446 * the lock for now.
447 */
448
449 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
450 if (ret) {
451 drm_err_once(connector->dev, "Failed to retain HDMI power domain: %d\n",
452 ret);
453 return connector_status_unknown;
454 }
455
456 if (vc4_hdmi->hpd_gpio) {
457 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
458 status = connector_status_connected;
459 } else {
460 if (vc4_hdmi->variant->hp_detect &&
461 vc4_hdmi->variant->hp_detect(vc4_hdmi))
462 status = connector_status_connected;
463 }
464
465 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status);
466 pm_runtime_put(&vc4_hdmi->pdev->dev);
467
468 return status;
469}
470
471static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
472{
473 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
474 struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
475 const struct drm_edid *drm_edid;
476 int ret = 0;
477
478 /*
479 * NOTE: This function should really take vc4_hdmi->mutex, but doing so
480 * results in reentrancy issues since cec_s_phys_addr() might call
481 * .adap_enable, which leads to that funtion being called with our mutex
482 * held.
483 *
484 * Concurrency isn't an issue at the moment since we don't share
485 * any state with any of the other frameworks so we can ignore
486 * the lock for now.
487 */
488
489 drm_edid = drm_edid_read_ddc(connector, vc4_hdmi->ddc);
490 drm_edid_connector_update(connector, drm_edid);
491 cec_s_phys_addr(vc4_hdmi->cec_adap,
492 connector->display_info.source_physical_address, false);
493 if (!drm_edid)
494 return 0;
495
496 ret = drm_edid_connector_add_modes(connector);
497 drm_edid_free(drm_edid);
498
499 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) {
500 struct drm_device *drm = connector->dev;
501 const struct drm_display_mode *mode;
502
503 list_for_each_entry(mode, &connector->probed_modes, head) {
504 if (vc4_hdmi_mode_needs_scrambling(mode, 8, HDMI_COLORSPACE_RGB)) {
505 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
506 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
507 }
508 }
509 }
510
511 return ret;
512}
513
514static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
515 struct drm_atomic_state *state)
516{
517 struct drm_connector_state *old_state =
518 drm_atomic_get_old_connector_state(state, connector);
519 struct drm_connector_state *new_state =
520 drm_atomic_get_new_connector_state(state, connector);
521 struct drm_crtc *crtc = new_state->crtc;
522
523 if (!crtc)
524 return 0;
525
526 if (old_state->tv.margins.left != new_state->tv.margins.left ||
527 old_state->tv.margins.right != new_state->tv.margins.right ||
528 old_state->tv.margins.top != new_state->tv.margins.top ||
529 old_state->tv.margins.bottom != new_state->tv.margins.bottom) {
530 struct drm_crtc_state *crtc_state;
531 int ret;
532
533 crtc_state = drm_atomic_get_crtc_state(state, crtc);
534 if (IS_ERR(crtc_state))
535 return PTR_ERR(crtc_state);
536
537 /*
538 * Strictly speaking, we should be calling
539 * drm_atomic_helper_check_planes() after our call to
540 * drm_atomic_add_affected_planes(). However, the
541 * connector atomic_check is called as part of
542 * drm_atomic_helper_check_modeset() that already
543 * happens before a call to
544 * drm_atomic_helper_check_planes() in
545 * drm_atomic_helper_check().
546 */
547 ret = drm_atomic_add_affected_planes(state, crtc);
548 if (ret)
549 return ret;
550 }
551
552 if (old_state->colorspace != new_state->colorspace) {
553 struct drm_crtc_state *crtc_state;
554
555 crtc_state = drm_atomic_get_crtc_state(state, crtc);
556 if (IS_ERR(crtc_state))
557 return PTR_ERR(crtc_state);
558
559 crtc_state->mode_changed = true;
560 }
561
562 return drm_atomic_helper_connector_hdmi_check(connector, state);
563}
564
565static void vc4_hdmi_connector_reset(struct drm_connector *connector)
566{
567 drm_atomic_helper_connector_reset(connector);
568 __drm_atomic_helper_connector_hdmi_reset(connector, connector->state);
569 drm_atomic_helper_connector_tv_margins_reset(connector);
570}
571
572static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
573 .fill_modes = drm_helper_probe_single_connector_modes,
574 .reset = vc4_hdmi_connector_reset,
575 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
576 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
577};
578
579static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
580 .detect_ctx = vc4_hdmi_connector_detect_ctx,
581 .get_modes = vc4_hdmi_connector_get_modes,
582 .atomic_check = vc4_hdmi_connector_atomic_check,
583};
584
585static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs;
586
587static int vc4_hdmi_connector_init(struct drm_device *dev,
588 struct vc4_hdmi *vc4_hdmi)
589{
590 struct drm_connector *connector = &vc4_hdmi->connector;
591 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
592 unsigned int max_bpc = 8;
593 int ret;
594
595 if (vc4_hdmi->variant->supports_hdr)
596 max_bpc = 12;
597
598 ret = drmm_connector_hdmi_init(dev, connector,
599 "Broadcom", "Videocore",
600 &vc4_hdmi_connector_funcs,
601 &vc4_hdmi_hdmi_connector_funcs,
602 DRM_MODE_CONNECTOR_HDMIA,
603 vc4_hdmi->ddc,
604 BIT(HDMI_COLORSPACE_RGB) |
605 BIT(HDMI_COLORSPACE_YUV422) |
606 BIT(HDMI_COLORSPACE_YUV444),
607 max_bpc);
608 if (ret)
609 return ret;
610
611 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
612
613 /*
614 * Some of the properties below require access to state, like bpc.
615 * Allocate some default initial connector state with our reset helper.
616 */
617 if (connector->funcs->reset)
618 connector->funcs->reset(connector);
619
620 /* Create and attach TV margin props to this connector. */
621 ret = drm_mode_create_tv_margin_properties(dev);
622 if (ret)
623 return ret;
624
625 ret = drm_mode_create_hdmi_colorspace_property(connector, 0);
626 if (ret)
627 return ret;
628
629 drm_connector_attach_colorspace_property(connector);
630 drm_connector_attach_tv_margin_properties(connector);
631
632 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
633 DRM_CONNECTOR_POLL_DISCONNECT);
634
635 connector->interlace_allowed = 1;
636 connector->doublescan_allowed = 0;
637 connector->stereo_allowed = 1;
638
639 ret = drm_connector_attach_broadcast_rgb_property(connector);
640 if (ret)
641 return ret;
642
643 drm_connector_attach_encoder(connector, encoder);
644
645 return 0;
646}
647
648static int vc4_hdmi_stop_packet(struct vc4_hdmi *vc4_hdmi,
649 enum hdmi_infoframe_type type,
650 bool poll)
651{
652 struct drm_device *drm = vc4_hdmi->connector.dev;
653 u32 packet_id = type - 0x80;
654 unsigned long flags;
655 int ret = 0;
656 int idx;
657
658 if (!drm_dev_enter(drm, &idx))
659 return -ENODEV;
660
661 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
662 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
663 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
664 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
665
666 if (poll) {
667 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
668 BIT(packet_id)), 100);
669 }
670
671 drm_dev_exit(idx);
672 return ret;
673}
674
675static int vc4_hdmi_write_infoframe(struct drm_connector *connector,
676 enum hdmi_infoframe_type type,
677 const u8 *infoframe, size_t len)
678{
679 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
680 struct drm_device *drm = connector->dev;
681 u32 packet_id = type - 0x80;
682 const struct vc4_hdmi_register *ram_packet_start =
683 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
684 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
685 u32 packet_reg_next = ram_packet_start->offset +
686 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
687 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
688 ram_packet_start->reg);
689 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
690 unsigned long flags;
691 ssize_t i;
692 int ret;
693 int idx;
694
695 if (!drm_dev_enter(drm, &idx))
696 return 0;
697
698 if (len > sizeof(buffer)) {
699 ret = -ENOMEM;
700 goto out;
701 }
702
703 memcpy(buffer, infoframe, len);
704
705 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
706 VC4_HDMI_RAM_PACKET_ENABLE),
707 "Packet RAM has to be on to store the packet.");
708
709 ret = vc4_hdmi_stop_packet(vc4_hdmi, type, true);
710 if (ret) {
711 drm_err(drm, "Failed to wait for infoframe to go idle: %d\n", ret);
712 goto out;
713 }
714
715 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
716
717 for (i = 0; i < len; i += 7) {
718 writel(buffer[i + 0] << 0 |
719 buffer[i + 1] << 8 |
720 buffer[i + 2] << 16,
721 base + packet_reg);
722 packet_reg += 4;
723
724 writel(buffer[i + 3] << 0 |
725 buffer[i + 4] << 8 |
726 buffer[i + 5] << 16 |
727 buffer[i + 6] << 24,
728 base + packet_reg);
729 packet_reg += 4;
730 }
731
732 /*
733 * clear remainder of packet ram as it's included in the
734 * infoframe and triggers a checksum error on hdmi analyser
735 */
736 for (; packet_reg < packet_reg_next; packet_reg += 4)
737 writel(0, base + packet_reg);
738
739 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
740 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
741
742 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
743
744 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
745 BIT(packet_id)), 100);
746 if (ret)
747 drm_err(drm, "Failed to wait for infoframe to start: %d\n", ret);
748
749out:
750 drm_dev_exit(idx);
751 return ret;
752}
753
754#define SCRAMBLING_POLLING_DELAY_MS 1000
755
756static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
757{
758 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
759 struct drm_connector *connector = &vc4_hdmi->connector;
760 struct drm_device *drm = connector->dev;
761 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
762 unsigned long flags;
763 int idx;
764
765 lockdep_assert_held(&vc4_hdmi->mutex);
766
767 if (!vc4_hdmi_supports_scrambling(vc4_hdmi))
768 return;
769
770 if (!vc4_hdmi_mode_needs_scrambling(mode,
771 vc4_hdmi->output_bpc,
772 vc4_hdmi->output_format))
773 return;
774
775 if (!drm_dev_enter(drm, &idx))
776 return;
777
778 drm_scdc_set_high_tmds_clock_ratio(connector, true);
779 drm_scdc_set_scrambling(connector, true);
780
781 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
782 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
783 VC5_HDMI_SCRAMBLER_CTL_ENABLE);
784 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
785
786 drm_dev_exit(idx);
787
788 vc4_hdmi->scdc_enabled = true;
789
790 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
791 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
792}
793
794static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
795{
796 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
797 struct drm_connector *connector = &vc4_hdmi->connector;
798 struct drm_device *drm = connector->dev;
799 unsigned long flags;
800 int idx;
801
802 lockdep_assert_held(&vc4_hdmi->mutex);
803
804 if (!vc4_hdmi->scdc_enabled)
805 return;
806
807 vc4_hdmi->scdc_enabled = false;
808
809 if (delayed_work_pending(&vc4_hdmi->scrambling_work))
810 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
811
812 if (!drm_dev_enter(drm, &idx))
813 return;
814
815 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
816 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
817 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
818 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
819
820 drm_scdc_set_scrambling(connector, false);
821 drm_scdc_set_high_tmds_clock_ratio(connector, false);
822
823 drm_dev_exit(idx);
824}
825
826static void vc4_hdmi_scrambling_wq(struct work_struct *work)
827{
828 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
829 struct vc4_hdmi,
830 scrambling_work);
831 struct drm_connector *connector = &vc4_hdmi->connector;
832
833 if (drm_scdc_get_scrambling_status(connector))
834 return;
835
836 drm_scdc_set_high_tmds_clock_ratio(connector, true);
837 drm_scdc_set_scrambling(connector, true);
838
839 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
840 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
841}
842
843static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
844 struct drm_atomic_state *state)
845{
846 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
847 struct drm_device *drm = vc4_hdmi->connector.dev;
848 unsigned long flags;
849 int idx;
850
851 mutex_lock(&vc4_hdmi->mutex);
852
853 vc4_hdmi->packet_ram_enabled = false;
854
855 if (!drm_dev_enter(drm, &idx))
856 goto out;
857
858 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
859
860 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
861
862 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
863
864 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
865
866 mdelay(1);
867
868 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
869 HDMI_WRITE(HDMI_VID_CTL,
870 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
871 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
872
873 vc4_hdmi_disable_scrambling(encoder);
874
875 drm_dev_exit(idx);
876
877out:
878 mutex_unlock(&vc4_hdmi->mutex);
879}
880
881static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
882 struct drm_atomic_state *state)
883{
884 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
885 struct drm_device *drm = vc4_hdmi->connector.dev;
886 unsigned long flags;
887 int ret;
888 int idx;
889
890 mutex_lock(&vc4_hdmi->mutex);
891
892 if (!drm_dev_enter(drm, &idx))
893 goto out;
894
895 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
896 HDMI_WRITE(HDMI_VID_CTL,
897 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
898 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
899
900 if (vc4_hdmi->variant->phy_disable)
901 vc4_hdmi->variant->phy_disable(vc4_hdmi);
902
903 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
904 clk_disable_unprepare(vc4_hdmi->pixel_clock);
905
906 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
907 if (ret < 0)
908 drm_err(drm, "Failed to release power domain: %d\n", ret);
909
910 drm_dev_exit(idx);
911
912out:
913 mutex_unlock(&vc4_hdmi->mutex);
914}
915
916static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
917 struct drm_connector_state *state,
918 const struct drm_display_mode *mode)
919{
920 struct drm_device *drm = vc4_hdmi->connector.dev;
921 unsigned long flags;
922 u32 csc_ctl;
923 int idx;
924
925 if (!drm_dev_enter(drm, &idx))
926 return;
927
928 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
929
930 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
931 VC4_HD_CSC_CTL_ORDER);
932
933 if (state->hdmi.is_limited_range) {
934 /* CEA VICs other than #1 requre limited range RGB
935 * output unless overridden by an AVI infoframe.
936 * Apply a colorspace conversion to squash 0-255 down
937 * to 16-235. The matrix here is:
938 *
939 * [ 0 0 0.8594 16]
940 * [ 0 0.8594 0 16]
941 * [ 0.8594 0 0 16]
942 * [ 0 0 0 1]
943 */
944 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
945 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
946 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
947 VC4_HD_CSC_CTL_MODE);
948
949 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
950 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
951 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
952 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
953 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
954 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
955 }
956
957 /* The RGB order applies even when CSC is disabled. */
958 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
959
960 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
961
962 drm_dev_exit(idx);
963}
964
965/*
966 * Matrices for (internal) RGB to RGB output.
967 *
968 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
969 */
970static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = {
971 {
972 /*
973 * Full range - unity
974 *
975 * [ 1 0 0 0]
976 * [ 0 1 0 0]
977 * [ 0 0 1 0]
978 */
979 { 0x2000, 0x0000, 0x0000, 0x0000 },
980 { 0x0000, 0x2000, 0x0000, 0x0000 },
981 { 0x0000, 0x0000, 0x2000, 0x0000 },
982 },
983 {
984 /*
985 * Limited range
986 *
987 * CEA VICs other than #1 require limited range RGB
988 * output unless overridden by an AVI infoframe. Apply a
989 * colorspace conversion to squash 0-255 down to 16-235.
990 * The matrix here is:
991 *
992 * [ 0.8594 0 0 16]
993 * [ 0 0.8594 0 16]
994 * [ 0 0 0.8594 16]
995 */
996 { 0x1b80, 0x0000, 0x0000, 0x0400 },
997 { 0x0000, 0x1b80, 0x0000, 0x0400 },
998 { 0x0000, 0x0000, 0x1b80, 0x0400 },
999 },
1000};
1001
1002/*
1003 * Conversion between Full Range RGB and YUV using the BT.601 Colorspace
1004 *
1005 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1006 */
1007static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = {
1008 {
1009 /*
1010 * Full Range
1011 *
1012 * [ 0.299000 0.587000 0.114000 0 ]
1013 * [ -0.168736 -0.331264 0.500000 128 ]
1014 * [ 0.500000 -0.418688 -0.081312 128 ]
1015 */
1016 { 0x0991, 0x12c9, 0x03a6, 0x0000 },
1017 { 0xfa9b, 0xf567, 0x1000, 0x2000 },
1018 { 0x1000, 0xf29b, 0xfd67, 0x2000 },
1019 },
1020 {
1021 /* Limited Range
1022 *
1023 * [ 0.255785 0.502160 0.097523 16 ]
1024 * [ -0.147644 -0.289856 0.437500 128 ]
1025 * [ 0.437500 -0.366352 -0.071148 128 ]
1026 */
1027 { 0x082f, 0x1012, 0x031f, 0x0400 },
1028 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1029 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1030 },
1031};
1032
1033/*
1034 * Conversion between Full Range RGB and YUV using the BT.709 Colorspace
1035 *
1036 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1037 */
1038static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = {
1039 {
1040 /*
1041 * Full Range
1042 *
1043 * [ 0.212600 0.715200 0.072200 0 ]
1044 * [ -0.114572 -0.385428 0.500000 128 ]
1045 * [ 0.500000 -0.454153 -0.045847 128 ]
1046 */
1047 { 0x06ce, 0x16e3, 0x024f, 0x0000 },
1048 { 0xfc56, 0xf3ac, 0x1000, 0x2000 },
1049 { 0x1000, 0xf179, 0xfe89, 0x2000 },
1050 },
1051 {
1052 /*
1053 * Limited Range
1054 *
1055 * [ 0.181906 0.611804 0.061758 16 ]
1056 * [ -0.100268 -0.337232 0.437500 128 ]
1057 * [ 0.437500 -0.397386 -0.040114 128 ]
1058 */
1059 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1060 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1061 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1062 },
1063};
1064
1065/*
1066 * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace
1067 *
1068 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1069 */
1070static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = {
1071 {
1072 /*
1073 * Full Range
1074 *
1075 * [ 0.262700 0.678000 0.059300 0 ]
1076 * [ -0.139630 -0.360370 0.500000 128 ]
1077 * [ 0.500000 -0.459786 -0.040214 128 ]
1078 */
1079 { 0x0868, 0x15b2, 0x01e6, 0x0000 },
1080 { 0xfb89, 0xf479, 0x1000, 0x2000 },
1081 { 0x1000, 0xf14a, 0xfeb8, 0x2000 },
1082 },
1083 {
1084 /* Limited Range
1085 *
1086 * [ 0.224732 0.580008 0.050729 16 ]
1087 * [ -0.122176 -0.315324 0.437500 128 ]
1088 * [ 0.437500 -0.402312 -0.035188 128 ]
1089 */
1090 { 0x082f, 0x1012, 0x031f, 0x0400 },
1091 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1092 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1093 },
1094};
1095
1096static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
1097 const u16 coeffs[3][4])
1098{
1099 lockdep_assert_held(&vc4_hdmi->hw_lock);
1100
1101 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
1102 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
1103 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
1104 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
1105 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
1106 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
1107}
1108
1109static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi,
1110 const u16 coeffs[3][4])
1111{
1112 lockdep_assert_held(&vc4_hdmi->hw_lock);
1113
1114 /* YUV444 needs the CSC matrices using the channels in a different order */
1115 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[1][1] << 16) | coeffs[1][0]);
1116 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[1][3] << 16) | coeffs[1][2]);
1117 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[2][1] << 16) | coeffs[2][0]);
1118 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[2][3] << 16) | coeffs[2][2]);
1119 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[0][1] << 16) | coeffs[0][0]);
1120 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[0][3] << 16) | coeffs[0][2]);
1121}
1122
1123static const u16
1124(*vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi *vc4_hdmi, u32 colorspace, bool limited))[4]
1125{
1126 switch (colorspace) {
1127 case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC:
1128 case DRM_MODE_COLORIMETRY_XVYCC_601:
1129 case DRM_MODE_COLORIMETRY_SYCC_601:
1130 case DRM_MODE_COLORIMETRY_OPYCC_601:
1131 case DRM_MODE_COLORIMETRY_BT601_YCC:
1132 return vc5_hdmi_csc_full_rgb_to_yuv_bt601[limited];
1133
1134 default:
1135 case DRM_MODE_COLORIMETRY_NO_DATA:
1136 case DRM_MODE_COLORIMETRY_BT709_YCC:
1137 case DRM_MODE_COLORIMETRY_XVYCC_709:
1138 case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED:
1139 case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT:
1140 return vc5_hdmi_csc_full_rgb_to_yuv_bt709[limited];
1141
1142 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1143 case DRM_MODE_COLORIMETRY_BT2020_YCC:
1144 case DRM_MODE_COLORIMETRY_BT2020_RGB:
1145 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1146 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1147 return vc5_hdmi_csc_full_rgb_to_yuv_bt2020[limited];
1148 }
1149}
1150
1151static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1152 struct drm_connector_state *state,
1153 const struct drm_display_mode *mode)
1154{
1155 struct drm_device *drm = vc4_hdmi->connector.dev;
1156 unsigned int lim_range = state->hdmi.is_limited_range ? 1 : 0;
1157 unsigned long flags;
1158 const u16 (*csc)[4];
1159 u32 if_cfg = 0;
1160 u32 if_xbar = 0x543210;
1161 u32 csc_chan_ctl = 0;
1162 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1163 VC5_MT_CP_CSC_CTL_MODE);
1164 int idx;
1165
1166 if (!drm_dev_enter(drm, &idx))
1167 return;
1168
1169 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1170
1171 switch (state->hdmi.output_format) {
1172 case HDMI_COLORSPACE_YUV444:
1173 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range);
1174
1175 vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc);
1176 break;
1177
1178 case HDMI_COLORSPACE_YUV422:
1179 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range);
1180
1181 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1182 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
1183 VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
1184 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
1185
1186 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1187 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
1188
1189 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1190 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
1191
1192 vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc);
1193 break;
1194
1195 case HDMI_COLORSPACE_RGB:
1196 if_xbar = 0x354021;
1197
1198 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_rgb[lim_range]);
1199 break;
1200
1201 default:
1202 break;
1203 }
1204
1205 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
1206 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
1207 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
1208 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1209
1210 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1211
1212 drm_dev_exit(idx);
1213}
1214
1215static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1216 struct drm_connector_state *state,
1217 const struct drm_display_mode *mode)
1218{
1219 struct drm_device *drm = vc4_hdmi->connector.dev;
1220 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1221 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1222 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1223 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1224 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1225 VC4_HDMI_VERTA_VSP) |
1226 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1227 VC4_HDMI_VERTA_VFP) |
1228 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1229 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1230 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1231 interlaced,
1232 VC4_HDMI_VERTB_VBP));
1233 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1234 VC4_SET_FIELD(mode->crtc_vtotal -
1235 mode->crtc_vsync_end,
1236 VC4_HDMI_VERTB_VBP));
1237 unsigned long flags;
1238 u32 reg;
1239 int idx;
1240
1241 if (!drm_dev_enter(drm, &idx))
1242 return;
1243
1244 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1245
1246 HDMI_WRITE(HDMI_HORZA,
1247 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1248 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1249 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1250 VC4_HDMI_HORZA_HAP));
1251
1252 HDMI_WRITE(HDMI_HORZB,
1253 VC4_SET_FIELD((mode->htotal -
1254 mode->hsync_end) * pixel_rep,
1255 VC4_HDMI_HORZB_HBP) |
1256 VC4_SET_FIELD((mode->hsync_end -
1257 mode->hsync_start) * pixel_rep,
1258 VC4_HDMI_HORZB_HSP) |
1259 VC4_SET_FIELD((mode->hsync_start -
1260 mode->hdisplay) * pixel_rep,
1261 VC4_HDMI_HORZB_HFP));
1262
1263 HDMI_WRITE(HDMI_VERTA0, verta);
1264 HDMI_WRITE(HDMI_VERTA1, verta);
1265
1266 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1267 HDMI_WRITE(HDMI_VERTB1, vertb);
1268
1269 reg = HDMI_READ(HDMI_MISC_CONTROL);
1270 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1271 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1272 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1273
1274 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1275
1276 drm_dev_exit(idx);
1277}
1278
1279static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1280 struct drm_connector_state *state,
1281 const struct drm_display_mode *mode)
1282{
1283 struct drm_device *drm = vc4_hdmi->connector.dev;
1284 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1285 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1286 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1287 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1288 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1289 VC5_HDMI_VERTA_VSP) |
1290 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1291 VC5_HDMI_VERTA_VFP) |
1292 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1293 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1294 VC5_HDMI_VERTB_VSPO) |
1295 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1296 interlaced,
1297 VC4_HDMI_VERTB_VBP));
1298 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1299 VC4_SET_FIELD(mode->crtc_vtotal -
1300 mode->crtc_vsync_end,
1301 VC4_HDMI_VERTB_VBP));
1302 unsigned long flags;
1303 unsigned char gcp;
1304 u32 reg;
1305 int idx;
1306
1307 if (!drm_dev_enter(drm, &idx))
1308 return;
1309
1310 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1311
1312 HDMI_WRITE(HDMI_HORZA,
1313 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1314 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1315 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1316 VC5_HDMI_HORZA_HAP) |
1317 VC4_SET_FIELD((mode->hsync_start -
1318 mode->hdisplay) * pixel_rep,
1319 VC5_HDMI_HORZA_HFP));
1320
1321 HDMI_WRITE(HDMI_HORZB,
1322 VC4_SET_FIELD((mode->htotal -
1323 mode->hsync_end) * pixel_rep,
1324 VC5_HDMI_HORZB_HBP) |
1325 VC4_SET_FIELD((mode->hsync_end -
1326 mode->hsync_start) * pixel_rep,
1327 VC5_HDMI_HORZB_HSP));
1328
1329 HDMI_WRITE(HDMI_VERTA0, verta);
1330 HDMI_WRITE(HDMI_VERTA1, verta);
1331
1332 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1333 HDMI_WRITE(HDMI_VERTB1, vertb);
1334
1335 switch (state->hdmi.output_bpc) {
1336 case 12:
1337 gcp = 6;
1338 break;
1339 case 10:
1340 gcp = 5;
1341 break;
1342 case 8:
1343 default:
1344 gcp = 0;
1345 break;
1346 }
1347
1348 /*
1349 * YCC422 is always 36-bit and not considered deep colour so
1350 * doesn't signal in GCP.
1351 */
1352 if (state->hdmi.output_format == HDMI_COLORSPACE_YUV422) {
1353 gcp = 0;
1354 }
1355
1356 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1357 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1358 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1359 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1360 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1361 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1362
1363 reg = HDMI_READ(HDMI_GCP_WORD_1);
1364 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1365 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1366 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK;
1367 reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE;
1368 HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1369
1370 reg = HDMI_READ(HDMI_GCP_CONFIG);
1371 reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1372 HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1373
1374 reg = HDMI_READ(HDMI_MISC_CONTROL);
1375 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1376 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1377 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1378
1379 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1380
1381 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1382
1383 drm_dev_exit(idx);
1384}
1385
1386static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1387{
1388 struct drm_device *drm = vc4_hdmi->connector.dev;
1389 unsigned long flags;
1390 u32 drift;
1391 int ret;
1392 int idx;
1393
1394 if (!drm_dev_enter(drm, &idx))
1395 return;
1396
1397 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1398
1399 drift = HDMI_READ(HDMI_FIFO_CTL);
1400 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1401
1402 HDMI_WRITE(HDMI_FIFO_CTL,
1403 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1404 HDMI_WRITE(HDMI_FIFO_CTL,
1405 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1406
1407 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1408
1409 usleep_range(1000, 1100);
1410
1411 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1412
1413 HDMI_WRITE(HDMI_FIFO_CTL,
1414 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1415 HDMI_WRITE(HDMI_FIFO_CTL,
1416 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1417
1418 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1419
1420 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1421 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1422 WARN_ONCE(ret, "Timeout waiting for "
1423 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1424
1425 drm_dev_exit(idx);
1426}
1427
1428static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1429 struct drm_atomic_state *state)
1430{
1431 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1432 struct drm_device *drm = vc4_hdmi->connector.dev;
1433 struct drm_connector *connector = &vc4_hdmi->connector;
1434 struct drm_connector_state *conn_state =
1435 drm_atomic_get_new_connector_state(state, connector);
1436 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1437 unsigned long long tmds_char_rate = conn_state->hdmi.tmds_char_rate;
1438 unsigned long bvb_rate, hsm_rate;
1439 unsigned long flags;
1440 int ret;
1441 int idx;
1442
1443 mutex_lock(&vc4_hdmi->mutex);
1444
1445 if (!drm_dev_enter(drm, &idx))
1446 goto out;
1447
1448 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1449 if (ret < 0) {
1450 drm_err(drm, "Failed to retain power domain: %d\n", ret);
1451 goto err_dev_exit;
1452 }
1453
1454 /*
1455 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1456 * be faster than pixel clock, infinitesimally faster, tested in
1457 * simulation. Otherwise, exact value is unimportant for HDMI
1458 * operation." This conflicts with bcm2835's vc4 documentation, which
1459 * states HSM's clock has to be at least 108% of the pixel clock.
1460 *
1461 * Real life tests reveal that vc4's firmware statement holds up, and
1462 * users are able to use pixel clocks closer to HSM's, namely for
1463 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1464 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1465 * 162MHz.
1466 *
1467 * Additionally, the AXI clock needs to be at least 25% of
1468 * pixel clock, but HSM ends up being the limiting factor.
1469 */
1470 hsm_rate = max_t(unsigned long,
1471 HSM_MIN_CLOCK_FREQ,
1472 div_u64(tmds_char_rate, 100) * 101);
1473 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1474 if (ret) {
1475 drm_err(drm, "Failed to set HSM clock rate: %d\n", ret);
1476 goto err_put_runtime_pm;
1477 }
1478
1479 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1480 if (ret) {
1481 drm_err(drm, "Failed to set pixel clock rate: %d\n", ret);
1482 goto err_put_runtime_pm;
1483 }
1484
1485 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1486 if (ret) {
1487 drm_err(drm, "Failed to turn on pixel clock: %d\n", ret);
1488 goto err_put_runtime_pm;
1489 }
1490
1491
1492 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1493
1494 if (tmds_char_rate > 297000000)
1495 bvb_rate = 300000000;
1496 else if (tmds_char_rate > 148500000)
1497 bvb_rate = 150000000;
1498 else
1499 bvb_rate = 75000000;
1500
1501 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1502 if (ret) {
1503 drm_err(drm, "Failed to set pixel bvb clock rate: %d\n", ret);
1504 goto err_disable_pixel_clock;
1505 }
1506
1507 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1508 if (ret) {
1509 drm_err(drm, "Failed to turn on pixel bvb clock: %d\n", ret);
1510 goto err_disable_pixel_clock;
1511 }
1512
1513 if (vc4_hdmi->variant->phy_init)
1514 vc4_hdmi->variant->phy_init(vc4_hdmi, conn_state);
1515
1516 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1517
1518 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1519 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1520 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1521 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1522
1523 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1524
1525 if (vc4_hdmi->variant->set_timings)
1526 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1527
1528 drm_dev_exit(idx);
1529
1530 mutex_unlock(&vc4_hdmi->mutex);
1531
1532 return;
1533
1534err_disable_pixel_clock:
1535 clk_disable_unprepare(vc4_hdmi->pixel_clock);
1536err_put_runtime_pm:
1537 pm_runtime_put(&vc4_hdmi->pdev->dev);
1538err_dev_exit:
1539 drm_dev_exit(idx);
1540out:
1541 mutex_unlock(&vc4_hdmi->mutex);
1542 return;
1543}
1544
1545static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1546 struct drm_atomic_state *state)
1547{
1548 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1549 struct drm_device *drm = vc4_hdmi->connector.dev;
1550 struct drm_connector *connector = &vc4_hdmi->connector;
1551 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1552 struct drm_connector_state *conn_state =
1553 drm_atomic_get_new_connector_state(state, connector);
1554 unsigned long flags;
1555 int idx;
1556
1557 mutex_lock(&vc4_hdmi->mutex);
1558
1559 if (!drm_dev_enter(drm, &idx))
1560 goto out;
1561
1562 if (vc4_hdmi->variant->csc_setup)
1563 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1564
1565 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1566 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1567 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1568
1569 drm_dev_exit(idx);
1570
1571out:
1572 mutex_unlock(&vc4_hdmi->mutex);
1573}
1574
1575static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1576 struct drm_atomic_state *state)
1577{
1578 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1579 struct drm_connector *connector = &vc4_hdmi->connector;
1580 struct drm_device *drm = connector->dev;
1581 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1582 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1583 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1584 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1585 unsigned long flags;
1586 int ret;
1587 int idx;
1588
1589 mutex_lock(&vc4_hdmi->mutex);
1590
1591 if (!drm_dev_enter(drm, &idx))
1592 goto out;
1593
1594 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1595
1596 HDMI_WRITE(HDMI_VID_CTL,
1597 VC4_HD_VID_CTL_ENABLE |
1598 VC4_HD_VID_CTL_CLRRGB |
1599 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1600 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1601 VC4_HD_VID_CTL_BLANK_INSERT_EN |
1602 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1603 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1604
1605 HDMI_WRITE(HDMI_VID_CTL,
1606 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1607
1608 if (display->is_hdmi) {
1609 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1610 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1611 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1612
1613 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1614
1615 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1616 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1617 WARN_ONCE(ret, "Timeout waiting for "
1618 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1619 } else {
1620 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1621 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1622 ~(VC4_HDMI_RAM_PACKET_ENABLE));
1623 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1624 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1625 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1626
1627 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1628
1629 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1630 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1631 WARN_ONCE(ret, "Timeout waiting for "
1632 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1633 }
1634
1635 if (display->is_hdmi) {
1636 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1637
1638 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1639 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1640
1641 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1642 VC4_HDMI_RAM_PACKET_ENABLE);
1643
1644 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1645 vc4_hdmi->packet_ram_enabled = true;
1646
1647 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state);
1648 }
1649
1650 vc4_hdmi_recenter_fifo(vc4_hdmi);
1651 vc4_hdmi_enable_scrambling(encoder);
1652
1653 drm_dev_exit(idx);
1654
1655out:
1656 mutex_unlock(&vc4_hdmi->mutex);
1657}
1658
1659static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1660 struct drm_crtc_state *crtc_state,
1661 struct drm_connector_state *conn_state)
1662{
1663 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1664
1665 mutex_lock(&vc4_hdmi->mutex);
1666 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1667 &crtc_state->adjusted_mode);
1668 vc4_hdmi->output_bpc = conn_state->hdmi.output_bpc;
1669 vc4_hdmi->output_format = conn_state->hdmi.output_format;
1670 mutex_unlock(&vc4_hdmi->mutex);
1671}
1672
1673static enum drm_mode_status
1674vc4_hdmi_connector_clock_valid(const struct drm_connector *connector,
1675 const struct drm_display_mode *mode,
1676 unsigned long long clock)
1677{
1678 const struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
1679 struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
1680
1681 if (clock > vc4_hdmi->variant->max_pixel_clock)
1682 return MODE_CLOCK_HIGH;
1683
1684 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK)
1685 return MODE_CLOCK_HIGH;
1686
1687 /* 4096x2160@60 is not reliable without overclocking core */
1688 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 &&
1689 mode->hdisplay > 3840 && mode->vdisplay >= 2160 &&
1690 drm_mode_vrefresh(mode) >= 50)
1691 return MODE_CLOCK_HIGH;
1692
1693 return MODE_OK;
1694}
1695
1696static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs = {
1697 .tmds_char_rate_valid = vc4_hdmi_connector_clock_valid,
1698 .write_infoframe = vc4_hdmi_write_infoframe,
1699};
1700
1701#define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
1702#define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
1703
1704static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1705 struct drm_crtc_state *crtc_state,
1706 struct drm_connector_state *conn_state)
1707{
1708 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1709 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1710 unsigned long long tmds_char_rate = mode->clock * 1000;
1711 unsigned long long tmds_bit_rate;
1712
1713 if (vc4_hdmi->variant->unsupported_odd_h_timings) {
1714 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1715 /* Only try to fixup DBLCLK modes to get 480i and 576i
1716 * working.
1717 * A generic solution for all modes with odd horizontal
1718 * timing values seems impossible based on trying to
1719 * solve it for 1366x768 monitors.
1720 */
1721 if ((mode->hsync_start - mode->hdisplay) & 1)
1722 mode->hsync_start--;
1723 if ((mode->hsync_end - mode->hsync_start) & 1)
1724 mode->hsync_end--;
1725 }
1726
1727 /* Now check whether we still have odd values remaining */
1728 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1729 (mode->hsync_end % 2) || (mode->htotal % 2))
1730 return -EINVAL;
1731 }
1732
1733 /*
1734 * The 1440p@60 pixel rate is in the same range than the first
1735 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1736 * bandwidth). Slightly lower the frequency to bring it out of
1737 * the WiFi range.
1738 */
1739 tmds_bit_rate = tmds_char_rate * 10;
1740 if (vc4_hdmi->disable_wifi_frequencies &&
1741 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1742 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1743 mode->clock = 238560;
1744 tmds_char_rate = mode->clock * 1000;
1745 }
1746
1747 return 0;
1748}
1749
1750static enum drm_mode_status
1751vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1752 const struct drm_display_mode *mode)
1753{
1754 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1755 unsigned long long rate;
1756
1757 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1758 !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1759 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1760 (mode->hsync_end % 2) || (mode->htotal % 2)))
1761 return MODE_H_ILLEGAL;
1762
1763 rate = drm_hdmi_compute_mode_clock(mode, 8, HDMI_COLORSPACE_RGB);
1764 return vc4_hdmi_connector_clock_valid(&vc4_hdmi->connector, mode, rate);
1765}
1766
1767static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1768 .atomic_check = vc4_hdmi_encoder_atomic_check,
1769 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
1770 .mode_valid = vc4_hdmi_encoder_mode_valid,
1771};
1772
1773static int vc4_hdmi_late_register(struct drm_encoder *encoder)
1774{
1775 struct drm_device *drm = encoder->dev;
1776 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1777 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1778
1779 drm_debugfs_add_file(drm, variant->debugfs_name,
1780 vc4_hdmi_debugfs_regs, vc4_hdmi);
1781
1782 return 0;
1783}
1784
1785static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
1786 .late_register = vc4_hdmi_late_register,
1787};
1788
1789static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1790{
1791 int i;
1792 u32 channel_map = 0;
1793
1794 for (i = 0; i < 8; i++) {
1795 if (channel_mask & BIT(i))
1796 channel_map |= i << (3 * i);
1797 }
1798 return channel_map;
1799}
1800
1801static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1802{
1803 int i;
1804 u32 channel_map = 0;
1805
1806 for (i = 0; i < 8; i++) {
1807 if (channel_mask & BIT(i))
1808 channel_map |= i << (4 * i);
1809 }
1810 return channel_map;
1811}
1812
1813static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
1814{
1815 struct drm_device *drm = vc4_hdmi->connector.dev;
1816 unsigned long flags;
1817 u32 hotplug;
1818 int idx;
1819
1820 if (!drm_dev_enter(drm, &idx))
1821 return false;
1822
1823 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1824 hotplug = HDMI_READ(HDMI_HOTPLUG);
1825 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1826
1827 drm_dev_exit(idx);
1828
1829 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
1830}
1831
1832/* HDMI audio codec callbacks */
1833static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1834 unsigned int samplerate)
1835{
1836 struct drm_device *drm = vc4_hdmi->connector.dev;
1837 u32 hsm_clock;
1838 unsigned long flags;
1839 unsigned long n, m;
1840 int idx;
1841
1842 if (!drm_dev_enter(drm, &idx))
1843 return;
1844
1845 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1846 rational_best_approximation(hsm_clock, samplerate,
1847 VC4_HD_MAI_SMP_N_MASK >>
1848 VC4_HD_MAI_SMP_N_SHIFT,
1849 (VC4_HD_MAI_SMP_M_MASK >>
1850 VC4_HD_MAI_SMP_M_SHIFT) + 1,
1851 &n, &m);
1852
1853 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1854 HDMI_WRITE(HDMI_MAI_SMP,
1855 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1856 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1857 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1858
1859 drm_dev_exit(idx);
1860}
1861
1862static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1863{
1864 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1865 u32 n, cts;
1866 u64 tmp;
1867
1868 lockdep_assert_held(&vc4_hdmi->mutex);
1869 lockdep_assert_held(&vc4_hdmi->hw_lock);
1870
1871 n = 128 * samplerate / 1000;
1872 tmp = (u64)(mode->clock * 1000) * n;
1873 do_div(tmp, 128 * samplerate);
1874 cts = tmp;
1875
1876 HDMI_WRITE(HDMI_CRP_CFG,
1877 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1878 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1879
1880 /*
1881 * We could get slightly more accurate clocks in some cases by
1882 * providing a CTS_1 value. The two CTS values are alternated
1883 * between based on the period fields
1884 */
1885 HDMI_WRITE(HDMI_CTS_0, cts);
1886 HDMI_WRITE(HDMI_CTS_1, cts);
1887}
1888
1889static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1890{
1891 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1892
1893 return snd_soc_card_get_drvdata(card);
1894}
1895
1896static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
1897{
1898 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1899
1900 lockdep_assert_held(&vc4_hdmi->mutex);
1901
1902 /*
1903 * If the encoder is currently in DVI mode, treat the codec DAI
1904 * as missing.
1905 */
1906 if (!display->is_hdmi)
1907 return false;
1908
1909 return true;
1910}
1911
1912static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1913{
1914 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1915 struct drm_device *drm = vc4_hdmi->connector.dev;
1916 unsigned long flags;
1917 int ret = 0;
1918 int idx;
1919
1920 mutex_lock(&vc4_hdmi->mutex);
1921
1922 if (!drm_dev_enter(drm, &idx)) {
1923 ret = -ENODEV;
1924 goto out;
1925 }
1926
1927 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1928 ret = -ENOTSUPP;
1929 goto out_dev_exit;
1930 }
1931
1932 vc4_hdmi->audio.streaming = true;
1933
1934 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1935 HDMI_WRITE(HDMI_MAI_CTL,
1936 VC4_HD_MAI_CTL_RESET |
1937 VC4_HD_MAI_CTL_FLUSH |
1938 VC4_HD_MAI_CTL_DLATE |
1939 VC4_HD_MAI_CTL_ERRORE |
1940 VC4_HD_MAI_CTL_ERRORF);
1941 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1942
1943 if (vc4_hdmi->variant->phy_rng_enable)
1944 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1945
1946out_dev_exit:
1947 drm_dev_exit(idx);
1948out:
1949 mutex_unlock(&vc4_hdmi->mutex);
1950
1951 return ret;
1952}
1953
1954static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1955{
1956 struct device *dev = &vc4_hdmi->pdev->dev;
1957 unsigned long flags;
1958 int ret;
1959
1960 lockdep_assert_held(&vc4_hdmi->mutex);
1961
1962 vc4_hdmi->audio.streaming = false;
1963 ret = vc4_hdmi_stop_packet(vc4_hdmi, HDMI_INFOFRAME_TYPE_AUDIO, false);
1964 if (ret)
1965 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1966
1967 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1968
1969 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1970 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1971 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1972
1973 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1974}
1975
1976static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1977{
1978 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1979 struct drm_device *drm = vc4_hdmi->connector.dev;
1980 unsigned long flags;
1981 int idx;
1982
1983 mutex_lock(&vc4_hdmi->mutex);
1984
1985 if (!drm_dev_enter(drm, &idx))
1986 goto out;
1987
1988 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1989
1990 HDMI_WRITE(HDMI_MAI_CTL,
1991 VC4_HD_MAI_CTL_DLATE |
1992 VC4_HD_MAI_CTL_ERRORE |
1993 VC4_HD_MAI_CTL_ERRORF);
1994
1995 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1996
1997 if (vc4_hdmi->variant->phy_rng_disable)
1998 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1999
2000 vc4_hdmi->audio.streaming = false;
2001 vc4_hdmi_audio_reset(vc4_hdmi);
2002
2003 drm_dev_exit(idx);
2004
2005out:
2006 mutex_unlock(&vc4_hdmi->mutex);
2007}
2008
2009static int sample_rate_to_mai_fmt(int samplerate)
2010{
2011 switch (samplerate) {
2012 case 8000:
2013 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
2014 case 11025:
2015 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
2016 case 12000:
2017 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
2018 case 16000:
2019 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
2020 case 22050:
2021 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
2022 case 24000:
2023 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
2024 case 32000:
2025 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
2026 case 44100:
2027 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
2028 case 48000:
2029 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
2030 case 64000:
2031 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
2032 case 88200:
2033 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
2034 case 96000:
2035 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
2036 case 128000:
2037 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
2038 case 176400:
2039 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
2040 case 192000:
2041 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
2042 default:
2043 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
2044 }
2045}
2046
2047/* HDMI audio codec callbacks */
2048static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
2049 struct hdmi_codec_daifmt *daifmt,
2050 struct hdmi_codec_params *params)
2051{
2052 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2053 struct drm_device *drm = vc4_hdmi->connector.dev;
2054 struct drm_connector *connector = &vc4_hdmi->connector;
2055 struct vc4_dev *vc4 = to_vc4_dev(drm);
2056 unsigned int sample_rate = params->sample_rate;
2057 unsigned int channels = params->channels;
2058 unsigned long flags;
2059 u32 audio_packet_config, channel_mask;
2060 u32 channel_map;
2061 u32 mai_audio_format;
2062 u32 mai_sample_rate;
2063 int ret = 0;
2064 int idx;
2065
2066 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
2067 sample_rate, params->sample_width, channels);
2068
2069 mutex_lock(&vc4_hdmi->mutex);
2070
2071 if (!drm_dev_enter(drm, &idx)) {
2072 ret = -ENODEV;
2073 goto out;
2074 }
2075
2076 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2077 ret = -EINVAL;
2078 goto out_dev_exit;
2079 }
2080
2081 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
2082
2083 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2084 HDMI_WRITE(HDMI_MAI_CTL,
2085 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
2086 VC4_HD_MAI_CTL_WHOLSMP |
2087 VC4_HD_MAI_CTL_CHALIGN |
2088 VC4_HD_MAI_CTL_ENABLE);
2089
2090 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
2091 if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
2092 params->channels == 8)
2093 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
2094 else
2095 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
2096 HDMI_WRITE(HDMI_MAI_FMT,
2097 VC4_SET_FIELD(mai_sample_rate,
2098 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
2099 VC4_SET_FIELD(mai_audio_format,
2100 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
2101
2102 /* The B frame identifier should match the value used by alsa-lib (8) */
2103 audio_packet_config =
2104 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
2105 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
2106 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
2107
2108 channel_mask = GENMASK(channels - 1, 0);
2109 audio_packet_config |= VC4_SET_FIELD(channel_mask,
2110 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
2111
2112 /* Set the MAI threshold */
2113 if (vc4->gen >= VC4_GEN_5)
2114 HDMI_WRITE(HDMI_MAI_THR,
2115 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
2116 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
2117 VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQHIGH) |
2118 VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQLOW));
2119 else
2120 HDMI_WRITE(HDMI_MAI_THR,
2121 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICHIGH) |
2122 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICLOW) |
2123 VC4_SET_FIELD(0x6, VC4_HD_MAI_THR_DREQHIGH) |
2124 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_DREQLOW));
2125
2126 HDMI_WRITE(HDMI_MAI_CONFIG,
2127 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
2128 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
2129 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
2130
2131 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
2132 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
2133 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
2134
2135 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
2136
2137 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2138
2139 ret = drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector,
2140 ¶ms->cea);
2141 if (ret)
2142 goto out_dev_exit;
2143
2144out_dev_exit:
2145 drm_dev_exit(idx);
2146out:
2147 mutex_unlock(&vc4_hdmi->mutex);
2148
2149 return ret;
2150}
2151
2152static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2153 .name = "vc4-hdmi-cpu-dai-component",
2154 .legacy_dai_naming = 1,
2155};
2156
2157static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2158{
2159 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2160
2161 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2162
2163 return 0;
2164}
2165
2166static const struct snd_soc_dai_ops vc4_snd_dai_ops = {
2167 .probe = vc4_hdmi_audio_cpu_dai_probe,
2168};
2169
2170static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2171 .name = "vc4-hdmi-cpu-dai",
2172 .ops = &vc4_snd_dai_ops,
2173 .playback = {
2174 .stream_name = "Playback",
2175 .channels_min = 1,
2176 .channels_max = 8,
2177 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2178 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2179 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2180 SNDRV_PCM_RATE_192000,
2181 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2182 },
2183};
2184
2185static const struct snd_dmaengine_pcm_config pcm_conf = {
2186 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2187 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2188};
2189
2190static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
2191 uint8_t *buf, size_t len)
2192{
2193 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2194 struct drm_connector *connector = &vc4_hdmi->connector;
2195
2196 mutex_lock(&connector->eld_mutex);
2197 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2198 mutex_unlock(&connector->eld_mutex);
2199
2200 return 0;
2201}
2202
2203static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
2204 .get_eld = vc4_hdmi_audio_get_eld,
2205 .prepare = vc4_hdmi_audio_prepare,
2206 .audio_shutdown = vc4_hdmi_audio_shutdown,
2207 .audio_startup = vc4_hdmi_audio_startup,
2208};
2209
2210static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
2211 .ops = &vc4_hdmi_codec_ops,
2212 .max_i2s_channels = 8,
2213 .i2s = 1,
2214};
2215
2216static void vc4_hdmi_audio_codec_release(void *ptr)
2217{
2218 struct vc4_hdmi *vc4_hdmi = ptr;
2219
2220 platform_device_unregister(vc4_hdmi->audio.codec_pdev);
2221 vc4_hdmi->audio.codec_pdev = NULL;
2222}
2223
2224static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2225{
2226 const struct vc4_hdmi_register *mai_data =
2227 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2228 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2229 struct snd_soc_card *card = &vc4_hdmi->audio.card;
2230 struct device *dev = &vc4_hdmi->pdev->dev;
2231 struct platform_device *codec_pdev;
2232 const __be32 *addr;
2233 int index, len;
2234 int ret;
2235
2236 /*
2237 * ASoC makes it a bit hard to retrieve a pointer to the
2238 * vc4_hdmi structure. Registering the card will overwrite our
2239 * device drvdata with a pointer to the snd_soc_card structure,
2240 * which can then be used to retrieve whatever drvdata we want
2241 * to associate.
2242 *
2243 * However, that doesn't fly in the case where we wouldn't
2244 * register an ASoC card (because of an old DT that is missing
2245 * the dmas properties for example), then the card isn't
2246 * registered and the device drvdata wouldn't be set.
2247 *
2248 * We can deal with both cases by making sure a snd_soc_card
2249 * pointer and a vc4_hdmi structure are pointing to the same
2250 * memory address, so we can treat them indistinctly without any
2251 * issue.
2252 */
2253 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2254 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2255
2256 if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
2257 dev_warn(dev,
2258 "'dmas' DT property is missing or empty, no HDMI audio\n");
2259 return 0;
2260 }
2261
2262 if (mai_data->reg != VC4_HD) {
2263 WARN_ONCE(true, "MAI isn't in the HD block\n");
2264 return -EINVAL;
2265 }
2266
2267 /*
2268 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2269 * the bus address specified in the DT, because the physical address
2270 * (the one returned by platform_get_resource()) is not appropriate
2271 * for DMA transfers.
2272 * This VC/MMU should probably be exposed to avoid this kind of hacks.
2273 */
2274 index = of_property_match_string(dev->of_node, "reg-names", "hd");
2275 /* Before BCM2711, we don't have a named register range */
2276 if (index < 0)
2277 index = 1;
2278
2279 addr = of_get_address(dev->of_node, index, NULL, NULL);
2280 if (!addr)
2281 return -EINVAL;
2282
2283 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2284 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2285 vc4_hdmi->audio.dma_data.maxburst = 2;
2286
2287 /*
2288 * NOTE: Strictly speaking, we should probably use a DRM-managed
2289 * registration there to avoid removing all the audio components
2290 * by the time the driver doesn't have any user anymore.
2291 *
2292 * However, the ASoC core uses a number of devm_kzalloc calls
2293 * when registering, even when using non-device-managed
2294 * functions (such as in snd_soc_register_component()).
2295 *
2296 * If we call snd_soc_unregister_component() in a DRM-managed
2297 * action, the device-managed actions have already been executed
2298 * and thus we would access memory that has been freed.
2299 *
2300 * Using device-managed hooks here probably leaves us open to a
2301 * bunch of issues if userspace still has a handle on the ALSA
2302 * device when the device is removed. However, this is mitigated
2303 * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2304 * path to prevent the access to the device resources if it
2305 * isn't there anymore.
2306 *
2307 * Then, the vc4_hdmi structure is DRM-managed and thus only
2308 * freed whenever the last user has closed the DRM device file.
2309 * It should thus outlive ALSA in most situations.
2310 */
2311 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2312 if (ret) {
2313 dev_err(dev, "Could not register PCM component: %d\n", ret);
2314 return ret;
2315 }
2316
2317 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2318 &vc4_hdmi_audio_cpu_dai_drv, 1);
2319 if (ret) {
2320 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2321 return ret;
2322 }
2323
2324 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
2325 PLATFORM_DEVID_AUTO,
2326 &vc4_hdmi_codec_pdata,
2327 sizeof(vc4_hdmi_codec_pdata));
2328 if (IS_ERR(codec_pdev)) {
2329 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
2330 return PTR_ERR(codec_pdev);
2331 }
2332 vc4_hdmi->audio.codec_pdev = codec_pdev;
2333
2334 ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi);
2335 if (ret)
2336 return ret;
2337
2338 dai_link->cpus = &vc4_hdmi->audio.cpu;
2339 dai_link->codecs = &vc4_hdmi->audio.codec;
2340 dai_link->platforms = &vc4_hdmi->audio.platform;
2341
2342 dai_link->num_cpus = 1;
2343 dai_link->num_codecs = 1;
2344 dai_link->num_platforms = 1;
2345
2346 dai_link->name = "MAI";
2347 dai_link->stream_name = "MAI PCM";
2348 dai_link->codecs->dai_name = "i2s-hifi";
2349 dai_link->cpus->dai_name = dev_name(dev);
2350 dai_link->codecs->name = dev_name(&codec_pdev->dev);
2351 dai_link->platforms->name = dev_name(dev);
2352
2353 card->dai_link = dai_link;
2354 card->num_links = 1;
2355 card->name = vc4_hdmi->variant->card_name;
2356 card->driver_name = "vc4-hdmi";
2357 card->dev = dev;
2358 card->owner = THIS_MODULE;
2359
2360 /*
2361 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2362 * stores a pointer to the snd card object in dev->driver_data. This
2363 * means we cannot use it for something else. The hdmi back-pointer is
2364 * now stored in card->drvdata and should be retrieved with
2365 * snd_soc_card_get_drvdata() if needed.
2366 */
2367 snd_soc_card_set_drvdata(card, vc4_hdmi);
2368 ret = devm_snd_soc_register_card(dev, card);
2369 if (ret)
2370 dev_err_probe(dev, ret, "Could not register sound card\n");
2371
2372 return ret;
2373
2374}
2375
2376static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2377{
2378 struct vc4_hdmi *vc4_hdmi = priv;
2379 struct drm_connector *connector = &vc4_hdmi->connector;
2380 struct drm_device *dev = connector->dev;
2381
2382 if (dev && dev->registered)
2383 drm_connector_helper_hpd_irq_event(connector);
2384
2385 return IRQ_HANDLED;
2386}
2387
2388static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2389{
2390 struct drm_connector *connector = &vc4_hdmi->connector;
2391 struct platform_device *pdev = vc4_hdmi->pdev;
2392 int ret;
2393
2394 if (vc4_hdmi->variant->external_irq_controller) {
2395 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2396 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2397
2398 ret = devm_request_threaded_irq(&pdev->dev, hpd_con,
2399 NULL,
2400 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2401 "vc4 hdmi hpd connected", vc4_hdmi);
2402 if (ret)
2403 return ret;
2404
2405 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm,
2406 NULL,
2407 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2408 "vc4 hdmi hpd disconnected", vc4_hdmi);
2409 if (ret)
2410 return ret;
2411
2412 connector->polled = DRM_CONNECTOR_POLL_HPD;
2413 }
2414
2415 return 0;
2416}
2417
2418#ifdef CONFIG_DRM_VC4_HDMI_CEC
2419static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2420{
2421 struct vc4_hdmi *vc4_hdmi = priv;
2422
2423 if (vc4_hdmi->cec_rx_msg.len)
2424 cec_received_msg(vc4_hdmi->cec_adap,
2425 &vc4_hdmi->cec_rx_msg);
2426
2427 return IRQ_HANDLED;
2428}
2429
2430static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2431{
2432 struct vc4_hdmi *vc4_hdmi = priv;
2433
2434 if (vc4_hdmi->cec_tx_ok) {
2435 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2436 0, 0, 0, 0);
2437 } else {
2438 /*
2439 * This CEC implementation makes 1 retry, so if we
2440 * get a NACK, then that means it made 2 attempts.
2441 */
2442 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2443 0, 2, 0, 0);
2444 }
2445 return IRQ_HANDLED;
2446}
2447
2448static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2449{
2450 struct vc4_hdmi *vc4_hdmi = priv;
2451 irqreturn_t ret;
2452
2453 if (vc4_hdmi->cec_irq_was_rx)
2454 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2455 else
2456 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2457
2458 return ret;
2459}
2460
2461static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2462{
2463 struct drm_device *dev = vc4_hdmi->connector.dev;
2464 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2465 unsigned int i;
2466
2467 lockdep_assert_held(&vc4_hdmi->hw_lock);
2468
2469 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2470 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2471
2472 if (msg->len > 16) {
2473 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2474 return;
2475 }
2476
2477 for (i = 0; i < msg->len; i += 4) {
2478 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2479
2480 msg->msg[i] = val & 0xff;
2481 msg->msg[i + 1] = (val >> 8) & 0xff;
2482 msg->msg[i + 2] = (val >> 16) & 0xff;
2483 msg->msg[i + 3] = (val >> 24) & 0xff;
2484 }
2485}
2486
2487static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2488{
2489 u32 cntrl1;
2490
2491 /*
2492 * We don't need to protect the register access using
2493 * drm_dev_enter() there because the interrupt handler lifetime
2494 * is tied to the device itself, and not to the DRM device.
2495 *
2496 * So when the device will be gone, one of the first thing we
2497 * will be doing will be to unregister the interrupt handler,
2498 * and then unregister the DRM device. drm_dev_enter() would
2499 * thus always succeed if we are here.
2500 */
2501
2502 lockdep_assert_held(&vc4_hdmi->hw_lock);
2503
2504 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2505 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2506 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2507 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2508
2509 return IRQ_WAKE_THREAD;
2510}
2511
2512static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2513{
2514 struct vc4_hdmi *vc4_hdmi = priv;
2515 irqreturn_t ret;
2516
2517 spin_lock(&vc4_hdmi->hw_lock);
2518 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2519 spin_unlock(&vc4_hdmi->hw_lock);
2520
2521 return ret;
2522}
2523
2524static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2525{
2526 u32 cntrl1;
2527
2528 lockdep_assert_held(&vc4_hdmi->hw_lock);
2529
2530 /*
2531 * We don't need to protect the register access using
2532 * drm_dev_enter() there because the interrupt handler lifetime
2533 * is tied to the device itself, and not to the DRM device.
2534 *
2535 * So when the device will be gone, one of the first thing we
2536 * will be doing will be to unregister the interrupt handler,
2537 * and then unregister the DRM device. drm_dev_enter() would
2538 * thus always succeed if we are here.
2539 */
2540
2541 vc4_hdmi->cec_rx_msg.len = 0;
2542 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2543 vc4_cec_read_msg(vc4_hdmi, cntrl1);
2544 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2545 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2546 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2547
2548 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2549
2550 return IRQ_WAKE_THREAD;
2551}
2552
2553static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
2554{
2555 struct vc4_hdmi *vc4_hdmi = priv;
2556 irqreturn_t ret;
2557
2558 spin_lock(&vc4_hdmi->hw_lock);
2559 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2560 spin_unlock(&vc4_hdmi->hw_lock);
2561
2562 return ret;
2563}
2564
2565static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
2566{
2567 struct vc4_hdmi *vc4_hdmi = priv;
2568 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
2569 irqreturn_t ret;
2570 u32 cntrl5;
2571
2572 /*
2573 * We don't need to protect the register access using
2574 * drm_dev_enter() there because the interrupt handler lifetime
2575 * is tied to the device itself, and not to the DRM device.
2576 *
2577 * So when the device will be gone, one of the first thing we
2578 * will be doing will be to unregister the interrupt handler,
2579 * and then unregister the DRM device. drm_dev_enter() would
2580 * thus always succeed if we are here.
2581 */
2582
2583 if (!(stat & VC4_HDMI_CPU_CEC))
2584 return IRQ_NONE;
2585
2586 spin_lock(&vc4_hdmi->hw_lock);
2587 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
2588 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
2589 if (vc4_hdmi->cec_irq_was_rx)
2590 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2591 else
2592 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2593
2594 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2595 spin_unlock(&vc4_hdmi->hw_lock);
2596
2597 return ret;
2598}
2599
2600static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2601{
2602 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2603 struct drm_device *drm = vc4_hdmi->connector.dev;
2604 /* clock period in microseconds */
2605 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2606 unsigned long flags;
2607 u32 val;
2608 int ret;
2609 int idx;
2610
2611 if (!drm_dev_enter(drm, &idx))
2612 /*
2613 * We can't return an error code, because the CEC
2614 * framework will emit WARN_ON messages at unbind
2615 * otherwise.
2616 */
2617 return 0;
2618
2619 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2620 if (ret) {
2621 drm_dev_exit(idx);
2622 return ret;
2623 }
2624
2625 mutex_lock(&vc4_hdmi->mutex);
2626
2627 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2628
2629 val = HDMI_READ(HDMI_CEC_CNTRL_5);
2630 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2631 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2632 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2633 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2634 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2635
2636 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2637 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2638 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2639 HDMI_WRITE(HDMI_CEC_CNTRL_2,
2640 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2641 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2642 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2643 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2644 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2645 HDMI_WRITE(HDMI_CEC_CNTRL_3,
2646 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2647 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2648 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2649 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2650 HDMI_WRITE(HDMI_CEC_CNTRL_4,
2651 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2652 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2653 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2654 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2655
2656 if (!vc4_hdmi->variant->external_irq_controller)
2657 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2658
2659 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2660
2661 mutex_unlock(&vc4_hdmi->mutex);
2662 drm_dev_exit(idx);
2663
2664 return 0;
2665}
2666
2667static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2668{
2669 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2670 struct drm_device *drm = vc4_hdmi->connector.dev;
2671 unsigned long flags;
2672 int idx;
2673
2674 if (!drm_dev_enter(drm, &idx))
2675 /*
2676 * We can't return an error code, because the CEC
2677 * framework will emit WARN_ON messages at unbind
2678 * otherwise.
2679 */
2680 return 0;
2681
2682 mutex_lock(&vc4_hdmi->mutex);
2683
2684 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2685
2686 if (!vc4_hdmi->variant->external_irq_controller)
2687 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2688
2689 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2690 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2691
2692 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2693
2694 mutex_unlock(&vc4_hdmi->mutex);
2695
2696 pm_runtime_put(&vc4_hdmi->pdev->dev);
2697
2698 drm_dev_exit(idx);
2699
2700 return 0;
2701}
2702
2703static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2704{
2705 if (enable)
2706 return vc4_hdmi_cec_enable(adap);
2707 else
2708 return vc4_hdmi_cec_disable(adap);
2709}
2710
2711static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2712{
2713 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2714 struct drm_device *drm = vc4_hdmi->connector.dev;
2715 unsigned long flags;
2716 int idx;
2717
2718 if (!drm_dev_enter(drm, &idx))
2719 /*
2720 * We can't return an error code, because the CEC
2721 * framework will emit WARN_ON messages at unbind
2722 * otherwise.
2723 */
2724 return 0;
2725
2726 mutex_lock(&vc4_hdmi->mutex);
2727 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2728 HDMI_WRITE(HDMI_CEC_CNTRL_1,
2729 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2730 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2731 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2732 mutex_unlock(&vc4_hdmi->mutex);
2733
2734 drm_dev_exit(idx);
2735
2736 return 0;
2737}
2738
2739static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2740 u32 signal_free_time, struct cec_msg *msg)
2741{
2742 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2743 struct drm_device *dev = vc4_hdmi->connector.dev;
2744 unsigned long flags;
2745 u32 val;
2746 unsigned int i;
2747 int idx;
2748
2749 if (!drm_dev_enter(dev, &idx))
2750 return -ENODEV;
2751
2752 if (msg->len > 16) {
2753 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2754 drm_dev_exit(idx);
2755 return -ENOMEM;
2756 }
2757
2758 mutex_lock(&vc4_hdmi->mutex);
2759
2760 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2761
2762 for (i = 0; i < msg->len; i += 4)
2763 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2764 (msg->msg[i]) |
2765 (msg->msg[i + 1] << 8) |
2766 (msg->msg[i + 2] << 16) |
2767 (msg->msg[i + 3] << 24));
2768
2769 val = HDMI_READ(HDMI_CEC_CNTRL_1);
2770 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2771 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2772 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2773 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2774 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2775
2776 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2777
2778 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2779 mutex_unlock(&vc4_hdmi->mutex);
2780 drm_dev_exit(idx);
2781
2782 return 0;
2783}
2784
2785static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2786 .adap_enable = vc4_hdmi_cec_adap_enable,
2787 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2788 .adap_transmit = vc4_hdmi_cec_adap_transmit,
2789};
2790
2791static void vc4_hdmi_cec_release(void *ptr)
2792{
2793 struct vc4_hdmi *vc4_hdmi = ptr;
2794
2795 cec_unregister_adapter(vc4_hdmi->cec_adap);
2796 vc4_hdmi->cec_adap = NULL;
2797}
2798
2799static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2800{
2801 struct cec_connector_info conn_info;
2802 struct platform_device *pdev = vc4_hdmi->pdev;
2803 struct device *dev = &pdev->dev;
2804 int ret;
2805
2806 if (!of_property_present(dev->of_node, "interrupts")) {
2807 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
2808 return 0;
2809 }
2810
2811 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
2812 vc4_hdmi,
2813 vc4_hdmi->variant->card_name,
2814 CEC_CAP_DEFAULTS |
2815 CEC_CAP_CONNECTOR_INFO, 1);
2816 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
2817 if (ret < 0)
2818 return ret;
2819
2820 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
2821 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
2822
2823 if (vc4_hdmi->variant->external_irq_controller) {
2824 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
2825 vc4_cec_irq_handler_rx_bare,
2826 vc4_cec_irq_handler_rx_thread, 0,
2827 "vc4 hdmi cec rx", vc4_hdmi);
2828 if (ret)
2829 goto err_delete_cec_adap;
2830
2831 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
2832 vc4_cec_irq_handler_tx_bare,
2833 vc4_cec_irq_handler_tx_thread, 0,
2834 "vc4 hdmi cec tx", vc4_hdmi);
2835 if (ret)
2836 goto err_delete_cec_adap;
2837 } else {
2838 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
2839 vc4_cec_irq_handler,
2840 vc4_cec_irq_handler_thread, 0,
2841 "vc4 hdmi cec", vc4_hdmi);
2842 if (ret)
2843 goto err_delete_cec_adap;
2844 }
2845
2846 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
2847 if (ret < 0)
2848 goto err_delete_cec_adap;
2849
2850 /*
2851 * NOTE: Strictly speaking, we should probably use a DRM-managed
2852 * registration there to avoid removing the CEC adapter by the
2853 * time the DRM driver doesn't have any user anymore.
2854 *
2855 * However, the CEC framework already cleans up the CEC adapter
2856 * only when the last user has closed its file descriptor, so we
2857 * don't need to handle it in DRM.
2858 *
2859 * By the time the device-managed hook is executed, we will give
2860 * up our reference to the CEC adapter and therefore don't
2861 * really care when it's actually freed.
2862 *
2863 * There's still a problematic sequence: if we unregister our
2864 * CEC adapter, but the userspace keeps a handle on the CEC
2865 * adapter but not the DRM device for some reason. In such a
2866 * case, our vc4_hdmi structure will be freed, but the
2867 * cec_adapter structure will have a dangling pointer to what
2868 * used to be our HDMI controller. If we get a CEC call at that
2869 * moment, we could end up with a use-after-free. Fortunately,
2870 * the CEC framework already handles this too, by calling
2871 * cec_is_registered() in cec_ioctl() and cec_poll().
2872 */
2873 ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
2874 if (ret)
2875 return ret;
2876
2877 return 0;
2878
2879err_delete_cec_adap:
2880 cec_delete_adapter(vc4_hdmi->cec_adap);
2881
2882 return ret;
2883}
2884#else
2885static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2886{
2887 return 0;
2888}
2889#endif
2890
2891static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr)
2892{
2893 struct debugfs_reg32 *regs = ptr;
2894
2895 kfree(regs);
2896}
2897
2898static int vc4_hdmi_build_regset(struct drm_device *drm,
2899 struct vc4_hdmi *vc4_hdmi,
2900 struct debugfs_regset32 *regset,
2901 enum vc4_hdmi_regs reg)
2902{
2903 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2904 struct debugfs_reg32 *regs, *new_regs;
2905 unsigned int count = 0;
2906 unsigned int i;
2907 int ret;
2908
2909 regs = kcalloc(variant->num_registers, sizeof(*regs),
2910 GFP_KERNEL);
2911 if (!regs)
2912 return -ENOMEM;
2913
2914 for (i = 0; i < variant->num_registers; i++) {
2915 const struct vc4_hdmi_register *field = &variant->registers[i];
2916
2917 if (field->reg != reg)
2918 continue;
2919
2920 regs[count].name = field->name;
2921 regs[count].offset = field->offset;
2922 count++;
2923 }
2924
2925 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
2926 if (!new_regs)
2927 return -ENOMEM;
2928
2929 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
2930 regset->regs = new_regs;
2931 regset->nregs = count;
2932
2933 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
2934 if (ret)
2935 return ret;
2936
2937 return 0;
2938}
2939
2940static int vc4_hdmi_init_resources(struct drm_device *drm,
2941 struct vc4_hdmi *vc4_hdmi)
2942{
2943 struct platform_device *pdev = vc4_hdmi->pdev;
2944 struct device *dev = &pdev->dev;
2945 int ret;
2946
2947 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
2948 if (IS_ERR(vc4_hdmi->hdmicore_regs))
2949 return PTR_ERR(vc4_hdmi->hdmicore_regs);
2950
2951 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
2952 if (IS_ERR(vc4_hdmi->hd_regs))
2953 return PTR_ERR(vc4_hdmi->hd_regs);
2954
2955 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2956 if (ret)
2957 return ret;
2958
2959 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2960 if (ret)
2961 return ret;
2962
2963 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
2964 if (IS_ERR(vc4_hdmi->pixel_clock)) {
2965 ret = PTR_ERR(vc4_hdmi->pixel_clock);
2966 if (ret != -EPROBE_DEFER)
2967 drm_err(drm, "Failed to get pixel clock\n");
2968 return ret;
2969 }
2970
2971 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2972 if (IS_ERR(vc4_hdmi->hsm_clock)) {
2973 drm_err(drm, "Failed to get HDMI state machine clock\n");
2974 return PTR_ERR(vc4_hdmi->hsm_clock);
2975 }
2976 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2977 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2978
2979 return 0;
2980}
2981
2982static int vc5_hdmi_init_resources(struct drm_device *drm,
2983 struct vc4_hdmi *vc4_hdmi)
2984{
2985 struct platform_device *pdev = vc4_hdmi->pdev;
2986 struct device *dev = &pdev->dev;
2987 struct resource *res;
2988 int ret;
2989
2990 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2991 if (!res)
2992 return -ENODEV;
2993
2994 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2995 resource_size(res));
2996 if (!vc4_hdmi->hdmicore_regs)
2997 return -ENOMEM;
2998
2999 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
3000 if (!res)
3001 return -ENODEV;
3002
3003 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
3004 if (!vc4_hdmi->hd_regs)
3005 return -ENOMEM;
3006
3007 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
3008 if (!res)
3009 return -ENODEV;
3010
3011 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
3012 if (!vc4_hdmi->cec_regs)
3013 return -ENOMEM;
3014
3015 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
3016 if (!res)
3017 return -ENODEV;
3018
3019 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
3020 if (!vc4_hdmi->csc_regs)
3021 return -ENOMEM;
3022
3023 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
3024 if (!res)
3025 return -ENODEV;
3026
3027 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
3028 if (!vc4_hdmi->dvp_regs)
3029 return -ENOMEM;
3030
3031 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
3032 if (!res)
3033 return -ENODEV;
3034
3035 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
3036 if (!vc4_hdmi->phy_regs)
3037 return -ENOMEM;
3038
3039 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
3040 if (!res)
3041 return -ENODEV;
3042
3043 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
3044 if (!vc4_hdmi->ram_regs)
3045 return -ENOMEM;
3046
3047 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
3048 if (!res)
3049 return -ENODEV;
3050
3051 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
3052 if (!vc4_hdmi->rm_regs)
3053 return -ENOMEM;
3054
3055 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3056 if (IS_ERR(vc4_hdmi->hsm_clock)) {
3057 drm_err(drm, "Failed to get HDMI state machine clock\n");
3058 return PTR_ERR(vc4_hdmi->hsm_clock);
3059 }
3060
3061 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3062 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3063 drm_err(drm, "Failed to get pixel bvb clock\n");
3064 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
3065 }
3066
3067 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
3068 if (IS_ERR(vc4_hdmi->audio_clock)) {
3069 drm_err(drm, "Failed to get audio clock\n");
3070 return PTR_ERR(vc4_hdmi->audio_clock);
3071 }
3072
3073 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
3074 if (IS_ERR(vc4_hdmi->cec_clock)) {
3075 drm_err(drm, "Failed to get CEC clock\n");
3076 return PTR_ERR(vc4_hdmi->cec_clock);
3077 }
3078
3079 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3080 if (IS_ERR(vc4_hdmi->reset)) {
3081 drm_err(drm, "Failed to get HDMI reset line\n");
3082 return PTR_ERR(vc4_hdmi->reset);
3083 }
3084
3085 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3086 if (ret)
3087 return ret;
3088
3089 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3090 if (ret)
3091 return ret;
3092
3093 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
3094 if (ret)
3095 return ret;
3096
3097 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
3098 if (ret)
3099 return ret;
3100
3101 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
3102 if (ret)
3103 return ret;
3104
3105 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
3106 if (ret)
3107 return ret;
3108
3109 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
3110 if (ret)
3111 return ret;
3112
3113 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
3114 if (ret)
3115 return ret;
3116
3117 return 0;
3118}
3119
3120static int vc4_hdmi_runtime_suspend(struct device *dev)
3121{
3122 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3123
3124 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3125
3126 return 0;
3127}
3128
3129static int vc4_hdmi_runtime_resume(struct device *dev)
3130{
3131 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3132 unsigned long __maybe_unused flags;
3133 u32 __maybe_unused value;
3134 unsigned long rate;
3135 int ret;
3136
3137 ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
3138 if (ret)
3139 return ret;
3140
3141 /*
3142 * Whenever the RaspberryPi boots without an HDMI monitor
3143 * plugged in, the firmware won't have initialized the HSM clock
3144 * rate and it will be reported as 0.
3145 *
3146 * If we try to access a register of the controller in such a
3147 * case, it will lead to a silent CPU stall. Let's make sure we
3148 * prevent such a case.
3149 */
3150 rate = clk_get_rate(vc4_hdmi->hsm_clock);
3151 if (!rate) {
3152 ret = -EINVAL;
3153 goto err_disable_clk;
3154 }
3155
3156 if (vc4_hdmi->variant->reset)
3157 vc4_hdmi->variant->reset(vc4_hdmi);
3158
3159#ifdef CONFIG_DRM_VC4_HDMI_CEC
3160 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3161 value = HDMI_READ(HDMI_CEC_CNTRL_1);
3162 /* Set the logical address to Unregistered */
3163 value |= VC4_HDMI_CEC_ADDR_MASK;
3164 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
3165 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3166
3167 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
3168
3169 if (!vc4_hdmi->variant->external_irq_controller) {
3170 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3171 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3172 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3173 }
3174#endif
3175
3176 return 0;
3177
3178err_disable_clk:
3179 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3180 return ret;
3181}
3182
3183static void vc4_hdmi_put_ddc_device(void *ptr)
3184{
3185 struct vc4_hdmi *vc4_hdmi = ptr;
3186
3187 put_device(&vc4_hdmi->ddc->dev);
3188}
3189
3190static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
3191{
3192 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
3193 struct platform_device *pdev = to_platform_device(dev);
3194 struct drm_device *drm = dev_get_drvdata(master);
3195 struct vc4_hdmi *vc4_hdmi;
3196 struct drm_encoder *encoder;
3197 struct device_node *ddc_node;
3198 int ret;
3199
3200 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
3201 if (!vc4_hdmi)
3202 return -ENOMEM;
3203
3204 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex);
3205 if (ret)
3206 return ret;
3207
3208 spin_lock_init(&vc4_hdmi->hw_lock);
3209 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
3210
3211 dev_set_drvdata(dev, vc4_hdmi);
3212 encoder = &vc4_hdmi->encoder.base;
3213 vc4_hdmi->encoder.type = variant->encoder_type;
3214 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
3215 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
3216 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
3217 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
3218 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
3219 vc4_hdmi->pdev = pdev;
3220 vc4_hdmi->variant = variant;
3221
3222 /*
3223 * Since we don't know the state of the controller and its
3224 * display (if any), let's assume it's always enabled.
3225 * vc4_hdmi_disable_scrambling() will thus run at boot, make
3226 * sure it's disabled, and avoid any inconsistency.
3227 */
3228 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
3229 vc4_hdmi->scdc_enabled = true;
3230
3231 ret = variant->init_resources(drm, vc4_hdmi);
3232 if (ret)
3233 return ret;
3234
3235 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3236 if (!ddc_node) {
3237 drm_err(drm, "Failed to find ddc node in device tree\n");
3238 return -ENODEV;
3239 }
3240
3241 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3242 of_node_put(ddc_node);
3243 if (!vc4_hdmi->ddc) {
3244 drm_err(drm, "Failed to get ddc i2c adapter by node\n");
3245 return -EPROBE_DEFER;
3246 }
3247
3248 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
3249 if (ret)
3250 return ret;
3251
3252 /* Only use the GPIO HPD pin if present in the DT, otherwise
3253 * we'll use the HDMI core's register.
3254 */
3255 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3256 if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3257 return PTR_ERR(vc4_hdmi->hpd_gpio);
3258 }
3259
3260 vc4_hdmi->disable_wifi_frequencies =
3261 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3262
3263 ret = devm_pm_runtime_enable(dev);
3264 if (ret)
3265 return ret;
3266
3267 /*
3268 * We need to have the device powered up at this point to call
3269 * our reset hook and for the CEC init.
3270 */
3271 ret = pm_runtime_resume_and_get(dev);
3272 if (ret)
3273 return ret;
3274
3275 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3276 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
3277 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3278 clk_prepare_enable(vc4_hdmi->pixel_clock);
3279 clk_prepare_enable(vc4_hdmi->hsm_clock);
3280 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3281 }
3282
3283 ret = drmm_encoder_init(drm, encoder,
3284 &vc4_hdmi_encoder_funcs,
3285 DRM_MODE_ENCODER_TMDS,
3286 NULL);
3287 if (ret)
3288 goto err_put_runtime_pm;
3289
3290 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3291
3292 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3293 if (ret)
3294 goto err_put_runtime_pm;
3295
3296 ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3297 if (ret)
3298 goto err_put_runtime_pm;
3299
3300 ret = vc4_hdmi_cec_init(vc4_hdmi);
3301 if (ret)
3302 goto err_put_runtime_pm;
3303
3304 ret = vc4_hdmi_audio_init(vc4_hdmi);
3305 if (ret)
3306 goto err_put_runtime_pm;
3307
3308 pm_runtime_put_sync(dev);
3309
3310 return 0;
3311
3312err_put_runtime_pm:
3313 pm_runtime_put_sync(dev);
3314
3315 return ret;
3316}
3317
3318static const struct component_ops vc4_hdmi_ops = {
3319 .bind = vc4_hdmi_bind,
3320};
3321
3322static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3323{
3324 return component_add(&pdev->dev, &vc4_hdmi_ops);
3325}
3326
3327static void vc4_hdmi_dev_remove(struct platform_device *pdev)
3328{
3329 component_del(&pdev->dev, &vc4_hdmi_ops);
3330}
3331
3332static const struct vc4_hdmi_variant bcm2835_variant = {
3333 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3334 .debugfs_name = "hdmi_regs",
3335 .card_name = "vc4-hdmi",
3336 .max_pixel_clock = 162000000,
3337 .registers = vc4_hdmi_fields,
3338 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
3339
3340 .init_resources = vc4_hdmi_init_resources,
3341 .csc_setup = vc4_hdmi_csc_setup,
3342 .reset = vc4_hdmi_reset,
3343 .set_timings = vc4_hdmi_set_timings,
3344 .phy_init = vc4_hdmi_phy_init,
3345 .phy_disable = vc4_hdmi_phy_disable,
3346 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
3347 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
3348 .channel_map = vc4_hdmi_channel_map,
3349 .supports_hdr = false,
3350};
3351
3352static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3353 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3354 .debugfs_name = "hdmi0_regs",
3355 .card_name = "vc4-hdmi-0",
3356 .max_pixel_clock = 600000000,
3357 .registers = vc5_hdmi_hdmi0_fields,
3358 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3359 .phy_lane_mapping = {
3360 PHY_LANE_0,
3361 PHY_LANE_1,
3362 PHY_LANE_2,
3363 PHY_LANE_CK,
3364 },
3365 .unsupported_odd_h_timings = true,
3366 .external_irq_controller = true,
3367
3368 .init_resources = vc5_hdmi_init_resources,
3369 .csc_setup = vc5_hdmi_csc_setup,
3370 .reset = vc5_hdmi_reset,
3371 .set_timings = vc5_hdmi_set_timings,
3372 .phy_init = vc5_hdmi_phy_init,
3373 .phy_disable = vc5_hdmi_phy_disable,
3374 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3375 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3376 .channel_map = vc5_hdmi_channel_map,
3377 .supports_hdr = true,
3378 .hp_detect = vc5_hdmi_hp_detect,
3379};
3380
3381static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3382 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
3383 .debugfs_name = "hdmi1_regs",
3384 .card_name = "vc4-hdmi-1",
3385 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
3386 .registers = vc5_hdmi_hdmi1_fields,
3387 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3388 .phy_lane_mapping = {
3389 PHY_LANE_1,
3390 PHY_LANE_0,
3391 PHY_LANE_CK,
3392 PHY_LANE_2,
3393 },
3394 .unsupported_odd_h_timings = true,
3395 .external_irq_controller = true,
3396
3397 .init_resources = vc5_hdmi_init_resources,
3398 .csc_setup = vc5_hdmi_csc_setup,
3399 .reset = vc5_hdmi_reset,
3400 .set_timings = vc5_hdmi_set_timings,
3401 .phy_init = vc5_hdmi_phy_init,
3402 .phy_disable = vc5_hdmi_phy_disable,
3403 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3404 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3405 .channel_map = vc5_hdmi_channel_map,
3406 .supports_hdr = true,
3407 .hp_detect = vc5_hdmi_hp_detect,
3408};
3409
3410static const struct of_device_id vc4_hdmi_dt_match[] = {
3411 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3412 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3413 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3414 {}
3415};
3416
3417static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3418 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3419 vc4_hdmi_runtime_resume,
3420 NULL)
3421};
3422
3423struct platform_driver vc4_hdmi_driver = {
3424 .probe = vc4_hdmi_dev_probe,
3425 .remove = vc4_hdmi_dev_remove,
3426 .driver = {
3427 .name = "vc4_hdmi",
3428 .of_match_table = vc4_hdmi_dt_match,
3429 .pm = &vc4_hdmi_pm_ops,
3430 },
3431};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
7 */
8
9/**
10 * DOC: VC4 Falcon HDMI module
11 *
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
15 *
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
18 *
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
23 * blank regions.
24 *
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
29 *
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
32 */
33
34#include <drm/display/drm_hdmi_helper.h>
35#include <drm/display/drm_scdc_helper.h>
36#include <drm/drm_atomic_helper.h>
37#include <drm/drm_drv.h>
38#include <drm/drm_edid.h>
39#include <drm/drm_probe_helper.h>
40#include <drm/drm_simple_kms_helper.h>
41#include <linux/clk.h>
42#include <linux/component.h>
43#include <linux/gpio/consumer.h>
44#include <linux/i2c.h>
45#include <linux/of.h>
46#include <linux/of_address.h>
47#include <linux/pm_runtime.h>
48#include <linux/rational.h>
49#include <linux/reset.h>
50#include <sound/dmaengine_pcm.h>
51#include <sound/hdmi-codec.h>
52#include <sound/pcm_drm_eld.h>
53#include <sound/pcm_params.h>
54#include <sound/soc.h>
55#include "media/cec.h"
56#include "vc4_drv.h"
57#include "vc4_hdmi.h"
58#include "vc4_hdmi_regs.h"
59#include "vc4_regs.h"
60
61#define VC5_HDMI_HORZA_HFP_SHIFT 16
62#define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
63#define VC5_HDMI_HORZA_VPOS BIT(15)
64#define VC5_HDMI_HORZA_HPOS BIT(14)
65#define VC5_HDMI_HORZA_HAP_SHIFT 0
66#define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
67
68#define VC5_HDMI_HORZB_HBP_SHIFT 16
69#define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
70#define VC5_HDMI_HORZB_HSP_SHIFT 0
71#define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
72
73#define VC5_HDMI_VERTA_VSP_SHIFT 24
74#define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
75#define VC5_HDMI_VERTA_VFP_SHIFT 16
76#define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
77#define VC5_HDMI_VERTA_VAL_SHIFT 0
78#define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
79
80#define VC5_HDMI_VERTB_VSPO_SHIFT 16
81#define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
82
83#define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
84#define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
85#define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
86#define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
87
88#define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
89
90#define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
91#define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
92
93#define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0
94#define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0)
95
96#define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31)
97
98#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8
99#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)
100
101#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK VC4_MASK(7, 0)
102#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE BIT(0)
103#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE BIT(4)
104
105# define VC4_HD_M_SW_RST BIT(2)
106# define VC4_HD_M_ENABLE BIT(0)
107
108#define HSM_MIN_CLOCK_FREQ 120000000
109#define CEC_CLOCK_FREQ 40000
110
111#define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
112
113static const char * const output_format_str[] = {
114 [VC4_HDMI_OUTPUT_RGB] = "RGB",
115 [VC4_HDMI_OUTPUT_YUV420] = "YUV 4:2:0",
116 [VC4_HDMI_OUTPUT_YUV422] = "YUV 4:2:2",
117 [VC4_HDMI_OUTPUT_YUV444] = "YUV 4:4:4",
118};
119
120static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt)
121{
122 if (fmt >= ARRAY_SIZE(output_format_str))
123 return "invalid";
124
125 return output_format_str[fmt];
126}
127
128static unsigned long long
129vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
130 unsigned int bpc, enum vc4_hdmi_output_format fmt);
131
132static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi)
133{
134 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
135
136 lockdep_assert_held(&vc4_hdmi->mutex);
137
138 if (!display->is_hdmi)
139 return false;
140
141 if (!display->hdmi.scdc.supported ||
142 !display->hdmi.scdc.scrambling.supported)
143 return false;
144
145 return true;
146}
147
148static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
149 unsigned int bpc,
150 enum vc4_hdmi_output_format fmt)
151{
152 unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
153
154 return clock > HDMI_14_MAX_TMDS_CLK;
155}
156
157static bool vc4_hdmi_is_full_range(struct vc4_hdmi *vc4_hdmi,
158 struct vc4_hdmi_connector_state *vc4_state)
159{
160 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
161 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
162
163 if (vc4_state->broadcast_rgb == VC4_HDMI_BROADCAST_RGB_LIMITED)
164 return false;
165 else if (vc4_state->broadcast_rgb == VC4_HDMI_BROADCAST_RGB_FULL)
166 return true;
167
168 return !display->is_hdmi ||
169 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;
170}
171
172static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
173{
174 struct drm_debugfs_entry *entry = m->private;
175 struct vc4_hdmi *vc4_hdmi = entry->file.data;
176 struct drm_device *drm = vc4_hdmi->connector.dev;
177 struct drm_printer p = drm_seq_file_printer(m);
178 int idx;
179
180 if (!drm_dev_enter(drm, &idx))
181 return -ENODEV;
182
183 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
184 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
185 drm_print_regset32(&p, &vc4_hdmi->cec_regset);
186 drm_print_regset32(&p, &vc4_hdmi->csc_regset);
187 drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
188 drm_print_regset32(&p, &vc4_hdmi->phy_regset);
189 drm_print_regset32(&p, &vc4_hdmi->ram_regset);
190 drm_print_regset32(&p, &vc4_hdmi->rm_regset);
191
192 drm_dev_exit(idx);
193
194 return 0;
195}
196
197static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
198{
199 struct drm_device *drm = vc4_hdmi->connector.dev;
200 unsigned long flags;
201 int idx;
202
203 /*
204 * We can be called by our bind callback, when the
205 * connector->dev pointer might not be initialised yet.
206 */
207 if (drm && !drm_dev_enter(drm, &idx))
208 return;
209
210 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
211
212 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
213 udelay(1);
214 HDMI_WRITE(HDMI_M_CTL, 0);
215
216 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
217
218 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
219 VC4_HDMI_SW_RESET_HDMI |
220 VC4_HDMI_SW_RESET_FORMAT_DETECT);
221
222 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
223
224 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
225
226 if (drm)
227 drm_dev_exit(idx);
228}
229
230static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
231{
232 struct drm_device *drm = vc4_hdmi->connector.dev;
233 unsigned long flags;
234 int idx;
235
236 /*
237 * We can be called by our bind callback, when the
238 * connector->dev pointer might not be initialised yet.
239 */
240 if (drm && !drm_dev_enter(drm, &idx))
241 return;
242
243 reset_control_reset(vc4_hdmi->reset);
244
245 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
246
247 HDMI_WRITE(HDMI_DVP_CTL, 0);
248
249 HDMI_WRITE(HDMI_CLOCK_STOP,
250 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
251
252 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
253
254 if (drm)
255 drm_dev_exit(idx);
256}
257
258#ifdef CONFIG_DRM_VC4_HDMI_CEC
259static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
260{
261 struct drm_device *drm = vc4_hdmi->connector.dev;
262 unsigned long cec_rate;
263 unsigned long flags;
264 u16 clk_cnt;
265 u32 value;
266 int idx;
267
268 /*
269 * This function is called by our runtime_resume implementation
270 * and thus at bind time, when we haven't registered our
271 * connector yet and thus don't have a pointer to the DRM
272 * device.
273 */
274 if (drm && !drm_dev_enter(drm, &idx))
275 return;
276
277 cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
278
279 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
280
281 value = HDMI_READ(HDMI_CEC_CNTRL_1);
282 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
283
284 /*
285 * Set the clock divider: the hsm_clock rate and this divider
286 * setting will give a 40 kHz CEC clock.
287 */
288 clk_cnt = cec_rate / CEC_CLOCK_FREQ;
289 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
290 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
291
292 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
293
294 if (drm)
295 drm_dev_exit(idx);
296}
297#else
298static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
299#endif
300
301static int reset_pipe(struct drm_crtc *crtc,
302 struct drm_modeset_acquire_ctx *ctx)
303{
304 struct drm_atomic_state *state;
305 struct drm_crtc_state *crtc_state;
306 int ret;
307
308 state = drm_atomic_state_alloc(crtc->dev);
309 if (!state)
310 return -ENOMEM;
311
312 state->acquire_ctx = ctx;
313
314 crtc_state = drm_atomic_get_crtc_state(state, crtc);
315 if (IS_ERR(crtc_state)) {
316 ret = PTR_ERR(crtc_state);
317 goto out;
318 }
319
320 crtc_state->connectors_changed = true;
321
322 ret = drm_atomic_commit(state);
323out:
324 drm_atomic_state_put(state);
325
326 return ret;
327}
328
329static int vc4_hdmi_reset_link(struct drm_connector *connector,
330 struct drm_modeset_acquire_ctx *ctx)
331{
332 struct drm_device *drm;
333 struct vc4_hdmi *vc4_hdmi;
334 struct drm_connector_state *conn_state;
335 struct drm_crtc_state *crtc_state;
336 struct drm_crtc *crtc;
337 bool scrambling_needed;
338 u8 config;
339 int ret;
340
341 if (!connector)
342 return 0;
343
344 drm = connector->dev;
345 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx);
346 if (ret)
347 return ret;
348
349 conn_state = connector->state;
350 crtc = conn_state->crtc;
351 if (!crtc)
352 return 0;
353
354 ret = drm_modeset_lock(&crtc->mutex, ctx);
355 if (ret)
356 return ret;
357
358 crtc_state = crtc->state;
359 if (!crtc_state->active)
360 return 0;
361
362 vc4_hdmi = connector_to_vc4_hdmi(connector);
363 mutex_lock(&vc4_hdmi->mutex);
364
365 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) {
366 mutex_unlock(&vc4_hdmi->mutex);
367 return 0;
368 }
369
370 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode,
371 vc4_hdmi->output_bpc,
372 vc4_hdmi->output_format);
373 if (!scrambling_needed) {
374 mutex_unlock(&vc4_hdmi->mutex);
375 return 0;
376 }
377
378 if (conn_state->commit &&
379 !try_wait_for_completion(&conn_state->commit->hw_done)) {
380 mutex_unlock(&vc4_hdmi->mutex);
381 return 0;
382 }
383
384 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
385 if (ret < 0) {
386 drm_err(drm, "Failed to read TMDS config: %d\n", ret);
387 mutex_unlock(&vc4_hdmi->mutex);
388 return 0;
389 }
390
391 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) {
392 mutex_unlock(&vc4_hdmi->mutex);
393 return 0;
394 }
395
396 mutex_unlock(&vc4_hdmi->mutex);
397
398 /*
399 * HDMI 2.0 says that one should not send scrambled data
400 * prior to configuring the sink scrambling, and that
401 * TMDS clock/data transmission should be suspended when
402 * changing the TMDS clock rate in the sink. So let's
403 * just do a full modeset here, even though some sinks
404 * would be perfectly happy if were to just reconfigure
405 * the SCDC settings on the fly.
406 */
407 return reset_pipe(crtc, ctx);
408}
409
410static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi,
411 struct drm_modeset_acquire_ctx *ctx,
412 enum drm_connector_status status)
413{
414 struct drm_connector *connector = &vc4_hdmi->connector;
415 struct edid *edid;
416 int ret;
417
418 /*
419 * NOTE: This function should really be called with
420 * vc4_hdmi->mutex held, but doing so results in reentrancy
421 * issues since cec_s_phys_addr_from_edid might call
422 * .adap_enable, which leads to that funtion being called with
423 * our mutex held.
424 *
425 * A similar situation occurs with vc4_hdmi_reset_link() that
426 * will call into our KMS hooks if the scrambling was enabled.
427 *
428 * Concurrency isn't an issue at the moment since we don't share
429 * any state with any of the other frameworks so we can ignore
430 * the lock for now.
431 */
432
433 if (status == connector_status_disconnected) {
434 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
435 return;
436 }
437
438 edid = drm_get_edid(connector, vc4_hdmi->ddc);
439 if (!edid)
440 return;
441
442 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
443 kfree(edid);
444
445 for (;;) {
446 ret = vc4_hdmi_reset_link(connector, ctx);
447 if (ret == -EDEADLK) {
448 drm_modeset_backoff(ctx);
449 continue;
450 }
451
452 break;
453 }
454}
455
456static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector,
457 struct drm_modeset_acquire_ctx *ctx,
458 bool force)
459{
460 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
461 enum drm_connector_status status = connector_status_disconnected;
462
463 /*
464 * NOTE: This function should really take vc4_hdmi->mutex, but
465 * doing so results in reentrancy issues since
466 * vc4_hdmi_handle_hotplug() can call into other functions that
467 * would take the mutex while it's held here.
468 *
469 * Concurrency isn't an issue at the moment since we don't share
470 * any state with any of the other frameworks so we can ignore
471 * the lock for now.
472 */
473
474 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
475
476 if (vc4_hdmi->hpd_gpio) {
477 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
478 status = connector_status_connected;
479 } else {
480 if (vc4_hdmi->variant->hp_detect &&
481 vc4_hdmi->variant->hp_detect(vc4_hdmi))
482 status = connector_status_connected;
483 }
484
485 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status);
486 pm_runtime_put(&vc4_hdmi->pdev->dev);
487
488 return status;
489}
490
491static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
492{
493 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
494 struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
495 int ret = 0;
496 struct edid *edid;
497
498 /*
499 * NOTE: This function should really take vc4_hdmi->mutex, but
500 * doing so results in reentrancy issues since
501 * cec_s_phys_addr_from_edid might call .adap_enable, which
502 * leads to that funtion being called with our mutex held.
503 *
504 * Concurrency isn't an issue at the moment since we don't share
505 * any state with any of the other frameworks so we can ignore
506 * the lock for now.
507 */
508
509 edid = drm_get_edid(connector, vc4_hdmi->ddc);
510 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
511 if (!edid)
512 return 0;
513
514 drm_connector_update_edid_property(connector, edid);
515 ret = drm_add_edid_modes(connector, edid);
516 kfree(edid);
517
518 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) {
519 struct drm_device *drm = connector->dev;
520 const struct drm_display_mode *mode;
521
522 list_for_each_entry(mode, &connector->probed_modes, head) {
523 if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) {
524 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
525 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
526 }
527 }
528 }
529
530 return ret;
531}
532
533static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
534 struct drm_atomic_state *state)
535{
536 struct drm_connector_state *old_state =
537 drm_atomic_get_old_connector_state(state, connector);
538 struct vc4_hdmi_connector_state *old_vc4_state =
539 conn_state_to_vc4_hdmi_conn_state(old_state);
540 struct drm_connector_state *new_state =
541 drm_atomic_get_new_connector_state(state, connector);
542 struct vc4_hdmi_connector_state *new_vc4_state =
543 conn_state_to_vc4_hdmi_conn_state(new_state);
544 struct drm_crtc *crtc = new_state->crtc;
545
546 if (!crtc)
547 return 0;
548
549 if (old_state->tv.margins.left != new_state->tv.margins.left ||
550 old_state->tv.margins.right != new_state->tv.margins.right ||
551 old_state->tv.margins.top != new_state->tv.margins.top ||
552 old_state->tv.margins.bottom != new_state->tv.margins.bottom) {
553 struct drm_crtc_state *crtc_state;
554 int ret;
555
556 crtc_state = drm_atomic_get_crtc_state(state, crtc);
557 if (IS_ERR(crtc_state))
558 return PTR_ERR(crtc_state);
559
560 /*
561 * Strictly speaking, we should be calling
562 * drm_atomic_helper_check_planes() after our call to
563 * drm_atomic_add_affected_planes(). However, the
564 * connector atomic_check is called as part of
565 * drm_atomic_helper_check_modeset() that already
566 * happens before a call to
567 * drm_atomic_helper_check_planes() in
568 * drm_atomic_helper_check().
569 */
570 ret = drm_atomic_add_affected_planes(state, crtc);
571 if (ret)
572 return ret;
573 }
574
575 if (old_state->colorspace != new_state->colorspace ||
576 old_vc4_state->broadcast_rgb != new_vc4_state->broadcast_rgb ||
577 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
578 struct drm_crtc_state *crtc_state;
579
580 crtc_state = drm_atomic_get_crtc_state(state, crtc);
581 if (IS_ERR(crtc_state))
582 return PTR_ERR(crtc_state);
583
584 crtc_state->mode_changed = true;
585 }
586
587 return 0;
588}
589
590static int vc4_hdmi_connector_get_property(struct drm_connector *connector,
591 const struct drm_connector_state *state,
592 struct drm_property *property,
593 uint64_t *val)
594{
595 struct drm_device *drm = connector->dev;
596 struct vc4_hdmi *vc4_hdmi =
597 connector_to_vc4_hdmi(connector);
598 const struct vc4_hdmi_connector_state *vc4_conn_state =
599 conn_state_to_vc4_hdmi_conn_state(state);
600
601 if (property == vc4_hdmi->broadcast_rgb_property) {
602 *val = vc4_conn_state->broadcast_rgb;
603 } else {
604 drm_dbg(drm, "Unknown property [PROP:%d:%s]\n",
605 property->base.id, property->name);
606 return -EINVAL;
607 }
608
609 return 0;
610}
611
612static int vc4_hdmi_connector_set_property(struct drm_connector *connector,
613 struct drm_connector_state *state,
614 struct drm_property *property,
615 uint64_t val)
616{
617 struct drm_device *drm = connector->dev;
618 struct vc4_hdmi *vc4_hdmi =
619 connector_to_vc4_hdmi(connector);
620 struct vc4_hdmi_connector_state *vc4_conn_state =
621 conn_state_to_vc4_hdmi_conn_state(state);
622
623 if (property == vc4_hdmi->broadcast_rgb_property) {
624 vc4_conn_state->broadcast_rgb = val;
625 return 0;
626 }
627
628 drm_dbg(drm, "Unknown property [PROP:%d:%s]\n",
629 property->base.id, property->name);
630 return -EINVAL;
631}
632
633static void vc4_hdmi_connector_reset(struct drm_connector *connector)
634{
635 struct vc4_hdmi_connector_state *old_state =
636 conn_state_to_vc4_hdmi_conn_state(connector->state);
637 struct vc4_hdmi_connector_state *new_state =
638 kzalloc(sizeof(*new_state), GFP_KERNEL);
639
640 if (connector->state)
641 __drm_atomic_helper_connector_destroy_state(connector->state);
642
643 kfree(old_state);
644 __drm_atomic_helper_connector_reset(connector, &new_state->base);
645
646 if (!new_state)
647 return;
648
649 new_state->base.max_bpc = 8;
650 new_state->base.max_requested_bpc = 8;
651 new_state->output_format = VC4_HDMI_OUTPUT_RGB;
652 new_state->broadcast_rgb = VC4_HDMI_BROADCAST_RGB_AUTO;
653 drm_atomic_helper_connector_tv_margins_reset(connector);
654}
655
656static struct drm_connector_state *
657vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
658{
659 struct drm_connector_state *conn_state = connector->state;
660 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
661 struct vc4_hdmi_connector_state *new_state;
662
663 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
664 if (!new_state)
665 return NULL;
666
667 new_state->tmds_char_rate = vc4_state->tmds_char_rate;
668 new_state->output_bpc = vc4_state->output_bpc;
669 new_state->output_format = vc4_state->output_format;
670 new_state->broadcast_rgb = vc4_state->broadcast_rgb;
671 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
672
673 return &new_state->base;
674}
675
676static void vc4_hdmi_connector_destroy_state(struct drm_connector *connector,
677 struct drm_connector_state *state)
678{
679 struct vc4_hdmi_connector_state *vc4_state =
680 conn_state_to_vc4_hdmi_conn_state(state);
681
682 __drm_atomic_helper_connector_destroy_state(state);
683 kfree(vc4_state);
684}
685
686static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
687 .fill_modes = drm_helper_probe_single_connector_modes,
688 .reset = vc4_hdmi_connector_reset,
689 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
690 .atomic_destroy_state = vc4_hdmi_connector_destroy_state,
691 .atomic_get_property = vc4_hdmi_connector_get_property,
692 .atomic_set_property = vc4_hdmi_connector_set_property,
693};
694
695static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
696 .detect_ctx = vc4_hdmi_connector_detect_ctx,
697 .get_modes = vc4_hdmi_connector_get_modes,
698 .atomic_check = vc4_hdmi_connector_atomic_check,
699};
700
701static const struct drm_prop_enum_list broadcast_rgb_names[] = {
702 { VC4_HDMI_BROADCAST_RGB_AUTO, "Automatic" },
703 { VC4_HDMI_BROADCAST_RGB_FULL, "Full" },
704 { VC4_HDMI_BROADCAST_RGB_LIMITED, "Limited 16:235" },
705};
706
707static void
708vc4_hdmi_attach_broadcast_rgb_property(struct drm_device *dev,
709 struct vc4_hdmi *vc4_hdmi)
710{
711 struct drm_property *prop = vc4_hdmi->broadcast_rgb_property;
712
713 if (!prop) {
714 prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
715 "Broadcast RGB",
716 broadcast_rgb_names,
717 ARRAY_SIZE(broadcast_rgb_names));
718 if (!prop)
719 return;
720
721 vc4_hdmi->broadcast_rgb_property = prop;
722 }
723
724 drm_object_attach_property(&vc4_hdmi->connector.base, prop,
725 VC4_HDMI_BROADCAST_RGB_AUTO);
726}
727
728static int vc4_hdmi_connector_init(struct drm_device *dev,
729 struct vc4_hdmi *vc4_hdmi)
730{
731 struct drm_connector *connector = &vc4_hdmi->connector;
732 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
733 int ret;
734
735 ret = drmm_connector_init(dev, connector,
736 &vc4_hdmi_connector_funcs,
737 DRM_MODE_CONNECTOR_HDMIA,
738 vc4_hdmi->ddc);
739 if (ret)
740 return ret;
741
742 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
743
744 /*
745 * Some of the properties below require access to state, like bpc.
746 * Allocate some default initial connector state with our reset helper.
747 */
748 if (connector->funcs->reset)
749 connector->funcs->reset(connector);
750
751 /* Create and attach TV margin props to this connector. */
752 ret = drm_mode_create_tv_margin_properties(dev);
753 if (ret)
754 return ret;
755
756 ret = drm_mode_create_hdmi_colorspace_property(connector, 0);
757 if (ret)
758 return ret;
759
760 drm_connector_attach_colorspace_property(connector);
761 drm_connector_attach_tv_margin_properties(connector);
762 drm_connector_attach_max_bpc_property(connector, 8, 12);
763
764 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
765 DRM_CONNECTOR_POLL_DISCONNECT);
766
767 connector->interlace_allowed = 1;
768 connector->doublescan_allowed = 0;
769 connector->stereo_allowed = 1;
770
771 if (vc4_hdmi->variant->supports_hdr)
772 drm_connector_attach_hdr_output_metadata_property(connector);
773
774 vc4_hdmi_attach_broadcast_rgb_property(dev, vc4_hdmi);
775
776 drm_connector_attach_encoder(connector, encoder);
777
778 return 0;
779}
780
781static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
782 enum hdmi_infoframe_type type,
783 bool poll)
784{
785 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
786 struct drm_device *drm = vc4_hdmi->connector.dev;
787 u32 packet_id = type - 0x80;
788 unsigned long flags;
789 int ret = 0;
790 int idx;
791
792 if (!drm_dev_enter(drm, &idx))
793 return -ENODEV;
794
795 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
796 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
797 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
798 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
799
800 if (poll) {
801 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
802 BIT(packet_id)), 100);
803 }
804
805 drm_dev_exit(idx);
806 return ret;
807}
808
809static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
810 union hdmi_infoframe *frame)
811{
812 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
813 struct drm_device *drm = vc4_hdmi->connector.dev;
814 u32 packet_id = frame->any.type - 0x80;
815 const struct vc4_hdmi_register *ram_packet_start =
816 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
817 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
818 u32 packet_reg_next = ram_packet_start->offset +
819 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
820 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
821 ram_packet_start->reg);
822 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
823 unsigned long flags;
824 ssize_t len, i;
825 int ret;
826 int idx;
827
828 if (!drm_dev_enter(drm, &idx))
829 return;
830
831 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
832 VC4_HDMI_RAM_PACKET_ENABLE),
833 "Packet RAM has to be on to store the packet.");
834
835 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
836 if (len < 0)
837 goto out;
838
839 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
840 if (ret) {
841 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
842 goto out;
843 }
844
845 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
846
847 for (i = 0; i < len; i += 7) {
848 writel(buffer[i + 0] << 0 |
849 buffer[i + 1] << 8 |
850 buffer[i + 2] << 16,
851 base + packet_reg);
852 packet_reg += 4;
853
854 writel(buffer[i + 3] << 0 |
855 buffer[i + 4] << 8 |
856 buffer[i + 5] << 16 |
857 buffer[i + 6] << 24,
858 base + packet_reg);
859 packet_reg += 4;
860 }
861
862 /*
863 * clear remainder of packet ram as it's included in the
864 * infoframe and triggers a checksum error on hdmi analyser
865 */
866 for (; packet_reg < packet_reg_next; packet_reg += 4)
867 writel(0, base + packet_reg);
868
869 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
870 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
871
872 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
873
874 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
875 BIT(packet_id)), 100);
876 if (ret)
877 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
878
879out:
880 drm_dev_exit(idx);
881}
882
883static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
884 enum vc4_hdmi_output_format fmt)
885{
886 switch (fmt) {
887 case VC4_HDMI_OUTPUT_RGB:
888 frame->colorspace = HDMI_COLORSPACE_RGB;
889 break;
890
891 case VC4_HDMI_OUTPUT_YUV420:
892 frame->colorspace = HDMI_COLORSPACE_YUV420;
893 break;
894
895 case VC4_HDMI_OUTPUT_YUV422:
896 frame->colorspace = HDMI_COLORSPACE_YUV422;
897 break;
898
899 case VC4_HDMI_OUTPUT_YUV444:
900 frame->colorspace = HDMI_COLORSPACE_YUV444;
901 break;
902
903 default:
904 break;
905 }
906}
907
908static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
909{
910 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
911 struct drm_connector *connector = &vc4_hdmi->connector;
912 struct drm_connector_state *cstate = connector->state;
913 struct vc4_hdmi_connector_state *vc4_state =
914 conn_state_to_vc4_hdmi_conn_state(cstate);
915 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
916 union hdmi_infoframe frame;
917 int ret;
918
919 lockdep_assert_held(&vc4_hdmi->mutex);
920
921 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
922 connector, mode);
923 if (ret < 0) {
924 DRM_ERROR("couldn't fill AVI infoframe\n");
925 return;
926 }
927
928 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
929 connector, mode,
930 vc4_hdmi_is_full_range(vc4_hdmi, vc4_state) ?
931 HDMI_QUANTIZATION_RANGE_FULL :
932 HDMI_QUANTIZATION_RANGE_LIMITED);
933 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate);
934 vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format);
935 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
936
937 vc4_hdmi_write_infoframe(encoder, &frame);
938}
939
940static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
941{
942 union hdmi_infoframe frame;
943 int ret;
944
945 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
946 if (ret < 0) {
947 DRM_ERROR("couldn't fill SPD infoframe\n");
948 return;
949 }
950
951 frame.spd.sdi = HDMI_SPD_SDI_PC;
952
953 vc4_hdmi_write_infoframe(encoder, &frame);
954}
955
956static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
957{
958 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
959 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
960 union hdmi_infoframe frame;
961
962 memcpy(&frame.audio, audio, sizeof(*audio));
963
964 if (vc4_hdmi->packet_ram_enabled)
965 vc4_hdmi_write_infoframe(encoder, &frame);
966}
967
968static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
969{
970 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
971 struct drm_connector *connector = &vc4_hdmi->connector;
972 struct drm_connector_state *conn_state = connector->state;
973 union hdmi_infoframe frame;
974
975 lockdep_assert_held(&vc4_hdmi->mutex);
976
977 if (!vc4_hdmi->variant->supports_hdr)
978 return;
979
980 if (!conn_state->hdr_output_metadata)
981 return;
982
983 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
984 return;
985
986 vc4_hdmi_write_infoframe(encoder, &frame);
987}
988
989static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
990{
991 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
992
993 lockdep_assert_held(&vc4_hdmi->mutex);
994
995 vc4_hdmi_set_avi_infoframe(encoder);
996 vc4_hdmi_set_spd_infoframe(encoder);
997 /*
998 * If audio was streaming, then we need to reenabled the audio
999 * infoframe here during encoder_enable.
1000 */
1001 if (vc4_hdmi->audio.streaming)
1002 vc4_hdmi_set_audio_infoframe(encoder);
1003
1004 vc4_hdmi_set_hdr_infoframe(encoder);
1005}
1006
1007#define SCRAMBLING_POLLING_DELAY_MS 1000
1008
1009static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
1010{
1011 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1012 struct drm_connector *connector = &vc4_hdmi->connector;
1013 struct drm_device *drm = connector->dev;
1014 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1015 unsigned long flags;
1016 int idx;
1017
1018 lockdep_assert_held(&vc4_hdmi->mutex);
1019
1020 if (!vc4_hdmi_supports_scrambling(vc4_hdmi))
1021 return;
1022
1023 if (!vc4_hdmi_mode_needs_scrambling(mode,
1024 vc4_hdmi->output_bpc,
1025 vc4_hdmi->output_format))
1026 return;
1027
1028 if (!drm_dev_enter(drm, &idx))
1029 return;
1030
1031 drm_scdc_set_high_tmds_clock_ratio(connector, true);
1032 drm_scdc_set_scrambling(connector, true);
1033
1034 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1035 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
1036 VC5_HDMI_SCRAMBLER_CTL_ENABLE);
1037 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1038
1039 drm_dev_exit(idx);
1040
1041 vc4_hdmi->scdc_enabled = true;
1042
1043 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
1044 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
1045}
1046
1047static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
1048{
1049 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1050 struct drm_connector *connector = &vc4_hdmi->connector;
1051 struct drm_device *drm = connector->dev;
1052 unsigned long flags;
1053 int idx;
1054
1055 lockdep_assert_held(&vc4_hdmi->mutex);
1056
1057 if (!vc4_hdmi->scdc_enabled)
1058 return;
1059
1060 vc4_hdmi->scdc_enabled = false;
1061
1062 if (delayed_work_pending(&vc4_hdmi->scrambling_work))
1063 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
1064
1065 if (!drm_dev_enter(drm, &idx))
1066 return;
1067
1068 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1069 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
1070 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
1071 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1072
1073 drm_scdc_set_scrambling(connector, false);
1074 drm_scdc_set_high_tmds_clock_ratio(connector, false);
1075
1076 drm_dev_exit(idx);
1077}
1078
1079static void vc4_hdmi_scrambling_wq(struct work_struct *work)
1080{
1081 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
1082 struct vc4_hdmi,
1083 scrambling_work);
1084 struct drm_connector *connector = &vc4_hdmi->connector;
1085
1086 if (drm_scdc_get_scrambling_status(connector))
1087 return;
1088
1089 drm_scdc_set_high_tmds_clock_ratio(connector, true);
1090 drm_scdc_set_scrambling(connector, true);
1091
1092 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
1093 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
1094}
1095
1096static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
1097 struct drm_atomic_state *state)
1098{
1099 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1100 struct drm_device *drm = vc4_hdmi->connector.dev;
1101 unsigned long flags;
1102 int idx;
1103
1104 mutex_lock(&vc4_hdmi->mutex);
1105
1106 vc4_hdmi->packet_ram_enabled = false;
1107
1108 if (!drm_dev_enter(drm, &idx))
1109 goto out;
1110
1111 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1112
1113 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
1114
1115 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
1116
1117 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1118
1119 mdelay(1);
1120
1121 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1122 HDMI_WRITE(HDMI_VID_CTL,
1123 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
1124 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1125
1126 vc4_hdmi_disable_scrambling(encoder);
1127
1128 drm_dev_exit(idx);
1129
1130out:
1131 mutex_unlock(&vc4_hdmi->mutex);
1132}
1133
1134static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
1135 struct drm_atomic_state *state)
1136{
1137 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1138 struct drm_device *drm = vc4_hdmi->connector.dev;
1139 unsigned long flags;
1140 int ret;
1141 int idx;
1142
1143 mutex_lock(&vc4_hdmi->mutex);
1144
1145 if (!drm_dev_enter(drm, &idx))
1146 goto out;
1147
1148 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1149 HDMI_WRITE(HDMI_VID_CTL,
1150 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
1151 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1152
1153 if (vc4_hdmi->variant->phy_disable)
1154 vc4_hdmi->variant->phy_disable(vc4_hdmi);
1155
1156 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
1157 clk_disable_unprepare(vc4_hdmi->pixel_clock);
1158
1159 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
1160 if (ret < 0)
1161 DRM_ERROR("Failed to release power domain: %d\n", ret);
1162
1163 drm_dev_exit(idx);
1164
1165out:
1166 mutex_unlock(&vc4_hdmi->mutex);
1167}
1168
1169static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1170 struct drm_connector_state *state,
1171 const struct drm_display_mode *mode)
1172{
1173 struct vc4_hdmi_connector_state *vc4_state =
1174 conn_state_to_vc4_hdmi_conn_state(state);
1175 struct drm_device *drm = vc4_hdmi->connector.dev;
1176 unsigned long flags;
1177 u32 csc_ctl;
1178 int idx;
1179
1180 if (!drm_dev_enter(drm, &idx))
1181 return;
1182
1183 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1184
1185 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
1186 VC4_HD_CSC_CTL_ORDER);
1187
1188 if (!vc4_hdmi_is_full_range(vc4_hdmi, vc4_state)) {
1189 /* CEA VICs other than #1 requre limited range RGB
1190 * output unless overridden by an AVI infoframe.
1191 * Apply a colorspace conversion to squash 0-255 down
1192 * to 16-235. The matrix here is:
1193 *
1194 * [ 0 0 0.8594 16]
1195 * [ 0 0.8594 0 16]
1196 * [ 0.8594 0 0 16]
1197 * [ 0 0 0 1]
1198 */
1199 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
1200 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
1201 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1202 VC4_HD_CSC_CTL_MODE);
1203
1204 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
1205 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
1206 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
1207 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
1208 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
1209 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
1210 }
1211
1212 /* The RGB order applies even when CSC is disabled. */
1213 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1214
1215 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1216
1217 drm_dev_exit(idx);
1218}
1219
1220/*
1221 * Matrices for (internal) RGB to RGB output.
1222 *
1223 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1224 */
1225static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = {
1226 {
1227 /*
1228 * Full range - unity
1229 *
1230 * [ 1 0 0 0]
1231 * [ 0 1 0 0]
1232 * [ 0 0 1 0]
1233 */
1234 { 0x2000, 0x0000, 0x0000, 0x0000 },
1235 { 0x0000, 0x2000, 0x0000, 0x0000 },
1236 { 0x0000, 0x0000, 0x2000, 0x0000 },
1237 },
1238 {
1239 /*
1240 * Limited range
1241 *
1242 * CEA VICs other than #1 require limited range RGB
1243 * output unless overridden by an AVI infoframe. Apply a
1244 * colorspace conversion to squash 0-255 down to 16-235.
1245 * The matrix here is:
1246 *
1247 * [ 0.8594 0 0 16]
1248 * [ 0 0.8594 0 16]
1249 * [ 0 0 0.8594 16]
1250 */
1251 { 0x1b80, 0x0000, 0x0000, 0x0400 },
1252 { 0x0000, 0x1b80, 0x0000, 0x0400 },
1253 { 0x0000, 0x0000, 0x1b80, 0x0400 },
1254 },
1255};
1256
1257/*
1258 * Conversion between Full Range RGB and YUV using the BT.601 Colorspace
1259 *
1260 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1261 */
1262static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = {
1263 {
1264 /*
1265 * Full Range
1266 *
1267 * [ 0.299000 0.587000 0.114000 0 ]
1268 * [ -0.168736 -0.331264 0.500000 128 ]
1269 * [ 0.500000 -0.418688 -0.081312 128 ]
1270 */
1271 { 0x0991, 0x12c9, 0x03a6, 0x0000 },
1272 { 0xfa9b, 0xf567, 0x1000, 0x2000 },
1273 { 0x1000, 0xf29b, 0xfd67, 0x2000 },
1274 },
1275 {
1276 /* Limited Range
1277 *
1278 * [ 0.255785 0.502160 0.097523 16 ]
1279 * [ -0.147644 -0.289856 0.437500 128 ]
1280 * [ 0.437500 -0.366352 -0.071148 128 ]
1281 */
1282 { 0x082f, 0x1012, 0x031f, 0x0400 },
1283 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1284 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1285 },
1286};
1287
1288/*
1289 * Conversion between Full Range RGB and YUV using the BT.709 Colorspace
1290 *
1291 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1292 */
1293static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = {
1294 {
1295 /*
1296 * Full Range
1297 *
1298 * [ 0.212600 0.715200 0.072200 0 ]
1299 * [ -0.114572 -0.385428 0.500000 128 ]
1300 * [ 0.500000 -0.454153 -0.045847 128 ]
1301 */
1302 { 0x06ce, 0x16e3, 0x024f, 0x0000 },
1303 { 0xfc56, 0xf3ac, 0x1000, 0x2000 },
1304 { 0x1000, 0xf179, 0xfe89, 0x2000 },
1305 },
1306 {
1307 /*
1308 * Limited Range
1309 *
1310 * [ 0.181906 0.611804 0.061758 16 ]
1311 * [ -0.100268 -0.337232 0.437500 128 ]
1312 * [ 0.437500 -0.397386 -0.040114 128 ]
1313 */
1314 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1315 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1316 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1317 },
1318};
1319
1320/*
1321 * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace
1322 *
1323 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1324 */
1325static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = {
1326 {
1327 /*
1328 * Full Range
1329 *
1330 * [ 0.262700 0.678000 0.059300 0 ]
1331 * [ -0.139630 -0.360370 0.500000 128 ]
1332 * [ 0.500000 -0.459786 -0.040214 128 ]
1333 */
1334 { 0x0868, 0x15b2, 0x01e6, 0x0000 },
1335 { 0xfb89, 0xf479, 0x1000, 0x2000 },
1336 { 0x1000, 0xf14a, 0xfeb8, 0x2000 },
1337 },
1338 {
1339 /* Limited Range
1340 *
1341 * [ 0.224732 0.580008 0.050729 16 ]
1342 * [ -0.122176 -0.315324 0.437500 128 ]
1343 * [ 0.437500 -0.402312 -0.035188 128 ]
1344 */
1345 { 0x082f, 0x1012, 0x031f, 0x0400 },
1346 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1347 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1348 },
1349};
1350
1351static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
1352 const u16 coeffs[3][4])
1353{
1354 lockdep_assert_held(&vc4_hdmi->hw_lock);
1355
1356 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
1357 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
1358 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
1359 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
1360 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
1361 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
1362}
1363
1364static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi,
1365 const u16 coeffs[3][4])
1366{
1367 lockdep_assert_held(&vc4_hdmi->hw_lock);
1368
1369 /* YUV444 needs the CSC matrices using the channels in a different order */
1370 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[1][1] << 16) | coeffs[1][0]);
1371 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[1][3] << 16) | coeffs[1][2]);
1372 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[2][1] << 16) | coeffs[2][0]);
1373 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[2][3] << 16) | coeffs[2][2]);
1374 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[0][1] << 16) | coeffs[0][0]);
1375 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[0][3] << 16) | coeffs[0][2]);
1376}
1377
1378static const u16
1379(*vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi *vc4_hdmi, u32 colorspace, bool limited))[4]
1380{
1381 switch (colorspace) {
1382 case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC:
1383 case DRM_MODE_COLORIMETRY_XVYCC_601:
1384 case DRM_MODE_COLORIMETRY_SYCC_601:
1385 case DRM_MODE_COLORIMETRY_OPYCC_601:
1386 case DRM_MODE_COLORIMETRY_BT601_YCC:
1387 return vc5_hdmi_csc_full_rgb_to_yuv_bt601[limited];
1388
1389 default:
1390 case DRM_MODE_COLORIMETRY_NO_DATA:
1391 case DRM_MODE_COLORIMETRY_BT709_YCC:
1392 case DRM_MODE_COLORIMETRY_XVYCC_709:
1393 case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED:
1394 case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT:
1395 return vc5_hdmi_csc_full_rgb_to_yuv_bt709[limited];
1396
1397 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1398 case DRM_MODE_COLORIMETRY_BT2020_YCC:
1399 case DRM_MODE_COLORIMETRY_BT2020_RGB:
1400 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1401 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1402 return vc5_hdmi_csc_full_rgb_to_yuv_bt2020[limited];
1403 }
1404}
1405
1406static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1407 struct drm_connector_state *state,
1408 const struct drm_display_mode *mode)
1409{
1410 struct drm_device *drm = vc4_hdmi->connector.dev;
1411 struct vc4_hdmi_connector_state *vc4_state =
1412 conn_state_to_vc4_hdmi_conn_state(state);
1413 unsigned int lim_range = vc4_hdmi_is_full_range(vc4_hdmi, vc4_state) ? 0 : 1;
1414 unsigned long flags;
1415 const u16 (*csc)[4];
1416 u32 if_cfg = 0;
1417 u32 if_xbar = 0x543210;
1418 u32 csc_chan_ctl = 0;
1419 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1420 VC5_MT_CP_CSC_CTL_MODE);
1421 int idx;
1422
1423 if (!drm_dev_enter(drm, &idx))
1424 return;
1425
1426 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1427
1428 switch (vc4_state->output_format) {
1429 case VC4_HDMI_OUTPUT_YUV444:
1430 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range);
1431
1432 vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc);
1433 break;
1434
1435 case VC4_HDMI_OUTPUT_YUV422:
1436 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range);
1437
1438 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1439 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
1440 VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
1441 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
1442
1443 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1444 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
1445
1446 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1447 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
1448
1449 vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc);
1450 break;
1451
1452 case VC4_HDMI_OUTPUT_RGB:
1453 if_xbar = 0x354021;
1454
1455 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_rgb[lim_range]);
1456 break;
1457
1458 default:
1459 break;
1460 }
1461
1462 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
1463 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
1464 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
1465 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1466
1467 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1468
1469 drm_dev_exit(idx);
1470}
1471
1472static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1473 struct drm_connector_state *state,
1474 const struct drm_display_mode *mode)
1475{
1476 struct drm_device *drm = vc4_hdmi->connector.dev;
1477 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1478 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1479 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1480 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1481 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1482 VC4_HDMI_VERTA_VSP) |
1483 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1484 VC4_HDMI_VERTA_VFP) |
1485 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1486 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1487 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1488 interlaced,
1489 VC4_HDMI_VERTB_VBP));
1490 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1491 VC4_SET_FIELD(mode->crtc_vtotal -
1492 mode->crtc_vsync_end,
1493 VC4_HDMI_VERTB_VBP));
1494 unsigned long flags;
1495 u32 reg;
1496 int idx;
1497
1498 if (!drm_dev_enter(drm, &idx))
1499 return;
1500
1501 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1502
1503 HDMI_WRITE(HDMI_HORZA,
1504 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1505 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1506 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1507 VC4_HDMI_HORZA_HAP));
1508
1509 HDMI_WRITE(HDMI_HORZB,
1510 VC4_SET_FIELD((mode->htotal -
1511 mode->hsync_end) * pixel_rep,
1512 VC4_HDMI_HORZB_HBP) |
1513 VC4_SET_FIELD((mode->hsync_end -
1514 mode->hsync_start) * pixel_rep,
1515 VC4_HDMI_HORZB_HSP) |
1516 VC4_SET_FIELD((mode->hsync_start -
1517 mode->hdisplay) * pixel_rep,
1518 VC4_HDMI_HORZB_HFP));
1519
1520 HDMI_WRITE(HDMI_VERTA0, verta);
1521 HDMI_WRITE(HDMI_VERTA1, verta);
1522
1523 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1524 HDMI_WRITE(HDMI_VERTB1, vertb);
1525
1526 reg = HDMI_READ(HDMI_MISC_CONTROL);
1527 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1528 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1529 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1530
1531 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1532
1533 drm_dev_exit(idx);
1534}
1535
1536static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1537 struct drm_connector_state *state,
1538 const struct drm_display_mode *mode)
1539{
1540 struct drm_device *drm = vc4_hdmi->connector.dev;
1541 const struct vc4_hdmi_connector_state *vc4_state =
1542 conn_state_to_vc4_hdmi_conn_state(state);
1543 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1544 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1545 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1546 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1547 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1548 VC5_HDMI_VERTA_VSP) |
1549 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1550 VC5_HDMI_VERTA_VFP) |
1551 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1552 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1553 VC5_HDMI_VERTB_VSPO) |
1554 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1555 interlaced,
1556 VC4_HDMI_VERTB_VBP));
1557 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1558 VC4_SET_FIELD(mode->crtc_vtotal -
1559 mode->crtc_vsync_end,
1560 VC4_HDMI_VERTB_VBP));
1561 unsigned long flags;
1562 unsigned char gcp;
1563 u32 reg;
1564 int idx;
1565
1566 if (!drm_dev_enter(drm, &idx))
1567 return;
1568
1569 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1570
1571 HDMI_WRITE(HDMI_HORZA,
1572 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1573 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1574 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1575 VC5_HDMI_HORZA_HAP) |
1576 VC4_SET_FIELD((mode->hsync_start -
1577 mode->hdisplay) * pixel_rep,
1578 VC5_HDMI_HORZA_HFP));
1579
1580 HDMI_WRITE(HDMI_HORZB,
1581 VC4_SET_FIELD((mode->htotal -
1582 mode->hsync_end) * pixel_rep,
1583 VC5_HDMI_HORZB_HBP) |
1584 VC4_SET_FIELD((mode->hsync_end -
1585 mode->hsync_start) * pixel_rep,
1586 VC5_HDMI_HORZB_HSP));
1587
1588 HDMI_WRITE(HDMI_VERTA0, verta);
1589 HDMI_WRITE(HDMI_VERTA1, verta);
1590
1591 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1592 HDMI_WRITE(HDMI_VERTB1, vertb);
1593
1594 switch (vc4_state->output_bpc) {
1595 case 12:
1596 gcp = 6;
1597 break;
1598 case 10:
1599 gcp = 5;
1600 break;
1601 case 8:
1602 default:
1603 gcp = 0;
1604 break;
1605 }
1606
1607 /*
1608 * YCC422 is always 36-bit and not considered deep colour so
1609 * doesn't signal in GCP.
1610 */
1611 if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) {
1612 gcp = 0;
1613 }
1614
1615 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1616 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1617 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1618 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1619 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1620 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1621
1622 reg = HDMI_READ(HDMI_GCP_WORD_1);
1623 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1624 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1625 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK;
1626 reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE;
1627 HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1628
1629 reg = HDMI_READ(HDMI_GCP_CONFIG);
1630 reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1631 HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1632
1633 reg = HDMI_READ(HDMI_MISC_CONTROL);
1634 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1635 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1636 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1637
1638 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1639
1640 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1641
1642 drm_dev_exit(idx);
1643}
1644
1645static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1646{
1647 struct drm_device *drm = vc4_hdmi->connector.dev;
1648 unsigned long flags;
1649 u32 drift;
1650 int ret;
1651 int idx;
1652
1653 if (!drm_dev_enter(drm, &idx))
1654 return;
1655
1656 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1657
1658 drift = HDMI_READ(HDMI_FIFO_CTL);
1659 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1660
1661 HDMI_WRITE(HDMI_FIFO_CTL,
1662 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1663 HDMI_WRITE(HDMI_FIFO_CTL,
1664 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1665
1666 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1667
1668 usleep_range(1000, 1100);
1669
1670 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1671
1672 HDMI_WRITE(HDMI_FIFO_CTL,
1673 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1674 HDMI_WRITE(HDMI_FIFO_CTL,
1675 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1676
1677 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1678
1679 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1680 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1681 WARN_ONCE(ret, "Timeout waiting for "
1682 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1683
1684 drm_dev_exit(idx);
1685}
1686
1687static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1688 struct drm_atomic_state *state)
1689{
1690 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1691 struct drm_device *drm = vc4_hdmi->connector.dev;
1692 struct drm_connector *connector = &vc4_hdmi->connector;
1693 struct drm_connector_state *conn_state =
1694 drm_atomic_get_new_connector_state(state, connector);
1695 struct vc4_hdmi_connector_state *vc4_conn_state =
1696 conn_state_to_vc4_hdmi_conn_state(conn_state);
1697 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1698 unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate;
1699 unsigned long bvb_rate, hsm_rate;
1700 unsigned long flags;
1701 int ret;
1702 int idx;
1703
1704 mutex_lock(&vc4_hdmi->mutex);
1705
1706 if (!drm_dev_enter(drm, &idx))
1707 goto out;
1708
1709 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1710 if (ret < 0) {
1711 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1712 goto err_dev_exit;
1713 }
1714
1715 /*
1716 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1717 * be faster than pixel clock, infinitesimally faster, tested in
1718 * simulation. Otherwise, exact value is unimportant for HDMI
1719 * operation." This conflicts with bcm2835's vc4 documentation, which
1720 * states HSM's clock has to be at least 108% of the pixel clock.
1721 *
1722 * Real life tests reveal that vc4's firmware statement holds up, and
1723 * users are able to use pixel clocks closer to HSM's, namely for
1724 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1725 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1726 * 162MHz.
1727 *
1728 * Additionally, the AXI clock needs to be at least 25% of
1729 * pixel clock, but HSM ends up being the limiting factor.
1730 */
1731 hsm_rate = max_t(unsigned long,
1732 HSM_MIN_CLOCK_FREQ,
1733 (tmds_char_rate / 100) * 101);
1734 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1735 if (ret) {
1736 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1737 goto err_put_runtime_pm;
1738 }
1739
1740 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1741 if (ret) {
1742 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1743 goto err_put_runtime_pm;
1744 }
1745
1746 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1747 if (ret) {
1748 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1749 goto err_put_runtime_pm;
1750 }
1751
1752
1753 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1754
1755 if (tmds_char_rate > 297000000)
1756 bvb_rate = 300000000;
1757 else if (tmds_char_rate > 148500000)
1758 bvb_rate = 150000000;
1759 else
1760 bvb_rate = 75000000;
1761
1762 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1763 if (ret) {
1764 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1765 goto err_disable_pixel_clock;
1766 }
1767
1768 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1769 if (ret) {
1770 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1771 goto err_disable_pixel_clock;
1772 }
1773
1774 if (vc4_hdmi->variant->phy_init)
1775 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1776
1777 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1778
1779 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1780 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1781 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1782 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1783
1784 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1785
1786 if (vc4_hdmi->variant->set_timings)
1787 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1788
1789 drm_dev_exit(idx);
1790
1791 mutex_unlock(&vc4_hdmi->mutex);
1792
1793 return;
1794
1795err_disable_pixel_clock:
1796 clk_disable_unprepare(vc4_hdmi->pixel_clock);
1797err_put_runtime_pm:
1798 pm_runtime_put(&vc4_hdmi->pdev->dev);
1799err_dev_exit:
1800 drm_dev_exit(idx);
1801out:
1802 mutex_unlock(&vc4_hdmi->mutex);
1803 return;
1804}
1805
1806static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1807 struct drm_atomic_state *state)
1808{
1809 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1810 struct drm_device *drm = vc4_hdmi->connector.dev;
1811 struct drm_connector *connector = &vc4_hdmi->connector;
1812 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1813 struct drm_connector_state *conn_state =
1814 drm_atomic_get_new_connector_state(state, connector);
1815 unsigned long flags;
1816 int idx;
1817
1818 mutex_lock(&vc4_hdmi->mutex);
1819
1820 if (!drm_dev_enter(drm, &idx))
1821 goto out;
1822
1823 if (vc4_hdmi->variant->csc_setup)
1824 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1825
1826 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1827 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1828 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1829
1830 drm_dev_exit(idx);
1831
1832out:
1833 mutex_unlock(&vc4_hdmi->mutex);
1834}
1835
1836static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1837 struct drm_atomic_state *state)
1838{
1839 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1840 struct drm_device *drm = vc4_hdmi->connector.dev;
1841 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1842 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1843 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1844 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1845 unsigned long flags;
1846 int ret;
1847 int idx;
1848
1849 mutex_lock(&vc4_hdmi->mutex);
1850
1851 if (!drm_dev_enter(drm, &idx))
1852 goto out;
1853
1854 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1855
1856 HDMI_WRITE(HDMI_VID_CTL,
1857 VC4_HD_VID_CTL_ENABLE |
1858 VC4_HD_VID_CTL_CLRRGB |
1859 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1860 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1861 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1862 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1863
1864 HDMI_WRITE(HDMI_VID_CTL,
1865 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1866
1867 if (display->is_hdmi) {
1868 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1869 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1870 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1871
1872 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1873
1874 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1875 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1876 WARN_ONCE(ret, "Timeout waiting for "
1877 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1878 } else {
1879 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1880 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1881 ~(VC4_HDMI_RAM_PACKET_ENABLE));
1882 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1883 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1884 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1885
1886 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1887
1888 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1889 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1890 WARN_ONCE(ret, "Timeout waiting for "
1891 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1892 }
1893
1894 if (display->is_hdmi) {
1895 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1896
1897 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1898 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1899
1900 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1901 VC4_HDMI_RAM_PACKET_ENABLE);
1902
1903 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1904 vc4_hdmi->packet_ram_enabled = true;
1905
1906 vc4_hdmi_set_infoframes(encoder);
1907 }
1908
1909 vc4_hdmi_recenter_fifo(vc4_hdmi);
1910 vc4_hdmi_enable_scrambling(encoder);
1911
1912 drm_dev_exit(idx);
1913
1914out:
1915 mutex_unlock(&vc4_hdmi->mutex);
1916}
1917
1918static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1919 struct drm_crtc_state *crtc_state,
1920 struct drm_connector_state *conn_state)
1921{
1922 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1923 struct vc4_hdmi_connector_state *vc4_state =
1924 conn_state_to_vc4_hdmi_conn_state(conn_state);
1925
1926 mutex_lock(&vc4_hdmi->mutex);
1927 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1928 &crtc_state->adjusted_mode);
1929 vc4_hdmi->output_bpc = vc4_state->output_bpc;
1930 vc4_hdmi->output_format = vc4_state->output_format;
1931 mutex_unlock(&vc4_hdmi->mutex);
1932}
1933
1934static bool
1935vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi,
1936 const struct drm_display_info *info,
1937 const struct drm_display_mode *mode,
1938 unsigned int format, unsigned int bpc)
1939{
1940 struct drm_device *dev = vc4_hdmi->connector.dev;
1941 u8 vic = drm_match_cea_mode(mode);
1942
1943 if (vic == 1 && bpc != 8) {
1944 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc);
1945 return false;
1946 }
1947
1948 if (!info->is_hdmi &&
1949 (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) {
1950 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n");
1951 return false;
1952 }
1953
1954 switch (format) {
1955 case VC4_HDMI_OUTPUT_RGB:
1956 drm_dbg(dev, "RGB Format, checking the constraints.\n");
1957
1958 if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444))
1959 return false;
1960
1961 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1962 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1963 return false;
1964 }
1965
1966 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1967 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1968 return false;
1969 }
1970
1971 drm_dbg(dev, "RGB format supported in that configuration.\n");
1972
1973 return true;
1974
1975 case VC4_HDMI_OUTPUT_YUV422:
1976 drm_dbg(dev, "YUV422 format, checking the constraints.\n");
1977
1978 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) {
1979 drm_dbg(dev, "Sink doesn't support YUV422.\n");
1980 return false;
1981 }
1982
1983 if (bpc != 12) {
1984 drm_dbg(dev, "YUV422 only supports 12 bpc.\n");
1985 return false;
1986 }
1987
1988 drm_dbg(dev, "YUV422 format supported in that configuration.\n");
1989
1990 return true;
1991
1992 case VC4_HDMI_OUTPUT_YUV444:
1993 drm_dbg(dev, "YUV444 format, checking the constraints.\n");
1994
1995 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) {
1996 drm_dbg(dev, "Sink doesn't support YUV444.\n");
1997 return false;
1998 }
1999
2000 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) {
2001 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
2002 return false;
2003 }
2004
2005 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) {
2006 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
2007 return false;
2008 }
2009
2010 drm_dbg(dev, "YUV444 format supported in that configuration.\n");
2011
2012 return true;
2013 }
2014
2015 return false;
2016}
2017
2018static enum drm_mode_status
2019vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
2020 const struct drm_display_mode *mode,
2021 unsigned long long clock)
2022{
2023 const struct drm_connector *connector = &vc4_hdmi->connector;
2024 const struct drm_display_info *info = &connector->display_info;
2025 struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
2026
2027 if (clock > vc4_hdmi->variant->max_pixel_clock)
2028 return MODE_CLOCK_HIGH;
2029
2030 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK)
2031 return MODE_CLOCK_HIGH;
2032
2033 /* 4096x2160@60 is not reliable without overclocking core */
2034 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 &&
2035 mode->hdisplay > 3840 && mode->vdisplay >= 2160 &&
2036 drm_mode_vrefresh(mode) >= 50)
2037 return MODE_CLOCK_HIGH;
2038
2039 if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000))
2040 return MODE_CLOCK_HIGH;
2041
2042 return MODE_OK;
2043}
2044
2045static unsigned long long
2046vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
2047 unsigned int bpc,
2048 enum vc4_hdmi_output_format fmt)
2049{
2050 unsigned long long clock = mode->clock * 1000ULL;
2051
2052 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2053 clock = clock * 2;
2054
2055 if (fmt == VC4_HDMI_OUTPUT_YUV422)
2056 bpc = 8;
2057
2058 clock = clock * bpc;
2059 do_div(clock, 8);
2060
2061 return clock;
2062}
2063
2064static int
2065vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
2066 struct vc4_hdmi_connector_state *vc4_state,
2067 const struct drm_display_mode *mode,
2068 unsigned int bpc, unsigned int fmt)
2069{
2070 unsigned long long clock;
2071
2072 clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
2073 if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, clock) != MODE_OK)
2074 return -EINVAL;
2075
2076 vc4_state->tmds_char_rate = clock;
2077
2078 return 0;
2079}
2080
2081static int
2082vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi,
2083 struct vc4_hdmi_connector_state *vc4_state,
2084 const struct drm_display_mode *mode,
2085 unsigned int bpc)
2086{
2087 struct drm_device *dev = vc4_hdmi->connector.dev;
2088 const struct drm_connector *connector = &vc4_hdmi->connector;
2089 const struct drm_display_info *info = &connector->display_info;
2090 unsigned int format;
2091
2092 drm_dbg(dev, "Trying with an RGB output\n");
2093
2094 format = VC4_HDMI_OUTPUT_RGB;
2095 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
2096 int ret;
2097
2098 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
2099 mode, bpc, format);
2100 if (!ret) {
2101 vc4_state->output_format = format;
2102 return 0;
2103 }
2104 }
2105
2106 drm_dbg(dev, "Failed, Trying with an YUV422 output\n");
2107
2108 format = VC4_HDMI_OUTPUT_YUV422;
2109 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
2110 int ret;
2111
2112 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
2113 mode, bpc, format);
2114 if (!ret) {
2115 vc4_state->output_format = format;
2116 return 0;
2117 }
2118 }
2119
2120 drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n");
2121
2122 return -EINVAL;
2123}
2124
2125static int
2126vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi,
2127 struct vc4_hdmi_connector_state *vc4_state,
2128 const struct drm_display_mode *mode)
2129{
2130 struct drm_device *dev = vc4_hdmi->connector.dev;
2131 struct drm_connector_state *conn_state = &vc4_state->base;
2132 unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12);
2133 unsigned int bpc;
2134 int ret;
2135
2136 for (bpc = max_bpc; bpc >= 8; bpc -= 2) {
2137 drm_dbg(dev, "Trying with a %d bpc output\n", bpc);
2138
2139 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state,
2140 mode, bpc);
2141 if (ret)
2142 continue;
2143
2144 vc4_state->output_bpc = bpc;
2145
2146 drm_dbg(dev,
2147 "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n",
2148 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
2149 vc4_state->output_bpc,
2150 vc4_hdmi_output_fmt_str(vc4_state->output_format),
2151 vc4_state->tmds_char_rate);
2152
2153 break;
2154 }
2155
2156 return ret;
2157}
2158
2159#define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
2160#define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
2161
2162static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
2163 struct drm_crtc_state *crtc_state,
2164 struct drm_connector_state *conn_state)
2165{
2166 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
2167 struct drm_connector *connector = &vc4_hdmi->connector;
2168 struct drm_connector_state *old_conn_state =
2169 drm_atomic_get_old_connector_state(conn_state->state, connector);
2170 struct vc4_hdmi_connector_state *old_vc4_state =
2171 conn_state_to_vc4_hdmi_conn_state(old_conn_state);
2172 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
2173 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
2174 unsigned long long tmds_char_rate = mode->clock * 1000;
2175 unsigned long long tmds_bit_rate;
2176 int ret;
2177
2178 if (vc4_hdmi->variant->unsupported_odd_h_timings) {
2179 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2180 /* Only try to fixup DBLCLK modes to get 480i and 576i
2181 * working.
2182 * A generic solution for all modes with odd horizontal
2183 * timing values seems impossible based on trying to
2184 * solve it for 1366x768 monitors.
2185 */
2186 if ((mode->hsync_start - mode->hdisplay) & 1)
2187 mode->hsync_start--;
2188 if ((mode->hsync_end - mode->hsync_start) & 1)
2189 mode->hsync_end--;
2190 }
2191
2192 /* Now check whether we still have odd values remaining */
2193 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
2194 (mode->hsync_end % 2) || (mode->htotal % 2))
2195 return -EINVAL;
2196 }
2197
2198 /*
2199 * The 1440p@60 pixel rate is in the same range than the first
2200 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
2201 * bandwidth). Slightly lower the frequency to bring it out of
2202 * the WiFi range.
2203 */
2204 tmds_bit_rate = tmds_char_rate * 10;
2205 if (vc4_hdmi->disable_wifi_frequencies &&
2206 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
2207 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
2208 mode->clock = 238560;
2209 tmds_char_rate = mode->clock * 1000;
2210 }
2211
2212 ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode);
2213 if (ret)
2214 return ret;
2215
2216 /* vc4_hdmi_encoder_compute_config may have changed output_bpc and/or output_format */
2217 if (vc4_state->output_bpc != old_vc4_state->output_bpc ||
2218 vc4_state->output_format != old_vc4_state->output_format)
2219 crtc_state->mode_changed = true;
2220
2221 return 0;
2222}
2223
2224static enum drm_mode_status
2225vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
2226 const struct drm_display_mode *mode)
2227{
2228 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
2229
2230 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
2231 !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
2232 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
2233 (mode->hsync_end % 2) || (mode->htotal % 2)))
2234 return MODE_H_ILLEGAL;
2235
2236 return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, mode->clock * 1000);
2237}
2238
2239static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
2240 .atomic_check = vc4_hdmi_encoder_atomic_check,
2241 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
2242 .mode_valid = vc4_hdmi_encoder_mode_valid,
2243};
2244
2245static int vc4_hdmi_late_register(struct drm_encoder *encoder)
2246{
2247 struct drm_device *drm = encoder->dev;
2248 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
2249 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2250
2251 drm_debugfs_add_file(drm, variant->debugfs_name,
2252 vc4_hdmi_debugfs_regs, vc4_hdmi);
2253
2254 return 0;
2255}
2256
2257static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
2258 .late_register = vc4_hdmi_late_register,
2259};
2260
2261static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2262{
2263 int i;
2264 u32 channel_map = 0;
2265
2266 for (i = 0; i < 8; i++) {
2267 if (channel_mask & BIT(i))
2268 channel_map |= i << (3 * i);
2269 }
2270 return channel_map;
2271}
2272
2273static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2274{
2275 int i;
2276 u32 channel_map = 0;
2277
2278 for (i = 0; i < 8; i++) {
2279 if (channel_mask & BIT(i))
2280 channel_map |= i << (4 * i);
2281 }
2282 return channel_map;
2283}
2284
2285static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
2286{
2287 struct drm_device *drm = vc4_hdmi->connector.dev;
2288 unsigned long flags;
2289 u32 hotplug;
2290 int idx;
2291
2292 if (!drm_dev_enter(drm, &idx))
2293 return false;
2294
2295 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2296 hotplug = HDMI_READ(HDMI_HOTPLUG);
2297 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2298
2299 drm_dev_exit(idx);
2300
2301 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
2302}
2303
2304/* HDMI audio codec callbacks */
2305static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
2306 unsigned int samplerate)
2307{
2308 struct drm_device *drm = vc4_hdmi->connector.dev;
2309 u32 hsm_clock;
2310 unsigned long flags;
2311 unsigned long n, m;
2312 int idx;
2313
2314 if (!drm_dev_enter(drm, &idx))
2315 return;
2316
2317 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
2318 rational_best_approximation(hsm_clock, samplerate,
2319 VC4_HD_MAI_SMP_N_MASK >>
2320 VC4_HD_MAI_SMP_N_SHIFT,
2321 (VC4_HD_MAI_SMP_M_MASK >>
2322 VC4_HD_MAI_SMP_M_SHIFT) + 1,
2323 &n, &m);
2324
2325 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2326 HDMI_WRITE(HDMI_MAI_SMP,
2327 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
2328 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
2329 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2330
2331 drm_dev_exit(idx);
2332}
2333
2334static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
2335{
2336 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
2337 u32 n, cts;
2338 u64 tmp;
2339
2340 lockdep_assert_held(&vc4_hdmi->mutex);
2341 lockdep_assert_held(&vc4_hdmi->hw_lock);
2342
2343 n = 128 * samplerate / 1000;
2344 tmp = (u64)(mode->clock * 1000) * n;
2345 do_div(tmp, 128 * samplerate);
2346 cts = tmp;
2347
2348 HDMI_WRITE(HDMI_CRP_CFG,
2349 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
2350 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
2351
2352 /*
2353 * We could get slightly more accurate clocks in some cases by
2354 * providing a CTS_1 value. The two CTS values are alternated
2355 * between based on the period fields
2356 */
2357 HDMI_WRITE(HDMI_CTS_0, cts);
2358 HDMI_WRITE(HDMI_CTS_1, cts);
2359}
2360
2361static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
2362{
2363 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
2364
2365 return snd_soc_card_get_drvdata(card);
2366}
2367
2368static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
2369{
2370 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
2371
2372 lockdep_assert_held(&vc4_hdmi->mutex);
2373
2374 /*
2375 * If the encoder is currently in DVI mode, treat the codec DAI
2376 * as missing.
2377 */
2378 if (!display->is_hdmi)
2379 return false;
2380
2381 return true;
2382}
2383
2384static int vc4_hdmi_audio_startup(struct device *dev, void *data)
2385{
2386 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2387 struct drm_device *drm = vc4_hdmi->connector.dev;
2388 unsigned long flags;
2389 int ret = 0;
2390 int idx;
2391
2392 mutex_lock(&vc4_hdmi->mutex);
2393
2394 if (!drm_dev_enter(drm, &idx)) {
2395 ret = -ENODEV;
2396 goto out;
2397 }
2398
2399 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2400 ret = -ENODEV;
2401 goto out_dev_exit;
2402 }
2403
2404 vc4_hdmi->audio.streaming = true;
2405
2406 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2407 HDMI_WRITE(HDMI_MAI_CTL,
2408 VC4_HD_MAI_CTL_RESET |
2409 VC4_HD_MAI_CTL_FLUSH |
2410 VC4_HD_MAI_CTL_DLATE |
2411 VC4_HD_MAI_CTL_ERRORE |
2412 VC4_HD_MAI_CTL_ERRORF);
2413 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2414
2415 if (vc4_hdmi->variant->phy_rng_enable)
2416 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
2417
2418out_dev_exit:
2419 drm_dev_exit(idx);
2420out:
2421 mutex_unlock(&vc4_hdmi->mutex);
2422
2423 return ret;
2424}
2425
2426static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
2427{
2428 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2429 struct device *dev = &vc4_hdmi->pdev->dev;
2430 unsigned long flags;
2431 int ret;
2432
2433 lockdep_assert_held(&vc4_hdmi->mutex);
2434
2435 vc4_hdmi->audio.streaming = false;
2436 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
2437 if (ret)
2438 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
2439
2440 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2441
2442 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
2443 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
2444 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
2445
2446 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2447}
2448
2449static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
2450{
2451 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2452 struct drm_device *drm = vc4_hdmi->connector.dev;
2453 unsigned long flags;
2454 int idx;
2455
2456 mutex_lock(&vc4_hdmi->mutex);
2457
2458 if (!drm_dev_enter(drm, &idx))
2459 goto out;
2460
2461 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2462
2463 HDMI_WRITE(HDMI_MAI_CTL,
2464 VC4_HD_MAI_CTL_DLATE |
2465 VC4_HD_MAI_CTL_ERRORE |
2466 VC4_HD_MAI_CTL_ERRORF);
2467
2468 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2469
2470 if (vc4_hdmi->variant->phy_rng_disable)
2471 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
2472
2473 vc4_hdmi->audio.streaming = false;
2474 vc4_hdmi_audio_reset(vc4_hdmi);
2475
2476 drm_dev_exit(idx);
2477
2478out:
2479 mutex_unlock(&vc4_hdmi->mutex);
2480}
2481
2482static int sample_rate_to_mai_fmt(int samplerate)
2483{
2484 switch (samplerate) {
2485 case 8000:
2486 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
2487 case 11025:
2488 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
2489 case 12000:
2490 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
2491 case 16000:
2492 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
2493 case 22050:
2494 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
2495 case 24000:
2496 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
2497 case 32000:
2498 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
2499 case 44100:
2500 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
2501 case 48000:
2502 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
2503 case 64000:
2504 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
2505 case 88200:
2506 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
2507 case 96000:
2508 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
2509 case 128000:
2510 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
2511 case 176400:
2512 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
2513 case 192000:
2514 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
2515 default:
2516 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
2517 }
2518}
2519
2520/* HDMI audio codec callbacks */
2521static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
2522 struct hdmi_codec_daifmt *daifmt,
2523 struct hdmi_codec_params *params)
2524{
2525 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2526 struct drm_device *drm = vc4_hdmi->connector.dev;
2527 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2528 unsigned int sample_rate = params->sample_rate;
2529 unsigned int channels = params->channels;
2530 unsigned long flags;
2531 u32 audio_packet_config, channel_mask;
2532 u32 channel_map;
2533 u32 mai_audio_format;
2534 u32 mai_sample_rate;
2535 int ret = 0;
2536 int idx;
2537
2538 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
2539 sample_rate, params->sample_width, channels);
2540
2541 mutex_lock(&vc4_hdmi->mutex);
2542
2543 if (!drm_dev_enter(drm, &idx)) {
2544 ret = -ENODEV;
2545 goto out;
2546 }
2547
2548 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2549 ret = -EINVAL;
2550 goto out_dev_exit;
2551 }
2552
2553 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
2554
2555 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2556 HDMI_WRITE(HDMI_MAI_CTL,
2557 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
2558 VC4_HD_MAI_CTL_WHOLSMP |
2559 VC4_HD_MAI_CTL_CHALIGN |
2560 VC4_HD_MAI_CTL_ENABLE);
2561
2562 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
2563 if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
2564 params->channels == 8)
2565 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
2566 else
2567 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
2568 HDMI_WRITE(HDMI_MAI_FMT,
2569 VC4_SET_FIELD(mai_sample_rate,
2570 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
2571 VC4_SET_FIELD(mai_audio_format,
2572 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
2573
2574 /* The B frame identifier should match the value used by alsa-lib (8) */
2575 audio_packet_config =
2576 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
2577 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
2578 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
2579
2580 channel_mask = GENMASK(channels - 1, 0);
2581 audio_packet_config |= VC4_SET_FIELD(channel_mask,
2582 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
2583
2584 /* Set the MAI threshold */
2585 HDMI_WRITE(HDMI_MAI_THR,
2586 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
2587 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
2588 VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
2589 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
2590
2591 HDMI_WRITE(HDMI_MAI_CONFIG,
2592 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
2593 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
2594 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
2595
2596 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
2597 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
2598 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
2599
2600 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
2601
2602 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2603
2604 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea));
2605 vc4_hdmi_set_audio_infoframe(encoder);
2606
2607out_dev_exit:
2608 drm_dev_exit(idx);
2609out:
2610 mutex_unlock(&vc4_hdmi->mutex);
2611
2612 return ret;
2613}
2614
2615static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2616 .name = "vc4-hdmi-cpu-dai-component",
2617 .legacy_dai_naming = 1,
2618};
2619
2620static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2621{
2622 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2623
2624 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2625
2626 return 0;
2627}
2628
2629static const struct snd_soc_dai_ops vc4_snd_dai_ops = {
2630 .probe = vc4_hdmi_audio_cpu_dai_probe,
2631};
2632
2633static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2634 .name = "vc4-hdmi-cpu-dai",
2635 .ops = &vc4_snd_dai_ops,
2636 .playback = {
2637 .stream_name = "Playback",
2638 .channels_min = 1,
2639 .channels_max = 8,
2640 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2641 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2642 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2643 SNDRV_PCM_RATE_192000,
2644 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2645 },
2646};
2647
2648static const struct snd_dmaengine_pcm_config pcm_conf = {
2649 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2650 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2651};
2652
2653static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
2654 uint8_t *buf, size_t len)
2655{
2656 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2657 struct drm_connector *connector = &vc4_hdmi->connector;
2658
2659 mutex_lock(&vc4_hdmi->mutex);
2660 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2661 mutex_unlock(&vc4_hdmi->mutex);
2662
2663 return 0;
2664}
2665
2666static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
2667 .get_eld = vc4_hdmi_audio_get_eld,
2668 .prepare = vc4_hdmi_audio_prepare,
2669 .audio_shutdown = vc4_hdmi_audio_shutdown,
2670 .audio_startup = vc4_hdmi_audio_startup,
2671};
2672
2673static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
2674 .ops = &vc4_hdmi_codec_ops,
2675 .max_i2s_channels = 8,
2676 .i2s = 1,
2677};
2678
2679static void vc4_hdmi_audio_codec_release(void *ptr)
2680{
2681 struct vc4_hdmi *vc4_hdmi = ptr;
2682
2683 platform_device_unregister(vc4_hdmi->audio.codec_pdev);
2684 vc4_hdmi->audio.codec_pdev = NULL;
2685}
2686
2687static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2688{
2689 const struct vc4_hdmi_register *mai_data =
2690 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2691 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2692 struct snd_soc_card *card = &vc4_hdmi->audio.card;
2693 struct device *dev = &vc4_hdmi->pdev->dev;
2694 struct platform_device *codec_pdev;
2695 const __be32 *addr;
2696 int index, len;
2697 int ret;
2698
2699 /*
2700 * ASoC makes it a bit hard to retrieve a pointer to the
2701 * vc4_hdmi structure. Registering the card will overwrite our
2702 * device drvdata with a pointer to the snd_soc_card structure,
2703 * which can then be used to retrieve whatever drvdata we want
2704 * to associate.
2705 *
2706 * However, that doesn't fly in the case where we wouldn't
2707 * register an ASoC card (because of an old DT that is missing
2708 * the dmas properties for example), then the card isn't
2709 * registered and the device drvdata wouldn't be set.
2710 *
2711 * We can deal with both cases by making sure a snd_soc_card
2712 * pointer and a vc4_hdmi structure are pointing to the same
2713 * memory address, so we can treat them indistinctly without any
2714 * issue.
2715 */
2716 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2717 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2718
2719 if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
2720 dev_warn(dev,
2721 "'dmas' DT property is missing or empty, no HDMI audio\n");
2722 return 0;
2723 }
2724
2725 if (mai_data->reg != VC4_HD) {
2726 WARN_ONCE(true, "MAI isn't in the HD block\n");
2727 return -EINVAL;
2728 }
2729
2730 /*
2731 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2732 * the bus address specified in the DT, because the physical address
2733 * (the one returned by platform_get_resource()) is not appropriate
2734 * for DMA transfers.
2735 * This VC/MMU should probably be exposed to avoid this kind of hacks.
2736 */
2737 index = of_property_match_string(dev->of_node, "reg-names", "hd");
2738 /* Before BCM2711, we don't have a named register range */
2739 if (index < 0)
2740 index = 1;
2741
2742 addr = of_get_address(dev->of_node, index, NULL, NULL);
2743 if (!addr)
2744 return -EINVAL;
2745
2746 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2747 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2748 vc4_hdmi->audio.dma_data.maxburst = 2;
2749
2750 /*
2751 * NOTE: Strictly speaking, we should probably use a DRM-managed
2752 * registration there to avoid removing all the audio components
2753 * by the time the driver doesn't have any user anymore.
2754 *
2755 * However, the ASoC core uses a number of devm_kzalloc calls
2756 * when registering, even when using non-device-managed
2757 * functions (such as in snd_soc_register_component()).
2758 *
2759 * If we call snd_soc_unregister_component() in a DRM-managed
2760 * action, the device-managed actions have already been executed
2761 * and thus we would access memory that has been freed.
2762 *
2763 * Using device-managed hooks here probably leaves us open to a
2764 * bunch of issues if userspace still has a handle on the ALSA
2765 * device when the device is removed. However, this is mitigated
2766 * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2767 * path to prevent the access to the device resources if it
2768 * isn't there anymore.
2769 *
2770 * Then, the vc4_hdmi structure is DRM-managed and thus only
2771 * freed whenever the last user has closed the DRM device file.
2772 * It should thus outlive ALSA in most situations.
2773 */
2774 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2775 if (ret) {
2776 dev_err(dev, "Could not register PCM component: %d\n", ret);
2777 return ret;
2778 }
2779
2780 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2781 &vc4_hdmi_audio_cpu_dai_drv, 1);
2782 if (ret) {
2783 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2784 return ret;
2785 }
2786
2787 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
2788 PLATFORM_DEVID_AUTO,
2789 &vc4_hdmi_codec_pdata,
2790 sizeof(vc4_hdmi_codec_pdata));
2791 if (IS_ERR(codec_pdev)) {
2792 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
2793 return PTR_ERR(codec_pdev);
2794 }
2795 vc4_hdmi->audio.codec_pdev = codec_pdev;
2796
2797 ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi);
2798 if (ret)
2799 return ret;
2800
2801 dai_link->cpus = &vc4_hdmi->audio.cpu;
2802 dai_link->codecs = &vc4_hdmi->audio.codec;
2803 dai_link->platforms = &vc4_hdmi->audio.platform;
2804
2805 dai_link->num_cpus = 1;
2806 dai_link->num_codecs = 1;
2807 dai_link->num_platforms = 1;
2808
2809 dai_link->name = "MAI";
2810 dai_link->stream_name = "MAI PCM";
2811 dai_link->codecs->dai_name = "i2s-hifi";
2812 dai_link->cpus->dai_name = dev_name(dev);
2813 dai_link->codecs->name = dev_name(&codec_pdev->dev);
2814 dai_link->platforms->name = dev_name(dev);
2815
2816 card->dai_link = dai_link;
2817 card->num_links = 1;
2818 card->name = vc4_hdmi->variant->card_name;
2819 card->driver_name = "vc4-hdmi";
2820 card->dev = dev;
2821 card->owner = THIS_MODULE;
2822
2823 /*
2824 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2825 * stores a pointer to the snd card object in dev->driver_data. This
2826 * means we cannot use it for something else. The hdmi back-pointer is
2827 * now stored in card->drvdata and should be retrieved with
2828 * snd_soc_card_get_drvdata() if needed.
2829 */
2830 snd_soc_card_set_drvdata(card, vc4_hdmi);
2831 ret = devm_snd_soc_register_card(dev, card);
2832 if (ret)
2833 dev_err_probe(dev, ret, "Could not register sound card\n");
2834
2835 return ret;
2836
2837}
2838
2839static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2840{
2841 struct vc4_hdmi *vc4_hdmi = priv;
2842 struct drm_connector *connector = &vc4_hdmi->connector;
2843 struct drm_device *dev = connector->dev;
2844
2845 if (dev && dev->registered)
2846 drm_connector_helper_hpd_irq_event(connector);
2847
2848 return IRQ_HANDLED;
2849}
2850
2851static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2852{
2853 struct drm_connector *connector = &vc4_hdmi->connector;
2854 struct platform_device *pdev = vc4_hdmi->pdev;
2855 int ret;
2856
2857 if (vc4_hdmi->variant->external_irq_controller) {
2858 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2859 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2860
2861 ret = devm_request_threaded_irq(&pdev->dev, hpd_con,
2862 NULL,
2863 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2864 "vc4 hdmi hpd connected", vc4_hdmi);
2865 if (ret)
2866 return ret;
2867
2868 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm,
2869 NULL,
2870 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2871 "vc4 hdmi hpd disconnected", vc4_hdmi);
2872 if (ret)
2873 return ret;
2874
2875 connector->polled = DRM_CONNECTOR_POLL_HPD;
2876 }
2877
2878 return 0;
2879}
2880
2881#ifdef CONFIG_DRM_VC4_HDMI_CEC
2882static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2883{
2884 struct vc4_hdmi *vc4_hdmi = priv;
2885
2886 if (vc4_hdmi->cec_rx_msg.len)
2887 cec_received_msg(vc4_hdmi->cec_adap,
2888 &vc4_hdmi->cec_rx_msg);
2889
2890 return IRQ_HANDLED;
2891}
2892
2893static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2894{
2895 struct vc4_hdmi *vc4_hdmi = priv;
2896
2897 if (vc4_hdmi->cec_tx_ok) {
2898 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2899 0, 0, 0, 0);
2900 } else {
2901 /*
2902 * This CEC implementation makes 1 retry, so if we
2903 * get a NACK, then that means it made 2 attempts.
2904 */
2905 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2906 0, 2, 0, 0);
2907 }
2908 return IRQ_HANDLED;
2909}
2910
2911static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2912{
2913 struct vc4_hdmi *vc4_hdmi = priv;
2914 irqreturn_t ret;
2915
2916 if (vc4_hdmi->cec_irq_was_rx)
2917 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2918 else
2919 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2920
2921 return ret;
2922}
2923
2924static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2925{
2926 struct drm_device *dev = vc4_hdmi->connector.dev;
2927 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2928 unsigned int i;
2929
2930 lockdep_assert_held(&vc4_hdmi->hw_lock);
2931
2932 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2933 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2934
2935 if (msg->len > 16) {
2936 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2937 return;
2938 }
2939
2940 for (i = 0; i < msg->len; i += 4) {
2941 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2942
2943 msg->msg[i] = val & 0xff;
2944 msg->msg[i + 1] = (val >> 8) & 0xff;
2945 msg->msg[i + 2] = (val >> 16) & 0xff;
2946 msg->msg[i + 3] = (val >> 24) & 0xff;
2947 }
2948}
2949
2950static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2951{
2952 u32 cntrl1;
2953
2954 /*
2955 * We don't need to protect the register access using
2956 * drm_dev_enter() there because the interrupt handler lifetime
2957 * is tied to the device itself, and not to the DRM device.
2958 *
2959 * So when the device will be gone, one of the first thing we
2960 * will be doing will be to unregister the interrupt handler,
2961 * and then unregister the DRM device. drm_dev_enter() would
2962 * thus always succeed if we are here.
2963 */
2964
2965 lockdep_assert_held(&vc4_hdmi->hw_lock);
2966
2967 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2968 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2969 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2970 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2971
2972 return IRQ_WAKE_THREAD;
2973}
2974
2975static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2976{
2977 struct vc4_hdmi *vc4_hdmi = priv;
2978 irqreturn_t ret;
2979
2980 spin_lock(&vc4_hdmi->hw_lock);
2981 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2982 spin_unlock(&vc4_hdmi->hw_lock);
2983
2984 return ret;
2985}
2986
2987static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2988{
2989 u32 cntrl1;
2990
2991 lockdep_assert_held(&vc4_hdmi->hw_lock);
2992
2993 /*
2994 * We don't need to protect the register access using
2995 * drm_dev_enter() there because the interrupt handler lifetime
2996 * is tied to the device itself, and not to the DRM device.
2997 *
2998 * So when the device will be gone, one of the first thing we
2999 * will be doing will be to unregister the interrupt handler,
3000 * and then unregister the DRM device. drm_dev_enter() would
3001 * thus always succeed if we are here.
3002 */
3003
3004 vc4_hdmi->cec_rx_msg.len = 0;
3005 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
3006 vc4_cec_read_msg(vc4_hdmi, cntrl1);
3007 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
3008 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
3009 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
3010
3011 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
3012
3013 return IRQ_WAKE_THREAD;
3014}
3015
3016static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
3017{
3018 struct vc4_hdmi *vc4_hdmi = priv;
3019 irqreturn_t ret;
3020
3021 spin_lock(&vc4_hdmi->hw_lock);
3022 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
3023 spin_unlock(&vc4_hdmi->hw_lock);
3024
3025 return ret;
3026}
3027
3028static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
3029{
3030 struct vc4_hdmi *vc4_hdmi = priv;
3031 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
3032 irqreturn_t ret;
3033 u32 cntrl5;
3034
3035 /*
3036 * We don't need to protect the register access using
3037 * drm_dev_enter() there because the interrupt handler lifetime
3038 * is tied to the device itself, and not to the DRM device.
3039 *
3040 * So when the device will be gone, one of the first thing we
3041 * will be doing will be to unregister the interrupt handler,
3042 * and then unregister the DRM device. drm_dev_enter() would
3043 * thus always succeed if we are here.
3044 */
3045
3046 if (!(stat & VC4_HDMI_CPU_CEC))
3047 return IRQ_NONE;
3048
3049 spin_lock(&vc4_hdmi->hw_lock);
3050 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
3051 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
3052 if (vc4_hdmi->cec_irq_was_rx)
3053 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
3054 else
3055 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
3056
3057 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
3058 spin_unlock(&vc4_hdmi->hw_lock);
3059
3060 return ret;
3061}
3062
3063static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
3064{
3065 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
3066 struct drm_device *drm = vc4_hdmi->connector.dev;
3067 /* clock period in microseconds */
3068 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
3069 unsigned long flags;
3070 u32 val;
3071 int ret;
3072 int idx;
3073
3074 if (!drm_dev_enter(drm, &idx))
3075 /*
3076 * We can't return an error code, because the CEC
3077 * framework will emit WARN_ON messages at unbind
3078 * otherwise.
3079 */
3080 return 0;
3081
3082 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
3083 if (ret) {
3084 drm_dev_exit(idx);
3085 return ret;
3086 }
3087
3088 mutex_lock(&vc4_hdmi->mutex);
3089
3090 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3091
3092 val = HDMI_READ(HDMI_CEC_CNTRL_5);
3093 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
3094 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
3095 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
3096 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
3097 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
3098
3099 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
3100 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
3101 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
3102 HDMI_WRITE(HDMI_CEC_CNTRL_2,
3103 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
3104 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
3105 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
3106 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
3107 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
3108 HDMI_WRITE(HDMI_CEC_CNTRL_3,
3109 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
3110 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
3111 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
3112 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
3113 HDMI_WRITE(HDMI_CEC_CNTRL_4,
3114 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
3115 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
3116 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
3117 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
3118
3119 if (!vc4_hdmi->variant->external_irq_controller)
3120 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
3121
3122 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3123
3124 mutex_unlock(&vc4_hdmi->mutex);
3125 drm_dev_exit(idx);
3126
3127 return 0;
3128}
3129
3130static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
3131{
3132 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
3133 struct drm_device *drm = vc4_hdmi->connector.dev;
3134 unsigned long flags;
3135 int idx;
3136
3137 if (!drm_dev_enter(drm, &idx))
3138 /*
3139 * We can't return an error code, because the CEC
3140 * framework will emit WARN_ON messages at unbind
3141 * otherwise.
3142 */
3143 return 0;
3144
3145 mutex_lock(&vc4_hdmi->mutex);
3146
3147 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3148
3149 if (!vc4_hdmi->variant->external_irq_controller)
3150 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
3151
3152 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
3153 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
3154
3155 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3156
3157 mutex_unlock(&vc4_hdmi->mutex);
3158
3159 pm_runtime_put(&vc4_hdmi->pdev->dev);
3160
3161 drm_dev_exit(idx);
3162
3163 return 0;
3164}
3165
3166static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
3167{
3168 if (enable)
3169 return vc4_hdmi_cec_enable(adap);
3170 else
3171 return vc4_hdmi_cec_disable(adap);
3172}
3173
3174static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
3175{
3176 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
3177 struct drm_device *drm = vc4_hdmi->connector.dev;
3178 unsigned long flags;
3179 int idx;
3180
3181 if (!drm_dev_enter(drm, &idx))
3182 /*
3183 * We can't return an error code, because the CEC
3184 * framework will emit WARN_ON messages at unbind
3185 * otherwise.
3186 */
3187 return 0;
3188
3189 mutex_lock(&vc4_hdmi->mutex);
3190 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3191 HDMI_WRITE(HDMI_CEC_CNTRL_1,
3192 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
3193 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
3194 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3195 mutex_unlock(&vc4_hdmi->mutex);
3196
3197 drm_dev_exit(idx);
3198
3199 return 0;
3200}
3201
3202static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
3203 u32 signal_free_time, struct cec_msg *msg)
3204{
3205 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
3206 struct drm_device *dev = vc4_hdmi->connector.dev;
3207 unsigned long flags;
3208 u32 val;
3209 unsigned int i;
3210 int idx;
3211
3212 if (!drm_dev_enter(dev, &idx))
3213 return -ENODEV;
3214
3215 if (msg->len > 16) {
3216 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
3217 drm_dev_exit(idx);
3218 return -ENOMEM;
3219 }
3220
3221 mutex_lock(&vc4_hdmi->mutex);
3222
3223 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3224
3225 for (i = 0; i < msg->len; i += 4)
3226 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
3227 (msg->msg[i]) |
3228 (msg->msg[i + 1] << 8) |
3229 (msg->msg[i + 2] << 16) |
3230 (msg->msg[i + 3] << 24));
3231
3232 val = HDMI_READ(HDMI_CEC_CNTRL_1);
3233 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
3234 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
3235 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
3236 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
3237 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
3238
3239 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
3240
3241 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3242 mutex_unlock(&vc4_hdmi->mutex);
3243 drm_dev_exit(idx);
3244
3245 return 0;
3246}
3247
3248static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
3249 .adap_enable = vc4_hdmi_cec_adap_enable,
3250 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
3251 .adap_transmit = vc4_hdmi_cec_adap_transmit,
3252};
3253
3254static void vc4_hdmi_cec_release(void *ptr)
3255{
3256 struct vc4_hdmi *vc4_hdmi = ptr;
3257
3258 cec_unregister_adapter(vc4_hdmi->cec_adap);
3259 vc4_hdmi->cec_adap = NULL;
3260}
3261
3262static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3263{
3264 struct cec_connector_info conn_info;
3265 struct platform_device *pdev = vc4_hdmi->pdev;
3266 struct device *dev = &pdev->dev;
3267 int ret;
3268
3269 if (!of_property_present(dev->of_node, "interrupts")) {
3270 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
3271 return 0;
3272 }
3273
3274 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
3275 vc4_hdmi,
3276 vc4_hdmi->variant->card_name,
3277 CEC_CAP_DEFAULTS |
3278 CEC_CAP_CONNECTOR_INFO, 1);
3279 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
3280 if (ret < 0)
3281 return ret;
3282
3283 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
3284 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
3285
3286 if (vc4_hdmi->variant->external_irq_controller) {
3287 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
3288 vc4_cec_irq_handler_rx_bare,
3289 vc4_cec_irq_handler_rx_thread, 0,
3290 "vc4 hdmi cec rx", vc4_hdmi);
3291 if (ret)
3292 goto err_delete_cec_adap;
3293
3294 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
3295 vc4_cec_irq_handler_tx_bare,
3296 vc4_cec_irq_handler_tx_thread, 0,
3297 "vc4 hdmi cec tx", vc4_hdmi);
3298 if (ret)
3299 goto err_delete_cec_adap;
3300 } else {
3301 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
3302 vc4_cec_irq_handler,
3303 vc4_cec_irq_handler_thread, 0,
3304 "vc4 hdmi cec", vc4_hdmi);
3305 if (ret)
3306 goto err_delete_cec_adap;
3307 }
3308
3309 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
3310 if (ret < 0)
3311 goto err_delete_cec_adap;
3312
3313 /*
3314 * NOTE: Strictly speaking, we should probably use a DRM-managed
3315 * registration there to avoid removing the CEC adapter by the
3316 * time the DRM driver doesn't have any user anymore.
3317 *
3318 * However, the CEC framework already cleans up the CEC adapter
3319 * only when the last user has closed its file descriptor, so we
3320 * don't need to handle it in DRM.
3321 *
3322 * By the time the device-managed hook is executed, we will give
3323 * up our reference to the CEC adapter and therefore don't
3324 * really care when it's actually freed.
3325 *
3326 * There's still a problematic sequence: if we unregister our
3327 * CEC adapter, but the userspace keeps a handle on the CEC
3328 * adapter but not the DRM device for some reason. In such a
3329 * case, our vc4_hdmi structure will be freed, but the
3330 * cec_adapter structure will have a dangling pointer to what
3331 * used to be our HDMI controller. If we get a CEC call at that
3332 * moment, we could end up with a use-after-free. Fortunately,
3333 * the CEC framework already handles this too, by calling
3334 * cec_is_registered() in cec_ioctl() and cec_poll().
3335 */
3336 ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
3337 if (ret)
3338 return ret;
3339
3340 return 0;
3341
3342err_delete_cec_adap:
3343 cec_delete_adapter(vc4_hdmi->cec_adap);
3344
3345 return ret;
3346}
3347#else
3348static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3349{
3350 return 0;
3351}
3352#endif
3353
3354static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr)
3355{
3356 struct debugfs_reg32 *regs = ptr;
3357
3358 kfree(regs);
3359}
3360
3361static int vc4_hdmi_build_regset(struct drm_device *drm,
3362 struct vc4_hdmi *vc4_hdmi,
3363 struct debugfs_regset32 *regset,
3364 enum vc4_hdmi_regs reg)
3365{
3366 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
3367 struct debugfs_reg32 *regs, *new_regs;
3368 unsigned int count = 0;
3369 unsigned int i;
3370 int ret;
3371
3372 regs = kcalloc(variant->num_registers, sizeof(*regs),
3373 GFP_KERNEL);
3374 if (!regs)
3375 return -ENOMEM;
3376
3377 for (i = 0; i < variant->num_registers; i++) {
3378 const struct vc4_hdmi_register *field = &variant->registers[i];
3379
3380 if (field->reg != reg)
3381 continue;
3382
3383 regs[count].name = field->name;
3384 regs[count].offset = field->offset;
3385 count++;
3386 }
3387
3388 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
3389 if (!new_regs)
3390 return -ENOMEM;
3391
3392 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
3393 regset->regs = new_regs;
3394 regset->nregs = count;
3395
3396 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
3397 if (ret)
3398 return ret;
3399
3400 return 0;
3401}
3402
3403static int vc4_hdmi_init_resources(struct drm_device *drm,
3404 struct vc4_hdmi *vc4_hdmi)
3405{
3406 struct platform_device *pdev = vc4_hdmi->pdev;
3407 struct device *dev = &pdev->dev;
3408 int ret;
3409
3410 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
3411 if (IS_ERR(vc4_hdmi->hdmicore_regs))
3412 return PTR_ERR(vc4_hdmi->hdmicore_regs);
3413
3414 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
3415 if (IS_ERR(vc4_hdmi->hd_regs))
3416 return PTR_ERR(vc4_hdmi->hd_regs);
3417
3418 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3419 if (ret)
3420 return ret;
3421
3422 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3423 if (ret)
3424 return ret;
3425
3426 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
3427 if (IS_ERR(vc4_hdmi->pixel_clock)) {
3428 ret = PTR_ERR(vc4_hdmi->pixel_clock);
3429 if (ret != -EPROBE_DEFER)
3430 DRM_ERROR("Failed to get pixel clock\n");
3431 return ret;
3432 }
3433
3434 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3435 if (IS_ERR(vc4_hdmi->hsm_clock)) {
3436 DRM_ERROR("Failed to get HDMI state machine clock\n");
3437 return PTR_ERR(vc4_hdmi->hsm_clock);
3438 }
3439 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
3440 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
3441
3442 return 0;
3443}
3444
3445static int vc5_hdmi_init_resources(struct drm_device *drm,
3446 struct vc4_hdmi *vc4_hdmi)
3447{
3448 struct platform_device *pdev = vc4_hdmi->pdev;
3449 struct device *dev = &pdev->dev;
3450 struct resource *res;
3451 int ret;
3452
3453 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
3454 if (!res)
3455 return -ENODEV;
3456
3457 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
3458 resource_size(res));
3459 if (!vc4_hdmi->hdmicore_regs)
3460 return -ENOMEM;
3461
3462 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
3463 if (!res)
3464 return -ENODEV;
3465
3466 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
3467 if (!vc4_hdmi->hd_regs)
3468 return -ENOMEM;
3469
3470 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
3471 if (!res)
3472 return -ENODEV;
3473
3474 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
3475 if (!vc4_hdmi->cec_regs)
3476 return -ENOMEM;
3477
3478 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
3479 if (!res)
3480 return -ENODEV;
3481
3482 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
3483 if (!vc4_hdmi->csc_regs)
3484 return -ENOMEM;
3485
3486 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
3487 if (!res)
3488 return -ENODEV;
3489
3490 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
3491 if (!vc4_hdmi->dvp_regs)
3492 return -ENOMEM;
3493
3494 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
3495 if (!res)
3496 return -ENODEV;
3497
3498 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
3499 if (!vc4_hdmi->phy_regs)
3500 return -ENOMEM;
3501
3502 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
3503 if (!res)
3504 return -ENODEV;
3505
3506 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
3507 if (!vc4_hdmi->ram_regs)
3508 return -ENOMEM;
3509
3510 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
3511 if (!res)
3512 return -ENODEV;
3513
3514 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
3515 if (!vc4_hdmi->rm_regs)
3516 return -ENOMEM;
3517
3518 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3519 if (IS_ERR(vc4_hdmi->hsm_clock)) {
3520 DRM_ERROR("Failed to get HDMI state machine clock\n");
3521 return PTR_ERR(vc4_hdmi->hsm_clock);
3522 }
3523
3524 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3525 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3526 DRM_ERROR("Failed to get pixel bvb clock\n");
3527 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
3528 }
3529
3530 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
3531 if (IS_ERR(vc4_hdmi->audio_clock)) {
3532 DRM_ERROR("Failed to get audio clock\n");
3533 return PTR_ERR(vc4_hdmi->audio_clock);
3534 }
3535
3536 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
3537 if (IS_ERR(vc4_hdmi->cec_clock)) {
3538 DRM_ERROR("Failed to get CEC clock\n");
3539 return PTR_ERR(vc4_hdmi->cec_clock);
3540 }
3541
3542 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3543 if (IS_ERR(vc4_hdmi->reset)) {
3544 DRM_ERROR("Failed to get HDMI reset line\n");
3545 return PTR_ERR(vc4_hdmi->reset);
3546 }
3547
3548 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3549 if (ret)
3550 return ret;
3551
3552 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3553 if (ret)
3554 return ret;
3555
3556 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
3557 if (ret)
3558 return ret;
3559
3560 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
3561 if (ret)
3562 return ret;
3563
3564 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
3565 if (ret)
3566 return ret;
3567
3568 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
3569 if (ret)
3570 return ret;
3571
3572 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
3573 if (ret)
3574 return ret;
3575
3576 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
3577 if (ret)
3578 return ret;
3579
3580 return 0;
3581}
3582
3583static int vc4_hdmi_runtime_suspend(struct device *dev)
3584{
3585 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3586
3587 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3588
3589 return 0;
3590}
3591
3592static int vc4_hdmi_runtime_resume(struct device *dev)
3593{
3594 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3595 unsigned long __maybe_unused flags;
3596 u32 __maybe_unused value;
3597 unsigned long rate;
3598 int ret;
3599
3600 ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
3601 if (ret)
3602 return ret;
3603
3604 /*
3605 * Whenever the RaspberryPi boots without an HDMI monitor
3606 * plugged in, the firmware won't have initialized the HSM clock
3607 * rate and it will be reported as 0.
3608 *
3609 * If we try to access a register of the controller in such a
3610 * case, it will lead to a silent CPU stall. Let's make sure we
3611 * prevent such a case.
3612 */
3613 rate = clk_get_rate(vc4_hdmi->hsm_clock);
3614 if (!rate) {
3615 ret = -EINVAL;
3616 goto err_disable_clk;
3617 }
3618
3619 if (vc4_hdmi->variant->reset)
3620 vc4_hdmi->variant->reset(vc4_hdmi);
3621
3622#ifdef CONFIG_DRM_VC4_HDMI_CEC
3623 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3624 value = HDMI_READ(HDMI_CEC_CNTRL_1);
3625 /* Set the logical address to Unregistered */
3626 value |= VC4_HDMI_CEC_ADDR_MASK;
3627 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
3628 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3629
3630 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
3631
3632 if (!vc4_hdmi->variant->external_irq_controller) {
3633 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3634 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3635 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3636 }
3637#endif
3638
3639 return 0;
3640
3641err_disable_clk:
3642 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3643 return ret;
3644}
3645
3646static void vc4_hdmi_put_ddc_device(void *ptr)
3647{
3648 struct vc4_hdmi *vc4_hdmi = ptr;
3649
3650 put_device(&vc4_hdmi->ddc->dev);
3651}
3652
3653static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
3654{
3655 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
3656 struct platform_device *pdev = to_platform_device(dev);
3657 struct drm_device *drm = dev_get_drvdata(master);
3658 struct vc4_hdmi *vc4_hdmi;
3659 struct drm_encoder *encoder;
3660 struct device_node *ddc_node;
3661 int ret;
3662
3663 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
3664 if (!vc4_hdmi)
3665 return -ENOMEM;
3666
3667 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex);
3668 if (ret)
3669 return ret;
3670
3671 spin_lock_init(&vc4_hdmi->hw_lock);
3672 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
3673
3674 dev_set_drvdata(dev, vc4_hdmi);
3675 encoder = &vc4_hdmi->encoder.base;
3676 vc4_hdmi->encoder.type = variant->encoder_type;
3677 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
3678 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
3679 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
3680 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
3681 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
3682 vc4_hdmi->pdev = pdev;
3683 vc4_hdmi->variant = variant;
3684
3685 /*
3686 * Since we don't know the state of the controller and its
3687 * display (if any), let's assume it's always enabled.
3688 * vc4_hdmi_disable_scrambling() will thus run at boot, make
3689 * sure it's disabled, and avoid any inconsistency.
3690 */
3691 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
3692 vc4_hdmi->scdc_enabled = true;
3693
3694 ret = variant->init_resources(drm, vc4_hdmi);
3695 if (ret)
3696 return ret;
3697
3698 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3699 if (!ddc_node) {
3700 DRM_ERROR("Failed to find ddc node in device tree\n");
3701 return -ENODEV;
3702 }
3703
3704 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3705 of_node_put(ddc_node);
3706 if (!vc4_hdmi->ddc) {
3707 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
3708 return -EPROBE_DEFER;
3709 }
3710
3711 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
3712 if (ret)
3713 return ret;
3714
3715 /* Only use the GPIO HPD pin if present in the DT, otherwise
3716 * we'll use the HDMI core's register.
3717 */
3718 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3719 if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3720 return PTR_ERR(vc4_hdmi->hpd_gpio);
3721 }
3722
3723 vc4_hdmi->disable_wifi_frequencies =
3724 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3725
3726 ret = devm_pm_runtime_enable(dev);
3727 if (ret)
3728 return ret;
3729
3730 /*
3731 * We need to have the device powered up at this point to call
3732 * our reset hook and for the CEC init.
3733 */
3734 ret = pm_runtime_resume_and_get(dev);
3735 if (ret)
3736 return ret;
3737
3738 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3739 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
3740 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3741 clk_prepare_enable(vc4_hdmi->pixel_clock);
3742 clk_prepare_enable(vc4_hdmi->hsm_clock);
3743 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3744 }
3745
3746 ret = drmm_encoder_init(drm, encoder,
3747 &vc4_hdmi_encoder_funcs,
3748 DRM_MODE_ENCODER_TMDS,
3749 NULL);
3750 if (ret)
3751 goto err_put_runtime_pm;
3752
3753 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3754
3755 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3756 if (ret)
3757 goto err_put_runtime_pm;
3758
3759 ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3760 if (ret)
3761 goto err_put_runtime_pm;
3762
3763 ret = vc4_hdmi_cec_init(vc4_hdmi);
3764 if (ret)
3765 goto err_put_runtime_pm;
3766
3767 ret = vc4_hdmi_audio_init(vc4_hdmi);
3768 if (ret)
3769 goto err_put_runtime_pm;
3770
3771 pm_runtime_put_sync(dev);
3772
3773 return 0;
3774
3775err_put_runtime_pm:
3776 pm_runtime_put_sync(dev);
3777
3778 return ret;
3779}
3780
3781static const struct component_ops vc4_hdmi_ops = {
3782 .bind = vc4_hdmi_bind,
3783};
3784
3785static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3786{
3787 return component_add(&pdev->dev, &vc4_hdmi_ops);
3788}
3789
3790static void vc4_hdmi_dev_remove(struct platform_device *pdev)
3791{
3792 component_del(&pdev->dev, &vc4_hdmi_ops);
3793}
3794
3795static const struct vc4_hdmi_variant bcm2835_variant = {
3796 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3797 .debugfs_name = "hdmi_regs",
3798 .card_name = "vc4-hdmi",
3799 .max_pixel_clock = 162000000,
3800 .registers = vc4_hdmi_fields,
3801 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
3802
3803 .init_resources = vc4_hdmi_init_resources,
3804 .csc_setup = vc4_hdmi_csc_setup,
3805 .reset = vc4_hdmi_reset,
3806 .set_timings = vc4_hdmi_set_timings,
3807 .phy_init = vc4_hdmi_phy_init,
3808 .phy_disable = vc4_hdmi_phy_disable,
3809 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
3810 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
3811 .channel_map = vc4_hdmi_channel_map,
3812 .supports_hdr = false,
3813};
3814
3815static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3816 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3817 .debugfs_name = "hdmi0_regs",
3818 .card_name = "vc4-hdmi-0",
3819 .max_pixel_clock = 600000000,
3820 .registers = vc5_hdmi_hdmi0_fields,
3821 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3822 .phy_lane_mapping = {
3823 PHY_LANE_0,
3824 PHY_LANE_1,
3825 PHY_LANE_2,
3826 PHY_LANE_CK,
3827 },
3828 .unsupported_odd_h_timings = true,
3829 .external_irq_controller = true,
3830
3831 .init_resources = vc5_hdmi_init_resources,
3832 .csc_setup = vc5_hdmi_csc_setup,
3833 .reset = vc5_hdmi_reset,
3834 .set_timings = vc5_hdmi_set_timings,
3835 .phy_init = vc5_hdmi_phy_init,
3836 .phy_disable = vc5_hdmi_phy_disable,
3837 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3838 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3839 .channel_map = vc5_hdmi_channel_map,
3840 .supports_hdr = true,
3841 .hp_detect = vc5_hdmi_hp_detect,
3842};
3843
3844static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3845 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
3846 .debugfs_name = "hdmi1_regs",
3847 .card_name = "vc4-hdmi-1",
3848 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
3849 .registers = vc5_hdmi_hdmi1_fields,
3850 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3851 .phy_lane_mapping = {
3852 PHY_LANE_1,
3853 PHY_LANE_0,
3854 PHY_LANE_CK,
3855 PHY_LANE_2,
3856 },
3857 .unsupported_odd_h_timings = true,
3858 .external_irq_controller = true,
3859
3860 .init_resources = vc5_hdmi_init_resources,
3861 .csc_setup = vc5_hdmi_csc_setup,
3862 .reset = vc5_hdmi_reset,
3863 .set_timings = vc5_hdmi_set_timings,
3864 .phy_init = vc5_hdmi_phy_init,
3865 .phy_disable = vc5_hdmi_phy_disable,
3866 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3867 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3868 .channel_map = vc5_hdmi_channel_map,
3869 .supports_hdr = true,
3870 .hp_detect = vc5_hdmi_hp_detect,
3871};
3872
3873static const struct of_device_id vc4_hdmi_dt_match[] = {
3874 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3875 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3876 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3877 {}
3878};
3879
3880static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3881 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3882 vc4_hdmi_runtime_resume,
3883 NULL)
3884};
3885
3886struct platform_driver vc4_hdmi_driver = {
3887 .probe = vc4_hdmi_dev_probe,
3888 .remove_new = vc4_hdmi_dev_remove,
3889 .driver = {
3890 .name = "vc4_hdmi",
3891 .of_match_table = vc4_hdmi_dt_match,
3892 .pm = &vc4_hdmi_pm_ops,
3893 },
3894};