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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8#include <linux/dma-mapping.h>
9#include <linux/fault-inject.h>
10#include <linux/debugfs.h>
11#include <linux/of_address.h>
12#include <linux/uaccess.h>
13
14#include <drm/drm_client_setup.h>
15#include <drm/drm_drv.h>
16#include <drm/drm_file.h>
17#include <drm/drm_ioctl.h>
18#include <drm/drm_of.h>
19
20#include "msm_drv.h"
21#include "msm_debugfs.h"
22#include "msm_gem.h"
23#include "msm_gpu.h"
24#include "msm_kms.h"
25
26/*
27 * MSM driver version:
28 * - 1.0.0 - initial interface
29 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
30 * - 1.2.0 - adds explicit fence support for submit ioctl
31 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
32 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
33 * MSM_GEM_INFO ioctl.
34 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
35 * GEM object's debug name
36 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
37 * - 1.6.0 - Syncobj support
38 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
39 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
40 * - 1.9.0 - Add MSM_SUBMIT_FENCE_SN_IN
41 * - 1.10.0 - Add MSM_SUBMIT_BO_NO_IMPLICIT
42 * - 1.11.0 - Add wait boost (MSM_WAIT_FENCE_BOOST, MSM_PREP_BOOST)
43 * - 1.12.0 - Add MSM_INFO_SET_METADATA and MSM_INFO_GET_METADATA
44 */
45#define MSM_VERSION_MAJOR 1
46#define MSM_VERSION_MINOR 12
47#define MSM_VERSION_PATCHLEVEL 0
48
49static void msm_deinit_vram(struct drm_device *ddev);
50
51static char *vram = "16m";
52MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
53module_param(vram, charp, 0);
54
55bool dumpstate;
56MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
57module_param(dumpstate, bool, 0600);
58
59static bool modeset = true;
60MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
61module_param(modeset, bool, 0600);
62
63DECLARE_FAULT_ATTR(fail_gem_alloc);
64DECLARE_FAULT_ATTR(fail_gem_iova);
65
66static int msm_drm_uninit(struct device *dev)
67{
68 struct platform_device *pdev = to_platform_device(dev);
69 struct msm_drm_private *priv = platform_get_drvdata(pdev);
70 struct drm_device *ddev = priv->dev;
71
72 /*
73 * Shutdown the hw if we're far enough along where things might be on.
74 * If we run this too early, we'll end up panicking in any variety of
75 * places. Since we don't register the drm device until late in
76 * msm_drm_init, drm_dev->registered is used as an indicator that the
77 * shutdown will be successful.
78 */
79 if (ddev->registered) {
80 drm_dev_unregister(ddev);
81 if (priv->kms)
82 drm_atomic_helper_shutdown(ddev);
83 }
84
85 /* We must cancel and cleanup any pending vblank enable/disable
86 * work before msm_irq_uninstall() to avoid work re-enabling an
87 * irq after uninstall has disabled it.
88 */
89
90 flush_workqueue(priv->wq);
91
92 msm_gem_shrinker_cleanup(ddev);
93
94 msm_perf_debugfs_cleanup(priv);
95 msm_rd_debugfs_cleanup(priv);
96
97 if (priv->kms)
98 msm_drm_kms_uninit(dev);
99
100 msm_deinit_vram(ddev);
101
102 component_unbind_all(dev, ddev);
103
104 ddev->dev_private = NULL;
105 drm_dev_put(ddev);
106
107 destroy_workqueue(priv->wq);
108
109 return 0;
110}
111
112bool msm_use_mmu(struct drm_device *dev)
113{
114 struct msm_drm_private *priv = dev->dev_private;
115
116 /*
117 * a2xx comes with its own MMU
118 * On other platforms IOMMU can be declared specified either for the
119 * MDP/DPU device or for its parent, MDSS device.
120 */
121 return priv->is_a2xx ||
122 device_iommu_mapped(dev->dev) ||
123 device_iommu_mapped(dev->dev->parent);
124}
125
126static int msm_init_vram(struct drm_device *dev)
127{
128 struct msm_drm_private *priv = dev->dev_private;
129 struct device_node *node;
130 unsigned long size = 0;
131 int ret = 0;
132
133 /* In the device-tree world, we could have a 'memory-region'
134 * phandle, which gives us a link to our "vram". Allocating
135 * is all nicely abstracted behind the dma api, but we need
136 * to know the entire size to allocate it all in one go. There
137 * are two cases:
138 * 1) device with no IOMMU, in which case we need exclusive
139 * access to a VRAM carveout big enough for all gpu
140 * buffers
141 * 2) device with IOMMU, but where the bootloader puts up
142 * a splash screen. In this case, the VRAM carveout
143 * need only be large enough for fbdev fb. But we need
144 * exclusive access to the buffer to avoid the kernel
145 * using those pages for other purposes (which appears
146 * as corruption on screen before we have a chance to
147 * load and do initial modeset)
148 */
149
150 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
151 if (node) {
152 struct resource r;
153 ret = of_address_to_resource(node, 0, &r);
154 of_node_put(node);
155 if (ret)
156 return ret;
157 size = r.end - r.start + 1;
158 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
159
160 /* if we have no IOMMU, then we need to use carveout allocator.
161 * Grab the entire DMA chunk carved out in early startup in
162 * mach-msm:
163 */
164 } else if (!msm_use_mmu(dev)) {
165 DRM_INFO("using %s VRAM carveout\n", vram);
166 size = memparse(vram, NULL);
167 }
168
169 if (size) {
170 unsigned long attrs = 0;
171 void *p;
172
173 priv->vram.size = size;
174
175 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
176 spin_lock_init(&priv->vram.lock);
177
178 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
179 attrs |= DMA_ATTR_WRITE_COMBINE;
180
181 /* note that for no-kernel-mapping, the vaddr returned
182 * is bogus, but non-null if allocation succeeded:
183 */
184 p = dma_alloc_attrs(dev->dev, size,
185 &priv->vram.paddr, GFP_KERNEL, attrs);
186 if (!p) {
187 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
188 priv->vram.paddr = 0;
189 return -ENOMEM;
190 }
191
192 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
193 (uint32_t)priv->vram.paddr,
194 (uint32_t)(priv->vram.paddr + size));
195 }
196
197 return ret;
198}
199
200static void msm_deinit_vram(struct drm_device *ddev)
201{
202 struct msm_drm_private *priv = ddev->dev_private;
203 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
204
205 if (!priv->vram.paddr)
206 return;
207
208 drm_mm_takedown(&priv->vram.mm);
209 dma_free_attrs(ddev->dev, priv->vram.size, NULL, priv->vram.paddr,
210 attrs);
211}
212
213static int msm_drm_init(struct device *dev, const struct drm_driver *drv)
214{
215 struct msm_drm_private *priv = dev_get_drvdata(dev);
216 struct drm_device *ddev;
217 int ret;
218
219 if (drm_firmware_drivers_only())
220 return -ENODEV;
221
222 ddev = drm_dev_alloc(drv, dev);
223 if (IS_ERR(ddev)) {
224 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
225 return PTR_ERR(ddev);
226 }
227 ddev->dev_private = priv;
228 priv->dev = ddev;
229
230 priv->wq = alloc_ordered_workqueue("msm", 0);
231 if (!priv->wq) {
232 ret = -ENOMEM;
233 goto err_put_dev;
234 }
235
236 INIT_LIST_HEAD(&priv->objects);
237 mutex_init(&priv->obj_lock);
238
239 /*
240 * Initialize the LRUs:
241 */
242 mutex_init(&priv->lru.lock);
243 drm_gem_lru_init(&priv->lru.unbacked, &priv->lru.lock);
244 drm_gem_lru_init(&priv->lru.pinned, &priv->lru.lock);
245 drm_gem_lru_init(&priv->lru.willneed, &priv->lru.lock);
246 drm_gem_lru_init(&priv->lru.dontneed, &priv->lru.lock);
247
248 /* Teach lockdep about lock ordering wrt. shrinker: */
249 fs_reclaim_acquire(GFP_KERNEL);
250 might_lock(&priv->lru.lock);
251 fs_reclaim_release(GFP_KERNEL);
252
253 if (priv->kms_init) {
254 ret = drmm_mode_config_init(ddev);
255 if (ret)
256 goto err_destroy_wq;
257 }
258
259 ret = msm_init_vram(ddev);
260 if (ret)
261 goto err_destroy_wq;
262
263 dma_set_max_seg_size(dev, UINT_MAX);
264
265 /* Bind all our sub-components: */
266 ret = component_bind_all(dev, ddev);
267 if (ret)
268 goto err_deinit_vram;
269
270 ret = msm_gem_shrinker_init(ddev);
271 if (ret)
272 goto err_msm_uninit;
273
274 if (priv->kms_init) {
275 ret = msm_drm_kms_init(dev, drv);
276 if (ret)
277 goto err_msm_uninit;
278 } else {
279 /* valid only for the dummy headless case, where of_node=NULL */
280 WARN_ON(dev->of_node);
281 ddev->driver_features &= ~DRIVER_MODESET;
282 ddev->driver_features &= ~DRIVER_ATOMIC;
283 }
284
285 ret = drm_dev_register(ddev, 0);
286 if (ret)
287 goto err_msm_uninit;
288
289 ret = msm_debugfs_late_init(ddev);
290 if (ret)
291 goto err_msm_uninit;
292
293 if (priv->kms_init) {
294 drm_kms_helper_poll_init(ddev);
295 drm_client_setup(ddev, NULL);
296 }
297
298 return 0;
299
300err_msm_uninit:
301 msm_drm_uninit(dev);
302
303 return ret;
304
305err_deinit_vram:
306 msm_deinit_vram(ddev);
307err_destroy_wq:
308 destroy_workqueue(priv->wq);
309err_put_dev:
310 drm_dev_put(ddev);
311
312 return ret;
313}
314
315/*
316 * DRM operations:
317 */
318
319static void load_gpu(struct drm_device *dev)
320{
321 static DEFINE_MUTEX(init_lock);
322 struct msm_drm_private *priv = dev->dev_private;
323
324 mutex_lock(&init_lock);
325
326 if (!priv->gpu)
327 priv->gpu = adreno_load_gpu(dev);
328
329 mutex_unlock(&init_lock);
330}
331
332static int context_init(struct drm_device *dev, struct drm_file *file)
333{
334 static atomic_t ident = ATOMIC_INIT(0);
335 struct msm_drm_private *priv = dev->dev_private;
336 struct msm_file_private *ctx;
337
338 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
339 if (!ctx)
340 return -ENOMEM;
341
342 INIT_LIST_HEAD(&ctx->submitqueues);
343 rwlock_init(&ctx->queuelock);
344
345 kref_init(&ctx->ref);
346 msm_submitqueue_init(dev, ctx);
347
348 ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current);
349 file->driver_priv = ctx;
350
351 ctx->seqno = atomic_inc_return(&ident);
352
353 return 0;
354}
355
356static int msm_open(struct drm_device *dev, struct drm_file *file)
357{
358 /* For now, load gpu on open.. to avoid the requirement of having
359 * firmware in the initrd.
360 */
361 load_gpu(dev);
362
363 return context_init(dev, file);
364}
365
366static void context_close(struct msm_file_private *ctx)
367{
368 msm_submitqueue_close(ctx);
369 msm_file_private_put(ctx);
370}
371
372static void msm_postclose(struct drm_device *dev, struct drm_file *file)
373{
374 struct msm_drm_private *priv = dev->dev_private;
375 struct msm_file_private *ctx = file->driver_priv;
376
377 /*
378 * It is not possible to set sysprof param to non-zero if gpu
379 * is not initialized:
380 */
381 if (priv->gpu)
382 msm_file_private_set_sysprof(ctx, priv->gpu, 0);
383
384 context_close(ctx);
385}
386
387/*
388 * DRM ioctls:
389 */
390
391static int msm_ioctl_get_param(struct drm_device *dev, void *data,
392 struct drm_file *file)
393{
394 struct msm_drm_private *priv = dev->dev_private;
395 struct drm_msm_param *args = data;
396 struct msm_gpu *gpu;
397
398 /* for now, we just have 3d pipe.. eventually this would need to
399 * be more clever to dispatch to appropriate gpu module:
400 */
401 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0))
402 return -EINVAL;
403
404 gpu = priv->gpu;
405
406 if (!gpu)
407 return -ENXIO;
408
409 return gpu->funcs->get_param(gpu, file->driver_priv,
410 args->param, &args->value, &args->len);
411}
412
413static int msm_ioctl_set_param(struct drm_device *dev, void *data,
414 struct drm_file *file)
415{
416 struct msm_drm_private *priv = dev->dev_private;
417 struct drm_msm_param *args = data;
418 struct msm_gpu *gpu;
419
420 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0))
421 return -EINVAL;
422
423 gpu = priv->gpu;
424
425 if (!gpu)
426 return -ENXIO;
427
428 return gpu->funcs->set_param(gpu, file->driver_priv,
429 args->param, args->value, args->len);
430}
431
432static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
433 struct drm_file *file)
434{
435 struct drm_msm_gem_new *args = data;
436 uint32_t flags = args->flags;
437
438 if (args->flags & ~MSM_BO_FLAGS) {
439 DRM_ERROR("invalid flags: %08x\n", args->flags);
440 return -EINVAL;
441 }
442
443 /*
444 * Uncached CPU mappings are deprecated, as of:
445 *
446 * 9ef364432db4 ("drm/msm: deprecate MSM_BO_UNCACHED (map as writecombine instead)")
447 *
448 * So promote them to WC.
449 */
450 if (flags & MSM_BO_UNCACHED) {
451 flags &= ~MSM_BO_CACHED;
452 flags |= MSM_BO_WC;
453 }
454
455 if (should_fail(&fail_gem_alloc, args->size))
456 return -ENOMEM;
457
458 return msm_gem_new_handle(dev, file, args->size,
459 args->flags, &args->handle, NULL);
460}
461
462static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
463{
464 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
465}
466
467static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
468 struct drm_file *file)
469{
470 struct drm_msm_gem_cpu_prep *args = data;
471 struct drm_gem_object *obj;
472 ktime_t timeout = to_ktime(args->timeout);
473 int ret;
474
475 if (args->op & ~MSM_PREP_FLAGS) {
476 DRM_ERROR("invalid op: %08x\n", args->op);
477 return -EINVAL;
478 }
479
480 obj = drm_gem_object_lookup(file, args->handle);
481 if (!obj)
482 return -ENOENT;
483
484 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
485
486 drm_gem_object_put(obj);
487
488 return ret;
489}
490
491static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
492 struct drm_file *file)
493{
494 struct drm_msm_gem_cpu_fini *args = data;
495 struct drm_gem_object *obj;
496 int ret;
497
498 obj = drm_gem_object_lookup(file, args->handle);
499 if (!obj)
500 return -ENOENT;
501
502 ret = msm_gem_cpu_fini(obj);
503
504 drm_gem_object_put(obj);
505
506 return ret;
507}
508
509static int msm_ioctl_gem_info_iova(struct drm_device *dev,
510 struct drm_file *file, struct drm_gem_object *obj,
511 uint64_t *iova)
512{
513 struct msm_drm_private *priv = dev->dev_private;
514 struct msm_file_private *ctx = file->driver_priv;
515
516 if (!priv->gpu)
517 return -EINVAL;
518
519 if (should_fail(&fail_gem_iova, obj->size))
520 return -ENOMEM;
521
522 /*
523 * Don't pin the memory here - just get an address so that userspace can
524 * be productive
525 */
526 return msm_gem_get_iova(obj, ctx->aspace, iova);
527}
528
529static int msm_ioctl_gem_info_set_iova(struct drm_device *dev,
530 struct drm_file *file, struct drm_gem_object *obj,
531 uint64_t iova)
532{
533 struct msm_drm_private *priv = dev->dev_private;
534 struct msm_file_private *ctx = file->driver_priv;
535
536 if (!priv->gpu)
537 return -EINVAL;
538
539 /* Only supported if per-process address space is supported: */
540 if (priv->gpu->aspace == ctx->aspace)
541 return -EOPNOTSUPP;
542
543 if (should_fail(&fail_gem_iova, obj->size))
544 return -ENOMEM;
545
546 return msm_gem_set_iova(obj, ctx->aspace, iova);
547}
548
549static int msm_ioctl_gem_info_set_metadata(struct drm_gem_object *obj,
550 __user void *metadata,
551 u32 metadata_size)
552{
553 struct msm_gem_object *msm_obj = to_msm_bo(obj);
554 void *buf;
555 int ret;
556
557 /* Impose a moderate upper bound on metadata size: */
558 if (metadata_size > 128) {
559 return -EOVERFLOW;
560 }
561
562 /* Use a temporary buf to keep copy_from_user() outside of gem obj lock: */
563 buf = memdup_user(metadata, metadata_size);
564 if (IS_ERR(buf))
565 return PTR_ERR(buf);
566
567 ret = msm_gem_lock_interruptible(obj);
568 if (ret)
569 goto out;
570
571 msm_obj->metadata =
572 krealloc(msm_obj->metadata, metadata_size, GFP_KERNEL);
573 msm_obj->metadata_size = metadata_size;
574 memcpy(msm_obj->metadata, buf, metadata_size);
575
576 msm_gem_unlock(obj);
577
578out:
579 kfree(buf);
580
581 return ret;
582}
583
584static int msm_ioctl_gem_info_get_metadata(struct drm_gem_object *obj,
585 __user void *metadata,
586 u32 *metadata_size)
587{
588 struct msm_gem_object *msm_obj = to_msm_bo(obj);
589 void *buf;
590 int ret, len;
591
592 if (!metadata) {
593 /*
594 * Querying the size is inherently racey, but
595 * EXT_external_objects expects the app to confirm
596 * via device and driver UUIDs that the exporter and
597 * importer versions match. All we can do from the
598 * kernel side is check the length under obj lock
599 * when userspace tries to retrieve the metadata
600 */
601 *metadata_size = msm_obj->metadata_size;
602 return 0;
603 }
604
605 ret = msm_gem_lock_interruptible(obj);
606 if (ret)
607 return ret;
608
609 /* Avoid copy_to_user() under gem obj lock: */
610 len = msm_obj->metadata_size;
611 buf = kmemdup(msm_obj->metadata, len, GFP_KERNEL);
612
613 msm_gem_unlock(obj);
614
615 if (*metadata_size < len) {
616 ret = -ETOOSMALL;
617 } else if (copy_to_user(metadata, buf, len)) {
618 ret = -EFAULT;
619 } else {
620 *metadata_size = len;
621 }
622
623 kfree(buf);
624
625 return 0;
626}
627
628static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
629 struct drm_file *file)
630{
631 struct drm_msm_gem_info *args = data;
632 struct drm_gem_object *obj;
633 struct msm_gem_object *msm_obj;
634 int i, ret = 0;
635
636 if (args->pad)
637 return -EINVAL;
638
639 switch (args->info) {
640 case MSM_INFO_GET_OFFSET:
641 case MSM_INFO_GET_IOVA:
642 case MSM_INFO_SET_IOVA:
643 case MSM_INFO_GET_FLAGS:
644 /* value returned as immediate, not pointer, so len==0: */
645 if (args->len)
646 return -EINVAL;
647 break;
648 case MSM_INFO_SET_NAME:
649 case MSM_INFO_GET_NAME:
650 case MSM_INFO_SET_METADATA:
651 case MSM_INFO_GET_METADATA:
652 break;
653 default:
654 return -EINVAL;
655 }
656
657 obj = drm_gem_object_lookup(file, args->handle);
658 if (!obj)
659 return -ENOENT;
660
661 msm_obj = to_msm_bo(obj);
662
663 switch (args->info) {
664 case MSM_INFO_GET_OFFSET:
665 args->value = msm_gem_mmap_offset(obj);
666 break;
667 case MSM_INFO_GET_IOVA:
668 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value);
669 break;
670 case MSM_INFO_SET_IOVA:
671 ret = msm_ioctl_gem_info_set_iova(dev, file, obj, args->value);
672 break;
673 case MSM_INFO_GET_FLAGS:
674 if (obj->import_attach) {
675 ret = -EINVAL;
676 break;
677 }
678 /* Hide internal kernel-only flags: */
679 args->value = to_msm_bo(obj)->flags & MSM_BO_FLAGS;
680 ret = 0;
681 break;
682 case MSM_INFO_SET_NAME:
683 /* length check should leave room for terminating null: */
684 if (args->len >= sizeof(msm_obj->name)) {
685 ret = -EINVAL;
686 break;
687 }
688 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
689 args->len)) {
690 msm_obj->name[0] = '\0';
691 ret = -EFAULT;
692 break;
693 }
694 msm_obj->name[args->len] = '\0';
695 for (i = 0; i < args->len; i++) {
696 if (!isprint(msm_obj->name[i])) {
697 msm_obj->name[i] = '\0';
698 break;
699 }
700 }
701 break;
702 case MSM_INFO_GET_NAME:
703 if (args->value && (args->len < strlen(msm_obj->name))) {
704 ret = -ETOOSMALL;
705 break;
706 }
707 args->len = strlen(msm_obj->name);
708 if (args->value) {
709 if (copy_to_user(u64_to_user_ptr(args->value),
710 msm_obj->name, args->len))
711 ret = -EFAULT;
712 }
713 break;
714 case MSM_INFO_SET_METADATA:
715 ret = msm_ioctl_gem_info_set_metadata(
716 obj, u64_to_user_ptr(args->value), args->len);
717 break;
718 case MSM_INFO_GET_METADATA:
719 ret = msm_ioctl_gem_info_get_metadata(
720 obj, u64_to_user_ptr(args->value), &args->len);
721 break;
722 }
723
724 drm_gem_object_put(obj);
725
726 return ret;
727}
728
729static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id,
730 ktime_t timeout, uint32_t flags)
731{
732 struct dma_fence *fence;
733 int ret;
734
735 if (fence_after(fence_id, queue->last_fence)) {
736 DRM_ERROR_RATELIMITED("waiting on invalid fence: %u (of %u)\n",
737 fence_id, queue->last_fence);
738 return -EINVAL;
739 }
740
741 /*
742 * Map submitqueue scoped "seqno" (which is actually an idr key)
743 * back to underlying dma-fence
744 *
745 * The fence is removed from the fence_idr when the submit is
746 * retired, so if the fence is not found it means there is nothing
747 * to wait for
748 */
749 spin_lock(&queue->idr_lock);
750 fence = idr_find(&queue->fence_idr, fence_id);
751 if (fence)
752 fence = dma_fence_get_rcu(fence);
753 spin_unlock(&queue->idr_lock);
754
755 if (!fence)
756 return 0;
757
758 if (flags & MSM_WAIT_FENCE_BOOST)
759 dma_fence_set_deadline(fence, ktime_get());
760
761 ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout));
762 if (ret == 0) {
763 ret = -ETIMEDOUT;
764 } else if (ret != -ERESTARTSYS) {
765 ret = 0;
766 }
767
768 dma_fence_put(fence);
769
770 return ret;
771}
772
773static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
774 struct drm_file *file)
775{
776 struct msm_drm_private *priv = dev->dev_private;
777 struct drm_msm_wait_fence *args = data;
778 struct msm_gpu_submitqueue *queue;
779 int ret;
780
781 if (args->flags & ~MSM_WAIT_FENCE_FLAGS) {
782 DRM_ERROR("invalid flags: %08x\n", args->flags);
783 return -EINVAL;
784 }
785
786 if (!priv->gpu)
787 return 0;
788
789 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
790 if (!queue)
791 return -ENOENT;
792
793 ret = wait_fence(queue, args->fence, to_ktime(args->timeout), args->flags);
794
795 msm_submitqueue_put(queue);
796
797 return ret;
798}
799
800static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
801 struct drm_file *file)
802{
803 struct drm_msm_gem_madvise *args = data;
804 struct drm_gem_object *obj;
805 int ret;
806
807 switch (args->madv) {
808 case MSM_MADV_DONTNEED:
809 case MSM_MADV_WILLNEED:
810 break;
811 default:
812 return -EINVAL;
813 }
814
815 obj = drm_gem_object_lookup(file, args->handle);
816 if (!obj) {
817 return -ENOENT;
818 }
819
820 ret = msm_gem_madvise(obj, args->madv);
821 if (ret >= 0) {
822 args->retained = ret;
823 ret = 0;
824 }
825
826 drm_gem_object_put(obj);
827
828 return ret;
829}
830
831
832static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
833 struct drm_file *file)
834{
835 struct drm_msm_submitqueue *args = data;
836
837 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
838 return -EINVAL;
839
840 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
841 args->flags, &args->id);
842}
843
844static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
845 struct drm_file *file)
846{
847 return msm_submitqueue_query(dev, file->driver_priv, data);
848}
849
850static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
851 struct drm_file *file)
852{
853 u32 id = *(u32 *) data;
854
855 return msm_submitqueue_remove(file->driver_priv, id);
856}
857
858static const struct drm_ioctl_desc msm_ioctls[] = {
859 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW),
860 DRM_IOCTL_DEF_DRV(MSM_SET_PARAM, msm_ioctl_set_param, DRM_RENDER_ALLOW),
861 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW),
862 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW),
863 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
864 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
865 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW),
866 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW),
867 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW),
868 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW),
869 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
870 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
871};
872
873static void msm_show_fdinfo(struct drm_printer *p, struct drm_file *file)
874{
875 struct drm_device *dev = file->minor->dev;
876 struct msm_drm_private *priv = dev->dev_private;
877
878 if (!priv->gpu)
879 return;
880
881 msm_gpu_show_fdinfo(priv->gpu, file->driver_priv, p);
882
883 drm_show_memory_stats(p, file);
884}
885
886static const struct file_operations fops = {
887 .owner = THIS_MODULE,
888 DRM_GEM_FOPS,
889 .show_fdinfo = drm_show_fdinfo,
890};
891
892static const struct drm_driver msm_driver = {
893 .driver_features = DRIVER_GEM |
894 DRIVER_RENDER |
895 DRIVER_ATOMIC |
896 DRIVER_MODESET |
897 DRIVER_SYNCOBJ,
898 .open = msm_open,
899 .postclose = msm_postclose,
900 .dumb_create = msm_gem_dumb_create,
901 .dumb_map_offset = msm_gem_dumb_map_offset,
902 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
903#ifdef CONFIG_DEBUG_FS
904 .debugfs_init = msm_debugfs_init,
905#endif
906 MSM_FBDEV_DRIVER_OPS,
907 .show_fdinfo = msm_show_fdinfo,
908 .ioctls = msm_ioctls,
909 .num_ioctls = ARRAY_SIZE(msm_ioctls),
910 .fops = &fops,
911 .name = "msm",
912 .desc = "MSM Snapdragon DRM",
913 .date = "20130625",
914 .major = MSM_VERSION_MAJOR,
915 .minor = MSM_VERSION_MINOR,
916 .patchlevel = MSM_VERSION_PATCHLEVEL,
917};
918
919/*
920 * Componentized driver support:
921 */
922
923/*
924 * Identify what components need to be added by parsing what remote-endpoints
925 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
926 * is no external component that we need to add since LVDS is within MDP4
927 * itself.
928 */
929static int add_components_mdp(struct device *master_dev,
930 struct component_match **matchptr)
931{
932 struct device_node *np = master_dev->of_node;
933 struct device_node *ep_node;
934
935 for_each_endpoint_of_node(np, ep_node) {
936 struct device_node *intf;
937 struct of_endpoint ep;
938 int ret;
939
940 ret = of_graph_parse_endpoint(ep_node, &ep);
941 if (ret) {
942 DRM_DEV_ERROR(master_dev, "unable to parse port endpoint\n");
943 of_node_put(ep_node);
944 return ret;
945 }
946
947 /*
948 * The LCDC/LVDS port on MDP4 is a speacial case where the
949 * remote-endpoint isn't a component that we need to add
950 */
951 if (of_device_is_compatible(np, "qcom,mdp4") &&
952 ep.port == 0)
953 continue;
954
955 /*
956 * It's okay if some of the ports don't have a remote endpoint
957 * specified. It just means that the port isn't connected to
958 * any external interface.
959 */
960 intf = of_graph_get_remote_port_parent(ep_node);
961 if (!intf)
962 continue;
963
964 if (of_device_is_available(intf))
965 drm_of_component_match_add(master_dev, matchptr,
966 component_compare_of, intf);
967
968 of_node_put(intf);
969 }
970
971 return 0;
972}
973
974#if !IS_REACHABLE(CONFIG_DRM_MSM_MDP5) || !IS_REACHABLE(CONFIG_DRM_MSM_DPU)
975bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver)
976{
977 /* If just a single driver is enabled, use it no matter what */
978 return true;
979}
980#else
981
982static bool prefer_mdp5 = true;
983MODULE_PARM_DESC(prefer_mdp5, "Select whether MDP5 or DPU driver should be preferred");
984module_param(prefer_mdp5, bool, 0444);
985
986/* list all platforms supported by both mdp5 and dpu drivers */
987static const char *const msm_mdp5_dpu_migration[] = {
988 "qcom,msm8917-mdp5",
989 "qcom,msm8937-mdp5",
990 "qcom,msm8953-mdp5",
991 "qcom,msm8996-mdp5",
992 "qcom,sdm630-mdp5",
993 "qcom,sdm660-mdp5",
994 NULL,
995};
996
997bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver)
998{
999 /* If it is not an MDP5 device, do not try MDP5 driver */
1000 if (!of_device_is_compatible(dev->of_node, "qcom,mdp5"))
1001 return dpu_driver;
1002
1003 /* If it is not in the migration list, use MDP5 */
1004 if (!of_device_compatible_match(dev->of_node, msm_mdp5_dpu_migration))
1005 return !dpu_driver;
1006
1007 return prefer_mdp5 ? !dpu_driver : dpu_driver;
1008}
1009#endif
1010
1011/*
1012 * We don't know what's the best binding to link the gpu with the drm device.
1013 * Fow now, we just hunt for all the possible gpus that we support, and add them
1014 * as components.
1015 */
1016static const struct of_device_id msm_gpu_match[] = {
1017 { .compatible = "qcom,adreno" },
1018 { .compatible = "qcom,adreno-3xx" },
1019 { .compatible = "amd,imageon" },
1020 { .compatible = "qcom,kgsl-3d0" },
1021 { },
1022};
1023
1024static int add_gpu_components(struct device *dev,
1025 struct component_match **matchptr)
1026{
1027 struct device_node *np;
1028
1029 np = of_find_matching_node(NULL, msm_gpu_match);
1030 if (!np)
1031 return 0;
1032
1033 if (of_device_is_available(np))
1034 drm_of_component_match_add(dev, matchptr, component_compare_of, np);
1035
1036 of_node_put(np);
1037
1038 return 0;
1039}
1040
1041static int msm_drm_bind(struct device *dev)
1042{
1043 return msm_drm_init(dev, &msm_driver);
1044}
1045
1046static void msm_drm_unbind(struct device *dev)
1047{
1048 msm_drm_uninit(dev);
1049}
1050
1051const struct component_master_ops msm_drm_ops = {
1052 .bind = msm_drm_bind,
1053 .unbind = msm_drm_unbind,
1054};
1055
1056int msm_drv_probe(struct device *master_dev,
1057 int (*kms_init)(struct drm_device *dev),
1058 struct msm_kms *kms)
1059{
1060 struct msm_drm_private *priv;
1061 struct component_match *match = NULL;
1062 int ret;
1063
1064 priv = devm_kzalloc(master_dev, sizeof(*priv), GFP_KERNEL);
1065 if (!priv)
1066 return -ENOMEM;
1067
1068 priv->kms = kms;
1069 priv->kms_init = kms_init;
1070 dev_set_drvdata(master_dev, priv);
1071
1072 /* Add mdp components if we have KMS. */
1073 if (kms_init) {
1074 ret = add_components_mdp(master_dev, &match);
1075 if (ret)
1076 return ret;
1077 }
1078
1079 ret = add_gpu_components(master_dev, &match);
1080 if (ret)
1081 return ret;
1082
1083 /* on all devices that I am aware of, iommu's which can map
1084 * any address the cpu can see are used:
1085 */
1086 ret = dma_set_mask_and_coherent(master_dev, ~0);
1087 if (ret)
1088 return ret;
1089
1090 ret = component_master_add_with_match(master_dev, &msm_drm_ops, match);
1091 if (ret)
1092 return ret;
1093
1094 return 0;
1095}
1096
1097/*
1098 * Platform driver:
1099 * Used only for headlesss GPU instances
1100 */
1101
1102static int msm_pdev_probe(struct platform_device *pdev)
1103{
1104 return msm_drv_probe(&pdev->dev, NULL, NULL);
1105}
1106
1107static void msm_pdev_remove(struct platform_device *pdev)
1108{
1109 component_master_del(&pdev->dev, &msm_drm_ops);
1110}
1111
1112static struct platform_driver msm_platform_driver = {
1113 .probe = msm_pdev_probe,
1114 .remove = msm_pdev_remove,
1115 .driver = {
1116 .name = "msm",
1117 },
1118};
1119
1120static int __init msm_drm_register(void)
1121{
1122 if (!modeset)
1123 return -EINVAL;
1124
1125 DBG("init");
1126 msm_mdp_register();
1127 msm_dpu_register();
1128 msm_dsi_register();
1129 msm_hdmi_register();
1130 msm_dp_register();
1131 adreno_register();
1132 msm_mdp4_register();
1133 msm_mdss_register();
1134 return platform_driver_register(&msm_platform_driver);
1135}
1136
1137static void __exit msm_drm_unregister(void)
1138{
1139 DBG("fini");
1140 platform_driver_unregister(&msm_platform_driver);
1141 msm_mdss_unregister();
1142 msm_mdp4_unregister();
1143 msm_dp_unregister();
1144 msm_hdmi_unregister();
1145 adreno_unregister();
1146 msm_dsi_unregister();
1147 msm_mdp_unregister();
1148 msm_dpu_unregister();
1149}
1150
1151module_init(msm_drm_register);
1152module_exit(msm_drm_unregister);
1153
1154MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1155MODULE_DESCRIPTION("MSM DRM Driver");
1156MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8#include <linux/dma-mapping.h>
9#include <linux/kthread.h>
10#include <linux/uaccess.h>
11#include <uapi/linux/sched/types.h>
12
13#include <drm/drm_drv.h>
14#include <drm/drm_file.h>
15#include <drm/drm_ioctl.h>
16#include <drm/drm_irq.h>
17#include <drm/drm_prime.h>
18#include <drm/drm_of.h>
19#include <drm/drm_vblank.h>
20
21#include "msm_drv.h"
22#include "msm_debugfs.h"
23#include "msm_fence.h"
24#include "msm_gem.h"
25#include "msm_gpu.h"
26#include "msm_kms.h"
27#include "adreno/adreno_gpu.h"
28
29/*
30 * MSM driver version:
31 * - 1.0.0 - initial interface
32 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
33 * - 1.2.0 - adds explicit fence support for submit ioctl
34 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
35 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
36 * MSM_GEM_INFO ioctl.
37 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
38 * GEM object's debug name
39 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
40 */
41#define MSM_VERSION_MAJOR 1
42#define MSM_VERSION_MINOR 5
43#define MSM_VERSION_PATCHLEVEL 0
44
45static const struct drm_mode_config_funcs mode_config_funcs = {
46 .fb_create = msm_framebuffer_create,
47 .output_poll_changed = drm_fb_helper_output_poll_changed,
48 .atomic_check = drm_atomic_helper_check,
49 .atomic_commit = drm_atomic_helper_commit,
50};
51
52static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
53 .atomic_commit_tail = msm_atomic_commit_tail,
54};
55
56#ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
57static bool reglog = false;
58MODULE_PARM_DESC(reglog, "Enable register read/write logging");
59module_param(reglog, bool, 0600);
60#else
61#define reglog 0
62#endif
63
64#ifdef CONFIG_DRM_FBDEV_EMULATION
65static bool fbdev = true;
66MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
67module_param(fbdev, bool, 0600);
68#endif
69
70static char *vram = "16m";
71MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
72module_param(vram, charp, 0);
73
74bool dumpstate = false;
75MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
76module_param(dumpstate, bool, 0600);
77
78static bool modeset = true;
79MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
80module_param(modeset, bool, 0600);
81
82/*
83 * Util/helpers:
84 */
85
86struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
87 const char *name)
88{
89 int i;
90 char n[32];
91
92 snprintf(n, sizeof(n), "%s_clk", name);
93
94 for (i = 0; bulk && i < count; i++) {
95 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
96 return bulk[i].clk;
97 }
98
99
100 return NULL;
101}
102
103struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
104{
105 struct clk *clk;
106 char name2[32];
107
108 clk = devm_clk_get(&pdev->dev, name);
109 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
110 return clk;
111
112 snprintf(name2, sizeof(name2), "%s_clk", name);
113
114 clk = devm_clk_get(&pdev->dev, name2);
115 if (!IS_ERR(clk))
116 dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
117 "\"%s\" instead of \"%s\"\n", name, name2);
118
119 return clk;
120}
121
122void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
123 const char *dbgname)
124{
125 struct resource *res;
126 unsigned long size;
127 void __iomem *ptr;
128
129 if (name)
130 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
131 else
132 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
133
134 if (!res) {
135 DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name);
136 return ERR_PTR(-EINVAL);
137 }
138
139 size = resource_size(res);
140
141 ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
142 if (!ptr) {
143 DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name);
144 return ERR_PTR(-ENOMEM);
145 }
146
147 if (reglog)
148 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
149
150 return ptr;
151}
152
153void msm_writel(u32 data, void __iomem *addr)
154{
155 if (reglog)
156 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
157 writel(data, addr);
158}
159
160u32 msm_readl(const void __iomem *addr)
161{
162 u32 val = readl(addr);
163 if (reglog)
164 pr_err("IO:R %p %08x\n", addr, val);
165 return val;
166}
167
168struct msm_vblank_work {
169 struct work_struct work;
170 int crtc_id;
171 bool enable;
172 struct msm_drm_private *priv;
173};
174
175static void vblank_ctrl_worker(struct work_struct *work)
176{
177 struct msm_vblank_work *vbl_work = container_of(work,
178 struct msm_vblank_work, work);
179 struct msm_drm_private *priv = vbl_work->priv;
180 struct msm_kms *kms = priv->kms;
181
182 if (vbl_work->enable)
183 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
184 else
185 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
186
187 kfree(vbl_work);
188}
189
190static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
191 int crtc_id, bool enable)
192{
193 struct msm_vblank_work *vbl_work;
194
195 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
196 if (!vbl_work)
197 return -ENOMEM;
198
199 INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
200
201 vbl_work->crtc_id = crtc_id;
202 vbl_work->enable = enable;
203 vbl_work->priv = priv;
204
205 queue_work(priv->wq, &vbl_work->work);
206
207 return 0;
208}
209
210static int msm_drm_uninit(struct device *dev)
211{
212 struct platform_device *pdev = to_platform_device(dev);
213 struct drm_device *ddev = platform_get_drvdata(pdev);
214 struct msm_drm_private *priv = ddev->dev_private;
215 struct msm_kms *kms = priv->kms;
216 struct msm_mdss *mdss = priv->mdss;
217 int i;
218
219 /*
220 * Shutdown the hw if we're far enough along where things might be on.
221 * If we run this too early, we'll end up panicking in any variety of
222 * places. Since we don't register the drm device until late in
223 * msm_drm_init, drm_dev->registered is used as an indicator that the
224 * shutdown will be successful.
225 */
226 if (ddev->registered) {
227 drm_dev_unregister(ddev);
228 drm_atomic_helper_shutdown(ddev);
229 }
230
231 /* We must cancel and cleanup any pending vblank enable/disable
232 * work before drm_irq_uninstall() to avoid work re-enabling an
233 * irq after uninstall has disabled it.
234 */
235
236 flush_workqueue(priv->wq);
237
238 /* clean up event worker threads */
239 for (i = 0; i < priv->num_crtcs; i++) {
240 if (priv->event_thread[i].thread) {
241 kthread_destroy_worker(&priv->event_thread[i].worker);
242 priv->event_thread[i].thread = NULL;
243 }
244 }
245
246 msm_gem_shrinker_cleanup(ddev);
247
248 drm_kms_helper_poll_fini(ddev);
249
250 msm_perf_debugfs_cleanup(priv);
251 msm_rd_debugfs_cleanup(priv);
252
253#ifdef CONFIG_DRM_FBDEV_EMULATION
254 if (fbdev && priv->fbdev)
255 msm_fbdev_free(ddev);
256#endif
257
258 drm_mode_config_cleanup(ddev);
259
260 pm_runtime_get_sync(dev);
261 drm_irq_uninstall(ddev);
262 pm_runtime_put_sync(dev);
263
264 if (kms && kms->funcs)
265 kms->funcs->destroy(kms);
266
267 if (priv->vram.paddr) {
268 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
269 drm_mm_takedown(&priv->vram.mm);
270 dma_free_attrs(dev, priv->vram.size, NULL,
271 priv->vram.paddr, attrs);
272 }
273
274 component_unbind_all(dev, ddev);
275
276 if (mdss && mdss->funcs)
277 mdss->funcs->destroy(ddev);
278
279 ddev->dev_private = NULL;
280 drm_dev_put(ddev);
281
282 destroy_workqueue(priv->wq);
283 kfree(priv);
284
285 return 0;
286}
287
288#define KMS_MDP4 4
289#define KMS_MDP5 5
290#define KMS_DPU 3
291
292static int get_mdp_ver(struct platform_device *pdev)
293{
294 struct device *dev = &pdev->dev;
295
296 return (int) (unsigned long) of_device_get_match_data(dev);
297}
298
299#include <linux/of_address.h>
300
301bool msm_use_mmu(struct drm_device *dev)
302{
303 struct msm_drm_private *priv = dev->dev_private;
304
305 /* a2xx comes with its own MMU */
306 return priv->is_a2xx || iommu_present(&platform_bus_type);
307}
308
309static int msm_init_vram(struct drm_device *dev)
310{
311 struct msm_drm_private *priv = dev->dev_private;
312 struct device_node *node;
313 unsigned long size = 0;
314 int ret = 0;
315
316 /* In the device-tree world, we could have a 'memory-region'
317 * phandle, which gives us a link to our "vram". Allocating
318 * is all nicely abstracted behind the dma api, but we need
319 * to know the entire size to allocate it all in one go. There
320 * are two cases:
321 * 1) device with no IOMMU, in which case we need exclusive
322 * access to a VRAM carveout big enough for all gpu
323 * buffers
324 * 2) device with IOMMU, but where the bootloader puts up
325 * a splash screen. In this case, the VRAM carveout
326 * need only be large enough for fbdev fb. But we need
327 * exclusive access to the buffer to avoid the kernel
328 * using those pages for other purposes (which appears
329 * as corruption on screen before we have a chance to
330 * load and do initial modeset)
331 */
332
333 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
334 if (node) {
335 struct resource r;
336 ret = of_address_to_resource(node, 0, &r);
337 of_node_put(node);
338 if (ret)
339 return ret;
340 size = r.end - r.start;
341 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
342
343 /* if we have no IOMMU, then we need to use carveout allocator.
344 * Grab the entire CMA chunk carved out in early startup in
345 * mach-msm:
346 */
347 } else if (!msm_use_mmu(dev)) {
348 DRM_INFO("using %s VRAM carveout\n", vram);
349 size = memparse(vram, NULL);
350 }
351
352 if (size) {
353 unsigned long attrs = 0;
354 void *p;
355
356 priv->vram.size = size;
357
358 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
359 spin_lock_init(&priv->vram.lock);
360
361 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
362 attrs |= DMA_ATTR_WRITE_COMBINE;
363
364 /* note that for no-kernel-mapping, the vaddr returned
365 * is bogus, but non-null if allocation succeeded:
366 */
367 p = dma_alloc_attrs(dev->dev, size,
368 &priv->vram.paddr, GFP_KERNEL, attrs);
369 if (!p) {
370 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
371 priv->vram.paddr = 0;
372 return -ENOMEM;
373 }
374
375 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
376 (uint32_t)priv->vram.paddr,
377 (uint32_t)(priv->vram.paddr + size));
378 }
379
380 return ret;
381}
382
383static int msm_drm_init(struct device *dev, struct drm_driver *drv)
384{
385 struct platform_device *pdev = to_platform_device(dev);
386 struct drm_device *ddev;
387 struct msm_drm_private *priv;
388 struct msm_kms *kms;
389 struct msm_mdss *mdss;
390 int ret, i;
391 struct sched_param param;
392
393 ddev = drm_dev_alloc(drv, dev);
394 if (IS_ERR(ddev)) {
395 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
396 return PTR_ERR(ddev);
397 }
398
399 platform_set_drvdata(pdev, ddev);
400
401 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
402 if (!priv) {
403 ret = -ENOMEM;
404 goto err_put_drm_dev;
405 }
406
407 ddev->dev_private = priv;
408 priv->dev = ddev;
409
410 switch (get_mdp_ver(pdev)) {
411 case KMS_MDP5:
412 ret = mdp5_mdss_init(ddev);
413 break;
414 case KMS_DPU:
415 ret = dpu_mdss_init(ddev);
416 break;
417 default:
418 ret = 0;
419 break;
420 }
421 if (ret)
422 goto err_free_priv;
423
424 mdss = priv->mdss;
425
426 priv->wq = alloc_ordered_workqueue("msm", 0);
427
428 INIT_WORK(&priv->free_work, msm_gem_free_work);
429 init_llist_head(&priv->free_list);
430
431 INIT_LIST_HEAD(&priv->inactive_list);
432
433 drm_mode_config_init(ddev);
434
435 /* Bind all our sub-components: */
436 ret = component_bind_all(dev, ddev);
437 if (ret)
438 goto err_destroy_mdss;
439
440 ret = msm_init_vram(ddev);
441 if (ret)
442 goto err_msm_uninit;
443
444 msm_gem_shrinker_init(ddev);
445
446 switch (get_mdp_ver(pdev)) {
447 case KMS_MDP4:
448 kms = mdp4_kms_init(ddev);
449 priv->kms = kms;
450 break;
451 case KMS_MDP5:
452 kms = mdp5_kms_init(ddev);
453 break;
454 case KMS_DPU:
455 kms = dpu_kms_init(ddev);
456 priv->kms = kms;
457 break;
458 default:
459 /* valid only for the dummy headless case, where of_node=NULL */
460 WARN_ON(dev->of_node);
461 kms = NULL;
462 break;
463 }
464
465 if (IS_ERR(kms)) {
466 DRM_DEV_ERROR(dev, "failed to load kms\n");
467 ret = PTR_ERR(kms);
468 priv->kms = NULL;
469 goto err_msm_uninit;
470 }
471
472 /* Enable normalization of plane zpos */
473 ddev->mode_config.normalize_zpos = true;
474
475 if (kms) {
476 kms->dev = ddev;
477 ret = kms->funcs->hw_init(kms);
478 if (ret) {
479 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
480 goto err_msm_uninit;
481 }
482 }
483
484 ddev->mode_config.funcs = &mode_config_funcs;
485 ddev->mode_config.helper_private = &mode_config_helper_funcs;
486
487 /**
488 * this priority was found during empiric testing to have appropriate
489 * realtime scheduling to process display updates and interact with
490 * other real time and normal priority task
491 */
492 param.sched_priority = 16;
493 for (i = 0; i < priv->num_crtcs; i++) {
494 /* initialize event thread */
495 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
496 kthread_init_worker(&priv->event_thread[i].worker);
497 priv->event_thread[i].dev = ddev;
498 priv->event_thread[i].thread =
499 kthread_run(kthread_worker_fn,
500 &priv->event_thread[i].worker,
501 "crtc_event:%d", priv->event_thread[i].crtc_id);
502 if (IS_ERR(priv->event_thread[i].thread)) {
503 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
504 priv->event_thread[i].thread = NULL;
505 goto err_msm_uninit;
506 }
507
508 ret = sched_setscheduler(priv->event_thread[i].thread,
509 SCHED_FIFO, ¶m);
510 if (ret)
511 dev_warn(dev, "event_thread set priority failed:%d\n",
512 ret);
513 }
514
515 ret = drm_vblank_init(ddev, priv->num_crtcs);
516 if (ret < 0) {
517 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
518 goto err_msm_uninit;
519 }
520
521 if (kms) {
522 pm_runtime_get_sync(dev);
523 ret = drm_irq_install(ddev, kms->irq);
524 pm_runtime_put_sync(dev);
525 if (ret < 0) {
526 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
527 goto err_msm_uninit;
528 }
529 }
530
531 ret = drm_dev_register(ddev, 0);
532 if (ret)
533 goto err_msm_uninit;
534
535 drm_mode_config_reset(ddev);
536
537#ifdef CONFIG_DRM_FBDEV_EMULATION
538 if (kms && fbdev)
539 priv->fbdev = msm_fbdev_init(ddev);
540#endif
541
542 ret = msm_debugfs_late_init(ddev);
543 if (ret)
544 goto err_msm_uninit;
545
546 drm_kms_helper_poll_init(ddev);
547
548 return 0;
549
550err_msm_uninit:
551 msm_drm_uninit(dev);
552 return ret;
553err_destroy_mdss:
554 if (mdss && mdss->funcs)
555 mdss->funcs->destroy(ddev);
556err_free_priv:
557 kfree(priv);
558err_put_drm_dev:
559 drm_dev_put(ddev);
560 return ret;
561}
562
563/*
564 * DRM operations:
565 */
566
567static void load_gpu(struct drm_device *dev)
568{
569 static DEFINE_MUTEX(init_lock);
570 struct msm_drm_private *priv = dev->dev_private;
571
572 mutex_lock(&init_lock);
573
574 if (!priv->gpu)
575 priv->gpu = adreno_load_gpu(dev);
576
577 mutex_unlock(&init_lock);
578}
579
580static int context_init(struct drm_device *dev, struct drm_file *file)
581{
582 struct msm_drm_private *priv = dev->dev_private;
583 struct msm_file_private *ctx;
584
585 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
586 if (!ctx)
587 return -ENOMEM;
588
589 msm_submitqueue_init(dev, ctx);
590
591 ctx->aspace = priv->gpu ? priv->gpu->aspace : NULL;
592 file->driver_priv = ctx;
593
594 return 0;
595}
596
597static int msm_open(struct drm_device *dev, struct drm_file *file)
598{
599 /* For now, load gpu on open.. to avoid the requirement of having
600 * firmware in the initrd.
601 */
602 load_gpu(dev);
603
604 return context_init(dev, file);
605}
606
607static void context_close(struct msm_file_private *ctx)
608{
609 msm_submitqueue_close(ctx);
610 kfree(ctx);
611}
612
613static void msm_postclose(struct drm_device *dev, struct drm_file *file)
614{
615 struct msm_drm_private *priv = dev->dev_private;
616 struct msm_file_private *ctx = file->driver_priv;
617
618 mutex_lock(&dev->struct_mutex);
619 if (ctx == priv->lastctx)
620 priv->lastctx = NULL;
621 mutex_unlock(&dev->struct_mutex);
622
623 context_close(ctx);
624}
625
626static irqreturn_t msm_irq(int irq, void *arg)
627{
628 struct drm_device *dev = arg;
629 struct msm_drm_private *priv = dev->dev_private;
630 struct msm_kms *kms = priv->kms;
631 BUG_ON(!kms);
632 return kms->funcs->irq(kms);
633}
634
635static void msm_irq_preinstall(struct drm_device *dev)
636{
637 struct msm_drm_private *priv = dev->dev_private;
638 struct msm_kms *kms = priv->kms;
639 BUG_ON(!kms);
640 kms->funcs->irq_preinstall(kms);
641}
642
643static int msm_irq_postinstall(struct drm_device *dev)
644{
645 struct msm_drm_private *priv = dev->dev_private;
646 struct msm_kms *kms = priv->kms;
647 BUG_ON(!kms);
648
649 if (kms->funcs->irq_postinstall)
650 return kms->funcs->irq_postinstall(kms);
651
652 return 0;
653}
654
655static void msm_irq_uninstall(struct drm_device *dev)
656{
657 struct msm_drm_private *priv = dev->dev_private;
658 struct msm_kms *kms = priv->kms;
659 BUG_ON(!kms);
660 kms->funcs->irq_uninstall(kms);
661}
662
663static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe)
664{
665 struct msm_drm_private *priv = dev->dev_private;
666 struct msm_kms *kms = priv->kms;
667 if (!kms)
668 return -ENXIO;
669 DBG("dev=%p, crtc=%u", dev, pipe);
670 return vblank_ctrl_queue_work(priv, pipe, true);
671}
672
673static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe)
674{
675 struct msm_drm_private *priv = dev->dev_private;
676 struct msm_kms *kms = priv->kms;
677 if (!kms)
678 return;
679 DBG("dev=%p, crtc=%u", dev, pipe);
680 vblank_ctrl_queue_work(priv, pipe, false);
681}
682
683/*
684 * DRM ioctls:
685 */
686
687static int msm_ioctl_get_param(struct drm_device *dev, void *data,
688 struct drm_file *file)
689{
690 struct msm_drm_private *priv = dev->dev_private;
691 struct drm_msm_param *args = data;
692 struct msm_gpu *gpu;
693
694 /* for now, we just have 3d pipe.. eventually this would need to
695 * be more clever to dispatch to appropriate gpu module:
696 */
697 if (args->pipe != MSM_PIPE_3D0)
698 return -EINVAL;
699
700 gpu = priv->gpu;
701
702 if (!gpu)
703 return -ENXIO;
704
705 return gpu->funcs->get_param(gpu, args->param, &args->value);
706}
707
708static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
709 struct drm_file *file)
710{
711 struct drm_msm_gem_new *args = data;
712
713 if (args->flags & ~MSM_BO_FLAGS) {
714 DRM_ERROR("invalid flags: %08x\n", args->flags);
715 return -EINVAL;
716 }
717
718 return msm_gem_new_handle(dev, file, args->size,
719 args->flags, &args->handle, NULL);
720}
721
722static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
723{
724 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
725}
726
727static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
728 struct drm_file *file)
729{
730 struct drm_msm_gem_cpu_prep *args = data;
731 struct drm_gem_object *obj;
732 ktime_t timeout = to_ktime(args->timeout);
733 int ret;
734
735 if (args->op & ~MSM_PREP_FLAGS) {
736 DRM_ERROR("invalid op: %08x\n", args->op);
737 return -EINVAL;
738 }
739
740 obj = drm_gem_object_lookup(file, args->handle);
741 if (!obj)
742 return -ENOENT;
743
744 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
745
746 drm_gem_object_put_unlocked(obj);
747
748 return ret;
749}
750
751static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
752 struct drm_file *file)
753{
754 struct drm_msm_gem_cpu_fini *args = data;
755 struct drm_gem_object *obj;
756 int ret;
757
758 obj = drm_gem_object_lookup(file, args->handle);
759 if (!obj)
760 return -ENOENT;
761
762 ret = msm_gem_cpu_fini(obj);
763
764 drm_gem_object_put_unlocked(obj);
765
766 return ret;
767}
768
769static int msm_ioctl_gem_info_iova(struct drm_device *dev,
770 struct drm_gem_object *obj, uint64_t *iova)
771{
772 struct msm_drm_private *priv = dev->dev_private;
773
774 if (!priv->gpu)
775 return -EINVAL;
776
777 /*
778 * Don't pin the memory here - just get an address so that userspace can
779 * be productive
780 */
781 return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
782}
783
784static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
785 struct drm_file *file)
786{
787 struct drm_msm_gem_info *args = data;
788 struct drm_gem_object *obj;
789 struct msm_gem_object *msm_obj;
790 int i, ret = 0;
791
792 if (args->pad)
793 return -EINVAL;
794
795 switch (args->info) {
796 case MSM_INFO_GET_OFFSET:
797 case MSM_INFO_GET_IOVA:
798 /* value returned as immediate, not pointer, so len==0: */
799 if (args->len)
800 return -EINVAL;
801 break;
802 case MSM_INFO_SET_NAME:
803 case MSM_INFO_GET_NAME:
804 break;
805 default:
806 return -EINVAL;
807 }
808
809 obj = drm_gem_object_lookup(file, args->handle);
810 if (!obj)
811 return -ENOENT;
812
813 msm_obj = to_msm_bo(obj);
814
815 switch (args->info) {
816 case MSM_INFO_GET_OFFSET:
817 args->value = msm_gem_mmap_offset(obj);
818 break;
819 case MSM_INFO_GET_IOVA:
820 ret = msm_ioctl_gem_info_iova(dev, obj, &args->value);
821 break;
822 case MSM_INFO_SET_NAME:
823 /* length check should leave room for terminating null: */
824 if (args->len >= sizeof(msm_obj->name)) {
825 ret = -EINVAL;
826 break;
827 }
828 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
829 args->len)) {
830 msm_obj->name[0] = '\0';
831 ret = -EFAULT;
832 break;
833 }
834 msm_obj->name[args->len] = '\0';
835 for (i = 0; i < args->len; i++) {
836 if (!isprint(msm_obj->name[i])) {
837 msm_obj->name[i] = '\0';
838 break;
839 }
840 }
841 break;
842 case MSM_INFO_GET_NAME:
843 if (args->value && (args->len < strlen(msm_obj->name))) {
844 ret = -EINVAL;
845 break;
846 }
847 args->len = strlen(msm_obj->name);
848 if (args->value) {
849 if (copy_to_user(u64_to_user_ptr(args->value),
850 msm_obj->name, args->len))
851 ret = -EFAULT;
852 }
853 break;
854 }
855
856 drm_gem_object_put_unlocked(obj);
857
858 return ret;
859}
860
861static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
862 struct drm_file *file)
863{
864 struct msm_drm_private *priv = dev->dev_private;
865 struct drm_msm_wait_fence *args = data;
866 ktime_t timeout = to_ktime(args->timeout);
867 struct msm_gpu_submitqueue *queue;
868 struct msm_gpu *gpu = priv->gpu;
869 int ret;
870
871 if (args->pad) {
872 DRM_ERROR("invalid pad: %08x\n", args->pad);
873 return -EINVAL;
874 }
875
876 if (!gpu)
877 return 0;
878
879 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
880 if (!queue)
881 return -ENOENT;
882
883 ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout,
884 true);
885
886 msm_submitqueue_put(queue);
887 return ret;
888}
889
890static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
891 struct drm_file *file)
892{
893 struct drm_msm_gem_madvise *args = data;
894 struct drm_gem_object *obj;
895 int ret;
896
897 switch (args->madv) {
898 case MSM_MADV_DONTNEED:
899 case MSM_MADV_WILLNEED:
900 break;
901 default:
902 return -EINVAL;
903 }
904
905 ret = mutex_lock_interruptible(&dev->struct_mutex);
906 if (ret)
907 return ret;
908
909 obj = drm_gem_object_lookup(file, args->handle);
910 if (!obj) {
911 ret = -ENOENT;
912 goto unlock;
913 }
914
915 ret = msm_gem_madvise(obj, args->madv);
916 if (ret >= 0) {
917 args->retained = ret;
918 ret = 0;
919 }
920
921 drm_gem_object_put(obj);
922
923unlock:
924 mutex_unlock(&dev->struct_mutex);
925 return ret;
926}
927
928
929static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
930 struct drm_file *file)
931{
932 struct drm_msm_submitqueue *args = data;
933
934 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
935 return -EINVAL;
936
937 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
938 args->flags, &args->id);
939}
940
941static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
942 struct drm_file *file)
943{
944 return msm_submitqueue_query(dev, file->driver_priv, data);
945}
946
947static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
948 struct drm_file *file)
949{
950 u32 id = *(u32 *) data;
951
952 return msm_submitqueue_remove(file->driver_priv, id);
953}
954
955static const struct drm_ioctl_desc msm_ioctls[] = {
956 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW),
957 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW),
958 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW),
959 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
960 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
961 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW),
962 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW),
963 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW),
964 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW),
965 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
966 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
967};
968
969static const struct vm_operations_struct vm_ops = {
970 .fault = msm_gem_fault,
971 .open = drm_gem_vm_open,
972 .close = drm_gem_vm_close,
973};
974
975static const struct file_operations fops = {
976 .owner = THIS_MODULE,
977 .open = drm_open,
978 .release = drm_release,
979 .unlocked_ioctl = drm_ioctl,
980 .compat_ioctl = drm_compat_ioctl,
981 .poll = drm_poll,
982 .read = drm_read,
983 .llseek = no_llseek,
984 .mmap = msm_gem_mmap,
985};
986
987static struct drm_driver msm_driver = {
988 .driver_features = DRIVER_GEM |
989 DRIVER_RENDER |
990 DRIVER_ATOMIC |
991 DRIVER_MODESET,
992 .open = msm_open,
993 .postclose = msm_postclose,
994 .lastclose = drm_fb_helper_lastclose,
995 .irq_handler = msm_irq,
996 .irq_preinstall = msm_irq_preinstall,
997 .irq_postinstall = msm_irq_postinstall,
998 .irq_uninstall = msm_irq_uninstall,
999 .enable_vblank = msm_enable_vblank,
1000 .disable_vblank = msm_disable_vblank,
1001 .gem_free_object_unlocked = msm_gem_free_object,
1002 .gem_vm_ops = &vm_ops,
1003 .dumb_create = msm_gem_dumb_create,
1004 .dumb_map_offset = msm_gem_dumb_map_offset,
1005 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1006 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1007 .gem_prime_pin = msm_gem_prime_pin,
1008 .gem_prime_unpin = msm_gem_prime_unpin,
1009 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
1010 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1011 .gem_prime_vmap = msm_gem_prime_vmap,
1012 .gem_prime_vunmap = msm_gem_prime_vunmap,
1013 .gem_prime_mmap = msm_gem_prime_mmap,
1014#ifdef CONFIG_DEBUG_FS
1015 .debugfs_init = msm_debugfs_init,
1016#endif
1017 .ioctls = msm_ioctls,
1018 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1019 .fops = &fops,
1020 .name = "msm",
1021 .desc = "MSM Snapdragon DRM",
1022 .date = "20130625",
1023 .major = MSM_VERSION_MAJOR,
1024 .minor = MSM_VERSION_MINOR,
1025 .patchlevel = MSM_VERSION_PATCHLEVEL,
1026};
1027
1028#ifdef CONFIG_PM_SLEEP
1029static int msm_pm_suspend(struct device *dev)
1030{
1031 struct drm_device *ddev = dev_get_drvdata(dev);
1032 struct msm_drm_private *priv = ddev->dev_private;
1033
1034 if (WARN_ON(priv->pm_state))
1035 drm_atomic_state_put(priv->pm_state);
1036
1037 priv->pm_state = drm_atomic_helper_suspend(ddev);
1038 if (IS_ERR(priv->pm_state)) {
1039 int ret = PTR_ERR(priv->pm_state);
1040 DRM_ERROR("Failed to suspend dpu, %d\n", ret);
1041 return ret;
1042 }
1043
1044 return 0;
1045}
1046
1047static int msm_pm_resume(struct device *dev)
1048{
1049 struct drm_device *ddev = dev_get_drvdata(dev);
1050 struct msm_drm_private *priv = ddev->dev_private;
1051 int ret;
1052
1053 if (WARN_ON(!priv->pm_state))
1054 return -ENOENT;
1055
1056 ret = drm_atomic_helper_resume(ddev, priv->pm_state);
1057 if (!ret)
1058 priv->pm_state = NULL;
1059
1060 return ret;
1061}
1062#endif
1063
1064#ifdef CONFIG_PM
1065static int msm_runtime_suspend(struct device *dev)
1066{
1067 struct drm_device *ddev = dev_get_drvdata(dev);
1068 struct msm_drm_private *priv = ddev->dev_private;
1069 struct msm_mdss *mdss = priv->mdss;
1070
1071 DBG("");
1072
1073 if (mdss && mdss->funcs)
1074 return mdss->funcs->disable(mdss);
1075
1076 return 0;
1077}
1078
1079static int msm_runtime_resume(struct device *dev)
1080{
1081 struct drm_device *ddev = dev_get_drvdata(dev);
1082 struct msm_drm_private *priv = ddev->dev_private;
1083 struct msm_mdss *mdss = priv->mdss;
1084
1085 DBG("");
1086
1087 if (mdss && mdss->funcs)
1088 return mdss->funcs->enable(mdss);
1089
1090 return 0;
1091}
1092#endif
1093
1094static const struct dev_pm_ops msm_pm_ops = {
1095 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1096 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
1097};
1098
1099/*
1100 * Componentized driver support:
1101 */
1102
1103/*
1104 * NOTE: duplication of the same code as exynos or imx (or probably any other).
1105 * so probably some room for some helpers
1106 */
1107static int compare_of(struct device *dev, void *data)
1108{
1109 return dev->of_node == data;
1110}
1111
1112/*
1113 * Identify what components need to be added by parsing what remote-endpoints
1114 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1115 * is no external component that we need to add since LVDS is within MDP4
1116 * itself.
1117 */
1118static int add_components_mdp(struct device *mdp_dev,
1119 struct component_match **matchptr)
1120{
1121 struct device_node *np = mdp_dev->of_node;
1122 struct device_node *ep_node;
1123 struct device *master_dev;
1124
1125 /*
1126 * on MDP4 based platforms, the MDP platform device is the component
1127 * master that adds other display interface components to itself.
1128 *
1129 * on MDP5 based platforms, the MDSS platform device is the component
1130 * master that adds MDP5 and other display interface components to
1131 * itself.
1132 */
1133 if (of_device_is_compatible(np, "qcom,mdp4"))
1134 master_dev = mdp_dev;
1135 else
1136 master_dev = mdp_dev->parent;
1137
1138 for_each_endpoint_of_node(np, ep_node) {
1139 struct device_node *intf;
1140 struct of_endpoint ep;
1141 int ret;
1142
1143 ret = of_graph_parse_endpoint(ep_node, &ep);
1144 if (ret) {
1145 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n");
1146 of_node_put(ep_node);
1147 return ret;
1148 }
1149
1150 /*
1151 * The LCDC/LVDS port on MDP4 is a speacial case where the
1152 * remote-endpoint isn't a component that we need to add
1153 */
1154 if (of_device_is_compatible(np, "qcom,mdp4") &&
1155 ep.port == 0)
1156 continue;
1157
1158 /*
1159 * It's okay if some of the ports don't have a remote endpoint
1160 * specified. It just means that the port isn't connected to
1161 * any external interface.
1162 */
1163 intf = of_graph_get_remote_port_parent(ep_node);
1164 if (!intf)
1165 continue;
1166
1167 if (of_device_is_available(intf))
1168 drm_of_component_match_add(master_dev, matchptr,
1169 compare_of, intf);
1170
1171 of_node_put(intf);
1172 }
1173
1174 return 0;
1175}
1176
1177static int compare_name_mdp(struct device *dev, void *data)
1178{
1179 return (strstr(dev_name(dev), "mdp") != NULL);
1180}
1181
1182static int add_display_components(struct device *dev,
1183 struct component_match **matchptr)
1184{
1185 struct device *mdp_dev;
1186 int ret;
1187
1188 /*
1189 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
1190 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
1191 * Populate the children devices, find the MDP5/DPU node, and then add
1192 * the interfaces to our components list.
1193 */
1194 if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
1195 of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss")) {
1196 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1197 if (ret) {
1198 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
1199 return ret;
1200 }
1201
1202 mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
1203 if (!mdp_dev) {
1204 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n");
1205 of_platform_depopulate(dev);
1206 return -ENODEV;
1207 }
1208
1209 put_device(mdp_dev);
1210
1211 /* add the MDP component itself */
1212 drm_of_component_match_add(dev, matchptr, compare_of,
1213 mdp_dev->of_node);
1214 } else {
1215 /* MDP4 */
1216 mdp_dev = dev;
1217 }
1218
1219 ret = add_components_mdp(mdp_dev, matchptr);
1220 if (ret)
1221 of_platform_depopulate(dev);
1222
1223 return ret;
1224}
1225
1226/*
1227 * We don't know what's the best binding to link the gpu with the drm device.
1228 * Fow now, we just hunt for all the possible gpus that we support, and add them
1229 * as components.
1230 */
1231static const struct of_device_id msm_gpu_match[] = {
1232 { .compatible = "qcom,adreno" },
1233 { .compatible = "qcom,adreno-3xx" },
1234 { .compatible = "amd,imageon" },
1235 { .compatible = "qcom,kgsl-3d0" },
1236 { },
1237};
1238
1239static int add_gpu_components(struct device *dev,
1240 struct component_match **matchptr)
1241{
1242 struct device_node *np;
1243
1244 np = of_find_matching_node(NULL, msm_gpu_match);
1245 if (!np)
1246 return 0;
1247
1248 if (of_device_is_available(np))
1249 drm_of_component_match_add(dev, matchptr, compare_of, np);
1250
1251 of_node_put(np);
1252
1253 return 0;
1254}
1255
1256static int msm_drm_bind(struct device *dev)
1257{
1258 return msm_drm_init(dev, &msm_driver);
1259}
1260
1261static void msm_drm_unbind(struct device *dev)
1262{
1263 msm_drm_uninit(dev);
1264}
1265
1266static const struct component_master_ops msm_drm_ops = {
1267 .bind = msm_drm_bind,
1268 .unbind = msm_drm_unbind,
1269};
1270
1271/*
1272 * Platform driver:
1273 */
1274
1275static int msm_pdev_probe(struct platform_device *pdev)
1276{
1277 struct component_match *match = NULL;
1278 int ret;
1279
1280 if (get_mdp_ver(pdev)) {
1281 ret = add_display_components(&pdev->dev, &match);
1282 if (ret)
1283 return ret;
1284 }
1285
1286 ret = add_gpu_components(&pdev->dev, &match);
1287 if (ret)
1288 goto fail;
1289
1290 /* on all devices that I am aware of, iommu's which can map
1291 * any address the cpu can see are used:
1292 */
1293 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1294 if (ret)
1295 goto fail;
1296
1297 ret = component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1298 if (ret)
1299 goto fail;
1300
1301 return 0;
1302
1303fail:
1304 of_platform_depopulate(&pdev->dev);
1305 return ret;
1306}
1307
1308static int msm_pdev_remove(struct platform_device *pdev)
1309{
1310 component_master_del(&pdev->dev, &msm_drm_ops);
1311 of_platform_depopulate(&pdev->dev);
1312
1313 return 0;
1314}
1315
1316static const struct of_device_id dt_match[] = {
1317 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1318 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
1319 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
1320 {}
1321};
1322MODULE_DEVICE_TABLE(of, dt_match);
1323
1324static struct platform_driver msm_platform_driver = {
1325 .probe = msm_pdev_probe,
1326 .remove = msm_pdev_remove,
1327 .driver = {
1328 .name = "msm",
1329 .of_match_table = dt_match,
1330 .pm = &msm_pm_ops,
1331 },
1332};
1333
1334static int __init msm_drm_register(void)
1335{
1336 if (!modeset)
1337 return -EINVAL;
1338
1339 DBG("init");
1340 msm_mdp_register();
1341 msm_dpu_register();
1342 msm_dsi_register();
1343 msm_edp_register();
1344 msm_hdmi_register();
1345 adreno_register();
1346 return platform_driver_register(&msm_platform_driver);
1347}
1348
1349static void __exit msm_drm_unregister(void)
1350{
1351 DBG("fini");
1352 platform_driver_unregister(&msm_platform_driver);
1353 msm_hdmi_unregister();
1354 adreno_unregister();
1355 msm_edp_unregister();
1356 msm_dsi_unregister();
1357 msm_mdp_unregister();
1358 msm_dpu_unregister();
1359}
1360
1361module_init(msm_drm_register);
1362module_exit(msm_drm_unregister);
1363
1364MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1365MODULE_DESCRIPTION("MSM DRM Driver");
1366MODULE_LICENSE("GPL");