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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2013 Altera Corporation
4 * Based on gpio-mpc8xxx.c
5 */
6
7#include <linux/bitops.h>
8#include <linux/device.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/irq.h>
12#include <linux/mod_devicetable.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/property.h>
16#include <linux/spinlock.h>
17#include <linux/types.h>
18
19#include <linux/gpio/driver.h>
20
21#define ALTERA_GPIO_MAX_NGPIO 32
22#define ALTERA_GPIO_DATA 0x0
23#define ALTERA_GPIO_DIR 0x4
24#define ALTERA_GPIO_IRQ_MASK 0x8
25#define ALTERA_GPIO_EDGE_CAP 0xc
26
27/**
28* struct altera_gpio_chip
29* @gc : GPIO chip structure.
30* @regs : memory mapped IO address for the controller registers.
31* @gpio_lock : synchronization lock so that new irq/set/get requests
32* will be blocked until the current one completes.
33* @interrupt_trigger : specifies the hardware configured IRQ trigger type
34* (rising, falling, both, high)
35* @mapped_irq : kernel mapped irq number.
36*/
37struct altera_gpio_chip {
38 struct gpio_chip gc;
39 void __iomem *regs;
40 raw_spinlock_t gpio_lock;
41 int interrupt_trigger;
42 int mapped_irq;
43};
44
45static void altera_gpio_irq_unmask(struct irq_data *d)
46{
47 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
48 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
49 unsigned long flags;
50 u32 intmask;
51
52 gpiochip_enable_irq(gc, irqd_to_hwirq(d));
53
54 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
55 intmask = readl(altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
56 /* Set ALTERA_GPIO_IRQ_MASK bit to unmask */
57 intmask |= BIT(irqd_to_hwirq(d));
58 writel(intmask, altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
59 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
60}
61
62static void altera_gpio_irq_mask(struct irq_data *d)
63{
64 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
65 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
66 unsigned long flags;
67 u32 intmask;
68
69 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
70 intmask = readl(altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
71 /* Clear ALTERA_GPIO_IRQ_MASK bit to mask */
72 intmask &= ~BIT(irqd_to_hwirq(d));
73 writel(intmask, altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
74 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
75
76 gpiochip_disable_irq(gc, irqd_to_hwirq(d));
77}
78
79/*
80 * This controller's IRQ type is synthesized in hardware, so this function
81 * just checks if the requested set_type matches the synthesized IRQ type
82 */
83static int altera_gpio_irq_set_type(struct irq_data *d,
84 unsigned int type)
85{
86 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
87 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
88
89 if (type == IRQ_TYPE_NONE) {
90 irq_set_handler_locked(d, handle_bad_irq);
91 return 0;
92 }
93 if (type == altera_gc->interrupt_trigger) {
94 if (type == IRQ_TYPE_LEVEL_HIGH)
95 irq_set_handler_locked(d, handle_level_irq);
96 else
97 irq_set_handler_locked(d, handle_simple_irq);
98 return 0;
99 }
100 irq_set_handler_locked(d, handle_bad_irq);
101 return -EINVAL;
102}
103
104static unsigned int altera_gpio_irq_startup(struct irq_data *d)
105{
106 altera_gpio_irq_unmask(d);
107
108 return 0;
109}
110
111static int altera_gpio_get(struct gpio_chip *gc, unsigned offset)
112{
113 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
114
115 return !!(readl(altera_gc->regs + ALTERA_GPIO_DATA) & BIT(offset));
116}
117
118static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
119{
120 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
121 unsigned long flags;
122 unsigned int data_reg;
123
124 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
125 data_reg = readl(altera_gc->regs + ALTERA_GPIO_DATA);
126 if (value)
127 data_reg |= BIT(offset);
128 else
129 data_reg &= ~BIT(offset);
130 writel(data_reg, altera_gc->regs + ALTERA_GPIO_DATA);
131 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
132}
133
134static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
135{
136 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
137 unsigned long flags;
138 unsigned int gpio_ddr;
139
140 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
141 /* Set pin as input, assumes software controlled IP */
142 gpio_ddr = readl(altera_gc->regs + ALTERA_GPIO_DIR);
143 gpio_ddr &= ~BIT(offset);
144 writel(gpio_ddr, altera_gc->regs + ALTERA_GPIO_DIR);
145 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
146
147 return 0;
148}
149
150static int altera_gpio_direction_output(struct gpio_chip *gc,
151 unsigned offset, int value)
152{
153 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
154 unsigned long flags;
155 unsigned int data_reg, gpio_ddr;
156
157 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
158 /* Sets the GPIO value */
159 data_reg = readl(altera_gc->regs + ALTERA_GPIO_DATA);
160 if (value)
161 data_reg |= BIT(offset);
162 else
163 data_reg &= ~BIT(offset);
164 writel(data_reg, altera_gc->regs + ALTERA_GPIO_DATA);
165
166 /* Set pin as output, assumes software controlled IP */
167 gpio_ddr = readl(altera_gc->regs + ALTERA_GPIO_DIR);
168 gpio_ddr |= BIT(offset);
169 writel(gpio_ddr, altera_gc->regs + ALTERA_GPIO_DIR);
170 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
171
172 return 0;
173}
174
175static void altera_gpio_irq_edge_handler(struct irq_desc *desc)
176{
177 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
178 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
179 struct irq_domain *irqdomain = gc->irq.domain;
180 struct irq_chip *chip;
181 unsigned long status;
182 int i;
183
184 chip = irq_desc_get_chip(desc);
185
186 chained_irq_enter(chip, desc);
187
188 while ((status =
189 (readl(altera_gc->regs + ALTERA_GPIO_EDGE_CAP) &
190 readl(altera_gc->regs + ALTERA_GPIO_IRQ_MASK)))) {
191 writel(status, altera_gc->regs + ALTERA_GPIO_EDGE_CAP);
192 for_each_set_bit(i, &status, gc->ngpio)
193 generic_handle_domain_irq(irqdomain, i);
194 }
195
196 chained_irq_exit(chip, desc);
197}
198
199static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc)
200{
201 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
202 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
203 struct irq_domain *irqdomain = gc->irq.domain;
204 struct irq_chip *chip;
205 unsigned long status;
206 int i;
207
208 chip = irq_desc_get_chip(desc);
209
210 chained_irq_enter(chip, desc);
211
212 status = readl(altera_gc->regs + ALTERA_GPIO_DATA);
213 status &= readl(altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
214
215 for_each_set_bit(i, &status, gc->ngpio)
216 generic_handle_domain_irq(irqdomain, i);
217
218 chained_irq_exit(chip, desc);
219}
220
221static const struct irq_chip altera_gpio_irq_chip = {
222 .name = "altera-gpio",
223 .irq_mask = altera_gpio_irq_mask,
224 .irq_unmask = altera_gpio_irq_unmask,
225 .irq_set_type = altera_gpio_irq_set_type,
226 .irq_startup = altera_gpio_irq_startup,
227 .irq_shutdown = altera_gpio_irq_mask,
228 .flags = IRQCHIP_IMMUTABLE,
229 GPIOCHIP_IRQ_RESOURCE_HELPERS,
230};
231
232static int altera_gpio_probe(struct platform_device *pdev)
233{
234 struct device *dev = &pdev->dev;
235 int reg, ret;
236 struct altera_gpio_chip *altera_gc;
237 struct gpio_irq_chip *girq;
238
239 altera_gc = devm_kzalloc(&pdev->dev, sizeof(*altera_gc), GFP_KERNEL);
240 if (!altera_gc)
241 return -ENOMEM;
242
243 raw_spin_lock_init(&altera_gc->gpio_lock);
244
245 if (device_property_read_u32(dev, "altr,ngpio", ®))
246 /* By default assume maximum ngpio */
247 altera_gc->gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
248 else
249 altera_gc->gc.ngpio = reg;
250
251 if (altera_gc->gc.ngpio > ALTERA_GPIO_MAX_NGPIO) {
252 dev_warn(&pdev->dev,
253 "ngpio is greater than %d, defaulting to %d\n",
254 ALTERA_GPIO_MAX_NGPIO, ALTERA_GPIO_MAX_NGPIO);
255 altera_gc->gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
256 }
257
258 altera_gc->gc.direction_input = altera_gpio_direction_input;
259 altera_gc->gc.direction_output = altera_gpio_direction_output;
260 altera_gc->gc.get = altera_gpio_get;
261 altera_gc->gc.set = altera_gpio_set;
262 altera_gc->gc.owner = THIS_MODULE;
263 altera_gc->gc.parent = &pdev->dev;
264 altera_gc->gc.base = -1;
265
266 altera_gc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", dev_fwnode(dev));
267 if (!altera_gc->gc.label)
268 return -ENOMEM;
269
270 altera_gc->regs = devm_platform_ioremap_resource(pdev, 0);
271 if (IS_ERR(altera_gc->regs))
272 return dev_err_probe(dev, PTR_ERR(altera_gc->regs), "failed to ioremap memory resource\n");
273
274 altera_gc->mapped_irq = platform_get_irq_optional(pdev, 0);
275 if (altera_gc->mapped_irq < 0)
276 goto skip_irq;
277
278 if (device_property_read_u32(dev, "altr,interrupt-type", ®)) {
279 dev_err(&pdev->dev,
280 "altr,interrupt-type value not set in device tree\n");
281 return -EINVAL;
282 }
283 altera_gc->interrupt_trigger = reg;
284
285 girq = &altera_gc->gc.irq;
286 gpio_irq_chip_set_chip(girq, &altera_gpio_irq_chip);
287
288 if (altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH)
289 girq->parent_handler = altera_gpio_irq_leveL_high_handler;
290 else
291 girq->parent_handler = altera_gpio_irq_edge_handler;
292 girq->num_parents = 1;
293 girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
294 GFP_KERNEL);
295 if (!girq->parents)
296 return -ENOMEM;
297 girq->default_type = IRQ_TYPE_NONE;
298 girq->handler = handle_bad_irq;
299 girq->parents[0] = altera_gc->mapped_irq;
300
301skip_irq:
302 ret = devm_gpiochip_add_data(dev, &altera_gc->gc, altera_gc);
303 if (ret) {
304 dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n");
305 return ret;
306 }
307
308 return 0;
309}
310
311static const struct of_device_id altera_gpio_of_match[] = {
312 { .compatible = "altr,pio-1.0", },
313 {},
314};
315MODULE_DEVICE_TABLE(of, altera_gpio_of_match);
316
317static struct platform_driver altera_gpio_driver = {
318 .driver = {
319 .name = "altera_gpio",
320 .of_match_table = altera_gpio_of_match,
321 },
322 .probe = altera_gpio_probe,
323};
324
325static int __init altera_gpio_init(void)
326{
327 return platform_driver_register(&altera_gpio_driver);
328}
329subsys_initcall(altera_gpio_init);
330
331static void __exit altera_gpio_exit(void)
332{
333 platform_driver_unregister(&altera_gpio_driver);
334}
335module_exit(altera_gpio_exit);
336
337MODULE_AUTHOR("Tien Hock Loh <thloh@altera.com>");
338MODULE_DESCRIPTION("Altera GPIO driver");
339MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2013 Altera Corporation
4 * Based on gpio-mpc8xxx.c
5 */
6
7#include <linux/io.h>
8#include <linux/module.h>
9#include <linux/gpio/driver.h>
10#include <linux/of_gpio.h> /* For of_mm_gpio_chip */
11#include <linux/platform_device.h>
12
13#define ALTERA_GPIO_MAX_NGPIO 32
14#define ALTERA_GPIO_DATA 0x0
15#define ALTERA_GPIO_DIR 0x4
16#define ALTERA_GPIO_IRQ_MASK 0x8
17#define ALTERA_GPIO_EDGE_CAP 0xc
18
19/**
20* struct altera_gpio_chip
21* @mmchip : memory mapped chip structure.
22* @gpio_lock : synchronization lock so that new irq/set/get requests
23* will be blocked until the current one completes.
24* @interrupt_trigger : specifies the hardware configured IRQ trigger type
25* (rising, falling, both, high)
26* @mapped_irq : kernel mapped irq number.
27*/
28struct altera_gpio_chip {
29 struct of_mm_gpio_chip mmchip;
30 raw_spinlock_t gpio_lock;
31 int interrupt_trigger;
32 int mapped_irq;
33 struct irq_chip irq_chip;
34};
35
36static void altera_gpio_irq_unmask(struct irq_data *d)
37{
38 struct altera_gpio_chip *altera_gc;
39 struct of_mm_gpio_chip *mm_gc;
40 unsigned long flags;
41 u32 intmask;
42
43 altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
44 mm_gc = &altera_gc->mmchip;
45
46 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
47 intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
48 /* Set ALTERA_GPIO_IRQ_MASK bit to unmask */
49 intmask |= BIT(irqd_to_hwirq(d));
50 writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
51 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
52}
53
54static void altera_gpio_irq_mask(struct irq_data *d)
55{
56 struct altera_gpio_chip *altera_gc;
57 struct of_mm_gpio_chip *mm_gc;
58 unsigned long flags;
59 u32 intmask;
60
61 altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
62 mm_gc = &altera_gc->mmchip;
63
64 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
65 intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
66 /* Clear ALTERA_GPIO_IRQ_MASK bit to mask */
67 intmask &= ~BIT(irqd_to_hwirq(d));
68 writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
69 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
70}
71
72/**
73 * This controller's IRQ type is synthesized in hardware, so this function
74 * just checks if the requested set_type matches the synthesized IRQ type
75 */
76static int altera_gpio_irq_set_type(struct irq_data *d,
77 unsigned int type)
78{
79 struct altera_gpio_chip *altera_gc;
80
81 altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
82
83 if (type == IRQ_TYPE_NONE) {
84 irq_set_handler_locked(d, handle_bad_irq);
85 return 0;
86 }
87 if (type == altera_gc->interrupt_trigger) {
88 if (type == IRQ_TYPE_LEVEL_HIGH)
89 irq_set_handler_locked(d, handle_level_irq);
90 else
91 irq_set_handler_locked(d, handle_simple_irq);
92 return 0;
93 }
94 irq_set_handler_locked(d, handle_bad_irq);
95 return -EINVAL;
96}
97
98static unsigned int altera_gpio_irq_startup(struct irq_data *d)
99{
100 altera_gpio_irq_unmask(d);
101
102 return 0;
103}
104
105static int altera_gpio_get(struct gpio_chip *gc, unsigned offset)
106{
107 struct of_mm_gpio_chip *mm_gc;
108
109 mm_gc = to_of_mm_gpio_chip(gc);
110
111 return !!(readl(mm_gc->regs + ALTERA_GPIO_DATA) & BIT(offset));
112}
113
114static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
115{
116 struct of_mm_gpio_chip *mm_gc;
117 struct altera_gpio_chip *chip;
118 unsigned long flags;
119 unsigned int data_reg;
120
121 mm_gc = to_of_mm_gpio_chip(gc);
122 chip = gpiochip_get_data(gc);
123
124 raw_spin_lock_irqsave(&chip->gpio_lock, flags);
125 data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
126 if (value)
127 data_reg |= BIT(offset);
128 else
129 data_reg &= ~BIT(offset);
130 writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
131 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
132}
133
134static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
135{
136 struct of_mm_gpio_chip *mm_gc;
137 struct altera_gpio_chip *chip;
138 unsigned long flags;
139 unsigned int gpio_ddr;
140
141 mm_gc = to_of_mm_gpio_chip(gc);
142 chip = gpiochip_get_data(gc);
143
144 raw_spin_lock_irqsave(&chip->gpio_lock, flags);
145 /* Set pin as input, assumes software controlled IP */
146 gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
147 gpio_ddr &= ~BIT(offset);
148 writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
149 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
150
151 return 0;
152}
153
154static int altera_gpio_direction_output(struct gpio_chip *gc,
155 unsigned offset, int value)
156{
157 struct of_mm_gpio_chip *mm_gc;
158 struct altera_gpio_chip *chip;
159 unsigned long flags;
160 unsigned int data_reg, gpio_ddr;
161
162 mm_gc = to_of_mm_gpio_chip(gc);
163 chip = gpiochip_get_data(gc);
164
165 raw_spin_lock_irqsave(&chip->gpio_lock, flags);
166 /* Sets the GPIO value */
167 data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
168 if (value)
169 data_reg |= BIT(offset);
170 else
171 data_reg &= ~BIT(offset);
172 writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
173
174 /* Set pin as output, assumes software controlled IP */
175 gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
176 gpio_ddr |= BIT(offset);
177 writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
178 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
179
180 return 0;
181}
182
183static void altera_gpio_irq_edge_handler(struct irq_desc *desc)
184{
185 struct altera_gpio_chip *altera_gc;
186 struct irq_chip *chip;
187 struct of_mm_gpio_chip *mm_gc;
188 struct irq_domain *irqdomain;
189 unsigned long status;
190 int i;
191
192 altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
193 chip = irq_desc_get_chip(desc);
194 mm_gc = &altera_gc->mmchip;
195 irqdomain = altera_gc->mmchip.gc.irq.domain;
196
197 chained_irq_enter(chip, desc);
198
199 while ((status =
200 (readl(mm_gc->regs + ALTERA_GPIO_EDGE_CAP) &
201 readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK)))) {
202 writel(status, mm_gc->regs + ALTERA_GPIO_EDGE_CAP);
203 for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
204 generic_handle_irq(irq_find_mapping(irqdomain, i));
205 }
206 }
207
208 chained_irq_exit(chip, desc);
209}
210
211static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc)
212{
213 struct altera_gpio_chip *altera_gc;
214 struct irq_chip *chip;
215 struct of_mm_gpio_chip *mm_gc;
216 struct irq_domain *irqdomain;
217 unsigned long status;
218 int i;
219
220 altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
221 chip = irq_desc_get_chip(desc);
222 mm_gc = &altera_gc->mmchip;
223 irqdomain = altera_gc->mmchip.gc.irq.domain;
224
225 chained_irq_enter(chip, desc);
226
227 status = readl(mm_gc->regs + ALTERA_GPIO_DATA);
228 status &= readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
229
230 for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
231 generic_handle_irq(irq_find_mapping(irqdomain, i));
232 }
233 chained_irq_exit(chip, desc);
234}
235
236static int altera_gpio_probe(struct platform_device *pdev)
237{
238 struct device_node *node = pdev->dev.of_node;
239 int reg, ret;
240 struct altera_gpio_chip *altera_gc;
241 struct gpio_irq_chip *girq;
242
243 altera_gc = devm_kzalloc(&pdev->dev, sizeof(*altera_gc), GFP_KERNEL);
244 if (!altera_gc)
245 return -ENOMEM;
246
247 raw_spin_lock_init(&altera_gc->gpio_lock);
248
249 if (of_property_read_u32(node, "altr,ngpio", ®))
250 /* By default assume maximum ngpio */
251 altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
252 else
253 altera_gc->mmchip.gc.ngpio = reg;
254
255 if (altera_gc->mmchip.gc.ngpio > ALTERA_GPIO_MAX_NGPIO) {
256 dev_warn(&pdev->dev,
257 "ngpio is greater than %d, defaulting to %d\n",
258 ALTERA_GPIO_MAX_NGPIO, ALTERA_GPIO_MAX_NGPIO);
259 altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
260 }
261
262 altera_gc->mmchip.gc.direction_input = altera_gpio_direction_input;
263 altera_gc->mmchip.gc.direction_output = altera_gpio_direction_output;
264 altera_gc->mmchip.gc.get = altera_gpio_get;
265 altera_gc->mmchip.gc.set = altera_gpio_set;
266 altera_gc->mmchip.gc.owner = THIS_MODULE;
267 altera_gc->mmchip.gc.parent = &pdev->dev;
268
269 altera_gc->mapped_irq = platform_get_irq(pdev, 0);
270
271 if (altera_gc->mapped_irq < 0)
272 goto skip_irq;
273
274 if (of_property_read_u32(node, "altr,interrupt-type", ®)) {
275 dev_err(&pdev->dev,
276 "altr,interrupt-type value not set in device tree\n");
277 return -EINVAL;
278 }
279 altera_gc->interrupt_trigger = reg;
280
281 altera_gc->irq_chip.name = "altera-gpio";
282 altera_gc->irq_chip.irq_mask = altera_gpio_irq_mask;
283 altera_gc->irq_chip.irq_unmask = altera_gpio_irq_unmask;
284 altera_gc->irq_chip.irq_set_type = altera_gpio_irq_set_type;
285 altera_gc->irq_chip.irq_startup = altera_gpio_irq_startup;
286 altera_gc->irq_chip.irq_shutdown = altera_gpio_irq_mask;
287
288 girq = &altera_gc->mmchip.gc.irq;
289 girq->chip = &altera_gc->irq_chip;
290 if (altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH)
291 girq->parent_handler = altera_gpio_irq_leveL_high_handler;
292 else
293 girq->parent_handler = altera_gpio_irq_edge_handler;
294 girq->num_parents = 1;
295 girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
296 GFP_KERNEL);
297 if (!girq->parents)
298 return -ENOMEM;
299 girq->default_type = IRQ_TYPE_NONE;
300 girq->handler = handle_bad_irq;
301 girq->parents[0] = altera_gc->mapped_irq;
302
303skip_irq:
304 ret = of_mm_gpiochip_add_data(node, &altera_gc->mmchip, altera_gc);
305 if (ret) {
306 dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n");
307 return ret;
308 }
309
310 platform_set_drvdata(pdev, altera_gc);
311
312 return 0;
313}
314
315static int altera_gpio_remove(struct platform_device *pdev)
316{
317 struct altera_gpio_chip *altera_gc = platform_get_drvdata(pdev);
318
319 of_mm_gpiochip_remove(&altera_gc->mmchip);
320
321 return 0;
322}
323
324static const struct of_device_id altera_gpio_of_match[] = {
325 { .compatible = "altr,pio-1.0", },
326 {},
327};
328MODULE_DEVICE_TABLE(of, altera_gpio_of_match);
329
330static struct platform_driver altera_gpio_driver = {
331 .driver = {
332 .name = "altera_gpio",
333 .of_match_table = of_match_ptr(altera_gpio_of_match),
334 },
335 .probe = altera_gpio_probe,
336 .remove = altera_gpio_remove,
337};
338
339static int __init altera_gpio_init(void)
340{
341 return platform_driver_register(&altera_gpio_driver);
342}
343subsys_initcall(altera_gpio_init);
344
345static void __exit altera_gpio_exit(void)
346{
347 platform_driver_unregister(&altera_gpio_driver);
348}
349module_exit(altera_gpio_exit);
350
351MODULE_AUTHOR("Tien Hock Loh <thloh@altera.com>");
352MODULE_DESCRIPTION("Altera GPIO driver");
353MODULE_LICENSE("GPL");