Loading...
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2013 Altera Corporation
4 * Based on gpio-mpc8xxx.c
5 */
6
7#include <linux/bitops.h>
8#include <linux/device.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/irq.h>
12#include <linux/mod_devicetable.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/property.h>
16#include <linux/spinlock.h>
17#include <linux/types.h>
18
19#include <linux/gpio/driver.h>
20
21#define ALTERA_GPIO_MAX_NGPIO 32
22#define ALTERA_GPIO_DATA 0x0
23#define ALTERA_GPIO_DIR 0x4
24#define ALTERA_GPIO_IRQ_MASK 0x8
25#define ALTERA_GPIO_EDGE_CAP 0xc
26
27/**
28* struct altera_gpio_chip
29* @gc : GPIO chip structure.
30* @regs : memory mapped IO address for the controller registers.
31* @gpio_lock : synchronization lock so that new irq/set/get requests
32* will be blocked until the current one completes.
33* @interrupt_trigger : specifies the hardware configured IRQ trigger type
34* (rising, falling, both, high)
35* @mapped_irq : kernel mapped irq number.
36*/
37struct altera_gpio_chip {
38 struct gpio_chip gc;
39 void __iomem *regs;
40 raw_spinlock_t gpio_lock;
41 int interrupt_trigger;
42 int mapped_irq;
43};
44
45static void altera_gpio_irq_unmask(struct irq_data *d)
46{
47 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
48 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
49 unsigned long flags;
50 u32 intmask;
51
52 gpiochip_enable_irq(gc, irqd_to_hwirq(d));
53
54 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
55 intmask = readl(altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
56 /* Set ALTERA_GPIO_IRQ_MASK bit to unmask */
57 intmask |= BIT(irqd_to_hwirq(d));
58 writel(intmask, altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
59 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
60}
61
62static void altera_gpio_irq_mask(struct irq_data *d)
63{
64 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
65 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
66 unsigned long flags;
67 u32 intmask;
68
69 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
70 intmask = readl(altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
71 /* Clear ALTERA_GPIO_IRQ_MASK bit to mask */
72 intmask &= ~BIT(irqd_to_hwirq(d));
73 writel(intmask, altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
74 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
75
76 gpiochip_disable_irq(gc, irqd_to_hwirq(d));
77}
78
79/*
80 * This controller's IRQ type is synthesized in hardware, so this function
81 * just checks if the requested set_type matches the synthesized IRQ type
82 */
83static int altera_gpio_irq_set_type(struct irq_data *d,
84 unsigned int type)
85{
86 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
87 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
88
89 if (type == IRQ_TYPE_NONE) {
90 irq_set_handler_locked(d, handle_bad_irq);
91 return 0;
92 }
93 if (type == altera_gc->interrupt_trigger) {
94 if (type == IRQ_TYPE_LEVEL_HIGH)
95 irq_set_handler_locked(d, handle_level_irq);
96 else
97 irq_set_handler_locked(d, handle_simple_irq);
98 return 0;
99 }
100 irq_set_handler_locked(d, handle_bad_irq);
101 return -EINVAL;
102}
103
104static unsigned int altera_gpio_irq_startup(struct irq_data *d)
105{
106 altera_gpio_irq_unmask(d);
107
108 return 0;
109}
110
111static int altera_gpio_get(struct gpio_chip *gc, unsigned offset)
112{
113 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
114
115 return !!(readl(altera_gc->regs + ALTERA_GPIO_DATA) & BIT(offset));
116}
117
118static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
119{
120 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
121 unsigned long flags;
122 unsigned int data_reg;
123
124 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
125 data_reg = readl(altera_gc->regs + ALTERA_GPIO_DATA);
126 if (value)
127 data_reg |= BIT(offset);
128 else
129 data_reg &= ~BIT(offset);
130 writel(data_reg, altera_gc->regs + ALTERA_GPIO_DATA);
131 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
132}
133
134static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
135{
136 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
137 unsigned long flags;
138 unsigned int gpio_ddr;
139
140 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
141 /* Set pin as input, assumes software controlled IP */
142 gpio_ddr = readl(altera_gc->regs + ALTERA_GPIO_DIR);
143 gpio_ddr &= ~BIT(offset);
144 writel(gpio_ddr, altera_gc->regs + ALTERA_GPIO_DIR);
145 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
146
147 return 0;
148}
149
150static int altera_gpio_direction_output(struct gpio_chip *gc,
151 unsigned offset, int value)
152{
153 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
154 unsigned long flags;
155 unsigned int data_reg, gpio_ddr;
156
157 raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
158 /* Sets the GPIO value */
159 data_reg = readl(altera_gc->regs + ALTERA_GPIO_DATA);
160 if (value)
161 data_reg |= BIT(offset);
162 else
163 data_reg &= ~BIT(offset);
164 writel(data_reg, altera_gc->regs + ALTERA_GPIO_DATA);
165
166 /* Set pin as output, assumes software controlled IP */
167 gpio_ddr = readl(altera_gc->regs + ALTERA_GPIO_DIR);
168 gpio_ddr |= BIT(offset);
169 writel(gpio_ddr, altera_gc->regs + ALTERA_GPIO_DIR);
170 raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
171
172 return 0;
173}
174
175static void altera_gpio_irq_edge_handler(struct irq_desc *desc)
176{
177 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
178 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
179 struct irq_domain *irqdomain = gc->irq.domain;
180 struct irq_chip *chip;
181 unsigned long status;
182 int i;
183
184 chip = irq_desc_get_chip(desc);
185
186 chained_irq_enter(chip, desc);
187
188 while ((status =
189 (readl(altera_gc->regs + ALTERA_GPIO_EDGE_CAP) &
190 readl(altera_gc->regs + ALTERA_GPIO_IRQ_MASK)))) {
191 writel(status, altera_gc->regs + ALTERA_GPIO_EDGE_CAP);
192 for_each_set_bit(i, &status, gc->ngpio)
193 generic_handle_domain_irq(irqdomain, i);
194 }
195
196 chained_irq_exit(chip, desc);
197}
198
199static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc)
200{
201 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
202 struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
203 struct irq_domain *irqdomain = gc->irq.domain;
204 struct irq_chip *chip;
205 unsigned long status;
206 int i;
207
208 chip = irq_desc_get_chip(desc);
209
210 chained_irq_enter(chip, desc);
211
212 status = readl(altera_gc->regs + ALTERA_GPIO_DATA);
213 status &= readl(altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
214
215 for_each_set_bit(i, &status, gc->ngpio)
216 generic_handle_domain_irq(irqdomain, i);
217
218 chained_irq_exit(chip, desc);
219}
220
221static const struct irq_chip altera_gpio_irq_chip = {
222 .name = "altera-gpio",
223 .irq_mask = altera_gpio_irq_mask,
224 .irq_unmask = altera_gpio_irq_unmask,
225 .irq_set_type = altera_gpio_irq_set_type,
226 .irq_startup = altera_gpio_irq_startup,
227 .irq_shutdown = altera_gpio_irq_mask,
228 .flags = IRQCHIP_IMMUTABLE,
229 GPIOCHIP_IRQ_RESOURCE_HELPERS,
230};
231
232static int altera_gpio_probe(struct platform_device *pdev)
233{
234 struct device *dev = &pdev->dev;
235 int reg, ret;
236 struct altera_gpio_chip *altera_gc;
237 struct gpio_irq_chip *girq;
238
239 altera_gc = devm_kzalloc(&pdev->dev, sizeof(*altera_gc), GFP_KERNEL);
240 if (!altera_gc)
241 return -ENOMEM;
242
243 raw_spin_lock_init(&altera_gc->gpio_lock);
244
245 if (device_property_read_u32(dev, "altr,ngpio", ®))
246 /* By default assume maximum ngpio */
247 altera_gc->gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
248 else
249 altera_gc->gc.ngpio = reg;
250
251 if (altera_gc->gc.ngpio > ALTERA_GPIO_MAX_NGPIO) {
252 dev_warn(&pdev->dev,
253 "ngpio is greater than %d, defaulting to %d\n",
254 ALTERA_GPIO_MAX_NGPIO, ALTERA_GPIO_MAX_NGPIO);
255 altera_gc->gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
256 }
257
258 altera_gc->gc.direction_input = altera_gpio_direction_input;
259 altera_gc->gc.direction_output = altera_gpio_direction_output;
260 altera_gc->gc.get = altera_gpio_get;
261 altera_gc->gc.set = altera_gpio_set;
262 altera_gc->gc.owner = THIS_MODULE;
263 altera_gc->gc.parent = &pdev->dev;
264 altera_gc->gc.base = -1;
265
266 altera_gc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", dev_fwnode(dev));
267 if (!altera_gc->gc.label)
268 return -ENOMEM;
269
270 altera_gc->regs = devm_platform_ioremap_resource(pdev, 0);
271 if (IS_ERR(altera_gc->regs))
272 return dev_err_probe(dev, PTR_ERR(altera_gc->regs), "failed to ioremap memory resource\n");
273
274 altera_gc->mapped_irq = platform_get_irq_optional(pdev, 0);
275 if (altera_gc->mapped_irq < 0)
276 goto skip_irq;
277
278 if (device_property_read_u32(dev, "altr,interrupt-type", ®)) {
279 dev_err(&pdev->dev,
280 "altr,interrupt-type value not set in device tree\n");
281 return -EINVAL;
282 }
283 altera_gc->interrupt_trigger = reg;
284
285 girq = &altera_gc->gc.irq;
286 gpio_irq_chip_set_chip(girq, &altera_gpio_irq_chip);
287
288 if (altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH)
289 girq->parent_handler = altera_gpio_irq_leveL_high_handler;
290 else
291 girq->parent_handler = altera_gpio_irq_edge_handler;
292 girq->num_parents = 1;
293 girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
294 GFP_KERNEL);
295 if (!girq->parents)
296 return -ENOMEM;
297 girq->default_type = IRQ_TYPE_NONE;
298 girq->handler = handle_bad_irq;
299 girq->parents[0] = altera_gc->mapped_irq;
300
301skip_irq:
302 ret = devm_gpiochip_add_data(dev, &altera_gc->gc, altera_gc);
303 if (ret) {
304 dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n");
305 return ret;
306 }
307
308 return 0;
309}
310
311static const struct of_device_id altera_gpio_of_match[] = {
312 { .compatible = "altr,pio-1.0", },
313 {},
314};
315MODULE_DEVICE_TABLE(of, altera_gpio_of_match);
316
317static struct platform_driver altera_gpio_driver = {
318 .driver = {
319 .name = "altera_gpio",
320 .of_match_table = altera_gpio_of_match,
321 },
322 .probe = altera_gpio_probe,
323};
324
325static int __init altera_gpio_init(void)
326{
327 return platform_driver_register(&altera_gpio_driver);
328}
329subsys_initcall(altera_gpio_init);
330
331static void __exit altera_gpio_exit(void)
332{
333 platform_driver_unregister(&altera_gpio_driver);
334}
335module_exit(altera_gpio_exit);
336
337MODULE_AUTHOR("Tien Hock Loh <thloh@altera.com>");
338MODULE_DESCRIPTION("Altera GPIO driver");
339MODULE_LICENSE("GPL");
1/*
2 * Copyright (C) 2013 Altera Corporation
3 * Based on gpio-mpc8xxx.c
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/io.h>
20#include <linux/module.h>
21#include <linux/of_gpio.h>
22#include <linux/platform_device.h>
23
24#define ALTERA_GPIO_MAX_NGPIO 32
25#define ALTERA_GPIO_DATA 0x0
26#define ALTERA_GPIO_DIR 0x4
27#define ALTERA_GPIO_IRQ_MASK 0x8
28#define ALTERA_GPIO_EDGE_CAP 0xc
29
30/**
31* struct altera_gpio_chip
32* @mmchip : memory mapped chip structure.
33* @gpio_lock : synchronization lock so that new irq/set/get requests
34 will be blocked until the current one completes.
35* @interrupt_trigger : specifies the hardware configured IRQ trigger type
36 (rising, falling, both, high)
37* @mapped_irq : kernel mapped irq number.
38*/
39struct altera_gpio_chip {
40 struct of_mm_gpio_chip mmchip;
41 spinlock_t gpio_lock;
42 int interrupt_trigger;
43 int mapped_irq;
44};
45
46static void altera_gpio_irq_unmask(struct irq_data *d)
47{
48 struct altera_gpio_chip *altera_gc;
49 struct of_mm_gpio_chip *mm_gc;
50 unsigned long flags;
51 u32 intmask;
52
53 altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
54 mm_gc = &altera_gc->mmchip;
55
56 spin_lock_irqsave(&altera_gc->gpio_lock, flags);
57 intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
58 /* Set ALTERA_GPIO_IRQ_MASK bit to unmask */
59 intmask |= BIT(irqd_to_hwirq(d));
60 writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
61 spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
62}
63
64static void altera_gpio_irq_mask(struct irq_data *d)
65{
66 struct altera_gpio_chip *altera_gc;
67 struct of_mm_gpio_chip *mm_gc;
68 unsigned long flags;
69 u32 intmask;
70
71 altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
72 mm_gc = &altera_gc->mmchip;
73
74 spin_lock_irqsave(&altera_gc->gpio_lock, flags);
75 intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
76 /* Clear ALTERA_GPIO_IRQ_MASK bit to mask */
77 intmask &= ~BIT(irqd_to_hwirq(d));
78 writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
79 spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
80}
81
82/**
83 * This controller's IRQ type is synthesized in hardware, so this function
84 * just checks if the requested set_type matches the synthesized IRQ type
85 */
86static int altera_gpio_irq_set_type(struct irq_data *d,
87 unsigned int type)
88{
89 struct altera_gpio_chip *altera_gc;
90
91 altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
92
93 if (type == IRQ_TYPE_NONE)
94 return 0;
95 if (type == IRQ_TYPE_LEVEL_HIGH &&
96 altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH)
97 return 0;
98 if (type == IRQ_TYPE_EDGE_RISING &&
99 altera_gc->interrupt_trigger == IRQ_TYPE_EDGE_RISING)
100 return 0;
101 if (type == IRQ_TYPE_EDGE_FALLING &&
102 altera_gc->interrupt_trigger == IRQ_TYPE_EDGE_FALLING)
103 return 0;
104 if (type == IRQ_TYPE_EDGE_BOTH &&
105 altera_gc->interrupt_trigger == IRQ_TYPE_EDGE_BOTH)
106 return 0;
107
108 return -EINVAL;
109}
110
111static unsigned int altera_gpio_irq_startup(struct irq_data *d)
112{
113 altera_gpio_irq_unmask(d);
114
115 return 0;
116}
117
118static struct irq_chip altera_irq_chip = {
119 .name = "altera-gpio",
120 .irq_mask = altera_gpio_irq_mask,
121 .irq_unmask = altera_gpio_irq_unmask,
122 .irq_set_type = altera_gpio_irq_set_type,
123 .irq_startup = altera_gpio_irq_startup,
124 .irq_shutdown = altera_gpio_irq_mask,
125};
126
127static int altera_gpio_get(struct gpio_chip *gc, unsigned offset)
128{
129 struct of_mm_gpio_chip *mm_gc;
130
131 mm_gc = to_of_mm_gpio_chip(gc);
132
133 return !!(readl(mm_gc->regs + ALTERA_GPIO_DATA) & BIT(offset));
134}
135
136static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
137{
138 struct of_mm_gpio_chip *mm_gc;
139 struct altera_gpio_chip *chip;
140 unsigned long flags;
141 unsigned int data_reg;
142
143 mm_gc = to_of_mm_gpio_chip(gc);
144 chip = gpiochip_get_data(gc);
145
146 spin_lock_irqsave(&chip->gpio_lock, flags);
147 data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
148 if (value)
149 data_reg |= BIT(offset);
150 else
151 data_reg &= ~BIT(offset);
152 writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
153 spin_unlock_irqrestore(&chip->gpio_lock, flags);
154}
155
156static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
157{
158 struct of_mm_gpio_chip *mm_gc;
159 struct altera_gpio_chip *chip;
160 unsigned long flags;
161 unsigned int gpio_ddr;
162
163 mm_gc = to_of_mm_gpio_chip(gc);
164 chip = gpiochip_get_data(gc);
165
166 spin_lock_irqsave(&chip->gpio_lock, flags);
167 /* Set pin as input, assumes software controlled IP */
168 gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
169 gpio_ddr &= ~BIT(offset);
170 writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
171 spin_unlock_irqrestore(&chip->gpio_lock, flags);
172
173 return 0;
174}
175
176static int altera_gpio_direction_output(struct gpio_chip *gc,
177 unsigned offset, int value)
178{
179 struct of_mm_gpio_chip *mm_gc;
180 struct altera_gpio_chip *chip;
181 unsigned long flags;
182 unsigned int data_reg, gpio_ddr;
183
184 mm_gc = to_of_mm_gpio_chip(gc);
185 chip = gpiochip_get_data(gc);
186
187 spin_lock_irqsave(&chip->gpio_lock, flags);
188 /* Sets the GPIO value */
189 data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
190 if (value)
191 data_reg |= BIT(offset);
192 else
193 data_reg &= ~BIT(offset);
194 writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
195
196 /* Set pin as output, assumes software controlled IP */
197 gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
198 gpio_ddr |= BIT(offset);
199 writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
200 spin_unlock_irqrestore(&chip->gpio_lock, flags);
201
202 return 0;
203}
204
205static void altera_gpio_irq_edge_handler(struct irq_desc *desc)
206{
207 struct altera_gpio_chip *altera_gc;
208 struct irq_chip *chip;
209 struct of_mm_gpio_chip *mm_gc;
210 struct irq_domain *irqdomain;
211 unsigned long status;
212 int i;
213
214 altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
215 chip = irq_desc_get_chip(desc);
216 mm_gc = &altera_gc->mmchip;
217 irqdomain = altera_gc->mmchip.gc.irqdomain;
218
219 chained_irq_enter(chip, desc);
220
221 while ((status =
222 (readl(mm_gc->regs + ALTERA_GPIO_EDGE_CAP) &
223 readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK)))) {
224 writel(status, mm_gc->regs + ALTERA_GPIO_EDGE_CAP);
225 for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
226 generic_handle_irq(irq_find_mapping(irqdomain, i));
227 }
228 }
229
230 chained_irq_exit(chip, desc);
231}
232
233
234static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc)
235{
236 struct altera_gpio_chip *altera_gc;
237 struct irq_chip *chip;
238 struct of_mm_gpio_chip *mm_gc;
239 struct irq_domain *irqdomain;
240 unsigned long status;
241 int i;
242
243 altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
244 chip = irq_desc_get_chip(desc);
245 mm_gc = &altera_gc->mmchip;
246 irqdomain = altera_gc->mmchip.gc.irqdomain;
247
248 chained_irq_enter(chip, desc);
249
250 status = readl(mm_gc->regs + ALTERA_GPIO_DATA);
251 status &= readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
252
253 for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
254 generic_handle_irq(irq_find_mapping(irqdomain, i));
255 }
256 chained_irq_exit(chip, desc);
257}
258
259static int altera_gpio_probe(struct platform_device *pdev)
260{
261 struct device_node *node = pdev->dev.of_node;
262 int reg, ret;
263 struct altera_gpio_chip *altera_gc;
264
265 altera_gc = devm_kzalloc(&pdev->dev, sizeof(*altera_gc), GFP_KERNEL);
266 if (!altera_gc)
267 return -ENOMEM;
268
269 spin_lock_init(&altera_gc->gpio_lock);
270
271 if (of_property_read_u32(node, "altr,ngpio", ®))
272 /* By default assume maximum ngpio */
273 altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
274 else
275 altera_gc->mmchip.gc.ngpio = reg;
276
277 if (altera_gc->mmchip.gc.ngpio > ALTERA_GPIO_MAX_NGPIO) {
278 dev_warn(&pdev->dev,
279 "ngpio is greater than %d, defaulting to %d\n",
280 ALTERA_GPIO_MAX_NGPIO, ALTERA_GPIO_MAX_NGPIO);
281 altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
282 }
283
284 altera_gc->mmchip.gc.direction_input = altera_gpio_direction_input;
285 altera_gc->mmchip.gc.direction_output = altera_gpio_direction_output;
286 altera_gc->mmchip.gc.get = altera_gpio_get;
287 altera_gc->mmchip.gc.set = altera_gpio_set;
288 altera_gc->mmchip.gc.owner = THIS_MODULE;
289 altera_gc->mmchip.gc.parent = &pdev->dev;
290
291 ret = of_mm_gpiochip_add_data(node, &altera_gc->mmchip, altera_gc);
292 if (ret) {
293 dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n");
294 return ret;
295 }
296
297 platform_set_drvdata(pdev, altera_gc);
298
299 altera_gc->mapped_irq = platform_get_irq(pdev, 0);
300
301 if (altera_gc->mapped_irq < 0)
302 goto skip_irq;
303
304 if (of_property_read_u32(node, "altr,interrupt-type", ®)) {
305 ret = -EINVAL;
306 dev_err(&pdev->dev,
307 "altr,interrupt-type value not set in device tree\n");
308 goto teardown;
309 }
310 altera_gc->interrupt_trigger = reg;
311
312 ret = gpiochip_irqchip_add(&altera_gc->mmchip.gc, &altera_irq_chip, 0,
313 handle_simple_irq, IRQ_TYPE_NONE);
314
315 if (ret) {
316 dev_err(&pdev->dev, "could not add irqchip\n");
317 goto teardown;
318 }
319
320 gpiochip_set_chained_irqchip(&altera_gc->mmchip.gc,
321 &altera_irq_chip,
322 altera_gc->mapped_irq,
323 altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH ?
324 altera_gpio_irq_leveL_high_handler :
325 altera_gpio_irq_edge_handler);
326
327skip_irq:
328 return 0;
329teardown:
330 of_mm_gpiochip_remove(&altera_gc->mmchip);
331 pr_err("%s: registration failed with status %d\n",
332 node->full_name, ret);
333
334 return ret;
335}
336
337static int altera_gpio_remove(struct platform_device *pdev)
338{
339 struct altera_gpio_chip *altera_gc = platform_get_drvdata(pdev);
340
341 of_mm_gpiochip_remove(&altera_gc->mmchip);
342
343 return 0;
344}
345
346static const struct of_device_id altera_gpio_of_match[] = {
347 { .compatible = "altr,pio-1.0", },
348 {},
349};
350MODULE_DEVICE_TABLE(of, altera_gpio_of_match);
351
352static struct platform_driver altera_gpio_driver = {
353 .driver = {
354 .name = "altera_gpio",
355 .of_match_table = of_match_ptr(altera_gpio_of_match),
356 },
357 .probe = altera_gpio_probe,
358 .remove = altera_gpio_remove,
359};
360
361static int __init altera_gpio_init(void)
362{
363 return platform_driver_register(&altera_gpio_driver);
364}
365subsys_initcall(altera_gpio_init);
366
367static void __exit altera_gpio_exit(void)
368{
369 platform_driver_unregister(&altera_gpio_driver);
370}
371module_exit(altera_gpio_exit);
372
373MODULE_AUTHOR("Tien Hock Loh <thloh@altera.com>");
374MODULE_DESCRIPTION("Altera GPIO driver");
375MODULE_LICENSE("GPL");