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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * GPIO driver for the ACCES 104-IDI-48 family
4 * Copyright (C) 2015 William Breathitt Gray
5 *
6 * This driver supports the following ACCES devices: 104-IDI-48A,
7 * 104-IDI-48AC, 104-IDI-48B, and 104-IDI-48BC.
8 */
9#include <linux/bits.h>
10#include <linux/device.h>
11#include <linux/err.h>
12#include <linux/gpio/regmap.h>
13#include <linux/interrupt.h>
14#include <linux/ioport.h>
15#include <linux/irq.h>
16#include <linux/isa.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/regmap.h>
21#include <linux/types.h>
22
23#define IDI_48_EXTENT 8
24#define MAX_NUM_IDI_48 max_num_isa_dev(IDI_48_EXTENT)
25
26static unsigned int base[MAX_NUM_IDI_48];
27static unsigned int num_idi_48;
28module_param_hw_array(base, uint, ioport, &num_idi_48, 0);
29MODULE_PARM_DESC(base, "ACCES 104-IDI-48 base addresses");
30
31static unsigned int irq[MAX_NUM_IDI_48];
32static unsigned int num_irq;
33module_param_hw_array(irq, uint, irq, &num_irq, 0);
34MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
35
36#define IDI48_IRQ_STATUS 0x7
37#define IDI48_IRQ_ENABLE IDI48_IRQ_STATUS
38
39static int idi_48_reg_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
40 unsigned int offset, unsigned int *reg,
41 unsigned int *mask)
42{
43 const unsigned int line = offset % 8;
44 const unsigned int stride = offset / 8;
45 const unsigned int port = (stride / 3) * 4;
46 const unsigned int port_stride = stride % 3;
47
48 *reg = base + port + port_stride;
49 *mask = BIT(line);
50
51 return 0;
52}
53
54static const struct regmap_range idi_48_wr_ranges[] = {
55 regmap_reg_range(0x0, 0x6),
56};
57static const struct regmap_range idi_48_rd_ranges[] = {
58 regmap_reg_range(0x0, 0x2), regmap_reg_range(0x4, 0x7),
59};
60static const struct regmap_range idi_48_precious_ranges[] = {
61 regmap_reg_range(0x7, 0x7),
62};
63static const struct regmap_access_table idi_48_wr_table = {
64 .no_ranges = idi_48_wr_ranges,
65 .n_no_ranges = ARRAY_SIZE(idi_48_wr_ranges),
66};
67static const struct regmap_access_table idi_48_rd_table = {
68 .yes_ranges = idi_48_rd_ranges,
69 .n_yes_ranges = ARRAY_SIZE(idi_48_rd_ranges),
70};
71static const struct regmap_access_table idi_48_precious_table = {
72 .yes_ranges = idi_48_precious_ranges,
73 .n_yes_ranges = ARRAY_SIZE(idi_48_precious_ranges),
74};
75static const struct regmap_config idi48_regmap_config = {
76 .reg_bits = 8,
77 .reg_stride = 1,
78 .val_bits = 8,
79 .io_port = true,
80 .max_register = 0x6,
81 .wr_table = &idi_48_wr_table,
82 .rd_table = &idi_48_rd_table,
83 .precious_table = &idi_48_precious_table,
84 .use_raw_spinlock = true,
85};
86
87#define IDI48_NGPIO 48
88
89#define IDI48_REGMAP_IRQ(_id) \
90 [_id] = { \
91 .mask = BIT((_id) / 8), \
92 .type = { .types_supported = IRQ_TYPE_EDGE_BOTH }, \
93 }
94
95static const struct regmap_irq idi48_regmap_irqs[IDI48_NGPIO] = {
96 IDI48_REGMAP_IRQ(0), IDI48_REGMAP_IRQ(1), IDI48_REGMAP_IRQ(2), /* 0-2 */
97 IDI48_REGMAP_IRQ(3), IDI48_REGMAP_IRQ(4), IDI48_REGMAP_IRQ(5), /* 3-5 */
98 IDI48_REGMAP_IRQ(6), IDI48_REGMAP_IRQ(7), IDI48_REGMAP_IRQ(8), /* 6-8 */
99 IDI48_REGMAP_IRQ(9), IDI48_REGMAP_IRQ(10), IDI48_REGMAP_IRQ(11), /* 9-11 */
100 IDI48_REGMAP_IRQ(12), IDI48_REGMAP_IRQ(13), IDI48_REGMAP_IRQ(14), /* 12-14 */
101 IDI48_REGMAP_IRQ(15), IDI48_REGMAP_IRQ(16), IDI48_REGMAP_IRQ(17), /* 15-17 */
102 IDI48_REGMAP_IRQ(18), IDI48_REGMAP_IRQ(19), IDI48_REGMAP_IRQ(20), /* 18-20 */
103 IDI48_REGMAP_IRQ(21), IDI48_REGMAP_IRQ(22), IDI48_REGMAP_IRQ(23), /* 21-23 */
104 IDI48_REGMAP_IRQ(24), IDI48_REGMAP_IRQ(25), IDI48_REGMAP_IRQ(26), /* 24-26 */
105 IDI48_REGMAP_IRQ(27), IDI48_REGMAP_IRQ(28), IDI48_REGMAP_IRQ(29), /* 27-29 */
106 IDI48_REGMAP_IRQ(30), IDI48_REGMAP_IRQ(31), IDI48_REGMAP_IRQ(32), /* 30-32 */
107 IDI48_REGMAP_IRQ(33), IDI48_REGMAP_IRQ(34), IDI48_REGMAP_IRQ(35), /* 33-35 */
108 IDI48_REGMAP_IRQ(36), IDI48_REGMAP_IRQ(37), IDI48_REGMAP_IRQ(38), /* 36-38 */
109 IDI48_REGMAP_IRQ(39), IDI48_REGMAP_IRQ(40), IDI48_REGMAP_IRQ(41), /* 39-41 */
110 IDI48_REGMAP_IRQ(42), IDI48_REGMAP_IRQ(43), IDI48_REGMAP_IRQ(44), /* 42-44 */
111 IDI48_REGMAP_IRQ(45), IDI48_REGMAP_IRQ(46), IDI48_REGMAP_IRQ(47), /* 45-47 */
112};
113
114static const char *idi48_names[IDI48_NGPIO] = {
115 "Bit 0 A", "Bit 1 A", "Bit 2 A", "Bit 3 A", "Bit 4 A", "Bit 5 A",
116 "Bit 6 A", "Bit 7 A", "Bit 8 A", "Bit 9 A", "Bit 10 A", "Bit 11 A",
117 "Bit 12 A", "Bit 13 A", "Bit 14 A", "Bit 15 A", "Bit 16 A", "Bit 17 A",
118 "Bit 18 A", "Bit 19 A", "Bit 20 A", "Bit 21 A", "Bit 22 A", "Bit 23 A",
119 "Bit 0 B", "Bit 1 B", "Bit 2 B", "Bit 3 B", "Bit 4 B", "Bit 5 B",
120 "Bit 6 B", "Bit 7 B", "Bit 8 B", "Bit 9 B", "Bit 10 B", "Bit 11 B",
121 "Bit 12 B", "Bit 13 B", "Bit 14 B", "Bit 15 B", "Bit 16 B", "Bit 17 B",
122 "Bit 18 B", "Bit 19 B", "Bit 20 B", "Bit 21 B", "Bit 22 B", "Bit 23 B"
123};
124
125static int idi_48_probe(struct device *dev, unsigned int id)
126{
127 const char *const name = dev_name(dev);
128 struct gpio_regmap_config config = {};
129 void __iomem *regs;
130 struct regmap *map;
131 struct regmap_irq_chip *chip;
132 struct regmap_irq_chip_data *chip_data;
133 int err;
134
135 if (!devm_request_region(dev, base[id], IDI_48_EXTENT, name)) {
136 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
137 base[id], base[id] + IDI_48_EXTENT);
138 return -EBUSY;
139 }
140
141 regs = devm_ioport_map(dev, base[id], IDI_48_EXTENT);
142 if (!regs)
143 return -ENOMEM;
144
145 map = devm_regmap_init_mmio(dev, regs, &idi48_regmap_config);
146 if (IS_ERR(map))
147 return dev_err_probe(dev, PTR_ERR(map),
148 "Unable to initialize register map\n");
149
150 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
151 if (!chip)
152 return -ENOMEM;
153
154 chip->name = name;
155 chip->status_base = IDI48_IRQ_STATUS;
156 chip->unmask_base = IDI48_IRQ_ENABLE;
157 chip->clear_on_unmask = true;
158 chip->num_regs = 1;
159 chip->irqs = idi48_regmap_irqs;
160 chip->num_irqs = ARRAY_SIZE(idi48_regmap_irqs);
161
162 err = devm_regmap_add_irq_chip(dev, map, irq[id], IRQF_SHARED, 0, chip,
163 &chip_data);
164 if (err)
165 return dev_err_probe(dev, err, "IRQ registration failed\n");
166
167 config.parent = dev;
168 config.regmap = map;
169 config.ngpio = IDI48_NGPIO;
170 config.names = idi48_names;
171 config.reg_dat_base = GPIO_REGMAP_ADDR(0x0);
172 config.ngpio_per_reg = 8;
173 config.reg_mask_xlate = idi_48_reg_mask_xlate;
174 config.irq_domain = regmap_irq_get_domain(chip_data);
175
176 return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &config));
177}
178
179static struct isa_driver idi_48_driver = {
180 .probe = idi_48_probe,
181 .driver = {
182 .name = "104-idi-48"
183 },
184};
185module_isa_driver_with_irq(idi_48_driver, num_idi_48, num_irq);
186
187MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
188MODULE_DESCRIPTION("ACCES 104-IDI-48 GPIO driver");
189MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * GPIO driver for the ACCES 104-IDI-48 family
4 * Copyright (C) 2015 William Breathitt Gray
5 *
6 * This driver supports the following ACCES devices: 104-IDI-48A,
7 * 104-IDI-48AC, 104-IDI-48B, and 104-IDI-48BC.
8 */
9#include <linux/bitmap.h>
10#include <linux/bitops.h>
11#include <linux/device.h>
12#include <linux/errno.h>
13#include <linux/gpio/driver.h>
14#include <linux/io.h>
15#include <linux/ioport.h>
16#include <linux/interrupt.h>
17#include <linux/irqdesc.h>
18#include <linux/isa.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/spinlock.h>
23
24#define IDI_48_EXTENT 8
25#define MAX_NUM_IDI_48 max_num_isa_dev(IDI_48_EXTENT)
26
27static unsigned int base[MAX_NUM_IDI_48];
28static unsigned int num_idi_48;
29module_param_hw_array(base, uint, ioport, &num_idi_48, 0);
30MODULE_PARM_DESC(base, "ACCES 104-IDI-48 base addresses");
31
32static unsigned int irq[MAX_NUM_IDI_48];
33module_param_hw_array(irq, uint, irq, NULL, 0);
34MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
35
36/**
37 * struct idi_48_gpio - GPIO device private data structure
38 * @chip: instance of the gpio_chip
39 * @lock: synchronization lock to prevent I/O race conditions
40 * @ack_lock: synchronization lock to prevent IRQ handler race conditions
41 * @irq_mask: input bits affected by interrupts
42 * @base: base port address of the GPIO device
43 * @cos_enb: Change-Of-State IRQ enable boundaries mask
44 */
45struct idi_48_gpio {
46 struct gpio_chip chip;
47 raw_spinlock_t lock;
48 spinlock_t ack_lock;
49 unsigned char irq_mask[6];
50 unsigned base;
51 unsigned char cos_enb;
52};
53
54static int idi_48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
55{
56 return 1;
57}
58
59static int idi_48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
60{
61 return 0;
62}
63
64static int idi_48_gpio_get(struct gpio_chip *chip, unsigned offset)
65{
66 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
67 unsigned i;
68 const unsigned register_offset[6] = { 0, 1, 2, 4, 5, 6 };
69 unsigned base_offset;
70 unsigned mask;
71
72 for (i = 0; i < 48; i += 8)
73 if (offset < i + 8) {
74 base_offset = register_offset[i / 8];
75 mask = BIT(offset - i);
76
77 return !!(inb(idi48gpio->base + base_offset) & mask);
78 }
79
80 /* The following line should never execute since offset < 48 */
81 return 0;
82}
83
84static int idi_48_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
85 unsigned long *bits)
86{
87 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
88 size_t i;
89 static const size_t ports[] = { 0, 1, 2, 4, 5, 6 };
90 const unsigned int gpio_reg_size = 8;
91 unsigned int bits_offset;
92 size_t word_index;
93 unsigned int word_offset;
94 unsigned long word_mask;
95 const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0);
96 unsigned long port_state;
97
98 /* clear bits array to a clean slate */
99 bitmap_zero(bits, chip->ngpio);
100
101 /* get bits are evaluated a gpio port register at a time */
102 for (i = 0; i < ARRAY_SIZE(ports); i++) {
103 /* gpio offset in bits array */
104 bits_offset = i * gpio_reg_size;
105
106 /* word index for bits array */
107 word_index = BIT_WORD(bits_offset);
108
109 /* gpio offset within current word of bits array */
110 word_offset = bits_offset % BITS_PER_LONG;
111
112 /* mask of get bits for current gpio within current word */
113 word_mask = mask[word_index] & (port_mask << word_offset);
114 if (!word_mask) {
115 /* no get bits in this port so skip to next one */
116 continue;
117 }
118
119 /* read bits from current gpio port */
120 port_state = inb(idi48gpio->base + ports[i]);
121
122 /* store acquired bits at respective bits array offset */
123 bits[word_index] |= (port_state << word_offset) & word_mask;
124 }
125
126 return 0;
127}
128
129static void idi_48_irq_ack(struct irq_data *data)
130{
131}
132
133static void idi_48_irq_mask(struct irq_data *data)
134{
135 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
136 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
137 const unsigned offset = irqd_to_hwirq(data);
138 unsigned i;
139 unsigned mask;
140 unsigned boundary;
141 unsigned long flags;
142
143 for (i = 0; i < 48; i += 8)
144 if (offset < i + 8) {
145 mask = BIT(offset - i);
146 boundary = i / 8;
147
148 idi48gpio->irq_mask[boundary] &= ~mask;
149
150 if (!idi48gpio->irq_mask[boundary]) {
151 idi48gpio->cos_enb &= ~BIT(boundary);
152
153 raw_spin_lock_irqsave(&idi48gpio->lock, flags);
154
155 outb(idi48gpio->cos_enb, idi48gpio->base + 7);
156
157 raw_spin_unlock_irqrestore(&idi48gpio->lock,
158 flags);
159 }
160
161 return;
162 }
163}
164
165static void idi_48_irq_unmask(struct irq_data *data)
166{
167 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
168 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
169 const unsigned offset = irqd_to_hwirq(data);
170 unsigned i;
171 unsigned mask;
172 unsigned boundary;
173 unsigned prev_irq_mask;
174 unsigned long flags;
175
176 for (i = 0; i < 48; i += 8)
177 if (offset < i + 8) {
178 mask = BIT(offset - i);
179 boundary = i / 8;
180 prev_irq_mask = idi48gpio->irq_mask[boundary];
181
182 idi48gpio->irq_mask[boundary] |= mask;
183
184 if (!prev_irq_mask) {
185 idi48gpio->cos_enb |= BIT(boundary);
186
187 raw_spin_lock_irqsave(&idi48gpio->lock, flags);
188
189 outb(idi48gpio->cos_enb, idi48gpio->base + 7);
190
191 raw_spin_unlock_irqrestore(&idi48gpio->lock,
192 flags);
193 }
194
195 return;
196 }
197}
198
199static int idi_48_irq_set_type(struct irq_data *data, unsigned flow_type)
200{
201 /* The only valid irq types are none and both-edges */
202 if (flow_type != IRQ_TYPE_NONE &&
203 (flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
204 return -EINVAL;
205
206 return 0;
207}
208
209static struct irq_chip idi_48_irqchip = {
210 .name = "104-idi-48",
211 .irq_ack = idi_48_irq_ack,
212 .irq_mask = idi_48_irq_mask,
213 .irq_unmask = idi_48_irq_unmask,
214 .irq_set_type = idi_48_irq_set_type
215};
216
217static irqreturn_t idi_48_irq_handler(int irq, void *dev_id)
218{
219 struct idi_48_gpio *const idi48gpio = dev_id;
220 unsigned long cos_status;
221 unsigned long boundary;
222 unsigned long irq_mask;
223 unsigned long bit_num;
224 unsigned long gpio;
225 struct gpio_chip *const chip = &idi48gpio->chip;
226
227 spin_lock(&idi48gpio->ack_lock);
228
229 raw_spin_lock(&idi48gpio->lock);
230
231 cos_status = inb(idi48gpio->base + 7);
232
233 raw_spin_unlock(&idi48gpio->lock);
234
235 /* IRQ Status (bit 6) is active low (0 = IRQ generated by device) */
236 if (cos_status & BIT(6)) {
237 spin_unlock(&idi48gpio->ack_lock);
238 return IRQ_NONE;
239 }
240
241 /* Bit 0-5 indicate which Change-Of-State boundary triggered the IRQ */
242 cos_status &= 0x3F;
243
244 for_each_set_bit(boundary, &cos_status, 6) {
245 irq_mask = idi48gpio->irq_mask[boundary];
246
247 for_each_set_bit(bit_num, &irq_mask, 8) {
248 gpio = bit_num + boundary * 8;
249
250 generic_handle_irq(irq_find_mapping(chip->irq.domain,
251 gpio));
252 }
253 }
254
255 spin_unlock(&idi48gpio->ack_lock);
256
257 return IRQ_HANDLED;
258}
259
260#define IDI48_NGPIO 48
261static const char *idi48_names[IDI48_NGPIO] = {
262 "Bit 0 A", "Bit 1 A", "Bit 2 A", "Bit 3 A", "Bit 4 A", "Bit 5 A",
263 "Bit 6 A", "Bit 7 A", "Bit 8 A", "Bit 9 A", "Bit 10 A", "Bit 11 A",
264 "Bit 12 A", "Bit 13 A", "Bit 14 A", "Bit 15 A", "Bit 16 A", "Bit 17 A",
265 "Bit 18 A", "Bit 19 A", "Bit 20 A", "Bit 21 A", "Bit 22 A", "Bit 23 A",
266 "Bit 0 B", "Bit 1 B", "Bit 2 B", "Bit 3 B", "Bit 4 B", "Bit 5 B",
267 "Bit 6 B", "Bit 7 B", "Bit 8 B", "Bit 9 B", "Bit 10 B", "Bit 11 B",
268 "Bit 12 B", "Bit 13 B", "Bit 14 B", "Bit 15 B", "Bit 16 B", "Bit 17 B",
269 "Bit 18 B", "Bit 19 B", "Bit 20 B", "Bit 21 B", "Bit 22 B", "Bit 23 B"
270};
271
272static int idi_48_probe(struct device *dev, unsigned int id)
273{
274 struct idi_48_gpio *idi48gpio;
275 const char *const name = dev_name(dev);
276 int err;
277
278 idi48gpio = devm_kzalloc(dev, sizeof(*idi48gpio), GFP_KERNEL);
279 if (!idi48gpio)
280 return -ENOMEM;
281
282 if (!devm_request_region(dev, base[id], IDI_48_EXTENT, name)) {
283 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
284 base[id], base[id] + IDI_48_EXTENT);
285 return -EBUSY;
286 }
287
288 idi48gpio->chip.label = name;
289 idi48gpio->chip.parent = dev;
290 idi48gpio->chip.owner = THIS_MODULE;
291 idi48gpio->chip.base = -1;
292 idi48gpio->chip.ngpio = IDI48_NGPIO;
293 idi48gpio->chip.names = idi48_names;
294 idi48gpio->chip.get_direction = idi_48_gpio_get_direction;
295 idi48gpio->chip.direction_input = idi_48_gpio_direction_input;
296 idi48gpio->chip.get = idi_48_gpio_get;
297 idi48gpio->chip.get_multiple = idi_48_gpio_get_multiple;
298 idi48gpio->base = base[id];
299
300 raw_spin_lock_init(&idi48gpio->lock);
301 spin_lock_init(&idi48gpio->ack_lock);
302
303 err = devm_gpiochip_add_data(dev, &idi48gpio->chip, idi48gpio);
304 if (err) {
305 dev_err(dev, "GPIO registering failed (%d)\n", err);
306 return err;
307 }
308
309 /* Disable IRQ by default */
310 outb(0, base[id] + 7);
311 inb(base[id] + 7);
312
313 err = gpiochip_irqchip_add(&idi48gpio->chip, &idi_48_irqchip, 0,
314 handle_edge_irq, IRQ_TYPE_NONE);
315 if (err) {
316 dev_err(dev, "Could not add irqchip (%d)\n", err);
317 return err;
318 }
319
320 err = devm_request_irq(dev, irq[id], idi_48_irq_handler, IRQF_SHARED,
321 name, idi48gpio);
322 if (err) {
323 dev_err(dev, "IRQ handler registering failed (%d)\n", err);
324 return err;
325 }
326
327 return 0;
328}
329
330static struct isa_driver idi_48_driver = {
331 .probe = idi_48_probe,
332 .driver = {
333 .name = "104-idi-48"
334 },
335};
336module_isa_driver(idi_48_driver, num_idi_48);
337
338MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
339MODULE_DESCRIPTION("ACCES 104-IDI-48 GPIO driver");
340MODULE_LICENSE("GPL v2");