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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * GPIO driver for the ACCES 104-IDI-48 family
4 * Copyright (C) 2015 William Breathitt Gray
5 *
6 * This driver supports the following ACCES devices: 104-IDI-48A,
7 * 104-IDI-48AC, 104-IDI-48B, and 104-IDI-48BC.
8 */
9#include <linux/bits.h>
10#include <linux/device.h>
11#include <linux/err.h>
12#include <linux/gpio/regmap.h>
13#include <linux/interrupt.h>
14#include <linux/ioport.h>
15#include <linux/irq.h>
16#include <linux/isa.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/regmap.h>
21#include <linux/types.h>
22
23#define IDI_48_EXTENT 8
24#define MAX_NUM_IDI_48 max_num_isa_dev(IDI_48_EXTENT)
25
26static unsigned int base[MAX_NUM_IDI_48];
27static unsigned int num_idi_48;
28module_param_hw_array(base, uint, ioport, &num_idi_48, 0);
29MODULE_PARM_DESC(base, "ACCES 104-IDI-48 base addresses");
30
31static unsigned int irq[MAX_NUM_IDI_48];
32static unsigned int num_irq;
33module_param_hw_array(irq, uint, irq, &num_irq, 0);
34MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
35
36#define IDI48_IRQ_STATUS 0x7
37#define IDI48_IRQ_ENABLE IDI48_IRQ_STATUS
38
39static int idi_48_reg_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
40 unsigned int offset, unsigned int *reg,
41 unsigned int *mask)
42{
43 const unsigned int line = offset % 8;
44 const unsigned int stride = offset / 8;
45 const unsigned int port = (stride / 3) * 4;
46 const unsigned int port_stride = stride % 3;
47
48 *reg = base + port + port_stride;
49 *mask = BIT(line);
50
51 return 0;
52}
53
54static const struct regmap_range idi_48_wr_ranges[] = {
55 regmap_reg_range(0x0, 0x6),
56};
57static const struct regmap_range idi_48_rd_ranges[] = {
58 regmap_reg_range(0x0, 0x2), regmap_reg_range(0x4, 0x7),
59};
60static const struct regmap_range idi_48_precious_ranges[] = {
61 regmap_reg_range(0x7, 0x7),
62};
63static const struct regmap_access_table idi_48_wr_table = {
64 .no_ranges = idi_48_wr_ranges,
65 .n_no_ranges = ARRAY_SIZE(idi_48_wr_ranges),
66};
67static const struct regmap_access_table idi_48_rd_table = {
68 .yes_ranges = idi_48_rd_ranges,
69 .n_yes_ranges = ARRAY_SIZE(idi_48_rd_ranges),
70};
71static const struct regmap_access_table idi_48_precious_table = {
72 .yes_ranges = idi_48_precious_ranges,
73 .n_yes_ranges = ARRAY_SIZE(idi_48_precious_ranges),
74};
75static const struct regmap_config idi48_regmap_config = {
76 .reg_bits = 8,
77 .reg_stride = 1,
78 .val_bits = 8,
79 .io_port = true,
80 .max_register = 0x6,
81 .wr_table = &idi_48_wr_table,
82 .rd_table = &idi_48_rd_table,
83 .precious_table = &idi_48_precious_table,
84 .use_raw_spinlock = true,
85};
86
87#define IDI48_NGPIO 48
88
89#define IDI48_REGMAP_IRQ(_id) \
90 [_id] = { \
91 .mask = BIT((_id) / 8), \
92 .type = { .types_supported = IRQ_TYPE_EDGE_BOTH }, \
93 }
94
95static const struct regmap_irq idi48_regmap_irqs[IDI48_NGPIO] = {
96 IDI48_REGMAP_IRQ(0), IDI48_REGMAP_IRQ(1), IDI48_REGMAP_IRQ(2), /* 0-2 */
97 IDI48_REGMAP_IRQ(3), IDI48_REGMAP_IRQ(4), IDI48_REGMAP_IRQ(5), /* 3-5 */
98 IDI48_REGMAP_IRQ(6), IDI48_REGMAP_IRQ(7), IDI48_REGMAP_IRQ(8), /* 6-8 */
99 IDI48_REGMAP_IRQ(9), IDI48_REGMAP_IRQ(10), IDI48_REGMAP_IRQ(11), /* 9-11 */
100 IDI48_REGMAP_IRQ(12), IDI48_REGMAP_IRQ(13), IDI48_REGMAP_IRQ(14), /* 12-14 */
101 IDI48_REGMAP_IRQ(15), IDI48_REGMAP_IRQ(16), IDI48_REGMAP_IRQ(17), /* 15-17 */
102 IDI48_REGMAP_IRQ(18), IDI48_REGMAP_IRQ(19), IDI48_REGMAP_IRQ(20), /* 18-20 */
103 IDI48_REGMAP_IRQ(21), IDI48_REGMAP_IRQ(22), IDI48_REGMAP_IRQ(23), /* 21-23 */
104 IDI48_REGMAP_IRQ(24), IDI48_REGMAP_IRQ(25), IDI48_REGMAP_IRQ(26), /* 24-26 */
105 IDI48_REGMAP_IRQ(27), IDI48_REGMAP_IRQ(28), IDI48_REGMAP_IRQ(29), /* 27-29 */
106 IDI48_REGMAP_IRQ(30), IDI48_REGMAP_IRQ(31), IDI48_REGMAP_IRQ(32), /* 30-32 */
107 IDI48_REGMAP_IRQ(33), IDI48_REGMAP_IRQ(34), IDI48_REGMAP_IRQ(35), /* 33-35 */
108 IDI48_REGMAP_IRQ(36), IDI48_REGMAP_IRQ(37), IDI48_REGMAP_IRQ(38), /* 36-38 */
109 IDI48_REGMAP_IRQ(39), IDI48_REGMAP_IRQ(40), IDI48_REGMAP_IRQ(41), /* 39-41 */
110 IDI48_REGMAP_IRQ(42), IDI48_REGMAP_IRQ(43), IDI48_REGMAP_IRQ(44), /* 42-44 */
111 IDI48_REGMAP_IRQ(45), IDI48_REGMAP_IRQ(46), IDI48_REGMAP_IRQ(47), /* 45-47 */
112};
113
114static const char *idi48_names[IDI48_NGPIO] = {
115 "Bit 0 A", "Bit 1 A", "Bit 2 A", "Bit 3 A", "Bit 4 A", "Bit 5 A",
116 "Bit 6 A", "Bit 7 A", "Bit 8 A", "Bit 9 A", "Bit 10 A", "Bit 11 A",
117 "Bit 12 A", "Bit 13 A", "Bit 14 A", "Bit 15 A", "Bit 16 A", "Bit 17 A",
118 "Bit 18 A", "Bit 19 A", "Bit 20 A", "Bit 21 A", "Bit 22 A", "Bit 23 A",
119 "Bit 0 B", "Bit 1 B", "Bit 2 B", "Bit 3 B", "Bit 4 B", "Bit 5 B",
120 "Bit 6 B", "Bit 7 B", "Bit 8 B", "Bit 9 B", "Bit 10 B", "Bit 11 B",
121 "Bit 12 B", "Bit 13 B", "Bit 14 B", "Bit 15 B", "Bit 16 B", "Bit 17 B",
122 "Bit 18 B", "Bit 19 B", "Bit 20 B", "Bit 21 B", "Bit 22 B", "Bit 23 B"
123};
124
125static int idi_48_probe(struct device *dev, unsigned int id)
126{
127 const char *const name = dev_name(dev);
128 struct gpio_regmap_config config = {};
129 void __iomem *regs;
130 struct regmap *map;
131 struct regmap_irq_chip *chip;
132 struct regmap_irq_chip_data *chip_data;
133 int err;
134
135 if (!devm_request_region(dev, base[id], IDI_48_EXTENT, name)) {
136 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
137 base[id], base[id] + IDI_48_EXTENT);
138 return -EBUSY;
139 }
140
141 regs = devm_ioport_map(dev, base[id], IDI_48_EXTENT);
142 if (!regs)
143 return -ENOMEM;
144
145 map = devm_regmap_init_mmio(dev, regs, &idi48_regmap_config);
146 if (IS_ERR(map))
147 return dev_err_probe(dev, PTR_ERR(map),
148 "Unable to initialize register map\n");
149
150 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
151 if (!chip)
152 return -ENOMEM;
153
154 chip->name = name;
155 chip->status_base = IDI48_IRQ_STATUS;
156 chip->unmask_base = IDI48_IRQ_ENABLE;
157 chip->clear_on_unmask = true;
158 chip->num_regs = 1;
159 chip->irqs = idi48_regmap_irqs;
160 chip->num_irqs = ARRAY_SIZE(idi48_regmap_irqs);
161
162 err = devm_regmap_add_irq_chip(dev, map, irq[id], IRQF_SHARED, 0, chip,
163 &chip_data);
164 if (err)
165 return dev_err_probe(dev, err, "IRQ registration failed\n");
166
167 config.parent = dev;
168 config.regmap = map;
169 config.ngpio = IDI48_NGPIO;
170 config.names = idi48_names;
171 config.reg_dat_base = GPIO_REGMAP_ADDR(0x0);
172 config.ngpio_per_reg = 8;
173 config.reg_mask_xlate = idi_48_reg_mask_xlate;
174 config.irq_domain = regmap_irq_get_domain(chip_data);
175
176 return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &config));
177}
178
179static struct isa_driver idi_48_driver = {
180 .probe = idi_48_probe,
181 .driver = {
182 .name = "104-idi-48"
183 },
184};
185module_isa_driver_with_irq(idi_48_driver, num_idi_48, num_irq);
186
187MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
188MODULE_DESCRIPTION("ACCES 104-IDI-48 GPIO driver");
189MODULE_LICENSE("GPL v2");
1/*
2 * GPIO driver for the ACCES 104-IDI-48 family
3 * Copyright (C) 2015 William Breathitt Gray
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 */
14#include <linux/bitops.h>
15#include <linux/device.h>
16#include <linux/errno.h>
17#include <linux/gpio/driver.h>
18#include <linux/io.h>
19#include <linux/ioport.h>
20#include <linux/interrupt.h>
21#include <linux/irqdesc.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/platform_device.h>
26#include <linux/spinlock.h>
27
28static unsigned idi_48_base;
29module_param(idi_48_base, uint, 0);
30MODULE_PARM_DESC(idi_48_base, "ACCES 104-IDI-48 base address");
31static unsigned idi_48_irq;
32module_param(idi_48_irq, uint, 0);
33MODULE_PARM_DESC(idi_48_irq, "ACCES 104-IDI-48 interrupt line number");
34
35/**
36 * struct idi_48_gpio - GPIO device private data structure
37 * @chip: instance of the gpio_chip
38 * @lock: synchronization lock to prevent I/O race conditions
39 * @ack_lock: synchronization lock to prevent IRQ handler race conditions
40 * @irq_mask: input bits affected by interrupts
41 * @base: base port address of the GPIO device
42 * @irq: Interrupt line number
43 * @cos_enb: Change-Of-State IRQ enable boundaries mask
44 */
45struct idi_48_gpio {
46 struct gpio_chip chip;
47 spinlock_t lock;
48 spinlock_t ack_lock;
49 unsigned char irq_mask[6];
50 unsigned base;
51 unsigned irq;
52 unsigned char cos_enb;
53};
54
55static int idi_48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
56{
57 return 1;
58}
59
60static int idi_48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
61{
62 return 0;
63}
64
65static int idi_48_gpio_get(struct gpio_chip *chip, unsigned offset)
66{
67 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
68 unsigned i;
69 const unsigned register_offset[6] = { 0, 1, 2, 4, 5, 6 };
70 unsigned base_offset;
71 unsigned mask;
72
73 for (i = 0; i < 48; i += 8)
74 if (offset < i + 8) {
75 base_offset = register_offset[i / 8];
76 mask = BIT(offset - i);
77
78 return !!(inb(idi48gpio->base + base_offset) & mask);
79 }
80
81 /* The following line should never execute since offset < 48 */
82 return 0;
83}
84
85static void idi_48_irq_ack(struct irq_data *data)
86{
87}
88
89static void idi_48_irq_mask(struct irq_data *data)
90{
91 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
92 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
93 const unsigned offset = irqd_to_hwirq(data);
94 unsigned i;
95 unsigned mask;
96 unsigned boundary;
97 unsigned long flags;
98
99 for (i = 0; i < 48; i += 8)
100 if (offset < i + 8) {
101 mask = BIT(offset - i);
102 boundary = i / 8;
103
104 idi48gpio->irq_mask[boundary] &= ~mask;
105
106 if (!idi48gpio->irq_mask[boundary]) {
107 idi48gpio->cos_enb &= ~BIT(boundary);
108
109 spin_lock_irqsave(&idi48gpio->lock, flags);
110
111 outb(idi48gpio->cos_enb, idi48gpio->base + 7);
112
113 spin_unlock_irqrestore(&idi48gpio->lock, flags);
114 }
115
116 return;
117 }
118}
119
120static void idi_48_irq_unmask(struct irq_data *data)
121{
122 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
123 struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
124 const unsigned offset = irqd_to_hwirq(data);
125 unsigned i;
126 unsigned mask;
127 unsigned boundary;
128 unsigned prev_irq_mask;
129 unsigned long flags;
130
131 for (i = 0; i < 48; i += 8)
132 if (offset < i + 8) {
133 mask = BIT(offset - i);
134 boundary = i / 8;
135 prev_irq_mask = idi48gpio->irq_mask[boundary];
136
137 idi48gpio->irq_mask[boundary] |= mask;
138
139 if (!prev_irq_mask) {
140 idi48gpio->cos_enb |= BIT(boundary);
141
142 spin_lock_irqsave(&idi48gpio->lock, flags);
143
144 outb(idi48gpio->cos_enb, idi48gpio->base + 7);
145
146 spin_unlock_irqrestore(&idi48gpio->lock, flags);
147 }
148
149 return;
150 }
151}
152
153static int idi_48_irq_set_type(struct irq_data *data, unsigned flow_type)
154{
155 /* The only valid irq types are none and both-edges */
156 if (flow_type != IRQ_TYPE_NONE &&
157 (flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
158 return -EINVAL;
159
160 return 0;
161}
162
163static struct irq_chip idi_48_irqchip = {
164 .name = "104-idi-48",
165 .irq_ack = idi_48_irq_ack,
166 .irq_mask = idi_48_irq_mask,
167 .irq_unmask = idi_48_irq_unmask,
168 .irq_set_type = idi_48_irq_set_type
169};
170
171static irqreturn_t idi_48_irq_handler(int irq, void *dev_id)
172{
173 struct idi_48_gpio *const idi48gpio = dev_id;
174 unsigned long cos_status;
175 unsigned long boundary;
176 unsigned long irq_mask;
177 unsigned long bit_num;
178 unsigned long gpio;
179 struct gpio_chip *const chip = &idi48gpio->chip;
180
181 spin_lock(&idi48gpio->ack_lock);
182
183 spin_lock(&idi48gpio->lock);
184
185 cos_status = inb(idi48gpio->base + 7);
186
187 spin_unlock(&idi48gpio->lock);
188
189 /* IRQ Status (bit 6) is active low (0 = IRQ generated by device) */
190 if (cos_status & BIT(6)) {
191 spin_unlock(&idi48gpio->ack_lock);
192 return IRQ_NONE;
193 }
194
195 /* Bit 0-5 indicate which Change-Of-State boundary triggered the IRQ */
196 cos_status &= 0x3F;
197
198 for_each_set_bit(boundary, &cos_status, 6) {
199 irq_mask = idi48gpio->irq_mask[boundary];
200
201 for_each_set_bit(bit_num, &irq_mask, 8) {
202 gpio = bit_num + boundary * 8;
203
204 generic_handle_irq(irq_find_mapping(chip->irqdomain,
205 gpio));
206 }
207 }
208
209 spin_unlock(&idi48gpio->ack_lock);
210
211 return IRQ_HANDLED;
212}
213
214static int __init idi_48_probe(struct platform_device *pdev)
215{
216 struct device *dev = &pdev->dev;
217 struct idi_48_gpio *idi48gpio;
218 const unsigned base = idi_48_base;
219 const unsigned extent = 8;
220 const char *const name = dev_name(dev);
221 int err;
222 const unsigned irq = idi_48_irq;
223
224 idi48gpio = devm_kzalloc(dev, sizeof(*idi48gpio), GFP_KERNEL);
225 if (!idi48gpio)
226 return -ENOMEM;
227
228 if (!devm_request_region(dev, base, extent, name)) {
229 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
230 base, base + extent);
231 return -EBUSY;
232 }
233
234 idi48gpio->chip.label = name;
235 idi48gpio->chip.parent = dev;
236 idi48gpio->chip.owner = THIS_MODULE;
237 idi48gpio->chip.base = -1;
238 idi48gpio->chip.ngpio = 48;
239 idi48gpio->chip.get_direction = idi_48_gpio_get_direction;
240 idi48gpio->chip.direction_input = idi_48_gpio_direction_input;
241 idi48gpio->chip.get = idi_48_gpio_get;
242 idi48gpio->base = base;
243 idi48gpio->irq = irq;
244
245 spin_lock_init(&idi48gpio->lock);
246
247 dev_set_drvdata(dev, idi48gpio);
248
249 err = gpiochip_add_data(&idi48gpio->chip, idi48gpio);
250 if (err) {
251 dev_err(dev, "GPIO registering failed (%d)\n", err);
252 return err;
253 }
254
255 /* Disable IRQ by default */
256 outb(0, base + 7);
257 inb(base + 7);
258
259 err = gpiochip_irqchip_add(&idi48gpio->chip, &idi_48_irqchip, 0,
260 handle_edge_irq, IRQ_TYPE_NONE);
261 if (err) {
262 dev_err(dev, "Could not add irqchip (%d)\n", err);
263 goto err_gpiochip_remove;
264 }
265
266 err = request_irq(irq, idi_48_irq_handler, IRQF_SHARED, name,
267 idi48gpio);
268 if (err) {
269 dev_err(dev, "IRQ handler registering failed (%d)\n", err);
270 goto err_gpiochip_remove;
271 }
272
273 return 0;
274
275err_gpiochip_remove:
276 gpiochip_remove(&idi48gpio->chip);
277 return err;
278}
279
280static int idi_48_remove(struct platform_device *pdev)
281{
282 struct idi_48_gpio *const idi48gpio = platform_get_drvdata(pdev);
283
284 free_irq(idi48gpio->irq, idi48gpio);
285 gpiochip_remove(&idi48gpio->chip);
286
287 return 0;
288}
289
290static struct platform_device *idi_48_device;
291
292static struct platform_driver idi_48_driver = {
293 .driver = {
294 .name = "104-idi-48"
295 },
296 .remove = idi_48_remove
297};
298
299static void __exit idi_48_exit(void)
300{
301 platform_device_unregister(idi_48_device);
302 platform_driver_unregister(&idi_48_driver);
303}
304
305static int __init idi_48_init(void)
306{
307 int err;
308
309 idi_48_device = platform_device_alloc(idi_48_driver.driver.name, -1);
310 if (!idi_48_device)
311 return -ENOMEM;
312
313 err = platform_device_add(idi_48_device);
314 if (err)
315 goto err_platform_device;
316
317 err = platform_driver_probe(&idi_48_driver, idi_48_probe);
318 if (err)
319 goto err_platform_driver;
320
321 return 0;
322
323err_platform_driver:
324 platform_device_del(idi_48_device);
325err_platform_device:
326 platform_device_put(idi_48_device);
327 return err;
328}
329
330module_init(idi_48_init);
331module_exit(idi_48_exit);
332
333MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
334MODULE_DESCRIPTION("ACCES 104-IDI-48 GPIO driver");
335MODULE_LICENSE("GPL v2");