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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) 2010-2011 Picochip Ltd., Jamie Iles
4 */
5#include <crypto/internal/aead.h>
6#include <crypto/aes.h>
7#include <crypto/algapi.h>
8#include <crypto/authenc.h>
9#include <crypto/internal/des.h>
10#include <crypto/md5.h>
11#include <crypto/sha.h>
12#include <crypto/internal/skcipher.h>
13#include <linux/clk.h>
14#include <linux/crypto.h>
15#include <linux/delay.h>
16#include <linux/dma-mapping.h>
17#include <linux/dmapool.h>
18#include <linux/err.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/list.h>
23#include <linux/module.h>
24#include <linux/of.h>
25#include <linux/platform_device.h>
26#include <linux/pm.h>
27#include <linux/rtnetlink.h>
28#include <linux/scatterlist.h>
29#include <linux/sched.h>
30#include <linux/sizes.h>
31#include <linux/slab.h>
32#include <linux/timer.h>
33
34#include "picoxcell_crypto_regs.h"
35
36/*
37 * The threshold for the number of entries in the CMD FIFO available before
38 * the CMD0_CNT interrupt is raised. Increasing this value will reduce the
39 * number of interrupts raised to the CPU.
40 */
41#define CMD0_IRQ_THRESHOLD 1
42
43/*
44 * The timeout period (in jiffies) for a PDU. When the the number of PDUs in
45 * flight is greater than the STAT_IRQ_THRESHOLD or 0 the timer is disabled.
46 * When there are packets in flight but lower than the threshold, we enable
47 * the timer and at expiry, attempt to remove any processed packets from the
48 * queue and if there are still packets left, schedule the timer again.
49 */
50#define PACKET_TIMEOUT 1
51
52/* The priority to register each algorithm with. */
53#define SPACC_CRYPTO_ALG_PRIORITY 10000
54
55#define SPACC_CRYPTO_KASUMI_F8_KEY_LEN 16
56#define SPACC_CRYPTO_IPSEC_CIPHER_PG_SZ 64
57#define SPACC_CRYPTO_IPSEC_HASH_PG_SZ 64
58#define SPACC_CRYPTO_IPSEC_MAX_CTXS 32
59#define SPACC_CRYPTO_IPSEC_FIFO_SZ 32
60#define SPACC_CRYPTO_L2_CIPHER_PG_SZ 64
61#define SPACC_CRYPTO_L2_HASH_PG_SZ 64
62#define SPACC_CRYPTO_L2_MAX_CTXS 128
63#define SPACC_CRYPTO_L2_FIFO_SZ 128
64
65#define MAX_DDT_LEN 16
66
67/* DDT format. This must match the hardware DDT format exactly. */
68struct spacc_ddt {
69 dma_addr_t p;
70 u32 len;
71};
72
73/*
74 * Asynchronous crypto request structure.
75 *
76 * This structure defines a request that is either queued for processing or
77 * being processed.
78 */
79struct spacc_req {
80 struct list_head list;
81 struct spacc_engine *engine;
82 struct crypto_async_request *req;
83 int result;
84 bool is_encrypt;
85 unsigned ctx_id;
86 dma_addr_t src_addr, dst_addr;
87 struct spacc_ddt *src_ddt, *dst_ddt;
88 void (*complete)(struct spacc_req *req);
89};
90
91struct spacc_aead {
92 unsigned long ctrl_default;
93 unsigned long type;
94 struct aead_alg alg;
95 struct spacc_engine *engine;
96 struct list_head entry;
97 int key_offs;
98 int iv_offs;
99};
100
101struct spacc_engine {
102 void __iomem *regs;
103 struct list_head pending;
104 int next_ctx;
105 spinlock_t hw_lock;
106 int in_flight;
107 struct list_head completed;
108 struct list_head in_progress;
109 struct tasklet_struct complete;
110 unsigned long fifo_sz;
111 void __iomem *cipher_ctx_base;
112 void __iomem *hash_key_base;
113 struct spacc_alg *algs;
114 unsigned num_algs;
115 struct list_head registered_algs;
116 struct spacc_aead *aeads;
117 unsigned num_aeads;
118 struct list_head registered_aeads;
119 size_t cipher_pg_sz;
120 size_t hash_pg_sz;
121 const char *name;
122 struct clk *clk;
123 struct device *dev;
124 unsigned max_ctxs;
125 struct timer_list packet_timeout;
126 unsigned stat_irq_thresh;
127 struct dma_pool *req_pool;
128};
129
130/* Algorithm type mask. */
131#define SPACC_CRYPTO_ALG_MASK 0x7
132
133/* SPACC definition of a crypto algorithm. */
134struct spacc_alg {
135 unsigned long ctrl_default;
136 unsigned long type;
137 struct crypto_alg alg;
138 struct spacc_engine *engine;
139 struct list_head entry;
140 int key_offs;
141 int iv_offs;
142};
143
144/* Generic context structure for any algorithm type. */
145struct spacc_generic_ctx {
146 struct spacc_engine *engine;
147 int flags;
148 int key_offs;
149 int iv_offs;
150};
151
152/* Block cipher context. */
153struct spacc_ablk_ctx {
154 struct spacc_generic_ctx generic;
155 u8 key[AES_MAX_KEY_SIZE];
156 u8 key_len;
157 /*
158 * The fallback cipher. If the operation can't be done in hardware,
159 * fallback to a software version.
160 */
161 struct crypto_sync_skcipher *sw_cipher;
162};
163
164/* AEAD cipher context. */
165struct spacc_aead_ctx {
166 struct spacc_generic_ctx generic;
167 u8 cipher_key[AES_MAX_KEY_SIZE];
168 u8 hash_ctx[SPACC_CRYPTO_IPSEC_HASH_PG_SZ];
169 u8 cipher_key_len;
170 u8 hash_key_len;
171 struct crypto_aead *sw_cipher;
172};
173
174static int spacc_ablk_submit(struct spacc_req *req);
175
176static inline struct spacc_alg *to_spacc_alg(struct crypto_alg *alg)
177{
178 return alg ? container_of(alg, struct spacc_alg, alg) : NULL;
179}
180
181static inline struct spacc_aead *to_spacc_aead(struct aead_alg *alg)
182{
183 return container_of(alg, struct spacc_aead, alg);
184}
185
186static inline int spacc_fifo_cmd_full(struct spacc_engine *engine)
187{
188 u32 fifo_stat = readl(engine->regs + SPA_FIFO_STAT_REG_OFFSET);
189
190 return fifo_stat & SPA_FIFO_CMD_FULL;
191}
192
193/*
194 * Given a cipher context, and a context number, get the base address of the
195 * context page.
196 *
197 * Returns the address of the context page where the key/context may
198 * be written.
199 */
200static inline void __iomem *spacc_ctx_page_addr(struct spacc_generic_ctx *ctx,
201 unsigned indx,
202 bool is_cipher_ctx)
203{
204 return is_cipher_ctx ? ctx->engine->cipher_ctx_base +
205 (indx * ctx->engine->cipher_pg_sz) :
206 ctx->engine->hash_key_base + (indx * ctx->engine->hash_pg_sz);
207}
208
209/* The context pages can only be written with 32-bit accesses. */
210static inline void memcpy_toio32(u32 __iomem *dst, const void *src,
211 unsigned count)
212{
213 const u32 *src32 = (const u32 *) src;
214
215 while (count--)
216 writel(*src32++, dst++);
217}
218
219static void spacc_cipher_write_ctx(struct spacc_generic_ctx *ctx,
220 void __iomem *page_addr, const u8 *key,
221 size_t key_len, const u8 *iv, size_t iv_len)
222{
223 void __iomem *key_ptr = page_addr + ctx->key_offs;
224 void __iomem *iv_ptr = page_addr + ctx->iv_offs;
225
226 memcpy_toio32(key_ptr, key, key_len / 4);
227 memcpy_toio32(iv_ptr, iv, iv_len / 4);
228}
229
230/*
231 * Load a context into the engines context memory.
232 *
233 * Returns the index of the context page where the context was loaded.
234 */
235static unsigned spacc_load_ctx(struct spacc_generic_ctx *ctx,
236 const u8 *ciph_key, size_t ciph_len,
237 const u8 *iv, size_t ivlen, const u8 *hash_key,
238 size_t hash_len)
239{
240 unsigned indx = ctx->engine->next_ctx++;
241 void __iomem *ciph_page_addr, *hash_page_addr;
242
243 ciph_page_addr = spacc_ctx_page_addr(ctx, indx, 1);
244 hash_page_addr = spacc_ctx_page_addr(ctx, indx, 0);
245
246 ctx->engine->next_ctx &= ctx->engine->fifo_sz - 1;
247 spacc_cipher_write_ctx(ctx, ciph_page_addr, ciph_key, ciph_len, iv,
248 ivlen);
249 writel(ciph_len | (indx << SPA_KEY_SZ_CTX_INDEX_OFFSET) |
250 (1 << SPA_KEY_SZ_CIPHER_OFFSET),
251 ctx->engine->regs + SPA_KEY_SZ_REG_OFFSET);
252
253 if (hash_key) {
254 memcpy_toio32(hash_page_addr, hash_key, hash_len / 4);
255 writel(hash_len | (indx << SPA_KEY_SZ_CTX_INDEX_OFFSET),
256 ctx->engine->regs + SPA_KEY_SZ_REG_OFFSET);
257 }
258
259 return indx;
260}
261
262static inline void ddt_set(struct spacc_ddt *ddt, dma_addr_t phys, size_t len)
263{
264 ddt->p = phys;
265 ddt->len = len;
266}
267
268/*
269 * Take a crypto request and scatterlists for the data and turn them into DDTs
270 * for passing to the crypto engines. This also DMA maps the data so that the
271 * crypto engines can DMA to/from them.
272 */
273static struct spacc_ddt *spacc_sg_to_ddt(struct spacc_engine *engine,
274 struct scatterlist *payload,
275 unsigned nbytes,
276 enum dma_data_direction dir,
277 dma_addr_t *ddt_phys)
278{
279 unsigned mapped_ents;
280 struct scatterlist *cur;
281 struct spacc_ddt *ddt;
282 int i;
283 int nents;
284
285 nents = sg_nents_for_len(payload, nbytes);
286 if (nents < 0) {
287 dev_err(engine->dev, "Invalid numbers of SG.\n");
288 return NULL;
289 }
290 mapped_ents = dma_map_sg(engine->dev, payload, nents, dir);
291
292 if (mapped_ents + 1 > MAX_DDT_LEN)
293 goto out;
294
295 ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, ddt_phys);
296 if (!ddt)
297 goto out;
298
299 for_each_sg(payload, cur, mapped_ents, i)
300 ddt_set(&ddt[i], sg_dma_address(cur), sg_dma_len(cur));
301 ddt_set(&ddt[mapped_ents], 0, 0);
302
303 return ddt;
304
305out:
306 dma_unmap_sg(engine->dev, payload, nents, dir);
307 return NULL;
308}
309
310static int spacc_aead_make_ddts(struct aead_request *areq)
311{
312 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
313 struct spacc_req *req = aead_request_ctx(areq);
314 struct spacc_engine *engine = req->engine;
315 struct spacc_ddt *src_ddt, *dst_ddt;
316 unsigned total;
317 int src_nents, dst_nents;
318 struct scatterlist *cur;
319 int i, dst_ents, src_ents;
320
321 total = areq->assoclen + areq->cryptlen;
322 if (req->is_encrypt)
323 total += crypto_aead_authsize(aead);
324
325 src_nents = sg_nents_for_len(areq->src, total);
326 if (src_nents < 0) {
327 dev_err(engine->dev, "Invalid numbers of src SG.\n");
328 return src_nents;
329 }
330 if (src_nents + 1 > MAX_DDT_LEN)
331 return -E2BIG;
332
333 dst_nents = 0;
334 if (areq->src != areq->dst) {
335 dst_nents = sg_nents_for_len(areq->dst, total);
336 if (dst_nents < 0) {
337 dev_err(engine->dev, "Invalid numbers of dst SG.\n");
338 return dst_nents;
339 }
340 if (src_nents + 1 > MAX_DDT_LEN)
341 return -E2BIG;
342 }
343
344 src_ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, &req->src_addr);
345 if (!src_ddt)
346 goto err;
347
348 dst_ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, &req->dst_addr);
349 if (!dst_ddt)
350 goto err_free_src;
351
352 req->src_ddt = src_ddt;
353 req->dst_ddt = dst_ddt;
354
355 if (dst_nents) {
356 src_ents = dma_map_sg(engine->dev, areq->src, src_nents,
357 DMA_TO_DEVICE);
358 if (!src_ents)
359 goto err_free_dst;
360
361 dst_ents = dma_map_sg(engine->dev, areq->dst, dst_nents,
362 DMA_FROM_DEVICE);
363
364 if (!dst_ents) {
365 dma_unmap_sg(engine->dev, areq->src, src_nents,
366 DMA_TO_DEVICE);
367 goto err_free_dst;
368 }
369 } else {
370 src_ents = dma_map_sg(engine->dev, areq->src, src_nents,
371 DMA_BIDIRECTIONAL);
372 if (!src_ents)
373 goto err_free_dst;
374 dst_ents = src_ents;
375 }
376
377 /*
378 * Now map in the payload for the source and destination and terminate
379 * with the NULL pointers.
380 */
381 for_each_sg(areq->src, cur, src_ents, i)
382 ddt_set(src_ddt++, sg_dma_address(cur), sg_dma_len(cur));
383
384 /* For decryption we need to skip the associated data. */
385 total = req->is_encrypt ? 0 : areq->assoclen;
386 for_each_sg(areq->dst, cur, dst_ents, i) {
387 unsigned len = sg_dma_len(cur);
388
389 if (len <= total) {
390 total -= len;
391 continue;
392 }
393
394 ddt_set(dst_ddt++, sg_dma_address(cur) + total, len - total);
395 }
396
397 ddt_set(src_ddt, 0, 0);
398 ddt_set(dst_ddt, 0, 0);
399
400 return 0;
401
402err_free_dst:
403 dma_pool_free(engine->req_pool, dst_ddt, req->dst_addr);
404err_free_src:
405 dma_pool_free(engine->req_pool, src_ddt, req->src_addr);
406err:
407 return -ENOMEM;
408}
409
410static void spacc_aead_free_ddts(struct spacc_req *req)
411{
412 struct aead_request *areq = container_of(req->req, struct aead_request,
413 base);
414 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
415 unsigned total = areq->assoclen + areq->cryptlen +
416 (req->is_encrypt ? crypto_aead_authsize(aead) : 0);
417 struct spacc_aead_ctx *aead_ctx = crypto_aead_ctx(aead);
418 struct spacc_engine *engine = aead_ctx->generic.engine;
419 int nents = sg_nents_for_len(areq->src, total);
420
421 /* sg_nents_for_len should not fail since it works when mapping sg */
422 if (unlikely(nents < 0)) {
423 dev_err(engine->dev, "Invalid numbers of src SG.\n");
424 return;
425 }
426
427 if (areq->src != areq->dst) {
428 dma_unmap_sg(engine->dev, areq->src, nents, DMA_TO_DEVICE);
429 nents = sg_nents_for_len(areq->dst, total);
430 if (unlikely(nents < 0)) {
431 dev_err(engine->dev, "Invalid numbers of dst SG.\n");
432 return;
433 }
434 dma_unmap_sg(engine->dev, areq->dst, nents, DMA_FROM_DEVICE);
435 } else
436 dma_unmap_sg(engine->dev, areq->src, nents, DMA_BIDIRECTIONAL);
437
438 dma_pool_free(engine->req_pool, req->src_ddt, req->src_addr);
439 dma_pool_free(engine->req_pool, req->dst_ddt, req->dst_addr);
440}
441
442static void spacc_free_ddt(struct spacc_req *req, struct spacc_ddt *ddt,
443 dma_addr_t ddt_addr, struct scatterlist *payload,
444 unsigned nbytes, enum dma_data_direction dir)
445{
446 int nents = sg_nents_for_len(payload, nbytes);
447
448 if (nents < 0) {
449 dev_err(req->engine->dev, "Invalid numbers of SG.\n");
450 return;
451 }
452
453 dma_unmap_sg(req->engine->dev, payload, nents, dir);
454 dma_pool_free(req->engine->req_pool, ddt, ddt_addr);
455}
456
457static int spacc_aead_setkey(struct crypto_aead *tfm, const u8 *key,
458 unsigned int keylen)
459{
460 struct spacc_aead_ctx *ctx = crypto_aead_ctx(tfm);
461 struct crypto_authenc_keys keys;
462 int err;
463
464 crypto_aead_clear_flags(ctx->sw_cipher, CRYPTO_TFM_REQ_MASK);
465 crypto_aead_set_flags(ctx->sw_cipher, crypto_aead_get_flags(tfm) &
466 CRYPTO_TFM_REQ_MASK);
467 err = crypto_aead_setkey(ctx->sw_cipher, key, keylen);
468 crypto_aead_clear_flags(tfm, CRYPTO_TFM_RES_MASK);
469 crypto_aead_set_flags(tfm, crypto_aead_get_flags(ctx->sw_cipher) &
470 CRYPTO_TFM_RES_MASK);
471 if (err)
472 return err;
473
474 if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
475 goto badkey;
476
477 if (keys.enckeylen > AES_MAX_KEY_SIZE)
478 goto badkey;
479
480 if (keys.authkeylen > sizeof(ctx->hash_ctx))
481 goto badkey;
482
483 memcpy(ctx->cipher_key, keys.enckey, keys.enckeylen);
484 ctx->cipher_key_len = keys.enckeylen;
485
486 memcpy(ctx->hash_ctx, keys.authkey, keys.authkeylen);
487 ctx->hash_key_len = keys.authkeylen;
488
489 memzero_explicit(&keys, sizeof(keys));
490 return 0;
491
492badkey:
493 crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
494 memzero_explicit(&keys, sizeof(keys));
495 return -EINVAL;
496}
497
498static int spacc_aead_setauthsize(struct crypto_aead *tfm,
499 unsigned int authsize)
500{
501 struct spacc_aead_ctx *ctx = crypto_tfm_ctx(crypto_aead_tfm(tfm));
502
503 return crypto_aead_setauthsize(ctx->sw_cipher, authsize);
504}
505
506/*
507 * Check if an AEAD request requires a fallback operation. Some requests can't
508 * be completed in hardware because the hardware may not support certain key
509 * sizes. In these cases we need to complete the request in software.
510 */
511static int spacc_aead_need_fallback(struct aead_request *aead_req)
512{
513 struct crypto_aead *aead = crypto_aead_reqtfm(aead_req);
514 struct aead_alg *alg = crypto_aead_alg(aead);
515 struct spacc_aead *spacc_alg = to_spacc_aead(alg);
516 struct spacc_aead_ctx *ctx = crypto_aead_ctx(aead);
517
518 /*
519 * If we have a non-supported key-length, then we need to do a
520 * software fallback.
521 */
522 if ((spacc_alg->ctrl_default & SPACC_CRYPTO_ALG_MASK) ==
523 SPA_CTRL_CIPH_ALG_AES &&
524 ctx->cipher_key_len != AES_KEYSIZE_128 &&
525 ctx->cipher_key_len != AES_KEYSIZE_256)
526 return 1;
527
528 return 0;
529}
530
531static int spacc_aead_do_fallback(struct aead_request *req, unsigned alg_type,
532 bool is_encrypt)
533{
534 struct crypto_tfm *old_tfm = crypto_aead_tfm(crypto_aead_reqtfm(req));
535 struct spacc_aead_ctx *ctx = crypto_tfm_ctx(old_tfm);
536 struct aead_request *subreq = aead_request_ctx(req);
537
538 aead_request_set_tfm(subreq, ctx->sw_cipher);
539 aead_request_set_callback(subreq, req->base.flags,
540 req->base.complete, req->base.data);
541 aead_request_set_crypt(subreq, req->src, req->dst, req->cryptlen,
542 req->iv);
543 aead_request_set_ad(subreq, req->assoclen);
544
545 return is_encrypt ? crypto_aead_encrypt(subreq) :
546 crypto_aead_decrypt(subreq);
547}
548
549static void spacc_aead_complete(struct spacc_req *req)
550{
551 spacc_aead_free_ddts(req);
552 req->req->complete(req->req, req->result);
553}
554
555static int spacc_aead_submit(struct spacc_req *req)
556{
557 struct aead_request *aead_req =
558 container_of(req->req, struct aead_request, base);
559 struct crypto_aead *aead = crypto_aead_reqtfm(aead_req);
560 unsigned int authsize = crypto_aead_authsize(aead);
561 struct spacc_aead_ctx *ctx = crypto_aead_ctx(aead);
562 struct aead_alg *alg = crypto_aead_alg(aead);
563 struct spacc_aead *spacc_alg = to_spacc_aead(alg);
564 struct spacc_engine *engine = ctx->generic.engine;
565 u32 ctrl, proc_len, assoc_len;
566
567 req->result = -EINPROGRESS;
568 req->ctx_id = spacc_load_ctx(&ctx->generic, ctx->cipher_key,
569 ctx->cipher_key_len, aead_req->iv, crypto_aead_ivsize(aead),
570 ctx->hash_ctx, ctx->hash_key_len);
571
572 /* Set the source and destination DDT pointers. */
573 writel(req->src_addr, engine->regs + SPA_SRC_PTR_REG_OFFSET);
574 writel(req->dst_addr, engine->regs + SPA_DST_PTR_REG_OFFSET);
575 writel(0, engine->regs + SPA_OFFSET_REG_OFFSET);
576
577 assoc_len = aead_req->assoclen;
578 proc_len = aead_req->cryptlen + assoc_len;
579
580 /*
581 * If we are decrypting, we need to take the length of the ICV out of
582 * the processing length.
583 */
584 if (!req->is_encrypt)
585 proc_len -= authsize;
586
587 writel(proc_len, engine->regs + SPA_PROC_LEN_REG_OFFSET);
588 writel(assoc_len, engine->regs + SPA_AAD_LEN_REG_OFFSET);
589 writel(authsize, engine->regs + SPA_ICV_LEN_REG_OFFSET);
590 writel(0, engine->regs + SPA_ICV_OFFSET_REG_OFFSET);
591 writel(0, engine->regs + SPA_AUX_INFO_REG_OFFSET);
592
593 ctrl = spacc_alg->ctrl_default | (req->ctx_id << SPA_CTRL_CTX_IDX) |
594 (1 << SPA_CTRL_ICV_APPEND);
595 if (req->is_encrypt)
596 ctrl |= (1 << SPA_CTRL_ENCRYPT_IDX) | (1 << SPA_CTRL_AAD_COPY);
597 else
598 ctrl |= (1 << SPA_CTRL_KEY_EXP);
599
600 mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT);
601
602 writel(ctrl, engine->regs + SPA_CTRL_REG_OFFSET);
603
604 return -EINPROGRESS;
605}
606
607static int spacc_req_submit(struct spacc_req *req);
608
609static void spacc_push(struct spacc_engine *engine)
610{
611 struct spacc_req *req;
612
613 while (!list_empty(&engine->pending) &&
614 engine->in_flight + 1 <= engine->fifo_sz) {
615
616 ++engine->in_flight;
617 req = list_first_entry(&engine->pending, struct spacc_req,
618 list);
619 list_move_tail(&req->list, &engine->in_progress);
620
621 req->result = spacc_req_submit(req);
622 }
623}
624
625/*
626 * Setup an AEAD request for processing. This will configure the engine, load
627 * the context and then start the packet processing.
628 */
629static int spacc_aead_setup(struct aead_request *req,
630 unsigned alg_type, bool is_encrypt)
631{
632 struct crypto_aead *aead = crypto_aead_reqtfm(req);
633 struct aead_alg *alg = crypto_aead_alg(aead);
634 struct spacc_engine *engine = to_spacc_aead(alg)->engine;
635 struct spacc_req *dev_req = aead_request_ctx(req);
636 int err;
637 unsigned long flags;
638
639 dev_req->req = &req->base;
640 dev_req->is_encrypt = is_encrypt;
641 dev_req->result = -EBUSY;
642 dev_req->engine = engine;
643 dev_req->complete = spacc_aead_complete;
644
645 if (unlikely(spacc_aead_need_fallback(req) ||
646 ((err = spacc_aead_make_ddts(req)) == -E2BIG)))
647 return spacc_aead_do_fallback(req, alg_type, is_encrypt);
648
649 if (err)
650 goto out;
651
652 err = -EINPROGRESS;
653 spin_lock_irqsave(&engine->hw_lock, flags);
654 if (unlikely(spacc_fifo_cmd_full(engine)) ||
655 engine->in_flight + 1 > engine->fifo_sz) {
656 if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
657 err = -EBUSY;
658 spin_unlock_irqrestore(&engine->hw_lock, flags);
659 goto out_free_ddts;
660 }
661 list_add_tail(&dev_req->list, &engine->pending);
662 } else {
663 list_add_tail(&dev_req->list, &engine->pending);
664 spacc_push(engine);
665 }
666 spin_unlock_irqrestore(&engine->hw_lock, flags);
667
668 goto out;
669
670out_free_ddts:
671 spacc_aead_free_ddts(dev_req);
672out:
673 return err;
674}
675
676static int spacc_aead_encrypt(struct aead_request *req)
677{
678 struct crypto_aead *aead = crypto_aead_reqtfm(req);
679 struct spacc_aead *alg = to_spacc_aead(crypto_aead_alg(aead));
680
681 return spacc_aead_setup(req, alg->type, 1);
682}
683
684static int spacc_aead_decrypt(struct aead_request *req)
685{
686 struct crypto_aead *aead = crypto_aead_reqtfm(req);
687 struct spacc_aead *alg = to_spacc_aead(crypto_aead_alg(aead));
688
689 return spacc_aead_setup(req, alg->type, 0);
690}
691
692/*
693 * Initialise a new AEAD context. This is responsible for allocating the
694 * fallback cipher and initialising the context.
695 */
696static int spacc_aead_cra_init(struct crypto_aead *tfm)
697{
698 struct spacc_aead_ctx *ctx = crypto_aead_ctx(tfm);
699 struct aead_alg *alg = crypto_aead_alg(tfm);
700 struct spacc_aead *spacc_alg = to_spacc_aead(alg);
701 struct spacc_engine *engine = spacc_alg->engine;
702
703 ctx->generic.flags = spacc_alg->type;
704 ctx->generic.engine = engine;
705 ctx->sw_cipher = crypto_alloc_aead(alg->base.cra_name, 0,
706 CRYPTO_ALG_NEED_FALLBACK);
707 if (IS_ERR(ctx->sw_cipher))
708 return PTR_ERR(ctx->sw_cipher);
709 ctx->generic.key_offs = spacc_alg->key_offs;
710 ctx->generic.iv_offs = spacc_alg->iv_offs;
711
712 crypto_aead_set_reqsize(
713 tfm,
714 max(sizeof(struct spacc_req),
715 sizeof(struct aead_request) +
716 crypto_aead_reqsize(ctx->sw_cipher)));
717
718 return 0;
719}
720
721/*
722 * Destructor for an AEAD context. This is called when the transform is freed
723 * and must free the fallback cipher.
724 */
725static void spacc_aead_cra_exit(struct crypto_aead *tfm)
726{
727 struct spacc_aead_ctx *ctx = crypto_aead_ctx(tfm);
728
729 crypto_free_aead(ctx->sw_cipher);
730}
731
732/*
733 * Set the DES key for a block cipher transform. This also performs weak key
734 * checking if the transform has requested it.
735 */
736static int spacc_des_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
737 unsigned int len)
738{
739 struct spacc_ablk_ctx *ctx = crypto_ablkcipher_ctx(cipher);
740 int err;
741
742 err = verify_ablkcipher_des_key(cipher, key);
743 if (err)
744 return err;
745
746 memcpy(ctx->key, key, len);
747 ctx->key_len = len;
748
749 return 0;
750}
751
752/*
753 * Set the 3DES key for a block cipher transform. This also performs weak key
754 * checking if the transform has requested it.
755 */
756static int spacc_des3_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
757 unsigned int len)
758{
759 struct spacc_ablk_ctx *ctx = crypto_ablkcipher_ctx(cipher);
760 int err;
761
762 err = verify_ablkcipher_des3_key(cipher, key);
763 if (err)
764 return err;
765
766 memcpy(ctx->key, key, len);
767 ctx->key_len = len;
768
769 return 0;
770}
771
772/*
773 * Set the key for an AES block cipher. Some key lengths are not supported in
774 * hardware so this must also check whether a fallback is needed.
775 */
776static int spacc_aes_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
777 unsigned int len)
778{
779 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
780 struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm);
781 int err = 0;
782
783 if (len > AES_MAX_KEY_SIZE) {
784 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
785 return -EINVAL;
786 }
787
788 /*
789 * IPSec engine only supports 128 and 256 bit AES keys. If we get a
790 * request for any other size (192 bits) then we need to do a software
791 * fallback.
792 */
793 if (len != AES_KEYSIZE_128 && len != AES_KEYSIZE_256) {
794 if (!ctx->sw_cipher)
795 return -EINVAL;
796
797 /*
798 * Set the fallback transform to use the same request flags as
799 * the hardware transform.
800 */
801 crypto_sync_skcipher_clear_flags(ctx->sw_cipher,
802 CRYPTO_TFM_REQ_MASK);
803 crypto_sync_skcipher_set_flags(ctx->sw_cipher,
804 cipher->base.crt_flags &
805 CRYPTO_TFM_REQ_MASK);
806
807 err = crypto_sync_skcipher_setkey(ctx->sw_cipher, key, len);
808
809 tfm->crt_flags &= ~CRYPTO_TFM_RES_MASK;
810 tfm->crt_flags |=
811 crypto_sync_skcipher_get_flags(ctx->sw_cipher) &
812 CRYPTO_TFM_RES_MASK;
813
814 if (err)
815 goto sw_setkey_failed;
816 }
817
818 memcpy(ctx->key, key, len);
819 ctx->key_len = len;
820
821sw_setkey_failed:
822 return err;
823}
824
825static int spacc_kasumi_f8_setkey(struct crypto_ablkcipher *cipher,
826 const u8 *key, unsigned int len)
827{
828 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
829 struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm);
830 int err = 0;
831
832 if (len > AES_MAX_KEY_SIZE) {
833 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
834 err = -EINVAL;
835 goto out;
836 }
837
838 memcpy(ctx->key, key, len);
839 ctx->key_len = len;
840
841out:
842 return err;
843}
844
845static int spacc_ablk_need_fallback(struct spacc_req *req)
846{
847 struct spacc_ablk_ctx *ctx;
848 struct crypto_tfm *tfm = req->req->tfm;
849 struct crypto_alg *alg = req->req->tfm->__crt_alg;
850 struct spacc_alg *spacc_alg = to_spacc_alg(alg);
851
852 ctx = crypto_tfm_ctx(tfm);
853
854 return (spacc_alg->ctrl_default & SPACC_CRYPTO_ALG_MASK) ==
855 SPA_CTRL_CIPH_ALG_AES &&
856 ctx->key_len != AES_KEYSIZE_128 &&
857 ctx->key_len != AES_KEYSIZE_256;
858}
859
860static void spacc_ablk_complete(struct spacc_req *req)
861{
862 struct ablkcipher_request *ablk_req = ablkcipher_request_cast(req->req);
863
864 if (ablk_req->src != ablk_req->dst) {
865 spacc_free_ddt(req, req->src_ddt, req->src_addr, ablk_req->src,
866 ablk_req->nbytes, DMA_TO_DEVICE);
867 spacc_free_ddt(req, req->dst_ddt, req->dst_addr, ablk_req->dst,
868 ablk_req->nbytes, DMA_FROM_DEVICE);
869 } else
870 spacc_free_ddt(req, req->dst_ddt, req->dst_addr, ablk_req->dst,
871 ablk_req->nbytes, DMA_BIDIRECTIONAL);
872
873 req->req->complete(req->req, req->result);
874}
875
876static int spacc_ablk_submit(struct spacc_req *req)
877{
878 struct crypto_tfm *tfm = req->req->tfm;
879 struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm);
880 struct ablkcipher_request *ablk_req = ablkcipher_request_cast(req->req);
881 struct crypto_alg *alg = req->req->tfm->__crt_alg;
882 struct spacc_alg *spacc_alg = to_spacc_alg(alg);
883 struct spacc_engine *engine = ctx->generic.engine;
884 u32 ctrl;
885
886 req->ctx_id = spacc_load_ctx(&ctx->generic, ctx->key,
887 ctx->key_len, ablk_req->info, alg->cra_ablkcipher.ivsize,
888 NULL, 0);
889
890 writel(req->src_addr, engine->regs + SPA_SRC_PTR_REG_OFFSET);
891 writel(req->dst_addr, engine->regs + SPA_DST_PTR_REG_OFFSET);
892 writel(0, engine->regs + SPA_OFFSET_REG_OFFSET);
893
894 writel(ablk_req->nbytes, engine->regs + SPA_PROC_LEN_REG_OFFSET);
895 writel(0, engine->regs + SPA_ICV_OFFSET_REG_OFFSET);
896 writel(0, engine->regs + SPA_AUX_INFO_REG_OFFSET);
897 writel(0, engine->regs + SPA_AAD_LEN_REG_OFFSET);
898
899 ctrl = spacc_alg->ctrl_default | (req->ctx_id << SPA_CTRL_CTX_IDX) |
900 (req->is_encrypt ? (1 << SPA_CTRL_ENCRYPT_IDX) :
901 (1 << SPA_CTRL_KEY_EXP));
902
903 mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT);
904
905 writel(ctrl, engine->regs + SPA_CTRL_REG_OFFSET);
906
907 return -EINPROGRESS;
908}
909
910static int spacc_ablk_do_fallback(struct ablkcipher_request *req,
911 unsigned alg_type, bool is_encrypt)
912{
913 struct crypto_tfm *old_tfm =
914 crypto_ablkcipher_tfm(crypto_ablkcipher_reqtfm(req));
915 struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(old_tfm);
916 SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->sw_cipher);
917 int err;
918
919 /*
920 * Change the request to use the software fallback transform, and once
921 * the ciphering has completed, put the old transform back into the
922 * request.
923 */
924 skcipher_request_set_sync_tfm(subreq, ctx->sw_cipher);
925 skcipher_request_set_callback(subreq, req->base.flags, NULL, NULL);
926 skcipher_request_set_crypt(subreq, req->src, req->dst,
927 req->nbytes, req->info);
928 err = is_encrypt ? crypto_skcipher_encrypt(subreq) :
929 crypto_skcipher_decrypt(subreq);
930 skcipher_request_zero(subreq);
931
932 return err;
933}
934
935static int spacc_ablk_setup(struct ablkcipher_request *req, unsigned alg_type,
936 bool is_encrypt)
937{
938 struct crypto_alg *alg = req->base.tfm->__crt_alg;
939 struct spacc_engine *engine = to_spacc_alg(alg)->engine;
940 struct spacc_req *dev_req = ablkcipher_request_ctx(req);
941 unsigned long flags;
942 int err = -ENOMEM;
943
944 dev_req->req = &req->base;
945 dev_req->is_encrypt = is_encrypt;
946 dev_req->engine = engine;
947 dev_req->complete = spacc_ablk_complete;
948 dev_req->result = -EINPROGRESS;
949
950 if (unlikely(spacc_ablk_need_fallback(dev_req)))
951 return spacc_ablk_do_fallback(req, alg_type, is_encrypt);
952
953 /*
954 * Create the DDT's for the engine. If we share the same source and
955 * destination then we can optimize by reusing the DDT's.
956 */
957 if (req->src != req->dst) {
958 dev_req->src_ddt = spacc_sg_to_ddt(engine, req->src,
959 req->nbytes, DMA_TO_DEVICE, &dev_req->src_addr);
960 if (!dev_req->src_ddt)
961 goto out;
962
963 dev_req->dst_ddt = spacc_sg_to_ddt(engine, req->dst,
964 req->nbytes, DMA_FROM_DEVICE, &dev_req->dst_addr);
965 if (!dev_req->dst_ddt)
966 goto out_free_src;
967 } else {
968 dev_req->dst_ddt = spacc_sg_to_ddt(engine, req->dst,
969 req->nbytes, DMA_BIDIRECTIONAL, &dev_req->dst_addr);
970 if (!dev_req->dst_ddt)
971 goto out;
972
973 dev_req->src_ddt = NULL;
974 dev_req->src_addr = dev_req->dst_addr;
975 }
976
977 err = -EINPROGRESS;
978 spin_lock_irqsave(&engine->hw_lock, flags);
979 /*
980 * Check if the engine will accept the operation now. If it won't then
981 * we either stick it on the end of a pending list if we can backlog,
982 * or bailout with an error if not.
983 */
984 if (unlikely(spacc_fifo_cmd_full(engine)) ||
985 engine->in_flight + 1 > engine->fifo_sz) {
986 if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
987 err = -EBUSY;
988 spin_unlock_irqrestore(&engine->hw_lock, flags);
989 goto out_free_ddts;
990 }
991 list_add_tail(&dev_req->list, &engine->pending);
992 } else {
993 list_add_tail(&dev_req->list, &engine->pending);
994 spacc_push(engine);
995 }
996 spin_unlock_irqrestore(&engine->hw_lock, flags);
997
998 goto out;
999
1000out_free_ddts:
1001 spacc_free_ddt(dev_req, dev_req->dst_ddt, dev_req->dst_addr, req->dst,
1002 req->nbytes, req->src == req->dst ?
1003 DMA_BIDIRECTIONAL : DMA_FROM_DEVICE);
1004out_free_src:
1005 if (req->src != req->dst)
1006 spacc_free_ddt(dev_req, dev_req->src_ddt, dev_req->src_addr,
1007 req->src, req->nbytes, DMA_TO_DEVICE);
1008out:
1009 return err;
1010}
1011
1012static int spacc_ablk_cra_init(struct crypto_tfm *tfm)
1013{
1014 struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm);
1015 struct crypto_alg *alg = tfm->__crt_alg;
1016 struct spacc_alg *spacc_alg = to_spacc_alg(alg);
1017 struct spacc_engine *engine = spacc_alg->engine;
1018
1019 ctx->generic.flags = spacc_alg->type;
1020 ctx->generic.engine = engine;
1021 if (alg->cra_flags & CRYPTO_ALG_NEED_FALLBACK) {
1022 ctx->sw_cipher = crypto_alloc_sync_skcipher(
1023 alg->cra_name, 0, CRYPTO_ALG_NEED_FALLBACK);
1024 if (IS_ERR(ctx->sw_cipher)) {
1025 dev_warn(engine->dev, "failed to allocate fallback for %s\n",
1026 alg->cra_name);
1027 return PTR_ERR(ctx->sw_cipher);
1028 }
1029 }
1030 ctx->generic.key_offs = spacc_alg->key_offs;
1031 ctx->generic.iv_offs = spacc_alg->iv_offs;
1032
1033 tfm->crt_ablkcipher.reqsize = sizeof(struct spacc_req);
1034
1035 return 0;
1036}
1037
1038static void spacc_ablk_cra_exit(struct crypto_tfm *tfm)
1039{
1040 struct spacc_ablk_ctx *ctx = crypto_tfm_ctx(tfm);
1041
1042 crypto_free_sync_skcipher(ctx->sw_cipher);
1043}
1044
1045static int spacc_ablk_encrypt(struct ablkcipher_request *req)
1046{
1047 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(req);
1048 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
1049 struct spacc_alg *alg = to_spacc_alg(tfm->__crt_alg);
1050
1051 return spacc_ablk_setup(req, alg->type, 1);
1052}
1053
1054static int spacc_ablk_decrypt(struct ablkcipher_request *req)
1055{
1056 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(req);
1057 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
1058 struct spacc_alg *alg = to_spacc_alg(tfm->__crt_alg);
1059
1060 return spacc_ablk_setup(req, alg->type, 0);
1061}
1062
1063static inline int spacc_fifo_stat_empty(struct spacc_engine *engine)
1064{
1065 return readl(engine->regs + SPA_FIFO_STAT_REG_OFFSET) &
1066 SPA_FIFO_STAT_EMPTY;
1067}
1068
1069static void spacc_process_done(struct spacc_engine *engine)
1070{
1071 struct spacc_req *req;
1072 unsigned long flags;
1073
1074 spin_lock_irqsave(&engine->hw_lock, flags);
1075
1076 while (!spacc_fifo_stat_empty(engine)) {
1077 req = list_first_entry(&engine->in_progress, struct spacc_req,
1078 list);
1079 list_move_tail(&req->list, &engine->completed);
1080 --engine->in_flight;
1081
1082 /* POP the status register. */
1083 writel(~0, engine->regs + SPA_STAT_POP_REG_OFFSET);
1084 req->result = (readl(engine->regs + SPA_STATUS_REG_OFFSET) &
1085 SPA_STATUS_RES_CODE_MASK) >> SPA_STATUS_RES_CODE_OFFSET;
1086
1087 /*
1088 * Convert the SPAcc error status into the standard POSIX error
1089 * codes.
1090 */
1091 if (unlikely(req->result)) {
1092 switch (req->result) {
1093 case SPA_STATUS_ICV_FAIL:
1094 req->result = -EBADMSG;
1095 break;
1096
1097 case SPA_STATUS_MEMORY_ERROR:
1098 dev_warn(engine->dev,
1099 "memory error triggered\n");
1100 req->result = -EFAULT;
1101 break;
1102
1103 case SPA_STATUS_BLOCK_ERROR:
1104 dev_warn(engine->dev,
1105 "block error triggered\n");
1106 req->result = -EIO;
1107 break;
1108 }
1109 }
1110 }
1111
1112 tasklet_schedule(&engine->complete);
1113
1114 spin_unlock_irqrestore(&engine->hw_lock, flags);
1115}
1116
1117static irqreturn_t spacc_spacc_irq(int irq, void *dev)
1118{
1119 struct spacc_engine *engine = (struct spacc_engine *)dev;
1120 u32 spacc_irq_stat = readl(engine->regs + SPA_IRQ_STAT_REG_OFFSET);
1121
1122 writel(spacc_irq_stat, engine->regs + SPA_IRQ_STAT_REG_OFFSET);
1123 spacc_process_done(engine);
1124
1125 return IRQ_HANDLED;
1126}
1127
1128static void spacc_packet_timeout(struct timer_list *t)
1129{
1130 struct spacc_engine *engine = from_timer(engine, t, packet_timeout);
1131
1132 spacc_process_done(engine);
1133}
1134
1135static int spacc_req_submit(struct spacc_req *req)
1136{
1137 struct crypto_alg *alg = req->req->tfm->__crt_alg;
1138
1139 if (CRYPTO_ALG_TYPE_AEAD == (CRYPTO_ALG_TYPE_MASK & alg->cra_flags))
1140 return spacc_aead_submit(req);
1141 else
1142 return spacc_ablk_submit(req);
1143}
1144
1145static void spacc_spacc_complete(unsigned long data)
1146{
1147 struct spacc_engine *engine = (struct spacc_engine *)data;
1148 struct spacc_req *req, *tmp;
1149 unsigned long flags;
1150 LIST_HEAD(completed);
1151
1152 spin_lock_irqsave(&engine->hw_lock, flags);
1153
1154 list_splice_init(&engine->completed, &completed);
1155 spacc_push(engine);
1156 if (engine->in_flight)
1157 mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT);
1158
1159 spin_unlock_irqrestore(&engine->hw_lock, flags);
1160
1161 list_for_each_entry_safe(req, tmp, &completed, list) {
1162 list_del(&req->list);
1163 req->complete(req);
1164 }
1165}
1166
1167#ifdef CONFIG_PM
1168static int spacc_suspend(struct device *dev)
1169{
1170 struct spacc_engine *engine = dev_get_drvdata(dev);
1171
1172 /*
1173 * We only support standby mode. All we have to do is gate the clock to
1174 * the spacc. The hardware will preserve state until we turn it back
1175 * on again.
1176 */
1177 clk_disable(engine->clk);
1178
1179 return 0;
1180}
1181
1182static int spacc_resume(struct device *dev)
1183{
1184 struct spacc_engine *engine = dev_get_drvdata(dev);
1185
1186 return clk_enable(engine->clk);
1187}
1188
1189static const struct dev_pm_ops spacc_pm_ops = {
1190 .suspend = spacc_suspend,
1191 .resume = spacc_resume,
1192};
1193#endif /* CONFIG_PM */
1194
1195static inline struct spacc_engine *spacc_dev_to_engine(struct device *dev)
1196{
1197 return dev ? dev_get_drvdata(dev) : NULL;
1198}
1199
1200static ssize_t spacc_stat_irq_thresh_show(struct device *dev,
1201 struct device_attribute *attr,
1202 char *buf)
1203{
1204 struct spacc_engine *engine = spacc_dev_to_engine(dev);
1205
1206 return snprintf(buf, PAGE_SIZE, "%u\n", engine->stat_irq_thresh);
1207}
1208
1209static ssize_t spacc_stat_irq_thresh_store(struct device *dev,
1210 struct device_attribute *attr,
1211 const char *buf, size_t len)
1212{
1213 struct spacc_engine *engine = spacc_dev_to_engine(dev);
1214 unsigned long thresh;
1215
1216 if (kstrtoul(buf, 0, &thresh))
1217 return -EINVAL;
1218
1219 thresh = clamp(thresh, 1UL, engine->fifo_sz - 1);
1220
1221 engine->stat_irq_thresh = thresh;
1222 writel(engine->stat_irq_thresh << SPA_IRQ_CTRL_STAT_CNT_OFFSET,
1223 engine->regs + SPA_IRQ_CTRL_REG_OFFSET);
1224
1225 return len;
1226}
1227static DEVICE_ATTR(stat_irq_thresh, 0644, spacc_stat_irq_thresh_show,
1228 spacc_stat_irq_thresh_store);
1229
1230static struct spacc_alg ipsec_engine_algs[] = {
1231 {
1232 .ctrl_default = SPA_CTRL_CIPH_ALG_AES | SPA_CTRL_CIPH_MODE_CBC,
1233 .key_offs = 0,
1234 .iv_offs = AES_MAX_KEY_SIZE,
1235 .alg = {
1236 .cra_name = "cbc(aes)",
1237 .cra_driver_name = "cbc-aes-picoxcell",
1238 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1239 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1240 CRYPTO_ALG_KERN_DRIVER_ONLY |
1241 CRYPTO_ALG_ASYNC |
1242 CRYPTO_ALG_NEED_FALLBACK,
1243 .cra_blocksize = AES_BLOCK_SIZE,
1244 .cra_ctxsize = sizeof(struct spacc_ablk_ctx),
1245 .cra_type = &crypto_ablkcipher_type,
1246 .cra_module = THIS_MODULE,
1247 .cra_ablkcipher = {
1248 .setkey = spacc_aes_setkey,
1249 .encrypt = spacc_ablk_encrypt,
1250 .decrypt = spacc_ablk_decrypt,
1251 .min_keysize = AES_MIN_KEY_SIZE,
1252 .max_keysize = AES_MAX_KEY_SIZE,
1253 .ivsize = AES_BLOCK_SIZE,
1254 },
1255 .cra_init = spacc_ablk_cra_init,
1256 .cra_exit = spacc_ablk_cra_exit,
1257 },
1258 },
1259 {
1260 .key_offs = 0,
1261 .iv_offs = AES_MAX_KEY_SIZE,
1262 .ctrl_default = SPA_CTRL_CIPH_ALG_AES | SPA_CTRL_CIPH_MODE_ECB,
1263 .alg = {
1264 .cra_name = "ecb(aes)",
1265 .cra_driver_name = "ecb-aes-picoxcell",
1266 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1267 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1268 CRYPTO_ALG_KERN_DRIVER_ONLY |
1269 CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
1270 .cra_blocksize = AES_BLOCK_SIZE,
1271 .cra_ctxsize = sizeof(struct spacc_ablk_ctx),
1272 .cra_type = &crypto_ablkcipher_type,
1273 .cra_module = THIS_MODULE,
1274 .cra_ablkcipher = {
1275 .setkey = spacc_aes_setkey,
1276 .encrypt = spacc_ablk_encrypt,
1277 .decrypt = spacc_ablk_decrypt,
1278 .min_keysize = AES_MIN_KEY_SIZE,
1279 .max_keysize = AES_MAX_KEY_SIZE,
1280 },
1281 .cra_init = spacc_ablk_cra_init,
1282 .cra_exit = spacc_ablk_cra_exit,
1283 },
1284 },
1285 {
1286 .key_offs = DES_BLOCK_SIZE,
1287 .iv_offs = 0,
1288 .ctrl_default = SPA_CTRL_CIPH_ALG_DES | SPA_CTRL_CIPH_MODE_CBC,
1289 .alg = {
1290 .cra_name = "cbc(des)",
1291 .cra_driver_name = "cbc-des-picoxcell",
1292 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1293 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1294 CRYPTO_ALG_ASYNC |
1295 CRYPTO_ALG_KERN_DRIVER_ONLY,
1296 .cra_blocksize = DES_BLOCK_SIZE,
1297 .cra_ctxsize = sizeof(struct spacc_ablk_ctx),
1298 .cra_type = &crypto_ablkcipher_type,
1299 .cra_module = THIS_MODULE,
1300 .cra_ablkcipher = {
1301 .setkey = spacc_des_setkey,
1302 .encrypt = spacc_ablk_encrypt,
1303 .decrypt = spacc_ablk_decrypt,
1304 .min_keysize = DES_KEY_SIZE,
1305 .max_keysize = DES_KEY_SIZE,
1306 .ivsize = DES_BLOCK_SIZE,
1307 },
1308 .cra_init = spacc_ablk_cra_init,
1309 .cra_exit = spacc_ablk_cra_exit,
1310 },
1311 },
1312 {
1313 .key_offs = DES_BLOCK_SIZE,
1314 .iv_offs = 0,
1315 .ctrl_default = SPA_CTRL_CIPH_ALG_DES | SPA_CTRL_CIPH_MODE_ECB,
1316 .alg = {
1317 .cra_name = "ecb(des)",
1318 .cra_driver_name = "ecb-des-picoxcell",
1319 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1320 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1321 CRYPTO_ALG_ASYNC |
1322 CRYPTO_ALG_KERN_DRIVER_ONLY,
1323 .cra_blocksize = DES_BLOCK_SIZE,
1324 .cra_ctxsize = sizeof(struct spacc_ablk_ctx),
1325 .cra_type = &crypto_ablkcipher_type,
1326 .cra_module = THIS_MODULE,
1327 .cra_ablkcipher = {
1328 .setkey = spacc_des_setkey,
1329 .encrypt = spacc_ablk_encrypt,
1330 .decrypt = spacc_ablk_decrypt,
1331 .min_keysize = DES_KEY_SIZE,
1332 .max_keysize = DES_KEY_SIZE,
1333 },
1334 .cra_init = spacc_ablk_cra_init,
1335 .cra_exit = spacc_ablk_cra_exit,
1336 },
1337 },
1338 {
1339 .key_offs = DES_BLOCK_SIZE,
1340 .iv_offs = 0,
1341 .ctrl_default = SPA_CTRL_CIPH_ALG_DES | SPA_CTRL_CIPH_MODE_CBC,
1342 .alg = {
1343 .cra_name = "cbc(des3_ede)",
1344 .cra_driver_name = "cbc-des3-ede-picoxcell",
1345 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1346 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1347 CRYPTO_ALG_ASYNC |
1348 CRYPTO_ALG_KERN_DRIVER_ONLY,
1349 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1350 .cra_ctxsize = sizeof(struct spacc_ablk_ctx),
1351 .cra_type = &crypto_ablkcipher_type,
1352 .cra_module = THIS_MODULE,
1353 .cra_ablkcipher = {
1354 .setkey = spacc_des3_setkey,
1355 .encrypt = spacc_ablk_encrypt,
1356 .decrypt = spacc_ablk_decrypt,
1357 .min_keysize = DES3_EDE_KEY_SIZE,
1358 .max_keysize = DES3_EDE_KEY_SIZE,
1359 .ivsize = DES3_EDE_BLOCK_SIZE,
1360 },
1361 .cra_init = spacc_ablk_cra_init,
1362 .cra_exit = spacc_ablk_cra_exit,
1363 },
1364 },
1365 {
1366 .key_offs = DES_BLOCK_SIZE,
1367 .iv_offs = 0,
1368 .ctrl_default = SPA_CTRL_CIPH_ALG_DES | SPA_CTRL_CIPH_MODE_ECB,
1369 .alg = {
1370 .cra_name = "ecb(des3_ede)",
1371 .cra_driver_name = "ecb-des3-ede-picoxcell",
1372 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1373 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1374 CRYPTO_ALG_ASYNC |
1375 CRYPTO_ALG_KERN_DRIVER_ONLY,
1376 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1377 .cra_ctxsize = sizeof(struct spacc_ablk_ctx),
1378 .cra_type = &crypto_ablkcipher_type,
1379 .cra_module = THIS_MODULE,
1380 .cra_ablkcipher = {
1381 .setkey = spacc_des3_setkey,
1382 .encrypt = spacc_ablk_encrypt,
1383 .decrypt = spacc_ablk_decrypt,
1384 .min_keysize = DES3_EDE_KEY_SIZE,
1385 .max_keysize = DES3_EDE_KEY_SIZE,
1386 },
1387 .cra_init = spacc_ablk_cra_init,
1388 .cra_exit = spacc_ablk_cra_exit,
1389 },
1390 },
1391};
1392
1393static struct spacc_aead ipsec_engine_aeads[] = {
1394 {
1395 .ctrl_default = SPA_CTRL_CIPH_ALG_AES |
1396 SPA_CTRL_CIPH_MODE_CBC |
1397 SPA_CTRL_HASH_ALG_SHA |
1398 SPA_CTRL_HASH_MODE_HMAC,
1399 .key_offs = 0,
1400 .iv_offs = AES_MAX_KEY_SIZE,
1401 .alg = {
1402 .base = {
1403 .cra_name = "authenc(hmac(sha1),cbc(aes))",
1404 .cra_driver_name = "authenc-hmac-sha1-"
1405 "cbc-aes-picoxcell",
1406 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1407 .cra_flags = CRYPTO_ALG_ASYNC |
1408 CRYPTO_ALG_NEED_FALLBACK |
1409 CRYPTO_ALG_KERN_DRIVER_ONLY,
1410 .cra_blocksize = AES_BLOCK_SIZE,
1411 .cra_ctxsize = sizeof(struct spacc_aead_ctx),
1412 .cra_module = THIS_MODULE,
1413 },
1414 .setkey = spacc_aead_setkey,
1415 .setauthsize = spacc_aead_setauthsize,
1416 .encrypt = spacc_aead_encrypt,
1417 .decrypt = spacc_aead_decrypt,
1418 .ivsize = AES_BLOCK_SIZE,
1419 .maxauthsize = SHA1_DIGEST_SIZE,
1420 .init = spacc_aead_cra_init,
1421 .exit = spacc_aead_cra_exit,
1422 },
1423 },
1424 {
1425 .ctrl_default = SPA_CTRL_CIPH_ALG_AES |
1426 SPA_CTRL_CIPH_MODE_CBC |
1427 SPA_CTRL_HASH_ALG_SHA256 |
1428 SPA_CTRL_HASH_MODE_HMAC,
1429 .key_offs = 0,
1430 .iv_offs = AES_MAX_KEY_SIZE,
1431 .alg = {
1432 .base = {
1433 .cra_name = "authenc(hmac(sha256),cbc(aes))",
1434 .cra_driver_name = "authenc-hmac-sha256-"
1435 "cbc-aes-picoxcell",
1436 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1437 .cra_flags = CRYPTO_ALG_ASYNC |
1438 CRYPTO_ALG_NEED_FALLBACK |
1439 CRYPTO_ALG_KERN_DRIVER_ONLY,
1440 .cra_blocksize = AES_BLOCK_SIZE,
1441 .cra_ctxsize = sizeof(struct spacc_aead_ctx),
1442 .cra_module = THIS_MODULE,
1443 },
1444 .setkey = spacc_aead_setkey,
1445 .setauthsize = spacc_aead_setauthsize,
1446 .encrypt = spacc_aead_encrypt,
1447 .decrypt = spacc_aead_decrypt,
1448 .ivsize = AES_BLOCK_SIZE,
1449 .maxauthsize = SHA256_DIGEST_SIZE,
1450 .init = spacc_aead_cra_init,
1451 .exit = spacc_aead_cra_exit,
1452 },
1453 },
1454 {
1455 .key_offs = 0,
1456 .iv_offs = AES_MAX_KEY_SIZE,
1457 .ctrl_default = SPA_CTRL_CIPH_ALG_AES |
1458 SPA_CTRL_CIPH_MODE_CBC |
1459 SPA_CTRL_HASH_ALG_MD5 |
1460 SPA_CTRL_HASH_MODE_HMAC,
1461 .alg = {
1462 .base = {
1463 .cra_name = "authenc(hmac(md5),cbc(aes))",
1464 .cra_driver_name = "authenc-hmac-md5-"
1465 "cbc-aes-picoxcell",
1466 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1467 .cra_flags = CRYPTO_ALG_ASYNC |
1468 CRYPTO_ALG_NEED_FALLBACK |
1469 CRYPTO_ALG_KERN_DRIVER_ONLY,
1470 .cra_blocksize = AES_BLOCK_SIZE,
1471 .cra_ctxsize = sizeof(struct spacc_aead_ctx),
1472 .cra_module = THIS_MODULE,
1473 },
1474 .setkey = spacc_aead_setkey,
1475 .setauthsize = spacc_aead_setauthsize,
1476 .encrypt = spacc_aead_encrypt,
1477 .decrypt = spacc_aead_decrypt,
1478 .ivsize = AES_BLOCK_SIZE,
1479 .maxauthsize = MD5_DIGEST_SIZE,
1480 .init = spacc_aead_cra_init,
1481 .exit = spacc_aead_cra_exit,
1482 },
1483 },
1484 {
1485 .key_offs = DES_BLOCK_SIZE,
1486 .iv_offs = 0,
1487 .ctrl_default = SPA_CTRL_CIPH_ALG_DES |
1488 SPA_CTRL_CIPH_MODE_CBC |
1489 SPA_CTRL_HASH_ALG_SHA |
1490 SPA_CTRL_HASH_MODE_HMAC,
1491 .alg = {
1492 .base = {
1493 .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1494 .cra_driver_name = "authenc-hmac-sha1-"
1495 "cbc-3des-picoxcell",
1496 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1497 .cra_flags = CRYPTO_ALG_ASYNC |
1498 CRYPTO_ALG_NEED_FALLBACK |
1499 CRYPTO_ALG_KERN_DRIVER_ONLY,
1500 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1501 .cra_ctxsize = sizeof(struct spacc_aead_ctx),
1502 .cra_module = THIS_MODULE,
1503 },
1504 .setkey = spacc_aead_setkey,
1505 .setauthsize = spacc_aead_setauthsize,
1506 .encrypt = spacc_aead_encrypt,
1507 .decrypt = spacc_aead_decrypt,
1508 .ivsize = DES3_EDE_BLOCK_SIZE,
1509 .maxauthsize = SHA1_DIGEST_SIZE,
1510 .init = spacc_aead_cra_init,
1511 .exit = spacc_aead_cra_exit,
1512 },
1513 },
1514 {
1515 .key_offs = DES_BLOCK_SIZE,
1516 .iv_offs = 0,
1517 .ctrl_default = SPA_CTRL_CIPH_ALG_AES |
1518 SPA_CTRL_CIPH_MODE_CBC |
1519 SPA_CTRL_HASH_ALG_SHA256 |
1520 SPA_CTRL_HASH_MODE_HMAC,
1521 .alg = {
1522 .base = {
1523 .cra_name = "authenc(hmac(sha256),"
1524 "cbc(des3_ede))",
1525 .cra_driver_name = "authenc-hmac-sha256-"
1526 "cbc-3des-picoxcell",
1527 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1528 .cra_flags = CRYPTO_ALG_ASYNC |
1529 CRYPTO_ALG_NEED_FALLBACK |
1530 CRYPTO_ALG_KERN_DRIVER_ONLY,
1531 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1532 .cra_ctxsize = sizeof(struct spacc_aead_ctx),
1533 .cra_module = THIS_MODULE,
1534 },
1535 .setkey = spacc_aead_setkey,
1536 .setauthsize = spacc_aead_setauthsize,
1537 .encrypt = spacc_aead_encrypt,
1538 .decrypt = spacc_aead_decrypt,
1539 .ivsize = DES3_EDE_BLOCK_SIZE,
1540 .maxauthsize = SHA256_DIGEST_SIZE,
1541 .init = spacc_aead_cra_init,
1542 .exit = spacc_aead_cra_exit,
1543 },
1544 },
1545 {
1546 .key_offs = DES_BLOCK_SIZE,
1547 .iv_offs = 0,
1548 .ctrl_default = SPA_CTRL_CIPH_ALG_DES |
1549 SPA_CTRL_CIPH_MODE_CBC |
1550 SPA_CTRL_HASH_ALG_MD5 |
1551 SPA_CTRL_HASH_MODE_HMAC,
1552 .alg = {
1553 .base = {
1554 .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
1555 .cra_driver_name = "authenc-hmac-md5-"
1556 "cbc-3des-picoxcell",
1557 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1558 .cra_flags = CRYPTO_ALG_ASYNC |
1559 CRYPTO_ALG_NEED_FALLBACK |
1560 CRYPTO_ALG_KERN_DRIVER_ONLY,
1561 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1562 .cra_ctxsize = sizeof(struct spacc_aead_ctx),
1563 .cra_module = THIS_MODULE,
1564 },
1565 .setkey = spacc_aead_setkey,
1566 .setauthsize = spacc_aead_setauthsize,
1567 .encrypt = spacc_aead_encrypt,
1568 .decrypt = spacc_aead_decrypt,
1569 .ivsize = DES3_EDE_BLOCK_SIZE,
1570 .maxauthsize = MD5_DIGEST_SIZE,
1571 .init = spacc_aead_cra_init,
1572 .exit = spacc_aead_cra_exit,
1573 },
1574 },
1575};
1576
1577static struct spacc_alg l2_engine_algs[] = {
1578 {
1579 .key_offs = 0,
1580 .iv_offs = SPACC_CRYPTO_KASUMI_F8_KEY_LEN,
1581 .ctrl_default = SPA_CTRL_CIPH_ALG_KASUMI |
1582 SPA_CTRL_CIPH_MODE_F8,
1583 .alg = {
1584 .cra_name = "f8(kasumi)",
1585 .cra_driver_name = "f8-kasumi-picoxcell",
1586 .cra_priority = SPACC_CRYPTO_ALG_PRIORITY,
1587 .cra_flags = CRYPTO_ALG_ASYNC |
1588 CRYPTO_ALG_KERN_DRIVER_ONLY,
1589 .cra_blocksize = 8,
1590 .cra_ctxsize = sizeof(struct spacc_ablk_ctx),
1591 .cra_type = &crypto_ablkcipher_type,
1592 .cra_module = THIS_MODULE,
1593 .cra_ablkcipher = {
1594 .setkey = spacc_kasumi_f8_setkey,
1595 .encrypt = spacc_ablk_encrypt,
1596 .decrypt = spacc_ablk_decrypt,
1597 .min_keysize = 16,
1598 .max_keysize = 16,
1599 .ivsize = 8,
1600 },
1601 .cra_init = spacc_ablk_cra_init,
1602 .cra_exit = spacc_ablk_cra_exit,
1603 },
1604 },
1605};
1606
1607#ifdef CONFIG_OF
1608static const struct of_device_id spacc_of_id_table[] = {
1609 { .compatible = "picochip,spacc-ipsec" },
1610 { .compatible = "picochip,spacc-l2" },
1611 {}
1612};
1613MODULE_DEVICE_TABLE(of, spacc_of_id_table);
1614#endif /* CONFIG_OF */
1615
1616static int spacc_probe(struct platform_device *pdev)
1617{
1618 int i, err, ret;
1619 struct resource *irq;
1620 struct device_node *np = pdev->dev.of_node;
1621 struct spacc_engine *engine = devm_kzalloc(&pdev->dev, sizeof(*engine),
1622 GFP_KERNEL);
1623 if (!engine)
1624 return -ENOMEM;
1625
1626 if (of_device_is_compatible(np, "picochip,spacc-ipsec")) {
1627 engine->max_ctxs = SPACC_CRYPTO_IPSEC_MAX_CTXS;
1628 engine->cipher_pg_sz = SPACC_CRYPTO_IPSEC_CIPHER_PG_SZ;
1629 engine->hash_pg_sz = SPACC_CRYPTO_IPSEC_HASH_PG_SZ;
1630 engine->fifo_sz = SPACC_CRYPTO_IPSEC_FIFO_SZ;
1631 engine->algs = ipsec_engine_algs;
1632 engine->num_algs = ARRAY_SIZE(ipsec_engine_algs);
1633 engine->aeads = ipsec_engine_aeads;
1634 engine->num_aeads = ARRAY_SIZE(ipsec_engine_aeads);
1635 } else if (of_device_is_compatible(np, "picochip,spacc-l2")) {
1636 engine->max_ctxs = SPACC_CRYPTO_L2_MAX_CTXS;
1637 engine->cipher_pg_sz = SPACC_CRYPTO_L2_CIPHER_PG_SZ;
1638 engine->hash_pg_sz = SPACC_CRYPTO_L2_HASH_PG_SZ;
1639 engine->fifo_sz = SPACC_CRYPTO_L2_FIFO_SZ;
1640 engine->algs = l2_engine_algs;
1641 engine->num_algs = ARRAY_SIZE(l2_engine_algs);
1642 } else {
1643 return -EINVAL;
1644 }
1645
1646 engine->name = dev_name(&pdev->dev);
1647
1648 engine->regs = devm_platform_ioremap_resource(pdev, 0);
1649 if (IS_ERR(engine->regs))
1650 return PTR_ERR(engine->regs);
1651
1652 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1653 if (!irq) {
1654 dev_err(&pdev->dev, "no memory/irq resource for engine\n");
1655 return -ENXIO;
1656 }
1657
1658 if (devm_request_irq(&pdev->dev, irq->start, spacc_spacc_irq, 0,
1659 engine->name, engine)) {
1660 dev_err(engine->dev, "failed to request IRQ\n");
1661 return -EBUSY;
1662 }
1663
1664 engine->dev = &pdev->dev;
1665 engine->cipher_ctx_base = engine->regs + SPA_CIPH_KEY_BASE_REG_OFFSET;
1666 engine->hash_key_base = engine->regs + SPA_HASH_KEY_BASE_REG_OFFSET;
1667
1668 engine->req_pool = dmam_pool_create(engine->name, engine->dev,
1669 MAX_DDT_LEN * sizeof(struct spacc_ddt), 8, SZ_64K);
1670 if (!engine->req_pool)
1671 return -ENOMEM;
1672
1673 spin_lock_init(&engine->hw_lock);
1674
1675 engine->clk = clk_get(&pdev->dev, "ref");
1676 if (IS_ERR(engine->clk)) {
1677 dev_info(&pdev->dev, "clk unavailable\n");
1678 return PTR_ERR(engine->clk);
1679 }
1680
1681 if (clk_prepare_enable(engine->clk)) {
1682 dev_info(&pdev->dev, "unable to prepare/enable clk\n");
1683 ret = -EIO;
1684 goto err_clk_put;
1685 }
1686
1687 ret = device_create_file(&pdev->dev, &dev_attr_stat_irq_thresh);
1688 if (ret)
1689 goto err_clk_disable;
1690
1691
1692 /*
1693 * Use an IRQ threshold of 50% as a default. This seems to be a
1694 * reasonable trade off of latency against throughput but can be
1695 * changed at runtime.
1696 */
1697 engine->stat_irq_thresh = (engine->fifo_sz / 2);
1698
1699 /*
1700 * Configure the interrupts. We only use the STAT_CNT interrupt as we
1701 * only submit a new packet for processing when we complete another in
1702 * the queue. This minimizes time spent in the interrupt handler.
1703 */
1704 writel(engine->stat_irq_thresh << SPA_IRQ_CTRL_STAT_CNT_OFFSET,
1705 engine->regs + SPA_IRQ_CTRL_REG_OFFSET);
1706 writel(SPA_IRQ_EN_STAT_EN | SPA_IRQ_EN_GLBL_EN,
1707 engine->regs + SPA_IRQ_EN_REG_OFFSET);
1708
1709 timer_setup(&engine->packet_timeout, spacc_packet_timeout, 0);
1710
1711 INIT_LIST_HEAD(&engine->pending);
1712 INIT_LIST_HEAD(&engine->completed);
1713 INIT_LIST_HEAD(&engine->in_progress);
1714 engine->in_flight = 0;
1715 tasklet_init(&engine->complete, spacc_spacc_complete,
1716 (unsigned long)engine);
1717
1718 platform_set_drvdata(pdev, engine);
1719
1720 ret = -EINVAL;
1721 INIT_LIST_HEAD(&engine->registered_algs);
1722 for (i = 0; i < engine->num_algs; ++i) {
1723 engine->algs[i].engine = engine;
1724 err = crypto_register_alg(&engine->algs[i].alg);
1725 if (!err) {
1726 list_add_tail(&engine->algs[i].entry,
1727 &engine->registered_algs);
1728 ret = 0;
1729 }
1730 if (err)
1731 dev_err(engine->dev, "failed to register alg \"%s\"\n",
1732 engine->algs[i].alg.cra_name);
1733 else
1734 dev_dbg(engine->dev, "registered alg \"%s\"\n",
1735 engine->algs[i].alg.cra_name);
1736 }
1737
1738 INIT_LIST_HEAD(&engine->registered_aeads);
1739 for (i = 0; i < engine->num_aeads; ++i) {
1740 engine->aeads[i].engine = engine;
1741 err = crypto_register_aead(&engine->aeads[i].alg);
1742 if (!err) {
1743 list_add_tail(&engine->aeads[i].entry,
1744 &engine->registered_aeads);
1745 ret = 0;
1746 }
1747 if (err)
1748 dev_err(engine->dev, "failed to register alg \"%s\"\n",
1749 engine->aeads[i].alg.base.cra_name);
1750 else
1751 dev_dbg(engine->dev, "registered alg \"%s\"\n",
1752 engine->aeads[i].alg.base.cra_name);
1753 }
1754
1755 if (!ret)
1756 return 0;
1757
1758 del_timer_sync(&engine->packet_timeout);
1759 device_remove_file(&pdev->dev, &dev_attr_stat_irq_thresh);
1760err_clk_disable:
1761 clk_disable_unprepare(engine->clk);
1762err_clk_put:
1763 clk_put(engine->clk);
1764
1765 return ret;
1766}
1767
1768static int spacc_remove(struct platform_device *pdev)
1769{
1770 struct spacc_aead *aead, *an;
1771 struct spacc_alg *alg, *next;
1772 struct spacc_engine *engine = platform_get_drvdata(pdev);
1773
1774 del_timer_sync(&engine->packet_timeout);
1775 device_remove_file(&pdev->dev, &dev_attr_stat_irq_thresh);
1776
1777 list_for_each_entry_safe(aead, an, &engine->registered_aeads, entry) {
1778 list_del(&aead->entry);
1779 crypto_unregister_aead(&aead->alg);
1780 }
1781
1782 list_for_each_entry_safe(alg, next, &engine->registered_algs, entry) {
1783 list_del(&alg->entry);
1784 crypto_unregister_alg(&alg->alg);
1785 }
1786
1787 clk_disable_unprepare(engine->clk);
1788 clk_put(engine->clk);
1789
1790 return 0;
1791}
1792
1793static struct platform_driver spacc_driver = {
1794 .probe = spacc_probe,
1795 .remove = spacc_remove,
1796 .driver = {
1797 .name = "picochip,spacc",
1798#ifdef CONFIG_PM
1799 .pm = &spacc_pm_ops,
1800#endif /* CONFIG_PM */
1801 .of_match_table = of_match_ptr(spacc_of_id_table),
1802 },
1803};
1804
1805module_platform_driver(spacc_driver);
1806
1807MODULE_LICENSE("GPL");
1808MODULE_AUTHOR("Jamie Iles");