Loading...
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2012 Freescale Semiconductor, Inc.
4 */
5
6#include <linux/clk.h>
7#include <linux/err.h>
8#include <linux/io.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/platform_device.h>
13#include <linux/pwm.h>
14#include <linux/slab.h>
15#include <linux/stmp_device.h>
16
17#define SET 0x4
18#define CLR 0x8
19#define TOG 0xc
20
21#define PWM_CTRL 0x0
22#define PWM_ACTIVE0 0x10
23#define PWM_PERIOD0 0x20
24#define PERIOD_PERIOD(p) ((p) & 0xffff)
25#define PERIOD_PERIOD_MAX 0x10000
26#define PERIOD_ACTIVE_HIGH (3 << 16)
27#define PERIOD_ACTIVE_LOW (2 << 16)
28#define PERIOD_INACTIVE_HIGH (3 << 18)
29#define PERIOD_INACTIVE_LOW (2 << 18)
30#define PERIOD_POLARITY_NORMAL (PERIOD_ACTIVE_HIGH | PERIOD_INACTIVE_LOW)
31#define PERIOD_POLARITY_INVERSE (PERIOD_ACTIVE_LOW | PERIOD_INACTIVE_HIGH)
32#define PERIOD_CDIV(div) (((div) & 0x7) << 20)
33#define PERIOD_CDIV_MAX 8
34
35static const u8 cdiv_shift[PERIOD_CDIV_MAX] = {
36 0, 1, 2, 3, 4, 6, 8, 10
37};
38
39struct mxs_pwm_chip {
40 struct clk *clk;
41 void __iomem *base;
42};
43
44static inline struct mxs_pwm_chip *to_mxs_pwm_chip(struct pwm_chip *chip)
45{
46 return pwmchip_get_drvdata(chip);
47}
48
49static int mxs_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
50 const struct pwm_state *state)
51{
52 struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
53 int ret, div = 0;
54 unsigned int period_cycles, duty_cycles;
55 unsigned long rate;
56 unsigned long long c;
57 unsigned int pol_bits;
58
59 /*
60 * If the PWM channel is disabled, make sure to turn on the
61 * clock before calling clk_get_rate() and writing to the
62 * registers. Otherwise, just keep it enabled.
63 */
64 if (!pwm_is_enabled(pwm)) {
65 ret = clk_prepare_enable(mxs->clk);
66 if (ret)
67 return ret;
68 }
69
70 if (!state->enabled && pwm_is_enabled(pwm))
71 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR);
72
73 rate = clk_get_rate(mxs->clk);
74 while (1) {
75 c = rate >> cdiv_shift[div];
76 c = c * state->period;
77 do_div(c, 1000000000);
78 if (c < PERIOD_PERIOD_MAX)
79 break;
80 div++;
81 if (div >= PERIOD_CDIV_MAX)
82 return -EINVAL;
83 }
84
85 period_cycles = c;
86 c *= state->duty_cycle;
87 do_div(c, state->period);
88 duty_cycles = c;
89
90 /*
91 * The data sheet the says registers must be written to in
92 * this order (ACTIVEn, then PERIODn). Also, the new settings
93 * only take effect at the beginning of a new period, avoiding
94 * glitches.
95 */
96
97 pol_bits = state->polarity == PWM_POLARITY_NORMAL ?
98 PERIOD_POLARITY_NORMAL : PERIOD_POLARITY_INVERSE;
99 writel(duty_cycles << 16,
100 mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20);
101 writel(PERIOD_PERIOD(period_cycles) | pol_bits | PERIOD_CDIV(div),
102 mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20);
103
104 if (state->enabled) {
105 if (!pwm_is_enabled(pwm)) {
106 /*
107 * The clock was enabled above. Just enable
108 * the channel in the control register.
109 */
110 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET);
111 }
112 } else {
113 clk_disable_unprepare(mxs->clk);
114 }
115 return 0;
116}
117
118static const struct pwm_ops mxs_pwm_ops = {
119 .apply = mxs_pwm_apply,
120};
121
122static int mxs_pwm_probe(struct platform_device *pdev)
123{
124 struct device_node *np = pdev->dev.of_node;
125 struct pwm_chip *chip;
126 struct mxs_pwm_chip *mxs;
127 u32 npwm;
128 int ret;
129
130 ret = of_property_read_u32(np, "fsl,pwm-number", &npwm);
131 if (ret < 0) {
132 dev_err(&pdev->dev, "failed to get pwm number: %d\n", ret);
133 return ret;
134 }
135
136 chip = devm_pwmchip_alloc(&pdev->dev, npwm, sizeof(*mxs));
137 if (IS_ERR(chip))
138 return PTR_ERR(chip);
139 mxs = to_mxs_pwm_chip(chip);
140
141 mxs->base = devm_platform_ioremap_resource(pdev, 0);
142 if (IS_ERR(mxs->base))
143 return PTR_ERR(mxs->base);
144
145 mxs->clk = devm_clk_get(&pdev->dev, NULL);
146 if (IS_ERR(mxs->clk))
147 return PTR_ERR(mxs->clk);
148
149 chip->ops = &mxs_pwm_ops;
150
151 /* FIXME: Only do this if the PWM isn't already running */
152 ret = stmp_reset_block(mxs->base);
153 if (ret)
154 return dev_err_probe(&pdev->dev, ret, "failed to reset PWM\n");
155
156 ret = devm_pwmchip_add(&pdev->dev, chip);
157 if (ret < 0) {
158 dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret);
159 return ret;
160 }
161
162 return 0;
163}
164
165static const struct of_device_id mxs_pwm_dt_ids[] = {
166 { .compatible = "fsl,imx23-pwm", },
167 { /* sentinel */ }
168};
169MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids);
170
171static struct platform_driver mxs_pwm_driver = {
172 .driver = {
173 .name = "mxs-pwm",
174 .of_match_table = mxs_pwm_dt_ids,
175 },
176 .probe = mxs_pwm_probe,
177};
178module_platform_driver(mxs_pwm_driver);
179
180MODULE_ALIAS("platform:mxs-pwm");
181MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
182MODULE_DESCRIPTION("Freescale MXS PWM Driver");
183MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2012 Freescale Semiconductor, Inc.
4 */
5
6#include <linux/clk.h>
7#include <linux/err.h>
8#include <linux/io.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/of_address.h>
13#include <linux/platform_device.h>
14#include <linux/pwm.h>
15#include <linux/slab.h>
16#include <linux/stmp_device.h>
17
18#define SET 0x4
19#define CLR 0x8
20#define TOG 0xc
21
22#define PWM_CTRL 0x0
23#define PWM_ACTIVE0 0x10
24#define PWM_PERIOD0 0x20
25#define PERIOD_PERIOD(p) ((p) & 0xffff)
26#define PERIOD_PERIOD_MAX 0x10000
27#define PERIOD_ACTIVE_HIGH (3 << 16)
28#define PERIOD_INACTIVE_LOW (2 << 18)
29#define PERIOD_CDIV(div) (((div) & 0x7) << 20)
30#define PERIOD_CDIV_MAX 8
31
32static const unsigned int cdiv[PERIOD_CDIV_MAX] = {
33 1, 2, 4, 8, 16, 64, 256, 1024
34};
35
36struct mxs_pwm_chip {
37 struct pwm_chip chip;
38 struct clk *clk;
39 void __iomem *base;
40};
41
42#define to_mxs_pwm_chip(_chip) container_of(_chip, struct mxs_pwm_chip, chip)
43
44static int mxs_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
45 int duty_ns, int period_ns)
46{
47 struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
48 int ret, div = 0;
49 unsigned int period_cycles, duty_cycles;
50 unsigned long rate;
51 unsigned long long c;
52
53 rate = clk_get_rate(mxs->clk);
54 while (1) {
55 c = rate / cdiv[div];
56 c = c * period_ns;
57 do_div(c, 1000000000);
58 if (c < PERIOD_PERIOD_MAX)
59 break;
60 div++;
61 if (div >= PERIOD_CDIV_MAX)
62 return -EINVAL;
63 }
64
65 period_cycles = c;
66 c *= duty_ns;
67 do_div(c, period_ns);
68 duty_cycles = c;
69
70 /*
71 * If the PWM channel is disabled, make sure to turn on the clock
72 * before writing the register. Otherwise, keep it enabled.
73 */
74 if (!pwm_is_enabled(pwm)) {
75 ret = clk_prepare_enable(mxs->clk);
76 if (ret)
77 return ret;
78 }
79
80 writel(duty_cycles << 16,
81 mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20);
82 writel(PERIOD_PERIOD(period_cycles) | PERIOD_ACTIVE_HIGH |
83 PERIOD_INACTIVE_LOW | PERIOD_CDIV(div),
84 mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20);
85
86 /*
87 * If the PWM is not enabled, turn the clock off again to save power.
88 */
89 if (!pwm_is_enabled(pwm))
90 clk_disable_unprepare(mxs->clk);
91
92 return 0;
93}
94
95static int mxs_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
96{
97 struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
98 int ret;
99
100 ret = clk_prepare_enable(mxs->clk);
101 if (ret)
102 return ret;
103
104 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET);
105
106 return 0;
107}
108
109static void mxs_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
110{
111 struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
112
113 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR);
114
115 clk_disable_unprepare(mxs->clk);
116}
117
118static const struct pwm_ops mxs_pwm_ops = {
119 .config = mxs_pwm_config,
120 .enable = mxs_pwm_enable,
121 .disable = mxs_pwm_disable,
122 .owner = THIS_MODULE,
123};
124
125static int mxs_pwm_probe(struct platform_device *pdev)
126{
127 struct device_node *np = pdev->dev.of_node;
128 struct mxs_pwm_chip *mxs;
129 int ret;
130
131 mxs = devm_kzalloc(&pdev->dev, sizeof(*mxs), GFP_KERNEL);
132 if (!mxs)
133 return -ENOMEM;
134
135 mxs->base = devm_platform_ioremap_resource(pdev, 0);
136 if (IS_ERR(mxs->base))
137 return PTR_ERR(mxs->base);
138
139 mxs->clk = devm_clk_get(&pdev->dev, NULL);
140 if (IS_ERR(mxs->clk))
141 return PTR_ERR(mxs->clk);
142
143 mxs->chip.dev = &pdev->dev;
144 mxs->chip.ops = &mxs_pwm_ops;
145 mxs->chip.base = -1;
146
147 ret = of_property_read_u32(np, "fsl,pwm-number", &mxs->chip.npwm);
148 if (ret < 0) {
149 dev_err(&pdev->dev, "failed to get pwm number: %d\n", ret);
150 return ret;
151 }
152
153 ret = pwmchip_add(&mxs->chip);
154 if (ret < 0) {
155 dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret);
156 return ret;
157 }
158
159 platform_set_drvdata(pdev, mxs);
160
161 ret = stmp_reset_block(mxs->base);
162 if (ret)
163 goto pwm_remove;
164
165 return 0;
166
167pwm_remove:
168 pwmchip_remove(&mxs->chip);
169 return ret;
170}
171
172static int mxs_pwm_remove(struct platform_device *pdev)
173{
174 struct mxs_pwm_chip *mxs = platform_get_drvdata(pdev);
175
176 return pwmchip_remove(&mxs->chip);
177}
178
179static const struct of_device_id mxs_pwm_dt_ids[] = {
180 { .compatible = "fsl,imx23-pwm", },
181 { /* sentinel */ }
182};
183MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids);
184
185static struct platform_driver mxs_pwm_driver = {
186 .driver = {
187 .name = "mxs-pwm",
188 .of_match_table = mxs_pwm_dt_ids,
189 },
190 .probe = mxs_pwm_probe,
191 .remove = mxs_pwm_remove,
192};
193module_platform_driver(mxs_pwm_driver);
194
195MODULE_ALIAS("platform:mxs-pwm");
196MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
197MODULE_DESCRIPTION("Freescale MXS PWM Driver");
198MODULE_LICENSE("GPL v2");