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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2013 - 2018 Intel Corporation. */
3
4#include <linux/bpf_trace.h>
5#include <linux/net/intel/libie/rx.h>
6#include <linux/prefetch.h>
7#include <linux/sctp.h>
8#include <net/mpls.h>
9#include <net/xdp.h>
10#include "i40e_txrx_common.h"
11#include "i40e_trace.h"
12#include "i40e_xsk.h"
13
14#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
15/**
16 * i40e_fdir - Generate a Flow Director descriptor based on fdata
17 * @tx_ring: Tx ring to send buffer on
18 * @fdata: Flow director filter data
19 * @add: Indicate if we are adding a rule or deleting one
20 *
21 **/
22static void i40e_fdir(struct i40e_ring *tx_ring,
23 struct i40e_fdir_filter *fdata, bool add)
24{
25 struct i40e_filter_program_desc *fdir_desc;
26 struct i40e_pf *pf = tx_ring->vsi->back;
27 u32 flex_ptype, dtype_cmd, vsi_id;
28 u16 i;
29
30 /* grab the next descriptor */
31 i = tx_ring->next_to_use;
32 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
33
34 i++;
35 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
36
37 flex_ptype = FIELD_PREP(I40E_TXD_FLTR_QW0_QINDEX_MASK, fdata->q_index);
38
39 flex_ptype |= FIELD_PREP(I40E_TXD_FLTR_QW0_FLEXOFF_MASK,
40 fdata->flex_off);
41
42 flex_ptype |= FIELD_PREP(I40E_TXD_FLTR_QW0_PCTYPE_MASK, fdata->pctype);
43
44 /* Use LAN VSI Id if not programmed by user */
45 vsi_id = fdata->dest_vsi ? : i40e_pf_get_main_vsi(pf)->id;
46 flex_ptype |= FIELD_PREP(I40E_TXD_FLTR_QW0_DEST_VSI_MASK, vsi_id);
47
48 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
49
50 dtype_cmd |= add ?
51 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
52 I40E_TXD_FLTR_QW1_PCMD_SHIFT :
53 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
54 I40E_TXD_FLTR_QW1_PCMD_SHIFT;
55
56 dtype_cmd |= FIELD_PREP(I40E_TXD_FLTR_QW1_DEST_MASK, fdata->dest_ctl);
57
58 dtype_cmd |= FIELD_PREP(I40E_TXD_FLTR_QW1_FD_STATUS_MASK,
59 fdata->fd_status);
60
61 if (fdata->cnt_index) {
62 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
63 dtype_cmd |= FIELD_PREP(I40E_TXD_FLTR_QW1_CNTINDEX_MASK,
64 fdata->cnt_index);
65 }
66
67 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
68 fdir_desc->rsvd = cpu_to_le32(0);
69 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
70 fdir_desc->fd_id = cpu_to_le32(fdata->fd_id);
71}
72
73#define I40E_FD_CLEAN_DELAY 10
74/**
75 * i40e_program_fdir_filter - Program a Flow Director filter
76 * @fdir_data: Packet data that will be filter parameters
77 * @raw_packet: the pre-allocated packet buffer for FDir
78 * @pf: The PF pointer
79 * @add: True for add/update, False for remove
80 **/
81static int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data,
82 u8 *raw_packet, struct i40e_pf *pf,
83 bool add)
84{
85 struct i40e_tx_buffer *tx_buf, *first;
86 struct i40e_tx_desc *tx_desc;
87 struct i40e_ring *tx_ring;
88 struct i40e_vsi *vsi;
89 struct device *dev;
90 dma_addr_t dma;
91 u32 td_cmd = 0;
92 u16 i;
93
94 /* find existing FDIR VSI */
95 vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR);
96 if (!vsi)
97 return -ENOENT;
98
99 tx_ring = vsi->tx_rings[0];
100 dev = tx_ring->dev;
101
102 /* we need two descriptors to add/del a filter and we can wait */
103 for (i = I40E_FD_CLEAN_DELAY; I40E_DESC_UNUSED(tx_ring) < 2; i--) {
104 if (!i)
105 return -EAGAIN;
106 msleep_interruptible(1);
107 }
108
109 dma = dma_map_single(dev, raw_packet,
110 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE);
111 if (dma_mapping_error(dev, dma))
112 goto dma_fail;
113
114 /* grab the next descriptor */
115 i = tx_ring->next_to_use;
116 first = &tx_ring->tx_bi[i];
117 i40e_fdir(tx_ring, fdir_data, add);
118
119 /* Now program a dummy descriptor */
120 i = tx_ring->next_to_use;
121 tx_desc = I40E_TX_DESC(tx_ring, i);
122 tx_buf = &tx_ring->tx_bi[i];
123
124 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
125
126 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer));
127
128 /* record length, and DMA address */
129 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE);
130 dma_unmap_addr_set(tx_buf, dma, dma);
131
132 tx_desc->buffer_addr = cpu_to_le64(dma);
133 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY;
134
135 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB;
136 tx_buf->raw_buf = (void *)raw_packet;
137
138 tx_desc->cmd_type_offset_bsz =
139 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0);
140
141 /* Force memory writes to complete before letting h/w
142 * know there are new descriptors to fetch.
143 */
144 wmb();
145
146 /* Mark the data descriptor to be watched */
147 first->next_to_watch = tx_desc;
148
149 writel(tx_ring->next_to_use, tx_ring->tail);
150 return 0;
151
152dma_fail:
153 return -1;
154}
155
156/**
157 * i40e_create_dummy_packet - Constructs dummy packet for HW
158 * @dummy_packet: preallocated space for dummy packet
159 * @ipv4: is layer 3 packet of version 4 or 6
160 * @l4proto: next level protocol used in data portion of l3
161 * @data: filter data
162 *
163 * Returns address of layer 4 protocol dummy packet.
164 **/
165static char *i40e_create_dummy_packet(u8 *dummy_packet, bool ipv4, u8 l4proto,
166 struct i40e_fdir_filter *data)
167{
168 bool is_vlan = !!data->vlan_tag;
169 struct vlan_hdr vlan = {};
170 struct ipv6hdr ipv6 = {};
171 struct ethhdr eth = {};
172 struct iphdr ip = {};
173 u8 *tmp;
174
175 if (ipv4) {
176 eth.h_proto = cpu_to_be16(ETH_P_IP);
177 ip.protocol = l4proto;
178 ip.version = 0x4;
179 ip.ihl = 0x5;
180
181 ip.daddr = data->dst_ip;
182 ip.saddr = data->src_ip;
183 } else {
184 eth.h_proto = cpu_to_be16(ETH_P_IPV6);
185 ipv6.nexthdr = l4proto;
186 ipv6.version = 0x6;
187
188 memcpy(&ipv6.saddr.in6_u.u6_addr32, data->src_ip6,
189 sizeof(__be32) * 4);
190 memcpy(&ipv6.daddr.in6_u.u6_addr32, data->dst_ip6,
191 sizeof(__be32) * 4);
192 }
193
194 if (is_vlan) {
195 vlan.h_vlan_TCI = data->vlan_tag;
196 vlan.h_vlan_encapsulated_proto = eth.h_proto;
197 eth.h_proto = data->vlan_etype;
198 }
199
200 tmp = dummy_packet;
201 memcpy(tmp, ð, sizeof(eth));
202 tmp += sizeof(eth);
203
204 if (is_vlan) {
205 memcpy(tmp, &vlan, sizeof(vlan));
206 tmp += sizeof(vlan);
207 }
208
209 if (ipv4) {
210 memcpy(tmp, &ip, sizeof(ip));
211 tmp += sizeof(ip);
212 } else {
213 memcpy(tmp, &ipv6, sizeof(ipv6));
214 tmp += sizeof(ipv6);
215 }
216
217 return tmp;
218}
219
220/**
221 * i40e_create_dummy_udp_packet - helper function to create UDP packet
222 * @raw_packet: preallocated space for dummy packet
223 * @ipv4: is layer 3 packet of version 4 or 6
224 * @l4proto: next level protocol used in data portion of l3
225 * @data: filter data
226 *
227 * Helper function to populate udp fields.
228 **/
229static void i40e_create_dummy_udp_packet(u8 *raw_packet, bool ipv4, u8 l4proto,
230 struct i40e_fdir_filter *data)
231{
232 struct udphdr *udp;
233 u8 *tmp;
234
235 tmp = i40e_create_dummy_packet(raw_packet, ipv4, IPPROTO_UDP, data);
236 udp = (struct udphdr *)(tmp);
237 udp->dest = data->dst_port;
238 udp->source = data->src_port;
239}
240
241/**
242 * i40e_create_dummy_tcp_packet - helper function to create TCP packet
243 * @raw_packet: preallocated space for dummy packet
244 * @ipv4: is layer 3 packet of version 4 or 6
245 * @l4proto: next level protocol used in data portion of l3
246 * @data: filter data
247 *
248 * Helper function to populate tcp fields.
249 **/
250static void i40e_create_dummy_tcp_packet(u8 *raw_packet, bool ipv4, u8 l4proto,
251 struct i40e_fdir_filter *data)
252{
253 struct tcphdr *tcp;
254 u8 *tmp;
255 /* Dummy tcp packet */
256 static const char tcp_packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
257 0x50, 0x11, 0x0, 0x72, 0, 0, 0, 0};
258
259 tmp = i40e_create_dummy_packet(raw_packet, ipv4, IPPROTO_TCP, data);
260
261 tcp = (struct tcphdr *)tmp;
262 memcpy(tcp, tcp_packet, sizeof(tcp_packet));
263 tcp->dest = data->dst_port;
264 tcp->source = data->src_port;
265}
266
267/**
268 * i40e_create_dummy_sctp_packet - helper function to create SCTP packet
269 * @raw_packet: preallocated space for dummy packet
270 * @ipv4: is layer 3 packet of version 4 or 6
271 * @l4proto: next level protocol used in data portion of l3
272 * @data: filter data
273 *
274 * Helper function to populate sctp fields.
275 **/
276static void i40e_create_dummy_sctp_packet(u8 *raw_packet, bool ipv4,
277 u8 l4proto,
278 struct i40e_fdir_filter *data)
279{
280 struct sctphdr *sctp;
281 u8 *tmp;
282
283 tmp = i40e_create_dummy_packet(raw_packet, ipv4, IPPROTO_SCTP, data);
284
285 sctp = (struct sctphdr *)tmp;
286 sctp->dest = data->dst_port;
287 sctp->source = data->src_port;
288}
289
290/**
291 * i40e_prepare_fdir_filter - Prepare and program fdir filter
292 * @pf: physical function to attach filter to
293 * @fd_data: filter data
294 * @add: add or delete filter
295 * @packet_addr: address of dummy packet, used in filtering
296 * @payload_offset: offset from dummy packet address to user defined data
297 * @pctype: Packet type for which filter is used
298 *
299 * Helper function to offset data of dummy packet, program it and
300 * handle errors.
301 **/
302static int i40e_prepare_fdir_filter(struct i40e_pf *pf,
303 struct i40e_fdir_filter *fd_data,
304 bool add, char *packet_addr,
305 int payload_offset, u8 pctype)
306{
307 int ret;
308
309 if (fd_data->flex_filter) {
310 u8 *payload;
311 __be16 pattern = fd_data->flex_word;
312 u16 off = fd_data->flex_offset;
313
314 payload = packet_addr + payload_offset;
315
316 /* If user provided vlan, offset payload by vlan header length */
317 if (!!fd_data->vlan_tag)
318 payload += VLAN_HLEN;
319
320 *((__force __be16 *)(payload + off)) = pattern;
321 }
322
323 fd_data->pctype = pctype;
324 ret = i40e_program_fdir_filter(fd_data, packet_addr, pf, add);
325 if (ret) {
326 dev_info(&pf->pdev->dev,
327 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
328 fd_data->pctype, fd_data->fd_id, ret);
329 /* Free the packet buffer since it wasn't added to the ring */
330 return -EOPNOTSUPP;
331 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
332 if (add)
333 dev_info(&pf->pdev->dev,
334 "Filter OK for PCTYPE %d loc = %d\n",
335 fd_data->pctype, fd_data->fd_id);
336 else
337 dev_info(&pf->pdev->dev,
338 "Filter deleted for PCTYPE %d loc = %d\n",
339 fd_data->pctype, fd_data->fd_id);
340 }
341
342 return ret;
343}
344
345/**
346 * i40e_change_filter_num - Prepare and program fdir filter
347 * @ipv4: is layer 3 packet of version 4 or 6
348 * @add: add or delete filter
349 * @ipv4_filter_num: field to update
350 * @ipv6_filter_num: field to update
351 *
352 * Update filter number field for pf.
353 **/
354static void i40e_change_filter_num(bool ipv4, bool add, u16 *ipv4_filter_num,
355 u16 *ipv6_filter_num)
356{
357 if (add) {
358 if (ipv4)
359 (*ipv4_filter_num)++;
360 else
361 (*ipv6_filter_num)++;
362 } else {
363 if (ipv4)
364 (*ipv4_filter_num)--;
365 else
366 (*ipv6_filter_num)--;
367 }
368}
369
370#define I40E_UDPIP_DUMMY_PACKET_LEN 42
371#define I40E_UDPIP6_DUMMY_PACKET_LEN 62
372/**
373 * i40e_add_del_fdir_udp - Add/Remove UDP filters
374 * @vsi: pointer to the targeted VSI
375 * @fd_data: the flow director data required for the FDir descriptor
376 * @add: true adds a filter, false removes it
377 * @ipv4: true is v4, false is v6
378 *
379 * Returns 0 if the filters were successfully added or removed
380 **/
381static int i40e_add_del_fdir_udp(struct i40e_vsi *vsi,
382 struct i40e_fdir_filter *fd_data,
383 bool add,
384 bool ipv4)
385{
386 struct i40e_pf *pf = vsi->back;
387 u8 *raw_packet;
388 int ret;
389
390 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
391 if (!raw_packet)
392 return -ENOMEM;
393
394 i40e_create_dummy_udp_packet(raw_packet, ipv4, IPPROTO_UDP, fd_data);
395
396 if (ipv4)
397 ret = i40e_prepare_fdir_filter
398 (pf, fd_data, add, raw_packet,
399 I40E_UDPIP_DUMMY_PACKET_LEN,
400 I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
401 else
402 ret = i40e_prepare_fdir_filter
403 (pf, fd_data, add, raw_packet,
404 I40E_UDPIP6_DUMMY_PACKET_LEN,
405 I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
406
407 if (ret) {
408 kfree(raw_packet);
409 return ret;
410 }
411
412 i40e_change_filter_num(ipv4, add, &pf->fd_udp4_filter_cnt,
413 &pf->fd_udp6_filter_cnt);
414
415 return 0;
416}
417
418#define I40E_TCPIP_DUMMY_PACKET_LEN 54
419#define I40E_TCPIP6_DUMMY_PACKET_LEN 74
420/**
421 * i40e_add_del_fdir_tcp - Add/Remove TCPv4 filters
422 * @vsi: pointer to the targeted VSI
423 * @fd_data: the flow director data required for the FDir descriptor
424 * @add: true adds a filter, false removes it
425 * @ipv4: true is v4, false is v6
426 *
427 * Returns 0 if the filters were successfully added or removed
428 **/
429static int i40e_add_del_fdir_tcp(struct i40e_vsi *vsi,
430 struct i40e_fdir_filter *fd_data,
431 bool add,
432 bool ipv4)
433{
434 struct i40e_pf *pf = vsi->back;
435 u8 *raw_packet;
436 int ret;
437
438 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
439 if (!raw_packet)
440 return -ENOMEM;
441
442 i40e_create_dummy_tcp_packet(raw_packet, ipv4, IPPROTO_TCP, fd_data);
443 if (ipv4)
444 ret = i40e_prepare_fdir_filter
445 (pf, fd_data, add, raw_packet,
446 I40E_TCPIP_DUMMY_PACKET_LEN,
447 I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
448 else
449 ret = i40e_prepare_fdir_filter
450 (pf, fd_data, add, raw_packet,
451 I40E_TCPIP6_DUMMY_PACKET_LEN,
452 I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
453
454 if (ret) {
455 kfree(raw_packet);
456 return ret;
457 }
458
459 i40e_change_filter_num(ipv4, add, &pf->fd_tcp4_filter_cnt,
460 &pf->fd_tcp6_filter_cnt);
461
462 if (add) {
463 if (test_bit(I40E_FLAG_FD_ATR_ENA, pf->flags) &&
464 I40E_DEBUG_FD & pf->hw.debug_mask)
465 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");
466 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
467 }
468 return 0;
469}
470
471#define I40E_SCTPIP_DUMMY_PACKET_LEN 46
472#define I40E_SCTPIP6_DUMMY_PACKET_LEN 66
473/**
474 * i40e_add_del_fdir_sctp - Add/Remove SCTPv4 Flow Director filters for
475 * a specific flow spec
476 * @vsi: pointer to the targeted VSI
477 * @fd_data: the flow director data required for the FDir descriptor
478 * @add: true adds a filter, false removes it
479 * @ipv4: true is v4, false is v6
480 *
481 * Returns 0 if the filters were successfully added or removed
482 **/
483static int i40e_add_del_fdir_sctp(struct i40e_vsi *vsi,
484 struct i40e_fdir_filter *fd_data,
485 bool add,
486 bool ipv4)
487{
488 struct i40e_pf *pf = vsi->back;
489 u8 *raw_packet;
490 int ret;
491
492 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
493 if (!raw_packet)
494 return -ENOMEM;
495
496 i40e_create_dummy_sctp_packet(raw_packet, ipv4, IPPROTO_SCTP, fd_data);
497
498 if (ipv4)
499 ret = i40e_prepare_fdir_filter
500 (pf, fd_data, add, raw_packet,
501 I40E_SCTPIP_DUMMY_PACKET_LEN,
502 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
503 else
504 ret = i40e_prepare_fdir_filter
505 (pf, fd_data, add, raw_packet,
506 I40E_SCTPIP6_DUMMY_PACKET_LEN,
507 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
508
509 if (ret) {
510 kfree(raw_packet);
511 return ret;
512 }
513
514 i40e_change_filter_num(ipv4, add, &pf->fd_sctp4_filter_cnt,
515 &pf->fd_sctp6_filter_cnt);
516
517 return 0;
518}
519
520#define I40E_IP_DUMMY_PACKET_LEN 34
521#define I40E_IP6_DUMMY_PACKET_LEN 54
522/**
523 * i40e_add_del_fdir_ip - Add/Remove IPv4 Flow Director filters for
524 * a specific flow spec
525 * @vsi: pointer to the targeted VSI
526 * @fd_data: the flow director data required for the FDir descriptor
527 * @add: true adds a filter, false removes it
528 * @ipv4: true is v4, false is v6
529 *
530 * Returns 0 if the filters were successfully added or removed
531 **/
532static int i40e_add_del_fdir_ip(struct i40e_vsi *vsi,
533 struct i40e_fdir_filter *fd_data,
534 bool add,
535 bool ipv4)
536{
537 struct i40e_pf *pf = vsi->back;
538 int payload_offset;
539 u8 *raw_packet;
540 int iter_start;
541 int iter_end;
542 int ret;
543 int i;
544
545 if (ipv4) {
546 iter_start = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
547 iter_end = I40E_FILTER_PCTYPE_FRAG_IPV4;
548 } else {
549 iter_start = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
550 iter_end = I40E_FILTER_PCTYPE_FRAG_IPV6;
551 }
552
553 for (i = iter_start; i <= iter_end; i++) {
554 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
555 if (!raw_packet)
556 return -ENOMEM;
557
558 /* IPv6 no header option differs from IPv4 */
559 (void)i40e_create_dummy_packet
560 (raw_packet, ipv4, (ipv4) ? IPPROTO_IP : IPPROTO_NONE,
561 fd_data);
562
563 payload_offset = (ipv4) ? I40E_IP_DUMMY_PACKET_LEN :
564 I40E_IP6_DUMMY_PACKET_LEN;
565 ret = i40e_prepare_fdir_filter(pf, fd_data, add, raw_packet,
566 payload_offset, i);
567 if (ret)
568 goto err;
569 }
570
571 i40e_change_filter_num(ipv4, add, &pf->fd_ip4_filter_cnt,
572 &pf->fd_ip6_filter_cnt);
573
574 return 0;
575err:
576 kfree(raw_packet);
577 return ret;
578}
579
580/**
581 * i40e_add_del_fdir - Build raw packets to add/del fdir filter
582 * @vsi: pointer to the targeted VSI
583 * @input: filter to add or delete
584 * @add: true adds a filter, false removes it
585 *
586 **/
587int i40e_add_del_fdir(struct i40e_vsi *vsi,
588 struct i40e_fdir_filter *input, bool add)
589{
590 enum ip_ver { ipv6 = 0, ipv4 = 1 };
591 struct i40e_pf *pf = vsi->back;
592 int ret;
593
594 switch (input->flow_type & ~FLOW_EXT) {
595 case TCP_V4_FLOW:
596 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv4);
597 break;
598 case UDP_V4_FLOW:
599 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv4);
600 break;
601 case SCTP_V4_FLOW:
602 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv4);
603 break;
604 case TCP_V6_FLOW:
605 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv6);
606 break;
607 case UDP_V6_FLOW:
608 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv6);
609 break;
610 case SCTP_V6_FLOW:
611 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv6);
612 break;
613 case IP_USER_FLOW:
614 switch (input->ipl4_proto) {
615 case IPPROTO_TCP:
616 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv4);
617 break;
618 case IPPROTO_UDP:
619 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv4);
620 break;
621 case IPPROTO_SCTP:
622 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv4);
623 break;
624 case IPPROTO_IP:
625 ret = i40e_add_del_fdir_ip(vsi, input, add, ipv4);
626 break;
627 default:
628 /* We cannot support masking based on protocol */
629 dev_info(&pf->pdev->dev, "Unsupported IPv4 protocol 0x%02x\n",
630 input->ipl4_proto);
631 return -EINVAL;
632 }
633 break;
634 case IPV6_USER_FLOW:
635 switch (input->ipl4_proto) {
636 case IPPROTO_TCP:
637 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv6);
638 break;
639 case IPPROTO_UDP:
640 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv6);
641 break;
642 case IPPROTO_SCTP:
643 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv6);
644 break;
645 case IPPROTO_IP:
646 ret = i40e_add_del_fdir_ip(vsi, input, add, ipv6);
647 break;
648 default:
649 /* We cannot support masking based on protocol */
650 dev_info(&pf->pdev->dev, "Unsupported IPv6 protocol 0x%02x\n",
651 input->ipl4_proto);
652 return -EINVAL;
653 }
654 break;
655 default:
656 dev_info(&pf->pdev->dev, "Unsupported flow type 0x%02x\n",
657 input->flow_type);
658 return -EINVAL;
659 }
660
661 /* The buffer allocated here will be normally be freed by
662 * i40e_clean_fdir_tx_irq() as it reclaims resources after transmit
663 * completion. In the event of an error adding the buffer to the FDIR
664 * ring, it will immediately be freed. It may also be freed by
665 * i40e_clean_tx_ring() when closing the VSI.
666 */
667 return ret;
668}
669
670/**
671 * i40e_fd_handle_status - check the Programming Status for FD
672 * @rx_ring: the Rx ring for this descriptor
673 * @qword0_raw: qword0
674 * @qword1: qword1 after le_to_cpu
675 * @prog_id: the id originally used for programming
676 *
677 * This is used to verify if the FD programming or invalidation
678 * requested by SW to the HW is successful or not and take actions accordingly.
679 **/
680static void i40e_fd_handle_status(struct i40e_ring *rx_ring, u64 qword0_raw,
681 u64 qword1, u8 prog_id)
682{
683 struct i40e_pf *pf = rx_ring->vsi->back;
684 struct pci_dev *pdev = pf->pdev;
685 struct i40e_16b_rx_wb_qw0 *qw0;
686 u32 fcnt_prog, fcnt_avail;
687 u32 error;
688
689 qw0 = (struct i40e_16b_rx_wb_qw0 *)&qword0_raw;
690 error = FIELD_GET(I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK, qword1);
691
692 if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
693 pf->fd_inv = le32_to_cpu(qw0->hi_dword.fd_id);
694 if (qw0->hi_dword.fd_id != 0 ||
695 (I40E_DEBUG_FD & pf->hw.debug_mask))
696 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
697 pf->fd_inv);
698
699 /* Check if the programming error is for ATR.
700 * If so, auto disable ATR and set a state for
701 * flush in progress. Next time we come here if flush is in
702 * progress do nothing, once flush is complete the state will
703 * be cleared.
704 */
705 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
706 return;
707
708 pf->fd_add_err++;
709 /* store the current atr filter count */
710 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf);
711
712 if (qw0->hi_dword.fd_id == 0 &&
713 test_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state)) {
714 /* These set_bit() calls aren't atomic with the
715 * test_bit() here, but worse case we potentially
716 * disable ATR and queue a flush right after SB
717 * support is re-enabled. That shouldn't cause an
718 * issue in practice
719 */
720 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
721 set_bit(__I40E_FD_FLUSH_REQUESTED, pf->state);
722 }
723
724 /* filter programming failed most likely due to table full */
725 fcnt_prog = i40e_get_global_fd_count(pf);
726 fcnt_avail = pf->fdir_pf_filter_count;
727 /* If ATR is running fcnt_prog can quickly change,
728 * if we are very close to full, it makes sense to disable
729 * FD ATR/SB and then re-enable it when there is room.
730 */
731 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {
732 if (test_bit(I40E_FLAG_FD_SB_ENA, pf->flags) &&
733 !test_and_set_bit(__I40E_FD_SB_AUTO_DISABLED,
734 pf->state))
735 if (I40E_DEBUG_FD & pf->hw.debug_mask)
736 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n");
737 }
738 } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
739 if (I40E_DEBUG_FD & pf->hw.debug_mask)
740 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n",
741 qw0->hi_dword.fd_id);
742 }
743}
744
745/**
746 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
747 * @ring: the ring that owns the buffer
748 * @tx_buffer: the buffer to free
749 **/
750static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
751 struct i40e_tx_buffer *tx_buffer)
752{
753 if (tx_buffer->skb) {
754 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
755 kfree(tx_buffer->raw_buf);
756 else if (ring_is_xdp(ring))
757 xdp_return_frame(tx_buffer->xdpf);
758 else
759 dev_kfree_skb_any(tx_buffer->skb);
760 if (dma_unmap_len(tx_buffer, len))
761 dma_unmap_single(ring->dev,
762 dma_unmap_addr(tx_buffer, dma),
763 dma_unmap_len(tx_buffer, len),
764 DMA_TO_DEVICE);
765 } else if (dma_unmap_len(tx_buffer, len)) {
766 dma_unmap_page(ring->dev,
767 dma_unmap_addr(tx_buffer, dma),
768 dma_unmap_len(tx_buffer, len),
769 DMA_TO_DEVICE);
770 }
771
772 tx_buffer->next_to_watch = NULL;
773 tx_buffer->skb = NULL;
774 dma_unmap_len_set(tx_buffer, len, 0);
775 /* tx_buffer must be completely set up in the transmit path */
776}
777
778/**
779 * i40e_clean_tx_ring - Free any empty Tx buffers
780 * @tx_ring: ring to be cleaned
781 **/
782void i40e_clean_tx_ring(struct i40e_ring *tx_ring)
783{
784 unsigned long bi_size;
785 u16 i;
786
787 if (ring_is_xdp(tx_ring) && tx_ring->xsk_pool) {
788 i40e_xsk_clean_tx_ring(tx_ring);
789 } else {
790 /* ring already cleared, nothing to do */
791 if (!tx_ring->tx_bi)
792 return;
793
794 /* Free all the Tx ring sk_buffs */
795 for (i = 0; i < tx_ring->count; i++)
796 i40e_unmap_and_free_tx_resource(tx_ring,
797 &tx_ring->tx_bi[i]);
798 }
799
800 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
801 memset(tx_ring->tx_bi, 0, bi_size);
802
803 /* Zero out the descriptor ring */
804 memset(tx_ring->desc, 0, tx_ring->size);
805
806 tx_ring->next_to_use = 0;
807 tx_ring->next_to_clean = 0;
808
809 if (!tx_ring->netdev)
810 return;
811
812 /* cleanup Tx queue statistics */
813 netdev_tx_reset_queue(txring_txq(tx_ring));
814}
815
816/**
817 * i40e_free_tx_resources - Free Tx resources per queue
818 * @tx_ring: Tx descriptor ring for a specific queue
819 *
820 * Free all transmit software resources
821 **/
822void i40e_free_tx_resources(struct i40e_ring *tx_ring)
823{
824 i40e_clean_tx_ring(tx_ring);
825 kfree(tx_ring->tx_bi);
826 tx_ring->tx_bi = NULL;
827
828 if (tx_ring->desc) {
829 dma_free_coherent(tx_ring->dev, tx_ring->size,
830 tx_ring->desc, tx_ring->dma);
831 tx_ring->desc = NULL;
832 }
833}
834
835/**
836 * i40e_get_tx_pending - how many tx descriptors not processed
837 * @ring: the ring of descriptors
838 * @in_sw: use SW variables
839 *
840 * Since there is no access to the ring head register
841 * in XL710, we need to use our local copies
842 **/
843u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw)
844{
845 u32 head, tail;
846
847 if (!in_sw) {
848 head = i40e_get_head(ring);
849 tail = readl(ring->tail);
850 } else {
851 head = ring->next_to_clean;
852 tail = ring->next_to_use;
853 }
854
855 if (head != tail)
856 return (head < tail) ?
857 tail - head : (tail + ring->count - head);
858
859 return 0;
860}
861
862/**
863 * i40e_detect_recover_hung - Function to detect and recover hung_queues
864 * @pf: pointer to PF struct
865 *
866 * LAN VSI has netdev and netdev has TX queues. This function is to check
867 * each of those TX queues if they are hung, trigger recovery by issuing
868 * SW interrupt.
869 **/
870void i40e_detect_recover_hung(struct i40e_pf *pf)
871{
872 struct i40e_vsi *vsi = i40e_pf_get_main_vsi(pf);
873 struct i40e_ring *tx_ring = NULL;
874 struct net_device *netdev;
875 unsigned int i;
876 int packets;
877
878 if (!vsi)
879 return;
880
881 if (test_bit(__I40E_VSI_DOWN, vsi->state))
882 return;
883
884 netdev = vsi->netdev;
885 if (!netdev)
886 return;
887
888 if (!netif_carrier_ok(netdev))
889 return;
890
891 for (i = 0; i < vsi->num_queue_pairs; i++) {
892 tx_ring = vsi->tx_rings[i];
893 if (tx_ring && tx_ring->desc) {
894 /* If packet counter has not changed the queue is
895 * likely stalled, so force an interrupt for this
896 * queue.
897 *
898 * prev_pkt_ctr would be negative if there was no
899 * pending work.
900 */
901 packets = tx_ring->stats.packets & INT_MAX;
902 if (tx_ring->tx_stats.prev_pkt_ctr == packets) {
903 i40e_force_wb(vsi, tx_ring->q_vector);
904 continue;
905 }
906
907 /* Memory barrier between read of packet count and call
908 * to i40e_get_tx_pending()
909 */
910 smp_rmb();
911 tx_ring->tx_stats.prev_pkt_ctr =
912 i40e_get_tx_pending(tx_ring, true) ? packets : -1;
913 }
914 }
915}
916
917/**
918 * i40e_clean_tx_irq - Reclaim resources after transmit completes
919 * @vsi: the VSI we care about
920 * @tx_ring: Tx ring to clean
921 * @napi_budget: Used to determine if we are in netpoll
922 * @tx_cleaned: Out parameter set to the number of TXes cleaned
923 *
924 * Returns true if there's any budget left (e.g. the clean is finished)
925 **/
926static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,
927 struct i40e_ring *tx_ring, int napi_budget,
928 unsigned int *tx_cleaned)
929{
930 int i = tx_ring->next_to_clean;
931 struct i40e_tx_buffer *tx_buf;
932 struct i40e_tx_desc *tx_head;
933 struct i40e_tx_desc *tx_desc;
934 unsigned int total_bytes = 0, total_packets = 0;
935 unsigned int budget = vsi->work_limit;
936
937 tx_buf = &tx_ring->tx_bi[i];
938 tx_desc = I40E_TX_DESC(tx_ring, i);
939 i -= tx_ring->count;
940
941 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
942
943 do {
944 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
945
946 /* if next_to_watch is not set then there is no work pending */
947 if (!eop_desc)
948 break;
949
950 /* prevent any other reads prior to eop_desc */
951 smp_rmb();
952
953 i40e_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf);
954 /* we have caught up to head, no work left to do */
955 if (tx_head == tx_desc)
956 break;
957
958 /* clear next_to_watch to prevent false hangs */
959 tx_buf->next_to_watch = NULL;
960
961 /* update the statistics for this packet */
962 total_bytes += tx_buf->bytecount;
963 total_packets += tx_buf->gso_segs;
964
965 /* free the skb/XDP data */
966 if (ring_is_xdp(tx_ring))
967 xdp_return_frame(tx_buf->xdpf);
968 else
969 napi_consume_skb(tx_buf->skb, napi_budget);
970
971 /* unmap skb header data */
972 dma_unmap_single(tx_ring->dev,
973 dma_unmap_addr(tx_buf, dma),
974 dma_unmap_len(tx_buf, len),
975 DMA_TO_DEVICE);
976
977 /* clear tx_buffer data */
978 tx_buf->skb = NULL;
979 dma_unmap_len_set(tx_buf, len, 0);
980
981 /* unmap remaining buffers */
982 while (tx_desc != eop_desc) {
983 i40e_trace(clean_tx_irq_unmap,
984 tx_ring, tx_desc, tx_buf);
985
986 tx_buf++;
987 tx_desc++;
988 i++;
989 if (unlikely(!i)) {
990 i -= tx_ring->count;
991 tx_buf = tx_ring->tx_bi;
992 tx_desc = I40E_TX_DESC(tx_ring, 0);
993 }
994
995 /* unmap any remaining paged data */
996 if (dma_unmap_len(tx_buf, len)) {
997 dma_unmap_page(tx_ring->dev,
998 dma_unmap_addr(tx_buf, dma),
999 dma_unmap_len(tx_buf, len),
1000 DMA_TO_DEVICE);
1001 dma_unmap_len_set(tx_buf, len, 0);
1002 }
1003 }
1004
1005 /* move us one more past the eop_desc for start of next pkt */
1006 tx_buf++;
1007 tx_desc++;
1008 i++;
1009 if (unlikely(!i)) {
1010 i -= tx_ring->count;
1011 tx_buf = tx_ring->tx_bi;
1012 tx_desc = I40E_TX_DESC(tx_ring, 0);
1013 }
1014
1015 prefetch(tx_desc);
1016
1017 /* update budget accounting */
1018 budget--;
1019 } while (likely(budget));
1020
1021 i += tx_ring->count;
1022 tx_ring->next_to_clean = i;
1023 i40e_update_tx_stats(tx_ring, total_packets, total_bytes);
1024 i40e_arm_wb(tx_ring, vsi, budget);
1025
1026 if (ring_is_xdp(tx_ring))
1027 return !!budget;
1028
1029 /* notify netdev of completed buffers */
1030 netdev_tx_completed_queue(txring_txq(tx_ring),
1031 total_packets, total_bytes);
1032
1033#define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2))
1034 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1035 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
1036 /* Make sure that anybody stopping the queue after this
1037 * sees the new next_to_clean.
1038 */
1039 smp_mb();
1040 if (__netif_subqueue_stopped(tx_ring->netdev,
1041 tx_ring->queue_index) &&
1042 !test_bit(__I40E_VSI_DOWN, vsi->state)) {
1043 netif_wake_subqueue(tx_ring->netdev,
1044 tx_ring->queue_index);
1045 ++tx_ring->tx_stats.restart_queue;
1046 }
1047 }
1048
1049 *tx_cleaned = total_packets;
1050 return !!budget;
1051}
1052
1053/**
1054 * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
1055 * @vsi: the VSI we care about
1056 * @q_vector: the vector on which to enable writeback
1057 *
1058 **/
1059static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
1060 struct i40e_q_vector *q_vector)
1061{
1062 u16 flags = q_vector->tx.ring[0].flags;
1063 u32 val;
1064
1065 if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
1066 return;
1067
1068 if (q_vector->arm_wb_state)
1069 return;
1070
1071 if (test_bit(I40E_FLAG_MSIX_ENA, vsi->back->flags)) {
1072 val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK |
1073 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */
1074
1075 wr32(&vsi->back->hw,
1076 I40E_PFINT_DYN_CTLN(q_vector->reg_idx),
1077 val);
1078 } else {
1079 val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK |
1080 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */
1081
1082 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
1083 }
1084 q_vector->arm_wb_state = true;
1085}
1086
1087/**
1088 * i40e_force_wb - Issue SW Interrupt so HW does a wb
1089 * @vsi: the VSI we care about
1090 * @q_vector: the vector on which to force writeback
1091 *
1092 **/
1093void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
1094{
1095 if (test_bit(I40E_FLAG_MSIX_ENA, vsi->back->flags)) {
1096 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1097 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */
1098 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
1099 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
1100 /* allow 00 to be written to the index */
1101
1102 wr32(&vsi->back->hw,
1103 I40E_PFINT_DYN_CTLN(q_vector->reg_idx), val);
1104 } else {
1105 u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
1106 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */
1107 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
1108 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK;
1109 /* allow 00 to be written to the index */
1110
1111 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
1112 }
1113}
1114
1115static inline bool i40e_container_is_rx(struct i40e_q_vector *q_vector,
1116 struct i40e_ring_container *rc)
1117{
1118 return &q_vector->rx == rc;
1119}
1120
1121static inline unsigned int i40e_itr_divisor(struct i40e_q_vector *q_vector)
1122{
1123 unsigned int divisor;
1124
1125 switch (q_vector->vsi->back->hw.phy.link_info.link_speed) {
1126 case I40E_LINK_SPEED_40GB:
1127 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 1024;
1128 break;
1129 case I40E_LINK_SPEED_25GB:
1130 case I40E_LINK_SPEED_20GB:
1131 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 512;
1132 break;
1133 default:
1134 case I40E_LINK_SPEED_10GB:
1135 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 256;
1136 break;
1137 case I40E_LINK_SPEED_1GB:
1138 case I40E_LINK_SPEED_100MB:
1139 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 32;
1140 break;
1141 }
1142
1143 return divisor;
1144}
1145
1146/**
1147 * i40e_update_itr - update the dynamic ITR value based on statistics
1148 * @q_vector: structure containing interrupt and ring information
1149 * @rc: structure containing ring performance data
1150 *
1151 * Stores a new ITR value based on packets and byte
1152 * counts during the last interrupt. The advantage of per interrupt
1153 * computation is faster updates and more accurate ITR for the current
1154 * traffic pattern. Constants in this function were computed
1155 * based on theoretical maximum wire speed and thresholds were set based
1156 * on testing data as well as attempting to minimize response time
1157 * while increasing bulk throughput.
1158 **/
1159static void i40e_update_itr(struct i40e_q_vector *q_vector,
1160 struct i40e_ring_container *rc)
1161{
1162 unsigned int avg_wire_size, packets, bytes, itr;
1163 unsigned long next_update = jiffies;
1164
1165 /* If we don't have any rings just leave ourselves set for maximum
1166 * possible latency so we take ourselves out of the equation.
1167 */
1168 if (!rc->ring || !ITR_IS_DYNAMIC(rc->ring->itr_setting))
1169 return;
1170
1171 /* For Rx we want to push the delay up and default to low latency.
1172 * for Tx we want to pull the delay down and default to high latency.
1173 */
1174 itr = i40e_container_is_rx(q_vector, rc) ?
1175 I40E_ITR_ADAPTIVE_MIN_USECS | I40E_ITR_ADAPTIVE_LATENCY :
1176 I40E_ITR_ADAPTIVE_MAX_USECS | I40E_ITR_ADAPTIVE_LATENCY;
1177
1178 /* If we didn't update within up to 1 - 2 jiffies we can assume
1179 * that either packets are coming in so slow there hasn't been
1180 * any work, or that there is so much work that NAPI is dealing
1181 * with interrupt moderation and we don't need to do anything.
1182 */
1183 if (time_after(next_update, rc->next_update))
1184 goto clear_counts;
1185
1186 /* If itr_countdown is set it means we programmed an ITR within
1187 * the last 4 interrupt cycles. This has a side effect of us
1188 * potentially firing an early interrupt. In order to work around
1189 * this we need to throw out any data received for a few
1190 * interrupts following the update.
1191 */
1192 if (q_vector->itr_countdown) {
1193 itr = rc->target_itr;
1194 goto clear_counts;
1195 }
1196
1197 packets = rc->total_packets;
1198 bytes = rc->total_bytes;
1199
1200 if (i40e_container_is_rx(q_vector, rc)) {
1201 /* If Rx there are 1 to 4 packets and bytes are less than
1202 * 9000 assume insufficient data to use bulk rate limiting
1203 * approach unless Tx is already in bulk rate limiting. We
1204 * are likely latency driven.
1205 */
1206 if (packets && packets < 4 && bytes < 9000 &&
1207 (q_vector->tx.target_itr & I40E_ITR_ADAPTIVE_LATENCY)) {
1208 itr = I40E_ITR_ADAPTIVE_LATENCY;
1209 goto adjust_by_size;
1210 }
1211 } else if (packets < 4) {
1212 /* If we have Tx and Rx ITR maxed and Tx ITR is running in
1213 * bulk mode and we are receiving 4 or fewer packets just
1214 * reset the ITR_ADAPTIVE_LATENCY bit for latency mode so
1215 * that the Rx can relax.
1216 */
1217 if (rc->target_itr == I40E_ITR_ADAPTIVE_MAX_USECS &&
1218 (q_vector->rx.target_itr & I40E_ITR_MASK) ==
1219 I40E_ITR_ADAPTIVE_MAX_USECS)
1220 goto clear_counts;
1221 } else if (packets > 32) {
1222 /* If we have processed over 32 packets in a single interrupt
1223 * for Tx assume we need to switch over to "bulk" mode.
1224 */
1225 rc->target_itr &= ~I40E_ITR_ADAPTIVE_LATENCY;
1226 }
1227
1228 /* We have no packets to actually measure against. This means
1229 * either one of the other queues on this vector is active or
1230 * we are a Tx queue doing TSO with too high of an interrupt rate.
1231 *
1232 * Between 4 and 56 we can assume that our current interrupt delay
1233 * is only slightly too low. As such we should increase it by a small
1234 * fixed amount.
1235 */
1236 if (packets < 56) {
1237 itr = rc->target_itr + I40E_ITR_ADAPTIVE_MIN_INC;
1238 if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) {
1239 itr &= I40E_ITR_ADAPTIVE_LATENCY;
1240 itr += I40E_ITR_ADAPTIVE_MAX_USECS;
1241 }
1242 goto clear_counts;
1243 }
1244
1245 if (packets <= 256) {
1246 itr = min(q_vector->tx.current_itr, q_vector->rx.current_itr);
1247 itr &= I40E_ITR_MASK;
1248
1249 /* Between 56 and 112 is our "goldilocks" zone where we are
1250 * working out "just right". Just report that our current
1251 * ITR is good for us.
1252 */
1253 if (packets <= 112)
1254 goto clear_counts;
1255
1256 /* If packet count is 128 or greater we are likely looking
1257 * at a slight overrun of the delay we want. Try halving
1258 * our delay to see if that will cut the number of packets
1259 * in half per interrupt.
1260 */
1261 itr /= 2;
1262 itr &= I40E_ITR_MASK;
1263 if (itr < I40E_ITR_ADAPTIVE_MIN_USECS)
1264 itr = I40E_ITR_ADAPTIVE_MIN_USECS;
1265
1266 goto clear_counts;
1267 }
1268
1269 /* The paths below assume we are dealing with a bulk ITR since
1270 * number of packets is greater than 256. We are just going to have
1271 * to compute a value and try to bring the count under control,
1272 * though for smaller packet sizes there isn't much we can do as
1273 * NAPI polling will likely be kicking in sooner rather than later.
1274 */
1275 itr = I40E_ITR_ADAPTIVE_BULK;
1276
1277adjust_by_size:
1278 /* If packet counts are 256 or greater we can assume we have a gross
1279 * overestimation of what the rate should be. Instead of trying to fine
1280 * tune it just use the formula below to try and dial in an exact value
1281 * give the current packet size of the frame.
1282 */
1283 avg_wire_size = bytes / packets;
1284
1285 /* The following is a crude approximation of:
1286 * wmem_default / (size + overhead) = desired_pkts_per_int
1287 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate
1288 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
1289 *
1290 * Assuming wmem_default is 212992 and overhead is 640 bytes per
1291 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
1292 * formula down to
1293 *
1294 * (170 * (size + 24)) / (size + 640) = ITR
1295 *
1296 * We first do some math on the packet size and then finally bitshift
1297 * by 8 after rounding up. We also have to account for PCIe link speed
1298 * difference as ITR scales based on this.
1299 */
1300 if (avg_wire_size <= 60) {
1301 /* Start at 250k ints/sec */
1302 avg_wire_size = 4096;
1303 } else if (avg_wire_size <= 380) {
1304 /* 250K ints/sec to 60K ints/sec */
1305 avg_wire_size *= 40;
1306 avg_wire_size += 1696;
1307 } else if (avg_wire_size <= 1084) {
1308 /* 60K ints/sec to 36K ints/sec */
1309 avg_wire_size *= 15;
1310 avg_wire_size += 11452;
1311 } else if (avg_wire_size <= 1980) {
1312 /* 36K ints/sec to 30K ints/sec */
1313 avg_wire_size *= 5;
1314 avg_wire_size += 22420;
1315 } else {
1316 /* plateau at a limit of 30K ints/sec */
1317 avg_wire_size = 32256;
1318 }
1319
1320 /* If we are in low latency mode halve our delay which doubles the
1321 * rate to somewhere between 100K to 16K ints/sec
1322 */
1323 if (itr & I40E_ITR_ADAPTIVE_LATENCY)
1324 avg_wire_size /= 2;
1325
1326 /* Resultant value is 256 times larger than it needs to be. This
1327 * gives us room to adjust the value as needed to either increase
1328 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc.
1329 *
1330 * Use addition as we have already recorded the new latency flag
1331 * for the ITR value.
1332 */
1333 itr += DIV_ROUND_UP(avg_wire_size, i40e_itr_divisor(q_vector)) *
1334 I40E_ITR_ADAPTIVE_MIN_INC;
1335
1336 if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) {
1337 itr &= I40E_ITR_ADAPTIVE_LATENCY;
1338 itr += I40E_ITR_ADAPTIVE_MAX_USECS;
1339 }
1340
1341clear_counts:
1342 /* write back value */
1343 rc->target_itr = itr;
1344
1345 /* next update should occur within next jiffy */
1346 rc->next_update = next_update + 1;
1347
1348 rc->total_bytes = 0;
1349 rc->total_packets = 0;
1350}
1351
1352static struct i40e_rx_buffer *i40e_rx_bi(struct i40e_ring *rx_ring, u32 idx)
1353{
1354 return &rx_ring->rx_bi[idx];
1355}
1356
1357/**
1358 * i40e_reuse_rx_page - page flip buffer and store it back on the ring
1359 * @rx_ring: rx descriptor ring to store buffers on
1360 * @old_buff: donor buffer to have page reused
1361 *
1362 * Synchronizes page for reuse by the adapter
1363 **/
1364static void i40e_reuse_rx_page(struct i40e_ring *rx_ring,
1365 struct i40e_rx_buffer *old_buff)
1366{
1367 struct i40e_rx_buffer *new_buff;
1368 u16 nta = rx_ring->next_to_alloc;
1369
1370 new_buff = i40e_rx_bi(rx_ring, nta);
1371
1372 /* update, and store next to alloc */
1373 nta++;
1374 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1375
1376 /* transfer page from old buffer to new buffer */
1377 new_buff->dma = old_buff->dma;
1378 new_buff->page = old_buff->page;
1379 new_buff->page_offset = old_buff->page_offset;
1380 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
1381
1382 /* clear contents of buffer_info */
1383 old_buff->page = NULL;
1384}
1385
1386/**
1387 * i40e_clean_programming_status - clean the programming status descriptor
1388 * @rx_ring: the rx ring that has this descriptor
1389 * @qword0_raw: qword0
1390 * @qword1: qword1 representing status_error_len in CPU ordering
1391 *
1392 * Flow director should handle FD_FILTER_STATUS to check its filter programming
1393 * status being successful or not and take actions accordingly. FCoE should
1394 * handle its context/filter programming/invalidation status and take actions.
1395 *
1396 * Returns an i40e_rx_buffer to reuse if the cleanup occurred, otherwise NULL.
1397 **/
1398void i40e_clean_programming_status(struct i40e_ring *rx_ring, u64 qword0_raw,
1399 u64 qword1)
1400{
1401 u8 id;
1402
1403 id = FIELD_GET(I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK, qword1);
1404
1405 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)
1406 i40e_fd_handle_status(rx_ring, qword0_raw, qword1, id);
1407}
1408
1409/**
1410 * i40e_setup_tx_descriptors - Allocate the Tx descriptors
1411 * @tx_ring: the tx ring to set up
1412 *
1413 * Return 0 on success, negative on error
1414 **/
1415int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring)
1416{
1417 struct device *dev = tx_ring->dev;
1418 int bi_size;
1419
1420 if (!dev)
1421 return -ENOMEM;
1422
1423 /* warn if we are about to overwrite the pointer */
1424 WARN_ON(tx_ring->tx_bi);
1425 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
1426 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
1427 if (!tx_ring->tx_bi)
1428 goto err;
1429
1430 u64_stats_init(&tx_ring->syncp);
1431
1432 /* round up to nearest 4K */
1433 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
1434 /* add u32 for head writeback, align after this takes care of
1435 * guaranteeing this is at least one cache line in size
1436 */
1437 tx_ring->size += sizeof(u32);
1438 tx_ring->size = ALIGN(tx_ring->size, 4096);
1439 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1440 &tx_ring->dma, GFP_KERNEL);
1441 if (!tx_ring->desc) {
1442 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
1443 tx_ring->size);
1444 goto err;
1445 }
1446
1447 tx_ring->next_to_use = 0;
1448 tx_ring->next_to_clean = 0;
1449 tx_ring->tx_stats.prev_pkt_ctr = -1;
1450 return 0;
1451
1452err:
1453 kfree(tx_ring->tx_bi);
1454 tx_ring->tx_bi = NULL;
1455 return -ENOMEM;
1456}
1457
1458static void i40e_clear_rx_bi(struct i40e_ring *rx_ring)
1459{
1460 memset(rx_ring->rx_bi, 0, sizeof(*rx_ring->rx_bi) * rx_ring->count);
1461}
1462
1463/**
1464 * i40e_clean_rx_ring - Free Rx buffers
1465 * @rx_ring: ring to be cleaned
1466 **/
1467void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
1468{
1469 u16 i;
1470
1471 /* ring already cleared, nothing to do */
1472 if (!rx_ring->rx_bi)
1473 return;
1474
1475 if (rx_ring->xsk_pool) {
1476 i40e_xsk_clean_rx_ring(rx_ring);
1477 goto skip_free;
1478 }
1479
1480 /* Free all the Rx ring sk_buffs */
1481 for (i = 0; i < rx_ring->count; i++) {
1482 struct i40e_rx_buffer *rx_bi = i40e_rx_bi(rx_ring, i);
1483
1484 if (!rx_bi->page)
1485 continue;
1486
1487 /* Invalidate cache lines that may have been written to by
1488 * device so that we avoid corrupting memory.
1489 */
1490 dma_sync_single_range_for_cpu(rx_ring->dev,
1491 rx_bi->dma,
1492 rx_bi->page_offset,
1493 rx_ring->rx_buf_len,
1494 DMA_FROM_DEVICE);
1495
1496 /* free resources associated with mapping */
1497 dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma,
1498 i40e_rx_pg_size(rx_ring),
1499 DMA_FROM_DEVICE,
1500 I40E_RX_DMA_ATTR);
1501
1502 __page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias);
1503
1504 rx_bi->page = NULL;
1505 rx_bi->page_offset = 0;
1506 }
1507
1508skip_free:
1509 if (rx_ring->xsk_pool)
1510 i40e_clear_rx_bi_zc(rx_ring);
1511 else
1512 i40e_clear_rx_bi(rx_ring);
1513
1514 /* Zero out the descriptor ring */
1515 memset(rx_ring->desc, 0, rx_ring->size);
1516
1517 rx_ring->next_to_alloc = 0;
1518 rx_ring->next_to_clean = 0;
1519 rx_ring->next_to_process = 0;
1520 rx_ring->next_to_use = 0;
1521}
1522
1523/**
1524 * i40e_free_rx_resources - Free Rx resources
1525 * @rx_ring: ring to clean the resources from
1526 *
1527 * Free all receive software resources
1528 **/
1529void i40e_free_rx_resources(struct i40e_ring *rx_ring)
1530{
1531 i40e_clean_rx_ring(rx_ring);
1532 if (rx_ring->vsi->type == I40E_VSI_MAIN)
1533 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
1534 rx_ring->xdp_prog = NULL;
1535 kfree(rx_ring->rx_bi);
1536 rx_ring->rx_bi = NULL;
1537
1538 if (rx_ring->desc) {
1539 dma_free_coherent(rx_ring->dev, rx_ring->size,
1540 rx_ring->desc, rx_ring->dma);
1541 rx_ring->desc = NULL;
1542 }
1543}
1544
1545/**
1546 * i40e_setup_rx_descriptors - Allocate Rx descriptors
1547 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1548 *
1549 * Returns 0 on success, negative on failure
1550 **/
1551int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
1552{
1553 struct device *dev = rx_ring->dev;
1554
1555 u64_stats_init(&rx_ring->syncp);
1556
1557 /* Round up to nearest 4K */
1558 rx_ring->size = rx_ring->count * sizeof(union i40e_rx_desc);
1559 rx_ring->size = ALIGN(rx_ring->size, 4096);
1560 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1561 &rx_ring->dma, GFP_KERNEL);
1562
1563 if (!rx_ring->desc) {
1564 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
1565 rx_ring->size);
1566 return -ENOMEM;
1567 }
1568
1569 rx_ring->next_to_alloc = 0;
1570 rx_ring->next_to_clean = 0;
1571 rx_ring->next_to_process = 0;
1572 rx_ring->next_to_use = 0;
1573
1574 rx_ring->xdp_prog = rx_ring->vsi->xdp_prog;
1575
1576 rx_ring->rx_bi =
1577 kcalloc(rx_ring->count, sizeof(*rx_ring->rx_bi), GFP_KERNEL);
1578 if (!rx_ring->rx_bi)
1579 return -ENOMEM;
1580
1581 return 0;
1582}
1583
1584/**
1585 * i40e_release_rx_desc - Store the new tail and head values
1586 * @rx_ring: ring to bump
1587 * @val: new head index
1588 **/
1589void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
1590{
1591 rx_ring->next_to_use = val;
1592
1593 /* update next to alloc since we have filled the ring */
1594 rx_ring->next_to_alloc = val;
1595
1596 /* Force memory writes to complete before letting h/w
1597 * know there are new descriptors to fetch. (Only
1598 * applicable for weak-ordered memory model archs,
1599 * such as IA-64).
1600 */
1601 wmb();
1602 writel(val, rx_ring->tail);
1603}
1604
1605#if (PAGE_SIZE >= 8192)
1606static unsigned int i40e_rx_frame_truesize(struct i40e_ring *rx_ring,
1607 unsigned int size)
1608{
1609 unsigned int truesize;
1610
1611 truesize = rx_ring->rx_offset ?
1612 SKB_DATA_ALIGN(size + rx_ring->rx_offset) +
1613 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
1614 SKB_DATA_ALIGN(size);
1615 return truesize;
1616}
1617#endif
1618
1619/**
1620 * i40e_alloc_mapped_page - recycle or make a new page
1621 * @rx_ring: ring to use
1622 * @bi: rx_buffer struct to modify
1623 *
1624 * Returns true if the page was successfully allocated or
1625 * reused.
1626 **/
1627static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring,
1628 struct i40e_rx_buffer *bi)
1629{
1630 struct page *page = bi->page;
1631 dma_addr_t dma;
1632
1633 /* since we are recycling buffers we should seldom need to alloc */
1634 if (likely(page)) {
1635 rx_ring->rx_stats.page_reuse_count++;
1636 return true;
1637 }
1638
1639 /* alloc new page for storage */
1640 page = dev_alloc_pages(i40e_rx_pg_order(rx_ring));
1641 if (unlikely(!page)) {
1642 rx_ring->rx_stats.alloc_page_failed++;
1643 return false;
1644 }
1645
1646 rx_ring->rx_stats.page_alloc_count++;
1647
1648 /* map page for use */
1649 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1650 i40e_rx_pg_size(rx_ring),
1651 DMA_FROM_DEVICE,
1652 I40E_RX_DMA_ATTR);
1653
1654 /* if mapping failed free memory back to system since
1655 * there isn't much point in holding memory we can't use
1656 */
1657 if (dma_mapping_error(rx_ring->dev, dma)) {
1658 __free_pages(page, i40e_rx_pg_order(rx_ring));
1659 rx_ring->rx_stats.alloc_page_failed++;
1660 return false;
1661 }
1662
1663 bi->dma = dma;
1664 bi->page = page;
1665 bi->page_offset = rx_ring->rx_offset;
1666 page_ref_add(page, USHRT_MAX - 1);
1667 bi->pagecnt_bias = USHRT_MAX;
1668
1669 return true;
1670}
1671
1672/**
1673 * i40e_alloc_rx_buffers - Replace used receive buffers
1674 * @rx_ring: ring to place buffers on
1675 * @cleaned_count: number of buffers to replace
1676 *
1677 * Returns false if all allocations were successful, true if any fail
1678 **/
1679bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
1680{
1681 u16 ntu = rx_ring->next_to_use;
1682 union i40e_rx_desc *rx_desc;
1683 struct i40e_rx_buffer *bi;
1684
1685 /* do nothing if no valid netdev defined */
1686 if (!rx_ring->netdev || !cleaned_count)
1687 return false;
1688
1689 rx_desc = I40E_RX_DESC(rx_ring, ntu);
1690 bi = i40e_rx_bi(rx_ring, ntu);
1691
1692 do {
1693 if (!i40e_alloc_mapped_page(rx_ring, bi))
1694 goto no_buffers;
1695
1696 /* sync the buffer for use by the device */
1697 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
1698 bi->page_offset,
1699 rx_ring->rx_buf_len,
1700 DMA_FROM_DEVICE);
1701
1702 /* Refresh the desc even if buffer_addrs didn't change
1703 * because each write-back erases this info.
1704 */
1705 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1706
1707 rx_desc++;
1708 bi++;
1709 ntu++;
1710 if (unlikely(ntu == rx_ring->count)) {
1711 rx_desc = I40E_RX_DESC(rx_ring, 0);
1712 bi = i40e_rx_bi(rx_ring, 0);
1713 ntu = 0;
1714 }
1715
1716 /* clear the status bits for the next_to_use descriptor */
1717 rx_desc->wb.qword1.status_error_len = 0;
1718
1719 cleaned_count--;
1720 } while (cleaned_count);
1721
1722 if (rx_ring->next_to_use != ntu)
1723 i40e_release_rx_desc(rx_ring, ntu);
1724
1725 return false;
1726
1727no_buffers:
1728 if (rx_ring->next_to_use != ntu)
1729 i40e_release_rx_desc(rx_ring, ntu);
1730
1731 /* make sure to come back via polling to try again after
1732 * allocation failure
1733 */
1734 return true;
1735}
1736
1737/**
1738 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
1739 * @vsi: the VSI we care about
1740 * @skb: skb currently being received and modified
1741 * @rx_desc: the receive descriptor
1742 **/
1743static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
1744 struct sk_buff *skb,
1745 union i40e_rx_desc *rx_desc)
1746{
1747 struct libeth_rx_pt decoded;
1748 u32 rx_error, rx_status;
1749 bool ipv4, ipv6;
1750 u8 ptype;
1751 u64 qword;
1752
1753 skb->ip_summed = CHECKSUM_NONE;
1754
1755 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1756 ptype = FIELD_GET(I40E_RXD_QW1_PTYPE_MASK, qword);
1757
1758 decoded = libie_rx_pt_parse(ptype);
1759 if (!libeth_rx_pt_has_checksum(vsi->netdev, decoded))
1760 return;
1761
1762 rx_error = FIELD_GET(I40E_RXD_QW1_ERROR_MASK, qword);
1763 rx_status = FIELD_GET(I40E_RXD_QW1_STATUS_MASK, qword);
1764
1765 /* did the hardware decode the packet and checksum? */
1766 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
1767 return;
1768
1769 ipv4 = libeth_rx_pt_get_ip_ver(decoded) == LIBETH_RX_PT_OUTER_IPV4;
1770 ipv6 = libeth_rx_pt_get_ip_ver(decoded) == LIBETH_RX_PT_OUTER_IPV6;
1771
1772 if (ipv4 &&
1773 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
1774 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
1775 goto checksum_fail;
1776
1777 /* likely incorrect csum if alternate IP extension headers found */
1778 if (ipv6 &&
1779 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
1780 /* don't increment checksum err here, non-fatal err */
1781 return;
1782
1783 /* there was some L4 error, count error and punt packet to the stack */
1784 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
1785 goto checksum_fail;
1786
1787 /* handle packets that were not able to be checksummed due
1788 * to arrival speed, in this case the stack can compute
1789 * the csum.
1790 */
1791 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
1792 return;
1793
1794 /* If there is an outer header present that might contain a checksum
1795 * we need to bump the checksum level by 1 to reflect the fact that
1796 * we are indicating we validated the inner checksum.
1797 */
1798 if (decoded.tunnel_type >= LIBETH_RX_PT_TUNNEL_IP_GRENAT)
1799 skb->csum_level = 1;
1800
1801 skb->ip_summed = CHECKSUM_UNNECESSARY;
1802 return;
1803
1804checksum_fail:
1805 vsi->back->hw_csum_rx_error++;
1806}
1807
1808/**
1809 * i40e_rx_hash - set the hash value in the skb
1810 * @ring: descriptor ring
1811 * @rx_desc: specific descriptor
1812 * @skb: skb currently being received and modified
1813 * @rx_ptype: Rx packet type
1814 **/
1815static inline void i40e_rx_hash(struct i40e_ring *ring,
1816 union i40e_rx_desc *rx_desc,
1817 struct sk_buff *skb,
1818 u8 rx_ptype)
1819{
1820 struct libeth_rx_pt decoded;
1821 u32 hash;
1822 const __le64 rss_mask =
1823 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
1824 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
1825
1826 decoded = libie_rx_pt_parse(rx_ptype);
1827 if (!libeth_rx_pt_has_hash(ring->netdev, decoded))
1828 return;
1829
1830 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
1831 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
1832 libeth_rx_pt_set_hash(skb, hash, decoded);
1833 }
1834}
1835
1836/**
1837 * i40e_process_skb_fields - Populate skb header fields from Rx descriptor
1838 * @rx_ring: rx descriptor ring packet is being transacted on
1839 * @rx_desc: pointer to the EOP Rx descriptor
1840 * @skb: pointer to current skb being populated
1841 *
1842 * This function checks the ring, descriptor, and packet information in
1843 * order to populate the hash, checksum, VLAN, protocol, and
1844 * other fields within the skb.
1845 **/
1846void i40e_process_skb_fields(struct i40e_ring *rx_ring,
1847 union i40e_rx_desc *rx_desc, struct sk_buff *skb)
1848{
1849 u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1850 u32 rx_status = FIELD_GET(I40E_RXD_QW1_STATUS_MASK, qword);
1851 u32 tsynvalid = rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK;
1852 u32 tsyn = FIELD_GET(I40E_RXD_QW1_STATUS_TSYNINDX_MASK, rx_status);
1853 u8 rx_ptype = FIELD_GET(I40E_RXD_QW1_PTYPE_MASK, qword);
1854
1855 if (unlikely(tsynvalid))
1856 i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, tsyn);
1857
1858 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1859
1860 i40e_rx_checksum(rx_ring->vsi, skb, rx_desc);
1861
1862 skb_record_rx_queue(skb, rx_ring->queue_index);
1863
1864 if (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1865 __le16 vlan_tag = rx_desc->wb.qword0.lo_dword.l2tag1;
1866
1867 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1868 le16_to_cpu(vlan_tag));
1869 }
1870
1871 /* modifies the skb - consumes the enet header */
1872 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1873}
1874
1875/**
1876 * i40e_cleanup_headers - Correct empty headers
1877 * @rx_ring: rx descriptor ring packet is being transacted on
1878 * @skb: pointer to current skb being fixed
1879 * @rx_desc: pointer to the EOP Rx descriptor
1880 *
1881 * In addition if skb is not at least 60 bytes we need to pad it so that
1882 * it is large enough to qualify as a valid Ethernet frame.
1883 *
1884 * Returns true if an error was encountered and skb was freed.
1885 **/
1886static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb,
1887 union i40e_rx_desc *rx_desc)
1888
1889{
1890 /* ERR_MASK will only have valid bits if EOP set, and
1891 * what we are doing here is actually checking
1892 * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in
1893 * the error field
1894 */
1895 if (unlikely(i40e_test_staterr(rx_desc,
1896 BIT(I40E_RXD_QW1_ERROR_SHIFT)))) {
1897 dev_kfree_skb_any(skb);
1898 return true;
1899 }
1900
1901 /* if eth_skb_pad returns an error the skb was freed */
1902 if (eth_skb_pad(skb))
1903 return true;
1904
1905 return false;
1906}
1907
1908/**
1909 * i40e_can_reuse_rx_page - Determine if page can be reused for another Rx
1910 * @rx_buffer: buffer containing the page
1911 * @rx_stats: rx stats structure for the rx ring
1912 *
1913 * If page is reusable, we have a green light for calling i40e_reuse_rx_page,
1914 * which will assign the current buffer to the buffer that next_to_alloc is
1915 * pointing to; otherwise, the DMA mapping needs to be destroyed and
1916 * page freed.
1917 *
1918 * rx_stats will be updated to indicate whether the page was waived
1919 * or busy if it could not be reused.
1920 */
1921static bool i40e_can_reuse_rx_page(struct i40e_rx_buffer *rx_buffer,
1922 struct i40e_rx_queue_stats *rx_stats)
1923{
1924 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1925 struct page *page = rx_buffer->page;
1926
1927 /* Is any reuse possible? */
1928 if (!dev_page_is_reusable(page)) {
1929 rx_stats->page_waive_count++;
1930 return false;
1931 }
1932
1933#if (PAGE_SIZE < 8192)
1934 /* if we are only owner of page we can reuse it */
1935 if (unlikely((rx_buffer->page_count - pagecnt_bias) > 1)) {
1936 rx_stats->page_busy_count++;
1937 return false;
1938 }
1939#else
1940#define I40E_LAST_OFFSET \
1941 (SKB_WITH_OVERHEAD(PAGE_SIZE) - I40E_RXBUFFER_2048)
1942 if (rx_buffer->page_offset > I40E_LAST_OFFSET) {
1943 rx_stats->page_busy_count++;
1944 return false;
1945 }
1946#endif
1947
1948 /* If we have drained the page fragment pool we need to update
1949 * the pagecnt_bias and page count so that we fully restock the
1950 * number of references the driver holds.
1951 */
1952 if (unlikely(pagecnt_bias == 1)) {
1953 page_ref_add(page, USHRT_MAX - 1);
1954 rx_buffer->pagecnt_bias = USHRT_MAX;
1955 }
1956
1957 return true;
1958}
1959
1960/**
1961 * i40e_rx_buffer_flip - adjusted rx_buffer to point to an unused region
1962 * @rx_buffer: Rx buffer to adjust
1963 * @truesize: Size of adjustment
1964 **/
1965static void i40e_rx_buffer_flip(struct i40e_rx_buffer *rx_buffer,
1966 unsigned int truesize)
1967{
1968#if (PAGE_SIZE < 8192)
1969 rx_buffer->page_offset ^= truesize;
1970#else
1971 rx_buffer->page_offset += truesize;
1972#endif
1973}
1974
1975/**
1976 * i40e_get_rx_buffer - Fetch Rx buffer and synchronize data for use
1977 * @rx_ring: rx descriptor ring to transact packets on
1978 * @size: size of buffer to add to skb
1979 *
1980 * This function will pull an Rx buffer from the ring and synchronize it
1981 * for use by the CPU.
1982 */
1983static struct i40e_rx_buffer *i40e_get_rx_buffer(struct i40e_ring *rx_ring,
1984 const unsigned int size)
1985{
1986 struct i40e_rx_buffer *rx_buffer;
1987
1988 rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_process);
1989 rx_buffer->page_count =
1990#if (PAGE_SIZE < 8192)
1991 page_count(rx_buffer->page);
1992#else
1993 0;
1994#endif
1995 prefetch_page_address(rx_buffer->page);
1996
1997 /* we are reusing so sync this buffer for CPU use */
1998 dma_sync_single_range_for_cpu(rx_ring->dev,
1999 rx_buffer->dma,
2000 rx_buffer->page_offset,
2001 size,
2002 DMA_FROM_DEVICE);
2003
2004 /* We have pulled a buffer for use, so decrement pagecnt_bias */
2005 rx_buffer->pagecnt_bias--;
2006
2007 return rx_buffer;
2008}
2009
2010/**
2011 * i40e_put_rx_buffer - Clean up used buffer and either recycle or free
2012 * @rx_ring: rx descriptor ring to transact packets on
2013 * @rx_buffer: rx buffer to pull data from
2014 *
2015 * This function will clean up the contents of the rx_buffer. It will
2016 * either recycle the buffer or unmap it and free the associated resources.
2017 */
2018static void i40e_put_rx_buffer(struct i40e_ring *rx_ring,
2019 struct i40e_rx_buffer *rx_buffer)
2020{
2021 if (i40e_can_reuse_rx_page(rx_buffer, &rx_ring->rx_stats)) {
2022 /* hand second half of page back to the ring */
2023 i40e_reuse_rx_page(rx_ring, rx_buffer);
2024 } else {
2025 /* we are not reusing the buffer so unmap it */
2026 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
2027 i40e_rx_pg_size(rx_ring),
2028 DMA_FROM_DEVICE, I40E_RX_DMA_ATTR);
2029 __page_frag_cache_drain(rx_buffer->page,
2030 rx_buffer->pagecnt_bias);
2031 /* clear contents of buffer_info */
2032 rx_buffer->page = NULL;
2033 }
2034}
2035
2036/**
2037 * i40e_process_rx_buffs- Processing of buffers post XDP prog or on error
2038 * @rx_ring: Rx descriptor ring to transact packets on
2039 * @xdp_res: Result of the XDP program
2040 * @xdp: xdp_buff pointing to the data
2041 **/
2042static void i40e_process_rx_buffs(struct i40e_ring *rx_ring, int xdp_res,
2043 struct xdp_buff *xdp)
2044{
2045 u32 nr_frags = xdp_get_shared_info_from_buff(xdp)->nr_frags;
2046 u32 next = rx_ring->next_to_clean, i = 0;
2047 struct i40e_rx_buffer *rx_buffer;
2048
2049 xdp->flags = 0;
2050
2051 while (1) {
2052 rx_buffer = i40e_rx_bi(rx_ring, next);
2053 if (++next == rx_ring->count)
2054 next = 0;
2055
2056 if (!rx_buffer->page)
2057 continue;
2058
2059 if (xdp_res != I40E_XDP_CONSUMED)
2060 i40e_rx_buffer_flip(rx_buffer, xdp->frame_sz);
2061 else if (i++ <= nr_frags)
2062 rx_buffer->pagecnt_bias++;
2063
2064 /* EOP buffer will be put in i40e_clean_rx_irq() */
2065 if (next == rx_ring->next_to_process)
2066 return;
2067
2068 i40e_put_rx_buffer(rx_ring, rx_buffer);
2069 }
2070}
2071
2072/**
2073 * i40e_construct_skb - Allocate skb and populate it
2074 * @rx_ring: rx descriptor ring to transact packets on
2075 * @xdp: xdp_buff pointing to the data
2076 *
2077 * This function allocates an skb. It then populates it with the page
2078 * data from the current receive descriptor, taking care to set up the
2079 * skb correctly.
2080 */
2081static struct sk_buff *i40e_construct_skb(struct i40e_ring *rx_ring,
2082 struct xdp_buff *xdp)
2083{
2084 unsigned int size = xdp->data_end - xdp->data;
2085 struct i40e_rx_buffer *rx_buffer;
2086 struct skb_shared_info *sinfo;
2087 unsigned int headlen;
2088 struct sk_buff *skb;
2089 u32 nr_frags = 0;
2090
2091 /* prefetch first cache line of first page */
2092 net_prefetch(xdp->data);
2093
2094 /* Note, we get here by enabling legacy-rx via:
2095 *
2096 * ethtool --set-priv-flags <dev> legacy-rx on
2097 *
2098 * In this mode, we currently get 0 extra XDP headroom as
2099 * opposed to having legacy-rx off, where we process XDP
2100 * packets going to stack via i40e_build_skb(). The latter
2101 * provides us currently with 192 bytes of headroom.
2102 *
2103 * For i40e_construct_skb() mode it means that the
2104 * xdp->data_meta will always point to xdp->data, since
2105 * the helper cannot expand the head. Should this ever
2106 * change in future for legacy-rx mode on, then lets also
2107 * add xdp->data_meta handling here.
2108 */
2109
2110 /* allocate a skb to store the frags */
2111 skb = napi_alloc_skb(&rx_ring->q_vector->napi, I40E_RX_HDR_SIZE);
2112 if (unlikely(!skb))
2113 return NULL;
2114
2115 /* Determine available headroom for copy */
2116 headlen = size;
2117 if (headlen > I40E_RX_HDR_SIZE)
2118 headlen = eth_get_headlen(skb->dev, xdp->data,
2119 I40E_RX_HDR_SIZE);
2120
2121 /* align pull length to size of long to optimize memcpy performance */
2122 memcpy(__skb_put(skb, headlen), xdp->data,
2123 ALIGN(headlen, sizeof(long)));
2124
2125 if (unlikely(xdp_buff_has_frags(xdp))) {
2126 sinfo = xdp_get_shared_info_from_buff(xdp);
2127 nr_frags = sinfo->nr_frags;
2128 }
2129 rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_clean);
2130 /* update all of the pointers */
2131 size -= headlen;
2132 if (size) {
2133 if (unlikely(nr_frags >= MAX_SKB_FRAGS)) {
2134 dev_kfree_skb(skb);
2135 return NULL;
2136 }
2137 skb_add_rx_frag(skb, 0, rx_buffer->page,
2138 rx_buffer->page_offset + headlen,
2139 size, xdp->frame_sz);
2140 /* buffer is used by skb, update page_offset */
2141 i40e_rx_buffer_flip(rx_buffer, xdp->frame_sz);
2142 } else {
2143 /* buffer is unused, reset bias back to rx_buffer */
2144 rx_buffer->pagecnt_bias++;
2145 }
2146
2147 if (unlikely(xdp_buff_has_frags(xdp))) {
2148 struct skb_shared_info *skinfo = skb_shinfo(skb);
2149
2150 memcpy(&skinfo->frags[skinfo->nr_frags], &sinfo->frags[0],
2151 sizeof(skb_frag_t) * nr_frags);
2152
2153 xdp_update_skb_shared_info(skb, skinfo->nr_frags + nr_frags,
2154 sinfo->xdp_frags_size,
2155 nr_frags * xdp->frame_sz,
2156 xdp_buff_is_frag_pfmemalloc(xdp));
2157
2158 /* First buffer has already been processed, so bump ntc */
2159 if (++rx_ring->next_to_clean == rx_ring->count)
2160 rx_ring->next_to_clean = 0;
2161
2162 i40e_process_rx_buffs(rx_ring, I40E_XDP_PASS, xdp);
2163 }
2164
2165 return skb;
2166}
2167
2168/**
2169 * i40e_build_skb - Build skb around an existing buffer
2170 * @rx_ring: Rx descriptor ring to transact packets on
2171 * @xdp: xdp_buff pointing to the data
2172 *
2173 * This function builds an skb around an existing Rx buffer, taking care
2174 * to set up the skb correctly and avoid any memcpy overhead.
2175 */
2176static struct sk_buff *i40e_build_skb(struct i40e_ring *rx_ring,
2177 struct xdp_buff *xdp)
2178{
2179 unsigned int metasize = xdp->data - xdp->data_meta;
2180 struct skb_shared_info *sinfo;
2181 struct sk_buff *skb;
2182 u32 nr_frags;
2183
2184 /* Prefetch first cache line of first page. If xdp->data_meta
2185 * is unused, this points exactly as xdp->data, otherwise we
2186 * likely have a consumer accessing first few bytes of meta
2187 * data, and then actual data.
2188 */
2189 net_prefetch(xdp->data_meta);
2190
2191 if (unlikely(xdp_buff_has_frags(xdp))) {
2192 sinfo = xdp_get_shared_info_from_buff(xdp);
2193 nr_frags = sinfo->nr_frags;
2194 }
2195
2196 /* build an skb around the page buffer */
2197 skb = napi_build_skb(xdp->data_hard_start, xdp->frame_sz);
2198 if (unlikely(!skb))
2199 return NULL;
2200
2201 /* update pointers within the skb to store the data */
2202 skb_reserve(skb, xdp->data - xdp->data_hard_start);
2203 __skb_put(skb, xdp->data_end - xdp->data);
2204 if (metasize)
2205 skb_metadata_set(skb, metasize);
2206
2207 if (unlikely(xdp_buff_has_frags(xdp))) {
2208 xdp_update_skb_shared_info(skb, nr_frags,
2209 sinfo->xdp_frags_size,
2210 nr_frags * xdp->frame_sz,
2211 xdp_buff_is_frag_pfmemalloc(xdp));
2212
2213 i40e_process_rx_buffs(rx_ring, I40E_XDP_PASS, xdp);
2214 } else {
2215 struct i40e_rx_buffer *rx_buffer;
2216
2217 rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_clean);
2218 /* buffer is used by skb, update page_offset */
2219 i40e_rx_buffer_flip(rx_buffer, xdp->frame_sz);
2220 }
2221
2222 return skb;
2223}
2224
2225/**
2226 * i40e_is_non_eop - process handling of non-EOP buffers
2227 * @rx_ring: Rx ring being processed
2228 * @rx_desc: Rx descriptor for current buffer
2229 *
2230 * If the buffer is an EOP buffer, this function exits returning false,
2231 * otherwise return true indicating that this is in fact a non-EOP buffer.
2232 */
2233bool i40e_is_non_eop(struct i40e_ring *rx_ring,
2234 union i40e_rx_desc *rx_desc)
2235{
2236 /* if we are the last buffer then there is nothing else to do */
2237#define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)
2238 if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF)))
2239 return false;
2240
2241 rx_ring->rx_stats.non_eop_descs++;
2242
2243 return true;
2244}
2245
2246static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf,
2247 struct i40e_ring *xdp_ring);
2248
2249int i40e_xmit_xdp_tx_ring(struct xdp_buff *xdp, struct i40e_ring *xdp_ring)
2250{
2251 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
2252
2253 if (unlikely(!xdpf))
2254 return I40E_XDP_CONSUMED;
2255
2256 return i40e_xmit_xdp_ring(xdpf, xdp_ring);
2257}
2258
2259/**
2260 * i40e_run_xdp - run an XDP program
2261 * @rx_ring: Rx ring being processed
2262 * @xdp: XDP buffer containing the frame
2263 * @xdp_prog: XDP program to run
2264 **/
2265static int i40e_run_xdp(struct i40e_ring *rx_ring, struct xdp_buff *xdp, struct bpf_prog *xdp_prog)
2266{
2267 int err, result = I40E_XDP_PASS;
2268 struct i40e_ring *xdp_ring;
2269 u32 act;
2270
2271 if (!xdp_prog)
2272 goto xdp_out;
2273
2274 prefetchw(xdp->data_hard_start); /* xdp_frame write */
2275
2276 act = bpf_prog_run_xdp(xdp_prog, xdp);
2277 switch (act) {
2278 case XDP_PASS:
2279 break;
2280 case XDP_TX:
2281 xdp_ring = rx_ring->vsi->xdp_rings[rx_ring->queue_index];
2282 result = i40e_xmit_xdp_tx_ring(xdp, xdp_ring);
2283 if (result == I40E_XDP_CONSUMED)
2284 goto out_failure;
2285 break;
2286 case XDP_REDIRECT:
2287 err = xdp_do_redirect(rx_ring->netdev, xdp, xdp_prog);
2288 if (err)
2289 goto out_failure;
2290 result = I40E_XDP_REDIR;
2291 break;
2292 default:
2293 bpf_warn_invalid_xdp_action(rx_ring->netdev, xdp_prog, act);
2294 fallthrough;
2295 case XDP_ABORTED:
2296out_failure:
2297 trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
2298 fallthrough; /* handle aborts by dropping packet */
2299 case XDP_DROP:
2300 result = I40E_XDP_CONSUMED;
2301 break;
2302 }
2303xdp_out:
2304 return result;
2305}
2306
2307/**
2308 * i40e_xdp_ring_update_tail - Updates the XDP Tx ring tail register
2309 * @xdp_ring: XDP Tx ring
2310 *
2311 * This function updates the XDP Tx ring tail register.
2312 **/
2313void i40e_xdp_ring_update_tail(struct i40e_ring *xdp_ring)
2314{
2315 /* Force memory writes to complete before letting h/w
2316 * know there are new descriptors to fetch.
2317 */
2318 wmb();
2319 writel_relaxed(xdp_ring->next_to_use, xdp_ring->tail);
2320}
2321
2322/**
2323 * i40e_update_rx_stats - Update Rx ring statistics
2324 * @rx_ring: rx descriptor ring
2325 * @total_rx_bytes: number of bytes received
2326 * @total_rx_packets: number of packets received
2327 *
2328 * This function updates the Rx ring statistics.
2329 **/
2330void i40e_update_rx_stats(struct i40e_ring *rx_ring,
2331 unsigned int total_rx_bytes,
2332 unsigned int total_rx_packets)
2333{
2334 u64_stats_update_begin(&rx_ring->syncp);
2335 rx_ring->stats.packets += total_rx_packets;
2336 rx_ring->stats.bytes += total_rx_bytes;
2337 u64_stats_update_end(&rx_ring->syncp);
2338 rx_ring->q_vector->rx.total_packets += total_rx_packets;
2339 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
2340}
2341
2342/**
2343 * i40e_finalize_xdp_rx - Bump XDP Tx tail and/or flush redirect map
2344 * @rx_ring: Rx ring
2345 * @xdp_res: Result of the receive batch
2346 *
2347 * This function bumps XDP Tx tail and/or flush redirect map, and
2348 * should be called when a batch of packets has been processed in the
2349 * napi loop.
2350 **/
2351void i40e_finalize_xdp_rx(struct i40e_ring *rx_ring, unsigned int xdp_res)
2352{
2353 if (xdp_res & I40E_XDP_REDIR)
2354 xdp_do_flush();
2355
2356 if (xdp_res & I40E_XDP_TX) {
2357 struct i40e_ring *xdp_ring =
2358 rx_ring->vsi->xdp_rings[rx_ring->queue_index];
2359
2360 i40e_xdp_ring_update_tail(xdp_ring);
2361 }
2362}
2363
2364/**
2365 * i40e_inc_ntp: Advance the next_to_process index
2366 * @rx_ring: Rx ring
2367 **/
2368static void i40e_inc_ntp(struct i40e_ring *rx_ring)
2369{
2370 u32 ntp = rx_ring->next_to_process + 1;
2371
2372 ntp = (ntp < rx_ring->count) ? ntp : 0;
2373 rx_ring->next_to_process = ntp;
2374 prefetch(I40E_RX_DESC(rx_ring, ntp));
2375}
2376
2377/**
2378 * i40e_add_xdp_frag: Add a frag to xdp_buff
2379 * @xdp: xdp_buff pointing to the data
2380 * @nr_frags: return number of buffers for the packet
2381 * @rx_buffer: rx_buffer holding data of the current frag
2382 * @size: size of data of current frag
2383 */
2384static int i40e_add_xdp_frag(struct xdp_buff *xdp, u32 *nr_frags,
2385 struct i40e_rx_buffer *rx_buffer, u32 size)
2386{
2387 struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp);
2388
2389 if (!xdp_buff_has_frags(xdp)) {
2390 sinfo->nr_frags = 0;
2391 sinfo->xdp_frags_size = 0;
2392 xdp_buff_set_frags_flag(xdp);
2393 } else if (unlikely(sinfo->nr_frags >= MAX_SKB_FRAGS)) {
2394 /* Overflowing packet: All frags need to be dropped */
2395 return -ENOMEM;
2396 }
2397
2398 __skb_fill_page_desc_noacc(sinfo, sinfo->nr_frags++, rx_buffer->page,
2399 rx_buffer->page_offset, size);
2400
2401 sinfo->xdp_frags_size += size;
2402
2403 if (page_is_pfmemalloc(rx_buffer->page))
2404 xdp_buff_set_frag_pfmemalloc(xdp);
2405 *nr_frags = sinfo->nr_frags;
2406
2407 return 0;
2408}
2409
2410/**
2411 * i40e_consume_xdp_buff - Consume all the buffers of the packet and update ntc
2412 * @rx_ring: rx descriptor ring to transact packets on
2413 * @xdp: xdp_buff pointing to the data
2414 * @rx_buffer: rx_buffer of eop desc
2415 */
2416static void i40e_consume_xdp_buff(struct i40e_ring *rx_ring,
2417 struct xdp_buff *xdp,
2418 struct i40e_rx_buffer *rx_buffer)
2419{
2420 i40e_process_rx_buffs(rx_ring, I40E_XDP_CONSUMED, xdp);
2421 i40e_put_rx_buffer(rx_ring, rx_buffer);
2422 rx_ring->next_to_clean = rx_ring->next_to_process;
2423 xdp->data = NULL;
2424}
2425
2426/**
2427 * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2428 * @rx_ring: rx descriptor ring to transact packets on
2429 * @budget: Total limit on number of packets to process
2430 * @rx_cleaned: Out parameter of the number of packets processed
2431 *
2432 * This function provides a "bounce buffer" approach to Rx interrupt
2433 * processing. The advantage to this is that on systems that have
2434 * expensive overhead for IOMMU access this provides a means of avoiding
2435 * it by maintaining the mapping of the page to the system.
2436 *
2437 * Returns amount of work completed
2438 **/
2439static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget,
2440 unsigned int *rx_cleaned)
2441{
2442 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2443 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
2444 u16 clean_threshold = rx_ring->count / 2;
2445 unsigned int offset = rx_ring->rx_offset;
2446 struct xdp_buff *xdp = &rx_ring->xdp;
2447 unsigned int xdp_xmit = 0;
2448 struct bpf_prog *xdp_prog;
2449 bool failure = false;
2450 int xdp_res = 0;
2451
2452 xdp_prog = READ_ONCE(rx_ring->xdp_prog);
2453
2454 while (likely(total_rx_packets < (unsigned int)budget)) {
2455 u16 ntp = rx_ring->next_to_process;
2456 struct i40e_rx_buffer *rx_buffer;
2457 union i40e_rx_desc *rx_desc;
2458 struct sk_buff *skb;
2459 unsigned int size;
2460 u32 nfrags = 0;
2461 bool neop;
2462 u64 qword;
2463
2464 /* return some buffers to hardware, one at a time is too slow */
2465 if (cleaned_count >= clean_threshold) {
2466 failure = failure ||
2467 i40e_alloc_rx_buffers(rx_ring, cleaned_count);
2468 cleaned_count = 0;
2469 }
2470
2471 rx_desc = I40E_RX_DESC(rx_ring, ntp);
2472
2473 /* status_error_len will always be zero for unused descriptors
2474 * because it's cleared in cleanup, and overlaps with hdr_addr
2475 * which is always zero because packet split isn't used, if the
2476 * hardware wrote DD then the length will be non-zero
2477 */
2478 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
2479
2480 /* This memory barrier is needed to keep us from reading
2481 * any other fields out of the rx_desc until we have
2482 * verified the descriptor has been written back.
2483 */
2484 dma_rmb();
2485
2486 if (i40e_rx_is_programming_status(qword)) {
2487 i40e_clean_programming_status(rx_ring,
2488 rx_desc->raw.qword[0],
2489 qword);
2490 rx_buffer = i40e_rx_bi(rx_ring, ntp);
2491 i40e_inc_ntp(rx_ring);
2492 i40e_reuse_rx_page(rx_ring, rx_buffer);
2493 /* Update ntc and bump cleaned count if not in the
2494 * middle of mb packet.
2495 */
2496 if (rx_ring->next_to_clean == ntp) {
2497 rx_ring->next_to_clean =
2498 rx_ring->next_to_process;
2499 cleaned_count++;
2500 }
2501 continue;
2502 }
2503
2504 size = FIELD_GET(I40E_RXD_QW1_LENGTH_PBUF_MASK, qword);
2505 if (!size)
2506 break;
2507
2508 i40e_trace(clean_rx_irq, rx_ring, rx_desc, xdp);
2509 /* retrieve a buffer from the ring */
2510 rx_buffer = i40e_get_rx_buffer(rx_ring, size);
2511
2512 neop = i40e_is_non_eop(rx_ring, rx_desc);
2513 i40e_inc_ntp(rx_ring);
2514
2515 if (!xdp->data) {
2516 unsigned char *hard_start;
2517
2518 hard_start = page_address(rx_buffer->page) +
2519 rx_buffer->page_offset - offset;
2520 xdp_prepare_buff(xdp, hard_start, offset, size, true);
2521#if (PAGE_SIZE > 4096)
2522 /* At larger PAGE_SIZE, frame_sz depend on len size */
2523 xdp->frame_sz = i40e_rx_frame_truesize(rx_ring, size);
2524#endif
2525 } else if (i40e_add_xdp_frag(xdp, &nfrags, rx_buffer, size) &&
2526 !neop) {
2527 /* Overflowing packet: Drop all frags on EOP */
2528 i40e_consume_xdp_buff(rx_ring, xdp, rx_buffer);
2529 break;
2530 }
2531
2532 if (neop)
2533 continue;
2534
2535 xdp_res = i40e_run_xdp(rx_ring, xdp, xdp_prog);
2536
2537 if (xdp_res) {
2538 xdp_xmit |= xdp_res & (I40E_XDP_TX | I40E_XDP_REDIR);
2539
2540 if (unlikely(xdp_buff_has_frags(xdp))) {
2541 i40e_process_rx_buffs(rx_ring, xdp_res, xdp);
2542 size = xdp_get_buff_len(xdp);
2543 } else if (xdp_res & (I40E_XDP_TX | I40E_XDP_REDIR)) {
2544 i40e_rx_buffer_flip(rx_buffer, xdp->frame_sz);
2545 } else {
2546 rx_buffer->pagecnt_bias++;
2547 }
2548 total_rx_bytes += size;
2549 } else {
2550 if (ring_uses_build_skb(rx_ring))
2551 skb = i40e_build_skb(rx_ring, xdp);
2552 else
2553 skb = i40e_construct_skb(rx_ring, xdp);
2554
2555 /* drop if we failed to retrieve a buffer */
2556 if (!skb) {
2557 rx_ring->rx_stats.alloc_buff_failed++;
2558 i40e_consume_xdp_buff(rx_ring, xdp, rx_buffer);
2559 break;
2560 }
2561
2562 if (i40e_cleanup_headers(rx_ring, skb, rx_desc))
2563 goto process_next;
2564
2565 /* probably a little skewed due to removing CRC */
2566 total_rx_bytes += skb->len;
2567
2568 /* populate checksum, VLAN, and protocol */
2569 i40e_process_skb_fields(rx_ring, rx_desc, skb);
2570
2571 i40e_trace(clean_rx_irq_rx, rx_ring, rx_desc, xdp);
2572 napi_gro_receive(&rx_ring->q_vector->napi, skb);
2573 }
2574
2575 /* update budget accounting */
2576 total_rx_packets++;
2577process_next:
2578 cleaned_count += nfrags + 1;
2579 i40e_put_rx_buffer(rx_ring, rx_buffer);
2580 rx_ring->next_to_clean = rx_ring->next_to_process;
2581
2582 xdp->data = NULL;
2583 }
2584
2585 i40e_finalize_xdp_rx(rx_ring, xdp_xmit);
2586
2587 i40e_update_rx_stats(rx_ring, total_rx_bytes, total_rx_packets);
2588
2589 *rx_cleaned = total_rx_packets;
2590
2591 /* guarantee a trip back through this routine if there was a failure */
2592 return failure ? budget : (int)total_rx_packets;
2593}
2594
2595/**
2596 * i40e_buildreg_itr - build a value for writing to I40E_PFINT_DYN_CTLN register
2597 * @itr_idx: interrupt throttling index
2598 * @interval: interrupt throttling interval value in usecs
2599 * @force_swint: force software interrupt
2600 *
2601 * The function builds a value for I40E_PFINT_DYN_CTLN register that
2602 * is used to update interrupt throttling interval for specified ITR index
2603 * and optionally enforces a software interrupt. If the @itr_idx is equal
2604 * to I40E_ITR_NONE then no interval change is applied and only @force_swint
2605 * parameter is taken into account. If the interval change and enforced
2606 * software interrupt are not requested then the built value just enables
2607 * appropriate vector interrupt.
2608 **/
2609static u32 i40e_buildreg_itr(enum i40e_dyn_idx itr_idx, u16 interval,
2610 bool force_swint)
2611{
2612 u32 val;
2613
2614 /* We don't bother with setting the CLEARPBA bit as the data sheet
2615 * points out doing so is "meaningless since it was already
2616 * auto-cleared". The auto-clearing happens when the interrupt is
2617 * asserted.
2618 *
2619 * Hardware errata 28 for also indicates that writing to a
2620 * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear
2621 * an event in the PBA anyway so we need to rely on the automask
2622 * to hold pending events for us until the interrupt is re-enabled
2623 *
2624 * We have to shift the given value as it is reported in microseconds
2625 * and the register value is recorded in 2 microsecond units.
2626 */
2627 interval >>= 1;
2628
2629 /* 1. Enable vector interrupt
2630 * 2. Update the interval for the specified ITR index
2631 * (I40E_ITR_NONE in the register is used to indicate that
2632 * no interval update is requested)
2633 */
2634 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2635 FIELD_PREP(I40E_PFINT_DYN_CTLN_ITR_INDX_MASK, itr_idx) |
2636 FIELD_PREP(I40E_PFINT_DYN_CTLN_INTERVAL_MASK, interval);
2637
2638 /* 3. Enforce software interrupt trigger if requested
2639 * (These software interrupts rate is limited by ITR2 that is
2640 * set to 20K interrupts per second)
2641 */
2642 if (force_swint)
2643 val |= I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
2644 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK |
2645 FIELD_PREP(I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK,
2646 I40E_SW_ITR);
2647
2648 return val;
2649}
2650
2651/* The act of updating the ITR will cause it to immediately trigger. In order
2652 * to prevent this from throwing off adaptive update statistics we defer the
2653 * update so that it can only happen so often. So after either Tx or Rx are
2654 * updated we make the adaptive scheme wait until either the ITR completely
2655 * expires via the next_update expiration or we have been through at least
2656 * 3 interrupts.
2657 */
2658#define ITR_COUNTDOWN_START 3
2659
2660/**
2661 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
2662 * @vsi: the VSI we care about
2663 * @q_vector: q_vector for which itr is being updated and interrupt enabled
2664 *
2665 **/
2666static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
2667 struct i40e_q_vector *q_vector)
2668{
2669 enum i40e_dyn_idx itr_idx = I40E_ITR_NONE;
2670 struct i40e_hw *hw = &vsi->back->hw;
2671 u16 interval = 0;
2672 u32 itr_val;
2673
2674 /* If we don't have MSIX, then we only need to re-enable icr0 */
2675 if (!test_bit(I40E_FLAG_MSIX_ENA, vsi->back->flags)) {
2676 i40e_irq_dynamic_enable_icr0(vsi->back);
2677 return;
2678 }
2679
2680 /* These will do nothing if dynamic updates are not enabled */
2681 i40e_update_itr(q_vector, &q_vector->tx);
2682 i40e_update_itr(q_vector, &q_vector->rx);
2683
2684 /* This block of logic allows us to get away with only updating
2685 * one ITR value with each interrupt. The idea is to perform a
2686 * pseudo-lazy update with the following criteria.
2687 *
2688 * 1. Rx is given higher priority than Tx if both are in same state
2689 * 2. If we must reduce an ITR that is given highest priority.
2690 * 3. We then give priority to increasing ITR based on amount.
2691 */
2692 if (q_vector->rx.target_itr < q_vector->rx.current_itr) {
2693 /* Rx ITR needs to be reduced, this is highest priority */
2694 itr_idx = I40E_RX_ITR;
2695 interval = q_vector->rx.target_itr;
2696 q_vector->rx.current_itr = q_vector->rx.target_itr;
2697 q_vector->itr_countdown = ITR_COUNTDOWN_START;
2698 } else if ((q_vector->tx.target_itr < q_vector->tx.current_itr) ||
2699 ((q_vector->rx.target_itr - q_vector->rx.current_itr) <
2700 (q_vector->tx.target_itr - q_vector->tx.current_itr))) {
2701 /* Tx ITR needs to be reduced, this is second priority
2702 * Tx ITR needs to be increased more than Rx, fourth priority
2703 */
2704 itr_idx = I40E_TX_ITR;
2705 interval = q_vector->tx.target_itr;
2706 q_vector->tx.current_itr = q_vector->tx.target_itr;
2707 q_vector->itr_countdown = ITR_COUNTDOWN_START;
2708 } else if (q_vector->rx.current_itr != q_vector->rx.target_itr) {
2709 /* Rx ITR needs to be increased, third priority */
2710 itr_idx = I40E_RX_ITR;
2711 interval = q_vector->rx.target_itr;
2712 q_vector->rx.current_itr = q_vector->rx.target_itr;
2713 q_vector->itr_countdown = ITR_COUNTDOWN_START;
2714 } else {
2715 /* No ITR update, lowest priority */
2716 if (q_vector->itr_countdown)
2717 q_vector->itr_countdown--;
2718 }
2719
2720 /* Do not update interrupt control register if VSI is down */
2721 if (test_bit(__I40E_VSI_DOWN, vsi->state))
2722 return;
2723
2724 /* Update ITR interval if necessary and enforce software interrupt
2725 * if we are exiting busy poll.
2726 */
2727 if (q_vector->in_busy_poll) {
2728 itr_val = i40e_buildreg_itr(itr_idx, interval, true);
2729 q_vector->in_busy_poll = false;
2730 } else {
2731 itr_val = i40e_buildreg_itr(itr_idx, interval, false);
2732 }
2733 wr32(hw, I40E_PFINT_DYN_CTLN(q_vector->reg_idx), itr_val);
2734}
2735
2736/**
2737 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine
2738 * @napi: napi struct with our devices info in it
2739 * @budget: amount of work driver is allowed to do this pass, in packets
2740 *
2741 * This function will clean all queues associated with a q_vector.
2742 *
2743 * Returns the amount of work done
2744 **/
2745int i40e_napi_poll(struct napi_struct *napi, int budget)
2746{
2747 struct i40e_q_vector *q_vector =
2748 container_of(napi, struct i40e_q_vector, napi);
2749 struct i40e_vsi *vsi = q_vector->vsi;
2750 struct i40e_ring *ring;
2751 bool tx_clean_complete = true;
2752 bool rx_clean_complete = true;
2753 unsigned int tx_cleaned = 0;
2754 unsigned int rx_cleaned = 0;
2755 bool clean_complete = true;
2756 bool arm_wb = false;
2757 int budget_per_ring;
2758 int work_done = 0;
2759
2760 if (test_bit(__I40E_VSI_DOWN, vsi->state)) {
2761 napi_complete(napi);
2762 return 0;
2763 }
2764
2765 /* Since the actual Tx work is minimal, we can give the Tx a larger
2766 * budget and be more aggressive about cleaning up the Tx descriptors.
2767 */
2768 i40e_for_each_ring(ring, q_vector->tx) {
2769 bool wd = ring->xsk_pool ?
2770 i40e_clean_xdp_tx_irq(vsi, ring) :
2771 i40e_clean_tx_irq(vsi, ring, budget, &tx_cleaned);
2772
2773 if (!wd) {
2774 clean_complete = tx_clean_complete = false;
2775 continue;
2776 }
2777 arm_wb |= ring->arm_wb;
2778 ring->arm_wb = false;
2779 }
2780
2781 /* Handle case where we are called by netpoll with a budget of 0 */
2782 if (budget <= 0)
2783 goto tx_only;
2784
2785 /* normally we have 1 Rx ring per q_vector */
2786 if (unlikely(q_vector->num_ringpairs > 1))
2787 /* We attempt to distribute budget to each Rx queue fairly, but
2788 * don't allow the budget to go below 1 because that would exit
2789 * polling early.
2790 */
2791 budget_per_ring = max_t(int, budget / q_vector->num_ringpairs, 1);
2792 else
2793 /* Max of 1 Rx ring in this q_vector so give it the budget */
2794 budget_per_ring = budget;
2795
2796 i40e_for_each_ring(ring, q_vector->rx) {
2797 int cleaned = ring->xsk_pool ?
2798 i40e_clean_rx_irq_zc(ring, budget_per_ring) :
2799 i40e_clean_rx_irq(ring, budget_per_ring, &rx_cleaned);
2800
2801 work_done += cleaned;
2802 /* if we clean as many as budgeted, we must not be done */
2803 if (cleaned >= budget_per_ring)
2804 clean_complete = rx_clean_complete = false;
2805 }
2806
2807 if (!i40e_enabled_xdp_vsi(vsi))
2808 trace_i40e_napi_poll(napi, q_vector, budget, budget_per_ring, rx_cleaned,
2809 tx_cleaned, rx_clean_complete, tx_clean_complete);
2810
2811 /* If work not completed, return budget and polling will return */
2812 if (!clean_complete) {
2813 int cpu_id = smp_processor_id();
2814
2815 /* It is possible that the interrupt affinity has changed but,
2816 * if the cpu is pegged at 100%, polling will never exit while
2817 * traffic continues and the interrupt will be stuck on this
2818 * cpu. We check to make sure affinity is correct before we
2819 * continue to poll, otherwise we must stop polling so the
2820 * interrupt can move to the correct cpu.
2821 */
2822 if (!cpumask_test_cpu(cpu_id, &q_vector->affinity_mask)) {
2823 /* Tell napi that we are done polling */
2824 napi_complete_done(napi, work_done);
2825
2826 /* Force an interrupt */
2827 i40e_force_wb(vsi, q_vector);
2828
2829 /* Return budget-1 so that polling stops */
2830 return budget - 1;
2831 }
2832tx_only:
2833 if (arm_wb) {
2834 q_vector->tx.ring[0].tx_stats.tx_force_wb++;
2835 i40e_enable_wb_on_itr(vsi, q_vector);
2836 }
2837 return budget;
2838 }
2839
2840 if (q_vector->tx.ring[0].flags & I40E_TXR_FLAGS_WB_ON_ITR)
2841 q_vector->arm_wb_state = false;
2842
2843 /* Exit the polling mode, but don't re-enable interrupts if stack might
2844 * poll us due to busy-polling
2845 */
2846 if (likely(napi_complete_done(napi, work_done)))
2847 i40e_update_enable_itr(vsi, q_vector);
2848 else
2849 q_vector->in_busy_poll = true;
2850
2851 return min(work_done, budget - 1);
2852}
2853
2854/**
2855 * i40e_atr - Add a Flow Director ATR filter
2856 * @tx_ring: ring to add programming descriptor to
2857 * @skb: send buffer
2858 * @tx_flags: send tx flags
2859 **/
2860static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,
2861 u32 tx_flags)
2862{
2863 struct i40e_filter_program_desc *fdir_desc;
2864 struct i40e_pf *pf = tx_ring->vsi->back;
2865 union {
2866 unsigned char *network;
2867 struct iphdr *ipv4;
2868 struct ipv6hdr *ipv6;
2869 } hdr;
2870 struct tcphdr *th;
2871 unsigned int hlen;
2872 u32 flex_ptype, dtype_cmd;
2873 int l4_proto;
2874 u16 i;
2875
2876 /* make sure ATR is enabled */
2877 if (!test_bit(I40E_FLAG_FD_ATR_ENA, pf->flags))
2878 return;
2879
2880 if (test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state))
2881 return;
2882
2883 /* if sampling is disabled do nothing */
2884 if (!tx_ring->atr_sample_rate)
2885 return;
2886
2887 /* Currently only IPv4/IPv6 with TCP is supported */
2888 if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6)))
2889 return;
2890
2891 /* snag network header to get L4 type and address */
2892 hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ?
2893 skb_inner_network_header(skb) : skb_network_header(skb);
2894
2895 /* Note: tx_flags gets modified to reflect inner protocols in
2896 * tx_enable_csum function if encap is enabled.
2897 */
2898 if (tx_flags & I40E_TX_FLAGS_IPV4) {
2899 /* access ihl as u8 to avoid unaligned access on ia64 */
2900 hlen = (hdr.network[0] & 0x0F) << 2;
2901 l4_proto = hdr.ipv4->protocol;
2902 } else {
2903 /* find the start of the innermost ipv6 header */
2904 unsigned int inner_hlen = hdr.network - skb->data;
2905 unsigned int h_offset = inner_hlen;
2906
2907 /* this function updates h_offset to the end of the header */
2908 l4_proto =
2909 ipv6_find_hdr(skb, &h_offset, IPPROTO_TCP, NULL, NULL);
2910 /* hlen will contain our best estimate of the tcp header */
2911 hlen = h_offset - inner_hlen;
2912 }
2913
2914 if (l4_proto != IPPROTO_TCP)
2915 return;
2916
2917 th = (struct tcphdr *)(hdr.network + hlen);
2918
2919 /* Due to lack of space, no more new filters can be programmed */
2920 if (th->syn && test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state))
2921 return;
2922 if (test_bit(I40E_FLAG_HW_ATR_EVICT_ENA, pf->flags)) {
2923 /* HW ATR eviction will take care of removing filters on FIN
2924 * and RST packets.
2925 */
2926 if (th->fin || th->rst)
2927 return;
2928 }
2929
2930 tx_ring->atr_count++;
2931
2932 /* sample on all syn/fin/rst packets or once every atr sample rate */
2933 if (!th->fin &&
2934 !th->syn &&
2935 !th->rst &&
2936 (tx_ring->atr_count < tx_ring->atr_sample_rate))
2937 return;
2938
2939 tx_ring->atr_count = 0;
2940
2941 /* grab the next descriptor */
2942 i = tx_ring->next_to_use;
2943 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
2944
2945 i++;
2946 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2947
2948 flex_ptype = FIELD_PREP(I40E_TXD_FLTR_QW0_QINDEX_MASK,
2949 tx_ring->queue_index);
2950 flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ?
2951 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP <<
2952 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :
2953 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP <<
2954 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
2955
2956 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
2957
2958 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
2959
2960 dtype_cmd |= (th->fin || th->rst) ?
2961 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
2962 I40E_TXD_FLTR_QW1_PCMD_SHIFT) :
2963 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
2964 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
2965
2966 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX <<
2967 I40E_TXD_FLTR_QW1_DEST_SHIFT;
2968
2969 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID <<
2970 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT;
2971
2972 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
2973 if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL))
2974 dtype_cmd |=
2975 FIELD_PREP(I40E_TXD_FLTR_QW1_CNTINDEX_MASK,
2976 I40E_FD_ATR_STAT_IDX(pf->hw.pf_id));
2977 else
2978 dtype_cmd |=
2979 FIELD_PREP(I40E_TXD_FLTR_QW1_CNTINDEX_MASK,
2980 I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id));
2981
2982 if (test_bit(I40E_FLAG_HW_ATR_EVICT_ENA, pf->flags))
2983 dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK;
2984
2985 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
2986 fdir_desc->rsvd = cpu_to_le32(0);
2987 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
2988 fdir_desc->fd_id = cpu_to_le32(0);
2989}
2990
2991/**
2992 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
2993 * @skb: send buffer
2994 * @tx_ring: ring to send buffer on
2995 * @flags: the tx flags to be set
2996 *
2997 * Checks the skb and set up correspondingly several generic transmit flags
2998 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
2999 *
3000 * Returns error code indicate the frame should be dropped upon error and the
3001 * otherwise returns 0 to indicate the flags has been set properly.
3002 **/
3003static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
3004 struct i40e_ring *tx_ring,
3005 u32 *flags)
3006{
3007 __be16 protocol = skb->protocol;
3008 u32 tx_flags = 0;
3009
3010 if (protocol == htons(ETH_P_8021Q) &&
3011 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
3012 /* When HW VLAN acceleration is turned off by the user the
3013 * stack sets the protocol to 8021q so that the driver
3014 * can take any steps required to support the SW only
3015 * VLAN handling. In our case the driver doesn't need
3016 * to take any further steps so just set the protocol
3017 * to the encapsulated ethertype.
3018 */
3019 skb->protocol = vlan_get_protocol(skb);
3020 goto out;
3021 }
3022
3023 /* if we have a HW VLAN tag being added, default to the HW one */
3024 if (skb_vlan_tag_present(skb)) {
3025 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
3026 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
3027 /* else if it is a SW VLAN, check the next protocol and store the tag */
3028 } else if (protocol == htons(ETH_P_8021Q)) {
3029 struct vlan_hdr *vhdr, _vhdr;
3030
3031 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
3032 if (!vhdr)
3033 return -EINVAL;
3034
3035 protocol = vhdr->h_vlan_encapsulated_proto;
3036 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
3037 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
3038 }
3039
3040 if (!test_bit(I40E_FLAG_DCB_ENA, tx_ring->vsi->back->flags))
3041 goto out;
3042
3043 /* Insert 802.1p priority into VLAN header */
3044 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) ||
3045 (skb->priority != TC_PRIO_CONTROL)) {
3046 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK;
3047 tx_flags |= (skb->priority & 0x7) <<
3048 I40E_TX_FLAGS_VLAN_PRIO_SHIFT;
3049 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) {
3050 struct vlan_ethhdr *vhdr;
3051 int rc;
3052
3053 rc = skb_cow_head(skb, 0);
3054 if (rc < 0)
3055 return rc;
3056 vhdr = skb_vlan_eth_hdr(skb);
3057 vhdr->h_vlan_TCI = htons(tx_flags >>
3058 I40E_TX_FLAGS_VLAN_SHIFT);
3059 } else {
3060 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
3061 }
3062 }
3063
3064out:
3065 *flags = tx_flags;
3066 return 0;
3067}
3068
3069/**
3070 * i40e_tso - set up the tso context descriptor
3071 * @first: pointer to first Tx buffer for xmit
3072 * @hdr_len: ptr to the size of the packet header
3073 * @cd_type_cmd_tso_mss: Quad Word 1
3074 *
3075 * Returns 0 if no TSO can happen, 1 if tso is going, or error
3076 **/
3077static int i40e_tso(struct i40e_tx_buffer *first, u8 *hdr_len,
3078 u64 *cd_type_cmd_tso_mss)
3079{
3080 struct sk_buff *skb = first->skb;
3081 u64 cd_cmd, cd_tso_len, cd_mss;
3082 __be16 protocol;
3083 union {
3084 struct iphdr *v4;
3085 struct ipv6hdr *v6;
3086 unsigned char *hdr;
3087 } ip;
3088 union {
3089 struct tcphdr *tcp;
3090 struct udphdr *udp;
3091 unsigned char *hdr;
3092 } l4;
3093 u32 paylen, l4_offset;
3094 u16 gso_size;
3095 int err;
3096
3097 if (skb->ip_summed != CHECKSUM_PARTIAL)
3098 return 0;
3099
3100 if (!skb_is_gso(skb))
3101 return 0;
3102
3103 err = skb_cow_head(skb, 0);
3104 if (err < 0)
3105 return err;
3106
3107 protocol = vlan_get_protocol(skb);
3108
3109 if (eth_p_mpls(protocol))
3110 ip.hdr = skb_inner_network_header(skb);
3111 else
3112 ip.hdr = skb_network_header(skb);
3113 l4.hdr = skb_checksum_start(skb);
3114
3115 /* initialize outer IP header fields */
3116 if (ip.v4->version == 4) {
3117 ip.v4->tot_len = 0;
3118 ip.v4->check = 0;
3119
3120 first->tx_flags |= I40E_TX_FLAGS_TSO;
3121 } else {
3122 ip.v6->payload_len = 0;
3123 first->tx_flags |= I40E_TX_FLAGS_TSO;
3124 }
3125
3126 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
3127 SKB_GSO_GRE_CSUM |
3128 SKB_GSO_IPXIP4 |
3129 SKB_GSO_IPXIP6 |
3130 SKB_GSO_UDP_TUNNEL |
3131 SKB_GSO_UDP_TUNNEL_CSUM)) {
3132 if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
3133 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) {
3134 l4.udp->len = 0;
3135
3136 /* determine offset of outer transport header */
3137 l4_offset = l4.hdr - skb->data;
3138
3139 /* remove payload length from outer checksum */
3140 paylen = skb->len - l4_offset;
3141 csum_replace_by_diff(&l4.udp->check,
3142 (__force __wsum)htonl(paylen));
3143 }
3144
3145 /* reset pointers to inner headers */
3146 ip.hdr = skb_inner_network_header(skb);
3147 l4.hdr = skb_inner_transport_header(skb);
3148
3149 /* initialize inner IP header fields */
3150 if (ip.v4->version == 4) {
3151 ip.v4->tot_len = 0;
3152 ip.v4->check = 0;
3153 } else {
3154 ip.v6->payload_len = 0;
3155 }
3156 }
3157
3158 /* determine offset of inner transport header */
3159 l4_offset = l4.hdr - skb->data;
3160
3161 /* remove payload length from inner checksum */
3162 paylen = skb->len - l4_offset;
3163
3164 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
3165 csum_replace_by_diff(&l4.udp->check, (__force __wsum)htonl(paylen));
3166 /* compute length of segmentation header */
3167 *hdr_len = sizeof(*l4.udp) + l4_offset;
3168 } else {
3169 csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen));
3170 /* compute length of segmentation header */
3171 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
3172 }
3173
3174 /* pull values out of skb_shinfo */
3175 gso_size = skb_shinfo(skb)->gso_size;
3176
3177 /* update GSO size and bytecount with header size */
3178 first->gso_segs = skb_shinfo(skb)->gso_segs;
3179 first->bytecount += (first->gso_segs - 1) * *hdr_len;
3180
3181 /* find the field values */
3182 cd_cmd = I40E_TX_CTX_DESC_TSO;
3183 cd_tso_len = skb->len - *hdr_len;
3184 cd_mss = gso_size;
3185 *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
3186 (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
3187 (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
3188 return 1;
3189}
3190
3191/**
3192 * i40e_tsyn - set up the tsyn context descriptor
3193 * @tx_ring: ptr to the ring to send
3194 * @skb: ptr to the skb we're sending
3195 * @tx_flags: the collected send information
3196 * @cd_type_cmd_tso_mss: Quad Word 1
3197 *
3198 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen
3199 **/
3200static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb,
3201 u32 tx_flags, u64 *cd_type_cmd_tso_mss)
3202{
3203 struct i40e_pf *pf;
3204
3205 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
3206 return 0;
3207
3208 /* Tx timestamps cannot be sampled when doing TSO */
3209 if (tx_flags & I40E_TX_FLAGS_TSO)
3210 return 0;
3211
3212 /* only timestamp the outbound packet if the user has requested it and
3213 * we are not already transmitting a packet to be timestamped
3214 */
3215 pf = i40e_netdev_to_pf(tx_ring->netdev);
3216 if (!test_bit(I40E_FLAG_PTP_ENA, pf->flags))
3217 return 0;
3218
3219 if (pf->ptp_tx &&
3220 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, pf->state)) {
3221 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3222 pf->ptp_tx_start = jiffies;
3223 pf->ptp_tx_skb = skb_get(skb);
3224 } else {
3225 pf->tx_hwtstamp_skipped++;
3226 return 0;
3227 }
3228
3229 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN <<
3230 I40E_TXD_CTX_QW1_CMD_SHIFT;
3231
3232 return 1;
3233}
3234
3235/**
3236 * i40e_tx_enable_csum - Enable Tx checksum offloads
3237 * @skb: send buffer
3238 * @tx_flags: pointer to Tx flags currently set
3239 * @td_cmd: Tx descriptor command bits to set
3240 * @td_offset: Tx descriptor header offsets to set
3241 * @tx_ring: Tx descriptor ring
3242 * @cd_tunneling: ptr to context desc bits
3243 **/
3244static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
3245 u32 *td_cmd, u32 *td_offset,
3246 struct i40e_ring *tx_ring,
3247 u32 *cd_tunneling)
3248{
3249 union {
3250 struct iphdr *v4;
3251 struct ipv6hdr *v6;
3252 unsigned char *hdr;
3253 } ip;
3254 union {
3255 struct tcphdr *tcp;
3256 struct udphdr *udp;
3257 unsigned char *hdr;
3258 } l4;
3259 unsigned char *exthdr;
3260 u32 offset, cmd = 0;
3261 __be16 frag_off;
3262 __be16 protocol;
3263 u8 l4_proto = 0;
3264
3265 if (skb->ip_summed != CHECKSUM_PARTIAL)
3266 return 0;
3267
3268 protocol = vlan_get_protocol(skb);
3269
3270 if (eth_p_mpls(protocol)) {
3271 ip.hdr = skb_inner_network_header(skb);
3272 l4.hdr = skb_checksum_start(skb);
3273 } else {
3274 ip.hdr = skb_network_header(skb);
3275 l4.hdr = skb_transport_header(skb);
3276 }
3277
3278 /* set the tx_flags to indicate the IP protocol type. this is
3279 * required so that checksum header computation below is accurate.
3280 */
3281 if (ip.v4->version == 4)
3282 *tx_flags |= I40E_TX_FLAGS_IPV4;
3283 else
3284 *tx_flags |= I40E_TX_FLAGS_IPV6;
3285
3286 /* compute outer L2 header size */
3287 offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
3288
3289 if (skb->encapsulation) {
3290 u32 tunnel = 0;
3291 /* define outer network header type */
3292 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
3293 tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
3294 I40E_TX_CTX_EXT_IP_IPV4 :
3295 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
3296
3297 l4_proto = ip.v4->protocol;
3298 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
3299 int ret;
3300
3301 tunnel |= I40E_TX_CTX_EXT_IP_IPV6;
3302
3303 exthdr = ip.hdr + sizeof(*ip.v6);
3304 l4_proto = ip.v6->nexthdr;
3305 ret = ipv6_skip_exthdr(skb, exthdr - skb->data,
3306 &l4_proto, &frag_off);
3307 if (ret < 0)
3308 return -1;
3309 }
3310
3311 /* define outer transport */
3312 switch (l4_proto) {
3313 case IPPROTO_UDP:
3314 tunnel |= I40E_TXD_CTX_UDP_TUNNELING;
3315 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3316 break;
3317 case IPPROTO_GRE:
3318 tunnel |= I40E_TXD_CTX_GRE_TUNNELING;
3319 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3320 break;
3321 case IPPROTO_IPIP:
3322 case IPPROTO_IPV6:
3323 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3324 l4.hdr = skb_inner_network_header(skb);
3325 break;
3326 default:
3327 if (*tx_flags & I40E_TX_FLAGS_TSO)
3328 return -1;
3329
3330 skb_checksum_help(skb);
3331 return 0;
3332 }
3333
3334 /* compute outer L3 header size */
3335 tunnel |= ((l4.hdr - ip.hdr) / 4) <<
3336 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
3337
3338 /* switch IP header pointer from outer to inner header */
3339 ip.hdr = skb_inner_network_header(skb);
3340
3341 /* compute tunnel header size */
3342 tunnel |= ((ip.hdr - l4.hdr) / 2) <<
3343 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
3344
3345 /* indicate if we need to offload outer UDP header */
3346 if ((*tx_flags & I40E_TX_FLAGS_TSO) &&
3347 !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
3348 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM))
3349 tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
3350
3351 /* record tunnel offload values */
3352 *cd_tunneling |= tunnel;
3353
3354 /* switch L4 header pointer from outer to inner */
3355 l4.hdr = skb_inner_transport_header(skb);
3356 l4_proto = 0;
3357
3358 /* reset type as we transition from outer to inner headers */
3359 *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6);
3360 if (ip.v4->version == 4)
3361 *tx_flags |= I40E_TX_FLAGS_IPV4;
3362 if (ip.v6->version == 6)
3363 *tx_flags |= I40E_TX_FLAGS_IPV6;
3364 }
3365
3366 /* Enable IP checksum offloads */
3367 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
3368 l4_proto = ip.v4->protocol;
3369 /* the stack computes the IP header already, the only time we
3370 * need the hardware to recompute it is in the case of TSO.
3371 */
3372 cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
3373 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM :
3374 I40E_TX_DESC_CMD_IIPT_IPV4;
3375 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
3376 cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
3377
3378 exthdr = ip.hdr + sizeof(*ip.v6);
3379 l4_proto = ip.v6->nexthdr;
3380 if (l4.hdr != exthdr)
3381 ipv6_skip_exthdr(skb, exthdr - skb->data,
3382 &l4_proto, &frag_off);
3383 }
3384
3385 /* compute inner L3 header size */
3386 offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
3387
3388 /* Enable L4 checksum offloads */
3389 switch (l4_proto) {
3390 case IPPROTO_TCP:
3391 /* enable checksum offloads */
3392 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
3393 offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3394 break;
3395 case IPPROTO_SCTP:
3396 /* enable SCTP checksum offload */
3397 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
3398 offset |= (sizeof(struct sctphdr) >> 2) <<
3399 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3400 break;
3401 case IPPROTO_UDP:
3402 /* enable UDP checksum offload */
3403 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
3404 offset |= (sizeof(struct udphdr) >> 2) <<
3405 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3406 break;
3407 default:
3408 if (*tx_flags & I40E_TX_FLAGS_TSO)
3409 return -1;
3410 skb_checksum_help(skb);
3411 return 0;
3412 }
3413
3414 *td_cmd |= cmd;
3415 *td_offset |= offset;
3416
3417 return 1;
3418}
3419
3420/**
3421 * i40e_create_tx_ctx - Build the Tx context descriptor
3422 * @tx_ring: ring to create the descriptor on
3423 * @cd_type_cmd_tso_mss: Quad Word 1
3424 * @cd_tunneling: Quad Word 0 - bits 0-31
3425 * @cd_l2tag2: Quad Word 0 - bits 32-63
3426 **/
3427static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
3428 const u64 cd_type_cmd_tso_mss,
3429 const u32 cd_tunneling, const u32 cd_l2tag2)
3430{
3431 struct i40e_tx_context_desc *context_desc;
3432 int i = tx_ring->next_to_use;
3433
3434 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
3435 !cd_tunneling && !cd_l2tag2)
3436 return;
3437
3438 /* grab the next descriptor */
3439 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
3440
3441 i++;
3442 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
3443
3444 /* cpu_to_le32 and assign to struct fields */
3445 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
3446 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
3447 context_desc->rsvd = cpu_to_le16(0);
3448 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
3449}
3450
3451/**
3452 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
3453 * @tx_ring: the ring to be checked
3454 * @size: the size buffer we want to assure is available
3455 *
3456 * Returns -EBUSY if a stop is needed, else 0
3457 **/
3458int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
3459{
3460 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
3461 /* Memory barrier before checking head and tail */
3462 smp_mb();
3463
3464 ++tx_ring->tx_stats.tx_stopped;
3465
3466 /* Check again in a case another CPU has just made room available. */
3467 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
3468 return -EBUSY;
3469
3470 /* A reprieve! - use start_queue because it doesn't call schedule */
3471 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
3472 ++tx_ring->tx_stats.restart_queue;
3473 return 0;
3474}
3475
3476/**
3477 * __i40e_chk_linearize - Check if there are more than 8 buffers per packet
3478 * @skb: send buffer
3479 *
3480 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire
3481 * and so we need to figure out the cases where we need to linearize the skb.
3482 *
3483 * For TSO we need to count the TSO header and segment payload separately.
3484 * As such we need to check cases where we have 7 fragments or more as we
3485 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
3486 * the segment payload in the first descriptor, and another 7 for the
3487 * fragments.
3488 **/
3489bool __i40e_chk_linearize(struct sk_buff *skb)
3490{
3491 const skb_frag_t *frag, *stale;
3492 int nr_frags, sum;
3493
3494 /* no need to check if number of frags is less than 7 */
3495 nr_frags = skb_shinfo(skb)->nr_frags;
3496 if (nr_frags < (I40E_MAX_BUFFER_TXD - 1))
3497 return false;
3498
3499 /* We need to walk through the list and validate that each group
3500 * of 6 fragments totals at least gso_size.
3501 */
3502 nr_frags -= I40E_MAX_BUFFER_TXD - 2;
3503 frag = &skb_shinfo(skb)->frags[0];
3504
3505 /* Initialize size to the negative value of gso_size minus 1. We
3506 * use this as the worst case scenerio in which the frag ahead
3507 * of us only provides one byte which is why we are limited to 6
3508 * descriptors for a single transmit as the header and previous
3509 * fragment are already consuming 2 descriptors.
3510 */
3511 sum = 1 - skb_shinfo(skb)->gso_size;
3512
3513 /* Add size of frags 0 through 4 to create our initial sum */
3514 sum += skb_frag_size(frag++);
3515 sum += skb_frag_size(frag++);
3516 sum += skb_frag_size(frag++);
3517 sum += skb_frag_size(frag++);
3518 sum += skb_frag_size(frag++);
3519
3520 /* Walk through fragments adding latest fragment, testing it, and
3521 * then removing stale fragments from the sum.
3522 */
3523 for (stale = &skb_shinfo(skb)->frags[0];; stale++) {
3524 int stale_size = skb_frag_size(stale);
3525
3526 sum += skb_frag_size(frag++);
3527
3528 /* The stale fragment may present us with a smaller
3529 * descriptor than the actual fragment size. To account
3530 * for that we need to remove all the data on the front and
3531 * figure out what the remainder would be in the last
3532 * descriptor associated with the fragment.
3533 */
3534 if (stale_size > I40E_MAX_DATA_PER_TXD) {
3535 int align_pad = -(skb_frag_off(stale)) &
3536 (I40E_MAX_READ_REQ_SIZE - 1);
3537
3538 sum -= align_pad;
3539 stale_size -= align_pad;
3540
3541 do {
3542 sum -= I40E_MAX_DATA_PER_TXD_ALIGNED;
3543 stale_size -= I40E_MAX_DATA_PER_TXD_ALIGNED;
3544 } while (stale_size > I40E_MAX_DATA_PER_TXD);
3545 }
3546
3547 /* if sum is negative we failed to make sufficient progress */
3548 if (sum < 0)
3549 return true;
3550
3551 if (!nr_frags--)
3552 break;
3553
3554 sum -= stale_size;
3555 }
3556
3557 return false;
3558}
3559
3560/**
3561 * i40e_tx_map - Build the Tx descriptor
3562 * @tx_ring: ring to send buffer on
3563 * @skb: send buffer
3564 * @first: first buffer info buffer to use
3565 * @tx_flags: collected send information
3566 * @hdr_len: size of the packet header
3567 * @td_cmd: the command field in the descriptor
3568 * @td_offset: offset for checksum or crc
3569 *
3570 * Returns 0 on success, -1 on failure to DMA
3571 **/
3572static inline int i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
3573 struct i40e_tx_buffer *first, u32 tx_flags,
3574 const u8 hdr_len, u32 td_cmd, u32 td_offset)
3575{
3576 unsigned int data_len = skb->data_len;
3577 unsigned int size = skb_headlen(skb);
3578 skb_frag_t *frag;
3579 struct i40e_tx_buffer *tx_bi;
3580 struct i40e_tx_desc *tx_desc;
3581 u16 i = tx_ring->next_to_use;
3582 u32 td_tag = 0;
3583 dma_addr_t dma;
3584 u16 desc_count = 1;
3585
3586 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
3587 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
3588 td_tag = FIELD_GET(I40E_TX_FLAGS_VLAN_MASK, tx_flags);
3589 }
3590
3591 first->tx_flags = tx_flags;
3592
3593 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
3594
3595 tx_desc = I40E_TX_DESC(tx_ring, i);
3596 tx_bi = first;
3597
3598 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
3599 unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
3600
3601 if (dma_mapping_error(tx_ring->dev, dma))
3602 goto dma_error;
3603
3604 /* record length, and DMA address */
3605 dma_unmap_len_set(tx_bi, len, size);
3606 dma_unmap_addr_set(tx_bi, dma, dma);
3607
3608 /* align size to end of page */
3609 max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1);
3610 tx_desc->buffer_addr = cpu_to_le64(dma);
3611
3612 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
3613 tx_desc->cmd_type_offset_bsz =
3614 build_ctob(td_cmd, td_offset,
3615 max_data, td_tag);
3616
3617 tx_desc++;
3618 i++;
3619 desc_count++;
3620
3621 if (i == tx_ring->count) {
3622 tx_desc = I40E_TX_DESC(tx_ring, 0);
3623 i = 0;
3624 }
3625
3626 dma += max_data;
3627 size -= max_data;
3628
3629 max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
3630 tx_desc->buffer_addr = cpu_to_le64(dma);
3631 }
3632
3633 if (likely(!data_len))
3634 break;
3635
3636 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
3637 size, td_tag);
3638
3639 tx_desc++;
3640 i++;
3641 desc_count++;
3642
3643 if (i == tx_ring->count) {
3644 tx_desc = I40E_TX_DESC(tx_ring, 0);
3645 i = 0;
3646 }
3647
3648 size = skb_frag_size(frag);
3649 data_len -= size;
3650
3651 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
3652 DMA_TO_DEVICE);
3653
3654 tx_bi = &tx_ring->tx_bi[i];
3655 }
3656
3657 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
3658
3659 i++;
3660 if (i == tx_ring->count)
3661 i = 0;
3662
3663 tx_ring->next_to_use = i;
3664
3665 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
3666
3667 /* write last descriptor with EOP bit */
3668 td_cmd |= I40E_TX_DESC_CMD_EOP;
3669
3670 /* We OR these values together to check both against 4 (WB_STRIDE)
3671 * below. This is safe since we don't re-use desc_count afterwards.
3672 */
3673 desc_count |= ++tx_ring->packet_stride;
3674
3675 if (desc_count >= WB_STRIDE) {
3676 /* write last descriptor with RS bit set */
3677 td_cmd |= I40E_TX_DESC_CMD_RS;
3678 tx_ring->packet_stride = 0;
3679 }
3680
3681 tx_desc->cmd_type_offset_bsz =
3682 build_ctob(td_cmd, td_offset, size, td_tag);
3683
3684 skb_tx_timestamp(skb);
3685
3686 /* Force memory writes to complete before letting h/w know there
3687 * are new descriptors to fetch.
3688 *
3689 * We also use this memory barrier to make certain all of the
3690 * status bits have been updated before next_to_watch is written.
3691 */
3692 wmb();
3693
3694 /* set next_to_watch value indicating a packet is present */
3695 first->next_to_watch = tx_desc;
3696
3697 /* notify HW of packet */
3698 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
3699 writel(i, tx_ring->tail);
3700 }
3701
3702 return 0;
3703
3704dma_error:
3705 dev_info(tx_ring->dev, "TX DMA map failed\n");
3706
3707 /* clear dma mappings for failed tx_bi map */
3708 for (;;) {
3709 tx_bi = &tx_ring->tx_bi[i];
3710 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
3711 if (tx_bi == first)
3712 break;
3713 if (i == 0)
3714 i = tx_ring->count;
3715 i--;
3716 }
3717
3718 tx_ring->next_to_use = i;
3719
3720 return -1;
3721}
3722
3723static u16 i40e_swdcb_skb_tx_hash(struct net_device *dev,
3724 const struct sk_buff *skb,
3725 u16 num_tx_queues)
3726{
3727 u32 jhash_initval_salt = 0xd631614b;
3728 u32 hash;
3729
3730 if (skb->sk && skb->sk->sk_hash)
3731 hash = skb->sk->sk_hash;
3732 else
3733 hash = (__force u16)skb->protocol ^ skb->hash;
3734
3735 hash = jhash_1word(hash, jhash_initval_salt);
3736
3737 return (u16)(((u64)hash * num_tx_queues) >> 32);
3738}
3739
3740u16 i40e_lan_select_queue(struct net_device *netdev,
3741 struct sk_buff *skb,
3742 struct net_device __always_unused *sb_dev)
3743{
3744 struct i40e_netdev_priv *np = netdev_priv(netdev);
3745 struct i40e_vsi *vsi = np->vsi;
3746 struct i40e_hw *hw;
3747 u16 qoffset;
3748 u16 qcount;
3749 u8 tclass;
3750 u16 hash;
3751 u8 prio;
3752
3753 /* is DCB enabled at all? */
3754 if (vsi->tc_config.numtc == 1 ||
3755 i40e_is_tc_mqprio_enabled(vsi->back))
3756 return netdev_pick_tx(netdev, skb, sb_dev);
3757
3758 prio = skb->priority;
3759 hw = &vsi->back->hw;
3760 tclass = hw->local_dcbx_config.etscfg.prioritytable[prio];
3761 /* sanity check */
3762 if (unlikely(!(vsi->tc_config.enabled_tc & BIT(tclass))))
3763 tclass = 0;
3764
3765 /* select a queue assigned for the given TC */
3766 qcount = vsi->tc_config.tc_info[tclass].qcount;
3767 hash = i40e_swdcb_skb_tx_hash(netdev, skb, qcount);
3768
3769 qoffset = vsi->tc_config.tc_info[tclass].qoffset;
3770 return qoffset + hash;
3771}
3772
3773/**
3774 * i40e_xmit_xdp_ring - transmits an XDP buffer to an XDP Tx ring
3775 * @xdpf: data to transmit
3776 * @xdp_ring: XDP Tx ring
3777 **/
3778static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf,
3779 struct i40e_ring *xdp_ring)
3780{
3781 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf);
3782 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0;
3783 u16 i = 0, index = xdp_ring->next_to_use;
3784 struct i40e_tx_buffer *tx_head = &xdp_ring->tx_bi[index];
3785 struct i40e_tx_buffer *tx_bi = tx_head;
3786 struct i40e_tx_desc *tx_desc = I40E_TX_DESC(xdp_ring, index);
3787 void *data = xdpf->data;
3788 u32 size = xdpf->len;
3789
3790 if (unlikely(I40E_DESC_UNUSED(xdp_ring) < 1 + nr_frags)) {
3791 xdp_ring->tx_stats.tx_busy++;
3792 return I40E_XDP_CONSUMED;
3793 }
3794
3795 tx_head->bytecount = xdp_get_frame_len(xdpf);
3796 tx_head->gso_segs = 1;
3797 tx_head->xdpf = xdpf;
3798
3799 for (;;) {
3800 dma_addr_t dma;
3801
3802 dma = dma_map_single(xdp_ring->dev, data, size, DMA_TO_DEVICE);
3803 if (dma_mapping_error(xdp_ring->dev, dma))
3804 goto unmap;
3805
3806 /* record length, and DMA address */
3807 dma_unmap_len_set(tx_bi, len, size);
3808 dma_unmap_addr_set(tx_bi, dma, dma);
3809
3810 tx_desc->buffer_addr = cpu_to_le64(dma);
3811 tx_desc->cmd_type_offset_bsz =
3812 build_ctob(I40E_TX_DESC_CMD_ICRC, 0, size, 0);
3813
3814 if (++index == xdp_ring->count)
3815 index = 0;
3816
3817 if (i == nr_frags)
3818 break;
3819
3820 tx_bi = &xdp_ring->tx_bi[index];
3821 tx_desc = I40E_TX_DESC(xdp_ring, index);
3822
3823 data = skb_frag_address(&sinfo->frags[i]);
3824 size = skb_frag_size(&sinfo->frags[i]);
3825 i++;
3826 }
3827
3828 tx_desc->cmd_type_offset_bsz |=
3829 cpu_to_le64(I40E_TXD_CMD << I40E_TXD_QW1_CMD_SHIFT);
3830
3831 /* Make certain all of the status bits have been updated
3832 * before next_to_watch is written.
3833 */
3834 smp_wmb();
3835
3836 xdp_ring->xdp_tx_active++;
3837
3838 tx_head->next_to_watch = tx_desc;
3839 xdp_ring->next_to_use = index;
3840
3841 return I40E_XDP_TX;
3842
3843unmap:
3844 for (;;) {
3845 tx_bi = &xdp_ring->tx_bi[index];
3846 if (dma_unmap_len(tx_bi, len))
3847 dma_unmap_page(xdp_ring->dev,
3848 dma_unmap_addr(tx_bi, dma),
3849 dma_unmap_len(tx_bi, len),
3850 DMA_TO_DEVICE);
3851 dma_unmap_len_set(tx_bi, len, 0);
3852 if (tx_bi == tx_head)
3853 break;
3854
3855 if (!index)
3856 index += xdp_ring->count;
3857 index--;
3858 }
3859
3860 return I40E_XDP_CONSUMED;
3861}
3862
3863/**
3864 * i40e_xmit_frame_ring - Sends buffer on Tx ring
3865 * @skb: send buffer
3866 * @tx_ring: ring to send buffer on
3867 *
3868 * Returns NETDEV_TX_OK if sent, else an error code
3869 **/
3870static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
3871 struct i40e_ring *tx_ring)
3872{
3873 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
3874 u32 cd_tunneling = 0, cd_l2tag2 = 0;
3875 struct i40e_tx_buffer *first;
3876 u32 td_offset = 0;
3877 u32 tx_flags = 0;
3878 u32 td_cmd = 0;
3879 u8 hdr_len = 0;
3880 int tso, count;
3881 int tsyn;
3882
3883 /* prefetch the data, we'll need it later */
3884 prefetch(skb->data);
3885
3886 i40e_trace(xmit_frame_ring, skb, tx_ring);
3887
3888 count = i40e_xmit_descriptor_count(skb);
3889 if (i40e_chk_linearize(skb, count)) {
3890 if (__skb_linearize(skb)) {
3891 dev_kfree_skb_any(skb);
3892 return NETDEV_TX_OK;
3893 }
3894 count = i40e_txd_use_count(skb->len);
3895 tx_ring->tx_stats.tx_linearize++;
3896 }
3897
3898 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
3899 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
3900 * + 4 desc gap to avoid the cache line where head is,
3901 * + 1 desc for context descriptor,
3902 * otherwise try next time
3903 */
3904 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
3905 tx_ring->tx_stats.tx_busy++;
3906 return NETDEV_TX_BUSY;
3907 }
3908
3909 /* record the location of the first descriptor for this packet */
3910 first = &tx_ring->tx_bi[tx_ring->next_to_use];
3911 first->skb = skb;
3912 first->bytecount = skb->len;
3913 first->gso_segs = 1;
3914
3915 /* prepare the xmit flags */
3916 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
3917 goto out_drop;
3918
3919 tso = i40e_tso(first, &hdr_len, &cd_type_cmd_tso_mss);
3920
3921 if (tso < 0)
3922 goto out_drop;
3923 else if (tso)
3924 tx_flags |= I40E_TX_FLAGS_TSO;
3925
3926 /* Always offload the checksum, since it's in the data descriptor */
3927 tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
3928 tx_ring, &cd_tunneling);
3929 if (tso < 0)
3930 goto out_drop;
3931
3932 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss);
3933
3934 if (tsyn)
3935 tx_flags |= I40E_TX_FLAGS_TSYN;
3936
3937 /* always enable CRC insertion offload */
3938 td_cmd |= I40E_TX_DESC_CMD_ICRC;
3939
3940 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
3941 cd_tunneling, cd_l2tag2);
3942
3943 /* Add Flow Director ATR if it's enabled.
3944 *
3945 * NOTE: this must always be directly before the data descriptor.
3946 */
3947 i40e_atr(tx_ring, skb, tx_flags);
3948
3949 if (i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
3950 td_cmd, td_offset))
3951 goto cleanup_tx_tstamp;
3952
3953 return NETDEV_TX_OK;
3954
3955out_drop:
3956 i40e_trace(xmit_frame_ring_drop, first->skb, tx_ring);
3957 dev_kfree_skb_any(first->skb);
3958 first->skb = NULL;
3959cleanup_tx_tstamp:
3960 if (unlikely(tx_flags & I40E_TX_FLAGS_TSYN)) {
3961 struct i40e_pf *pf = i40e_netdev_to_pf(tx_ring->netdev);
3962
3963 dev_kfree_skb_any(pf->ptp_tx_skb);
3964 pf->ptp_tx_skb = NULL;
3965 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
3966 }
3967
3968 return NETDEV_TX_OK;
3969}
3970
3971/**
3972 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer
3973 * @skb: send buffer
3974 * @netdev: network interface device structure
3975 *
3976 * Returns NETDEV_TX_OK if sent, else an error code
3977 **/
3978netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3979{
3980 struct i40e_netdev_priv *np = netdev_priv(netdev);
3981 struct i40e_vsi *vsi = np->vsi;
3982 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping];
3983
3984 /* hardware can't handle really short frames, hardware padding works
3985 * beyond this point
3986 */
3987 if (skb_put_padto(skb, I40E_MIN_TX_LEN))
3988 return NETDEV_TX_OK;
3989
3990 return i40e_xmit_frame_ring(skb, tx_ring);
3991}
3992
3993/**
3994 * i40e_xdp_xmit - Implements ndo_xdp_xmit
3995 * @dev: netdev
3996 * @n: number of frames
3997 * @frames: array of XDP buffer pointers
3998 * @flags: XDP extra info
3999 *
4000 * Returns number of frames successfully sent. Failed frames
4001 * will be free'ed by XDP core.
4002 *
4003 * For error cases, a negative errno code is returned and no-frames
4004 * are transmitted (caller must handle freeing frames).
4005 **/
4006int i40e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
4007 u32 flags)
4008{
4009 struct i40e_netdev_priv *np = netdev_priv(dev);
4010 unsigned int queue_index = smp_processor_id();
4011 struct i40e_vsi *vsi = np->vsi;
4012 struct i40e_pf *pf = vsi->back;
4013 struct i40e_ring *xdp_ring;
4014 int nxmit = 0;
4015 int i;
4016
4017 if (test_bit(__I40E_VSI_DOWN, vsi->state))
4018 return -ENETDOWN;
4019
4020 if (!i40e_enabled_xdp_vsi(vsi) || queue_index >= vsi->num_queue_pairs ||
4021 test_bit(__I40E_CONFIG_BUSY, pf->state))
4022 return -ENXIO;
4023
4024 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
4025 return -EINVAL;
4026
4027 xdp_ring = vsi->xdp_rings[queue_index];
4028
4029 for (i = 0; i < n; i++) {
4030 struct xdp_frame *xdpf = frames[i];
4031 int err;
4032
4033 err = i40e_xmit_xdp_ring(xdpf, xdp_ring);
4034 if (err != I40E_XDP_TX)
4035 break;
4036 nxmit++;
4037 }
4038
4039 if (unlikely(flags & XDP_XMIT_FLUSH))
4040 i40e_xdp_ring_update_tail(xdp_ring);
4041
4042 return nxmit;
4043}
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2013 - 2018 Intel Corporation. */
3
4#include <linux/prefetch.h>
5#include <linux/bpf_trace.h>
6#include <net/xdp.h>
7#include "i40e.h"
8#include "i40e_trace.h"
9#include "i40e_prototype.h"
10#include "i40e_txrx_common.h"
11#include "i40e_xsk.h"
12
13#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
14/**
15 * i40e_fdir - Generate a Flow Director descriptor based on fdata
16 * @tx_ring: Tx ring to send buffer on
17 * @fdata: Flow director filter data
18 * @add: Indicate if we are adding a rule or deleting one
19 *
20 **/
21static void i40e_fdir(struct i40e_ring *tx_ring,
22 struct i40e_fdir_filter *fdata, bool add)
23{
24 struct i40e_filter_program_desc *fdir_desc;
25 struct i40e_pf *pf = tx_ring->vsi->back;
26 u32 flex_ptype, dtype_cmd;
27 u16 i;
28
29 /* grab the next descriptor */
30 i = tx_ring->next_to_use;
31 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
32
33 i++;
34 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
35
36 flex_ptype = I40E_TXD_FLTR_QW0_QINDEX_MASK &
37 (fdata->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT);
38
39 flex_ptype |= I40E_TXD_FLTR_QW0_FLEXOFF_MASK &
40 (fdata->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT);
41
42 flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK &
43 (fdata->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
44
45 /* Use LAN VSI Id if not programmed by user */
46 flex_ptype |= I40E_TXD_FLTR_QW0_DEST_VSI_MASK &
47 ((u32)(fdata->dest_vsi ? : pf->vsi[pf->lan_vsi]->id) <<
48 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT);
49
50 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
51
52 dtype_cmd |= add ?
53 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
54 I40E_TXD_FLTR_QW1_PCMD_SHIFT :
55 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
56 I40E_TXD_FLTR_QW1_PCMD_SHIFT;
57
58 dtype_cmd |= I40E_TXD_FLTR_QW1_DEST_MASK &
59 (fdata->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT);
60
61 dtype_cmd |= I40E_TXD_FLTR_QW1_FD_STATUS_MASK &
62 (fdata->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT);
63
64 if (fdata->cnt_index) {
65 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
66 dtype_cmd |= I40E_TXD_FLTR_QW1_CNTINDEX_MASK &
67 ((u32)fdata->cnt_index <<
68 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT);
69 }
70
71 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
72 fdir_desc->rsvd = cpu_to_le32(0);
73 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
74 fdir_desc->fd_id = cpu_to_le32(fdata->fd_id);
75}
76
77#define I40E_FD_CLEAN_DELAY 10
78/**
79 * i40e_program_fdir_filter - Program a Flow Director filter
80 * @fdir_data: Packet data that will be filter parameters
81 * @raw_packet: the pre-allocated packet buffer for FDir
82 * @pf: The PF pointer
83 * @add: True for add/update, False for remove
84 **/
85static int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data,
86 u8 *raw_packet, struct i40e_pf *pf,
87 bool add)
88{
89 struct i40e_tx_buffer *tx_buf, *first;
90 struct i40e_tx_desc *tx_desc;
91 struct i40e_ring *tx_ring;
92 struct i40e_vsi *vsi;
93 struct device *dev;
94 dma_addr_t dma;
95 u32 td_cmd = 0;
96 u16 i;
97
98 /* find existing FDIR VSI */
99 vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR);
100 if (!vsi)
101 return -ENOENT;
102
103 tx_ring = vsi->tx_rings[0];
104 dev = tx_ring->dev;
105
106 /* we need two descriptors to add/del a filter and we can wait */
107 for (i = I40E_FD_CLEAN_DELAY; I40E_DESC_UNUSED(tx_ring) < 2; i--) {
108 if (!i)
109 return -EAGAIN;
110 msleep_interruptible(1);
111 }
112
113 dma = dma_map_single(dev, raw_packet,
114 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE);
115 if (dma_mapping_error(dev, dma))
116 goto dma_fail;
117
118 /* grab the next descriptor */
119 i = tx_ring->next_to_use;
120 first = &tx_ring->tx_bi[i];
121 i40e_fdir(tx_ring, fdir_data, add);
122
123 /* Now program a dummy descriptor */
124 i = tx_ring->next_to_use;
125 tx_desc = I40E_TX_DESC(tx_ring, i);
126 tx_buf = &tx_ring->tx_bi[i];
127
128 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
129
130 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer));
131
132 /* record length, and DMA address */
133 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE);
134 dma_unmap_addr_set(tx_buf, dma, dma);
135
136 tx_desc->buffer_addr = cpu_to_le64(dma);
137 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY;
138
139 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB;
140 tx_buf->raw_buf = (void *)raw_packet;
141
142 tx_desc->cmd_type_offset_bsz =
143 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0);
144
145 /* Force memory writes to complete before letting h/w
146 * know there are new descriptors to fetch.
147 */
148 wmb();
149
150 /* Mark the data descriptor to be watched */
151 first->next_to_watch = tx_desc;
152
153 writel(tx_ring->next_to_use, tx_ring->tail);
154 return 0;
155
156dma_fail:
157 return -1;
158}
159
160/**
161 * i40e_create_dummy_packet - Constructs dummy packet for HW
162 * @dummy_packet: preallocated space for dummy packet
163 * @ipv4: is layer 3 packet of version 4 or 6
164 * @l4proto: next level protocol used in data portion of l3
165 * @data: filter data
166 *
167 * Returns address of layer 4 protocol dummy packet.
168 **/
169static char *i40e_create_dummy_packet(u8 *dummy_packet, bool ipv4, u8 l4proto,
170 struct i40e_fdir_filter *data)
171{
172 bool is_vlan = !!data->vlan_tag;
173 struct vlan_hdr vlan;
174 struct ipv6hdr ipv6;
175 struct ethhdr eth;
176 struct iphdr ip;
177 u8 *tmp;
178
179 if (ipv4) {
180 eth.h_proto = cpu_to_be16(ETH_P_IP);
181 ip.protocol = l4proto;
182 ip.version = 0x4;
183 ip.ihl = 0x5;
184
185 ip.daddr = data->dst_ip;
186 ip.saddr = data->src_ip;
187 } else {
188 eth.h_proto = cpu_to_be16(ETH_P_IPV6);
189 ipv6.nexthdr = l4proto;
190 ipv6.version = 0x6;
191
192 memcpy(&ipv6.saddr.in6_u.u6_addr32, data->src_ip6,
193 sizeof(__be32) * 4);
194 memcpy(&ipv6.daddr.in6_u.u6_addr32, data->dst_ip6,
195 sizeof(__be32) * 4);
196 }
197
198 if (is_vlan) {
199 vlan.h_vlan_TCI = data->vlan_tag;
200 vlan.h_vlan_encapsulated_proto = eth.h_proto;
201 eth.h_proto = data->vlan_etype;
202 }
203
204 tmp = dummy_packet;
205 memcpy(tmp, ð, sizeof(eth));
206 tmp += sizeof(eth);
207
208 if (is_vlan) {
209 memcpy(tmp, &vlan, sizeof(vlan));
210 tmp += sizeof(vlan);
211 }
212
213 if (ipv4) {
214 memcpy(tmp, &ip, sizeof(ip));
215 tmp += sizeof(ip);
216 } else {
217 memcpy(tmp, &ipv6, sizeof(ipv6));
218 tmp += sizeof(ipv6);
219 }
220
221 return tmp;
222}
223
224/**
225 * i40e_create_dummy_udp_packet - helper function to create UDP packet
226 * @raw_packet: preallocated space for dummy packet
227 * @ipv4: is layer 3 packet of version 4 or 6
228 * @l4proto: next level protocol used in data portion of l3
229 * @data: filter data
230 *
231 * Helper function to populate udp fields.
232 **/
233static void i40e_create_dummy_udp_packet(u8 *raw_packet, bool ipv4, u8 l4proto,
234 struct i40e_fdir_filter *data)
235{
236 struct udphdr *udp;
237 u8 *tmp;
238
239 tmp = i40e_create_dummy_packet(raw_packet, ipv4, IPPROTO_UDP, data);
240 udp = (struct udphdr *)(tmp);
241 udp->dest = data->dst_port;
242 udp->source = data->src_port;
243}
244
245/**
246 * i40e_create_dummy_tcp_packet - helper function to create TCP packet
247 * @raw_packet: preallocated space for dummy packet
248 * @ipv4: is layer 3 packet of version 4 or 6
249 * @l4proto: next level protocol used in data portion of l3
250 * @data: filter data
251 *
252 * Helper function to populate tcp fields.
253 **/
254static void i40e_create_dummy_tcp_packet(u8 *raw_packet, bool ipv4, u8 l4proto,
255 struct i40e_fdir_filter *data)
256{
257 struct tcphdr *tcp;
258 u8 *tmp;
259 /* Dummy tcp packet */
260 static const char tcp_packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
261 0x50, 0x11, 0x0, 0x72, 0, 0, 0, 0};
262
263 tmp = i40e_create_dummy_packet(raw_packet, ipv4, IPPROTO_TCP, data);
264
265 tcp = (struct tcphdr *)tmp;
266 memcpy(tcp, tcp_packet, sizeof(tcp_packet));
267 tcp->dest = data->dst_port;
268 tcp->source = data->src_port;
269}
270
271/**
272 * i40e_create_dummy_sctp_packet - helper function to create SCTP packet
273 * @raw_packet: preallocated space for dummy packet
274 * @ipv4: is layer 3 packet of version 4 or 6
275 * @l4proto: next level protocol used in data portion of l3
276 * @data: filter data
277 *
278 * Helper function to populate sctp fields.
279 **/
280static void i40e_create_dummy_sctp_packet(u8 *raw_packet, bool ipv4,
281 u8 l4proto,
282 struct i40e_fdir_filter *data)
283{
284 struct sctphdr *sctp;
285 u8 *tmp;
286
287 tmp = i40e_create_dummy_packet(raw_packet, ipv4, IPPROTO_SCTP, data);
288
289 sctp = (struct sctphdr *)tmp;
290 sctp->dest = data->dst_port;
291 sctp->source = data->src_port;
292}
293
294/**
295 * i40e_prepare_fdir_filter - Prepare and program fdir filter
296 * @pf: physical function to attach filter to
297 * @fd_data: filter data
298 * @add: add or delete filter
299 * @packet_addr: address of dummy packet, used in filtering
300 * @payload_offset: offset from dummy packet address to user defined data
301 * @pctype: Packet type for which filter is used
302 *
303 * Helper function to offset data of dummy packet, program it and
304 * handle errors.
305 **/
306static int i40e_prepare_fdir_filter(struct i40e_pf *pf,
307 struct i40e_fdir_filter *fd_data,
308 bool add, char *packet_addr,
309 int payload_offset, u8 pctype)
310{
311 int ret;
312
313 if (fd_data->flex_filter) {
314 u8 *payload;
315 __be16 pattern = fd_data->flex_word;
316 u16 off = fd_data->flex_offset;
317
318 payload = packet_addr + payload_offset;
319
320 /* If user provided vlan, offset payload by vlan header length */
321 if (!!fd_data->vlan_tag)
322 payload += VLAN_HLEN;
323
324 *((__force __be16 *)(payload + off)) = pattern;
325 }
326
327 fd_data->pctype = pctype;
328 ret = i40e_program_fdir_filter(fd_data, packet_addr, pf, add);
329 if (ret) {
330 dev_info(&pf->pdev->dev,
331 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
332 fd_data->pctype, fd_data->fd_id, ret);
333 /* Free the packet buffer since it wasn't added to the ring */
334 return -EOPNOTSUPP;
335 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
336 if (add)
337 dev_info(&pf->pdev->dev,
338 "Filter OK for PCTYPE %d loc = %d\n",
339 fd_data->pctype, fd_data->fd_id);
340 else
341 dev_info(&pf->pdev->dev,
342 "Filter deleted for PCTYPE %d loc = %d\n",
343 fd_data->pctype, fd_data->fd_id);
344 }
345
346 return ret;
347}
348
349/**
350 * i40e_change_filter_num - Prepare and program fdir filter
351 * @ipv4: is layer 3 packet of version 4 or 6
352 * @add: add or delete filter
353 * @ipv4_filter_num: field to update
354 * @ipv6_filter_num: field to update
355 *
356 * Update filter number field for pf.
357 **/
358static void i40e_change_filter_num(bool ipv4, bool add, u16 *ipv4_filter_num,
359 u16 *ipv6_filter_num)
360{
361 if (add) {
362 if (ipv4)
363 (*ipv4_filter_num)++;
364 else
365 (*ipv6_filter_num)++;
366 } else {
367 if (ipv4)
368 (*ipv4_filter_num)--;
369 else
370 (*ipv6_filter_num)--;
371 }
372}
373
374#define IP_HEADER_OFFSET 14
375#define I40E_UDPIP_DUMMY_PACKET_LEN 42
376#define I40E_UDPIP6_DUMMY_PACKET_LEN 62
377/**
378 * i40e_add_del_fdir_udp - Add/Remove UDP filters
379 * @vsi: pointer to the targeted VSI
380 * @fd_data: the flow director data required for the FDir descriptor
381 * @add: true adds a filter, false removes it
382 * @ipv4: true is v4, false is v6
383 *
384 * Returns 0 if the filters were successfully added or removed
385 **/
386static int i40e_add_del_fdir_udp(struct i40e_vsi *vsi,
387 struct i40e_fdir_filter *fd_data,
388 bool add,
389 bool ipv4)
390{
391 struct i40e_pf *pf = vsi->back;
392 u8 *raw_packet;
393 int ret;
394
395 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
396 if (!raw_packet)
397 return -ENOMEM;
398
399 i40e_create_dummy_udp_packet(raw_packet, ipv4, IPPROTO_UDP, fd_data);
400
401 if (ipv4)
402 ret = i40e_prepare_fdir_filter
403 (pf, fd_data, add, raw_packet,
404 I40E_UDPIP_DUMMY_PACKET_LEN,
405 I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
406 else
407 ret = i40e_prepare_fdir_filter
408 (pf, fd_data, add, raw_packet,
409 I40E_UDPIP6_DUMMY_PACKET_LEN,
410 I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
411
412 if (ret) {
413 kfree(raw_packet);
414 return ret;
415 }
416
417 i40e_change_filter_num(ipv4, add, &pf->fd_udp4_filter_cnt,
418 &pf->fd_udp6_filter_cnt);
419
420 return 0;
421}
422
423#define I40E_TCPIP_DUMMY_PACKET_LEN 54
424#define I40E_TCPIP6_DUMMY_PACKET_LEN 74
425/**
426 * i40e_add_del_fdir_tcp - Add/Remove TCPv4 filters
427 * @vsi: pointer to the targeted VSI
428 * @fd_data: the flow director data required for the FDir descriptor
429 * @add: true adds a filter, false removes it
430 * @ipv4: true is v4, false is v6
431 *
432 * Returns 0 if the filters were successfully added or removed
433 **/
434static int i40e_add_del_fdir_tcp(struct i40e_vsi *vsi,
435 struct i40e_fdir_filter *fd_data,
436 bool add,
437 bool ipv4)
438{
439 struct i40e_pf *pf = vsi->back;
440 u8 *raw_packet;
441 int ret;
442
443 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
444 if (!raw_packet)
445 return -ENOMEM;
446
447 i40e_create_dummy_tcp_packet(raw_packet, ipv4, IPPROTO_TCP, fd_data);
448 if (ipv4)
449 ret = i40e_prepare_fdir_filter
450 (pf, fd_data, add, raw_packet,
451 I40E_TCPIP_DUMMY_PACKET_LEN,
452 I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
453 else
454 ret = i40e_prepare_fdir_filter
455 (pf, fd_data, add, raw_packet,
456 I40E_TCPIP6_DUMMY_PACKET_LEN,
457 I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
458
459 if (ret) {
460 kfree(raw_packet);
461 return ret;
462 }
463
464 i40e_change_filter_num(ipv4, add, &pf->fd_tcp4_filter_cnt,
465 &pf->fd_tcp6_filter_cnt);
466
467 if (add) {
468 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
469 I40E_DEBUG_FD & pf->hw.debug_mask)
470 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");
471 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
472 }
473 return 0;
474}
475
476#define I40E_SCTPIP_DUMMY_PACKET_LEN 46
477#define I40E_SCTPIP6_DUMMY_PACKET_LEN 66
478/**
479 * i40e_add_del_fdir_sctp - Add/Remove SCTPv4 Flow Director filters for
480 * a specific flow spec
481 * @vsi: pointer to the targeted VSI
482 * @fd_data: the flow director data required for the FDir descriptor
483 * @add: true adds a filter, false removes it
484 * @ipv4: true is v4, false is v6
485 *
486 * Returns 0 if the filters were successfully added or removed
487 **/
488static int i40e_add_del_fdir_sctp(struct i40e_vsi *vsi,
489 struct i40e_fdir_filter *fd_data,
490 bool add,
491 bool ipv4)
492{
493 struct i40e_pf *pf = vsi->back;
494 u8 *raw_packet;
495 int ret;
496
497 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
498 if (!raw_packet)
499 return -ENOMEM;
500
501 i40e_create_dummy_sctp_packet(raw_packet, ipv4, IPPROTO_SCTP, fd_data);
502
503 if (ipv4)
504 ret = i40e_prepare_fdir_filter
505 (pf, fd_data, add, raw_packet,
506 I40E_SCTPIP_DUMMY_PACKET_LEN,
507 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
508 else
509 ret = i40e_prepare_fdir_filter
510 (pf, fd_data, add, raw_packet,
511 I40E_SCTPIP6_DUMMY_PACKET_LEN,
512 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
513
514 if (ret) {
515 kfree(raw_packet);
516 return ret;
517 }
518
519 i40e_change_filter_num(ipv4, add, &pf->fd_sctp4_filter_cnt,
520 &pf->fd_sctp6_filter_cnt);
521
522 return 0;
523}
524
525#define I40E_IP_DUMMY_PACKET_LEN 34
526#define I40E_IP6_DUMMY_PACKET_LEN 54
527/**
528 * i40e_add_del_fdir_ip - Add/Remove IPv4 Flow Director filters for
529 * a specific flow spec
530 * @vsi: pointer to the targeted VSI
531 * @fd_data: the flow director data required for the FDir descriptor
532 * @add: true adds a filter, false removes it
533 * @ipv4: true is v4, false is v6
534 *
535 * Returns 0 if the filters were successfully added or removed
536 **/
537static int i40e_add_del_fdir_ip(struct i40e_vsi *vsi,
538 struct i40e_fdir_filter *fd_data,
539 bool add,
540 bool ipv4)
541{
542 struct i40e_pf *pf = vsi->back;
543 int payload_offset;
544 u8 *raw_packet;
545 int iter_start;
546 int iter_end;
547 int ret;
548 int i;
549
550 if (ipv4) {
551 iter_start = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
552 iter_end = I40E_FILTER_PCTYPE_FRAG_IPV4;
553 } else {
554 iter_start = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
555 iter_end = I40E_FILTER_PCTYPE_FRAG_IPV6;
556 }
557
558 for (i = iter_start; i <= iter_end; i++) {
559 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
560 if (!raw_packet)
561 return -ENOMEM;
562
563 /* IPv6 no header option differs from IPv4 */
564 (void)i40e_create_dummy_packet
565 (raw_packet, ipv4, (ipv4) ? IPPROTO_IP : IPPROTO_NONE,
566 fd_data);
567
568 payload_offset = (ipv4) ? I40E_IP_DUMMY_PACKET_LEN :
569 I40E_IP6_DUMMY_PACKET_LEN;
570 ret = i40e_prepare_fdir_filter(pf, fd_data, add, raw_packet,
571 payload_offset, i);
572 if (ret)
573 goto err;
574 }
575
576 i40e_change_filter_num(ipv4, add, &pf->fd_ip4_filter_cnt,
577 &pf->fd_ip6_filter_cnt);
578
579 return 0;
580err:
581 kfree(raw_packet);
582 return ret;
583}
584
585/**
586 * i40e_add_del_fdir - Build raw packets to add/del fdir filter
587 * @vsi: pointer to the targeted VSI
588 * @input: filter to add or delete
589 * @add: true adds a filter, false removes it
590 *
591 **/
592int i40e_add_del_fdir(struct i40e_vsi *vsi,
593 struct i40e_fdir_filter *input, bool add)
594{
595 enum ip_ver { ipv6 = 0, ipv4 = 1 };
596 struct i40e_pf *pf = vsi->back;
597 int ret;
598
599 switch (input->flow_type & ~FLOW_EXT) {
600 case TCP_V4_FLOW:
601 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv4);
602 break;
603 case UDP_V4_FLOW:
604 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv4);
605 break;
606 case SCTP_V4_FLOW:
607 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv4);
608 break;
609 case TCP_V6_FLOW:
610 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv6);
611 break;
612 case UDP_V6_FLOW:
613 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv6);
614 break;
615 case SCTP_V6_FLOW:
616 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv6);
617 break;
618 case IP_USER_FLOW:
619 switch (input->ipl4_proto) {
620 case IPPROTO_TCP:
621 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv4);
622 break;
623 case IPPROTO_UDP:
624 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv4);
625 break;
626 case IPPROTO_SCTP:
627 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv4);
628 break;
629 case IPPROTO_IP:
630 ret = i40e_add_del_fdir_ip(vsi, input, add, ipv4);
631 break;
632 default:
633 /* We cannot support masking based on protocol */
634 dev_info(&pf->pdev->dev, "Unsupported IPv4 protocol 0x%02x\n",
635 input->ipl4_proto);
636 return -EINVAL;
637 }
638 break;
639 case IPV6_USER_FLOW:
640 switch (input->ipl4_proto) {
641 case IPPROTO_TCP:
642 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv6);
643 break;
644 case IPPROTO_UDP:
645 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv6);
646 break;
647 case IPPROTO_SCTP:
648 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv6);
649 break;
650 case IPPROTO_IP:
651 ret = i40e_add_del_fdir_ip(vsi, input, add, ipv6);
652 break;
653 default:
654 /* We cannot support masking based on protocol */
655 dev_info(&pf->pdev->dev, "Unsupported IPv6 protocol 0x%02x\n",
656 input->ipl4_proto);
657 return -EINVAL;
658 }
659 break;
660 default:
661 dev_info(&pf->pdev->dev, "Unsupported flow type 0x%02x\n",
662 input->flow_type);
663 return -EINVAL;
664 }
665
666 /* The buffer allocated here will be normally be freed by
667 * i40e_clean_fdir_tx_irq() as it reclaims resources after transmit
668 * completion. In the event of an error adding the buffer to the FDIR
669 * ring, it will immediately be freed. It may also be freed by
670 * i40e_clean_tx_ring() when closing the VSI.
671 */
672 return ret;
673}
674
675/**
676 * i40e_fd_handle_status - check the Programming Status for FD
677 * @rx_ring: the Rx ring for this descriptor
678 * @qword0_raw: qword0
679 * @qword1: qword1 after le_to_cpu
680 * @prog_id: the id originally used for programming
681 *
682 * This is used to verify if the FD programming or invalidation
683 * requested by SW to the HW is successful or not and take actions accordingly.
684 **/
685static void i40e_fd_handle_status(struct i40e_ring *rx_ring, u64 qword0_raw,
686 u64 qword1, u8 prog_id)
687{
688 struct i40e_pf *pf = rx_ring->vsi->back;
689 struct pci_dev *pdev = pf->pdev;
690 struct i40e_16b_rx_wb_qw0 *qw0;
691 u32 fcnt_prog, fcnt_avail;
692 u32 error;
693
694 qw0 = (struct i40e_16b_rx_wb_qw0 *)&qword0_raw;
695 error = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
696 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
697
698 if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
699 pf->fd_inv = le32_to_cpu(qw0->hi_dword.fd_id);
700 if (qw0->hi_dword.fd_id != 0 ||
701 (I40E_DEBUG_FD & pf->hw.debug_mask))
702 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
703 pf->fd_inv);
704
705 /* Check if the programming error is for ATR.
706 * If so, auto disable ATR and set a state for
707 * flush in progress. Next time we come here if flush is in
708 * progress do nothing, once flush is complete the state will
709 * be cleared.
710 */
711 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
712 return;
713
714 pf->fd_add_err++;
715 /* store the current atr filter count */
716 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf);
717
718 if (qw0->hi_dword.fd_id == 0 &&
719 test_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state)) {
720 /* These set_bit() calls aren't atomic with the
721 * test_bit() here, but worse case we potentially
722 * disable ATR and queue a flush right after SB
723 * support is re-enabled. That shouldn't cause an
724 * issue in practice
725 */
726 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
727 set_bit(__I40E_FD_FLUSH_REQUESTED, pf->state);
728 }
729
730 /* filter programming failed most likely due to table full */
731 fcnt_prog = i40e_get_global_fd_count(pf);
732 fcnt_avail = pf->fdir_pf_filter_count;
733 /* If ATR is running fcnt_prog can quickly change,
734 * if we are very close to full, it makes sense to disable
735 * FD ATR/SB and then re-enable it when there is room.
736 */
737 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {
738 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
739 !test_and_set_bit(__I40E_FD_SB_AUTO_DISABLED,
740 pf->state))
741 if (I40E_DEBUG_FD & pf->hw.debug_mask)
742 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n");
743 }
744 } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
745 if (I40E_DEBUG_FD & pf->hw.debug_mask)
746 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n",
747 qw0->hi_dword.fd_id);
748 }
749}
750
751/**
752 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
753 * @ring: the ring that owns the buffer
754 * @tx_buffer: the buffer to free
755 **/
756static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
757 struct i40e_tx_buffer *tx_buffer)
758{
759 if (tx_buffer->skb) {
760 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
761 kfree(tx_buffer->raw_buf);
762 else if (ring_is_xdp(ring))
763 xdp_return_frame(tx_buffer->xdpf);
764 else
765 dev_kfree_skb_any(tx_buffer->skb);
766 if (dma_unmap_len(tx_buffer, len))
767 dma_unmap_single(ring->dev,
768 dma_unmap_addr(tx_buffer, dma),
769 dma_unmap_len(tx_buffer, len),
770 DMA_TO_DEVICE);
771 } else if (dma_unmap_len(tx_buffer, len)) {
772 dma_unmap_page(ring->dev,
773 dma_unmap_addr(tx_buffer, dma),
774 dma_unmap_len(tx_buffer, len),
775 DMA_TO_DEVICE);
776 }
777
778 tx_buffer->next_to_watch = NULL;
779 tx_buffer->skb = NULL;
780 dma_unmap_len_set(tx_buffer, len, 0);
781 /* tx_buffer must be completely set up in the transmit path */
782}
783
784/**
785 * i40e_clean_tx_ring - Free any empty Tx buffers
786 * @tx_ring: ring to be cleaned
787 **/
788void i40e_clean_tx_ring(struct i40e_ring *tx_ring)
789{
790 unsigned long bi_size;
791 u16 i;
792
793 if (ring_is_xdp(tx_ring) && tx_ring->xsk_pool) {
794 i40e_xsk_clean_tx_ring(tx_ring);
795 } else {
796 /* ring already cleared, nothing to do */
797 if (!tx_ring->tx_bi)
798 return;
799
800 /* Free all the Tx ring sk_buffs */
801 for (i = 0; i < tx_ring->count; i++)
802 i40e_unmap_and_free_tx_resource(tx_ring,
803 &tx_ring->tx_bi[i]);
804 }
805
806 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
807 memset(tx_ring->tx_bi, 0, bi_size);
808
809 /* Zero out the descriptor ring */
810 memset(tx_ring->desc, 0, tx_ring->size);
811
812 tx_ring->next_to_use = 0;
813 tx_ring->next_to_clean = 0;
814
815 if (!tx_ring->netdev)
816 return;
817
818 /* cleanup Tx queue statistics */
819 netdev_tx_reset_queue(txring_txq(tx_ring));
820}
821
822/**
823 * i40e_free_tx_resources - Free Tx resources per queue
824 * @tx_ring: Tx descriptor ring for a specific queue
825 *
826 * Free all transmit software resources
827 **/
828void i40e_free_tx_resources(struct i40e_ring *tx_ring)
829{
830 i40e_clean_tx_ring(tx_ring);
831 kfree(tx_ring->tx_bi);
832 tx_ring->tx_bi = NULL;
833 kfree(tx_ring->xsk_descs);
834 tx_ring->xsk_descs = NULL;
835
836 if (tx_ring->desc) {
837 dma_free_coherent(tx_ring->dev, tx_ring->size,
838 tx_ring->desc, tx_ring->dma);
839 tx_ring->desc = NULL;
840 }
841}
842
843/**
844 * i40e_get_tx_pending - how many tx descriptors not processed
845 * @ring: the ring of descriptors
846 * @in_sw: use SW variables
847 *
848 * Since there is no access to the ring head register
849 * in XL710, we need to use our local copies
850 **/
851u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw)
852{
853 u32 head, tail;
854
855 if (!in_sw) {
856 head = i40e_get_head(ring);
857 tail = readl(ring->tail);
858 } else {
859 head = ring->next_to_clean;
860 tail = ring->next_to_use;
861 }
862
863 if (head != tail)
864 return (head < tail) ?
865 tail - head : (tail + ring->count - head);
866
867 return 0;
868}
869
870/**
871 * i40e_detect_recover_hung - Function to detect and recover hung_queues
872 * @vsi: pointer to vsi struct with tx queues
873 *
874 * VSI has netdev and netdev has TX queues. This function is to check each of
875 * those TX queues if they are hung, trigger recovery by issuing SW interrupt.
876 **/
877void i40e_detect_recover_hung(struct i40e_vsi *vsi)
878{
879 struct i40e_ring *tx_ring = NULL;
880 struct net_device *netdev;
881 unsigned int i;
882 int packets;
883
884 if (!vsi)
885 return;
886
887 if (test_bit(__I40E_VSI_DOWN, vsi->state))
888 return;
889
890 netdev = vsi->netdev;
891 if (!netdev)
892 return;
893
894 if (!netif_carrier_ok(netdev))
895 return;
896
897 for (i = 0; i < vsi->num_queue_pairs; i++) {
898 tx_ring = vsi->tx_rings[i];
899 if (tx_ring && tx_ring->desc) {
900 /* If packet counter has not changed the queue is
901 * likely stalled, so force an interrupt for this
902 * queue.
903 *
904 * prev_pkt_ctr would be negative if there was no
905 * pending work.
906 */
907 packets = tx_ring->stats.packets & INT_MAX;
908 if (tx_ring->tx_stats.prev_pkt_ctr == packets) {
909 i40e_force_wb(vsi, tx_ring->q_vector);
910 continue;
911 }
912
913 /* Memory barrier between read of packet count and call
914 * to i40e_get_tx_pending()
915 */
916 smp_rmb();
917 tx_ring->tx_stats.prev_pkt_ctr =
918 i40e_get_tx_pending(tx_ring, true) ? packets : -1;
919 }
920 }
921}
922
923/**
924 * i40e_clean_tx_irq - Reclaim resources after transmit completes
925 * @vsi: the VSI we care about
926 * @tx_ring: Tx ring to clean
927 * @napi_budget: Used to determine if we are in netpoll
928 *
929 * Returns true if there's any budget left (e.g. the clean is finished)
930 **/
931static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,
932 struct i40e_ring *tx_ring, int napi_budget)
933{
934 int i = tx_ring->next_to_clean;
935 struct i40e_tx_buffer *tx_buf;
936 struct i40e_tx_desc *tx_head;
937 struct i40e_tx_desc *tx_desc;
938 unsigned int total_bytes = 0, total_packets = 0;
939 unsigned int budget = vsi->work_limit;
940
941 tx_buf = &tx_ring->tx_bi[i];
942 tx_desc = I40E_TX_DESC(tx_ring, i);
943 i -= tx_ring->count;
944
945 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
946
947 do {
948 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
949
950 /* if next_to_watch is not set then there is no work pending */
951 if (!eop_desc)
952 break;
953
954 /* prevent any other reads prior to eop_desc */
955 smp_rmb();
956
957 i40e_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf);
958 /* we have caught up to head, no work left to do */
959 if (tx_head == tx_desc)
960 break;
961
962 /* clear next_to_watch to prevent false hangs */
963 tx_buf->next_to_watch = NULL;
964
965 /* update the statistics for this packet */
966 total_bytes += tx_buf->bytecount;
967 total_packets += tx_buf->gso_segs;
968
969 /* free the skb/XDP data */
970 if (ring_is_xdp(tx_ring))
971 xdp_return_frame(tx_buf->xdpf);
972 else
973 napi_consume_skb(tx_buf->skb, napi_budget);
974
975 /* unmap skb header data */
976 dma_unmap_single(tx_ring->dev,
977 dma_unmap_addr(tx_buf, dma),
978 dma_unmap_len(tx_buf, len),
979 DMA_TO_DEVICE);
980
981 /* clear tx_buffer data */
982 tx_buf->skb = NULL;
983 dma_unmap_len_set(tx_buf, len, 0);
984
985 /* unmap remaining buffers */
986 while (tx_desc != eop_desc) {
987 i40e_trace(clean_tx_irq_unmap,
988 tx_ring, tx_desc, tx_buf);
989
990 tx_buf++;
991 tx_desc++;
992 i++;
993 if (unlikely(!i)) {
994 i -= tx_ring->count;
995 tx_buf = tx_ring->tx_bi;
996 tx_desc = I40E_TX_DESC(tx_ring, 0);
997 }
998
999 /* unmap any remaining paged data */
1000 if (dma_unmap_len(tx_buf, len)) {
1001 dma_unmap_page(tx_ring->dev,
1002 dma_unmap_addr(tx_buf, dma),
1003 dma_unmap_len(tx_buf, len),
1004 DMA_TO_DEVICE);
1005 dma_unmap_len_set(tx_buf, len, 0);
1006 }
1007 }
1008
1009 /* move us one more past the eop_desc for start of next pkt */
1010 tx_buf++;
1011 tx_desc++;
1012 i++;
1013 if (unlikely(!i)) {
1014 i -= tx_ring->count;
1015 tx_buf = tx_ring->tx_bi;
1016 tx_desc = I40E_TX_DESC(tx_ring, 0);
1017 }
1018
1019 prefetch(tx_desc);
1020
1021 /* update budget accounting */
1022 budget--;
1023 } while (likely(budget));
1024
1025 i += tx_ring->count;
1026 tx_ring->next_to_clean = i;
1027 i40e_update_tx_stats(tx_ring, total_packets, total_bytes);
1028 i40e_arm_wb(tx_ring, vsi, budget);
1029
1030 if (ring_is_xdp(tx_ring))
1031 return !!budget;
1032
1033 /* notify netdev of completed buffers */
1034 netdev_tx_completed_queue(txring_txq(tx_ring),
1035 total_packets, total_bytes);
1036
1037#define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2))
1038 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1039 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
1040 /* Make sure that anybody stopping the queue after this
1041 * sees the new next_to_clean.
1042 */
1043 smp_mb();
1044 if (__netif_subqueue_stopped(tx_ring->netdev,
1045 tx_ring->queue_index) &&
1046 !test_bit(__I40E_VSI_DOWN, vsi->state)) {
1047 netif_wake_subqueue(tx_ring->netdev,
1048 tx_ring->queue_index);
1049 ++tx_ring->tx_stats.restart_queue;
1050 }
1051 }
1052
1053 return !!budget;
1054}
1055
1056/**
1057 * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
1058 * @vsi: the VSI we care about
1059 * @q_vector: the vector on which to enable writeback
1060 *
1061 **/
1062static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
1063 struct i40e_q_vector *q_vector)
1064{
1065 u16 flags = q_vector->tx.ring[0].flags;
1066 u32 val;
1067
1068 if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
1069 return;
1070
1071 if (q_vector->arm_wb_state)
1072 return;
1073
1074 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
1075 val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK |
1076 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */
1077
1078 wr32(&vsi->back->hw,
1079 I40E_PFINT_DYN_CTLN(q_vector->reg_idx),
1080 val);
1081 } else {
1082 val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK |
1083 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */
1084
1085 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
1086 }
1087 q_vector->arm_wb_state = true;
1088}
1089
1090/**
1091 * i40e_force_wb - Issue SW Interrupt so HW does a wb
1092 * @vsi: the VSI we care about
1093 * @q_vector: the vector on which to force writeback
1094 *
1095 **/
1096void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
1097{
1098 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
1099 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1100 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */
1101 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
1102 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
1103 /* allow 00 to be written to the index */
1104
1105 wr32(&vsi->back->hw,
1106 I40E_PFINT_DYN_CTLN(q_vector->reg_idx), val);
1107 } else {
1108 u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
1109 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */
1110 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
1111 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK;
1112 /* allow 00 to be written to the index */
1113
1114 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
1115 }
1116}
1117
1118static inline bool i40e_container_is_rx(struct i40e_q_vector *q_vector,
1119 struct i40e_ring_container *rc)
1120{
1121 return &q_vector->rx == rc;
1122}
1123
1124static inline unsigned int i40e_itr_divisor(struct i40e_q_vector *q_vector)
1125{
1126 unsigned int divisor;
1127
1128 switch (q_vector->vsi->back->hw.phy.link_info.link_speed) {
1129 case I40E_LINK_SPEED_40GB:
1130 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 1024;
1131 break;
1132 case I40E_LINK_SPEED_25GB:
1133 case I40E_LINK_SPEED_20GB:
1134 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 512;
1135 break;
1136 default:
1137 case I40E_LINK_SPEED_10GB:
1138 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 256;
1139 break;
1140 case I40E_LINK_SPEED_1GB:
1141 case I40E_LINK_SPEED_100MB:
1142 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 32;
1143 break;
1144 }
1145
1146 return divisor;
1147}
1148
1149/**
1150 * i40e_update_itr - update the dynamic ITR value based on statistics
1151 * @q_vector: structure containing interrupt and ring information
1152 * @rc: structure containing ring performance data
1153 *
1154 * Stores a new ITR value based on packets and byte
1155 * counts during the last interrupt. The advantage of per interrupt
1156 * computation is faster updates and more accurate ITR for the current
1157 * traffic pattern. Constants in this function were computed
1158 * based on theoretical maximum wire speed and thresholds were set based
1159 * on testing data as well as attempting to minimize response time
1160 * while increasing bulk throughput.
1161 **/
1162static void i40e_update_itr(struct i40e_q_vector *q_vector,
1163 struct i40e_ring_container *rc)
1164{
1165 unsigned int avg_wire_size, packets, bytes, itr;
1166 unsigned long next_update = jiffies;
1167
1168 /* If we don't have any rings just leave ourselves set for maximum
1169 * possible latency so we take ourselves out of the equation.
1170 */
1171 if (!rc->ring || !ITR_IS_DYNAMIC(rc->ring->itr_setting))
1172 return;
1173
1174 /* For Rx we want to push the delay up and default to low latency.
1175 * for Tx we want to pull the delay down and default to high latency.
1176 */
1177 itr = i40e_container_is_rx(q_vector, rc) ?
1178 I40E_ITR_ADAPTIVE_MIN_USECS | I40E_ITR_ADAPTIVE_LATENCY :
1179 I40E_ITR_ADAPTIVE_MAX_USECS | I40E_ITR_ADAPTIVE_LATENCY;
1180
1181 /* If we didn't update within up to 1 - 2 jiffies we can assume
1182 * that either packets are coming in so slow there hasn't been
1183 * any work, or that there is so much work that NAPI is dealing
1184 * with interrupt moderation and we don't need to do anything.
1185 */
1186 if (time_after(next_update, rc->next_update))
1187 goto clear_counts;
1188
1189 /* If itr_countdown is set it means we programmed an ITR within
1190 * the last 4 interrupt cycles. This has a side effect of us
1191 * potentially firing an early interrupt. In order to work around
1192 * this we need to throw out any data received for a few
1193 * interrupts following the update.
1194 */
1195 if (q_vector->itr_countdown) {
1196 itr = rc->target_itr;
1197 goto clear_counts;
1198 }
1199
1200 packets = rc->total_packets;
1201 bytes = rc->total_bytes;
1202
1203 if (i40e_container_is_rx(q_vector, rc)) {
1204 /* If Rx there are 1 to 4 packets and bytes are less than
1205 * 9000 assume insufficient data to use bulk rate limiting
1206 * approach unless Tx is already in bulk rate limiting. We
1207 * are likely latency driven.
1208 */
1209 if (packets && packets < 4 && bytes < 9000 &&
1210 (q_vector->tx.target_itr & I40E_ITR_ADAPTIVE_LATENCY)) {
1211 itr = I40E_ITR_ADAPTIVE_LATENCY;
1212 goto adjust_by_size;
1213 }
1214 } else if (packets < 4) {
1215 /* If we have Tx and Rx ITR maxed and Tx ITR is running in
1216 * bulk mode and we are receiving 4 or fewer packets just
1217 * reset the ITR_ADAPTIVE_LATENCY bit for latency mode so
1218 * that the Rx can relax.
1219 */
1220 if (rc->target_itr == I40E_ITR_ADAPTIVE_MAX_USECS &&
1221 (q_vector->rx.target_itr & I40E_ITR_MASK) ==
1222 I40E_ITR_ADAPTIVE_MAX_USECS)
1223 goto clear_counts;
1224 } else if (packets > 32) {
1225 /* If we have processed over 32 packets in a single interrupt
1226 * for Tx assume we need to switch over to "bulk" mode.
1227 */
1228 rc->target_itr &= ~I40E_ITR_ADAPTIVE_LATENCY;
1229 }
1230
1231 /* We have no packets to actually measure against. This means
1232 * either one of the other queues on this vector is active or
1233 * we are a Tx queue doing TSO with too high of an interrupt rate.
1234 *
1235 * Between 4 and 56 we can assume that our current interrupt delay
1236 * is only slightly too low. As such we should increase it by a small
1237 * fixed amount.
1238 */
1239 if (packets < 56) {
1240 itr = rc->target_itr + I40E_ITR_ADAPTIVE_MIN_INC;
1241 if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) {
1242 itr &= I40E_ITR_ADAPTIVE_LATENCY;
1243 itr += I40E_ITR_ADAPTIVE_MAX_USECS;
1244 }
1245 goto clear_counts;
1246 }
1247
1248 if (packets <= 256) {
1249 itr = min(q_vector->tx.current_itr, q_vector->rx.current_itr);
1250 itr &= I40E_ITR_MASK;
1251
1252 /* Between 56 and 112 is our "goldilocks" zone where we are
1253 * working out "just right". Just report that our current
1254 * ITR is good for us.
1255 */
1256 if (packets <= 112)
1257 goto clear_counts;
1258
1259 /* If packet count is 128 or greater we are likely looking
1260 * at a slight overrun of the delay we want. Try halving
1261 * our delay to see if that will cut the number of packets
1262 * in half per interrupt.
1263 */
1264 itr /= 2;
1265 itr &= I40E_ITR_MASK;
1266 if (itr < I40E_ITR_ADAPTIVE_MIN_USECS)
1267 itr = I40E_ITR_ADAPTIVE_MIN_USECS;
1268
1269 goto clear_counts;
1270 }
1271
1272 /* The paths below assume we are dealing with a bulk ITR since
1273 * number of packets is greater than 256. We are just going to have
1274 * to compute a value and try to bring the count under control,
1275 * though for smaller packet sizes there isn't much we can do as
1276 * NAPI polling will likely be kicking in sooner rather than later.
1277 */
1278 itr = I40E_ITR_ADAPTIVE_BULK;
1279
1280adjust_by_size:
1281 /* If packet counts are 256 or greater we can assume we have a gross
1282 * overestimation of what the rate should be. Instead of trying to fine
1283 * tune it just use the formula below to try and dial in an exact value
1284 * give the current packet size of the frame.
1285 */
1286 avg_wire_size = bytes / packets;
1287
1288 /* The following is a crude approximation of:
1289 * wmem_default / (size + overhead) = desired_pkts_per_int
1290 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate
1291 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
1292 *
1293 * Assuming wmem_default is 212992 and overhead is 640 bytes per
1294 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
1295 * formula down to
1296 *
1297 * (170 * (size + 24)) / (size + 640) = ITR
1298 *
1299 * We first do some math on the packet size and then finally bitshift
1300 * by 8 after rounding up. We also have to account for PCIe link speed
1301 * difference as ITR scales based on this.
1302 */
1303 if (avg_wire_size <= 60) {
1304 /* Start at 250k ints/sec */
1305 avg_wire_size = 4096;
1306 } else if (avg_wire_size <= 380) {
1307 /* 250K ints/sec to 60K ints/sec */
1308 avg_wire_size *= 40;
1309 avg_wire_size += 1696;
1310 } else if (avg_wire_size <= 1084) {
1311 /* 60K ints/sec to 36K ints/sec */
1312 avg_wire_size *= 15;
1313 avg_wire_size += 11452;
1314 } else if (avg_wire_size <= 1980) {
1315 /* 36K ints/sec to 30K ints/sec */
1316 avg_wire_size *= 5;
1317 avg_wire_size += 22420;
1318 } else {
1319 /* plateau at a limit of 30K ints/sec */
1320 avg_wire_size = 32256;
1321 }
1322
1323 /* If we are in low latency mode halve our delay which doubles the
1324 * rate to somewhere between 100K to 16K ints/sec
1325 */
1326 if (itr & I40E_ITR_ADAPTIVE_LATENCY)
1327 avg_wire_size /= 2;
1328
1329 /* Resultant value is 256 times larger than it needs to be. This
1330 * gives us room to adjust the value as needed to either increase
1331 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc.
1332 *
1333 * Use addition as we have already recorded the new latency flag
1334 * for the ITR value.
1335 */
1336 itr += DIV_ROUND_UP(avg_wire_size, i40e_itr_divisor(q_vector)) *
1337 I40E_ITR_ADAPTIVE_MIN_INC;
1338
1339 if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) {
1340 itr &= I40E_ITR_ADAPTIVE_LATENCY;
1341 itr += I40E_ITR_ADAPTIVE_MAX_USECS;
1342 }
1343
1344clear_counts:
1345 /* write back value */
1346 rc->target_itr = itr;
1347
1348 /* next update should occur within next jiffy */
1349 rc->next_update = next_update + 1;
1350
1351 rc->total_bytes = 0;
1352 rc->total_packets = 0;
1353}
1354
1355static struct i40e_rx_buffer *i40e_rx_bi(struct i40e_ring *rx_ring, u32 idx)
1356{
1357 return &rx_ring->rx_bi[idx];
1358}
1359
1360/**
1361 * i40e_reuse_rx_page - page flip buffer and store it back on the ring
1362 * @rx_ring: rx descriptor ring to store buffers on
1363 * @old_buff: donor buffer to have page reused
1364 *
1365 * Synchronizes page for reuse by the adapter
1366 **/
1367static void i40e_reuse_rx_page(struct i40e_ring *rx_ring,
1368 struct i40e_rx_buffer *old_buff)
1369{
1370 struct i40e_rx_buffer *new_buff;
1371 u16 nta = rx_ring->next_to_alloc;
1372
1373 new_buff = i40e_rx_bi(rx_ring, nta);
1374
1375 /* update, and store next to alloc */
1376 nta++;
1377 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1378
1379 /* transfer page from old buffer to new buffer */
1380 new_buff->dma = old_buff->dma;
1381 new_buff->page = old_buff->page;
1382 new_buff->page_offset = old_buff->page_offset;
1383 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
1384
1385 rx_ring->rx_stats.page_reuse_count++;
1386
1387 /* clear contents of buffer_info */
1388 old_buff->page = NULL;
1389}
1390
1391/**
1392 * i40e_clean_programming_status - clean the programming status descriptor
1393 * @rx_ring: the rx ring that has this descriptor
1394 * @qword0_raw: qword0
1395 * @qword1: qword1 representing status_error_len in CPU ordering
1396 *
1397 * Flow director should handle FD_FILTER_STATUS to check its filter programming
1398 * status being successful or not and take actions accordingly. FCoE should
1399 * handle its context/filter programming/invalidation status and take actions.
1400 *
1401 * Returns an i40e_rx_buffer to reuse if the cleanup occurred, otherwise NULL.
1402 **/
1403void i40e_clean_programming_status(struct i40e_ring *rx_ring, u64 qword0_raw,
1404 u64 qword1)
1405{
1406 u8 id;
1407
1408 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
1409 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
1410
1411 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)
1412 i40e_fd_handle_status(rx_ring, qword0_raw, qword1, id);
1413}
1414
1415/**
1416 * i40e_setup_tx_descriptors - Allocate the Tx descriptors
1417 * @tx_ring: the tx ring to set up
1418 *
1419 * Return 0 on success, negative on error
1420 **/
1421int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring)
1422{
1423 struct device *dev = tx_ring->dev;
1424 int bi_size;
1425
1426 if (!dev)
1427 return -ENOMEM;
1428
1429 /* warn if we are about to overwrite the pointer */
1430 WARN_ON(tx_ring->tx_bi);
1431 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
1432 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
1433 if (!tx_ring->tx_bi)
1434 goto err;
1435
1436 if (ring_is_xdp(tx_ring)) {
1437 tx_ring->xsk_descs = kcalloc(I40E_MAX_NUM_DESCRIPTORS, sizeof(*tx_ring->xsk_descs),
1438 GFP_KERNEL);
1439 if (!tx_ring->xsk_descs)
1440 goto err;
1441 }
1442
1443 u64_stats_init(&tx_ring->syncp);
1444
1445 /* round up to nearest 4K */
1446 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
1447 /* add u32 for head writeback, align after this takes care of
1448 * guaranteeing this is at least one cache line in size
1449 */
1450 tx_ring->size += sizeof(u32);
1451 tx_ring->size = ALIGN(tx_ring->size, 4096);
1452 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1453 &tx_ring->dma, GFP_KERNEL);
1454 if (!tx_ring->desc) {
1455 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
1456 tx_ring->size);
1457 goto err;
1458 }
1459
1460 tx_ring->next_to_use = 0;
1461 tx_ring->next_to_clean = 0;
1462 tx_ring->tx_stats.prev_pkt_ctr = -1;
1463 return 0;
1464
1465err:
1466 kfree(tx_ring->xsk_descs);
1467 tx_ring->xsk_descs = NULL;
1468 kfree(tx_ring->tx_bi);
1469 tx_ring->tx_bi = NULL;
1470 return -ENOMEM;
1471}
1472
1473int i40e_alloc_rx_bi(struct i40e_ring *rx_ring)
1474{
1475 unsigned long sz = sizeof(*rx_ring->rx_bi) * rx_ring->count;
1476
1477 rx_ring->rx_bi = kzalloc(sz, GFP_KERNEL);
1478 return rx_ring->rx_bi ? 0 : -ENOMEM;
1479}
1480
1481static void i40e_clear_rx_bi(struct i40e_ring *rx_ring)
1482{
1483 memset(rx_ring->rx_bi, 0, sizeof(*rx_ring->rx_bi) * rx_ring->count);
1484}
1485
1486/**
1487 * i40e_clean_rx_ring - Free Rx buffers
1488 * @rx_ring: ring to be cleaned
1489 **/
1490void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
1491{
1492 u16 i;
1493
1494 /* ring already cleared, nothing to do */
1495 if (!rx_ring->rx_bi)
1496 return;
1497
1498 if (rx_ring->skb) {
1499 dev_kfree_skb(rx_ring->skb);
1500 rx_ring->skb = NULL;
1501 }
1502
1503 if (rx_ring->xsk_pool) {
1504 i40e_xsk_clean_rx_ring(rx_ring);
1505 goto skip_free;
1506 }
1507
1508 /* Free all the Rx ring sk_buffs */
1509 for (i = 0; i < rx_ring->count; i++) {
1510 struct i40e_rx_buffer *rx_bi = i40e_rx_bi(rx_ring, i);
1511
1512 if (!rx_bi->page)
1513 continue;
1514
1515 /* Invalidate cache lines that may have been written to by
1516 * device so that we avoid corrupting memory.
1517 */
1518 dma_sync_single_range_for_cpu(rx_ring->dev,
1519 rx_bi->dma,
1520 rx_bi->page_offset,
1521 rx_ring->rx_buf_len,
1522 DMA_FROM_DEVICE);
1523
1524 /* free resources associated with mapping */
1525 dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma,
1526 i40e_rx_pg_size(rx_ring),
1527 DMA_FROM_DEVICE,
1528 I40E_RX_DMA_ATTR);
1529
1530 __page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias);
1531
1532 rx_bi->page = NULL;
1533 rx_bi->page_offset = 0;
1534 }
1535
1536skip_free:
1537 if (rx_ring->xsk_pool)
1538 i40e_clear_rx_bi_zc(rx_ring);
1539 else
1540 i40e_clear_rx_bi(rx_ring);
1541
1542 /* Zero out the descriptor ring */
1543 memset(rx_ring->desc, 0, rx_ring->size);
1544
1545 rx_ring->next_to_alloc = 0;
1546 rx_ring->next_to_clean = 0;
1547 rx_ring->next_to_use = 0;
1548}
1549
1550/**
1551 * i40e_free_rx_resources - Free Rx resources
1552 * @rx_ring: ring to clean the resources from
1553 *
1554 * Free all receive software resources
1555 **/
1556void i40e_free_rx_resources(struct i40e_ring *rx_ring)
1557{
1558 i40e_clean_rx_ring(rx_ring);
1559 if (rx_ring->vsi->type == I40E_VSI_MAIN)
1560 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
1561 rx_ring->xdp_prog = NULL;
1562 kfree(rx_ring->rx_bi);
1563 rx_ring->rx_bi = NULL;
1564
1565 if (rx_ring->desc) {
1566 dma_free_coherent(rx_ring->dev, rx_ring->size,
1567 rx_ring->desc, rx_ring->dma);
1568 rx_ring->desc = NULL;
1569 }
1570}
1571
1572/**
1573 * i40e_setup_rx_descriptors - Allocate Rx descriptors
1574 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1575 *
1576 * Returns 0 on success, negative on failure
1577 **/
1578int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
1579{
1580 struct device *dev = rx_ring->dev;
1581 int err;
1582
1583 u64_stats_init(&rx_ring->syncp);
1584
1585 /* Round up to nearest 4K */
1586 rx_ring->size = rx_ring->count * sizeof(union i40e_rx_desc);
1587 rx_ring->size = ALIGN(rx_ring->size, 4096);
1588 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1589 &rx_ring->dma, GFP_KERNEL);
1590
1591 if (!rx_ring->desc) {
1592 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
1593 rx_ring->size);
1594 return -ENOMEM;
1595 }
1596
1597 rx_ring->next_to_alloc = 0;
1598 rx_ring->next_to_clean = 0;
1599 rx_ring->next_to_use = 0;
1600
1601 /* XDP RX-queue info only needed for RX rings exposed to XDP */
1602 if (rx_ring->vsi->type == I40E_VSI_MAIN) {
1603 err = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev,
1604 rx_ring->queue_index, rx_ring->q_vector->napi.napi_id);
1605 if (err < 0)
1606 return err;
1607 }
1608
1609 rx_ring->xdp_prog = rx_ring->vsi->xdp_prog;
1610
1611 return 0;
1612}
1613
1614/**
1615 * i40e_release_rx_desc - Store the new tail and head values
1616 * @rx_ring: ring to bump
1617 * @val: new head index
1618 **/
1619void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
1620{
1621 rx_ring->next_to_use = val;
1622
1623 /* update next to alloc since we have filled the ring */
1624 rx_ring->next_to_alloc = val;
1625
1626 /* Force memory writes to complete before letting h/w
1627 * know there are new descriptors to fetch. (Only
1628 * applicable for weak-ordered memory model archs,
1629 * such as IA-64).
1630 */
1631 wmb();
1632 writel(val, rx_ring->tail);
1633}
1634
1635static unsigned int i40e_rx_frame_truesize(struct i40e_ring *rx_ring,
1636 unsigned int size)
1637{
1638 unsigned int truesize;
1639
1640#if (PAGE_SIZE < 8192)
1641 truesize = i40e_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */
1642#else
1643 truesize = rx_ring->rx_offset ?
1644 SKB_DATA_ALIGN(size + rx_ring->rx_offset) +
1645 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
1646 SKB_DATA_ALIGN(size);
1647#endif
1648 return truesize;
1649}
1650
1651/**
1652 * i40e_alloc_mapped_page - recycle or make a new page
1653 * @rx_ring: ring to use
1654 * @bi: rx_buffer struct to modify
1655 *
1656 * Returns true if the page was successfully allocated or
1657 * reused.
1658 **/
1659static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring,
1660 struct i40e_rx_buffer *bi)
1661{
1662 struct page *page = bi->page;
1663 dma_addr_t dma;
1664
1665 /* since we are recycling buffers we should seldom need to alloc */
1666 if (likely(page)) {
1667 rx_ring->rx_stats.page_reuse_count++;
1668 return true;
1669 }
1670
1671 /* alloc new page for storage */
1672 page = dev_alloc_pages(i40e_rx_pg_order(rx_ring));
1673 if (unlikely(!page)) {
1674 rx_ring->rx_stats.alloc_page_failed++;
1675 return false;
1676 }
1677
1678 /* map page for use */
1679 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1680 i40e_rx_pg_size(rx_ring),
1681 DMA_FROM_DEVICE,
1682 I40E_RX_DMA_ATTR);
1683
1684 /* if mapping failed free memory back to system since
1685 * there isn't much point in holding memory we can't use
1686 */
1687 if (dma_mapping_error(rx_ring->dev, dma)) {
1688 __free_pages(page, i40e_rx_pg_order(rx_ring));
1689 rx_ring->rx_stats.alloc_page_failed++;
1690 return false;
1691 }
1692
1693 bi->dma = dma;
1694 bi->page = page;
1695 bi->page_offset = rx_ring->rx_offset;
1696 page_ref_add(page, USHRT_MAX - 1);
1697 bi->pagecnt_bias = USHRT_MAX;
1698
1699 return true;
1700}
1701
1702/**
1703 * i40e_alloc_rx_buffers - Replace used receive buffers
1704 * @rx_ring: ring to place buffers on
1705 * @cleaned_count: number of buffers to replace
1706 *
1707 * Returns false if all allocations were successful, true if any fail
1708 **/
1709bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
1710{
1711 u16 ntu = rx_ring->next_to_use;
1712 union i40e_rx_desc *rx_desc;
1713 struct i40e_rx_buffer *bi;
1714
1715 /* do nothing if no valid netdev defined */
1716 if (!rx_ring->netdev || !cleaned_count)
1717 return false;
1718
1719 rx_desc = I40E_RX_DESC(rx_ring, ntu);
1720 bi = i40e_rx_bi(rx_ring, ntu);
1721
1722 do {
1723 if (!i40e_alloc_mapped_page(rx_ring, bi))
1724 goto no_buffers;
1725
1726 /* sync the buffer for use by the device */
1727 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
1728 bi->page_offset,
1729 rx_ring->rx_buf_len,
1730 DMA_FROM_DEVICE);
1731
1732 /* Refresh the desc even if buffer_addrs didn't change
1733 * because each write-back erases this info.
1734 */
1735 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1736
1737 rx_desc++;
1738 bi++;
1739 ntu++;
1740 if (unlikely(ntu == rx_ring->count)) {
1741 rx_desc = I40E_RX_DESC(rx_ring, 0);
1742 bi = i40e_rx_bi(rx_ring, 0);
1743 ntu = 0;
1744 }
1745
1746 /* clear the status bits for the next_to_use descriptor */
1747 rx_desc->wb.qword1.status_error_len = 0;
1748
1749 cleaned_count--;
1750 } while (cleaned_count);
1751
1752 if (rx_ring->next_to_use != ntu)
1753 i40e_release_rx_desc(rx_ring, ntu);
1754
1755 return false;
1756
1757no_buffers:
1758 if (rx_ring->next_to_use != ntu)
1759 i40e_release_rx_desc(rx_ring, ntu);
1760
1761 /* make sure to come back via polling to try again after
1762 * allocation failure
1763 */
1764 return true;
1765}
1766
1767/**
1768 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
1769 * @vsi: the VSI we care about
1770 * @skb: skb currently being received and modified
1771 * @rx_desc: the receive descriptor
1772 **/
1773static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
1774 struct sk_buff *skb,
1775 union i40e_rx_desc *rx_desc)
1776{
1777 struct i40e_rx_ptype_decoded decoded;
1778 u32 rx_error, rx_status;
1779 bool ipv4, ipv6;
1780 u8 ptype;
1781 u64 qword;
1782
1783 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1784 ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT;
1785 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1786 I40E_RXD_QW1_ERROR_SHIFT;
1787 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1788 I40E_RXD_QW1_STATUS_SHIFT;
1789 decoded = decode_rx_desc_ptype(ptype);
1790
1791 skb->ip_summed = CHECKSUM_NONE;
1792
1793 skb_checksum_none_assert(skb);
1794
1795 /* Rx csum enabled and ip headers found? */
1796 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
1797 return;
1798
1799 /* did the hardware decode the packet and checksum? */
1800 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
1801 return;
1802
1803 /* both known and outer_ip must be set for the below code to work */
1804 if (!(decoded.known && decoded.outer_ip))
1805 return;
1806
1807 ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
1808 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4);
1809 ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
1810 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6);
1811
1812 if (ipv4 &&
1813 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
1814 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
1815 goto checksum_fail;
1816
1817 /* likely incorrect csum if alternate IP extension headers found */
1818 if (ipv6 &&
1819 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
1820 /* don't increment checksum err here, non-fatal err */
1821 return;
1822
1823 /* there was some L4 error, count error and punt packet to the stack */
1824 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
1825 goto checksum_fail;
1826
1827 /* handle packets that were not able to be checksummed due
1828 * to arrival speed, in this case the stack can compute
1829 * the csum.
1830 */
1831 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
1832 return;
1833
1834 /* If there is an outer header present that might contain a checksum
1835 * we need to bump the checksum level by 1 to reflect the fact that
1836 * we are indicating we validated the inner checksum.
1837 */
1838 if (decoded.tunnel_type >= I40E_RX_PTYPE_TUNNEL_IP_GRENAT)
1839 skb->csum_level = 1;
1840
1841 /* Only report checksum unnecessary for TCP, UDP, or SCTP */
1842 switch (decoded.inner_prot) {
1843 case I40E_RX_PTYPE_INNER_PROT_TCP:
1844 case I40E_RX_PTYPE_INNER_PROT_UDP:
1845 case I40E_RX_PTYPE_INNER_PROT_SCTP:
1846 skb->ip_summed = CHECKSUM_UNNECESSARY;
1847 fallthrough;
1848 default:
1849 break;
1850 }
1851
1852 return;
1853
1854checksum_fail:
1855 vsi->back->hw_csum_rx_error++;
1856}
1857
1858/**
1859 * i40e_ptype_to_htype - get a hash type
1860 * @ptype: the ptype value from the descriptor
1861 *
1862 * Returns a hash type to be used by skb_set_hash
1863 **/
1864static inline int i40e_ptype_to_htype(u8 ptype)
1865{
1866 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
1867
1868 if (!decoded.known)
1869 return PKT_HASH_TYPE_NONE;
1870
1871 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1872 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
1873 return PKT_HASH_TYPE_L4;
1874 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1875 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
1876 return PKT_HASH_TYPE_L3;
1877 else
1878 return PKT_HASH_TYPE_L2;
1879}
1880
1881/**
1882 * i40e_rx_hash - set the hash value in the skb
1883 * @ring: descriptor ring
1884 * @rx_desc: specific descriptor
1885 * @skb: skb currently being received and modified
1886 * @rx_ptype: Rx packet type
1887 **/
1888static inline void i40e_rx_hash(struct i40e_ring *ring,
1889 union i40e_rx_desc *rx_desc,
1890 struct sk_buff *skb,
1891 u8 rx_ptype)
1892{
1893 u32 hash;
1894 const __le64 rss_mask =
1895 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
1896 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
1897
1898 if (!(ring->netdev->features & NETIF_F_RXHASH))
1899 return;
1900
1901 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
1902 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
1903 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
1904 }
1905}
1906
1907/**
1908 * i40e_process_skb_fields - Populate skb header fields from Rx descriptor
1909 * @rx_ring: rx descriptor ring packet is being transacted on
1910 * @rx_desc: pointer to the EOP Rx descriptor
1911 * @skb: pointer to current skb being populated
1912 *
1913 * This function checks the ring, descriptor, and packet information in
1914 * order to populate the hash, checksum, VLAN, protocol, and
1915 * other fields within the skb.
1916 **/
1917void i40e_process_skb_fields(struct i40e_ring *rx_ring,
1918 union i40e_rx_desc *rx_desc, struct sk_buff *skb)
1919{
1920 u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1921 u32 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1922 I40E_RXD_QW1_STATUS_SHIFT;
1923 u32 tsynvalid = rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK;
1924 u32 tsyn = (rx_status & I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1925 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT;
1926 u8 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1927 I40E_RXD_QW1_PTYPE_SHIFT;
1928
1929 if (unlikely(tsynvalid))
1930 i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, tsyn);
1931
1932 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1933
1934 i40e_rx_checksum(rx_ring->vsi, skb, rx_desc);
1935
1936 skb_record_rx_queue(skb, rx_ring->queue_index);
1937
1938 if (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1939 __le16 vlan_tag = rx_desc->wb.qword0.lo_dword.l2tag1;
1940
1941 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1942 le16_to_cpu(vlan_tag));
1943 }
1944
1945 /* modifies the skb - consumes the enet header */
1946 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1947}
1948
1949/**
1950 * i40e_cleanup_headers - Correct empty headers
1951 * @rx_ring: rx descriptor ring packet is being transacted on
1952 * @skb: pointer to current skb being fixed
1953 * @rx_desc: pointer to the EOP Rx descriptor
1954 *
1955 * In addition if skb is not at least 60 bytes we need to pad it so that
1956 * it is large enough to qualify as a valid Ethernet frame.
1957 *
1958 * Returns true if an error was encountered and skb was freed.
1959 **/
1960static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb,
1961 union i40e_rx_desc *rx_desc)
1962
1963{
1964 /* ERR_MASK will only have valid bits if EOP set, and
1965 * what we are doing here is actually checking
1966 * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in
1967 * the error field
1968 */
1969 if (unlikely(i40e_test_staterr(rx_desc,
1970 BIT(I40E_RXD_QW1_ERROR_SHIFT)))) {
1971 dev_kfree_skb_any(skb);
1972 return true;
1973 }
1974
1975 /* if eth_skb_pad returns an error the skb was freed */
1976 if (eth_skb_pad(skb))
1977 return true;
1978
1979 return false;
1980}
1981
1982/**
1983 * i40e_can_reuse_rx_page - Determine if page can be reused for another Rx
1984 * @rx_buffer: buffer containing the page
1985 * @rx_buffer_pgcnt: buffer page refcount pre xdp_do_redirect() call
1986 *
1987 * If page is reusable, we have a green light for calling i40e_reuse_rx_page,
1988 * which will assign the current buffer to the buffer that next_to_alloc is
1989 * pointing to; otherwise, the DMA mapping needs to be destroyed and
1990 * page freed
1991 */
1992static bool i40e_can_reuse_rx_page(struct i40e_rx_buffer *rx_buffer,
1993 int rx_buffer_pgcnt)
1994{
1995 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1996 struct page *page = rx_buffer->page;
1997
1998 /* Is any reuse possible? */
1999 if (!dev_page_is_reusable(page))
2000 return false;
2001
2002#if (PAGE_SIZE < 8192)
2003 /* if we are only owner of page we can reuse it */
2004 if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1))
2005 return false;
2006#else
2007#define I40E_LAST_OFFSET \
2008 (SKB_WITH_OVERHEAD(PAGE_SIZE) - I40E_RXBUFFER_2048)
2009 if (rx_buffer->page_offset > I40E_LAST_OFFSET)
2010 return false;
2011#endif
2012
2013 /* If we have drained the page fragment pool we need to update
2014 * the pagecnt_bias and page count so that we fully restock the
2015 * number of references the driver holds.
2016 */
2017 if (unlikely(pagecnt_bias == 1)) {
2018 page_ref_add(page, USHRT_MAX - 1);
2019 rx_buffer->pagecnt_bias = USHRT_MAX;
2020 }
2021
2022 return true;
2023}
2024
2025/**
2026 * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff
2027 * @rx_ring: rx descriptor ring to transact packets on
2028 * @rx_buffer: buffer containing page to add
2029 * @skb: sk_buff to place the data into
2030 * @size: packet length from rx_desc
2031 *
2032 * This function will add the data contained in rx_buffer->page to the skb.
2033 * It will just attach the page as a frag to the skb.
2034 *
2035 * The function will then update the page offset.
2036 **/
2037static void i40e_add_rx_frag(struct i40e_ring *rx_ring,
2038 struct i40e_rx_buffer *rx_buffer,
2039 struct sk_buff *skb,
2040 unsigned int size)
2041{
2042#if (PAGE_SIZE < 8192)
2043 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
2044#else
2045 unsigned int truesize = SKB_DATA_ALIGN(size + rx_ring->rx_offset);
2046#endif
2047
2048 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
2049 rx_buffer->page_offset, size, truesize);
2050
2051 /* page is being used so we must update the page offset */
2052#if (PAGE_SIZE < 8192)
2053 rx_buffer->page_offset ^= truesize;
2054#else
2055 rx_buffer->page_offset += truesize;
2056#endif
2057}
2058
2059/**
2060 * i40e_get_rx_buffer - Fetch Rx buffer and synchronize data for use
2061 * @rx_ring: rx descriptor ring to transact packets on
2062 * @size: size of buffer to add to skb
2063 * @rx_buffer_pgcnt: buffer page refcount
2064 *
2065 * This function will pull an Rx buffer from the ring and synchronize it
2066 * for use by the CPU.
2067 */
2068static struct i40e_rx_buffer *i40e_get_rx_buffer(struct i40e_ring *rx_ring,
2069 const unsigned int size,
2070 int *rx_buffer_pgcnt)
2071{
2072 struct i40e_rx_buffer *rx_buffer;
2073
2074 rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_clean);
2075 *rx_buffer_pgcnt =
2076#if (PAGE_SIZE < 8192)
2077 page_count(rx_buffer->page);
2078#else
2079 0;
2080#endif
2081 prefetch_page_address(rx_buffer->page);
2082
2083 /* we are reusing so sync this buffer for CPU use */
2084 dma_sync_single_range_for_cpu(rx_ring->dev,
2085 rx_buffer->dma,
2086 rx_buffer->page_offset,
2087 size,
2088 DMA_FROM_DEVICE);
2089
2090 /* We have pulled a buffer for use, so decrement pagecnt_bias */
2091 rx_buffer->pagecnt_bias--;
2092
2093 return rx_buffer;
2094}
2095
2096/**
2097 * i40e_construct_skb - Allocate skb and populate it
2098 * @rx_ring: rx descriptor ring to transact packets on
2099 * @rx_buffer: rx buffer to pull data from
2100 * @xdp: xdp_buff pointing to the data
2101 *
2102 * This function allocates an skb. It then populates it with the page
2103 * data from the current receive descriptor, taking care to set up the
2104 * skb correctly.
2105 */
2106static struct sk_buff *i40e_construct_skb(struct i40e_ring *rx_ring,
2107 struct i40e_rx_buffer *rx_buffer,
2108 struct xdp_buff *xdp)
2109{
2110 unsigned int size = xdp->data_end - xdp->data;
2111#if (PAGE_SIZE < 8192)
2112 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
2113#else
2114 unsigned int truesize = SKB_DATA_ALIGN(size);
2115#endif
2116 unsigned int headlen;
2117 struct sk_buff *skb;
2118
2119 /* prefetch first cache line of first page */
2120 net_prefetch(xdp->data);
2121
2122 /* Note, we get here by enabling legacy-rx via:
2123 *
2124 * ethtool --set-priv-flags <dev> legacy-rx on
2125 *
2126 * In this mode, we currently get 0 extra XDP headroom as
2127 * opposed to having legacy-rx off, where we process XDP
2128 * packets going to stack via i40e_build_skb(). The latter
2129 * provides us currently with 192 bytes of headroom.
2130 *
2131 * For i40e_construct_skb() mode it means that the
2132 * xdp->data_meta will always point to xdp->data, since
2133 * the helper cannot expand the head. Should this ever
2134 * change in future for legacy-rx mode on, then lets also
2135 * add xdp->data_meta handling here.
2136 */
2137
2138 /* allocate a skb to store the frags */
2139 skb = __napi_alloc_skb(&rx_ring->q_vector->napi,
2140 I40E_RX_HDR_SIZE,
2141 GFP_ATOMIC | __GFP_NOWARN);
2142 if (unlikely(!skb))
2143 return NULL;
2144
2145 /* Determine available headroom for copy */
2146 headlen = size;
2147 if (headlen > I40E_RX_HDR_SIZE)
2148 headlen = eth_get_headlen(skb->dev, xdp->data,
2149 I40E_RX_HDR_SIZE);
2150
2151 /* align pull length to size of long to optimize memcpy performance */
2152 memcpy(__skb_put(skb, headlen), xdp->data,
2153 ALIGN(headlen, sizeof(long)));
2154
2155 /* update all of the pointers */
2156 size -= headlen;
2157 if (size) {
2158 skb_add_rx_frag(skb, 0, rx_buffer->page,
2159 rx_buffer->page_offset + headlen,
2160 size, truesize);
2161
2162 /* buffer is used by skb, update page_offset */
2163#if (PAGE_SIZE < 8192)
2164 rx_buffer->page_offset ^= truesize;
2165#else
2166 rx_buffer->page_offset += truesize;
2167#endif
2168 } else {
2169 /* buffer is unused, reset bias back to rx_buffer */
2170 rx_buffer->pagecnt_bias++;
2171 }
2172
2173 return skb;
2174}
2175
2176/**
2177 * i40e_build_skb - Build skb around an existing buffer
2178 * @rx_ring: Rx descriptor ring to transact packets on
2179 * @rx_buffer: Rx buffer to pull data from
2180 * @xdp: xdp_buff pointing to the data
2181 *
2182 * This function builds an skb around an existing Rx buffer, taking care
2183 * to set up the skb correctly and avoid any memcpy overhead.
2184 */
2185static struct sk_buff *i40e_build_skb(struct i40e_ring *rx_ring,
2186 struct i40e_rx_buffer *rx_buffer,
2187 struct xdp_buff *xdp)
2188{
2189 unsigned int metasize = xdp->data - xdp->data_meta;
2190#if (PAGE_SIZE < 8192)
2191 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
2192#else
2193 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
2194 SKB_DATA_ALIGN(xdp->data_end -
2195 xdp->data_hard_start);
2196#endif
2197 struct sk_buff *skb;
2198
2199 /* Prefetch first cache line of first page. If xdp->data_meta
2200 * is unused, this points exactly as xdp->data, otherwise we
2201 * likely have a consumer accessing first few bytes of meta
2202 * data, and then actual data.
2203 */
2204 net_prefetch(xdp->data_meta);
2205
2206 /* build an skb around the page buffer */
2207 skb = build_skb(xdp->data_hard_start, truesize);
2208 if (unlikely(!skb))
2209 return NULL;
2210
2211 /* update pointers within the skb to store the data */
2212 skb_reserve(skb, xdp->data - xdp->data_hard_start);
2213 __skb_put(skb, xdp->data_end - xdp->data);
2214 if (metasize)
2215 skb_metadata_set(skb, metasize);
2216
2217 /* buffer is used by skb, update page_offset */
2218#if (PAGE_SIZE < 8192)
2219 rx_buffer->page_offset ^= truesize;
2220#else
2221 rx_buffer->page_offset += truesize;
2222#endif
2223
2224 return skb;
2225}
2226
2227/**
2228 * i40e_put_rx_buffer - Clean up used buffer and either recycle or free
2229 * @rx_ring: rx descriptor ring to transact packets on
2230 * @rx_buffer: rx buffer to pull data from
2231 * @rx_buffer_pgcnt: rx buffer page refcount pre xdp_do_redirect() call
2232 *
2233 * This function will clean up the contents of the rx_buffer. It will
2234 * either recycle the buffer or unmap it and free the associated resources.
2235 */
2236static void i40e_put_rx_buffer(struct i40e_ring *rx_ring,
2237 struct i40e_rx_buffer *rx_buffer,
2238 int rx_buffer_pgcnt)
2239{
2240 if (i40e_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) {
2241 /* hand second half of page back to the ring */
2242 i40e_reuse_rx_page(rx_ring, rx_buffer);
2243 } else {
2244 /* we are not reusing the buffer so unmap it */
2245 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
2246 i40e_rx_pg_size(rx_ring),
2247 DMA_FROM_DEVICE, I40E_RX_DMA_ATTR);
2248 __page_frag_cache_drain(rx_buffer->page,
2249 rx_buffer->pagecnt_bias);
2250 /* clear contents of buffer_info */
2251 rx_buffer->page = NULL;
2252 }
2253}
2254
2255/**
2256 * i40e_is_non_eop - process handling of non-EOP buffers
2257 * @rx_ring: Rx ring being processed
2258 * @rx_desc: Rx descriptor for current buffer
2259 *
2260 * If the buffer is an EOP buffer, this function exits returning false,
2261 * otherwise return true indicating that this is in fact a non-EOP buffer.
2262 */
2263static bool i40e_is_non_eop(struct i40e_ring *rx_ring,
2264 union i40e_rx_desc *rx_desc)
2265{
2266 /* if we are the last buffer then there is nothing else to do */
2267#define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)
2268 if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF)))
2269 return false;
2270
2271 rx_ring->rx_stats.non_eop_descs++;
2272
2273 return true;
2274}
2275
2276static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf,
2277 struct i40e_ring *xdp_ring);
2278
2279int i40e_xmit_xdp_tx_ring(struct xdp_buff *xdp, struct i40e_ring *xdp_ring)
2280{
2281 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
2282
2283 if (unlikely(!xdpf))
2284 return I40E_XDP_CONSUMED;
2285
2286 return i40e_xmit_xdp_ring(xdpf, xdp_ring);
2287}
2288
2289/**
2290 * i40e_run_xdp - run an XDP program
2291 * @rx_ring: Rx ring being processed
2292 * @xdp: XDP buffer containing the frame
2293 **/
2294static int i40e_run_xdp(struct i40e_ring *rx_ring, struct xdp_buff *xdp)
2295{
2296 int err, result = I40E_XDP_PASS;
2297 struct i40e_ring *xdp_ring;
2298 struct bpf_prog *xdp_prog;
2299 u32 act;
2300
2301 xdp_prog = READ_ONCE(rx_ring->xdp_prog);
2302
2303 if (!xdp_prog)
2304 goto xdp_out;
2305
2306 prefetchw(xdp->data_hard_start); /* xdp_frame write */
2307
2308 act = bpf_prog_run_xdp(xdp_prog, xdp);
2309 switch (act) {
2310 case XDP_PASS:
2311 break;
2312 case XDP_TX:
2313 xdp_ring = rx_ring->vsi->xdp_rings[rx_ring->queue_index];
2314 result = i40e_xmit_xdp_tx_ring(xdp, xdp_ring);
2315 if (result == I40E_XDP_CONSUMED)
2316 goto out_failure;
2317 break;
2318 case XDP_REDIRECT:
2319 err = xdp_do_redirect(rx_ring->netdev, xdp, xdp_prog);
2320 if (err)
2321 goto out_failure;
2322 result = I40E_XDP_REDIR;
2323 break;
2324 default:
2325 bpf_warn_invalid_xdp_action(act);
2326 fallthrough;
2327 case XDP_ABORTED:
2328out_failure:
2329 trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
2330 fallthrough; /* handle aborts by dropping packet */
2331 case XDP_DROP:
2332 result = I40E_XDP_CONSUMED;
2333 break;
2334 }
2335xdp_out:
2336 return result;
2337}
2338
2339/**
2340 * i40e_rx_buffer_flip - adjusted rx_buffer to point to an unused region
2341 * @rx_ring: Rx ring
2342 * @rx_buffer: Rx buffer to adjust
2343 * @size: Size of adjustment
2344 **/
2345static void i40e_rx_buffer_flip(struct i40e_ring *rx_ring,
2346 struct i40e_rx_buffer *rx_buffer,
2347 unsigned int size)
2348{
2349 unsigned int truesize = i40e_rx_frame_truesize(rx_ring, size);
2350
2351#if (PAGE_SIZE < 8192)
2352 rx_buffer->page_offset ^= truesize;
2353#else
2354 rx_buffer->page_offset += truesize;
2355#endif
2356}
2357
2358/**
2359 * i40e_xdp_ring_update_tail - Updates the XDP Tx ring tail register
2360 * @xdp_ring: XDP Tx ring
2361 *
2362 * This function updates the XDP Tx ring tail register.
2363 **/
2364void i40e_xdp_ring_update_tail(struct i40e_ring *xdp_ring)
2365{
2366 /* Force memory writes to complete before letting h/w
2367 * know there are new descriptors to fetch.
2368 */
2369 wmb();
2370 writel_relaxed(xdp_ring->next_to_use, xdp_ring->tail);
2371}
2372
2373/**
2374 * i40e_update_rx_stats - Update Rx ring statistics
2375 * @rx_ring: rx descriptor ring
2376 * @total_rx_bytes: number of bytes received
2377 * @total_rx_packets: number of packets received
2378 *
2379 * This function updates the Rx ring statistics.
2380 **/
2381void i40e_update_rx_stats(struct i40e_ring *rx_ring,
2382 unsigned int total_rx_bytes,
2383 unsigned int total_rx_packets)
2384{
2385 u64_stats_update_begin(&rx_ring->syncp);
2386 rx_ring->stats.packets += total_rx_packets;
2387 rx_ring->stats.bytes += total_rx_bytes;
2388 u64_stats_update_end(&rx_ring->syncp);
2389 rx_ring->q_vector->rx.total_packets += total_rx_packets;
2390 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
2391}
2392
2393/**
2394 * i40e_finalize_xdp_rx - Bump XDP Tx tail and/or flush redirect map
2395 * @rx_ring: Rx ring
2396 * @xdp_res: Result of the receive batch
2397 *
2398 * This function bumps XDP Tx tail and/or flush redirect map, and
2399 * should be called when a batch of packets has been processed in the
2400 * napi loop.
2401 **/
2402void i40e_finalize_xdp_rx(struct i40e_ring *rx_ring, unsigned int xdp_res)
2403{
2404 if (xdp_res & I40E_XDP_REDIR)
2405 xdp_do_flush_map();
2406
2407 if (xdp_res & I40E_XDP_TX) {
2408 struct i40e_ring *xdp_ring =
2409 rx_ring->vsi->xdp_rings[rx_ring->queue_index];
2410
2411 i40e_xdp_ring_update_tail(xdp_ring);
2412 }
2413}
2414
2415/**
2416 * i40e_inc_ntc: Advance the next_to_clean index
2417 * @rx_ring: Rx ring
2418 **/
2419static void i40e_inc_ntc(struct i40e_ring *rx_ring)
2420{
2421 u32 ntc = rx_ring->next_to_clean + 1;
2422
2423 ntc = (ntc < rx_ring->count) ? ntc : 0;
2424 rx_ring->next_to_clean = ntc;
2425 prefetch(I40E_RX_DESC(rx_ring, ntc));
2426}
2427
2428/**
2429 * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2430 * @rx_ring: rx descriptor ring to transact packets on
2431 * @budget: Total limit on number of packets to process
2432 *
2433 * This function provides a "bounce buffer" approach to Rx interrupt
2434 * processing. The advantage to this is that on systems that have
2435 * expensive overhead for IOMMU access this provides a means of avoiding
2436 * it by maintaining the mapping of the page to the system.
2437 *
2438 * Returns amount of work completed
2439 **/
2440static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)
2441{
2442 unsigned int total_rx_bytes = 0, total_rx_packets = 0, frame_sz = 0;
2443 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
2444 unsigned int offset = rx_ring->rx_offset;
2445 struct sk_buff *skb = rx_ring->skb;
2446 unsigned int xdp_xmit = 0;
2447 bool failure = false;
2448 struct xdp_buff xdp;
2449 int xdp_res = 0;
2450
2451#if (PAGE_SIZE < 8192)
2452 frame_sz = i40e_rx_frame_truesize(rx_ring, 0);
2453#endif
2454 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq);
2455
2456 while (likely(total_rx_packets < (unsigned int)budget)) {
2457 struct i40e_rx_buffer *rx_buffer;
2458 union i40e_rx_desc *rx_desc;
2459 int rx_buffer_pgcnt;
2460 unsigned int size;
2461 u64 qword;
2462
2463 /* return some buffers to hardware, one at a time is too slow */
2464 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
2465 failure = failure ||
2466 i40e_alloc_rx_buffers(rx_ring, cleaned_count);
2467 cleaned_count = 0;
2468 }
2469
2470 rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean);
2471
2472 /* status_error_len will always be zero for unused descriptors
2473 * because it's cleared in cleanup, and overlaps with hdr_addr
2474 * which is always zero because packet split isn't used, if the
2475 * hardware wrote DD then the length will be non-zero
2476 */
2477 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
2478
2479 /* This memory barrier is needed to keep us from reading
2480 * any other fields out of the rx_desc until we have
2481 * verified the descriptor has been written back.
2482 */
2483 dma_rmb();
2484
2485 if (i40e_rx_is_programming_status(qword)) {
2486 i40e_clean_programming_status(rx_ring,
2487 rx_desc->raw.qword[0],
2488 qword);
2489 rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_clean);
2490 i40e_inc_ntc(rx_ring);
2491 i40e_reuse_rx_page(rx_ring, rx_buffer);
2492 cleaned_count++;
2493 continue;
2494 }
2495
2496 size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
2497 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
2498 if (!size)
2499 break;
2500
2501 i40e_trace(clean_rx_irq, rx_ring, rx_desc, skb);
2502 rx_buffer = i40e_get_rx_buffer(rx_ring, size, &rx_buffer_pgcnt);
2503
2504 /* retrieve a buffer from the ring */
2505 if (!skb) {
2506 unsigned char *hard_start;
2507
2508 hard_start = page_address(rx_buffer->page) +
2509 rx_buffer->page_offset - offset;
2510 xdp_prepare_buff(&xdp, hard_start, offset, size, true);
2511#if (PAGE_SIZE > 4096)
2512 /* At larger PAGE_SIZE, frame_sz depend on len size */
2513 xdp.frame_sz = i40e_rx_frame_truesize(rx_ring, size);
2514#endif
2515 xdp_res = i40e_run_xdp(rx_ring, &xdp);
2516 }
2517
2518 if (xdp_res) {
2519 if (xdp_res & (I40E_XDP_TX | I40E_XDP_REDIR)) {
2520 xdp_xmit |= xdp_res;
2521 i40e_rx_buffer_flip(rx_ring, rx_buffer, size);
2522 } else {
2523 rx_buffer->pagecnt_bias++;
2524 }
2525 total_rx_bytes += size;
2526 total_rx_packets++;
2527 } else if (skb) {
2528 i40e_add_rx_frag(rx_ring, rx_buffer, skb, size);
2529 } else if (ring_uses_build_skb(rx_ring)) {
2530 skb = i40e_build_skb(rx_ring, rx_buffer, &xdp);
2531 } else {
2532 skb = i40e_construct_skb(rx_ring, rx_buffer, &xdp);
2533 }
2534
2535 /* exit if we failed to retrieve a buffer */
2536 if (!xdp_res && !skb) {
2537 rx_ring->rx_stats.alloc_buff_failed++;
2538 rx_buffer->pagecnt_bias++;
2539 break;
2540 }
2541
2542 i40e_put_rx_buffer(rx_ring, rx_buffer, rx_buffer_pgcnt);
2543 cleaned_count++;
2544
2545 i40e_inc_ntc(rx_ring);
2546 if (i40e_is_non_eop(rx_ring, rx_desc))
2547 continue;
2548
2549 if (xdp_res || i40e_cleanup_headers(rx_ring, skb, rx_desc)) {
2550 skb = NULL;
2551 continue;
2552 }
2553
2554 /* probably a little skewed due to removing CRC */
2555 total_rx_bytes += skb->len;
2556
2557 /* populate checksum, VLAN, and protocol */
2558 i40e_process_skb_fields(rx_ring, rx_desc, skb);
2559
2560 i40e_trace(clean_rx_irq_rx, rx_ring, rx_desc, skb);
2561 napi_gro_receive(&rx_ring->q_vector->napi, skb);
2562 skb = NULL;
2563
2564 /* update budget accounting */
2565 total_rx_packets++;
2566 }
2567
2568 i40e_finalize_xdp_rx(rx_ring, xdp_xmit);
2569 rx_ring->skb = skb;
2570
2571 i40e_update_rx_stats(rx_ring, total_rx_bytes, total_rx_packets);
2572
2573 /* guarantee a trip back through this routine if there was a failure */
2574 return failure ? budget : (int)total_rx_packets;
2575}
2576
2577static inline u32 i40e_buildreg_itr(const int type, u16 itr)
2578{
2579 u32 val;
2580
2581 /* We don't bother with setting the CLEARPBA bit as the data sheet
2582 * points out doing so is "meaningless since it was already
2583 * auto-cleared". The auto-clearing happens when the interrupt is
2584 * asserted.
2585 *
2586 * Hardware errata 28 for also indicates that writing to a
2587 * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear
2588 * an event in the PBA anyway so we need to rely on the automask
2589 * to hold pending events for us until the interrupt is re-enabled
2590 *
2591 * The itr value is reported in microseconds, and the register
2592 * value is recorded in 2 microsecond units. For this reason we
2593 * only need to shift by the interval shift - 1 instead of the
2594 * full value.
2595 */
2596 itr &= I40E_ITR_MASK;
2597
2598 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2599 (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
2600 (itr << (I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT - 1));
2601
2602 return val;
2603}
2604
2605/* a small macro to shorten up some long lines */
2606#define INTREG I40E_PFINT_DYN_CTLN
2607
2608/* The act of updating the ITR will cause it to immediately trigger. In order
2609 * to prevent this from throwing off adaptive update statistics we defer the
2610 * update so that it can only happen so often. So after either Tx or Rx are
2611 * updated we make the adaptive scheme wait until either the ITR completely
2612 * expires via the next_update expiration or we have been through at least
2613 * 3 interrupts.
2614 */
2615#define ITR_COUNTDOWN_START 3
2616
2617/**
2618 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
2619 * @vsi: the VSI we care about
2620 * @q_vector: q_vector for which itr is being updated and interrupt enabled
2621 *
2622 **/
2623static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
2624 struct i40e_q_vector *q_vector)
2625{
2626 struct i40e_hw *hw = &vsi->back->hw;
2627 u32 intval;
2628
2629 /* If we don't have MSIX, then we only need to re-enable icr0 */
2630 if (!(vsi->back->flags & I40E_FLAG_MSIX_ENABLED)) {
2631 i40e_irq_dynamic_enable_icr0(vsi->back);
2632 return;
2633 }
2634
2635 /* These will do nothing if dynamic updates are not enabled */
2636 i40e_update_itr(q_vector, &q_vector->tx);
2637 i40e_update_itr(q_vector, &q_vector->rx);
2638
2639 /* This block of logic allows us to get away with only updating
2640 * one ITR value with each interrupt. The idea is to perform a
2641 * pseudo-lazy update with the following criteria.
2642 *
2643 * 1. Rx is given higher priority than Tx if both are in same state
2644 * 2. If we must reduce an ITR that is given highest priority.
2645 * 3. We then give priority to increasing ITR based on amount.
2646 */
2647 if (q_vector->rx.target_itr < q_vector->rx.current_itr) {
2648 /* Rx ITR needs to be reduced, this is highest priority */
2649 intval = i40e_buildreg_itr(I40E_RX_ITR,
2650 q_vector->rx.target_itr);
2651 q_vector->rx.current_itr = q_vector->rx.target_itr;
2652 q_vector->itr_countdown = ITR_COUNTDOWN_START;
2653 } else if ((q_vector->tx.target_itr < q_vector->tx.current_itr) ||
2654 ((q_vector->rx.target_itr - q_vector->rx.current_itr) <
2655 (q_vector->tx.target_itr - q_vector->tx.current_itr))) {
2656 /* Tx ITR needs to be reduced, this is second priority
2657 * Tx ITR needs to be increased more than Rx, fourth priority
2658 */
2659 intval = i40e_buildreg_itr(I40E_TX_ITR,
2660 q_vector->tx.target_itr);
2661 q_vector->tx.current_itr = q_vector->tx.target_itr;
2662 q_vector->itr_countdown = ITR_COUNTDOWN_START;
2663 } else if (q_vector->rx.current_itr != q_vector->rx.target_itr) {
2664 /* Rx ITR needs to be increased, third priority */
2665 intval = i40e_buildreg_itr(I40E_RX_ITR,
2666 q_vector->rx.target_itr);
2667 q_vector->rx.current_itr = q_vector->rx.target_itr;
2668 q_vector->itr_countdown = ITR_COUNTDOWN_START;
2669 } else {
2670 /* No ITR update, lowest priority */
2671 intval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
2672 if (q_vector->itr_countdown)
2673 q_vector->itr_countdown--;
2674 }
2675
2676 if (!test_bit(__I40E_VSI_DOWN, vsi->state))
2677 wr32(hw, INTREG(q_vector->reg_idx), intval);
2678}
2679
2680/**
2681 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine
2682 * @napi: napi struct with our devices info in it
2683 * @budget: amount of work driver is allowed to do this pass, in packets
2684 *
2685 * This function will clean all queues associated with a q_vector.
2686 *
2687 * Returns the amount of work done
2688 **/
2689int i40e_napi_poll(struct napi_struct *napi, int budget)
2690{
2691 struct i40e_q_vector *q_vector =
2692 container_of(napi, struct i40e_q_vector, napi);
2693 struct i40e_vsi *vsi = q_vector->vsi;
2694 struct i40e_ring *ring;
2695 bool clean_complete = true;
2696 bool arm_wb = false;
2697 int budget_per_ring;
2698 int work_done = 0;
2699
2700 if (test_bit(__I40E_VSI_DOWN, vsi->state)) {
2701 napi_complete(napi);
2702 return 0;
2703 }
2704
2705 /* Since the actual Tx work is minimal, we can give the Tx a larger
2706 * budget and be more aggressive about cleaning up the Tx descriptors.
2707 */
2708 i40e_for_each_ring(ring, q_vector->tx) {
2709 bool wd = ring->xsk_pool ?
2710 i40e_clean_xdp_tx_irq(vsi, ring) :
2711 i40e_clean_tx_irq(vsi, ring, budget);
2712
2713 if (!wd) {
2714 clean_complete = false;
2715 continue;
2716 }
2717 arm_wb |= ring->arm_wb;
2718 ring->arm_wb = false;
2719 }
2720
2721 /* Handle case where we are called by netpoll with a budget of 0 */
2722 if (budget <= 0)
2723 goto tx_only;
2724
2725 /* normally we have 1 Rx ring per q_vector */
2726 if (unlikely(q_vector->num_ringpairs > 1))
2727 /* We attempt to distribute budget to each Rx queue fairly, but
2728 * don't allow the budget to go below 1 because that would exit
2729 * polling early.
2730 */
2731 budget_per_ring = max_t(int, budget / q_vector->num_ringpairs, 1);
2732 else
2733 /* Max of 1 Rx ring in this q_vector so give it the budget */
2734 budget_per_ring = budget;
2735
2736 i40e_for_each_ring(ring, q_vector->rx) {
2737 int cleaned = ring->xsk_pool ?
2738 i40e_clean_rx_irq_zc(ring, budget_per_ring) :
2739 i40e_clean_rx_irq(ring, budget_per_ring);
2740
2741 work_done += cleaned;
2742 /* if we clean as many as budgeted, we must not be done */
2743 if (cleaned >= budget_per_ring)
2744 clean_complete = false;
2745 }
2746
2747 /* If work not completed, return budget and polling will return */
2748 if (!clean_complete) {
2749 int cpu_id = smp_processor_id();
2750
2751 /* It is possible that the interrupt affinity has changed but,
2752 * if the cpu is pegged at 100%, polling will never exit while
2753 * traffic continues and the interrupt will be stuck on this
2754 * cpu. We check to make sure affinity is correct before we
2755 * continue to poll, otherwise we must stop polling so the
2756 * interrupt can move to the correct cpu.
2757 */
2758 if (!cpumask_test_cpu(cpu_id, &q_vector->affinity_mask)) {
2759 /* Tell napi that we are done polling */
2760 napi_complete_done(napi, work_done);
2761
2762 /* Force an interrupt */
2763 i40e_force_wb(vsi, q_vector);
2764
2765 /* Return budget-1 so that polling stops */
2766 return budget - 1;
2767 }
2768tx_only:
2769 if (arm_wb) {
2770 q_vector->tx.ring[0].tx_stats.tx_force_wb++;
2771 i40e_enable_wb_on_itr(vsi, q_vector);
2772 }
2773 return budget;
2774 }
2775
2776 if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
2777 q_vector->arm_wb_state = false;
2778
2779 /* Exit the polling mode, but don't re-enable interrupts if stack might
2780 * poll us due to busy-polling
2781 */
2782 if (likely(napi_complete_done(napi, work_done)))
2783 i40e_update_enable_itr(vsi, q_vector);
2784
2785 return min(work_done, budget - 1);
2786}
2787
2788/**
2789 * i40e_atr - Add a Flow Director ATR filter
2790 * @tx_ring: ring to add programming descriptor to
2791 * @skb: send buffer
2792 * @tx_flags: send tx flags
2793 **/
2794static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,
2795 u32 tx_flags)
2796{
2797 struct i40e_filter_program_desc *fdir_desc;
2798 struct i40e_pf *pf = tx_ring->vsi->back;
2799 union {
2800 unsigned char *network;
2801 struct iphdr *ipv4;
2802 struct ipv6hdr *ipv6;
2803 } hdr;
2804 struct tcphdr *th;
2805 unsigned int hlen;
2806 u32 flex_ptype, dtype_cmd;
2807 int l4_proto;
2808 u16 i;
2809
2810 /* make sure ATR is enabled */
2811 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
2812 return;
2813
2814 if (test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state))
2815 return;
2816
2817 /* if sampling is disabled do nothing */
2818 if (!tx_ring->atr_sample_rate)
2819 return;
2820
2821 /* Currently only IPv4/IPv6 with TCP is supported */
2822 if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6)))
2823 return;
2824
2825 /* snag network header to get L4 type and address */
2826 hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ?
2827 skb_inner_network_header(skb) : skb_network_header(skb);
2828
2829 /* Note: tx_flags gets modified to reflect inner protocols in
2830 * tx_enable_csum function if encap is enabled.
2831 */
2832 if (tx_flags & I40E_TX_FLAGS_IPV4) {
2833 /* access ihl as u8 to avoid unaligned access on ia64 */
2834 hlen = (hdr.network[0] & 0x0F) << 2;
2835 l4_proto = hdr.ipv4->protocol;
2836 } else {
2837 /* find the start of the innermost ipv6 header */
2838 unsigned int inner_hlen = hdr.network - skb->data;
2839 unsigned int h_offset = inner_hlen;
2840
2841 /* this function updates h_offset to the end of the header */
2842 l4_proto =
2843 ipv6_find_hdr(skb, &h_offset, IPPROTO_TCP, NULL, NULL);
2844 /* hlen will contain our best estimate of the tcp header */
2845 hlen = h_offset - inner_hlen;
2846 }
2847
2848 if (l4_proto != IPPROTO_TCP)
2849 return;
2850
2851 th = (struct tcphdr *)(hdr.network + hlen);
2852
2853 /* Due to lack of space, no more new filters can be programmed */
2854 if (th->syn && test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state))
2855 return;
2856 if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED) {
2857 /* HW ATR eviction will take care of removing filters on FIN
2858 * and RST packets.
2859 */
2860 if (th->fin || th->rst)
2861 return;
2862 }
2863
2864 tx_ring->atr_count++;
2865
2866 /* sample on all syn/fin/rst packets or once every atr sample rate */
2867 if (!th->fin &&
2868 !th->syn &&
2869 !th->rst &&
2870 (tx_ring->atr_count < tx_ring->atr_sample_rate))
2871 return;
2872
2873 tx_ring->atr_count = 0;
2874
2875 /* grab the next descriptor */
2876 i = tx_ring->next_to_use;
2877 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
2878
2879 i++;
2880 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2881
2882 flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
2883 I40E_TXD_FLTR_QW0_QINDEX_MASK;
2884 flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ?
2885 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP <<
2886 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :
2887 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP <<
2888 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
2889
2890 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
2891
2892 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
2893
2894 dtype_cmd |= (th->fin || th->rst) ?
2895 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
2896 I40E_TXD_FLTR_QW1_PCMD_SHIFT) :
2897 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
2898 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
2899
2900 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX <<
2901 I40E_TXD_FLTR_QW1_DEST_SHIFT;
2902
2903 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID <<
2904 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT;
2905
2906 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
2907 if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL))
2908 dtype_cmd |=
2909 ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) <<
2910 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2911 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2912 else
2913 dtype_cmd |=
2914 ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) <<
2915 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2916 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2917
2918 if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED)
2919 dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK;
2920
2921 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
2922 fdir_desc->rsvd = cpu_to_le32(0);
2923 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
2924 fdir_desc->fd_id = cpu_to_le32(0);
2925}
2926
2927/**
2928 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
2929 * @skb: send buffer
2930 * @tx_ring: ring to send buffer on
2931 * @flags: the tx flags to be set
2932 *
2933 * Checks the skb and set up correspondingly several generic transmit flags
2934 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
2935 *
2936 * Returns error code indicate the frame should be dropped upon error and the
2937 * otherwise returns 0 to indicate the flags has been set properly.
2938 **/
2939static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2940 struct i40e_ring *tx_ring,
2941 u32 *flags)
2942{
2943 __be16 protocol = skb->protocol;
2944 u32 tx_flags = 0;
2945
2946 if (protocol == htons(ETH_P_8021Q) &&
2947 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
2948 /* When HW VLAN acceleration is turned off by the user the
2949 * stack sets the protocol to 8021q so that the driver
2950 * can take any steps required to support the SW only
2951 * VLAN handling. In our case the driver doesn't need
2952 * to take any further steps so just set the protocol
2953 * to the encapsulated ethertype.
2954 */
2955 skb->protocol = vlan_get_protocol(skb);
2956 goto out;
2957 }
2958
2959 /* if we have a HW VLAN tag being added, default to the HW one */
2960 if (skb_vlan_tag_present(skb)) {
2961 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
2962 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2963 /* else if it is a SW VLAN, check the next protocol and store the tag */
2964 } else if (protocol == htons(ETH_P_8021Q)) {
2965 struct vlan_hdr *vhdr, _vhdr;
2966
2967 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
2968 if (!vhdr)
2969 return -EINVAL;
2970
2971 protocol = vhdr->h_vlan_encapsulated_proto;
2972 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
2973 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
2974 }
2975
2976 if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2977 goto out;
2978
2979 /* Insert 802.1p priority into VLAN header */
2980 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) ||
2981 (skb->priority != TC_PRIO_CONTROL)) {
2982 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK;
2983 tx_flags |= (skb->priority & 0x7) <<
2984 I40E_TX_FLAGS_VLAN_PRIO_SHIFT;
2985 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) {
2986 struct vlan_ethhdr *vhdr;
2987 int rc;
2988
2989 rc = skb_cow_head(skb, 0);
2990 if (rc < 0)
2991 return rc;
2992 vhdr = (struct vlan_ethhdr *)skb->data;
2993 vhdr->h_vlan_TCI = htons(tx_flags >>
2994 I40E_TX_FLAGS_VLAN_SHIFT);
2995 } else {
2996 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2997 }
2998 }
2999
3000out:
3001 *flags = tx_flags;
3002 return 0;
3003}
3004
3005/**
3006 * i40e_tso - set up the tso context descriptor
3007 * @first: pointer to first Tx buffer for xmit
3008 * @hdr_len: ptr to the size of the packet header
3009 * @cd_type_cmd_tso_mss: Quad Word 1
3010 *
3011 * Returns 0 if no TSO can happen, 1 if tso is going, or error
3012 **/
3013static int i40e_tso(struct i40e_tx_buffer *first, u8 *hdr_len,
3014 u64 *cd_type_cmd_tso_mss)
3015{
3016 struct sk_buff *skb = first->skb;
3017 u64 cd_cmd, cd_tso_len, cd_mss;
3018 union {
3019 struct iphdr *v4;
3020 struct ipv6hdr *v6;
3021 unsigned char *hdr;
3022 } ip;
3023 union {
3024 struct tcphdr *tcp;
3025 struct udphdr *udp;
3026 unsigned char *hdr;
3027 } l4;
3028 u32 paylen, l4_offset;
3029 u16 gso_segs, gso_size;
3030 int err;
3031
3032 if (skb->ip_summed != CHECKSUM_PARTIAL)
3033 return 0;
3034
3035 if (!skb_is_gso(skb))
3036 return 0;
3037
3038 err = skb_cow_head(skb, 0);
3039 if (err < 0)
3040 return err;
3041
3042 ip.hdr = skb_network_header(skb);
3043 l4.hdr = skb_transport_header(skb);
3044
3045 /* initialize outer IP header fields */
3046 if (ip.v4->version == 4) {
3047 ip.v4->tot_len = 0;
3048 ip.v4->check = 0;
3049 } else {
3050 ip.v6->payload_len = 0;
3051 }
3052
3053 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
3054 SKB_GSO_GRE_CSUM |
3055 SKB_GSO_IPXIP4 |
3056 SKB_GSO_IPXIP6 |
3057 SKB_GSO_UDP_TUNNEL |
3058 SKB_GSO_UDP_TUNNEL_CSUM)) {
3059 if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
3060 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) {
3061 l4.udp->len = 0;
3062
3063 /* determine offset of outer transport header */
3064 l4_offset = l4.hdr - skb->data;
3065
3066 /* remove payload length from outer checksum */
3067 paylen = skb->len - l4_offset;
3068 csum_replace_by_diff(&l4.udp->check,
3069 (__force __wsum)htonl(paylen));
3070 }
3071
3072 /* reset pointers to inner headers */
3073 ip.hdr = skb_inner_network_header(skb);
3074 l4.hdr = skb_inner_transport_header(skb);
3075
3076 /* initialize inner IP header fields */
3077 if (ip.v4->version == 4) {
3078 ip.v4->tot_len = 0;
3079 ip.v4->check = 0;
3080 } else {
3081 ip.v6->payload_len = 0;
3082 }
3083 }
3084
3085 /* determine offset of inner transport header */
3086 l4_offset = l4.hdr - skb->data;
3087
3088 /* remove payload length from inner checksum */
3089 paylen = skb->len - l4_offset;
3090
3091 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
3092 csum_replace_by_diff(&l4.udp->check, (__force __wsum)htonl(paylen));
3093 /* compute length of segmentation header */
3094 *hdr_len = sizeof(*l4.udp) + l4_offset;
3095 } else {
3096 csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen));
3097 /* compute length of segmentation header */
3098 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
3099 }
3100
3101 /* pull values out of skb_shinfo */
3102 gso_size = skb_shinfo(skb)->gso_size;
3103 gso_segs = skb_shinfo(skb)->gso_segs;
3104
3105 /* update GSO size and bytecount with header size */
3106 first->gso_segs = gso_segs;
3107 first->bytecount += (first->gso_segs - 1) * *hdr_len;
3108
3109 /* find the field values */
3110 cd_cmd = I40E_TX_CTX_DESC_TSO;
3111 cd_tso_len = skb->len - *hdr_len;
3112 cd_mss = gso_size;
3113 *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
3114 (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
3115 (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
3116 return 1;
3117}
3118
3119/**
3120 * i40e_tsyn - set up the tsyn context descriptor
3121 * @tx_ring: ptr to the ring to send
3122 * @skb: ptr to the skb we're sending
3123 * @tx_flags: the collected send information
3124 * @cd_type_cmd_tso_mss: Quad Word 1
3125 *
3126 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen
3127 **/
3128static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb,
3129 u32 tx_flags, u64 *cd_type_cmd_tso_mss)
3130{
3131 struct i40e_pf *pf;
3132
3133 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
3134 return 0;
3135
3136 /* Tx timestamps cannot be sampled when doing TSO */
3137 if (tx_flags & I40E_TX_FLAGS_TSO)
3138 return 0;
3139
3140 /* only timestamp the outbound packet if the user has requested it and
3141 * we are not already transmitting a packet to be timestamped
3142 */
3143 pf = i40e_netdev_to_pf(tx_ring->netdev);
3144 if (!(pf->flags & I40E_FLAG_PTP))
3145 return 0;
3146
3147 if (pf->ptp_tx &&
3148 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, pf->state)) {
3149 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3150 pf->ptp_tx_start = jiffies;
3151 pf->ptp_tx_skb = skb_get(skb);
3152 } else {
3153 pf->tx_hwtstamp_skipped++;
3154 return 0;
3155 }
3156
3157 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN <<
3158 I40E_TXD_CTX_QW1_CMD_SHIFT;
3159
3160 return 1;
3161}
3162
3163/**
3164 * i40e_tx_enable_csum - Enable Tx checksum offloads
3165 * @skb: send buffer
3166 * @tx_flags: pointer to Tx flags currently set
3167 * @td_cmd: Tx descriptor command bits to set
3168 * @td_offset: Tx descriptor header offsets to set
3169 * @tx_ring: Tx descriptor ring
3170 * @cd_tunneling: ptr to context desc bits
3171 **/
3172static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
3173 u32 *td_cmd, u32 *td_offset,
3174 struct i40e_ring *tx_ring,
3175 u32 *cd_tunneling)
3176{
3177 union {
3178 struct iphdr *v4;
3179 struct ipv6hdr *v6;
3180 unsigned char *hdr;
3181 } ip;
3182 union {
3183 struct tcphdr *tcp;
3184 struct udphdr *udp;
3185 unsigned char *hdr;
3186 } l4;
3187 unsigned char *exthdr;
3188 u32 offset, cmd = 0;
3189 __be16 frag_off;
3190 u8 l4_proto = 0;
3191
3192 if (skb->ip_summed != CHECKSUM_PARTIAL)
3193 return 0;
3194
3195 ip.hdr = skb_network_header(skb);
3196 l4.hdr = skb_transport_header(skb);
3197
3198 /* compute outer L2 header size */
3199 offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
3200
3201 if (skb->encapsulation) {
3202 u32 tunnel = 0;
3203 /* define outer network header type */
3204 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
3205 tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
3206 I40E_TX_CTX_EXT_IP_IPV4 :
3207 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
3208
3209 l4_proto = ip.v4->protocol;
3210 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
3211 int ret;
3212
3213 tunnel |= I40E_TX_CTX_EXT_IP_IPV6;
3214
3215 exthdr = ip.hdr + sizeof(*ip.v6);
3216 l4_proto = ip.v6->nexthdr;
3217 ret = ipv6_skip_exthdr(skb, exthdr - skb->data,
3218 &l4_proto, &frag_off);
3219 if (ret < 0)
3220 return -1;
3221 }
3222
3223 /* define outer transport */
3224 switch (l4_proto) {
3225 case IPPROTO_UDP:
3226 tunnel |= I40E_TXD_CTX_UDP_TUNNELING;
3227 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3228 break;
3229 case IPPROTO_GRE:
3230 tunnel |= I40E_TXD_CTX_GRE_TUNNELING;
3231 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3232 break;
3233 case IPPROTO_IPIP:
3234 case IPPROTO_IPV6:
3235 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3236 l4.hdr = skb_inner_network_header(skb);
3237 break;
3238 default:
3239 if (*tx_flags & I40E_TX_FLAGS_TSO)
3240 return -1;
3241
3242 skb_checksum_help(skb);
3243 return 0;
3244 }
3245
3246 /* compute outer L3 header size */
3247 tunnel |= ((l4.hdr - ip.hdr) / 4) <<
3248 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
3249
3250 /* switch IP header pointer from outer to inner header */
3251 ip.hdr = skb_inner_network_header(skb);
3252
3253 /* compute tunnel header size */
3254 tunnel |= ((ip.hdr - l4.hdr) / 2) <<
3255 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
3256
3257 /* indicate if we need to offload outer UDP header */
3258 if ((*tx_flags & I40E_TX_FLAGS_TSO) &&
3259 !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
3260 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM))
3261 tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
3262
3263 /* record tunnel offload values */
3264 *cd_tunneling |= tunnel;
3265
3266 /* switch L4 header pointer from outer to inner */
3267 l4.hdr = skb_inner_transport_header(skb);
3268 l4_proto = 0;
3269
3270 /* reset type as we transition from outer to inner headers */
3271 *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6);
3272 if (ip.v4->version == 4)
3273 *tx_flags |= I40E_TX_FLAGS_IPV4;
3274 if (ip.v6->version == 6)
3275 *tx_flags |= I40E_TX_FLAGS_IPV6;
3276 }
3277
3278 /* Enable IP checksum offloads */
3279 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
3280 l4_proto = ip.v4->protocol;
3281 /* the stack computes the IP header already, the only time we
3282 * need the hardware to recompute it is in the case of TSO.
3283 */
3284 cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
3285 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM :
3286 I40E_TX_DESC_CMD_IIPT_IPV4;
3287 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
3288 cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
3289
3290 exthdr = ip.hdr + sizeof(*ip.v6);
3291 l4_proto = ip.v6->nexthdr;
3292 if (l4.hdr != exthdr)
3293 ipv6_skip_exthdr(skb, exthdr - skb->data,
3294 &l4_proto, &frag_off);
3295 }
3296
3297 /* compute inner L3 header size */
3298 offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
3299
3300 /* Enable L4 checksum offloads */
3301 switch (l4_proto) {
3302 case IPPROTO_TCP:
3303 /* enable checksum offloads */
3304 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
3305 offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3306 break;
3307 case IPPROTO_SCTP:
3308 /* enable SCTP checksum offload */
3309 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
3310 offset |= (sizeof(struct sctphdr) >> 2) <<
3311 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3312 break;
3313 case IPPROTO_UDP:
3314 /* enable UDP checksum offload */
3315 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
3316 offset |= (sizeof(struct udphdr) >> 2) <<
3317 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3318 break;
3319 default:
3320 if (*tx_flags & I40E_TX_FLAGS_TSO)
3321 return -1;
3322 skb_checksum_help(skb);
3323 return 0;
3324 }
3325
3326 *td_cmd |= cmd;
3327 *td_offset |= offset;
3328
3329 return 1;
3330}
3331
3332/**
3333 * i40e_create_tx_ctx - Build the Tx context descriptor
3334 * @tx_ring: ring to create the descriptor on
3335 * @cd_type_cmd_tso_mss: Quad Word 1
3336 * @cd_tunneling: Quad Word 0 - bits 0-31
3337 * @cd_l2tag2: Quad Word 0 - bits 32-63
3338 **/
3339static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
3340 const u64 cd_type_cmd_tso_mss,
3341 const u32 cd_tunneling, const u32 cd_l2tag2)
3342{
3343 struct i40e_tx_context_desc *context_desc;
3344 int i = tx_ring->next_to_use;
3345
3346 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
3347 !cd_tunneling && !cd_l2tag2)
3348 return;
3349
3350 /* grab the next descriptor */
3351 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
3352
3353 i++;
3354 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
3355
3356 /* cpu_to_le32 and assign to struct fields */
3357 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
3358 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
3359 context_desc->rsvd = cpu_to_le16(0);
3360 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
3361}
3362
3363/**
3364 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
3365 * @tx_ring: the ring to be checked
3366 * @size: the size buffer we want to assure is available
3367 *
3368 * Returns -EBUSY if a stop is needed, else 0
3369 **/
3370int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
3371{
3372 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
3373 /* Memory barrier before checking head and tail */
3374 smp_mb();
3375
3376 /* Check again in a case another CPU has just made room available. */
3377 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
3378 return -EBUSY;
3379
3380 /* A reprieve! - use start_queue because it doesn't call schedule */
3381 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
3382 ++tx_ring->tx_stats.restart_queue;
3383 return 0;
3384}
3385
3386/**
3387 * __i40e_chk_linearize - Check if there are more than 8 buffers per packet
3388 * @skb: send buffer
3389 *
3390 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire
3391 * and so we need to figure out the cases where we need to linearize the skb.
3392 *
3393 * For TSO we need to count the TSO header and segment payload separately.
3394 * As such we need to check cases where we have 7 fragments or more as we
3395 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
3396 * the segment payload in the first descriptor, and another 7 for the
3397 * fragments.
3398 **/
3399bool __i40e_chk_linearize(struct sk_buff *skb)
3400{
3401 const skb_frag_t *frag, *stale;
3402 int nr_frags, sum;
3403
3404 /* no need to check if number of frags is less than 7 */
3405 nr_frags = skb_shinfo(skb)->nr_frags;
3406 if (nr_frags < (I40E_MAX_BUFFER_TXD - 1))
3407 return false;
3408
3409 /* We need to walk through the list and validate that each group
3410 * of 6 fragments totals at least gso_size.
3411 */
3412 nr_frags -= I40E_MAX_BUFFER_TXD - 2;
3413 frag = &skb_shinfo(skb)->frags[0];
3414
3415 /* Initialize size to the negative value of gso_size minus 1. We
3416 * use this as the worst case scenerio in which the frag ahead
3417 * of us only provides one byte which is why we are limited to 6
3418 * descriptors for a single transmit as the header and previous
3419 * fragment are already consuming 2 descriptors.
3420 */
3421 sum = 1 - skb_shinfo(skb)->gso_size;
3422
3423 /* Add size of frags 0 through 4 to create our initial sum */
3424 sum += skb_frag_size(frag++);
3425 sum += skb_frag_size(frag++);
3426 sum += skb_frag_size(frag++);
3427 sum += skb_frag_size(frag++);
3428 sum += skb_frag_size(frag++);
3429
3430 /* Walk through fragments adding latest fragment, testing it, and
3431 * then removing stale fragments from the sum.
3432 */
3433 for (stale = &skb_shinfo(skb)->frags[0];; stale++) {
3434 int stale_size = skb_frag_size(stale);
3435
3436 sum += skb_frag_size(frag++);
3437
3438 /* The stale fragment may present us with a smaller
3439 * descriptor than the actual fragment size. To account
3440 * for that we need to remove all the data on the front and
3441 * figure out what the remainder would be in the last
3442 * descriptor associated with the fragment.
3443 */
3444 if (stale_size > I40E_MAX_DATA_PER_TXD) {
3445 int align_pad = -(skb_frag_off(stale)) &
3446 (I40E_MAX_READ_REQ_SIZE - 1);
3447
3448 sum -= align_pad;
3449 stale_size -= align_pad;
3450
3451 do {
3452 sum -= I40E_MAX_DATA_PER_TXD_ALIGNED;
3453 stale_size -= I40E_MAX_DATA_PER_TXD_ALIGNED;
3454 } while (stale_size > I40E_MAX_DATA_PER_TXD);
3455 }
3456
3457 /* if sum is negative we failed to make sufficient progress */
3458 if (sum < 0)
3459 return true;
3460
3461 if (!nr_frags--)
3462 break;
3463
3464 sum -= stale_size;
3465 }
3466
3467 return false;
3468}
3469
3470/**
3471 * i40e_tx_map - Build the Tx descriptor
3472 * @tx_ring: ring to send buffer on
3473 * @skb: send buffer
3474 * @first: first buffer info buffer to use
3475 * @tx_flags: collected send information
3476 * @hdr_len: size of the packet header
3477 * @td_cmd: the command field in the descriptor
3478 * @td_offset: offset for checksum or crc
3479 *
3480 * Returns 0 on success, -1 on failure to DMA
3481 **/
3482static inline int i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
3483 struct i40e_tx_buffer *first, u32 tx_flags,
3484 const u8 hdr_len, u32 td_cmd, u32 td_offset)
3485{
3486 unsigned int data_len = skb->data_len;
3487 unsigned int size = skb_headlen(skb);
3488 skb_frag_t *frag;
3489 struct i40e_tx_buffer *tx_bi;
3490 struct i40e_tx_desc *tx_desc;
3491 u16 i = tx_ring->next_to_use;
3492 u32 td_tag = 0;
3493 dma_addr_t dma;
3494 u16 desc_count = 1;
3495
3496 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
3497 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
3498 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
3499 I40E_TX_FLAGS_VLAN_SHIFT;
3500 }
3501
3502 first->tx_flags = tx_flags;
3503
3504 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
3505
3506 tx_desc = I40E_TX_DESC(tx_ring, i);
3507 tx_bi = first;
3508
3509 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
3510 unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
3511
3512 if (dma_mapping_error(tx_ring->dev, dma))
3513 goto dma_error;
3514
3515 /* record length, and DMA address */
3516 dma_unmap_len_set(tx_bi, len, size);
3517 dma_unmap_addr_set(tx_bi, dma, dma);
3518
3519 /* align size to end of page */
3520 max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1);
3521 tx_desc->buffer_addr = cpu_to_le64(dma);
3522
3523 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
3524 tx_desc->cmd_type_offset_bsz =
3525 build_ctob(td_cmd, td_offset,
3526 max_data, td_tag);
3527
3528 tx_desc++;
3529 i++;
3530 desc_count++;
3531
3532 if (i == tx_ring->count) {
3533 tx_desc = I40E_TX_DESC(tx_ring, 0);
3534 i = 0;
3535 }
3536
3537 dma += max_data;
3538 size -= max_data;
3539
3540 max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
3541 tx_desc->buffer_addr = cpu_to_le64(dma);
3542 }
3543
3544 if (likely(!data_len))
3545 break;
3546
3547 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
3548 size, td_tag);
3549
3550 tx_desc++;
3551 i++;
3552 desc_count++;
3553
3554 if (i == tx_ring->count) {
3555 tx_desc = I40E_TX_DESC(tx_ring, 0);
3556 i = 0;
3557 }
3558
3559 size = skb_frag_size(frag);
3560 data_len -= size;
3561
3562 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
3563 DMA_TO_DEVICE);
3564
3565 tx_bi = &tx_ring->tx_bi[i];
3566 }
3567
3568 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
3569
3570 i++;
3571 if (i == tx_ring->count)
3572 i = 0;
3573
3574 tx_ring->next_to_use = i;
3575
3576 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
3577
3578 /* write last descriptor with EOP bit */
3579 td_cmd |= I40E_TX_DESC_CMD_EOP;
3580
3581 /* We OR these values together to check both against 4 (WB_STRIDE)
3582 * below. This is safe since we don't re-use desc_count afterwards.
3583 */
3584 desc_count |= ++tx_ring->packet_stride;
3585
3586 if (desc_count >= WB_STRIDE) {
3587 /* write last descriptor with RS bit set */
3588 td_cmd |= I40E_TX_DESC_CMD_RS;
3589 tx_ring->packet_stride = 0;
3590 }
3591
3592 tx_desc->cmd_type_offset_bsz =
3593 build_ctob(td_cmd, td_offset, size, td_tag);
3594
3595 skb_tx_timestamp(skb);
3596
3597 /* Force memory writes to complete before letting h/w know there
3598 * are new descriptors to fetch.
3599 *
3600 * We also use this memory barrier to make certain all of the
3601 * status bits have been updated before next_to_watch is written.
3602 */
3603 wmb();
3604
3605 /* set next_to_watch value indicating a packet is present */
3606 first->next_to_watch = tx_desc;
3607
3608 /* notify HW of packet */
3609 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
3610 writel(i, tx_ring->tail);
3611 }
3612
3613 return 0;
3614
3615dma_error:
3616 dev_info(tx_ring->dev, "TX DMA map failed\n");
3617
3618 /* clear dma mappings for failed tx_bi map */
3619 for (;;) {
3620 tx_bi = &tx_ring->tx_bi[i];
3621 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
3622 if (tx_bi == first)
3623 break;
3624 if (i == 0)
3625 i = tx_ring->count;
3626 i--;
3627 }
3628
3629 tx_ring->next_to_use = i;
3630
3631 return -1;
3632}
3633
3634static u16 i40e_swdcb_skb_tx_hash(struct net_device *dev,
3635 const struct sk_buff *skb,
3636 u16 num_tx_queues)
3637{
3638 u32 jhash_initval_salt = 0xd631614b;
3639 u32 hash;
3640
3641 if (skb->sk && skb->sk->sk_hash)
3642 hash = skb->sk->sk_hash;
3643 else
3644 hash = (__force u16)skb->protocol ^ skb->hash;
3645
3646 hash = jhash_1word(hash, jhash_initval_salt);
3647
3648 return (u16)(((u64)hash * num_tx_queues) >> 32);
3649}
3650
3651u16 i40e_lan_select_queue(struct net_device *netdev,
3652 struct sk_buff *skb,
3653 struct net_device __always_unused *sb_dev)
3654{
3655 struct i40e_netdev_priv *np = netdev_priv(netdev);
3656 struct i40e_vsi *vsi = np->vsi;
3657 struct i40e_hw *hw;
3658 u16 qoffset;
3659 u16 qcount;
3660 u8 tclass;
3661 u16 hash;
3662 u8 prio;
3663
3664 /* is DCB enabled at all? */
3665 if (vsi->tc_config.numtc == 1)
3666 return netdev_pick_tx(netdev, skb, sb_dev);
3667
3668 prio = skb->priority;
3669 hw = &vsi->back->hw;
3670 tclass = hw->local_dcbx_config.etscfg.prioritytable[prio];
3671 /* sanity check */
3672 if (unlikely(!(vsi->tc_config.enabled_tc & BIT(tclass))))
3673 tclass = 0;
3674
3675 /* select a queue assigned for the given TC */
3676 qcount = vsi->tc_config.tc_info[tclass].qcount;
3677 hash = i40e_swdcb_skb_tx_hash(netdev, skb, qcount);
3678
3679 qoffset = vsi->tc_config.tc_info[tclass].qoffset;
3680 return qoffset + hash;
3681}
3682
3683/**
3684 * i40e_xmit_xdp_ring - transmits an XDP buffer to an XDP Tx ring
3685 * @xdpf: data to transmit
3686 * @xdp_ring: XDP Tx ring
3687 **/
3688static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf,
3689 struct i40e_ring *xdp_ring)
3690{
3691 u16 i = xdp_ring->next_to_use;
3692 struct i40e_tx_buffer *tx_bi;
3693 struct i40e_tx_desc *tx_desc;
3694 void *data = xdpf->data;
3695 u32 size = xdpf->len;
3696 dma_addr_t dma;
3697
3698 if (!unlikely(I40E_DESC_UNUSED(xdp_ring))) {
3699 xdp_ring->tx_stats.tx_busy++;
3700 return I40E_XDP_CONSUMED;
3701 }
3702 dma = dma_map_single(xdp_ring->dev, data, size, DMA_TO_DEVICE);
3703 if (dma_mapping_error(xdp_ring->dev, dma))
3704 return I40E_XDP_CONSUMED;
3705
3706 tx_bi = &xdp_ring->tx_bi[i];
3707 tx_bi->bytecount = size;
3708 tx_bi->gso_segs = 1;
3709 tx_bi->xdpf = xdpf;
3710
3711 /* record length, and DMA address */
3712 dma_unmap_len_set(tx_bi, len, size);
3713 dma_unmap_addr_set(tx_bi, dma, dma);
3714
3715 tx_desc = I40E_TX_DESC(xdp_ring, i);
3716 tx_desc->buffer_addr = cpu_to_le64(dma);
3717 tx_desc->cmd_type_offset_bsz = build_ctob(I40E_TX_DESC_CMD_ICRC
3718 | I40E_TXD_CMD,
3719 0, size, 0);
3720
3721 /* Make certain all of the status bits have been updated
3722 * before next_to_watch is written.
3723 */
3724 smp_wmb();
3725
3726 xdp_ring->xdp_tx_active++;
3727 i++;
3728 if (i == xdp_ring->count)
3729 i = 0;
3730
3731 tx_bi->next_to_watch = tx_desc;
3732 xdp_ring->next_to_use = i;
3733
3734 return I40E_XDP_TX;
3735}
3736
3737/**
3738 * i40e_xmit_frame_ring - Sends buffer on Tx ring
3739 * @skb: send buffer
3740 * @tx_ring: ring to send buffer on
3741 *
3742 * Returns NETDEV_TX_OK if sent, else an error code
3743 **/
3744static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
3745 struct i40e_ring *tx_ring)
3746{
3747 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
3748 u32 cd_tunneling = 0, cd_l2tag2 = 0;
3749 struct i40e_tx_buffer *first;
3750 u32 td_offset = 0;
3751 u32 tx_flags = 0;
3752 __be16 protocol;
3753 u32 td_cmd = 0;
3754 u8 hdr_len = 0;
3755 int tso, count;
3756 int tsyn;
3757
3758 /* prefetch the data, we'll need it later */
3759 prefetch(skb->data);
3760
3761 i40e_trace(xmit_frame_ring, skb, tx_ring);
3762
3763 count = i40e_xmit_descriptor_count(skb);
3764 if (i40e_chk_linearize(skb, count)) {
3765 if (__skb_linearize(skb)) {
3766 dev_kfree_skb_any(skb);
3767 return NETDEV_TX_OK;
3768 }
3769 count = i40e_txd_use_count(skb->len);
3770 tx_ring->tx_stats.tx_linearize++;
3771 }
3772
3773 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
3774 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
3775 * + 4 desc gap to avoid the cache line where head is,
3776 * + 1 desc for context descriptor,
3777 * otherwise try next time
3778 */
3779 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
3780 tx_ring->tx_stats.tx_busy++;
3781 return NETDEV_TX_BUSY;
3782 }
3783
3784 /* record the location of the first descriptor for this packet */
3785 first = &tx_ring->tx_bi[tx_ring->next_to_use];
3786 first->skb = skb;
3787 first->bytecount = skb->len;
3788 first->gso_segs = 1;
3789
3790 /* prepare the xmit flags */
3791 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
3792 goto out_drop;
3793
3794 /* obtain protocol of skb */
3795 protocol = vlan_get_protocol(skb);
3796
3797 /* setup IPv4/IPv6 offloads */
3798 if (protocol == htons(ETH_P_IP))
3799 tx_flags |= I40E_TX_FLAGS_IPV4;
3800 else if (protocol == htons(ETH_P_IPV6))
3801 tx_flags |= I40E_TX_FLAGS_IPV6;
3802
3803 tso = i40e_tso(first, &hdr_len, &cd_type_cmd_tso_mss);
3804
3805 if (tso < 0)
3806 goto out_drop;
3807 else if (tso)
3808 tx_flags |= I40E_TX_FLAGS_TSO;
3809
3810 /* Always offload the checksum, since it's in the data descriptor */
3811 tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
3812 tx_ring, &cd_tunneling);
3813 if (tso < 0)
3814 goto out_drop;
3815
3816 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss);
3817
3818 if (tsyn)
3819 tx_flags |= I40E_TX_FLAGS_TSYN;
3820
3821 /* always enable CRC insertion offload */
3822 td_cmd |= I40E_TX_DESC_CMD_ICRC;
3823
3824 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
3825 cd_tunneling, cd_l2tag2);
3826
3827 /* Add Flow Director ATR if it's enabled.
3828 *
3829 * NOTE: this must always be directly before the data descriptor.
3830 */
3831 i40e_atr(tx_ring, skb, tx_flags);
3832
3833 if (i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
3834 td_cmd, td_offset))
3835 goto cleanup_tx_tstamp;
3836
3837 return NETDEV_TX_OK;
3838
3839out_drop:
3840 i40e_trace(xmit_frame_ring_drop, first->skb, tx_ring);
3841 dev_kfree_skb_any(first->skb);
3842 first->skb = NULL;
3843cleanup_tx_tstamp:
3844 if (unlikely(tx_flags & I40E_TX_FLAGS_TSYN)) {
3845 struct i40e_pf *pf = i40e_netdev_to_pf(tx_ring->netdev);
3846
3847 dev_kfree_skb_any(pf->ptp_tx_skb);
3848 pf->ptp_tx_skb = NULL;
3849 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
3850 }
3851
3852 return NETDEV_TX_OK;
3853}
3854
3855/**
3856 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer
3857 * @skb: send buffer
3858 * @netdev: network interface device structure
3859 *
3860 * Returns NETDEV_TX_OK if sent, else an error code
3861 **/
3862netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3863{
3864 struct i40e_netdev_priv *np = netdev_priv(netdev);
3865 struct i40e_vsi *vsi = np->vsi;
3866 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping];
3867
3868 /* hardware can't handle really short frames, hardware padding works
3869 * beyond this point
3870 */
3871 if (skb_put_padto(skb, I40E_MIN_TX_LEN))
3872 return NETDEV_TX_OK;
3873
3874 return i40e_xmit_frame_ring(skb, tx_ring);
3875}
3876
3877/**
3878 * i40e_xdp_xmit - Implements ndo_xdp_xmit
3879 * @dev: netdev
3880 * @n: number of frames
3881 * @frames: array of XDP buffer pointers
3882 * @flags: XDP extra info
3883 *
3884 * Returns number of frames successfully sent. Failed frames
3885 * will be free'ed by XDP core.
3886 *
3887 * For error cases, a negative errno code is returned and no-frames
3888 * are transmitted (caller must handle freeing frames).
3889 **/
3890int i40e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
3891 u32 flags)
3892{
3893 struct i40e_netdev_priv *np = netdev_priv(dev);
3894 unsigned int queue_index = smp_processor_id();
3895 struct i40e_vsi *vsi = np->vsi;
3896 struct i40e_pf *pf = vsi->back;
3897 struct i40e_ring *xdp_ring;
3898 int nxmit = 0;
3899 int i;
3900
3901 if (test_bit(__I40E_VSI_DOWN, vsi->state))
3902 return -ENETDOWN;
3903
3904 if (!i40e_enabled_xdp_vsi(vsi) || queue_index >= vsi->num_queue_pairs ||
3905 test_bit(__I40E_CONFIG_BUSY, pf->state))
3906 return -ENXIO;
3907
3908 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
3909 return -EINVAL;
3910
3911 xdp_ring = vsi->xdp_rings[queue_index];
3912
3913 for (i = 0; i < n; i++) {
3914 struct xdp_frame *xdpf = frames[i];
3915 int err;
3916
3917 err = i40e_xmit_xdp_ring(xdpf, xdp_ring);
3918 if (err != I40E_XDP_TX)
3919 break;
3920 nxmit++;
3921 }
3922
3923 if (unlikely(flags & XDP_XMIT_FLUSH))
3924 i40e_xdp_ring_update_tail(xdp_ring);
3925
3926 return nxmit;
3927}