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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 *
9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 */
12
13#include <linux/bitfield.h>
14#include <linux/delay.h>
15#include <linux/dsa/mv88e6xxx.h>
16#include <linux/etherdevice.h>
17#include <linux/ethtool.h>
18#include <linux/if_bridge.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/irqdomain.h>
22#include <linux/jiffies.h>
23#include <linux/list.h>
24#include <linux/mdio.h>
25#include <linux/module.h>
26#include <linux/of.h>
27#include <linux/of_irq.h>
28#include <linux/of_mdio.h>
29#include <linux/platform_data/mv88e6xxx.h>
30#include <linux/property.h>
31#include <linux/netdevice.h>
32#include <linux/gpio/consumer.h>
33#include <linux/phylink.h>
34#include <net/dsa.h>
35
36#include "chip.h"
37#include "devlink.h"
38#include "global1.h"
39#include "global2.h"
40#include "hwtstamp.h"
41#include "phy.h"
42#include "port.h"
43#include "ptp.h"
44#include "serdes.h"
45#include "smi.h"
46
47static void assert_reg_lock(struct mv88e6xxx_chip *chip)
48{
49 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
50 dev_err(chip->dev, "Switch registers lock not held!\n");
51 dump_stack();
52 }
53}
54
55int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
56{
57 int err;
58
59 assert_reg_lock(chip);
60
61 err = mv88e6xxx_smi_read(chip, addr, reg, val);
62 if (err)
63 return err;
64
65 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
66 addr, reg, *val);
67
68 return 0;
69}
70
71int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
72{
73 int err;
74
75 assert_reg_lock(chip);
76
77 err = mv88e6xxx_smi_write(chip, addr, reg, val);
78 if (err)
79 return err;
80
81 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
82 addr, reg, val);
83
84 return 0;
85}
86
87int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
88 u16 mask, u16 val)
89{
90 const unsigned long timeout = jiffies + msecs_to_jiffies(50);
91 u16 data;
92 int err;
93 int i;
94
95 /* There's no bus specific operation to wait for a mask. Even
96 * if the initial poll takes longer than 50ms, always do at
97 * least one more attempt.
98 */
99 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) {
100 err = mv88e6xxx_read(chip, addr, reg, &data);
101 if (err)
102 return err;
103
104 if ((data & mask) == val)
105 return 0;
106
107 if (i < 2)
108 cpu_relax();
109 else
110 usleep_range(1000, 2000);
111 }
112
113 err = mv88e6xxx_read(chip, addr, reg, &data);
114 if (err)
115 return err;
116
117 if ((data & mask) == val)
118 return 0;
119
120 dev_err(chip->dev, "Timeout while waiting for switch\n");
121 return -ETIMEDOUT;
122}
123
124int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
125 int bit, int val)
126{
127 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
128 val ? BIT(bit) : 0x0000);
129}
130
131struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
132{
133 struct mv88e6xxx_mdio_bus *mdio_bus;
134
135 mdio_bus = list_first_entry_or_null(&chip->mdios,
136 struct mv88e6xxx_mdio_bus, list);
137 if (!mdio_bus)
138 return NULL;
139
140 return mdio_bus->bus;
141}
142
143static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
144{
145 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
146 unsigned int n = d->hwirq;
147
148 chip->g1_irq.masked |= (1 << n);
149}
150
151static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
152{
153 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
154 unsigned int n = d->hwirq;
155
156 chip->g1_irq.masked &= ~(1 << n);
157}
158
159static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
160{
161 unsigned int nhandled = 0;
162 unsigned int sub_irq;
163 unsigned int n;
164 u16 reg;
165 u16 ctl1;
166 int err;
167
168 mv88e6xxx_reg_lock(chip);
169 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
170 mv88e6xxx_reg_unlock(chip);
171
172 if (err)
173 goto out;
174
175 do {
176 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
177 if (reg & (1 << n)) {
178 sub_irq = irq_find_mapping(chip->g1_irq.domain,
179 n);
180 handle_nested_irq(sub_irq);
181 ++nhandled;
182 }
183 }
184
185 mv88e6xxx_reg_lock(chip);
186 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
187 if (err)
188 goto unlock;
189 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
190unlock:
191 mv88e6xxx_reg_unlock(chip);
192 if (err)
193 goto out;
194 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
195 } while (reg & ctl1);
196
197out:
198 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
199}
200
201static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
202{
203 struct mv88e6xxx_chip *chip = dev_id;
204
205 return mv88e6xxx_g1_irq_thread_work(chip);
206}
207
208static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
209{
210 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
211
212 mv88e6xxx_reg_lock(chip);
213}
214
215static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
216{
217 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
218 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
219 u16 reg;
220 int err;
221
222 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
223 if (err)
224 goto out;
225
226 reg &= ~mask;
227 reg |= (~chip->g1_irq.masked & mask);
228
229 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
230 if (err)
231 goto out;
232
233out:
234 mv88e6xxx_reg_unlock(chip);
235}
236
237static const struct irq_chip mv88e6xxx_g1_irq_chip = {
238 .name = "mv88e6xxx-g1",
239 .irq_mask = mv88e6xxx_g1_irq_mask,
240 .irq_unmask = mv88e6xxx_g1_irq_unmask,
241 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
242 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
243};
244
245static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
246 unsigned int irq,
247 irq_hw_number_t hwirq)
248{
249 struct mv88e6xxx_chip *chip = d->host_data;
250
251 irq_set_chip_data(irq, d->host_data);
252 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
253 irq_set_noprobe(irq);
254
255 return 0;
256}
257
258static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
259 .map = mv88e6xxx_g1_irq_domain_map,
260 .xlate = irq_domain_xlate_twocell,
261};
262
263/* To be called with reg_lock held */
264static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
265{
266 int irq, virq;
267 u16 mask;
268
269 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
270 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
271 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
272
273 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
274 virq = irq_find_mapping(chip->g1_irq.domain, irq);
275 irq_dispose_mapping(virq);
276 }
277
278 irq_domain_remove(chip->g1_irq.domain);
279}
280
281static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
282{
283 /*
284 * free_irq must be called without reg_lock taken because the irq
285 * handler takes this lock, too.
286 */
287 free_irq(chip->irq, chip);
288
289 mv88e6xxx_reg_lock(chip);
290 mv88e6xxx_g1_irq_free_common(chip);
291 mv88e6xxx_reg_unlock(chip);
292}
293
294static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
295{
296 int err, irq, virq;
297 u16 reg, mask;
298
299 chip->g1_irq.nirqs = chip->info->g1_irqs;
300 chip->g1_irq.domain = irq_domain_add_simple(
301 NULL, chip->g1_irq.nirqs, 0,
302 &mv88e6xxx_g1_irq_domain_ops, chip);
303 if (!chip->g1_irq.domain)
304 return -ENOMEM;
305
306 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
307 irq_create_mapping(chip->g1_irq.domain, irq);
308
309 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
310 chip->g1_irq.masked = ~0;
311
312 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
313 if (err)
314 goto out_mapping;
315
316 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
317
318 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
319 if (err)
320 goto out_disable;
321
322 /* Reading the interrupt status clears (most of) them */
323 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
324 if (err)
325 goto out_disable;
326
327 return 0;
328
329out_disable:
330 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
331 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
332
333out_mapping:
334 for (irq = 0; irq < 16; irq++) {
335 virq = irq_find_mapping(chip->g1_irq.domain, irq);
336 irq_dispose_mapping(virq);
337 }
338
339 irq_domain_remove(chip->g1_irq.domain);
340
341 return err;
342}
343
344static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
345{
346 static struct lock_class_key lock_key;
347 static struct lock_class_key request_key;
348 int err;
349
350 err = mv88e6xxx_g1_irq_setup_common(chip);
351 if (err)
352 return err;
353
354 /* These lock classes tells lockdep that global 1 irqs are in
355 * a different category than their parent GPIO, so it won't
356 * report false recursion.
357 */
358 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
359
360 snprintf(chip->irq_name, sizeof(chip->irq_name),
361 "mv88e6xxx-%s", dev_name(chip->dev));
362
363 mv88e6xxx_reg_unlock(chip);
364 err = request_threaded_irq(chip->irq, NULL,
365 mv88e6xxx_g1_irq_thread_fn,
366 IRQF_ONESHOT | IRQF_SHARED,
367 chip->irq_name, chip);
368 mv88e6xxx_reg_lock(chip);
369 if (err)
370 mv88e6xxx_g1_irq_free_common(chip);
371
372 return err;
373}
374
375static void mv88e6xxx_irq_poll(struct kthread_work *work)
376{
377 struct mv88e6xxx_chip *chip = container_of(work,
378 struct mv88e6xxx_chip,
379 irq_poll_work.work);
380 mv88e6xxx_g1_irq_thread_work(chip);
381
382 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
383 msecs_to_jiffies(100));
384}
385
386static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
387{
388 int err;
389
390 err = mv88e6xxx_g1_irq_setup_common(chip);
391 if (err)
392 return err;
393
394 kthread_init_delayed_work(&chip->irq_poll_work,
395 mv88e6xxx_irq_poll);
396
397 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
398 if (IS_ERR(chip->kworker))
399 return PTR_ERR(chip->kworker);
400
401 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
402 msecs_to_jiffies(100));
403
404 return 0;
405}
406
407static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
408{
409 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
410 kthread_destroy_worker(chip->kworker);
411
412 mv88e6xxx_reg_lock(chip);
413 mv88e6xxx_g1_irq_free_common(chip);
414 mv88e6xxx_reg_unlock(chip);
415}
416
417static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
418 int port, phy_interface_t interface)
419{
420 int err;
421
422 if (chip->info->ops->port_set_rgmii_delay) {
423 err = chip->info->ops->port_set_rgmii_delay(chip, port,
424 interface);
425 if (err && err != -EOPNOTSUPP)
426 return err;
427 }
428
429 if (chip->info->ops->port_set_cmode) {
430 err = chip->info->ops->port_set_cmode(chip, port,
431 interface);
432 if (err && err != -EOPNOTSUPP)
433 return err;
434 }
435
436 return 0;
437}
438
439static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
440 int link, int speed, int duplex, int pause,
441 phy_interface_t mode)
442{
443 int err;
444
445 if (!chip->info->ops->port_set_link)
446 return 0;
447
448 /* Port's MAC control must not be changed unless the link is down */
449 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
450 if (err)
451 return err;
452
453 if (chip->info->ops->port_set_speed_duplex) {
454 err = chip->info->ops->port_set_speed_duplex(chip, port,
455 speed, duplex);
456 if (err && err != -EOPNOTSUPP)
457 goto restore_link;
458 }
459
460 if (chip->info->ops->port_set_pause) {
461 err = chip->info->ops->port_set_pause(chip, port, pause);
462 if (err)
463 goto restore_link;
464 }
465
466 err = mv88e6xxx_port_config_interface(chip, port, mode);
467restore_link:
468 if (chip->info->ops->port_set_link(chip, port, link))
469 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
470
471 return err;
472}
473
474static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
475{
476 return port >= chip->info->internal_phys_offset &&
477 port < chip->info->num_internal_phys +
478 chip->info->internal_phys_offset;
479}
480
481static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
482{
483 u16 reg;
484 int err;
485
486 /* The 88e6250 family does not have the PHY detect bit. Instead,
487 * report whether the port is internal.
488 */
489 if (chip->info->family == MV88E6XXX_FAMILY_6250)
490 return mv88e6xxx_phy_is_internal(chip, port);
491
492 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
493 if (err) {
494 dev_err(chip->dev,
495 "p%d: %s: failed to read port status\n",
496 port, __func__);
497 return err;
498 }
499
500 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
501}
502
503static const u8 mv88e6185_phy_interface_modes[] = {
504 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII,
505 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII,
506 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII,
507 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII,
508 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX,
509 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX,
510 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII,
511};
512
513static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
514 struct phylink_config *config)
515{
516 u8 cmode = chip->ports[port].cmode;
517
518 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
519
520 if (mv88e6xxx_phy_is_internal(chip, port)) {
521 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
522 } else {
523 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
524 mv88e6185_phy_interface_modes[cmode])
525 __set_bit(mv88e6185_phy_interface_modes[cmode],
526 config->supported_interfaces);
527
528 config->mac_capabilities |= MAC_1000FD;
529 }
530}
531
532static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
533 struct phylink_config *config)
534{
535 u8 cmode = chip->ports[port].cmode;
536
537 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
538 mv88e6185_phy_interface_modes[cmode])
539 __set_bit(mv88e6185_phy_interface_modes[cmode],
540 config->supported_interfaces);
541
542 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
543 MAC_1000FD;
544}
545
546static const u8 mv88e6xxx_phy_interface_modes[] = {
547 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII,
548 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII,
549 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII,
550 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII,
551 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII,
552 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX,
553 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX,
554 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII,
555 /* higher interface modes are not needed here, since ports supporting
556 * them are writable, and so the supported interfaces are filled in the
557 * corresponding .phylink_set_interfaces() implementation below
558 */
559};
560
561static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported)
562{
563 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) &&
564 mv88e6xxx_phy_interface_modes[cmode])
565 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported);
566 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII)
567 phy_interface_set_rgmii(supported);
568}
569
570static void
571mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port,
572 struct phylink_config *config)
573{
574 unsigned long *supported = config->supported_interfaces;
575 int err;
576 u16 reg;
577
578 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
579 if (err) {
580 dev_err(chip->dev, "p%d: failed to read port status\n", port);
581 return;
582 }
583
584 switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) {
585 case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY:
586 case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY:
587 case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY:
588 case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY:
589 __set_bit(PHY_INTERFACE_MODE_REVMII, supported);
590 break;
591
592 case MV88E6250_PORT_STS_PORTMODE_MII_HALF:
593 case MV88E6250_PORT_STS_PORTMODE_MII_FULL:
594 __set_bit(PHY_INTERFACE_MODE_MII, supported);
595 break;
596
597 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY:
598 case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY:
599 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY:
600 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY:
601 __set_bit(PHY_INTERFACE_MODE_REVRMII, supported);
602 break;
603
604 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL:
605 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL:
606 __set_bit(PHY_INTERFACE_MODE_RMII, supported);
607 break;
608
609 case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII:
610 __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
611 break;
612
613 default:
614 dev_err(chip->dev,
615 "p%d: invalid port mode in status register: %04x\n",
616 port, reg);
617 }
618}
619
620static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
621 struct phylink_config *config)
622{
623 if (!mv88e6xxx_phy_is_internal(chip, port))
624 mv88e6250_setup_supported_interfaces(chip, port, config);
625
626 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
627}
628
629static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
630 struct phylink_config *config)
631{
632 unsigned long *supported = config->supported_interfaces;
633
634 /* Translate the default cmode */
635 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
636
637 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
638 MAC_1000FD;
639}
640
641static int mv88e63xx_get_port_serdes_cmode(struct mv88e6xxx_chip *chip, int port)
642{
643 u16 reg, val;
644 int err;
645
646 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
647 if (err)
648 return err;
649
650 /* If PHY_DETECT is zero, then we are not in auto-media mode */
651 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT))
652 return 0xf;
653
654 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT;
655 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, val);
656 if (err)
657 return err;
658
659 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &val);
660 if (err)
661 return err;
662
663 /* Restore PHY_DETECT value */
664 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
665 if (err)
666 return err;
667
668 return val & MV88E6XXX_PORT_STS_CMODE_MASK;
669}
670
671static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
672 struct phylink_config *config)
673{
674 unsigned long *supported = config->supported_interfaces;
675 int err, cmode;
676
677 /* Translate the default cmode */
678 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
679
680 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
681 MAC_1000FD;
682
683 /* Port 4 supports automedia if the serdes is associated with it. */
684 if (port == 4) {
685 err = mv88e6352_g2_scratch_port_has_serdes(chip, port);
686 if (err < 0)
687 dev_err(chip->dev, "p%d: failed to read scratch\n",
688 port);
689 if (err <= 0)
690 return;
691
692 cmode = mv88e63xx_get_port_serdes_cmode(chip, port);
693 if (cmode < 0)
694 dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
695 port);
696 else
697 mv88e6xxx_translate_cmode(cmode, supported);
698 }
699}
700
701static void mv88e632x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
702 struct phylink_config *config)
703{
704 unsigned long *supported = config->supported_interfaces;
705 int cmode;
706
707 /* Translate the default cmode */
708 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
709
710 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
711 MAC_1000FD;
712
713 /* Port 0/1 are serdes only ports */
714 if (port == 0 || port == 1) {
715 cmode = mv88e63xx_get_port_serdes_cmode(chip, port);
716 if (cmode < 0)
717 dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
718 port);
719 else
720 mv88e6xxx_translate_cmode(cmode, supported);
721 }
722}
723
724static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
725 struct phylink_config *config)
726{
727 unsigned long *supported = config->supported_interfaces;
728
729 /* Translate the default cmode */
730 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
731
732 /* No ethtool bits for 200Mbps */
733 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
734 MAC_1000FD;
735
736 /* The C_Mode field is programmable on port 5 */
737 if (port == 5) {
738 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
739 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
740 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
741
742 config->mac_capabilities |= MAC_2500FD;
743 }
744}
745
746static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
747 struct phylink_config *config)
748{
749 unsigned long *supported = config->supported_interfaces;
750
751 /* Translate the default cmode */
752 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
753
754 /* No ethtool bits for 200Mbps */
755 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
756 MAC_1000FD;
757
758 /* The C_Mode field is programmable on ports 9 and 10 */
759 if (port == 9 || port == 10) {
760 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
761 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
762 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
763
764 config->mac_capabilities |= MAC_2500FD;
765 }
766}
767
768static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
769 struct phylink_config *config)
770{
771 unsigned long *supported = config->supported_interfaces;
772
773 mv88e6390_phylink_get_caps(chip, port, config);
774
775 /* For the 6x90X, ports 2-7 can be in automedia mode.
776 * (Note that 6x90 doesn't support RXAUI nor XAUI).
777 *
778 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is
779 * configured for 1000BASE-X, SGMII or 2500BASE-X.
780 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is
781 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
782 *
783 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is
784 * configured for 1000BASE-X, SGMII or 2500BASE-X.
785 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is
786 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
787 *
788 * For now, be permissive (as the old code was) and allow 1000BASE-X
789 * on ports 2..7.
790 */
791 if (port >= 2 && port <= 7)
792 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
793
794 /* The C_Mode field can also be programmed for 10G speeds */
795 if (port == 9 || port == 10) {
796 __set_bit(PHY_INTERFACE_MODE_XAUI, supported);
797 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported);
798
799 config->mac_capabilities |= MAC_10000FD;
800 }
801}
802
803static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
804 struct phylink_config *config)
805{
806 unsigned long *supported = config->supported_interfaces;
807 bool is_6191x =
808 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
809 bool is_6361 =
810 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361;
811
812 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
813
814 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
815 MAC_1000FD;
816
817 /* The C_Mode field can be programmed for ports 0, 9 and 10 */
818 if (port == 0 || port == 9 || port == 10) {
819 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
820 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
821
822 /* 6191X supports >1G modes only on port 10 */
823 if (!is_6191x || port == 10) {
824 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
825 config->mac_capabilities |= MAC_2500FD;
826
827 /* 6361 only supports up to 2500BaseX */
828 if (!is_6361) {
829 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
830 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
831 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported);
832 config->mac_capabilities |= MAC_5000FD |
833 MAC_10000FD;
834 }
835 }
836 }
837
838 if (port == 0) {
839 __set_bit(PHY_INTERFACE_MODE_RMII, supported);
840 __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
841 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported);
842 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported);
843 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported);
844 }
845}
846
847static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port,
848 struct phylink_config *config)
849{
850 struct mv88e6xxx_chip *chip = ds->priv;
851
852 mv88e6xxx_reg_lock(chip);
853 chip->info->ops->phylink_get_caps(chip, port, config);
854 mv88e6xxx_reg_unlock(chip);
855
856 if (mv88e6xxx_phy_is_internal(chip, port)) {
857 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
858 config->supported_interfaces);
859 /* Internal ports with no phy-mode need GMII for PHYLIB */
860 __set_bit(PHY_INTERFACE_MODE_GMII,
861 config->supported_interfaces);
862 }
863}
864
865static struct phylink_pcs *
866mv88e6xxx_mac_select_pcs(struct phylink_config *config,
867 phy_interface_t interface)
868{
869 struct dsa_port *dp = dsa_phylink_to_port(config);
870 struct mv88e6xxx_chip *chip = dp->ds->priv;
871 struct phylink_pcs *pcs = NULL;
872
873 if (chip->info->ops->pcs_ops)
874 pcs = chip->info->ops->pcs_ops->pcs_select(chip, dp->index,
875 interface);
876
877 return pcs;
878}
879
880static int mv88e6xxx_mac_prepare(struct phylink_config *config,
881 unsigned int mode, phy_interface_t interface)
882{
883 struct dsa_port *dp = dsa_phylink_to_port(config);
884 struct mv88e6xxx_chip *chip = dp->ds->priv;
885 int port = dp->index;
886 int err = 0;
887
888 /* In inband mode, the link may come up at any time while the link
889 * is not forced down. Force the link down while we reconfigure the
890 * interface mode.
891 */
892 if (mode == MLO_AN_INBAND &&
893 chip->ports[port].interface != interface &&
894 chip->info->ops->port_set_link) {
895 mv88e6xxx_reg_lock(chip);
896 err = chip->info->ops->port_set_link(chip, port,
897 LINK_FORCED_DOWN);
898 mv88e6xxx_reg_unlock(chip);
899 }
900
901 return err;
902}
903
904static void mv88e6xxx_mac_config(struct phylink_config *config,
905 unsigned int mode,
906 const struct phylink_link_state *state)
907{
908 struct dsa_port *dp = dsa_phylink_to_port(config);
909 struct mv88e6xxx_chip *chip = dp->ds->priv;
910 int port = dp->index;
911 int err = 0;
912
913 mv88e6xxx_reg_lock(chip);
914
915 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) {
916 err = mv88e6xxx_port_config_interface(chip, port,
917 state->interface);
918 if (err && err != -EOPNOTSUPP)
919 goto err_unlock;
920 }
921
922err_unlock:
923 mv88e6xxx_reg_unlock(chip);
924
925 if (err && err != -EOPNOTSUPP)
926 dev_err(chip->dev, "p%d: failed to configure MAC/PCS\n", port);
927}
928
929static int mv88e6xxx_mac_finish(struct phylink_config *config,
930 unsigned int mode, phy_interface_t interface)
931{
932 struct dsa_port *dp = dsa_phylink_to_port(config);
933 struct mv88e6xxx_chip *chip = dp->ds->priv;
934 int port = dp->index;
935 int err = 0;
936
937 /* Undo the forced down state above after completing configuration
938 * irrespective of its state on entry, which allows the link to come
939 * up in the in-band case where there is no separate SERDES. Also
940 * ensure that the link can come up if the PPU is in use and we are
941 * in PHY mode (we treat the PPU as an effective in-band mechanism.)
942 */
943 mv88e6xxx_reg_lock(chip);
944
945 if (chip->info->ops->port_set_link &&
946 ((mode == MLO_AN_INBAND &&
947 chip->ports[port].interface != interface) ||
948 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
949 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
950
951 mv88e6xxx_reg_unlock(chip);
952
953 chip->ports[port].interface = interface;
954
955 return err;
956}
957
958static void mv88e6xxx_mac_link_down(struct phylink_config *config,
959 unsigned int mode,
960 phy_interface_t interface)
961{
962 struct dsa_port *dp = dsa_phylink_to_port(config);
963 struct mv88e6xxx_chip *chip = dp->ds->priv;
964 const struct mv88e6xxx_ops *ops;
965 int port = dp->index;
966 int err = 0;
967
968 ops = chip->info->ops;
969
970 mv88e6xxx_reg_lock(chip);
971 /* Force the link down if we know the port may not be automatically
972 * updated by the switch or if we are using fixed-link mode.
973 */
974 if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
975 mode == MLO_AN_FIXED) && ops->port_sync_link)
976 err = ops->port_sync_link(chip, port, mode, false);
977
978 if (!err && ops->port_set_speed_duplex)
979 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED,
980 DUPLEX_UNFORCED);
981 mv88e6xxx_reg_unlock(chip);
982
983 if (err)
984 dev_err(chip->dev,
985 "p%d: failed to force MAC link down\n", port);
986}
987
988static void mv88e6xxx_mac_link_up(struct phylink_config *config,
989 struct phy_device *phydev,
990 unsigned int mode, phy_interface_t interface,
991 int speed, int duplex,
992 bool tx_pause, bool rx_pause)
993{
994 struct dsa_port *dp = dsa_phylink_to_port(config);
995 struct mv88e6xxx_chip *chip = dp->ds->priv;
996 const struct mv88e6xxx_ops *ops;
997 int port = dp->index;
998 int err = 0;
999
1000 ops = chip->info->ops;
1001
1002 mv88e6xxx_reg_lock(chip);
1003 /* Configure and force the link up if we know that the port may not
1004 * automatically updated by the switch or if we are using fixed-link
1005 * mode.
1006 */
1007 if (!mv88e6xxx_port_ppu_updates(chip, port) ||
1008 mode == MLO_AN_FIXED) {
1009 if (ops->port_set_speed_duplex) {
1010 err = ops->port_set_speed_duplex(chip, port,
1011 speed, duplex);
1012 if (err && err != -EOPNOTSUPP)
1013 goto error;
1014 }
1015
1016 if (ops->port_sync_link)
1017 err = ops->port_sync_link(chip, port, mode, true);
1018 }
1019error:
1020 mv88e6xxx_reg_unlock(chip);
1021
1022 if (err && err != -EOPNOTSUPP)
1023 dev_err(chip->dev,
1024 "p%d: failed to configure MAC link up\n", port);
1025}
1026
1027static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
1028{
1029 int err;
1030
1031 if (!chip->info->ops->stats_snapshot)
1032 return -EOPNOTSUPP;
1033
1034 mv88e6xxx_reg_lock(chip);
1035 err = chip->info->ops->stats_snapshot(chip, port);
1036 mv88e6xxx_reg_unlock(chip);
1037
1038 return err;
1039}
1040
1041#define MV88E6XXX_HW_STAT_MAPPER(_fn) \
1042 _fn(in_good_octets, 8, 0x00, STATS_TYPE_BANK0), \
1043 _fn(in_bad_octets, 4, 0x02, STATS_TYPE_BANK0), \
1044 _fn(in_unicast, 4, 0x04, STATS_TYPE_BANK0), \
1045 _fn(in_broadcasts, 4, 0x06, STATS_TYPE_BANK0), \
1046 _fn(in_multicasts, 4, 0x07, STATS_TYPE_BANK0), \
1047 _fn(in_pause, 4, 0x16, STATS_TYPE_BANK0), \
1048 _fn(in_undersize, 4, 0x18, STATS_TYPE_BANK0), \
1049 _fn(in_fragments, 4, 0x19, STATS_TYPE_BANK0), \
1050 _fn(in_oversize, 4, 0x1a, STATS_TYPE_BANK0), \
1051 _fn(in_jabber, 4, 0x1b, STATS_TYPE_BANK0), \
1052 _fn(in_rx_error, 4, 0x1c, STATS_TYPE_BANK0), \
1053 _fn(in_fcs_error, 4, 0x1d, STATS_TYPE_BANK0), \
1054 _fn(out_octets, 8, 0x0e, STATS_TYPE_BANK0), \
1055 _fn(out_unicast, 4, 0x10, STATS_TYPE_BANK0), \
1056 _fn(out_broadcasts, 4, 0x13, STATS_TYPE_BANK0), \
1057 _fn(out_multicasts, 4, 0x12, STATS_TYPE_BANK0), \
1058 _fn(out_pause, 4, 0x15, STATS_TYPE_BANK0), \
1059 _fn(excessive, 4, 0x11, STATS_TYPE_BANK0), \
1060 _fn(collisions, 4, 0x1e, STATS_TYPE_BANK0), \
1061 _fn(deferred, 4, 0x05, STATS_TYPE_BANK0), \
1062 _fn(single, 4, 0x14, STATS_TYPE_BANK0), \
1063 _fn(multiple, 4, 0x17, STATS_TYPE_BANK0), \
1064 _fn(out_fcs_error, 4, 0x03, STATS_TYPE_BANK0), \
1065 _fn(late, 4, 0x1f, STATS_TYPE_BANK0), \
1066 _fn(hist_64bytes, 4, 0x08, STATS_TYPE_BANK0), \
1067 _fn(hist_65_127bytes, 4, 0x09, STATS_TYPE_BANK0), \
1068 _fn(hist_128_255bytes, 4, 0x0a, STATS_TYPE_BANK0), \
1069 _fn(hist_256_511bytes, 4, 0x0b, STATS_TYPE_BANK0), \
1070 _fn(hist_512_1023bytes, 4, 0x0c, STATS_TYPE_BANK0), \
1071 _fn(hist_1024_max_bytes, 4, 0x0d, STATS_TYPE_BANK0), \
1072 _fn(sw_in_discards, 4, 0x10, STATS_TYPE_PORT), \
1073 _fn(sw_in_filtered, 2, 0x12, STATS_TYPE_PORT), \
1074 _fn(sw_out_filtered, 2, 0x13, STATS_TYPE_PORT), \
1075 _fn(in_discards, 4, 0x00, STATS_TYPE_BANK1), \
1076 _fn(in_filtered, 4, 0x01, STATS_TYPE_BANK1), \
1077 _fn(in_accepted, 4, 0x02, STATS_TYPE_BANK1), \
1078 _fn(in_bad_accepted, 4, 0x03, STATS_TYPE_BANK1), \
1079 _fn(in_good_avb_class_a, 4, 0x04, STATS_TYPE_BANK1), \
1080 _fn(in_good_avb_class_b, 4, 0x05, STATS_TYPE_BANK1), \
1081 _fn(in_bad_avb_class_a, 4, 0x06, STATS_TYPE_BANK1), \
1082 _fn(in_bad_avb_class_b, 4, 0x07, STATS_TYPE_BANK1), \
1083 _fn(tcam_counter_0, 4, 0x08, STATS_TYPE_BANK1), \
1084 _fn(tcam_counter_1, 4, 0x09, STATS_TYPE_BANK1), \
1085 _fn(tcam_counter_2, 4, 0x0a, STATS_TYPE_BANK1), \
1086 _fn(tcam_counter_3, 4, 0x0b, STATS_TYPE_BANK1), \
1087 _fn(in_da_unknown, 4, 0x0e, STATS_TYPE_BANK1), \
1088 _fn(in_management, 4, 0x0f, STATS_TYPE_BANK1), \
1089 _fn(out_queue_0, 4, 0x10, STATS_TYPE_BANK1), \
1090 _fn(out_queue_1, 4, 0x11, STATS_TYPE_BANK1), \
1091 _fn(out_queue_2, 4, 0x12, STATS_TYPE_BANK1), \
1092 _fn(out_queue_3, 4, 0x13, STATS_TYPE_BANK1), \
1093 _fn(out_queue_4, 4, 0x14, STATS_TYPE_BANK1), \
1094 _fn(out_queue_5, 4, 0x15, STATS_TYPE_BANK1), \
1095 _fn(out_queue_6, 4, 0x16, STATS_TYPE_BANK1), \
1096 _fn(out_queue_7, 4, 0x17, STATS_TYPE_BANK1), \
1097 _fn(out_cut_through, 4, 0x18, STATS_TYPE_BANK1), \
1098 _fn(out_octets_a, 4, 0x1a, STATS_TYPE_BANK1), \
1099 _fn(out_octets_b, 4, 0x1b, STATS_TYPE_BANK1), \
1100 _fn(out_management, 4, 0x1f, STATS_TYPE_BANK1), \
1101 /* */
1102
1103#define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \
1104 { #_string, _size, _reg, _type }
1105static const struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
1106 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENTRY)
1107};
1108
1109#define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \
1110 MV88E6XXX_HW_STAT_ID_ ## _string
1111enum mv88e6xxx_hw_stat_id {
1112 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENUM)
1113};
1114
1115static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
1116 const struct mv88e6xxx_hw_stat *s,
1117 int port, u16 bank1_select,
1118 u16 histogram)
1119{
1120 u32 low;
1121 u32 high = 0;
1122 u16 reg = 0;
1123 int err;
1124 u64 value;
1125
1126 switch (s->type) {
1127 case STATS_TYPE_PORT:
1128 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
1129 if (err)
1130 return U64_MAX;
1131
1132 low = reg;
1133 if (s->size == 4) {
1134 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
1135 if (err)
1136 return U64_MAX;
1137 low |= ((u32)reg) << 16;
1138 }
1139 break;
1140 case STATS_TYPE_BANK1:
1141 reg = bank1_select;
1142 fallthrough;
1143 case STATS_TYPE_BANK0:
1144 reg |= s->reg | histogram;
1145 mv88e6xxx_g1_stats_read(chip, reg, &low);
1146 if (s->size == 8)
1147 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
1148 break;
1149 default:
1150 return U64_MAX;
1151 }
1152 value = (((u64)high) << 32) | low;
1153 return value;
1154}
1155
1156static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
1157 uint8_t **data, int types)
1158{
1159 const struct mv88e6xxx_hw_stat *stat;
1160 int i;
1161
1162 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1163 stat = &mv88e6xxx_hw_stats[i];
1164 if (stat->type & types)
1165 ethtool_puts(data, stat->string);
1166 }
1167}
1168
1169static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
1170 uint8_t **data)
1171{
1172 mv88e6xxx_stats_get_strings(chip, data,
1173 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
1174}
1175
1176static void mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
1177 uint8_t **data)
1178{
1179 mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
1180}
1181
1182static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
1183 uint8_t **data)
1184{
1185 mv88e6xxx_stats_get_strings(chip, data,
1186 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
1187}
1188
1189static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
1190 "atu_member_violation",
1191 "atu_miss_violation",
1192 "atu_full_violation",
1193 "vtu_member_violation",
1194 "vtu_miss_violation",
1195};
1196
1197static void mv88e6xxx_atu_vtu_get_strings(uint8_t **data)
1198{
1199 unsigned int i;
1200
1201 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
1202 ethtool_puts(data, mv88e6xxx_atu_vtu_stats_strings[i]);
1203}
1204
1205static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
1206 u32 stringset, uint8_t *data)
1207{
1208 struct mv88e6xxx_chip *chip = ds->priv;
1209
1210 if (stringset != ETH_SS_STATS)
1211 return;
1212
1213 mv88e6xxx_reg_lock(chip);
1214
1215 if (chip->info->ops->stats_get_strings)
1216 chip->info->ops->stats_get_strings(chip, &data);
1217
1218 if (chip->info->ops->serdes_get_strings)
1219 chip->info->ops->serdes_get_strings(chip, port, &data);
1220
1221 mv88e6xxx_atu_vtu_get_strings(&data);
1222
1223 mv88e6xxx_reg_unlock(chip);
1224}
1225
1226static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1227 int types)
1228{
1229 const struct mv88e6xxx_hw_stat *stat;
1230 int i, j;
1231
1232 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1233 stat = &mv88e6xxx_hw_stats[i];
1234 if (stat->type & types)
1235 j++;
1236 }
1237 return j;
1238}
1239
1240static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1241{
1242 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1243 STATS_TYPE_PORT);
1244}
1245
1246static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1247{
1248 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1249}
1250
1251static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1252{
1253 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1254 STATS_TYPE_BANK1);
1255}
1256
1257static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1258{
1259 struct mv88e6xxx_chip *chip = ds->priv;
1260 int serdes_count = 0;
1261 int count = 0;
1262
1263 if (sset != ETH_SS_STATS)
1264 return 0;
1265
1266 mv88e6xxx_reg_lock(chip);
1267 if (chip->info->ops->stats_get_sset_count)
1268 count = chip->info->ops->stats_get_sset_count(chip);
1269 if (count < 0)
1270 goto out;
1271
1272 if (chip->info->ops->serdes_get_sset_count)
1273 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1274 port);
1275 if (serdes_count < 0) {
1276 count = serdes_count;
1277 goto out;
1278 }
1279 count += serdes_count;
1280 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1281
1282out:
1283 mv88e6xxx_reg_unlock(chip);
1284
1285 return count;
1286}
1287
1288static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1289 const struct mv88e6xxx_hw_stat *stat,
1290 uint64_t *data)
1291{
1292 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_PORT)))
1293 return 0;
1294
1295 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0,
1296 MV88E6XXX_G1_STATS_OP_HIST_RX);
1297 return 1;
1298}
1299
1300static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1301 const struct mv88e6xxx_hw_stat *stat,
1302 uint64_t *data)
1303{
1304 if (!(stat->type & STATS_TYPE_BANK0))
1305 return 0;
1306
1307 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0,
1308 MV88E6XXX_G1_STATS_OP_HIST_RX);
1309 return 1;
1310}
1311
1312static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1313 const struct mv88e6xxx_hw_stat *stat,
1314 uint64_t *data)
1315{
1316 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1)))
1317 return 0;
1318
1319 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1320 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1321 MV88E6XXX_G1_STATS_OP_HIST_RX);
1322 return 1;
1323}
1324
1325static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1326 const struct mv88e6xxx_hw_stat *stat,
1327 uint64_t *data)
1328{
1329 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1)))
1330 return 0;
1331
1332 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1333 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1334 0);
1335 return 1;
1336}
1337
1338static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1339 const struct mv88e6xxx_hw_stat *stat,
1340 uint64_t *data)
1341{
1342 int ret = 0;
1343
1344 if (chip->info->ops->stats_get_stat) {
1345 mv88e6xxx_reg_lock(chip);
1346 ret = chip->info->ops->stats_get_stat(chip, port, stat, data);
1347 mv88e6xxx_reg_unlock(chip);
1348 }
1349
1350 return ret;
1351}
1352
1353static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1354 uint64_t *data)
1355{
1356 const struct mv88e6xxx_hw_stat *stat;
1357 size_t i, j;
1358
1359 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1360 stat = &mv88e6xxx_hw_stats[i];
1361 j += mv88e6xxx_stats_get_stat(chip, port, stat, &data[j]);
1362 }
1363 return j;
1364}
1365
1366static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1367 uint64_t *data)
1368{
1369 *data++ = chip->ports[port].atu_member_violation;
1370 *data++ = chip->ports[port].atu_miss_violation;
1371 *data++ = chip->ports[port].atu_full_violation;
1372 *data++ = chip->ports[port].vtu_member_violation;
1373 *data++ = chip->ports[port].vtu_miss_violation;
1374}
1375
1376static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1377 uint64_t *data)
1378{
1379 size_t count;
1380
1381 count = mv88e6xxx_stats_get_stats(chip, port, data);
1382
1383 mv88e6xxx_reg_lock(chip);
1384 if (chip->info->ops->serdes_get_stats) {
1385 data += count;
1386 count = chip->info->ops->serdes_get_stats(chip, port, data);
1387 }
1388 data += count;
1389 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1390 mv88e6xxx_reg_unlock(chip);
1391}
1392
1393static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1394 uint64_t *data)
1395{
1396 struct mv88e6xxx_chip *chip = ds->priv;
1397 int ret;
1398
1399 ret = mv88e6xxx_stats_snapshot(chip, port);
1400 if (ret < 0)
1401 return;
1402
1403 mv88e6xxx_get_stats(chip, port, data);
1404}
1405
1406static void mv88e6xxx_get_eth_mac_stats(struct dsa_switch *ds, int port,
1407 struct ethtool_eth_mac_stats *mac_stats)
1408{
1409 struct mv88e6xxx_chip *chip = ds->priv;
1410 int ret;
1411
1412 ret = mv88e6xxx_stats_snapshot(chip, port);
1413 if (ret < 0)
1414 return;
1415
1416#define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member) \
1417 mv88e6xxx_stats_get_stat(chip, port, \
1418 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \
1419 &mac_stats->stats._member)
1420
1421 MV88E6XXX_ETH_MAC_STAT_MAP(out_unicast, FramesTransmittedOK);
1422 MV88E6XXX_ETH_MAC_STAT_MAP(single, SingleCollisionFrames);
1423 MV88E6XXX_ETH_MAC_STAT_MAP(multiple, MultipleCollisionFrames);
1424 MV88E6XXX_ETH_MAC_STAT_MAP(in_unicast, FramesReceivedOK);
1425 MV88E6XXX_ETH_MAC_STAT_MAP(in_fcs_error, FrameCheckSequenceErrors);
1426 MV88E6XXX_ETH_MAC_STAT_MAP(out_octets, OctetsTransmittedOK);
1427 MV88E6XXX_ETH_MAC_STAT_MAP(deferred, FramesWithDeferredXmissions);
1428 MV88E6XXX_ETH_MAC_STAT_MAP(late, LateCollisions);
1429 MV88E6XXX_ETH_MAC_STAT_MAP(in_good_octets, OctetsReceivedOK);
1430 MV88E6XXX_ETH_MAC_STAT_MAP(out_multicasts, MulticastFramesXmittedOK);
1431 MV88E6XXX_ETH_MAC_STAT_MAP(out_broadcasts, BroadcastFramesXmittedOK);
1432 MV88E6XXX_ETH_MAC_STAT_MAP(excessive, FramesWithExcessiveDeferral);
1433 MV88E6XXX_ETH_MAC_STAT_MAP(in_multicasts, MulticastFramesReceivedOK);
1434 MV88E6XXX_ETH_MAC_STAT_MAP(in_broadcasts, BroadcastFramesReceivedOK);
1435
1436#undef MV88E6XXX_ETH_MAC_STAT_MAP
1437
1438 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.MulticastFramesXmittedOK;
1439 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.BroadcastFramesXmittedOK;
1440 mac_stats->stats.FramesReceivedOK += mac_stats->stats.MulticastFramesReceivedOK;
1441 mac_stats->stats.FramesReceivedOK += mac_stats->stats.BroadcastFramesReceivedOK;
1442}
1443
1444static void mv88e6xxx_get_rmon_stats(struct dsa_switch *ds, int port,
1445 struct ethtool_rmon_stats *rmon_stats,
1446 const struct ethtool_rmon_hist_range **ranges)
1447{
1448 static const struct ethtool_rmon_hist_range rmon_ranges[] = {
1449 { 64, 64 },
1450 { 65, 127 },
1451 { 128, 255 },
1452 { 256, 511 },
1453 { 512, 1023 },
1454 { 1024, 65535 },
1455 {}
1456 };
1457 struct mv88e6xxx_chip *chip = ds->priv;
1458 int ret;
1459
1460 ret = mv88e6xxx_stats_snapshot(chip, port);
1461 if (ret < 0)
1462 return;
1463
1464#define MV88E6XXX_RMON_STAT_MAP(_id, _member) \
1465 mv88e6xxx_stats_get_stat(chip, port, \
1466 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \
1467 &rmon_stats->stats._member)
1468
1469 MV88E6XXX_RMON_STAT_MAP(in_undersize, undersize_pkts);
1470 MV88E6XXX_RMON_STAT_MAP(in_oversize, oversize_pkts);
1471 MV88E6XXX_RMON_STAT_MAP(in_fragments, fragments);
1472 MV88E6XXX_RMON_STAT_MAP(in_jabber, jabbers);
1473 MV88E6XXX_RMON_STAT_MAP(hist_64bytes, hist[0]);
1474 MV88E6XXX_RMON_STAT_MAP(hist_65_127bytes, hist[1]);
1475 MV88E6XXX_RMON_STAT_MAP(hist_128_255bytes, hist[2]);
1476 MV88E6XXX_RMON_STAT_MAP(hist_256_511bytes, hist[3]);
1477 MV88E6XXX_RMON_STAT_MAP(hist_512_1023bytes, hist[4]);
1478 MV88E6XXX_RMON_STAT_MAP(hist_1024_max_bytes, hist[5]);
1479
1480#undef MV88E6XXX_RMON_STAT_MAP
1481
1482 *ranges = rmon_ranges;
1483}
1484
1485static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1486{
1487 struct mv88e6xxx_chip *chip = ds->priv;
1488 int len;
1489
1490 len = 32 * sizeof(u16);
1491 if (chip->info->ops->serdes_get_regs_len)
1492 len += chip->info->ops->serdes_get_regs_len(chip, port);
1493
1494 return len;
1495}
1496
1497static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1498 struct ethtool_regs *regs, void *_p)
1499{
1500 struct mv88e6xxx_chip *chip = ds->priv;
1501 int err;
1502 u16 reg;
1503 u16 *p = _p;
1504 int i;
1505
1506 regs->version = chip->info->prod_num;
1507
1508 memset(p, 0xff, 32 * sizeof(u16));
1509
1510 mv88e6xxx_reg_lock(chip);
1511
1512 for (i = 0; i < 32; i++) {
1513
1514 err = mv88e6xxx_port_read(chip, port, i, ®);
1515 if (!err)
1516 p[i] = reg;
1517 }
1518
1519 if (chip->info->ops->serdes_get_regs)
1520 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1521
1522 mv88e6xxx_reg_unlock(chip);
1523}
1524
1525static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1526 struct ethtool_keee *e)
1527{
1528 /* Nothing to do on the port's MAC */
1529 return 0;
1530}
1531
1532static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1533 struct ethtool_keee *e)
1534{
1535 /* Nothing to do on the port's MAC */
1536 return 0;
1537}
1538
1539/* Mask of the local ports allowed to receive frames from a given fabric port */
1540static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1541{
1542 struct dsa_switch *ds = chip->ds;
1543 struct dsa_switch_tree *dst = ds->dst;
1544 struct dsa_port *dp, *other_dp;
1545 bool found = false;
1546 u16 pvlan;
1547
1548 /* dev is a physical switch */
1549 if (dev <= dst->last_switch) {
1550 list_for_each_entry(dp, &dst->ports, list) {
1551 if (dp->ds->index == dev && dp->index == port) {
1552 /* dp might be a DSA link or a user port, so it
1553 * might or might not have a bridge.
1554 * Use the "found" variable for both cases.
1555 */
1556 found = true;
1557 break;
1558 }
1559 }
1560 /* dev is a virtual bridge */
1561 } else {
1562 list_for_each_entry(dp, &dst->ports, list) {
1563 unsigned int bridge_num = dsa_port_bridge_num_get(dp);
1564
1565 if (!bridge_num)
1566 continue;
1567
1568 if (bridge_num + dst->last_switch != dev)
1569 continue;
1570
1571 found = true;
1572 break;
1573 }
1574 }
1575
1576 /* Prevent frames from unknown switch or virtual bridge */
1577 if (!found)
1578 return 0;
1579
1580 /* Frames from DSA links and CPU ports can egress any local port */
1581 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1582 return mv88e6xxx_port_mask(chip);
1583
1584 pvlan = 0;
1585
1586 /* Frames from standalone user ports can only egress on the
1587 * upstream port.
1588 */
1589 if (!dsa_port_bridge_dev_get(dp))
1590 return BIT(dsa_switch_upstream_port(ds));
1591
1592 /* Frames from bridged user ports can egress any local DSA
1593 * links and CPU ports, as well as any local member of their
1594 * bridge group.
1595 */
1596 dsa_switch_for_each_port(other_dp, ds)
1597 if (other_dp->type == DSA_PORT_TYPE_CPU ||
1598 other_dp->type == DSA_PORT_TYPE_DSA ||
1599 dsa_port_bridge_same(dp, other_dp))
1600 pvlan |= BIT(other_dp->index);
1601
1602 return pvlan;
1603}
1604
1605static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1606{
1607 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1608
1609 /* prevent frames from going back out of the port they came in on */
1610 output_ports &= ~BIT(port);
1611
1612 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1613}
1614
1615static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1616 u8 state)
1617{
1618 struct mv88e6xxx_chip *chip = ds->priv;
1619 int err;
1620
1621 mv88e6xxx_reg_lock(chip);
1622 err = mv88e6xxx_port_set_state(chip, port, state);
1623 mv88e6xxx_reg_unlock(chip);
1624
1625 if (err)
1626 dev_err(ds->dev, "p%d: failed to update state\n", port);
1627}
1628
1629static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1630{
1631 int err;
1632
1633 if (chip->info->ops->ieee_pri_map) {
1634 err = chip->info->ops->ieee_pri_map(chip);
1635 if (err)
1636 return err;
1637 }
1638
1639 if (chip->info->ops->ip_pri_map) {
1640 err = chip->info->ops->ip_pri_map(chip);
1641 if (err)
1642 return err;
1643 }
1644
1645 return 0;
1646}
1647
1648static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1649{
1650 struct dsa_switch *ds = chip->ds;
1651 int target, port;
1652 int err;
1653
1654 if (!chip->info->global2_addr)
1655 return 0;
1656
1657 /* Initialize the routing port to the 32 possible target devices */
1658 for (target = 0; target < 32; target++) {
1659 port = dsa_routing_port(ds, target);
1660 if (port == ds->num_ports)
1661 port = 0x1f;
1662
1663 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1664 if (err)
1665 return err;
1666 }
1667
1668 if (chip->info->ops->set_cascade_port) {
1669 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1670 err = chip->info->ops->set_cascade_port(chip, port);
1671 if (err)
1672 return err;
1673 }
1674
1675 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1676 if (err)
1677 return err;
1678
1679 return 0;
1680}
1681
1682static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1683{
1684 /* Clear all trunk masks and mapping */
1685 if (chip->info->global2_addr)
1686 return mv88e6xxx_g2_trunk_clear(chip);
1687
1688 return 0;
1689}
1690
1691static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1692{
1693 if (chip->info->ops->rmu_disable)
1694 return chip->info->ops->rmu_disable(chip);
1695
1696 return 0;
1697}
1698
1699static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1700{
1701 if (chip->info->ops->pot_clear)
1702 return chip->info->ops->pot_clear(chip);
1703
1704 return 0;
1705}
1706
1707static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1708{
1709 if (chip->info->ops->mgmt_rsvd2cpu)
1710 return chip->info->ops->mgmt_rsvd2cpu(chip);
1711
1712 return 0;
1713}
1714
1715static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1716{
1717 int err;
1718
1719 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1720 if (err)
1721 return err;
1722
1723 /* The chips that have a "learn2all" bit in Global1, ATU
1724 * Control are precisely those whose port registers have a
1725 * Message Port bit in Port Control 1 and hence implement
1726 * ->port_setup_message_port.
1727 */
1728 if (chip->info->ops->port_setup_message_port) {
1729 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1730 if (err)
1731 return err;
1732 }
1733
1734 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1735}
1736
1737static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1738{
1739 int port;
1740 int err;
1741
1742 if (!chip->info->ops->irl_init_all)
1743 return 0;
1744
1745 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1746 /* Disable ingress rate limiting by resetting all per port
1747 * ingress rate limit resources to their initial state.
1748 */
1749 err = chip->info->ops->irl_init_all(chip, port);
1750 if (err)
1751 return err;
1752 }
1753
1754 return 0;
1755}
1756
1757static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1758{
1759 if (chip->info->ops->set_switch_mac) {
1760 u8 addr[ETH_ALEN];
1761
1762 eth_random_addr(addr);
1763
1764 return chip->info->ops->set_switch_mac(chip, addr);
1765 }
1766
1767 return 0;
1768}
1769
1770static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1771{
1772 struct dsa_switch_tree *dst = chip->ds->dst;
1773 struct dsa_switch *ds;
1774 struct dsa_port *dp;
1775 u16 pvlan = 0;
1776
1777 if (!mv88e6xxx_has_pvt(chip))
1778 return 0;
1779
1780 /* Skip the local source device, which uses in-chip port VLAN */
1781 if (dev != chip->ds->index) {
1782 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1783
1784 ds = dsa_switch_find(dst->index, dev);
1785 dp = ds ? dsa_to_port(ds, port) : NULL;
1786 if (dp && dp->lag) {
1787 /* As the PVT is used to limit flooding of
1788 * FORWARD frames, which use the LAG ID as the
1789 * source port, we must translate dev/port to
1790 * the special "LAG device" in the PVT, using
1791 * the LAG ID (one-based) as the port number
1792 * (zero-based).
1793 */
1794 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1795 port = dsa_port_lag_id_get(dp) - 1;
1796 }
1797 }
1798
1799 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1800}
1801
1802static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1803{
1804 int dev, port;
1805 int err;
1806
1807 if (!mv88e6xxx_has_pvt(chip))
1808 return 0;
1809
1810 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1811 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1812 */
1813 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1814 if (err)
1815 return err;
1816
1817 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1818 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1819 err = mv88e6xxx_pvt_map(chip, dev, port);
1820 if (err)
1821 return err;
1822 }
1823 }
1824
1825 return 0;
1826}
1827
1828static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port,
1829 u16 fid)
1830{
1831 if (dsa_to_port(chip->ds, port)->lag)
1832 /* Hardware is incapable of fast-aging a LAG through a
1833 * regular ATU move operation. Until we have something
1834 * more fancy in place this is a no-op.
1835 */
1836 return -EOPNOTSUPP;
1837
1838 return mv88e6xxx_g1_atu_remove(chip, fid, port, false);
1839}
1840
1841static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1842{
1843 struct mv88e6xxx_chip *chip = ds->priv;
1844 int err;
1845
1846 mv88e6xxx_reg_lock(chip);
1847 err = mv88e6xxx_port_fast_age_fid(chip, port, 0);
1848 mv88e6xxx_reg_unlock(chip);
1849
1850 if (err)
1851 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n",
1852 port, err);
1853}
1854
1855static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1856{
1857 if (!mv88e6xxx_max_vid(chip))
1858 return 0;
1859
1860 return mv88e6xxx_g1_vtu_flush(chip);
1861}
1862
1863static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1864 struct mv88e6xxx_vtu_entry *entry)
1865{
1866 int err;
1867
1868 if (!chip->info->ops->vtu_getnext)
1869 return -EOPNOTSUPP;
1870
1871 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1872 entry->valid = false;
1873
1874 err = chip->info->ops->vtu_getnext(chip, entry);
1875
1876 if (entry->vid != vid)
1877 entry->valid = false;
1878
1879 return err;
1880}
1881
1882int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1883 int (*cb)(struct mv88e6xxx_chip *chip,
1884 const struct mv88e6xxx_vtu_entry *entry,
1885 void *priv),
1886 void *priv)
1887{
1888 struct mv88e6xxx_vtu_entry entry = {
1889 .vid = mv88e6xxx_max_vid(chip),
1890 .valid = false,
1891 };
1892 int err;
1893
1894 if (!chip->info->ops->vtu_getnext)
1895 return -EOPNOTSUPP;
1896
1897 do {
1898 err = chip->info->ops->vtu_getnext(chip, &entry);
1899 if (err)
1900 return err;
1901
1902 if (!entry.valid)
1903 break;
1904
1905 err = cb(chip, &entry, priv);
1906 if (err)
1907 return err;
1908 } while (entry.vid < mv88e6xxx_max_vid(chip));
1909
1910 return 0;
1911}
1912
1913static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1914 struct mv88e6xxx_vtu_entry *entry)
1915{
1916 if (!chip->info->ops->vtu_loadpurge)
1917 return -EOPNOTSUPP;
1918
1919 return chip->info->ops->vtu_loadpurge(chip, entry);
1920}
1921
1922static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1923{
1924 *fid = find_first_zero_bit(chip->fid_bitmap, MV88E6XXX_N_FID);
1925 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1926 return -ENOSPC;
1927
1928 /* Clear the database */
1929 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1930}
1931
1932static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1933 struct mv88e6xxx_stu_entry *entry)
1934{
1935 if (!chip->info->ops->stu_loadpurge)
1936 return -EOPNOTSUPP;
1937
1938 return chip->info->ops->stu_loadpurge(chip, entry);
1939}
1940
1941static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip)
1942{
1943 struct mv88e6xxx_stu_entry stu = {
1944 .valid = true,
1945 .sid = 0
1946 };
1947
1948 if (!mv88e6xxx_has_stu(chip))
1949 return 0;
1950
1951 /* Make sure that SID 0 is always valid. This is used by VTU
1952 * entries that do not make use of the STU, e.g. when creating
1953 * a VLAN upper on a port that is also part of a VLAN
1954 * filtering bridge.
1955 */
1956 return mv88e6xxx_stu_loadpurge(chip, &stu);
1957}
1958
1959static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid)
1960{
1961 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 };
1962 struct mv88e6xxx_mst *mst;
1963
1964 __set_bit(0, busy);
1965
1966 list_for_each_entry(mst, &chip->msts, node)
1967 __set_bit(mst->stu.sid, busy);
1968
1969 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID);
1970
1971 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0;
1972}
1973
1974static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid)
1975{
1976 struct mv88e6xxx_mst *mst, *tmp;
1977 int err;
1978
1979 if (!sid)
1980 return 0;
1981
1982 list_for_each_entry_safe(mst, tmp, &chip->msts, node) {
1983 if (mst->stu.sid != sid)
1984 continue;
1985
1986 if (!refcount_dec_and_test(&mst->refcnt))
1987 return 0;
1988
1989 mst->stu.valid = false;
1990 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1991 if (err) {
1992 refcount_set(&mst->refcnt, 1);
1993 return err;
1994 }
1995
1996 list_del(&mst->node);
1997 kfree(mst);
1998 return 0;
1999 }
2000
2001 return -ENOENT;
2002}
2003
2004static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br,
2005 u16 msti, u8 *sid)
2006{
2007 struct mv88e6xxx_mst *mst;
2008 int err, i;
2009
2010 if (!mv88e6xxx_has_stu(chip)) {
2011 err = -EOPNOTSUPP;
2012 goto err;
2013 }
2014
2015 if (!msti) {
2016 *sid = 0;
2017 return 0;
2018 }
2019
2020 list_for_each_entry(mst, &chip->msts, node) {
2021 if (mst->br == br && mst->msti == msti) {
2022 refcount_inc(&mst->refcnt);
2023 *sid = mst->stu.sid;
2024 return 0;
2025 }
2026 }
2027
2028 err = mv88e6xxx_sid_get(chip, sid);
2029 if (err)
2030 goto err;
2031
2032 mst = kzalloc(sizeof(*mst), GFP_KERNEL);
2033 if (!mst) {
2034 err = -ENOMEM;
2035 goto err;
2036 }
2037
2038 INIT_LIST_HEAD(&mst->node);
2039 refcount_set(&mst->refcnt, 1);
2040 mst->br = br;
2041 mst->msti = msti;
2042 mst->stu.valid = true;
2043 mst->stu.sid = *sid;
2044
2045 /* The bridge starts out all ports in the disabled state. But
2046 * a STU state of disabled means to go by the port-global
2047 * state. So we set all user port's initial state to blocking,
2048 * to match the bridge's behavior.
2049 */
2050 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
2051 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ?
2052 MV88E6XXX_PORT_CTL0_STATE_BLOCKING :
2053 MV88E6XXX_PORT_CTL0_STATE_DISABLED;
2054
2055 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2056 if (err)
2057 goto err_free;
2058
2059 list_add_tail(&mst->node, &chip->msts);
2060 return 0;
2061
2062err_free:
2063 kfree(mst);
2064err:
2065 return err;
2066}
2067
2068static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port,
2069 const struct switchdev_mst_state *st)
2070{
2071 struct dsa_port *dp = dsa_to_port(ds, port);
2072 struct mv88e6xxx_chip *chip = ds->priv;
2073 struct mv88e6xxx_mst *mst;
2074 u8 state;
2075 int err;
2076
2077 if (!mv88e6xxx_has_stu(chip))
2078 return -EOPNOTSUPP;
2079
2080 switch (st->state) {
2081 case BR_STATE_DISABLED:
2082 case BR_STATE_BLOCKING:
2083 case BR_STATE_LISTENING:
2084 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
2085 break;
2086 case BR_STATE_LEARNING:
2087 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
2088 break;
2089 case BR_STATE_FORWARDING:
2090 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2091 break;
2092 default:
2093 return -EINVAL;
2094 }
2095
2096 list_for_each_entry(mst, &chip->msts, node) {
2097 if (mst->br == dsa_port_bridge_dev_get(dp) &&
2098 mst->msti == st->msti) {
2099 if (mst->stu.state[port] == state)
2100 return 0;
2101
2102 mst->stu.state[port] = state;
2103 mv88e6xxx_reg_lock(chip);
2104 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2105 mv88e6xxx_reg_unlock(chip);
2106 return err;
2107 }
2108 }
2109
2110 return -ENOENT;
2111}
2112
2113static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
2114 u16 vid)
2115{
2116 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
2117 struct mv88e6xxx_chip *chip = ds->priv;
2118 struct mv88e6xxx_vtu_entry vlan;
2119 int err;
2120
2121 /* DSA and CPU ports have to be members of multiple vlans */
2122 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp))
2123 return 0;
2124
2125 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2126 if (err)
2127 return err;
2128
2129 if (!vlan.valid)
2130 return 0;
2131
2132 dsa_switch_for_each_user_port(other_dp, ds) {
2133 struct net_device *other_br;
2134
2135 if (vlan.member[other_dp->index] ==
2136 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2137 continue;
2138
2139 if (dsa_port_bridge_same(dp, other_dp))
2140 break; /* same bridge, check next VLAN */
2141
2142 other_br = dsa_port_bridge_dev_get(other_dp);
2143 if (!other_br)
2144 continue;
2145
2146 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
2147 port, vlan.vid, other_dp->index, netdev_name(other_br));
2148 return -EOPNOTSUPP;
2149 }
2150
2151 return 0;
2152}
2153
2154static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
2155{
2156 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2157 struct net_device *br = dsa_port_bridge_dev_get(dp);
2158 struct mv88e6xxx_port *p = &chip->ports[port];
2159 u16 pvid = MV88E6XXX_VID_STANDALONE;
2160 bool drop_untagged = false;
2161 int err;
2162
2163 if (br) {
2164 if (br_vlan_enabled(br)) {
2165 pvid = p->bridge_pvid.vid;
2166 drop_untagged = !p->bridge_pvid.valid;
2167 } else {
2168 pvid = MV88E6XXX_VID_BRIDGED;
2169 }
2170 }
2171
2172 err = mv88e6xxx_port_set_pvid(chip, port, pvid);
2173 if (err)
2174 return err;
2175
2176 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
2177}
2178
2179static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2180 bool vlan_filtering,
2181 struct netlink_ext_ack *extack)
2182{
2183 struct mv88e6xxx_chip *chip = ds->priv;
2184 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
2185 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
2186 int err;
2187
2188 if (!mv88e6xxx_max_vid(chip))
2189 return -EOPNOTSUPP;
2190
2191 mv88e6xxx_reg_lock(chip);
2192
2193 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
2194 if (err)
2195 goto unlock;
2196
2197 err = mv88e6xxx_port_commit_pvid(chip, port);
2198 if (err)
2199 goto unlock;
2200
2201unlock:
2202 mv88e6xxx_reg_unlock(chip);
2203
2204 return err;
2205}
2206
2207static int
2208mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2209 const struct switchdev_obj_port_vlan *vlan)
2210{
2211 struct mv88e6xxx_chip *chip = ds->priv;
2212 int err;
2213
2214 if (!mv88e6xxx_max_vid(chip))
2215 return -EOPNOTSUPP;
2216
2217 /* If the requested port doesn't belong to the same bridge as the VLAN
2218 * members, do not support it (yet) and fallback to software VLAN.
2219 */
2220 mv88e6xxx_reg_lock(chip);
2221 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
2222 mv88e6xxx_reg_unlock(chip);
2223
2224 return err;
2225}
2226
2227static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2228 const unsigned char *addr, u16 vid,
2229 u8 state)
2230{
2231 struct mv88e6xxx_atu_entry entry;
2232 struct mv88e6xxx_vtu_entry vlan;
2233 u16 fid;
2234 int err;
2235
2236 /* Ports have two private address databases: one for when the port is
2237 * standalone and one for when the port is under a bridge and the
2238 * 802.1Q mode is disabled. When the port is standalone, DSA wants its
2239 * address database to remain 100% empty, so we never load an ATU entry
2240 * into a standalone port's database. Therefore, translate the null
2241 * VLAN ID into the port's database used for VLAN-unaware bridging.
2242 */
2243 if (vid == 0) {
2244 fid = MV88E6XXX_FID_BRIDGED;
2245 } else {
2246 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2247 if (err)
2248 return err;
2249
2250 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
2251 if (!vlan.valid)
2252 return -EOPNOTSUPP;
2253
2254 fid = vlan.fid;
2255 }
2256
2257 entry.state = 0;
2258 ether_addr_copy(entry.mac, addr);
2259 eth_addr_dec(entry.mac);
2260
2261 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
2262 if (err)
2263 return err;
2264
2265 /* Initialize a fresh ATU entry if it isn't found */
2266 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
2267 memset(&entry, 0, sizeof(entry));
2268 ether_addr_copy(entry.mac, addr);
2269 }
2270
2271 /* Purge the ATU entry only if no port is using it anymore */
2272 if (!state) {
2273 entry.portvec &= ~BIT(port);
2274 if (!entry.portvec)
2275 entry.state = 0;
2276 } else {
2277 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
2278 entry.portvec = BIT(port);
2279 else
2280 entry.portvec |= BIT(port);
2281
2282 entry.state = state;
2283 }
2284
2285 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
2286}
2287
2288static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
2289 const struct mv88e6xxx_policy *policy)
2290{
2291 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
2292 enum mv88e6xxx_policy_action action = policy->action;
2293 const u8 *addr = policy->addr;
2294 u16 vid = policy->vid;
2295 u8 state;
2296 int err;
2297 int id;
2298
2299 if (!chip->info->ops->port_set_policy)
2300 return -EOPNOTSUPP;
2301
2302 switch (mapping) {
2303 case MV88E6XXX_POLICY_MAPPING_DA:
2304 case MV88E6XXX_POLICY_MAPPING_SA:
2305 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2306 state = 0; /* Dissociate the port and address */
2307 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2308 is_multicast_ether_addr(addr))
2309 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
2310 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2311 is_unicast_ether_addr(addr))
2312 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
2313 else
2314 return -EOPNOTSUPP;
2315
2316 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2317 state);
2318 if (err)
2319 return err;
2320 break;
2321 default:
2322 return -EOPNOTSUPP;
2323 }
2324
2325 /* Skip the port's policy clearing if the mapping is still in use */
2326 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2327 idr_for_each_entry(&chip->policies, policy, id)
2328 if (policy->port == port &&
2329 policy->mapping == mapping &&
2330 policy->action != action)
2331 return 0;
2332
2333 return chip->info->ops->port_set_policy(chip, port, mapping, action);
2334}
2335
2336static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
2337 struct ethtool_rx_flow_spec *fs)
2338{
2339 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
2340 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
2341 enum mv88e6xxx_policy_mapping mapping;
2342 enum mv88e6xxx_policy_action action;
2343 struct mv88e6xxx_policy *policy;
2344 u16 vid = 0;
2345 u8 *addr;
2346 int err;
2347 int id;
2348
2349 if (fs->location != RX_CLS_LOC_ANY)
2350 return -EINVAL;
2351
2352 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
2353 action = MV88E6XXX_POLICY_ACTION_DISCARD;
2354 else
2355 return -EOPNOTSUPP;
2356
2357 switch (fs->flow_type & ~FLOW_EXT) {
2358 case ETHER_FLOW:
2359 if (!is_zero_ether_addr(mac_mask->h_dest) &&
2360 is_zero_ether_addr(mac_mask->h_source)) {
2361 mapping = MV88E6XXX_POLICY_MAPPING_DA;
2362 addr = mac_entry->h_dest;
2363 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
2364 !is_zero_ether_addr(mac_mask->h_source)) {
2365 mapping = MV88E6XXX_POLICY_MAPPING_SA;
2366 addr = mac_entry->h_source;
2367 } else {
2368 /* Cannot support DA and SA mapping in the same rule */
2369 return -EOPNOTSUPP;
2370 }
2371 break;
2372 default:
2373 return -EOPNOTSUPP;
2374 }
2375
2376 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
2377 if (fs->m_ext.vlan_tci != htons(0xffff))
2378 return -EOPNOTSUPP;
2379 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
2380 }
2381
2382 idr_for_each_entry(&chip->policies, policy, id) {
2383 if (policy->port == port && policy->mapping == mapping &&
2384 policy->action == action && policy->vid == vid &&
2385 ether_addr_equal(policy->addr, addr))
2386 return -EEXIST;
2387 }
2388
2389 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
2390 if (!policy)
2391 return -ENOMEM;
2392
2393 fs->location = 0;
2394 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
2395 GFP_KERNEL);
2396 if (err) {
2397 devm_kfree(chip->dev, policy);
2398 return err;
2399 }
2400
2401 memcpy(&policy->fs, fs, sizeof(*fs));
2402 ether_addr_copy(policy->addr, addr);
2403 policy->mapping = mapping;
2404 policy->action = action;
2405 policy->port = port;
2406 policy->vid = vid;
2407
2408 err = mv88e6xxx_policy_apply(chip, port, policy);
2409 if (err) {
2410 idr_remove(&chip->policies, fs->location);
2411 devm_kfree(chip->dev, policy);
2412 return err;
2413 }
2414
2415 return 0;
2416}
2417
2418static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
2419 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
2420{
2421 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2422 struct mv88e6xxx_chip *chip = ds->priv;
2423 struct mv88e6xxx_policy *policy;
2424 int err;
2425 int id;
2426
2427 mv88e6xxx_reg_lock(chip);
2428
2429 switch (rxnfc->cmd) {
2430 case ETHTOOL_GRXCLSRLCNT:
2431 rxnfc->data = 0;
2432 rxnfc->data |= RX_CLS_LOC_SPECIAL;
2433 rxnfc->rule_cnt = 0;
2434 idr_for_each_entry(&chip->policies, policy, id)
2435 if (policy->port == port)
2436 rxnfc->rule_cnt++;
2437 err = 0;
2438 break;
2439 case ETHTOOL_GRXCLSRULE:
2440 err = -ENOENT;
2441 policy = idr_find(&chip->policies, fs->location);
2442 if (policy) {
2443 memcpy(fs, &policy->fs, sizeof(*fs));
2444 err = 0;
2445 }
2446 break;
2447 case ETHTOOL_GRXCLSRLALL:
2448 rxnfc->data = 0;
2449 rxnfc->rule_cnt = 0;
2450 idr_for_each_entry(&chip->policies, policy, id)
2451 if (policy->port == port)
2452 rule_locs[rxnfc->rule_cnt++] = id;
2453 err = 0;
2454 break;
2455 default:
2456 err = -EOPNOTSUPP;
2457 break;
2458 }
2459
2460 mv88e6xxx_reg_unlock(chip);
2461
2462 return err;
2463}
2464
2465static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
2466 struct ethtool_rxnfc *rxnfc)
2467{
2468 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2469 struct mv88e6xxx_chip *chip = ds->priv;
2470 struct mv88e6xxx_policy *policy;
2471 int err;
2472
2473 mv88e6xxx_reg_lock(chip);
2474
2475 switch (rxnfc->cmd) {
2476 case ETHTOOL_SRXCLSRLINS:
2477 err = mv88e6xxx_policy_insert(chip, port, fs);
2478 break;
2479 case ETHTOOL_SRXCLSRLDEL:
2480 err = -ENOENT;
2481 policy = idr_remove(&chip->policies, fs->location);
2482 if (policy) {
2483 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
2484 err = mv88e6xxx_policy_apply(chip, port, policy);
2485 devm_kfree(chip->dev, policy);
2486 }
2487 break;
2488 default:
2489 err = -EOPNOTSUPP;
2490 break;
2491 }
2492
2493 mv88e6xxx_reg_unlock(chip);
2494
2495 return err;
2496}
2497
2498static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
2499 u16 vid)
2500{
2501 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2502 u8 broadcast[ETH_ALEN];
2503
2504 eth_broadcast_addr(broadcast);
2505
2506 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
2507}
2508
2509static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
2510{
2511 int port;
2512 int err;
2513
2514 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2515 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2516 struct net_device *brport;
2517
2518 if (dsa_is_unused_port(chip->ds, port))
2519 continue;
2520
2521 brport = dsa_port_to_bridge_port(dp);
2522 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
2523 /* Skip bridged user ports where broadcast
2524 * flooding is disabled.
2525 */
2526 continue;
2527
2528 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2529 if (err)
2530 return err;
2531 }
2532
2533 return 0;
2534}
2535
2536struct mv88e6xxx_port_broadcast_sync_ctx {
2537 int port;
2538 bool flood;
2539};
2540
2541static int
2542mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2543 const struct mv88e6xxx_vtu_entry *vlan,
2544 void *_ctx)
2545{
2546 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2547 u8 broadcast[ETH_ALEN];
2548 u8 state;
2549
2550 if (ctx->flood)
2551 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2552 else
2553 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2554
2555 eth_broadcast_addr(broadcast);
2556
2557 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2558 vlan->vid, state);
2559}
2560
2561static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2562 bool flood)
2563{
2564 struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2565 .port = port,
2566 .flood = flood,
2567 };
2568 struct mv88e6xxx_vtu_entry vid0 = {
2569 .vid = 0,
2570 };
2571 int err;
2572
2573 /* Update the port's private database... */
2574 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2575 if (err)
2576 return err;
2577
2578 /* ...and the database for all VLANs. */
2579 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2580 &ctx);
2581}
2582
2583static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2584 u16 vid, u8 member, bool warn)
2585{
2586 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2587 struct mv88e6xxx_vtu_entry vlan;
2588 int i, err;
2589
2590 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2591 if (err)
2592 return err;
2593
2594 if (!vlan.valid) {
2595 memset(&vlan, 0, sizeof(vlan));
2596
2597 if (vid == MV88E6XXX_VID_STANDALONE)
2598 vlan.policy = true;
2599
2600 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2601 if (err)
2602 return err;
2603
2604 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2605 if (i == port)
2606 vlan.member[i] = member;
2607 else
2608 vlan.member[i] = non_member;
2609
2610 vlan.vid = vid;
2611 vlan.valid = true;
2612
2613 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2614 if (err)
2615 return err;
2616
2617 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2618 if (err)
2619 return err;
2620 } else if (vlan.member[port] != member) {
2621 vlan.member[port] = member;
2622
2623 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2624 if (err)
2625 return err;
2626 } else if (warn) {
2627 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2628 port, vid);
2629 }
2630
2631 /* Record FID used in SW FID map */
2632 bitmap_set(chip->fid_bitmap, vlan.fid, 1);
2633
2634 return 0;
2635}
2636
2637static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2638 const struct switchdev_obj_port_vlan *vlan,
2639 struct netlink_ext_ack *extack)
2640{
2641 struct mv88e6xxx_chip *chip = ds->priv;
2642 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2643 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2644 struct mv88e6xxx_port *p = &chip->ports[port];
2645 bool warn;
2646 u8 member;
2647 int err;
2648
2649 if (!vlan->vid)
2650 return 0;
2651
2652 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2653 if (err)
2654 return err;
2655
2656 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2657 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2658 else if (untagged)
2659 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2660 else
2661 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2662
2663 /* net/dsa/user.c will call dsa_port_vlan_add() for the affected port
2664 * and then the CPU port. Do not warn for duplicates for the CPU port.
2665 */
2666 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2667
2668 mv88e6xxx_reg_lock(chip);
2669
2670 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2671 if (err) {
2672 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2673 vlan->vid, untagged ? 'u' : 't');
2674 goto out;
2675 }
2676
2677 if (pvid) {
2678 p->bridge_pvid.vid = vlan->vid;
2679 p->bridge_pvid.valid = true;
2680
2681 err = mv88e6xxx_port_commit_pvid(chip, port);
2682 if (err)
2683 goto out;
2684 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) {
2685 /* The old pvid was reinstalled as a non-pvid VLAN */
2686 p->bridge_pvid.valid = false;
2687
2688 err = mv88e6xxx_port_commit_pvid(chip, port);
2689 if (err)
2690 goto out;
2691 }
2692
2693out:
2694 mv88e6xxx_reg_unlock(chip);
2695
2696 return err;
2697}
2698
2699static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2700 int port, u16 vid)
2701{
2702 struct mv88e6xxx_vtu_entry vlan;
2703 int i, err;
2704
2705 if (!vid)
2706 return 0;
2707
2708 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2709 if (err)
2710 return err;
2711
2712 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2713 * tell switchdev that this VLAN is likely handled in software.
2714 */
2715 if (!vlan.valid ||
2716 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2717 return -EOPNOTSUPP;
2718
2719 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2720
2721 /* keep the VLAN unless all ports are excluded */
2722 vlan.valid = false;
2723 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2724 if (vlan.member[i] !=
2725 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2726 vlan.valid = true;
2727 break;
2728 }
2729 }
2730
2731 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2732 if (err)
2733 return err;
2734
2735 if (!vlan.valid) {
2736 err = mv88e6xxx_mst_put(chip, vlan.sid);
2737 if (err)
2738 return err;
2739
2740 /* Record FID freed in SW FID map */
2741 bitmap_clear(chip->fid_bitmap, vlan.fid, 1);
2742 }
2743
2744 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2745}
2746
2747static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2748 const struct switchdev_obj_port_vlan *vlan)
2749{
2750 struct mv88e6xxx_chip *chip = ds->priv;
2751 struct mv88e6xxx_port *p = &chip->ports[port];
2752 int err = 0;
2753 u16 pvid;
2754
2755 if (!mv88e6xxx_max_vid(chip))
2756 return -EOPNOTSUPP;
2757
2758 /* The ATU removal procedure needs the FID to be mapped in the VTU,
2759 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA
2760 * switchdev workqueue to ensure that all FDB entries are deleted
2761 * before we remove the VLAN.
2762 */
2763 dsa_flush_workqueue();
2764
2765 mv88e6xxx_reg_lock(chip);
2766
2767 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2768 if (err)
2769 goto unlock;
2770
2771 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2772 if (err)
2773 goto unlock;
2774
2775 if (vlan->vid == pvid) {
2776 p->bridge_pvid.valid = false;
2777
2778 err = mv88e6xxx_port_commit_pvid(chip, port);
2779 if (err)
2780 goto unlock;
2781 }
2782
2783unlock:
2784 mv88e6xxx_reg_unlock(chip);
2785
2786 return err;
2787}
2788
2789static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid)
2790{
2791 struct mv88e6xxx_chip *chip = ds->priv;
2792 struct mv88e6xxx_vtu_entry vlan;
2793 int err;
2794
2795 mv88e6xxx_reg_lock(chip);
2796
2797 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2798 if (err)
2799 goto unlock;
2800
2801 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid);
2802
2803unlock:
2804 mv88e6xxx_reg_unlock(chip);
2805
2806 return err;
2807}
2808
2809static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds,
2810 struct dsa_bridge bridge,
2811 const struct switchdev_vlan_msti *msti)
2812{
2813 struct mv88e6xxx_chip *chip = ds->priv;
2814 struct mv88e6xxx_vtu_entry vlan;
2815 u8 old_sid, new_sid;
2816 int err;
2817
2818 if (!mv88e6xxx_has_stu(chip))
2819 return -EOPNOTSUPP;
2820
2821 mv88e6xxx_reg_lock(chip);
2822
2823 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan);
2824 if (err)
2825 goto unlock;
2826
2827 if (!vlan.valid) {
2828 err = -EINVAL;
2829 goto unlock;
2830 }
2831
2832 old_sid = vlan.sid;
2833
2834 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid);
2835 if (err)
2836 goto unlock;
2837
2838 if (new_sid != old_sid) {
2839 vlan.sid = new_sid;
2840
2841 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2842 if (err) {
2843 mv88e6xxx_mst_put(chip, new_sid);
2844 goto unlock;
2845 }
2846 }
2847
2848 err = mv88e6xxx_mst_put(chip, old_sid);
2849
2850unlock:
2851 mv88e6xxx_reg_unlock(chip);
2852 return err;
2853}
2854
2855static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2856 const unsigned char *addr, u16 vid,
2857 struct dsa_db db)
2858{
2859 struct mv88e6xxx_chip *chip = ds->priv;
2860 int err;
2861
2862 mv88e6xxx_reg_lock(chip);
2863 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2864 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2865 mv88e6xxx_reg_unlock(chip);
2866
2867 return err;
2868}
2869
2870static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2871 const unsigned char *addr, u16 vid,
2872 struct dsa_db db)
2873{
2874 struct mv88e6xxx_chip *chip = ds->priv;
2875 int err;
2876
2877 mv88e6xxx_reg_lock(chip);
2878 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2879 mv88e6xxx_reg_unlock(chip);
2880
2881 return err;
2882}
2883
2884static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2885 u16 fid, u16 vid, int port,
2886 dsa_fdb_dump_cb_t *cb, void *data)
2887{
2888 struct mv88e6xxx_atu_entry addr;
2889 bool is_static;
2890 int err;
2891
2892 addr.state = 0;
2893 eth_broadcast_addr(addr.mac);
2894
2895 do {
2896 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2897 if (err)
2898 return err;
2899
2900 if (!addr.state)
2901 break;
2902
2903 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2904 continue;
2905
2906 if (!is_unicast_ether_addr(addr.mac))
2907 continue;
2908
2909 is_static = (addr.state ==
2910 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2911 err = cb(addr.mac, vid, is_static, data);
2912 if (err)
2913 return err;
2914 } while (!is_broadcast_ether_addr(addr.mac));
2915
2916 return err;
2917}
2918
2919struct mv88e6xxx_port_db_dump_vlan_ctx {
2920 int port;
2921 dsa_fdb_dump_cb_t *cb;
2922 void *data;
2923};
2924
2925static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2926 const struct mv88e6xxx_vtu_entry *entry,
2927 void *_data)
2928{
2929 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2930
2931 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2932 ctx->port, ctx->cb, ctx->data);
2933}
2934
2935static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2936 dsa_fdb_dump_cb_t *cb, void *data)
2937{
2938 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2939 .port = port,
2940 .cb = cb,
2941 .data = data,
2942 };
2943 u16 fid;
2944 int err;
2945
2946 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2947 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2948 if (err)
2949 return err;
2950
2951 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2952 if (err)
2953 return err;
2954
2955 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
2956}
2957
2958static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2959 dsa_fdb_dump_cb_t *cb, void *data)
2960{
2961 struct mv88e6xxx_chip *chip = ds->priv;
2962 int err;
2963
2964 mv88e6xxx_reg_lock(chip);
2965 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2966 mv88e6xxx_reg_unlock(chip);
2967
2968 return err;
2969}
2970
2971static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2972 struct dsa_bridge bridge)
2973{
2974 struct dsa_switch *ds = chip->ds;
2975 struct dsa_switch_tree *dst = ds->dst;
2976 struct dsa_port *dp;
2977 int err;
2978
2979 list_for_each_entry(dp, &dst->ports, list) {
2980 if (dsa_port_offloads_bridge(dp, &bridge)) {
2981 if (dp->ds == ds) {
2982 /* This is a local bridge group member,
2983 * remap its Port VLAN Map.
2984 */
2985 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2986 if (err)
2987 return err;
2988 } else {
2989 /* This is an external bridge group member,
2990 * remap its cross-chip Port VLAN Table entry.
2991 */
2992 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2993 dp->index);
2994 if (err)
2995 return err;
2996 }
2997 }
2998 }
2999
3000 return 0;
3001}
3002
3003/* Treat the software bridge as a virtual single-port switch behind the
3004 * CPU and map in the PVT. First dst->last_switch elements are taken by
3005 * physical switches, so start from beyond that range.
3006 */
3007static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
3008 unsigned int bridge_num)
3009{
3010 u8 dev = bridge_num + ds->dst->last_switch;
3011 struct mv88e6xxx_chip *chip = ds->priv;
3012
3013 return mv88e6xxx_pvt_map(chip, dev, 0);
3014}
3015
3016static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
3017 struct dsa_bridge bridge,
3018 bool *tx_fwd_offload,
3019 struct netlink_ext_ack *extack)
3020{
3021 struct mv88e6xxx_chip *chip = ds->priv;
3022 int err;
3023
3024 mv88e6xxx_reg_lock(chip);
3025
3026 err = mv88e6xxx_bridge_map(chip, bridge);
3027 if (err)
3028 goto unlock;
3029
3030 err = mv88e6xxx_port_set_map_da(chip, port, true);
3031 if (err)
3032 goto unlock;
3033
3034 err = mv88e6xxx_port_commit_pvid(chip, port);
3035 if (err)
3036 goto unlock;
3037
3038 if (mv88e6xxx_has_pvt(chip)) {
3039 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
3040 if (err)
3041 goto unlock;
3042
3043 *tx_fwd_offload = true;
3044 }
3045
3046unlock:
3047 mv88e6xxx_reg_unlock(chip);
3048
3049 return err;
3050}
3051
3052static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
3053 struct dsa_bridge bridge)
3054{
3055 struct mv88e6xxx_chip *chip = ds->priv;
3056 int err;
3057
3058 mv88e6xxx_reg_lock(chip);
3059
3060 if (bridge.tx_fwd_offload &&
3061 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
3062 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3063
3064 if (mv88e6xxx_bridge_map(chip, bridge) ||
3065 mv88e6xxx_port_vlan_map(chip, port))
3066 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
3067
3068 err = mv88e6xxx_port_set_map_da(chip, port, false);
3069 if (err)
3070 dev_err(ds->dev,
3071 "port %d failed to restore map-DA: %pe\n",
3072 port, ERR_PTR(err));
3073
3074 err = mv88e6xxx_port_commit_pvid(chip, port);
3075 if (err)
3076 dev_err(ds->dev,
3077 "port %d failed to restore standalone pvid: %pe\n",
3078 port, ERR_PTR(err));
3079
3080 mv88e6xxx_reg_unlock(chip);
3081}
3082
3083static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
3084 int tree_index, int sw_index,
3085 int port, struct dsa_bridge bridge,
3086 struct netlink_ext_ack *extack)
3087{
3088 struct mv88e6xxx_chip *chip = ds->priv;
3089 int err;
3090
3091 if (tree_index != ds->dst->index)
3092 return 0;
3093
3094 mv88e6xxx_reg_lock(chip);
3095 err = mv88e6xxx_pvt_map(chip, sw_index, port);
3096 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
3097 mv88e6xxx_reg_unlock(chip);
3098
3099 return err;
3100}
3101
3102static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
3103 int tree_index, int sw_index,
3104 int port, struct dsa_bridge bridge)
3105{
3106 struct mv88e6xxx_chip *chip = ds->priv;
3107
3108 if (tree_index != ds->dst->index)
3109 return;
3110
3111 mv88e6xxx_reg_lock(chip);
3112 if (mv88e6xxx_pvt_map(chip, sw_index, port) ||
3113 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
3114 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3115 mv88e6xxx_reg_unlock(chip);
3116}
3117
3118static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
3119{
3120 if (chip->info->ops->reset)
3121 return chip->info->ops->reset(chip);
3122
3123 return 0;
3124}
3125
3126static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
3127{
3128 struct gpio_desc *gpiod = chip->reset;
3129 int err;
3130
3131 /* If there is a GPIO connected to the reset pin, toggle it */
3132 if (gpiod) {
3133 /* If the switch has just been reset and not yet completed
3134 * loading EEPROM, the reset may interrupt the I2C transaction
3135 * mid-byte, causing the first EEPROM read after the reset
3136 * from the wrong location resulting in the switch booting
3137 * to wrong mode and inoperable.
3138 * For this reason, switch families with EEPROM support
3139 * generally wait for EEPROM loads to complete as their pre-
3140 * and post-reset handlers.
3141 */
3142 if (chip->info->ops->hardware_reset_pre) {
3143 err = chip->info->ops->hardware_reset_pre(chip);
3144 if (err)
3145 dev_err(chip->dev, "pre-reset error: %d\n", err);
3146 }
3147
3148 gpiod_set_value_cansleep(gpiod, 1);
3149 usleep_range(10000, 20000);
3150 gpiod_set_value_cansleep(gpiod, 0);
3151 usleep_range(10000, 20000);
3152
3153 if (chip->info->ops->hardware_reset_post) {
3154 err = chip->info->ops->hardware_reset_post(chip);
3155 if (err)
3156 dev_err(chip->dev, "post-reset error: %d\n", err);
3157 }
3158 }
3159}
3160
3161static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
3162{
3163 int i, err;
3164
3165 /* Set all ports to the Disabled state */
3166 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3167 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
3168 if (err)
3169 return err;
3170 }
3171
3172 /* Wait for transmit queues to drain,
3173 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
3174 */
3175 usleep_range(2000, 4000);
3176
3177 return 0;
3178}
3179
3180static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
3181{
3182 int err;
3183
3184 err = mv88e6xxx_disable_ports(chip);
3185 if (err)
3186 return err;
3187
3188 mv88e6xxx_hardware_reset(chip);
3189
3190 return mv88e6xxx_software_reset(chip);
3191}
3192
3193static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
3194 enum mv88e6xxx_frame_mode frame,
3195 enum mv88e6xxx_egress_mode egress, u16 etype)
3196{
3197 int err;
3198
3199 if (!chip->info->ops->port_set_frame_mode)
3200 return -EOPNOTSUPP;
3201
3202 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
3203 if (err)
3204 return err;
3205
3206 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
3207 if (err)
3208 return err;
3209
3210 if (chip->info->ops->port_set_ether_type)
3211 return chip->info->ops->port_set_ether_type(chip, port, etype);
3212
3213 return 0;
3214}
3215
3216static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
3217{
3218 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
3219 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3220 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3221}
3222
3223static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
3224{
3225 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
3226 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3227 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3228}
3229
3230static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
3231{
3232 return mv88e6xxx_set_port_mode(chip, port,
3233 MV88E6XXX_FRAME_MODE_ETHERTYPE,
3234 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
3235 ETH_P_EDSA);
3236}
3237
3238static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
3239{
3240 if (dsa_is_dsa_port(chip->ds, port))
3241 return mv88e6xxx_set_port_mode_dsa(chip, port);
3242
3243 if (dsa_is_user_port(chip->ds, port))
3244 return mv88e6xxx_set_port_mode_normal(chip, port);
3245
3246 /* Setup CPU port mode depending on its supported tag format */
3247 if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
3248 return mv88e6xxx_set_port_mode_dsa(chip, port);
3249
3250 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
3251 return mv88e6xxx_set_port_mode_edsa(chip, port);
3252
3253 return -EINVAL;
3254}
3255
3256static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
3257{
3258 bool message = dsa_is_dsa_port(chip->ds, port);
3259
3260 return mv88e6xxx_port_set_message_port(chip, port, message);
3261}
3262
3263static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
3264{
3265 int err;
3266
3267 if (chip->info->ops->port_set_ucast_flood) {
3268 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
3269 if (err)
3270 return err;
3271 }
3272 if (chip->info->ops->port_set_mcast_flood) {
3273 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
3274 if (err)
3275 return err;
3276 }
3277
3278 return 0;
3279}
3280
3281static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
3282 enum mv88e6xxx_egress_direction direction,
3283 int port)
3284{
3285 int err;
3286
3287 if (!chip->info->ops->set_egress_port)
3288 return -EOPNOTSUPP;
3289
3290 err = chip->info->ops->set_egress_port(chip, direction, port);
3291 if (err)
3292 return err;
3293
3294 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
3295 chip->ingress_dest_port = port;
3296 else
3297 chip->egress_dest_port = port;
3298
3299 return 0;
3300}
3301
3302static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
3303{
3304 struct dsa_switch *ds = chip->ds;
3305 int upstream_port;
3306 int err;
3307
3308 upstream_port = dsa_upstream_port(ds, port);
3309 if (chip->info->ops->port_set_upstream_port) {
3310 err = chip->info->ops->port_set_upstream_port(chip, port,
3311 upstream_port);
3312 if (err)
3313 return err;
3314 }
3315
3316 if (port == upstream_port) {
3317 if (chip->info->ops->set_cpu_port) {
3318 err = chip->info->ops->set_cpu_port(chip,
3319 upstream_port);
3320 if (err)
3321 return err;
3322 }
3323
3324 err = mv88e6xxx_set_egress_port(chip,
3325 MV88E6XXX_EGRESS_DIR_INGRESS,
3326 upstream_port);
3327 if (err && err != -EOPNOTSUPP)
3328 return err;
3329
3330 err = mv88e6xxx_set_egress_port(chip,
3331 MV88E6XXX_EGRESS_DIR_EGRESS,
3332 upstream_port);
3333 if (err && err != -EOPNOTSUPP)
3334 return err;
3335 }
3336
3337 return 0;
3338}
3339
3340static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
3341{
3342 struct device_node *phy_handle = NULL;
3343 struct fwnode_handle *ports_fwnode;
3344 struct fwnode_handle *port_fwnode;
3345 struct dsa_switch *ds = chip->ds;
3346 struct mv88e6xxx_port *p;
3347 struct dsa_port *dp;
3348 int tx_amp;
3349 int err;
3350 u16 reg;
3351 u32 val;
3352
3353 p = &chip->ports[port];
3354 p->chip = chip;
3355 p->port = port;
3356
3357 /* Look up corresponding fwnode if any */
3358 ports_fwnode = device_get_named_child_node(chip->dev, "ethernet-ports");
3359 if (!ports_fwnode)
3360 ports_fwnode = device_get_named_child_node(chip->dev, "ports");
3361 if (ports_fwnode) {
3362 fwnode_for_each_child_node(ports_fwnode, port_fwnode) {
3363 if (fwnode_property_read_u32(port_fwnode, "reg", &val))
3364 continue;
3365 if (val == port) {
3366 p->fwnode = port_fwnode;
3367 p->fiber = fwnode_property_present(port_fwnode, "sfp");
3368 break;
3369 }
3370 }
3371 fwnode_handle_put(ports_fwnode);
3372 } else {
3373 dev_dbg(chip->dev, "no ethernet ports node defined for the device\n");
3374 }
3375
3376 if (chip->info->ops->port_setup_leds) {
3377 err = chip->info->ops->port_setup_leds(chip, port);
3378 if (err && err != -EOPNOTSUPP)
3379 return err;
3380 }
3381
3382 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
3383 SPEED_UNFORCED, DUPLEX_UNFORCED,
3384 PAUSE_ON, PHY_INTERFACE_MODE_NA);
3385 if (err)
3386 return err;
3387
3388 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
3389 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
3390 * tunneling, determine priority by looking at 802.1p and IP
3391 * priority fields (IP prio has precedence), and set STP state
3392 * to Forwarding.
3393 *
3394 * If this is the CPU link, use DSA or EDSA tagging depending
3395 * on which tagging mode was configured.
3396 *
3397 * If this is a link to another switch, use DSA tagging mode.
3398 *
3399 * If this is the upstream port for this switch, enable
3400 * forwarding of unknown unicasts and multicasts.
3401 */
3402 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
3403 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
3404 /* Forward any IPv4 IGMP or IPv6 MLD frames received
3405 * by a USER port to the CPU port to allow snooping.
3406 */
3407 if (dsa_is_user_port(ds, port))
3408 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP;
3409
3410 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
3411 if (err)
3412 return err;
3413
3414 err = mv88e6xxx_setup_port_mode(chip, port);
3415 if (err)
3416 return err;
3417
3418 err = mv88e6xxx_setup_egress_floods(chip, port);
3419 if (err)
3420 return err;
3421
3422 /* Port Control 2: don't force a good FCS, set the MTU size to
3423 * 10222 bytes, disable 802.1q tags checking, don't discard
3424 * tagged or untagged frames on this port, skip destination
3425 * address lookup on user ports, disable ARP mirroring and don't
3426 * send a copy of all transmitted/received frames on this port
3427 * to the CPU.
3428 */
3429 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port));
3430 if (err)
3431 return err;
3432
3433 err = mv88e6xxx_setup_upstream_port(chip, port);
3434 if (err)
3435 return err;
3436
3437 /* On chips that support it, set all downstream DSA ports'
3438 * VLAN policy to TRAP. In combination with loading
3439 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this
3440 * provides a better isolation barrier between standalone
3441 * ports, as the ATU is bypassed on any intermediate switches
3442 * between the incoming port and the CPU.
3443 */
3444 if (dsa_is_downstream_port(ds, port) &&
3445 chip->info->ops->port_set_policy) {
3446 err = chip->info->ops->port_set_policy(chip, port,
3447 MV88E6XXX_POLICY_MAPPING_VTU,
3448 MV88E6XXX_POLICY_ACTION_TRAP);
3449 if (err)
3450 return err;
3451 }
3452
3453 /* User ports start out in standalone mode and 802.1Q is
3454 * therefore disabled. On DSA ports, all valid VIDs are always
3455 * loaded in the VTU - therefore, enable 802.1Q in order to take
3456 * advantage of VLAN policy on chips that supports it.
3457 */
3458 err = mv88e6xxx_port_set_8021q_mode(chip, port,
3459 dsa_is_user_port(ds, port) ?
3460 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED :
3461 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE);
3462 if (err)
3463 return err;
3464
3465 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by
3466 * virtue of the fact that mv88e6xxx_atu_new() will pick it as
3467 * the first free FID. This will be used as the private PVID for
3468 * unbridged ports. Shared (DSA and CPU) ports must also be
3469 * members of this VID, in order to trap all frames assigned to
3470 * it to the CPU.
3471 */
3472 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE,
3473 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3474 false);
3475 if (err)
3476 return err;
3477
3478 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the
3479 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as
3480 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used
3481 * as the private PVID on ports under a VLAN-unaware bridge.
3482 * Shared (DSA and CPU) ports must also be members of it, to translate
3483 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of
3484 * relying on their port default FID.
3485 */
3486 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
3487 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3488 false);
3489 if (err)
3490 return err;
3491
3492 if (chip->info->ops->port_set_jumbo_size) {
3493 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
3494 if (err)
3495 return err;
3496 }
3497
3498 /* Port Association Vector: disable automatic address learning
3499 * on all user ports since they start out in standalone
3500 * mode. When joining a bridge, learning will be configured to
3501 * match the bridge port settings. Enable learning on all
3502 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
3503 * learning process.
3504 *
3505 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
3506 * and RefreshLocked. I.e. setup standard automatic learning.
3507 */
3508 if (dsa_is_user_port(ds, port))
3509 reg = 0;
3510 else
3511 reg = 1 << port;
3512
3513 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
3514 reg);
3515 if (err)
3516 return err;
3517
3518 /* Egress rate control 2: disable egress rate control. */
3519 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
3520 0x0000);
3521 if (err)
3522 return err;
3523
3524 if (chip->info->ops->port_pause_limit) {
3525 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
3526 if (err)
3527 return err;
3528 }
3529
3530 if (chip->info->ops->port_disable_learn_limit) {
3531 err = chip->info->ops->port_disable_learn_limit(chip, port);
3532 if (err)
3533 return err;
3534 }
3535
3536 if (chip->info->ops->port_disable_pri_override) {
3537 err = chip->info->ops->port_disable_pri_override(chip, port);
3538 if (err)
3539 return err;
3540 }
3541
3542 if (chip->info->ops->port_tag_remap) {
3543 err = chip->info->ops->port_tag_remap(chip, port);
3544 if (err)
3545 return err;
3546 }
3547
3548 if (chip->info->ops->port_egress_rate_limiting) {
3549 err = chip->info->ops->port_egress_rate_limiting(chip, port);
3550 if (err)
3551 return err;
3552 }
3553
3554 if (chip->info->ops->port_setup_message_port) {
3555 err = chip->info->ops->port_setup_message_port(chip, port);
3556 if (err)
3557 return err;
3558 }
3559
3560 if (chip->info->ops->serdes_set_tx_amplitude) {
3561 dp = dsa_to_port(ds, port);
3562 if (dp)
3563 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0);
3564
3565 if (phy_handle && !of_property_read_u32(phy_handle,
3566 "tx-p2p-microvolt",
3567 &tx_amp))
3568 err = chip->info->ops->serdes_set_tx_amplitude(chip,
3569 port, tx_amp);
3570 if (phy_handle) {
3571 of_node_put(phy_handle);
3572 if (err)
3573 return err;
3574 }
3575 }
3576
3577 /* Port based VLAN map: give each port the same default address
3578 * database, and allow bidirectional communication between the
3579 * CPU and DSA port(s), and the other ports.
3580 */
3581 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
3582 if (err)
3583 return err;
3584
3585 err = mv88e6xxx_port_vlan_map(chip, port);
3586 if (err)
3587 return err;
3588
3589 /* Default VLAN ID and priority: don't set a default VLAN
3590 * ID, and set the default packet priority to zero.
3591 */
3592 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
3593}
3594
3595static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
3596{
3597 struct mv88e6xxx_chip *chip = ds->priv;
3598
3599 if (chip->info->ops->port_set_jumbo_size)
3600 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3601 else if (chip->info->ops->set_max_frame_size)
3602 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3603 return ETH_DATA_LEN;
3604}
3605
3606static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
3607{
3608 struct mv88e6xxx_chip *chip = ds->priv;
3609 int ret = 0;
3610
3611 /* For families where we don't know how to alter the MTU,
3612 * just accept any value up to ETH_DATA_LEN
3613 */
3614 if (!chip->info->ops->port_set_jumbo_size &&
3615 !chip->info->ops->set_max_frame_size) {
3616 if (new_mtu > ETH_DATA_LEN)
3617 return -EINVAL;
3618
3619 return 0;
3620 }
3621
3622 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
3623 new_mtu += EDSA_HLEN;
3624
3625 mv88e6xxx_reg_lock(chip);
3626 if (chip->info->ops->port_set_jumbo_size)
3627 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
3628 else if (chip->info->ops->set_max_frame_size &&
3629 dsa_is_cpu_port(ds, port))
3630 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
3631 mv88e6xxx_reg_unlock(chip);
3632
3633 return ret;
3634}
3635
3636static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
3637 unsigned int ageing_time)
3638{
3639 struct mv88e6xxx_chip *chip = ds->priv;
3640 int err;
3641
3642 mv88e6xxx_reg_lock(chip);
3643 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
3644 mv88e6xxx_reg_unlock(chip);
3645
3646 return err;
3647}
3648
3649static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
3650{
3651 int err;
3652
3653 /* Initialize the statistics unit */
3654 if (chip->info->ops->stats_set_histogram) {
3655 err = chip->info->ops->stats_set_histogram(chip);
3656 if (err)
3657 return err;
3658 }
3659
3660 return mv88e6xxx_g1_stats_clear(chip);
3661}
3662
3663/* Check if the errata has already been applied. */
3664static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3665{
3666 int port;
3667 int err;
3668 u16 val;
3669
3670 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3671 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
3672 if (err) {
3673 dev_err(chip->dev,
3674 "Error reading hidden register: %d\n", err);
3675 return false;
3676 }
3677 if (val != 0x01c0)
3678 return false;
3679 }
3680
3681 return true;
3682}
3683
3684/* The 6390 copper ports have an errata which require poking magic
3685 * values into undocumented hidden registers and then performing a
3686 * software reset.
3687 */
3688static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3689{
3690 int port;
3691 int err;
3692
3693 if (mv88e6390_setup_errata_applied(chip))
3694 return 0;
3695
3696 /* Set the ports into blocking mode */
3697 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3698 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3699 if (err)
3700 return err;
3701 }
3702
3703 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3704 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3705 if (err)
3706 return err;
3707 }
3708
3709 return mv88e6xxx_software_reset(chip);
3710}
3711
3712/* prod_id for switch families which do not have a PHY model number */
3713static const u16 family_prod_id_table[] = {
3714 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3715 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3716 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
3717};
3718
3719static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3720{
3721 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3722 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3723 u16 prod_id;
3724 u16 val;
3725 int err;
3726
3727 if (!chip->info->ops->phy_read)
3728 return -EOPNOTSUPP;
3729
3730 mv88e6xxx_reg_lock(chip);
3731 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3732 mv88e6xxx_reg_unlock(chip);
3733
3734 /* Some internal PHYs don't have a model number. */
3735 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3736 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3737 prod_id = family_prod_id_table[chip->info->family];
3738 if (prod_id)
3739 val |= prod_id >> 4;
3740 }
3741
3742 return err ? err : val;
3743}
3744
3745static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad,
3746 int reg)
3747{
3748 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3749 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3750 u16 val;
3751 int err;
3752
3753 if (!chip->info->ops->phy_read_c45)
3754 return -ENODEV;
3755
3756 mv88e6xxx_reg_lock(chip);
3757 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val);
3758 mv88e6xxx_reg_unlock(chip);
3759
3760 return err ? err : val;
3761}
3762
3763static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3764{
3765 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3766 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3767 int err;
3768
3769 if (!chip->info->ops->phy_write)
3770 return -EOPNOTSUPP;
3771
3772 mv88e6xxx_reg_lock(chip);
3773 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3774 mv88e6xxx_reg_unlock(chip);
3775
3776 return err;
3777}
3778
3779static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad,
3780 int reg, u16 val)
3781{
3782 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3783 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3784 int err;
3785
3786 if (!chip->info->ops->phy_write_c45)
3787 return -EOPNOTSUPP;
3788
3789 mv88e6xxx_reg_lock(chip);
3790 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val);
3791 mv88e6xxx_reg_unlock(chip);
3792
3793 return err;
3794}
3795
3796static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3797 struct device_node *np,
3798 bool external)
3799{
3800 static int index;
3801 struct mv88e6xxx_mdio_bus *mdio_bus;
3802 struct mii_bus *bus;
3803 int err;
3804
3805 if (external) {
3806 mv88e6xxx_reg_lock(chip);
3807 if (chip->info->family == MV88E6XXX_FAMILY_6393)
3808 err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true);
3809 else
3810 err = mv88e6390_g2_scratch_gpio_set_smi(chip, true);
3811 mv88e6xxx_reg_unlock(chip);
3812
3813 if (err)
3814 return err;
3815 }
3816
3817 bus = mdiobus_alloc_size(sizeof(*mdio_bus));
3818 if (!bus)
3819 return -ENOMEM;
3820
3821 mdio_bus = bus->priv;
3822 mdio_bus->bus = bus;
3823 mdio_bus->chip = chip;
3824 INIT_LIST_HEAD(&mdio_bus->list);
3825 mdio_bus->external = external;
3826
3827 if (np) {
3828 bus->name = np->full_name;
3829 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3830 } else {
3831 bus->name = "mv88e6xxx SMI";
3832 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3833 }
3834
3835 bus->read = mv88e6xxx_mdio_read;
3836 bus->write = mv88e6xxx_mdio_write;
3837 bus->read_c45 = mv88e6xxx_mdio_read_c45;
3838 bus->write_c45 = mv88e6xxx_mdio_write_c45;
3839 bus->parent = chip->dev;
3840 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr +
3841 mv88e6xxx_num_ports(chip) - 1,
3842 chip->info->phy_base_addr);
3843
3844 if (!external) {
3845 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3846 if (err)
3847 goto out;
3848 }
3849
3850 err = of_mdiobus_register(bus, np);
3851 if (err) {
3852 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3853 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3854 goto out;
3855 }
3856
3857 if (external)
3858 list_add_tail(&mdio_bus->list, &chip->mdios);
3859 else
3860 list_add(&mdio_bus->list, &chip->mdios);
3861
3862 return 0;
3863
3864out:
3865 mdiobus_free(bus);
3866 return err;
3867}
3868
3869static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3870
3871{
3872 struct mv88e6xxx_mdio_bus *mdio_bus, *p;
3873 struct mii_bus *bus;
3874
3875 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) {
3876 bus = mdio_bus->bus;
3877
3878 if (!mdio_bus->external)
3879 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3880
3881 mdiobus_unregister(bus);
3882 mdiobus_free(bus);
3883 }
3884}
3885
3886static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip)
3887{
3888 struct device_node *np = chip->dev->of_node;
3889 struct device_node *child;
3890 int err;
3891
3892 /* Always register one mdio bus for the internal/default mdio
3893 * bus. This maybe represented in the device tree, but is
3894 * optional.
3895 */
3896 child = of_get_child_by_name(np, "mdio");
3897 err = mv88e6xxx_mdio_register(chip, child, false);
3898 of_node_put(child);
3899 if (err)
3900 return err;
3901
3902 /* Walk the device tree, and see if there are any other nodes
3903 * which say they are compatible with the external mdio
3904 * bus.
3905 */
3906 for_each_available_child_of_node(np, child) {
3907 if (of_device_is_compatible(
3908 child, "marvell,mv88e6xxx-mdio-external")) {
3909 err = mv88e6xxx_mdio_register(chip, child, true);
3910 if (err) {
3911 mv88e6xxx_mdios_unregister(chip);
3912 of_node_put(child);
3913 return err;
3914 }
3915 }
3916 }
3917
3918 return 0;
3919}
3920
3921static void mv88e6xxx_teardown(struct dsa_switch *ds)
3922{
3923 struct mv88e6xxx_chip *chip = ds->priv;
3924
3925 mv88e6xxx_teardown_devlink_params(ds);
3926 dsa_devlink_resources_unregister(ds);
3927 mv88e6xxx_teardown_devlink_regions_global(ds);
3928 mv88e6xxx_mdios_unregister(chip);
3929}
3930
3931static int mv88e6xxx_setup(struct dsa_switch *ds)
3932{
3933 struct mv88e6xxx_chip *chip = ds->priv;
3934 u8 cmode;
3935 int err;
3936 int i;
3937
3938 err = mv88e6xxx_mdios_register(chip);
3939 if (err)
3940 return err;
3941
3942 chip->ds = ds;
3943 ds->user_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3944
3945 /* Since virtual bridges are mapped in the PVT, the number we support
3946 * depends on the physical switch topology. We need to let DSA figure
3947 * that out and therefore we cannot set this at dsa_register_switch()
3948 * time.
3949 */
3950 if (mv88e6xxx_has_pvt(chip))
3951 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
3952 ds->dst->last_switch - 1;
3953
3954 mv88e6xxx_reg_lock(chip);
3955
3956 if (chip->info->ops->setup_errata) {
3957 err = chip->info->ops->setup_errata(chip);
3958 if (err)
3959 goto unlock;
3960 }
3961
3962 /* Cache the cmode of each port. */
3963 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3964 if (chip->info->ops->port_get_cmode) {
3965 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3966 if (err)
3967 goto unlock;
3968
3969 chip->ports[i].cmode = cmode;
3970 }
3971 }
3972
3973 err = mv88e6xxx_vtu_setup(chip);
3974 if (err)
3975 goto unlock;
3976
3977 /* Must be called after mv88e6xxx_vtu_setup (which flushes the
3978 * VTU, thereby also flushing the STU).
3979 */
3980 err = mv88e6xxx_stu_setup(chip);
3981 if (err)
3982 goto unlock;
3983
3984 /* Setup Switch Port Registers */
3985 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3986 if (dsa_is_unused_port(ds, i))
3987 continue;
3988
3989 /* Prevent the use of an invalid port. */
3990 if (mv88e6xxx_is_invalid_port(chip, i)) {
3991 dev_err(chip->dev, "port %d is invalid\n", i);
3992 err = -EINVAL;
3993 goto unlock;
3994 }
3995
3996 err = mv88e6xxx_setup_port(chip, i);
3997 if (err)
3998 goto unlock;
3999 }
4000
4001 err = mv88e6xxx_irl_setup(chip);
4002 if (err)
4003 goto unlock;
4004
4005 err = mv88e6xxx_mac_setup(chip);
4006 if (err)
4007 goto unlock;
4008
4009 err = mv88e6xxx_phy_setup(chip);
4010 if (err)
4011 goto unlock;
4012
4013 err = mv88e6xxx_pvt_setup(chip);
4014 if (err)
4015 goto unlock;
4016
4017 err = mv88e6xxx_atu_setup(chip);
4018 if (err)
4019 goto unlock;
4020
4021 err = mv88e6xxx_broadcast_setup(chip, 0);
4022 if (err)
4023 goto unlock;
4024
4025 err = mv88e6xxx_pot_setup(chip);
4026 if (err)
4027 goto unlock;
4028
4029 err = mv88e6xxx_rmu_setup(chip);
4030 if (err)
4031 goto unlock;
4032
4033 err = mv88e6xxx_rsvd2cpu_setup(chip);
4034 if (err)
4035 goto unlock;
4036
4037 err = mv88e6xxx_trunk_setup(chip);
4038 if (err)
4039 goto unlock;
4040
4041 err = mv88e6xxx_devmap_setup(chip);
4042 if (err)
4043 goto unlock;
4044
4045 err = mv88e6xxx_pri_setup(chip);
4046 if (err)
4047 goto unlock;
4048
4049 /* Setup PTP Hardware Clock and timestamping */
4050 if (chip->info->ptp_support) {
4051 err = mv88e6xxx_ptp_setup(chip);
4052 if (err)
4053 goto unlock;
4054
4055 err = mv88e6xxx_hwtstamp_setup(chip);
4056 if (err)
4057 goto unlock;
4058 }
4059
4060 err = mv88e6xxx_stats_setup(chip);
4061 if (err)
4062 goto unlock;
4063
4064unlock:
4065 mv88e6xxx_reg_unlock(chip);
4066
4067 if (err)
4068 goto out_mdios;
4069
4070 /* Have to be called without holding the register lock, since
4071 * they take the devlink lock, and we later take the locks in
4072 * the reverse order when getting/setting parameters or
4073 * resource occupancy.
4074 */
4075 err = mv88e6xxx_setup_devlink_resources(ds);
4076 if (err)
4077 goto out_mdios;
4078
4079 err = mv88e6xxx_setup_devlink_params(ds);
4080 if (err)
4081 goto out_resources;
4082
4083 err = mv88e6xxx_setup_devlink_regions_global(ds);
4084 if (err)
4085 goto out_params;
4086
4087 return 0;
4088
4089out_params:
4090 mv88e6xxx_teardown_devlink_params(ds);
4091out_resources:
4092 dsa_devlink_resources_unregister(ds);
4093out_mdios:
4094 mv88e6xxx_mdios_unregister(chip);
4095
4096 return err;
4097}
4098
4099static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
4100{
4101 struct mv88e6xxx_chip *chip = ds->priv;
4102 int err;
4103
4104 if (chip->info->ops->pcs_ops &&
4105 chip->info->ops->pcs_ops->pcs_init) {
4106 err = chip->info->ops->pcs_ops->pcs_init(chip, port);
4107 if (err)
4108 return err;
4109 }
4110
4111 return mv88e6xxx_setup_devlink_regions_port(ds, port);
4112}
4113
4114static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
4115{
4116 struct mv88e6xxx_chip *chip = ds->priv;
4117
4118 mv88e6xxx_teardown_devlink_regions_port(ds, port);
4119
4120 if (chip->info->ops->pcs_ops &&
4121 chip->info->ops->pcs_ops->pcs_teardown)
4122 chip->info->ops->pcs_ops->pcs_teardown(chip, port);
4123}
4124
4125static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
4126{
4127 struct mv88e6xxx_chip *chip = ds->priv;
4128
4129 return chip->eeprom_len;
4130}
4131
4132static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
4133 struct ethtool_eeprom *eeprom, u8 *data)
4134{
4135 struct mv88e6xxx_chip *chip = ds->priv;
4136 int err;
4137
4138 if (!chip->info->ops->get_eeprom)
4139 return -EOPNOTSUPP;
4140
4141 mv88e6xxx_reg_lock(chip);
4142 err = chip->info->ops->get_eeprom(chip, eeprom, data);
4143 mv88e6xxx_reg_unlock(chip);
4144
4145 if (err)
4146 return err;
4147
4148 eeprom->magic = 0xc3ec4951;
4149
4150 return 0;
4151}
4152
4153static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
4154 struct ethtool_eeprom *eeprom, u8 *data)
4155{
4156 struct mv88e6xxx_chip *chip = ds->priv;
4157 int err;
4158
4159 if (!chip->info->ops->set_eeprom)
4160 return -EOPNOTSUPP;
4161
4162 if (eeprom->magic != 0xc3ec4951)
4163 return -EINVAL;
4164
4165 mv88e6xxx_reg_lock(chip);
4166 err = chip->info->ops->set_eeprom(chip, eeprom, data);
4167 mv88e6xxx_reg_unlock(chip);
4168
4169 return err;
4170}
4171
4172static const struct mv88e6xxx_ops mv88e6085_ops = {
4173 /* MV88E6XXX_FAMILY_6097 */
4174 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4175 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4176 .irl_init_all = mv88e6352_g2_irl_init_all,
4177 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4178 .phy_read = mv88e6185_phy_ppu_read,
4179 .phy_write = mv88e6185_phy_ppu_write,
4180 .port_set_link = mv88e6xxx_port_set_link,
4181 .port_sync_link = mv88e6xxx_port_sync_link,
4182 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4183 .port_tag_remap = mv88e6095_port_tag_remap,
4184 .port_set_policy = mv88e6352_port_set_policy,
4185 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4186 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4187 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4188 .port_set_ether_type = mv88e6351_port_set_ether_type,
4189 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4190 .port_pause_limit = mv88e6097_port_pause_limit,
4191 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4192 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4193 .port_get_cmode = mv88e6185_port_get_cmode,
4194 .port_setup_message_port = mv88e6xxx_setup_message_port,
4195 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4196 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4197 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4198 .stats_get_strings = mv88e6095_stats_get_strings,
4199 .stats_get_stat = mv88e6095_stats_get_stat,
4200 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4201 .set_egress_port = mv88e6095_g1_set_egress_port,
4202 .watchdog_ops = &mv88e6097_watchdog_ops,
4203 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4204 .pot_clear = mv88e6xxx_g2_pot_clear,
4205 .ppu_enable = mv88e6185_g1_ppu_enable,
4206 .ppu_disable = mv88e6185_g1_ppu_disable,
4207 .reset = mv88e6185_g1_reset,
4208 .rmu_disable = mv88e6085_g1_rmu_disable,
4209 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4210 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4211 .stu_getnext = mv88e6352_g1_stu_getnext,
4212 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4213 .phylink_get_caps = mv88e6185_phylink_get_caps,
4214 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4215};
4216
4217static const struct mv88e6xxx_ops mv88e6095_ops = {
4218 /* MV88E6XXX_FAMILY_6095 */
4219 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4220 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4221 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4222 .phy_read = mv88e6185_phy_ppu_read,
4223 .phy_write = mv88e6185_phy_ppu_write,
4224 .port_set_link = mv88e6xxx_port_set_link,
4225 .port_sync_link = mv88e6185_port_sync_link,
4226 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4227 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4228 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4229 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4230 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4231 .port_get_cmode = mv88e6185_port_get_cmode,
4232 .port_setup_message_port = mv88e6xxx_setup_message_port,
4233 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4234 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4235 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4236 .stats_get_strings = mv88e6095_stats_get_strings,
4237 .stats_get_stat = mv88e6095_stats_get_stat,
4238 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4239 .ppu_enable = mv88e6185_g1_ppu_enable,
4240 .ppu_disable = mv88e6185_g1_ppu_disable,
4241 .reset = mv88e6185_g1_reset,
4242 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4243 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4244 .phylink_get_caps = mv88e6095_phylink_get_caps,
4245 .pcs_ops = &mv88e6185_pcs_ops,
4246 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4247};
4248
4249static const struct mv88e6xxx_ops mv88e6097_ops = {
4250 /* MV88E6XXX_FAMILY_6097 */
4251 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4252 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4253 .irl_init_all = mv88e6352_g2_irl_init_all,
4254 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4255 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4256 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4257 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4258 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4259 .port_set_link = mv88e6xxx_port_set_link,
4260 .port_sync_link = mv88e6185_port_sync_link,
4261 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4262 .port_tag_remap = mv88e6095_port_tag_remap,
4263 .port_set_policy = mv88e6352_port_set_policy,
4264 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4265 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4266 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4267 .port_set_ether_type = mv88e6351_port_set_ether_type,
4268 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4269 .port_pause_limit = mv88e6097_port_pause_limit,
4270 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4271 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4272 .port_get_cmode = mv88e6185_port_get_cmode,
4273 .port_setup_message_port = mv88e6xxx_setup_message_port,
4274 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4275 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4276 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4277 .stats_get_strings = mv88e6095_stats_get_strings,
4278 .stats_get_stat = mv88e6095_stats_get_stat,
4279 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4280 .set_egress_port = mv88e6095_g1_set_egress_port,
4281 .watchdog_ops = &mv88e6097_watchdog_ops,
4282 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4283 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4284 .pot_clear = mv88e6xxx_g2_pot_clear,
4285 .reset = mv88e6352_g1_reset,
4286 .rmu_disable = mv88e6085_g1_rmu_disable,
4287 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4288 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4289 .phylink_get_caps = mv88e6095_phylink_get_caps,
4290 .pcs_ops = &mv88e6185_pcs_ops,
4291 .stu_getnext = mv88e6352_g1_stu_getnext,
4292 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4293 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4294};
4295
4296static const struct mv88e6xxx_ops mv88e6123_ops = {
4297 /* MV88E6XXX_FAMILY_6165 */
4298 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4299 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4300 .irl_init_all = mv88e6352_g2_irl_init_all,
4301 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4302 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4303 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4304 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4305 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4306 .port_set_link = mv88e6xxx_port_set_link,
4307 .port_sync_link = mv88e6xxx_port_sync_link,
4308 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4309 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4310 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4311 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4312 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4313 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4314 .port_get_cmode = mv88e6185_port_get_cmode,
4315 .port_setup_message_port = mv88e6xxx_setup_message_port,
4316 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4317 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4318 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4319 .stats_get_strings = mv88e6095_stats_get_strings,
4320 .stats_get_stat = mv88e6095_stats_get_stat,
4321 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4322 .set_egress_port = mv88e6095_g1_set_egress_port,
4323 .watchdog_ops = &mv88e6097_watchdog_ops,
4324 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4325 .pot_clear = mv88e6xxx_g2_pot_clear,
4326 .reset = mv88e6352_g1_reset,
4327 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4328 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4329 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4330 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4331 .stu_getnext = mv88e6352_g1_stu_getnext,
4332 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4333 .phylink_get_caps = mv88e6185_phylink_get_caps,
4334 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4335};
4336
4337static const struct mv88e6xxx_ops mv88e6131_ops = {
4338 /* MV88E6XXX_FAMILY_6185 */
4339 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4340 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4341 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4342 .phy_read = mv88e6185_phy_ppu_read,
4343 .phy_write = mv88e6185_phy_ppu_write,
4344 .port_set_link = mv88e6xxx_port_set_link,
4345 .port_sync_link = mv88e6xxx_port_sync_link,
4346 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4347 .port_tag_remap = mv88e6095_port_tag_remap,
4348 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4349 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4350 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4351 .port_set_ether_type = mv88e6351_port_set_ether_type,
4352 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4353 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4354 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4355 .port_pause_limit = mv88e6097_port_pause_limit,
4356 .port_set_pause = mv88e6185_port_set_pause,
4357 .port_get_cmode = mv88e6185_port_get_cmode,
4358 .port_setup_message_port = mv88e6xxx_setup_message_port,
4359 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4360 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4361 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4362 .stats_get_strings = mv88e6095_stats_get_strings,
4363 .stats_get_stat = mv88e6095_stats_get_stat,
4364 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4365 .set_egress_port = mv88e6095_g1_set_egress_port,
4366 .watchdog_ops = &mv88e6097_watchdog_ops,
4367 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4368 .ppu_enable = mv88e6185_g1_ppu_enable,
4369 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4370 .ppu_disable = mv88e6185_g1_ppu_disable,
4371 .reset = mv88e6185_g1_reset,
4372 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4373 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4374 .phylink_get_caps = mv88e6185_phylink_get_caps,
4375};
4376
4377static const struct mv88e6xxx_ops mv88e6141_ops = {
4378 /* MV88E6XXX_FAMILY_6341 */
4379 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4380 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4381 .irl_init_all = mv88e6352_g2_irl_init_all,
4382 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4383 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4384 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4385 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4386 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4387 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4388 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4389 .port_set_link = mv88e6xxx_port_set_link,
4390 .port_sync_link = mv88e6xxx_port_sync_link,
4391 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4392 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4393 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4394 .port_tag_remap = mv88e6095_port_tag_remap,
4395 .port_set_policy = mv88e6352_port_set_policy,
4396 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4397 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4398 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4399 .port_set_ether_type = mv88e6351_port_set_ether_type,
4400 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4401 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4402 .port_pause_limit = mv88e6097_port_pause_limit,
4403 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4404 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4405 .port_get_cmode = mv88e6352_port_get_cmode,
4406 .port_set_cmode = mv88e6341_port_set_cmode,
4407 .port_setup_message_port = mv88e6xxx_setup_message_port,
4408 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4409 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4410 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4411 .stats_get_strings = mv88e6320_stats_get_strings,
4412 .stats_get_stat = mv88e6390_stats_get_stat,
4413 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4414 .set_egress_port = mv88e6390_g1_set_egress_port,
4415 .watchdog_ops = &mv88e6390_watchdog_ops,
4416 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4417 .pot_clear = mv88e6xxx_g2_pot_clear,
4418 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4419 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4420 .reset = mv88e6352_g1_reset,
4421 .rmu_disable = mv88e6390_g1_rmu_disable,
4422 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4423 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4424 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4425 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4426 .stu_getnext = mv88e6352_g1_stu_getnext,
4427 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4428 .serdes_get_lane = mv88e6341_serdes_get_lane,
4429 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4430 .gpio_ops = &mv88e6352_gpio_ops,
4431 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4432 .serdes_get_strings = mv88e6390_serdes_get_strings,
4433 .serdes_get_stats = mv88e6390_serdes_get_stats,
4434 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4435 .serdes_get_regs = mv88e6390_serdes_get_regs,
4436 .phylink_get_caps = mv88e6341_phylink_get_caps,
4437 .pcs_ops = &mv88e6390_pcs_ops,
4438};
4439
4440static const struct mv88e6xxx_ops mv88e6161_ops = {
4441 /* MV88E6XXX_FAMILY_6165 */
4442 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4443 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4444 .irl_init_all = mv88e6352_g2_irl_init_all,
4445 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4446 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4447 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4448 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4449 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4450 .port_set_link = mv88e6xxx_port_set_link,
4451 .port_sync_link = mv88e6xxx_port_sync_link,
4452 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4453 .port_tag_remap = mv88e6095_port_tag_remap,
4454 .port_set_policy = mv88e6352_port_set_policy,
4455 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4456 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4457 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4458 .port_set_ether_type = mv88e6351_port_set_ether_type,
4459 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4460 .port_pause_limit = mv88e6097_port_pause_limit,
4461 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4462 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4463 .port_get_cmode = mv88e6185_port_get_cmode,
4464 .port_setup_message_port = mv88e6xxx_setup_message_port,
4465 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4466 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4467 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4468 .stats_get_strings = mv88e6095_stats_get_strings,
4469 .stats_get_stat = mv88e6095_stats_get_stat,
4470 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4471 .set_egress_port = mv88e6095_g1_set_egress_port,
4472 .watchdog_ops = &mv88e6097_watchdog_ops,
4473 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4474 .pot_clear = mv88e6xxx_g2_pot_clear,
4475 .reset = mv88e6352_g1_reset,
4476 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4477 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4478 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4479 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4480 .stu_getnext = mv88e6352_g1_stu_getnext,
4481 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4482 .avb_ops = &mv88e6165_avb_ops,
4483 .ptp_ops = &mv88e6165_ptp_ops,
4484 .phylink_get_caps = mv88e6185_phylink_get_caps,
4485 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4486};
4487
4488static const struct mv88e6xxx_ops mv88e6165_ops = {
4489 /* MV88E6XXX_FAMILY_6165 */
4490 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4491 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4492 .irl_init_all = mv88e6352_g2_irl_init_all,
4493 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4494 .phy_read = mv88e6165_phy_read,
4495 .phy_write = mv88e6165_phy_write,
4496 .port_set_link = mv88e6xxx_port_set_link,
4497 .port_sync_link = mv88e6xxx_port_sync_link,
4498 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4499 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4500 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4501 .port_get_cmode = mv88e6185_port_get_cmode,
4502 .port_setup_message_port = mv88e6xxx_setup_message_port,
4503 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4504 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4505 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4506 .stats_get_strings = mv88e6095_stats_get_strings,
4507 .stats_get_stat = mv88e6095_stats_get_stat,
4508 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4509 .set_egress_port = mv88e6095_g1_set_egress_port,
4510 .watchdog_ops = &mv88e6097_watchdog_ops,
4511 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4512 .pot_clear = mv88e6xxx_g2_pot_clear,
4513 .reset = mv88e6352_g1_reset,
4514 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4515 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4516 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4517 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4518 .stu_getnext = mv88e6352_g1_stu_getnext,
4519 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4520 .avb_ops = &mv88e6165_avb_ops,
4521 .ptp_ops = &mv88e6165_ptp_ops,
4522 .phylink_get_caps = mv88e6185_phylink_get_caps,
4523};
4524
4525static const struct mv88e6xxx_ops mv88e6171_ops = {
4526 /* MV88E6XXX_FAMILY_6351 */
4527 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4528 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4529 .irl_init_all = mv88e6352_g2_irl_init_all,
4530 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4531 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4532 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4533 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4534 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4535 .port_set_link = mv88e6xxx_port_set_link,
4536 .port_sync_link = mv88e6xxx_port_sync_link,
4537 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4538 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4539 .port_tag_remap = mv88e6095_port_tag_remap,
4540 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4541 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4542 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4543 .port_set_ether_type = mv88e6351_port_set_ether_type,
4544 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4545 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4546 .port_pause_limit = mv88e6097_port_pause_limit,
4547 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4548 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4549 .port_get_cmode = mv88e6352_port_get_cmode,
4550 .port_setup_message_port = mv88e6xxx_setup_message_port,
4551 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4552 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4553 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4554 .stats_get_strings = mv88e6095_stats_get_strings,
4555 .stats_get_stat = mv88e6095_stats_get_stat,
4556 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4557 .set_egress_port = mv88e6095_g1_set_egress_port,
4558 .watchdog_ops = &mv88e6097_watchdog_ops,
4559 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4560 .pot_clear = mv88e6xxx_g2_pot_clear,
4561 .reset = mv88e6352_g1_reset,
4562 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4563 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4564 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4565 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4566 .stu_getnext = mv88e6352_g1_stu_getnext,
4567 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4568 .phylink_get_caps = mv88e6351_phylink_get_caps,
4569};
4570
4571static const struct mv88e6xxx_ops mv88e6172_ops = {
4572 /* MV88E6XXX_FAMILY_6352 */
4573 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4574 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4575 .irl_init_all = mv88e6352_g2_irl_init_all,
4576 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4577 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4578 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4579 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4580 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4581 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4582 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4583 .port_set_link = mv88e6xxx_port_set_link,
4584 .port_sync_link = mv88e6xxx_port_sync_link,
4585 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4586 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4587 .port_tag_remap = mv88e6095_port_tag_remap,
4588 .port_set_policy = mv88e6352_port_set_policy,
4589 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4590 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4591 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4592 .port_set_ether_type = mv88e6351_port_set_ether_type,
4593 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4594 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4595 .port_pause_limit = mv88e6097_port_pause_limit,
4596 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4597 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4598 .port_get_cmode = mv88e6352_port_get_cmode,
4599 .port_setup_leds = mv88e6xxx_port_setup_leds,
4600 .port_setup_message_port = mv88e6xxx_setup_message_port,
4601 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4602 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4603 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4604 .stats_get_strings = mv88e6095_stats_get_strings,
4605 .stats_get_stat = mv88e6095_stats_get_stat,
4606 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4607 .set_egress_port = mv88e6095_g1_set_egress_port,
4608 .watchdog_ops = &mv88e6097_watchdog_ops,
4609 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4610 .pot_clear = mv88e6xxx_g2_pot_clear,
4611 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4612 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4613 .reset = mv88e6352_g1_reset,
4614 .rmu_disable = mv88e6352_g1_rmu_disable,
4615 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4616 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4617 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4618 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4619 .stu_getnext = mv88e6352_g1_stu_getnext,
4620 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4621 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4622 .serdes_get_regs = mv88e6352_serdes_get_regs,
4623 .gpio_ops = &mv88e6352_gpio_ops,
4624 .phylink_get_caps = mv88e6352_phylink_get_caps,
4625 .pcs_ops = &mv88e6352_pcs_ops,
4626};
4627
4628static const struct mv88e6xxx_ops mv88e6175_ops = {
4629 /* MV88E6XXX_FAMILY_6351 */
4630 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4631 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4632 .irl_init_all = mv88e6352_g2_irl_init_all,
4633 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4634 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4635 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4636 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4637 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4638 .port_set_link = mv88e6xxx_port_set_link,
4639 .port_sync_link = mv88e6xxx_port_sync_link,
4640 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4641 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4642 .port_tag_remap = mv88e6095_port_tag_remap,
4643 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4644 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4645 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4646 .port_set_ether_type = mv88e6351_port_set_ether_type,
4647 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4648 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4649 .port_pause_limit = mv88e6097_port_pause_limit,
4650 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4651 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4652 .port_get_cmode = mv88e6352_port_get_cmode,
4653 .port_setup_message_port = mv88e6xxx_setup_message_port,
4654 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4655 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4656 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4657 .stats_get_strings = mv88e6095_stats_get_strings,
4658 .stats_get_stat = mv88e6095_stats_get_stat,
4659 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4660 .set_egress_port = mv88e6095_g1_set_egress_port,
4661 .watchdog_ops = &mv88e6097_watchdog_ops,
4662 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4663 .pot_clear = mv88e6xxx_g2_pot_clear,
4664 .reset = mv88e6352_g1_reset,
4665 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4666 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4667 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4668 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4669 .stu_getnext = mv88e6352_g1_stu_getnext,
4670 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4671 .phylink_get_caps = mv88e6351_phylink_get_caps,
4672};
4673
4674static const struct mv88e6xxx_ops mv88e6176_ops = {
4675 /* MV88E6XXX_FAMILY_6352 */
4676 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4677 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4678 .irl_init_all = mv88e6352_g2_irl_init_all,
4679 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4680 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4681 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4682 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4683 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4684 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4685 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4686 .port_set_link = mv88e6xxx_port_set_link,
4687 .port_sync_link = mv88e6xxx_port_sync_link,
4688 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4689 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4690 .port_tag_remap = mv88e6095_port_tag_remap,
4691 .port_set_policy = mv88e6352_port_set_policy,
4692 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4693 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4694 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4695 .port_set_ether_type = mv88e6351_port_set_ether_type,
4696 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4697 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4698 .port_pause_limit = mv88e6097_port_pause_limit,
4699 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4700 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4701 .port_get_cmode = mv88e6352_port_get_cmode,
4702 .port_setup_leds = mv88e6xxx_port_setup_leds,
4703 .port_setup_message_port = mv88e6xxx_setup_message_port,
4704 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4705 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4706 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4707 .stats_get_strings = mv88e6095_stats_get_strings,
4708 .stats_get_stat = mv88e6095_stats_get_stat,
4709 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4710 .set_egress_port = mv88e6095_g1_set_egress_port,
4711 .watchdog_ops = &mv88e6097_watchdog_ops,
4712 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4713 .pot_clear = mv88e6xxx_g2_pot_clear,
4714 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4715 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4716 .reset = mv88e6352_g1_reset,
4717 .rmu_disable = mv88e6352_g1_rmu_disable,
4718 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4719 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4720 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4721 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4722 .stu_getnext = mv88e6352_g1_stu_getnext,
4723 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4724 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4725 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4726 .serdes_get_regs = mv88e6352_serdes_get_regs,
4727 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4728 .gpio_ops = &mv88e6352_gpio_ops,
4729 .phylink_get_caps = mv88e6352_phylink_get_caps,
4730 .pcs_ops = &mv88e6352_pcs_ops,
4731};
4732
4733static const struct mv88e6xxx_ops mv88e6185_ops = {
4734 /* MV88E6XXX_FAMILY_6185 */
4735 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4736 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4737 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4738 .phy_read = mv88e6185_phy_ppu_read,
4739 .phy_write = mv88e6185_phy_ppu_write,
4740 .port_set_link = mv88e6xxx_port_set_link,
4741 .port_sync_link = mv88e6185_port_sync_link,
4742 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4743 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4744 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4745 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4746 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4747 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4748 .port_set_pause = mv88e6185_port_set_pause,
4749 .port_get_cmode = mv88e6185_port_get_cmode,
4750 .port_setup_message_port = mv88e6xxx_setup_message_port,
4751 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4752 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4753 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4754 .stats_get_strings = mv88e6095_stats_get_strings,
4755 .stats_get_stat = mv88e6095_stats_get_stat,
4756 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4757 .set_egress_port = mv88e6095_g1_set_egress_port,
4758 .watchdog_ops = &mv88e6097_watchdog_ops,
4759 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4760 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4761 .ppu_enable = mv88e6185_g1_ppu_enable,
4762 .ppu_disable = mv88e6185_g1_ppu_disable,
4763 .reset = mv88e6185_g1_reset,
4764 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4765 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4766 .phylink_get_caps = mv88e6185_phylink_get_caps,
4767 .pcs_ops = &mv88e6185_pcs_ops,
4768 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4769};
4770
4771static const struct mv88e6xxx_ops mv88e6190_ops = {
4772 /* MV88E6XXX_FAMILY_6390 */
4773 .setup_errata = mv88e6390_setup_errata,
4774 .irl_init_all = mv88e6390_g2_irl_init_all,
4775 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4776 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4777 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4778 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4779 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4780 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4781 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4782 .port_set_link = mv88e6xxx_port_set_link,
4783 .port_sync_link = mv88e6xxx_port_sync_link,
4784 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4785 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4786 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4787 .port_tag_remap = mv88e6390_port_tag_remap,
4788 .port_set_policy = mv88e6352_port_set_policy,
4789 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4790 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4791 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4792 .port_set_ether_type = mv88e6351_port_set_ether_type,
4793 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4794 .port_pause_limit = mv88e6390_port_pause_limit,
4795 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4796 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4797 .port_get_cmode = mv88e6352_port_get_cmode,
4798 .port_set_cmode = mv88e6390_port_set_cmode,
4799 .port_setup_message_port = mv88e6xxx_setup_message_port,
4800 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4801 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4802 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4803 .stats_get_strings = mv88e6320_stats_get_strings,
4804 .stats_get_stat = mv88e6390_stats_get_stat,
4805 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4806 .set_egress_port = mv88e6390_g1_set_egress_port,
4807 .watchdog_ops = &mv88e6390_watchdog_ops,
4808 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4809 .pot_clear = mv88e6xxx_g2_pot_clear,
4810 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4811 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4812 .reset = mv88e6352_g1_reset,
4813 .rmu_disable = mv88e6390_g1_rmu_disable,
4814 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4815 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4816 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4817 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4818 .stu_getnext = mv88e6390_g1_stu_getnext,
4819 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4820 .serdes_get_lane = mv88e6390_serdes_get_lane,
4821 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4822 .serdes_get_strings = mv88e6390_serdes_get_strings,
4823 .serdes_get_stats = mv88e6390_serdes_get_stats,
4824 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4825 .serdes_get_regs = mv88e6390_serdes_get_regs,
4826 .gpio_ops = &mv88e6352_gpio_ops,
4827 .phylink_get_caps = mv88e6390_phylink_get_caps,
4828 .pcs_ops = &mv88e6390_pcs_ops,
4829};
4830
4831static const struct mv88e6xxx_ops mv88e6190x_ops = {
4832 /* MV88E6XXX_FAMILY_6390 */
4833 .setup_errata = mv88e6390_setup_errata,
4834 .irl_init_all = mv88e6390_g2_irl_init_all,
4835 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4836 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4837 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4838 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4839 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4840 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4841 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4842 .port_set_link = mv88e6xxx_port_set_link,
4843 .port_sync_link = mv88e6xxx_port_sync_link,
4844 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4845 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4846 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4847 .port_tag_remap = mv88e6390_port_tag_remap,
4848 .port_set_policy = mv88e6352_port_set_policy,
4849 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4850 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4851 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4852 .port_set_ether_type = mv88e6351_port_set_ether_type,
4853 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4854 .port_pause_limit = mv88e6390_port_pause_limit,
4855 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4856 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4857 .port_get_cmode = mv88e6352_port_get_cmode,
4858 .port_set_cmode = mv88e6390x_port_set_cmode,
4859 .port_setup_message_port = mv88e6xxx_setup_message_port,
4860 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4861 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4862 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4863 .stats_get_strings = mv88e6320_stats_get_strings,
4864 .stats_get_stat = mv88e6390_stats_get_stat,
4865 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4866 .set_egress_port = mv88e6390_g1_set_egress_port,
4867 .watchdog_ops = &mv88e6390_watchdog_ops,
4868 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4869 .pot_clear = mv88e6xxx_g2_pot_clear,
4870 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4871 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4872 .reset = mv88e6352_g1_reset,
4873 .rmu_disable = mv88e6390_g1_rmu_disable,
4874 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4875 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4876 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4877 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4878 .stu_getnext = mv88e6390_g1_stu_getnext,
4879 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4880 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4881 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4882 .serdes_get_strings = mv88e6390_serdes_get_strings,
4883 .serdes_get_stats = mv88e6390_serdes_get_stats,
4884 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4885 .serdes_get_regs = mv88e6390_serdes_get_regs,
4886 .gpio_ops = &mv88e6352_gpio_ops,
4887 .phylink_get_caps = mv88e6390x_phylink_get_caps,
4888 .pcs_ops = &mv88e6390_pcs_ops,
4889};
4890
4891static const struct mv88e6xxx_ops mv88e6191_ops = {
4892 /* MV88E6XXX_FAMILY_6390 */
4893 .setup_errata = mv88e6390_setup_errata,
4894 .irl_init_all = mv88e6390_g2_irl_init_all,
4895 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4896 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4897 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4898 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4899 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4900 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4901 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4902 .port_set_link = mv88e6xxx_port_set_link,
4903 .port_sync_link = mv88e6xxx_port_sync_link,
4904 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4905 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4906 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4907 .port_tag_remap = mv88e6390_port_tag_remap,
4908 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4909 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4910 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4911 .port_set_ether_type = mv88e6351_port_set_ether_type,
4912 .port_pause_limit = mv88e6390_port_pause_limit,
4913 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4914 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4915 .port_get_cmode = mv88e6352_port_get_cmode,
4916 .port_set_cmode = mv88e6390_port_set_cmode,
4917 .port_setup_message_port = mv88e6xxx_setup_message_port,
4918 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4919 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4920 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4921 .stats_get_strings = mv88e6320_stats_get_strings,
4922 .stats_get_stat = mv88e6390_stats_get_stat,
4923 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4924 .set_egress_port = mv88e6390_g1_set_egress_port,
4925 .watchdog_ops = &mv88e6390_watchdog_ops,
4926 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4927 .pot_clear = mv88e6xxx_g2_pot_clear,
4928 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4929 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4930 .reset = mv88e6352_g1_reset,
4931 .rmu_disable = mv88e6390_g1_rmu_disable,
4932 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4933 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4934 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4935 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4936 .stu_getnext = mv88e6390_g1_stu_getnext,
4937 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4938 .serdes_get_lane = mv88e6390_serdes_get_lane,
4939 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4940 .serdes_get_strings = mv88e6390_serdes_get_strings,
4941 .serdes_get_stats = mv88e6390_serdes_get_stats,
4942 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4943 .serdes_get_regs = mv88e6390_serdes_get_regs,
4944 .avb_ops = &mv88e6390_avb_ops,
4945 .ptp_ops = &mv88e6352_ptp_ops,
4946 .phylink_get_caps = mv88e6390_phylink_get_caps,
4947 .pcs_ops = &mv88e6390_pcs_ops,
4948};
4949
4950static const struct mv88e6xxx_ops mv88e6240_ops = {
4951 /* MV88E6XXX_FAMILY_6352 */
4952 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4953 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4954 .irl_init_all = mv88e6352_g2_irl_init_all,
4955 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4956 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4957 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4958 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4959 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4960 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4961 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4962 .port_set_link = mv88e6xxx_port_set_link,
4963 .port_sync_link = mv88e6xxx_port_sync_link,
4964 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4965 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4966 .port_tag_remap = mv88e6095_port_tag_remap,
4967 .port_set_policy = mv88e6352_port_set_policy,
4968 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4969 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4970 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4971 .port_set_ether_type = mv88e6351_port_set_ether_type,
4972 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4973 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4974 .port_pause_limit = mv88e6097_port_pause_limit,
4975 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4976 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4977 .port_get_cmode = mv88e6352_port_get_cmode,
4978 .port_setup_leds = mv88e6xxx_port_setup_leds,
4979 .port_setup_message_port = mv88e6xxx_setup_message_port,
4980 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4981 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4982 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4983 .stats_get_strings = mv88e6095_stats_get_strings,
4984 .stats_get_stat = mv88e6095_stats_get_stat,
4985 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4986 .set_egress_port = mv88e6095_g1_set_egress_port,
4987 .watchdog_ops = &mv88e6097_watchdog_ops,
4988 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4989 .pot_clear = mv88e6xxx_g2_pot_clear,
4990 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4991 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4992 .reset = mv88e6352_g1_reset,
4993 .rmu_disable = mv88e6352_g1_rmu_disable,
4994 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4995 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4996 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4997 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4998 .stu_getnext = mv88e6352_g1_stu_getnext,
4999 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5000 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5001 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5002 .serdes_get_regs = mv88e6352_serdes_get_regs,
5003 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5004 .gpio_ops = &mv88e6352_gpio_ops,
5005 .avb_ops = &mv88e6352_avb_ops,
5006 .ptp_ops = &mv88e6352_ptp_ops,
5007 .phylink_get_caps = mv88e6352_phylink_get_caps,
5008 .pcs_ops = &mv88e6352_pcs_ops,
5009};
5010
5011static const struct mv88e6xxx_ops mv88e6250_ops = {
5012 /* MV88E6XXX_FAMILY_6250 */
5013 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
5014 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5015 .irl_init_all = mv88e6352_g2_irl_init_all,
5016 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5017 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5018 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5019 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5020 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5021 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5022 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5023 .port_set_link = mv88e6xxx_port_set_link,
5024 .port_sync_link = mv88e6xxx_port_sync_link,
5025 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5026 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
5027 .port_tag_remap = mv88e6095_port_tag_remap,
5028 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5029 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5030 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5031 .port_set_ether_type = mv88e6351_port_set_ether_type,
5032 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5033 .port_pause_limit = mv88e6097_port_pause_limit,
5034 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5035 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5036 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5037 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
5038 .stats_get_strings = mv88e6250_stats_get_strings,
5039 .stats_get_stat = mv88e6250_stats_get_stat,
5040 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5041 .set_egress_port = mv88e6095_g1_set_egress_port,
5042 .watchdog_ops = &mv88e6250_watchdog_ops,
5043 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5044 .pot_clear = mv88e6xxx_g2_pot_clear,
5045 .hardware_reset_pre = mv88e6250_g1_wait_eeprom_done_prereset,
5046 .hardware_reset_post = mv88e6xxx_g1_wait_eeprom_done,
5047 .reset = mv88e6250_g1_reset,
5048 .vtu_getnext = mv88e6185_g1_vtu_getnext,
5049 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5050 .avb_ops = &mv88e6352_avb_ops,
5051 .ptp_ops = &mv88e6250_ptp_ops,
5052 .phylink_get_caps = mv88e6250_phylink_get_caps,
5053 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
5054};
5055
5056static const struct mv88e6xxx_ops mv88e6290_ops = {
5057 /* MV88E6XXX_FAMILY_6390 */
5058 .setup_errata = mv88e6390_setup_errata,
5059 .irl_init_all = mv88e6390_g2_irl_init_all,
5060 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5061 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5062 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5063 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5064 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5065 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5066 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5067 .port_set_link = mv88e6xxx_port_set_link,
5068 .port_sync_link = mv88e6xxx_port_sync_link,
5069 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5070 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5071 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5072 .port_tag_remap = mv88e6390_port_tag_remap,
5073 .port_set_policy = mv88e6352_port_set_policy,
5074 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5075 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5076 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5077 .port_set_ether_type = mv88e6351_port_set_ether_type,
5078 .port_pause_limit = mv88e6390_port_pause_limit,
5079 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5080 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5081 .port_get_cmode = mv88e6352_port_get_cmode,
5082 .port_set_cmode = mv88e6390_port_set_cmode,
5083 .port_setup_message_port = mv88e6xxx_setup_message_port,
5084 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5085 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5086 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5087 .stats_get_strings = mv88e6320_stats_get_strings,
5088 .stats_get_stat = mv88e6390_stats_get_stat,
5089 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5090 .set_egress_port = mv88e6390_g1_set_egress_port,
5091 .watchdog_ops = &mv88e6390_watchdog_ops,
5092 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5093 .pot_clear = mv88e6xxx_g2_pot_clear,
5094 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5095 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5096 .reset = mv88e6352_g1_reset,
5097 .rmu_disable = mv88e6390_g1_rmu_disable,
5098 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5099 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5100 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5101 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5102 .stu_getnext = mv88e6390_g1_stu_getnext,
5103 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5104 .serdes_get_lane = mv88e6390_serdes_get_lane,
5105 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5106 .serdes_get_strings = mv88e6390_serdes_get_strings,
5107 .serdes_get_stats = mv88e6390_serdes_get_stats,
5108 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5109 .serdes_get_regs = mv88e6390_serdes_get_regs,
5110 .gpio_ops = &mv88e6352_gpio_ops,
5111 .avb_ops = &mv88e6390_avb_ops,
5112 .ptp_ops = &mv88e6390_ptp_ops,
5113 .phylink_get_caps = mv88e6390_phylink_get_caps,
5114 .pcs_ops = &mv88e6390_pcs_ops,
5115};
5116
5117static const struct mv88e6xxx_ops mv88e6320_ops = {
5118 /* MV88E6XXX_FAMILY_6320 */
5119 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5120 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5121 .irl_init_all = mv88e6352_g2_irl_init_all,
5122 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5123 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5124 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5125 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5126 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5127 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5128 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5129 .port_set_link = mv88e6xxx_port_set_link,
5130 .port_sync_link = mv88e6xxx_port_sync_link,
5131 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5132 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5133 .port_tag_remap = mv88e6095_port_tag_remap,
5134 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5135 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5136 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5137 .port_set_ether_type = mv88e6351_port_set_ether_type,
5138 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5139 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5140 .port_pause_limit = mv88e6097_port_pause_limit,
5141 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5142 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5143 .port_get_cmode = mv88e6352_port_get_cmode,
5144 .port_setup_message_port = mv88e6xxx_setup_message_port,
5145 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5146 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5147 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5148 .stats_get_strings = mv88e6320_stats_get_strings,
5149 .stats_get_stat = mv88e6320_stats_get_stat,
5150 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5151 .set_egress_port = mv88e6095_g1_set_egress_port,
5152 .watchdog_ops = &mv88e6390_watchdog_ops,
5153 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5154 .pot_clear = mv88e6xxx_g2_pot_clear,
5155 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5156 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5157 .reset = mv88e6352_g1_reset,
5158 .vtu_getnext = mv88e6185_g1_vtu_getnext,
5159 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5160 .gpio_ops = &mv88e6352_gpio_ops,
5161 .avb_ops = &mv88e6352_avb_ops,
5162 .ptp_ops = &mv88e6352_ptp_ops,
5163 .phylink_get_caps = mv88e632x_phylink_get_caps,
5164};
5165
5166static const struct mv88e6xxx_ops mv88e6321_ops = {
5167 /* MV88E6XXX_FAMILY_6320 */
5168 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5169 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5170 .irl_init_all = mv88e6352_g2_irl_init_all,
5171 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5172 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5173 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5174 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5175 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5176 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5177 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5178 .port_set_link = mv88e6xxx_port_set_link,
5179 .port_sync_link = mv88e6xxx_port_sync_link,
5180 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5181 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5182 .port_tag_remap = mv88e6095_port_tag_remap,
5183 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5184 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5185 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5186 .port_set_ether_type = mv88e6351_port_set_ether_type,
5187 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5188 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5189 .port_pause_limit = mv88e6097_port_pause_limit,
5190 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5191 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5192 .port_get_cmode = mv88e6352_port_get_cmode,
5193 .port_setup_message_port = mv88e6xxx_setup_message_port,
5194 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5195 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5196 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5197 .stats_get_strings = mv88e6320_stats_get_strings,
5198 .stats_get_stat = mv88e6320_stats_get_stat,
5199 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5200 .set_egress_port = mv88e6095_g1_set_egress_port,
5201 .watchdog_ops = &mv88e6390_watchdog_ops,
5202 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5203 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5204 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5205 .reset = mv88e6352_g1_reset,
5206 .vtu_getnext = mv88e6185_g1_vtu_getnext,
5207 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5208 .gpio_ops = &mv88e6352_gpio_ops,
5209 .avb_ops = &mv88e6352_avb_ops,
5210 .ptp_ops = &mv88e6352_ptp_ops,
5211 .phylink_get_caps = mv88e632x_phylink_get_caps,
5212};
5213
5214static const struct mv88e6xxx_ops mv88e6341_ops = {
5215 /* MV88E6XXX_FAMILY_6341 */
5216 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5217 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5218 .irl_init_all = mv88e6352_g2_irl_init_all,
5219 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5220 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5221 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5222 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5223 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5224 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5225 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5226 .port_set_link = mv88e6xxx_port_set_link,
5227 .port_sync_link = mv88e6xxx_port_sync_link,
5228 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5229 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
5230 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
5231 .port_tag_remap = mv88e6095_port_tag_remap,
5232 .port_set_policy = mv88e6352_port_set_policy,
5233 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5234 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5235 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5236 .port_set_ether_type = mv88e6351_port_set_ether_type,
5237 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5238 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5239 .port_pause_limit = mv88e6097_port_pause_limit,
5240 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5241 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5242 .port_get_cmode = mv88e6352_port_get_cmode,
5243 .port_set_cmode = mv88e6341_port_set_cmode,
5244 .port_setup_message_port = mv88e6xxx_setup_message_port,
5245 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5246 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5247 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5248 .stats_get_strings = mv88e6320_stats_get_strings,
5249 .stats_get_stat = mv88e6390_stats_get_stat,
5250 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5251 .set_egress_port = mv88e6390_g1_set_egress_port,
5252 .watchdog_ops = &mv88e6390_watchdog_ops,
5253 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5254 .pot_clear = mv88e6xxx_g2_pot_clear,
5255 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5256 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5257 .reset = mv88e6352_g1_reset,
5258 .rmu_disable = mv88e6390_g1_rmu_disable,
5259 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5260 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5261 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5262 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5263 .stu_getnext = mv88e6352_g1_stu_getnext,
5264 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5265 .serdes_get_lane = mv88e6341_serdes_get_lane,
5266 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5267 .gpio_ops = &mv88e6352_gpio_ops,
5268 .avb_ops = &mv88e6390_avb_ops,
5269 .ptp_ops = &mv88e6352_ptp_ops,
5270 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5271 .serdes_get_strings = mv88e6390_serdes_get_strings,
5272 .serdes_get_stats = mv88e6390_serdes_get_stats,
5273 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5274 .serdes_get_regs = mv88e6390_serdes_get_regs,
5275 .phylink_get_caps = mv88e6341_phylink_get_caps,
5276 .pcs_ops = &mv88e6390_pcs_ops,
5277};
5278
5279static const struct mv88e6xxx_ops mv88e6350_ops = {
5280 /* MV88E6XXX_FAMILY_6351 */
5281 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5282 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5283 .irl_init_all = mv88e6352_g2_irl_init_all,
5284 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5285 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5286 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5287 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5288 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5289 .port_set_link = mv88e6xxx_port_set_link,
5290 .port_sync_link = mv88e6xxx_port_sync_link,
5291 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5292 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5293 .port_tag_remap = mv88e6095_port_tag_remap,
5294 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5295 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5296 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5297 .port_set_ether_type = mv88e6351_port_set_ether_type,
5298 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5299 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5300 .port_pause_limit = mv88e6097_port_pause_limit,
5301 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5302 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5303 .port_get_cmode = mv88e6352_port_get_cmode,
5304 .port_setup_message_port = mv88e6xxx_setup_message_port,
5305 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5306 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5307 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5308 .stats_get_strings = mv88e6095_stats_get_strings,
5309 .stats_get_stat = mv88e6095_stats_get_stat,
5310 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5311 .set_egress_port = mv88e6095_g1_set_egress_port,
5312 .watchdog_ops = &mv88e6097_watchdog_ops,
5313 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5314 .pot_clear = mv88e6xxx_g2_pot_clear,
5315 .reset = mv88e6352_g1_reset,
5316 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5317 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5318 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5319 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5320 .stu_getnext = mv88e6352_g1_stu_getnext,
5321 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5322 .phylink_get_caps = mv88e6351_phylink_get_caps,
5323};
5324
5325static const struct mv88e6xxx_ops mv88e6351_ops = {
5326 /* MV88E6XXX_FAMILY_6351 */
5327 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5328 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5329 .irl_init_all = mv88e6352_g2_irl_init_all,
5330 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5331 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5332 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5333 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5334 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5335 .port_set_link = mv88e6xxx_port_set_link,
5336 .port_sync_link = mv88e6xxx_port_sync_link,
5337 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5338 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5339 .port_tag_remap = mv88e6095_port_tag_remap,
5340 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5341 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5342 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5343 .port_set_ether_type = mv88e6351_port_set_ether_type,
5344 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5345 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5346 .port_pause_limit = mv88e6097_port_pause_limit,
5347 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5348 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5349 .port_get_cmode = mv88e6352_port_get_cmode,
5350 .port_setup_message_port = mv88e6xxx_setup_message_port,
5351 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5352 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5353 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5354 .stats_get_strings = mv88e6095_stats_get_strings,
5355 .stats_get_stat = mv88e6095_stats_get_stat,
5356 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5357 .set_egress_port = mv88e6095_g1_set_egress_port,
5358 .watchdog_ops = &mv88e6097_watchdog_ops,
5359 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5360 .pot_clear = mv88e6xxx_g2_pot_clear,
5361 .reset = mv88e6352_g1_reset,
5362 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5363 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5364 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5365 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5366 .stu_getnext = mv88e6352_g1_stu_getnext,
5367 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5368 .avb_ops = &mv88e6352_avb_ops,
5369 .ptp_ops = &mv88e6352_ptp_ops,
5370 .phylink_get_caps = mv88e6351_phylink_get_caps,
5371};
5372
5373static const struct mv88e6xxx_ops mv88e6352_ops = {
5374 /* MV88E6XXX_FAMILY_6352 */
5375 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5376 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5377 .irl_init_all = mv88e6352_g2_irl_init_all,
5378 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5379 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5380 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5381 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5382 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5383 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5384 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5385 .port_set_link = mv88e6xxx_port_set_link,
5386 .port_sync_link = mv88e6xxx_port_sync_link,
5387 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5388 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
5389 .port_tag_remap = mv88e6095_port_tag_remap,
5390 .port_set_policy = mv88e6352_port_set_policy,
5391 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5392 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5393 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5394 .port_set_ether_type = mv88e6351_port_set_ether_type,
5395 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5396 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5397 .port_pause_limit = mv88e6097_port_pause_limit,
5398 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5399 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5400 .port_get_cmode = mv88e6352_port_get_cmode,
5401 .port_setup_leds = mv88e6xxx_port_setup_leds,
5402 .port_setup_message_port = mv88e6xxx_setup_message_port,
5403 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5404 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5405 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5406 .stats_get_strings = mv88e6095_stats_get_strings,
5407 .stats_get_stat = mv88e6095_stats_get_stat,
5408 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5409 .set_egress_port = mv88e6095_g1_set_egress_port,
5410 .watchdog_ops = &mv88e6097_watchdog_ops,
5411 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5412 .pot_clear = mv88e6xxx_g2_pot_clear,
5413 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5414 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5415 .reset = mv88e6352_g1_reset,
5416 .rmu_disable = mv88e6352_g1_rmu_disable,
5417 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5418 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5419 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5420 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5421 .stu_getnext = mv88e6352_g1_stu_getnext,
5422 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5423 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5424 .gpio_ops = &mv88e6352_gpio_ops,
5425 .avb_ops = &mv88e6352_avb_ops,
5426 .ptp_ops = &mv88e6352_ptp_ops,
5427 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
5428 .serdes_get_strings = mv88e6352_serdes_get_strings,
5429 .serdes_get_stats = mv88e6352_serdes_get_stats,
5430 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5431 .serdes_get_regs = mv88e6352_serdes_get_regs,
5432 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5433 .phylink_get_caps = mv88e6352_phylink_get_caps,
5434 .pcs_ops = &mv88e6352_pcs_ops,
5435};
5436
5437static const struct mv88e6xxx_ops mv88e6390_ops = {
5438 /* MV88E6XXX_FAMILY_6390 */
5439 .setup_errata = mv88e6390_setup_errata,
5440 .irl_init_all = mv88e6390_g2_irl_init_all,
5441 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5442 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5443 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5444 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5445 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5446 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5447 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5448 .port_set_link = mv88e6xxx_port_set_link,
5449 .port_sync_link = mv88e6xxx_port_sync_link,
5450 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5451 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5452 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5453 .port_tag_remap = mv88e6390_port_tag_remap,
5454 .port_set_policy = mv88e6352_port_set_policy,
5455 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5456 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5457 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5458 .port_set_ether_type = mv88e6351_port_set_ether_type,
5459 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5460 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5461 .port_pause_limit = mv88e6390_port_pause_limit,
5462 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5463 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5464 .port_get_cmode = mv88e6352_port_get_cmode,
5465 .port_set_cmode = mv88e6390_port_set_cmode,
5466 .port_setup_message_port = mv88e6xxx_setup_message_port,
5467 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5468 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5469 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5470 .stats_get_strings = mv88e6320_stats_get_strings,
5471 .stats_get_stat = mv88e6390_stats_get_stat,
5472 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5473 .set_egress_port = mv88e6390_g1_set_egress_port,
5474 .watchdog_ops = &mv88e6390_watchdog_ops,
5475 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5476 .pot_clear = mv88e6xxx_g2_pot_clear,
5477 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5478 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5479 .reset = mv88e6352_g1_reset,
5480 .rmu_disable = mv88e6390_g1_rmu_disable,
5481 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5482 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5483 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5484 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5485 .stu_getnext = mv88e6390_g1_stu_getnext,
5486 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5487 .serdes_get_lane = mv88e6390_serdes_get_lane,
5488 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5489 .gpio_ops = &mv88e6352_gpio_ops,
5490 .avb_ops = &mv88e6390_avb_ops,
5491 .ptp_ops = &mv88e6390_ptp_ops,
5492 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5493 .serdes_get_strings = mv88e6390_serdes_get_strings,
5494 .serdes_get_stats = mv88e6390_serdes_get_stats,
5495 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5496 .serdes_get_regs = mv88e6390_serdes_get_regs,
5497 .phylink_get_caps = mv88e6390_phylink_get_caps,
5498 .pcs_ops = &mv88e6390_pcs_ops,
5499};
5500
5501static const struct mv88e6xxx_ops mv88e6390x_ops = {
5502 /* MV88E6XXX_FAMILY_6390 */
5503 .setup_errata = mv88e6390_setup_errata,
5504 .irl_init_all = mv88e6390_g2_irl_init_all,
5505 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5506 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5507 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5508 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5509 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5510 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5511 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5512 .port_set_link = mv88e6xxx_port_set_link,
5513 .port_sync_link = mv88e6xxx_port_sync_link,
5514 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5515 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
5516 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
5517 .port_tag_remap = mv88e6390_port_tag_remap,
5518 .port_set_policy = mv88e6352_port_set_policy,
5519 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5520 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5521 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5522 .port_set_ether_type = mv88e6351_port_set_ether_type,
5523 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5524 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5525 .port_pause_limit = mv88e6390_port_pause_limit,
5526 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5527 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5528 .port_get_cmode = mv88e6352_port_get_cmode,
5529 .port_set_cmode = mv88e6390x_port_set_cmode,
5530 .port_setup_message_port = mv88e6xxx_setup_message_port,
5531 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5532 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5533 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5534 .stats_get_strings = mv88e6320_stats_get_strings,
5535 .stats_get_stat = mv88e6390_stats_get_stat,
5536 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5537 .set_egress_port = mv88e6390_g1_set_egress_port,
5538 .watchdog_ops = &mv88e6390_watchdog_ops,
5539 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5540 .pot_clear = mv88e6xxx_g2_pot_clear,
5541 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5542 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5543 .reset = mv88e6352_g1_reset,
5544 .rmu_disable = mv88e6390_g1_rmu_disable,
5545 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5546 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5547 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5548 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5549 .stu_getnext = mv88e6390_g1_stu_getnext,
5550 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5551 .serdes_get_lane = mv88e6390x_serdes_get_lane,
5552 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5553 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5554 .serdes_get_strings = mv88e6390_serdes_get_strings,
5555 .serdes_get_stats = mv88e6390_serdes_get_stats,
5556 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5557 .serdes_get_regs = mv88e6390_serdes_get_regs,
5558 .gpio_ops = &mv88e6352_gpio_ops,
5559 .avb_ops = &mv88e6390_avb_ops,
5560 .ptp_ops = &mv88e6390_ptp_ops,
5561 .phylink_get_caps = mv88e6390x_phylink_get_caps,
5562 .pcs_ops = &mv88e6390_pcs_ops,
5563};
5564
5565static const struct mv88e6xxx_ops mv88e6393x_ops = {
5566 /* MV88E6XXX_FAMILY_6393 */
5567 .irl_init_all = mv88e6390_g2_irl_init_all,
5568 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5569 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5570 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5571 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5572 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5573 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5574 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5575 .port_set_link = mv88e6xxx_port_set_link,
5576 .port_sync_link = mv88e6xxx_port_sync_link,
5577 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5578 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
5579 .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
5580 .port_tag_remap = mv88e6390_port_tag_remap,
5581 .port_set_policy = mv88e6393x_port_set_policy,
5582 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5583 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5584 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5585 .port_set_ether_type = mv88e6393x_port_set_ether_type,
5586 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5587 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5588 .port_pause_limit = mv88e6390_port_pause_limit,
5589 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5590 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5591 .port_get_cmode = mv88e6352_port_get_cmode,
5592 .port_set_cmode = mv88e6393x_port_set_cmode,
5593 .port_setup_message_port = mv88e6xxx_setup_message_port,
5594 .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
5595 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5596 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5597 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5598 .stats_get_strings = mv88e6320_stats_get_strings,
5599 .stats_get_stat = mv88e6390_stats_get_stat,
5600 /* .set_cpu_port is missing because this family does not support a global
5601 * CPU port, only per port CPU port which is set via
5602 * .port_set_upstream_port method.
5603 */
5604 .set_egress_port = mv88e6393x_set_egress_port,
5605 .watchdog_ops = &mv88e6393x_watchdog_ops,
5606 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
5607 .pot_clear = mv88e6xxx_g2_pot_clear,
5608 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5609 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5610 .reset = mv88e6352_g1_reset,
5611 .rmu_disable = mv88e6390_g1_rmu_disable,
5612 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5613 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5614 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5615 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5616 .stu_getnext = mv88e6390_g1_stu_getnext,
5617 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5618 .serdes_get_lane = mv88e6393x_serdes_get_lane,
5619 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5620 /* TODO: serdes stats */
5621 .gpio_ops = &mv88e6352_gpio_ops,
5622 .avb_ops = &mv88e6390_avb_ops,
5623 .ptp_ops = &mv88e6352_ptp_ops,
5624 .phylink_get_caps = mv88e6393x_phylink_get_caps,
5625 .pcs_ops = &mv88e6393x_pcs_ops,
5626};
5627
5628static const struct mv88e6xxx_info mv88e6xxx_table[] = {
5629 [MV88E6020] = {
5630 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020,
5631 .family = MV88E6XXX_FAMILY_6250,
5632 .name = "Marvell 88E6020",
5633 .num_databases = 64,
5634 /* Ports 2-4 are not routed to pins
5635 * => usable ports 0, 1, 5, 6
5636 */
5637 .num_ports = 7,
5638 .num_internal_phys = 2,
5639 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5640 .max_vid = 4095,
5641 .port_base_addr = 0x8,
5642 .phy_base_addr = 0x0,
5643 .global1_addr = 0xf,
5644 .global2_addr = 0x7,
5645 .age_time_coeff = 15000,
5646 .g1_irqs = 9,
5647 .g2_irqs = 5,
5648 .atu_move_port_mask = 0xf,
5649 .dual_chip = true,
5650 .ops = &mv88e6250_ops,
5651 },
5652
5653 [MV88E6071] = {
5654 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071,
5655 .family = MV88E6XXX_FAMILY_6250,
5656 .name = "Marvell 88E6071",
5657 .num_databases = 64,
5658 .num_ports = 7,
5659 .num_internal_phys = 5,
5660 .max_vid = 4095,
5661 .port_base_addr = 0x08,
5662 .phy_base_addr = 0x00,
5663 .global1_addr = 0x0f,
5664 .global2_addr = 0x07,
5665 .age_time_coeff = 15000,
5666 .g1_irqs = 9,
5667 .g2_irqs = 5,
5668 .atu_move_port_mask = 0xf,
5669 .dual_chip = true,
5670 .ops = &mv88e6250_ops,
5671 },
5672
5673 [MV88E6085] = {
5674 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
5675 .family = MV88E6XXX_FAMILY_6097,
5676 .name = "Marvell 88E6085",
5677 .num_databases = 4096,
5678 .num_macs = 8192,
5679 .num_ports = 10,
5680 .num_internal_phys = 5,
5681 .max_vid = 4095,
5682 .max_sid = 63,
5683 .port_base_addr = 0x10,
5684 .phy_base_addr = 0x0,
5685 .global1_addr = 0x1b,
5686 .global2_addr = 0x1c,
5687 .age_time_coeff = 15000,
5688 .g1_irqs = 8,
5689 .g2_irqs = 10,
5690 .atu_move_port_mask = 0xf,
5691 .pvt = true,
5692 .multi_chip = true,
5693 .ops = &mv88e6085_ops,
5694 },
5695
5696 [MV88E6095] = {
5697 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
5698 .family = MV88E6XXX_FAMILY_6095,
5699 .name = "Marvell 88E6095/88E6095F",
5700 .num_databases = 256,
5701 .num_macs = 8192,
5702 .num_ports = 11,
5703 .num_internal_phys = 0,
5704 .max_vid = 4095,
5705 .port_base_addr = 0x10,
5706 .phy_base_addr = 0x0,
5707 .global1_addr = 0x1b,
5708 .global2_addr = 0x1c,
5709 .age_time_coeff = 15000,
5710 .g1_irqs = 8,
5711 .atu_move_port_mask = 0xf,
5712 .multi_chip = true,
5713 .ops = &mv88e6095_ops,
5714 },
5715
5716 [MV88E6097] = {
5717 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
5718 .family = MV88E6XXX_FAMILY_6097,
5719 .name = "Marvell 88E6097/88E6097F",
5720 .num_databases = 4096,
5721 .num_macs = 8192,
5722 .num_ports = 11,
5723 .num_internal_phys = 8,
5724 .max_vid = 4095,
5725 .max_sid = 63,
5726 .port_base_addr = 0x10,
5727 .phy_base_addr = 0x0,
5728 .global1_addr = 0x1b,
5729 .global2_addr = 0x1c,
5730 .age_time_coeff = 15000,
5731 .g1_irqs = 8,
5732 .g2_irqs = 10,
5733 .atu_move_port_mask = 0xf,
5734 .pvt = true,
5735 .multi_chip = true,
5736 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5737 .ops = &mv88e6097_ops,
5738 },
5739
5740 [MV88E6123] = {
5741 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
5742 .family = MV88E6XXX_FAMILY_6165,
5743 .name = "Marvell 88E6123",
5744 .num_databases = 4096,
5745 .num_macs = 1024,
5746 .num_ports = 3,
5747 .num_internal_phys = 5,
5748 .max_vid = 4095,
5749 .max_sid = 63,
5750 .port_base_addr = 0x10,
5751 .phy_base_addr = 0x0,
5752 .global1_addr = 0x1b,
5753 .global2_addr = 0x1c,
5754 .age_time_coeff = 15000,
5755 .g1_irqs = 9,
5756 .g2_irqs = 10,
5757 .atu_move_port_mask = 0xf,
5758 .pvt = true,
5759 .multi_chip = true,
5760 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5761 .ops = &mv88e6123_ops,
5762 },
5763
5764 [MV88E6131] = {
5765 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
5766 .family = MV88E6XXX_FAMILY_6185,
5767 .name = "Marvell 88E6131",
5768 .num_databases = 256,
5769 .num_macs = 8192,
5770 .num_ports = 8,
5771 .num_internal_phys = 0,
5772 .max_vid = 4095,
5773 .port_base_addr = 0x10,
5774 .phy_base_addr = 0x0,
5775 .global1_addr = 0x1b,
5776 .global2_addr = 0x1c,
5777 .age_time_coeff = 15000,
5778 .g1_irqs = 9,
5779 .atu_move_port_mask = 0xf,
5780 .multi_chip = true,
5781 .ops = &mv88e6131_ops,
5782 },
5783
5784 [MV88E6141] = {
5785 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
5786 .family = MV88E6XXX_FAMILY_6341,
5787 .name = "Marvell 88E6141",
5788 .num_databases = 256,
5789 .num_macs = 2048,
5790 .num_ports = 6,
5791 .num_internal_phys = 5,
5792 .num_gpio = 11,
5793 .max_vid = 4095,
5794 .max_sid = 63,
5795 .port_base_addr = 0x10,
5796 .phy_base_addr = 0x10,
5797 .global1_addr = 0x1b,
5798 .global2_addr = 0x1c,
5799 .age_time_coeff = 3750,
5800 .atu_move_port_mask = 0x1f,
5801 .g1_irqs = 9,
5802 .g2_irqs = 10,
5803 .pvt = true,
5804 .multi_chip = true,
5805 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5806 .ops = &mv88e6141_ops,
5807 },
5808
5809 [MV88E6161] = {
5810 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
5811 .family = MV88E6XXX_FAMILY_6165,
5812 .name = "Marvell 88E6161",
5813 .num_databases = 4096,
5814 .num_macs = 1024,
5815 .num_ports = 6,
5816 .num_internal_phys = 5,
5817 .max_vid = 4095,
5818 .max_sid = 63,
5819 .port_base_addr = 0x10,
5820 .phy_base_addr = 0x0,
5821 .global1_addr = 0x1b,
5822 .global2_addr = 0x1c,
5823 .age_time_coeff = 15000,
5824 .g1_irqs = 9,
5825 .g2_irqs = 10,
5826 .atu_move_port_mask = 0xf,
5827 .pvt = true,
5828 .multi_chip = true,
5829 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5830 .ptp_support = true,
5831 .ops = &mv88e6161_ops,
5832 },
5833
5834 [MV88E6165] = {
5835 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
5836 .family = MV88E6XXX_FAMILY_6165,
5837 .name = "Marvell 88E6165",
5838 .num_databases = 4096,
5839 .num_macs = 8192,
5840 .num_ports = 6,
5841 .num_internal_phys = 0,
5842 .max_vid = 4095,
5843 .max_sid = 63,
5844 .port_base_addr = 0x10,
5845 .phy_base_addr = 0x0,
5846 .global1_addr = 0x1b,
5847 .global2_addr = 0x1c,
5848 .age_time_coeff = 15000,
5849 .g1_irqs = 9,
5850 .g2_irqs = 10,
5851 .atu_move_port_mask = 0xf,
5852 .pvt = true,
5853 .multi_chip = true,
5854 .ptp_support = true,
5855 .ops = &mv88e6165_ops,
5856 },
5857
5858 [MV88E6171] = {
5859 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
5860 .family = MV88E6XXX_FAMILY_6351,
5861 .name = "Marvell 88E6171",
5862 .num_databases = 4096,
5863 .num_macs = 8192,
5864 .num_ports = 7,
5865 .num_internal_phys = 5,
5866 .max_vid = 4095,
5867 .max_sid = 63,
5868 .port_base_addr = 0x10,
5869 .phy_base_addr = 0x0,
5870 .global1_addr = 0x1b,
5871 .global2_addr = 0x1c,
5872 .age_time_coeff = 15000,
5873 .g1_irqs = 9,
5874 .g2_irqs = 10,
5875 .atu_move_port_mask = 0xf,
5876 .pvt = true,
5877 .multi_chip = true,
5878 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5879 .ops = &mv88e6171_ops,
5880 },
5881
5882 [MV88E6172] = {
5883 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
5884 .family = MV88E6XXX_FAMILY_6352,
5885 .name = "Marvell 88E6172",
5886 .num_databases = 4096,
5887 .num_macs = 8192,
5888 .num_ports = 7,
5889 .num_internal_phys = 5,
5890 .num_gpio = 15,
5891 .max_vid = 4095,
5892 .max_sid = 63,
5893 .port_base_addr = 0x10,
5894 .phy_base_addr = 0x0,
5895 .global1_addr = 0x1b,
5896 .global2_addr = 0x1c,
5897 .age_time_coeff = 15000,
5898 .g1_irqs = 9,
5899 .g2_irqs = 10,
5900 .atu_move_port_mask = 0xf,
5901 .pvt = true,
5902 .multi_chip = true,
5903 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5904 .ops = &mv88e6172_ops,
5905 },
5906
5907 [MV88E6175] = {
5908 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
5909 .family = MV88E6XXX_FAMILY_6351,
5910 .name = "Marvell 88E6175",
5911 .num_databases = 4096,
5912 .num_macs = 8192,
5913 .num_ports = 7,
5914 .num_internal_phys = 5,
5915 .max_vid = 4095,
5916 .max_sid = 63,
5917 .port_base_addr = 0x10,
5918 .phy_base_addr = 0x0,
5919 .global1_addr = 0x1b,
5920 .global2_addr = 0x1c,
5921 .age_time_coeff = 15000,
5922 .g1_irqs = 9,
5923 .g2_irqs = 10,
5924 .atu_move_port_mask = 0xf,
5925 .pvt = true,
5926 .multi_chip = true,
5927 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5928 .ops = &mv88e6175_ops,
5929 },
5930
5931 [MV88E6176] = {
5932 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5933 .family = MV88E6XXX_FAMILY_6352,
5934 .name = "Marvell 88E6176",
5935 .num_databases = 4096,
5936 .num_macs = 8192,
5937 .num_ports = 7,
5938 .num_internal_phys = 5,
5939 .num_gpio = 15,
5940 .max_vid = 4095,
5941 .max_sid = 63,
5942 .port_base_addr = 0x10,
5943 .phy_base_addr = 0x0,
5944 .global1_addr = 0x1b,
5945 .global2_addr = 0x1c,
5946 .age_time_coeff = 15000,
5947 .g1_irqs = 9,
5948 .g2_irqs = 10,
5949 .atu_move_port_mask = 0xf,
5950 .pvt = true,
5951 .multi_chip = true,
5952 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5953 .ops = &mv88e6176_ops,
5954 },
5955
5956 [MV88E6185] = {
5957 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
5958 .family = MV88E6XXX_FAMILY_6185,
5959 .name = "Marvell 88E6185",
5960 .num_databases = 256,
5961 .num_macs = 8192,
5962 .num_ports = 10,
5963 .num_internal_phys = 0,
5964 .max_vid = 4095,
5965 .port_base_addr = 0x10,
5966 .phy_base_addr = 0x0,
5967 .global1_addr = 0x1b,
5968 .global2_addr = 0x1c,
5969 .age_time_coeff = 15000,
5970 .g1_irqs = 8,
5971 .atu_move_port_mask = 0xf,
5972 .multi_chip = true,
5973 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5974 .ops = &mv88e6185_ops,
5975 },
5976
5977 [MV88E6190] = {
5978 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
5979 .family = MV88E6XXX_FAMILY_6390,
5980 .name = "Marvell 88E6190",
5981 .num_databases = 4096,
5982 .num_macs = 16384,
5983 .num_ports = 11, /* 10 + Z80 */
5984 .num_internal_phys = 9,
5985 .num_gpio = 16,
5986 .max_vid = 8191,
5987 .max_sid = 63,
5988 .port_base_addr = 0x0,
5989 .phy_base_addr = 0x0,
5990 .global1_addr = 0x1b,
5991 .global2_addr = 0x1c,
5992 .age_time_coeff = 3750,
5993 .g1_irqs = 9,
5994 .g2_irqs = 14,
5995 .pvt = true,
5996 .multi_chip = true,
5997 .atu_move_port_mask = 0x1f,
5998 .ops = &mv88e6190_ops,
5999 },
6000
6001 [MV88E6190X] = {
6002 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
6003 .family = MV88E6XXX_FAMILY_6390,
6004 .name = "Marvell 88E6190X",
6005 .num_databases = 4096,
6006 .num_macs = 16384,
6007 .num_ports = 11, /* 10 + Z80 */
6008 .num_internal_phys = 9,
6009 .num_gpio = 16,
6010 .max_vid = 8191,
6011 .max_sid = 63,
6012 .port_base_addr = 0x0,
6013 .phy_base_addr = 0x0,
6014 .global1_addr = 0x1b,
6015 .global2_addr = 0x1c,
6016 .age_time_coeff = 3750,
6017 .g1_irqs = 9,
6018 .g2_irqs = 14,
6019 .atu_move_port_mask = 0x1f,
6020 .pvt = true,
6021 .multi_chip = true,
6022 .ops = &mv88e6190x_ops,
6023 },
6024
6025 [MV88E6191] = {
6026 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
6027 .family = MV88E6XXX_FAMILY_6390,
6028 .name = "Marvell 88E6191",
6029 .num_databases = 4096,
6030 .num_macs = 16384,
6031 .num_ports = 11, /* 10 + Z80 */
6032 .num_internal_phys = 9,
6033 .max_vid = 8191,
6034 .max_sid = 63,
6035 .port_base_addr = 0x0,
6036 .phy_base_addr = 0x0,
6037 .global1_addr = 0x1b,
6038 .global2_addr = 0x1c,
6039 .age_time_coeff = 3750,
6040 .g1_irqs = 9,
6041 .g2_irqs = 14,
6042 .atu_move_port_mask = 0x1f,
6043 .pvt = true,
6044 .multi_chip = true,
6045 .ptp_support = true,
6046 .ops = &mv88e6191_ops,
6047 },
6048
6049 [MV88E6191X] = {
6050 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
6051 .family = MV88E6XXX_FAMILY_6393,
6052 .name = "Marvell 88E6191X",
6053 .num_databases = 4096,
6054 .num_ports = 11, /* 10 + Z80 */
6055 .num_internal_phys = 8,
6056 .internal_phys_offset = 1,
6057 .max_vid = 8191,
6058 .max_sid = 63,
6059 .port_base_addr = 0x0,
6060 .phy_base_addr = 0x0,
6061 .global1_addr = 0x1b,
6062 .global2_addr = 0x1c,
6063 .age_time_coeff = 3750,
6064 .g1_irqs = 10,
6065 .g2_irqs = 14,
6066 .atu_move_port_mask = 0x1f,
6067 .pvt = true,
6068 .multi_chip = true,
6069 .ptp_support = true,
6070 .ops = &mv88e6393x_ops,
6071 },
6072
6073 [MV88E6193X] = {
6074 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
6075 .family = MV88E6XXX_FAMILY_6393,
6076 .name = "Marvell 88E6193X",
6077 .num_databases = 4096,
6078 .num_ports = 11, /* 10 + Z80 */
6079 .num_internal_phys = 8,
6080 .internal_phys_offset = 1,
6081 .max_vid = 8191,
6082 .max_sid = 63,
6083 .port_base_addr = 0x0,
6084 .phy_base_addr = 0x0,
6085 .global1_addr = 0x1b,
6086 .global2_addr = 0x1c,
6087 .age_time_coeff = 3750,
6088 .g1_irqs = 10,
6089 .g2_irqs = 14,
6090 .atu_move_port_mask = 0x1f,
6091 .pvt = true,
6092 .multi_chip = true,
6093 .ptp_support = true,
6094 .ops = &mv88e6393x_ops,
6095 },
6096
6097 [MV88E6220] = {
6098 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
6099 .family = MV88E6XXX_FAMILY_6250,
6100 .name = "Marvell 88E6220",
6101 .num_databases = 64,
6102
6103 /* Ports 2-4 are not routed to pins
6104 * => usable ports 0, 1, 5, 6
6105 */
6106 .num_ports = 7,
6107 .num_internal_phys = 2,
6108 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
6109 .max_vid = 4095,
6110 .port_base_addr = 0x08,
6111 .phy_base_addr = 0x00,
6112 .global1_addr = 0x0f,
6113 .global2_addr = 0x07,
6114 .age_time_coeff = 15000,
6115 .g1_irqs = 9,
6116 .g2_irqs = 10,
6117 .atu_move_port_mask = 0xf,
6118 .dual_chip = true,
6119 .ptp_support = true,
6120 .ops = &mv88e6250_ops,
6121 },
6122
6123 [MV88E6240] = {
6124 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
6125 .family = MV88E6XXX_FAMILY_6352,
6126 .name = "Marvell 88E6240",
6127 .num_databases = 4096,
6128 .num_macs = 8192,
6129 .num_ports = 7,
6130 .num_internal_phys = 5,
6131 .num_gpio = 15,
6132 .max_vid = 4095,
6133 .max_sid = 63,
6134 .port_base_addr = 0x10,
6135 .phy_base_addr = 0x0,
6136 .global1_addr = 0x1b,
6137 .global2_addr = 0x1c,
6138 .age_time_coeff = 15000,
6139 .g1_irqs = 9,
6140 .g2_irqs = 10,
6141 .atu_move_port_mask = 0xf,
6142 .pvt = true,
6143 .multi_chip = true,
6144 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6145 .ptp_support = true,
6146 .ops = &mv88e6240_ops,
6147 },
6148
6149 [MV88E6250] = {
6150 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
6151 .family = MV88E6XXX_FAMILY_6250,
6152 .name = "Marvell 88E6250",
6153 .num_databases = 64,
6154 .num_ports = 7,
6155 .num_internal_phys = 5,
6156 .max_vid = 4095,
6157 .port_base_addr = 0x08,
6158 .phy_base_addr = 0x00,
6159 .global1_addr = 0x0f,
6160 .global2_addr = 0x07,
6161 .age_time_coeff = 15000,
6162 .g1_irqs = 9,
6163 .g2_irqs = 10,
6164 .atu_move_port_mask = 0xf,
6165 .dual_chip = true,
6166 .ptp_support = true,
6167 .ops = &mv88e6250_ops,
6168 },
6169
6170 [MV88E6290] = {
6171 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
6172 .family = MV88E6XXX_FAMILY_6390,
6173 .name = "Marvell 88E6290",
6174 .num_databases = 4096,
6175 .num_ports = 11, /* 10 + Z80 */
6176 .num_internal_phys = 9,
6177 .num_gpio = 16,
6178 .max_vid = 8191,
6179 .max_sid = 63,
6180 .port_base_addr = 0x0,
6181 .phy_base_addr = 0x0,
6182 .global1_addr = 0x1b,
6183 .global2_addr = 0x1c,
6184 .age_time_coeff = 3750,
6185 .g1_irqs = 9,
6186 .g2_irqs = 14,
6187 .atu_move_port_mask = 0x1f,
6188 .pvt = true,
6189 .multi_chip = true,
6190 .ptp_support = true,
6191 .ops = &mv88e6290_ops,
6192 },
6193
6194 [MV88E6320] = {
6195 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
6196 .family = MV88E6XXX_FAMILY_6320,
6197 .name = "Marvell 88E6320",
6198 .num_databases = 4096,
6199 .num_macs = 8192,
6200 .num_ports = 7,
6201 .num_internal_phys = 5,
6202 .num_gpio = 15,
6203 .max_vid = 4095,
6204 .port_base_addr = 0x10,
6205 .phy_base_addr = 0x0,
6206 .global1_addr = 0x1b,
6207 .global2_addr = 0x1c,
6208 .age_time_coeff = 15000,
6209 .g1_irqs = 8,
6210 .g2_irqs = 10,
6211 .atu_move_port_mask = 0xf,
6212 .pvt = true,
6213 .multi_chip = true,
6214 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6215 .ptp_support = true,
6216 .ops = &mv88e6320_ops,
6217 },
6218
6219 [MV88E6321] = {
6220 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
6221 .family = MV88E6XXX_FAMILY_6320,
6222 .name = "Marvell 88E6321",
6223 .num_databases = 4096,
6224 .num_macs = 8192,
6225 .num_ports = 7,
6226 .num_internal_phys = 5,
6227 .num_gpio = 15,
6228 .max_vid = 4095,
6229 .port_base_addr = 0x10,
6230 .phy_base_addr = 0x0,
6231 .global1_addr = 0x1b,
6232 .global2_addr = 0x1c,
6233 .age_time_coeff = 15000,
6234 .g1_irqs = 8,
6235 .g2_irqs = 10,
6236 .atu_move_port_mask = 0xf,
6237 .multi_chip = true,
6238 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6239 .ptp_support = true,
6240 .ops = &mv88e6321_ops,
6241 },
6242
6243 [MV88E6341] = {
6244 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
6245 .family = MV88E6XXX_FAMILY_6341,
6246 .name = "Marvell 88E6341",
6247 .num_databases = 256,
6248 .num_macs = 2048,
6249 .num_internal_phys = 5,
6250 .num_ports = 6,
6251 .num_gpio = 11,
6252 .max_vid = 4095,
6253 .max_sid = 63,
6254 .port_base_addr = 0x10,
6255 .phy_base_addr = 0x10,
6256 .global1_addr = 0x1b,
6257 .global2_addr = 0x1c,
6258 .age_time_coeff = 3750,
6259 .atu_move_port_mask = 0x1f,
6260 .g1_irqs = 9,
6261 .g2_irqs = 10,
6262 .pvt = true,
6263 .multi_chip = true,
6264 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6265 .ptp_support = true,
6266 .ops = &mv88e6341_ops,
6267 },
6268
6269 [MV88E6350] = {
6270 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
6271 .family = MV88E6XXX_FAMILY_6351,
6272 .name = "Marvell 88E6350",
6273 .num_databases = 4096,
6274 .num_macs = 8192,
6275 .num_ports = 7,
6276 .num_internal_phys = 5,
6277 .max_vid = 4095,
6278 .max_sid = 63,
6279 .port_base_addr = 0x10,
6280 .phy_base_addr = 0x0,
6281 .global1_addr = 0x1b,
6282 .global2_addr = 0x1c,
6283 .age_time_coeff = 15000,
6284 .g1_irqs = 9,
6285 .g2_irqs = 10,
6286 .atu_move_port_mask = 0xf,
6287 .pvt = true,
6288 .multi_chip = true,
6289 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6290 .ops = &mv88e6350_ops,
6291 },
6292
6293 [MV88E6351] = {
6294 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
6295 .family = MV88E6XXX_FAMILY_6351,
6296 .name = "Marvell 88E6351",
6297 .num_databases = 4096,
6298 .num_macs = 8192,
6299 .num_ports = 7,
6300 .num_internal_phys = 5,
6301 .max_vid = 4095,
6302 .max_sid = 63,
6303 .port_base_addr = 0x10,
6304 .phy_base_addr = 0x0,
6305 .global1_addr = 0x1b,
6306 .global2_addr = 0x1c,
6307 .age_time_coeff = 15000,
6308 .g1_irqs = 9,
6309 .g2_irqs = 10,
6310 .atu_move_port_mask = 0xf,
6311 .pvt = true,
6312 .multi_chip = true,
6313 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6314 .ops = &mv88e6351_ops,
6315 },
6316
6317 [MV88E6352] = {
6318 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
6319 .family = MV88E6XXX_FAMILY_6352,
6320 .name = "Marvell 88E6352",
6321 .num_databases = 4096,
6322 .num_macs = 8192,
6323 .num_ports = 7,
6324 .num_internal_phys = 5,
6325 .num_gpio = 15,
6326 .max_vid = 4095,
6327 .max_sid = 63,
6328 .port_base_addr = 0x10,
6329 .phy_base_addr = 0x0,
6330 .global1_addr = 0x1b,
6331 .global2_addr = 0x1c,
6332 .age_time_coeff = 15000,
6333 .g1_irqs = 9,
6334 .g2_irqs = 10,
6335 .atu_move_port_mask = 0xf,
6336 .pvt = true,
6337 .multi_chip = true,
6338 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6339 .ptp_support = true,
6340 .ops = &mv88e6352_ops,
6341 },
6342 [MV88E6361] = {
6343 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361,
6344 .family = MV88E6XXX_FAMILY_6393,
6345 .name = "Marvell 88E6361",
6346 .num_databases = 4096,
6347 .num_macs = 16384,
6348 .num_ports = 11,
6349 /* Ports 1, 2 and 8 are not routed */
6350 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8),
6351 .num_internal_phys = 5,
6352 .internal_phys_offset = 3,
6353 .max_vid = 8191,
6354 .max_sid = 63,
6355 .port_base_addr = 0x0,
6356 .phy_base_addr = 0x0,
6357 .global1_addr = 0x1b,
6358 .global2_addr = 0x1c,
6359 .age_time_coeff = 3750,
6360 .g1_irqs = 10,
6361 .g2_irqs = 14,
6362 .atu_move_port_mask = 0x1f,
6363 .pvt = true,
6364 .multi_chip = true,
6365 .ptp_support = true,
6366 .ops = &mv88e6393x_ops,
6367 },
6368 [MV88E6390] = {
6369 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
6370 .family = MV88E6XXX_FAMILY_6390,
6371 .name = "Marvell 88E6390",
6372 .num_databases = 4096,
6373 .num_macs = 16384,
6374 .num_ports = 11, /* 10 + Z80 */
6375 .num_internal_phys = 9,
6376 .num_gpio = 16,
6377 .max_vid = 8191,
6378 .max_sid = 63,
6379 .port_base_addr = 0x0,
6380 .phy_base_addr = 0x0,
6381 .global1_addr = 0x1b,
6382 .global2_addr = 0x1c,
6383 .age_time_coeff = 3750,
6384 .g1_irqs = 9,
6385 .g2_irqs = 14,
6386 .atu_move_port_mask = 0x1f,
6387 .pvt = true,
6388 .multi_chip = true,
6389 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6390 .ptp_support = true,
6391 .ops = &mv88e6390_ops,
6392 },
6393 [MV88E6390X] = {
6394 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
6395 .family = MV88E6XXX_FAMILY_6390,
6396 .name = "Marvell 88E6390X",
6397 .num_databases = 4096,
6398 .num_macs = 16384,
6399 .num_ports = 11, /* 10 + Z80 */
6400 .num_internal_phys = 9,
6401 .num_gpio = 16,
6402 .max_vid = 8191,
6403 .max_sid = 63,
6404 .port_base_addr = 0x0,
6405 .phy_base_addr = 0x0,
6406 .global1_addr = 0x1b,
6407 .global2_addr = 0x1c,
6408 .age_time_coeff = 3750,
6409 .g1_irqs = 9,
6410 .g2_irqs = 14,
6411 .atu_move_port_mask = 0x1f,
6412 .pvt = true,
6413 .multi_chip = true,
6414 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6415 .ptp_support = true,
6416 .ops = &mv88e6390x_ops,
6417 },
6418
6419 [MV88E6393X] = {
6420 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
6421 .family = MV88E6XXX_FAMILY_6393,
6422 .name = "Marvell 88E6393X",
6423 .num_databases = 4096,
6424 .num_ports = 11, /* 10 + Z80 */
6425 .num_internal_phys = 8,
6426 .internal_phys_offset = 1,
6427 .max_vid = 8191,
6428 .max_sid = 63,
6429 .port_base_addr = 0x0,
6430 .phy_base_addr = 0x0,
6431 .global1_addr = 0x1b,
6432 .global2_addr = 0x1c,
6433 .age_time_coeff = 3750,
6434 .g1_irqs = 10,
6435 .g2_irqs = 14,
6436 .atu_move_port_mask = 0x1f,
6437 .pvt = true,
6438 .multi_chip = true,
6439 .ptp_support = true,
6440 .ops = &mv88e6393x_ops,
6441 },
6442};
6443
6444static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
6445{
6446 int i;
6447
6448 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
6449 if (mv88e6xxx_table[i].prod_num == prod_num)
6450 return &mv88e6xxx_table[i];
6451
6452 return NULL;
6453}
6454
6455static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
6456{
6457 const struct mv88e6xxx_info *info;
6458 unsigned int prod_num, rev;
6459 u16 id;
6460 int err;
6461
6462 mv88e6xxx_reg_lock(chip);
6463 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
6464 mv88e6xxx_reg_unlock(chip);
6465 if (err)
6466 return err;
6467
6468 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
6469 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
6470
6471 info = mv88e6xxx_lookup_info(prod_num);
6472 if (!info)
6473 return -ENODEV;
6474
6475 /* Update the compatible info with the probed one */
6476 chip->info = info;
6477
6478 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
6479 chip->info->prod_num, chip->info->name, rev);
6480
6481 return 0;
6482}
6483
6484static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip,
6485 struct mdio_device *mdiodev)
6486{
6487 int err;
6488
6489 /* dual_chip takes precedence over single/multi-chip modes */
6490 if (chip->info->dual_chip)
6491 return -EINVAL;
6492
6493 /* If the mdio addr is 16 indicating the first port address of a switch
6494 * (e.g. mv88e6*41) in single chip addressing mode the device may be
6495 * configured in single chip addressing mode. Setup the smi access as
6496 * single chip addressing mode and attempt to detect the model of the
6497 * switch, if this fails the device is not configured in single chip
6498 * addressing mode.
6499 */
6500 if (mdiodev->addr != 16)
6501 return -EINVAL;
6502
6503 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0);
6504 if (err)
6505 return err;
6506
6507 return mv88e6xxx_detect(chip);
6508}
6509
6510static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
6511{
6512 struct mv88e6xxx_chip *chip;
6513
6514 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
6515 if (!chip)
6516 return NULL;
6517
6518 chip->dev = dev;
6519
6520 mutex_init(&chip->reg_lock);
6521 INIT_LIST_HEAD(&chip->mdios);
6522 idr_init(&chip->policies);
6523 INIT_LIST_HEAD(&chip->msts);
6524
6525 return chip;
6526}
6527
6528static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
6529 int port,
6530 enum dsa_tag_protocol m)
6531{
6532 struct mv88e6xxx_chip *chip = ds->priv;
6533
6534 return chip->tag_protocol;
6535}
6536
6537static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds,
6538 enum dsa_tag_protocol proto)
6539{
6540 struct mv88e6xxx_chip *chip = ds->priv;
6541 enum dsa_tag_protocol old_protocol;
6542 struct dsa_port *cpu_dp;
6543 int err;
6544
6545 switch (proto) {
6546 case DSA_TAG_PROTO_EDSA:
6547 switch (chip->info->edsa_support) {
6548 case MV88E6XXX_EDSA_UNSUPPORTED:
6549 return -EPROTONOSUPPORT;
6550 case MV88E6XXX_EDSA_UNDOCUMENTED:
6551 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
6552 fallthrough;
6553 case MV88E6XXX_EDSA_SUPPORTED:
6554 break;
6555 }
6556 break;
6557 case DSA_TAG_PROTO_DSA:
6558 break;
6559 default:
6560 return -EPROTONOSUPPORT;
6561 }
6562
6563 old_protocol = chip->tag_protocol;
6564 chip->tag_protocol = proto;
6565
6566 mv88e6xxx_reg_lock(chip);
6567 dsa_switch_for_each_cpu_port(cpu_dp, ds) {
6568 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6569 if (err) {
6570 mv88e6xxx_reg_unlock(chip);
6571 goto unwind;
6572 }
6573 }
6574 mv88e6xxx_reg_unlock(chip);
6575
6576 return 0;
6577
6578unwind:
6579 chip->tag_protocol = old_protocol;
6580
6581 mv88e6xxx_reg_lock(chip);
6582 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds)
6583 mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6584 mv88e6xxx_reg_unlock(chip);
6585
6586 return err;
6587}
6588
6589static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
6590 const struct switchdev_obj_port_mdb *mdb,
6591 struct dsa_db db)
6592{
6593 struct mv88e6xxx_chip *chip = ds->priv;
6594 int err;
6595
6596 mv88e6xxx_reg_lock(chip);
6597 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
6598 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
6599 mv88e6xxx_reg_unlock(chip);
6600
6601 return err;
6602}
6603
6604static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
6605 const struct switchdev_obj_port_mdb *mdb,
6606 struct dsa_db db)
6607{
6608 struct mv88e6xxx_chip *chip = ds->priv;
6609 int err;
6610
6611 mv88e6xxx_reg_lock(chip);
6612 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
6613 mv88e6xxx_reg_unlock(chip);
6614
6615 return err;
6616}
6617
6618static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
6619 struct dsa_mall_mirror_tc_entry *mirror,
6620 bool ingress,
6621 struct netlink_ext_ack *extack)
6622{
6623 enum mv88e6xxx_egress_direction direction = ingress ?
6624 MV88E6XXX_EGRESS_DIR_INGRESS :
6625 MV88E6XXX_EGRESS_DIR_EGRESS;
6626 struct mv88e6xxx_chip *chip = ds->priv;
6627 bool other_mirrors = false;
6628 int i;
6629 int err;
6630
6631 mutex_lock(&chip->reg_lock);
6632 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
6633 mirror->to_local_port) {
6634 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6635 other_mirrors |= ingress ?
6636 chip->ports[i].mirror_ingress :
6637 chip->ports[i].mirror_egress;
6638
6639 /* Can't change egress port when other mirror is active */
6640 if (other_mirrors) {
6641 err = -EBUSY;
6642 goto out;
6643 }
6644
6645 err = mv88e6xxx_set_egress_port(chip, direction,
6646 mirror->to_local_port);
6647 if (err)
6648 goto out;
6649 }
6650
6651 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
6652out:
6653 mutex_unlock(&chip->reg_lock);
6654
6655 return err;
6656}
6657
6658static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
6659 struct dsa_mall_mirror_tc_entry *mirror)
6660{
6661 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
6662 MV88E6XXX_EGRESS_DIR_INGRESS :
6663 MV88E6XXX_EGRESS_DIR_EGRESS;
6664 struct mv88e6xxx_chip *chip = ds->priv;
6665 bool other_mirrors = false;
6666 int i;
6667
6668 mutex_lock(&chip->reg_lock);
6669 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
6670 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
6671
6672 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6673 other_mirrors |= mirror->ingress ?
6674 chip->ports[i].mirror_ingress :
6675 chip->ports[i].mirror_egress;
6676
6677 /* Reset egress port when no other mirror is active */
6678 if (!other_mirrors) {
6679 if (mv88e6xxx_set_egress_port(chip, direction,
6680 dsa_upstream_port(ds, port)))
6681 dev_err(ds->dev, "failed to set egress port\n");
6682 }
6683
6684 mutex_unlock(&chip->reg_lock);
6685}
6686
6687static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
6688 struct switchdev_brport_flags flags,
6689 struct netlink_ext_ack *extack)
6690{
6691 struct mv88e6xxx_chip *chip = ds->priv;
6692 const struct mv88e6xxx_ops *ops;
6693
6694 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
6695 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB))
6696 return -EINVAL;
6697
6698 ops = chip->info->ops;
6699
6700 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
6701 return -EINVAL;
6702
6703 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
6704 return -EINVAL;
6705
6706 return 0;
6707}
6708
6709static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
6710 struct switchdev_brport_flags flags,
6711 struct netlink_ext_ack *extack)
6712{
6713 struct mv88e6xxx_chip *chip = ds->priv;
6714 int err = 0;
6715
6716 mv88e6xxx_reg_lock(chip);
6717
6718 if (flags.mask & BR_LEARNING) {
6719 bool learning = !!(flags.val & BR_LEARNING);
6720 u16 pav = learning ? (1 << port) : 0;
6721
6722 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
6723 if (err)
6724 goto out;
6725 }
6726
6727 if (flags.mask & BR_FLOOD) {
6728 bool unicast = !!(flags.val & BR_FLOOD);
6729
6730 err = chip->info->ops->port_set_ucast_flood(chip, port,
6731 unicast);
6732 if (err)
6733 goto out;
6734 }
6735
6736 if (flags.mask & BR_MCAST_FLOOD) {
6737 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
6738
6739 err = chip->info->ops->port_set_mcast_flood(chip, port,
6740 multicast);
6741 if (err)
6742 goto out;
6743 }
6744
6745 if (flags.mask & BR_BCAST_FLOOD) {
6746 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
6747
6748 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
6749 if (err)
6750 goto out;
6751 }
6752
6753 if (flags.mask & BR_PORT_MAB) {
6754 bool mab = !!(flags.val & BR_PORT_MAB);
6755
6756 mv88e6xxx_port_set_mab(chip, port, mab);
6757 }
6758
6759 if (flags.mask & BR_PORT_LOCKED) {
6760 bool locked = !!(flags.val & BR_PORT_LOCKED);
6761
6762 err = mv88e6xxx_port_set_lock(chip, port, locked);
6763 if (err)
6764 goto out;
6765 }
6766out:
6767 mv88e6xxx_reg_unlock(chip);
6768
6769 return err;
6770}
6771
6772static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
6773 struct dsa_lag lag,
6774 struct netdev_lag_upper_info *info,
6775 struct netlink_ext_ack *extack)
6776{
6777 struct mv88e6xxx_chip *chip = ds->priv;
6778 struct dsa_port *dp;
6779 int members = 0;
6780
6781 if (!mv88e6xxx_has_lag(chip)) {
6782 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload");
6783 return false;
6784 }
6785
6786 if (!lag.id)
6787 return false;
6788
6789 dsa_lag_foreach_port(dp, ds->dst, &lag)
6790 /* Includes the port joining the LAG */
6791 members++;
6792
6793 if (members > 8) {
6794 NL_SET_ERR_MSG_MOD(extack,
6795 "Cannot offload more than 8 LAG ports");
6796 return false;
6797 }
6798
6799 /* We could potentially relax this to include active
6800 * backup in the future.
6801 */
6802 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
6803 NL_SET_ERR_MSG_MOD(extack,
6804 "Can only offload LAG using hash TX type");
6805 return false;
6806 }
6807
6808 /* Ideally we would also validate that the hash type matches
6809 * the hardware. Alas, this is always set to unknown on team
6810 * interfaces.
6811 */
6812 return true;
6813}
6814
6815static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag)
6816{
6817 struct mv88e6xxx_chip *chip = ds->priv;
6818 struct dsa_port *dp;
6819 u16 map = 0;
6820 int id;
6821
6822 /* DSA LAG IDs are one-based, hardware is zero-based */
6823 id = lag.id - 1;
6824
6825 /* Build the map of all ports to distribute flows destined for
6826 * this LAG. This can be either a local user port, or a DSA
6827 * port if the LAG port is on a remote chip.
6828 */
6829 dsa_lag_foreach_port(dp, ds->dst, &lag)
6830 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
6831
6832 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
6833}
6834
6835static const u8 mv88e6xxx_lag_mask_table[8][8] = {
6836 /* Row number corresponds to the number of active members in a
6837 * LAG. Each column states which of the eight hash buckets are
6838 * mapped to the column:th port in the LAG.
6839 *
6840 * Example: In a LAG with three active ports, the second port
6841 * ([2][1]) would be selected for traffic mapped to buckets
6842 * 3,4,5 (0x38).
6843 */
6844 { 0xff, 0, 0, 0, 0, 0, 0, 0 },
6845 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 },
6846 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 },
6847 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 },
6848 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 },
6849 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 },
6850 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 },
6851 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
6852};
6853
6854static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
6855 int num_tx, int nth)
6856{
6857 u8 active = 0;
6858 int i;
6859
6860 num_tx = num_tx <= 8 ? num_tx : 8;
6861 if (nth < num_tx)
6862 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
6863
6864 for (i = 0; i < 8; i++) {
6865 if (BIT(i) & active)
6866 mask[i] |= BIT(port);
6867 }
6868}
6869
6870static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
6871{
6872 struct mv88e6xxx_chip *chip = ds->priv;
6873 unsigned int id, num_tx;
6874 struct dsa_port *dp;
6875 struct dsa_lag *lag;
6876 int i, err, nth;
6877 u16 mask[8];
6878 u16 ivec;
6879
6880 /* Assume no port is a member of any LAG. */
6881 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
6882
6883 /* Disable all masks for ports that _are_ members of a LAG. */
6884 dsa_switch_for_each_port(dp, ds) {
6885 if (!dp->lag)
6886 continue;
6887
6888 ivec &= ~BIT(dp->index);
6889 }
6890
6891 for (i = 0; i < 8; i++)
6892 mask[i] = ivec;
6893
6894 /* Enable the correct subset of masks for all LAG ports that
6895 * are in the Tx set.
6896 */
6897 dsa_lags_foreach_id(id, ds->dst) {
6898 lag = dsa_lag_by_id(ds->dst, id);
6899 if (!lag)
6900 continue;
6901
6902 num_tx = 0;
6903 dsa_lag_foreach_port(dp, ds->dst, lag) {
6904 if (dp->lag_tx_enabled)
6905 num_tx++;
6906 }
6907
6908 if (!num_tx)
6909 continue;
6910
6911 nth = 0;
6912 dsa_lag_foreach_port(dp, ds->dst, lag) {
6913 if (!dp->lag_tx_enabled)
6914 continue;
6915
6916 if (dp->ds == ds)
6917 mv88e6xxx_lag_set_port_mask(mask, dp->index,
6918 num_tx, nth);
6919
6920 nth++;
6921 }
6922 }
6923
6924 for (i = 0; i < 8; i++) {
6925 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
6926 if (err)
6927 return err;
6928 }
6929
6930 return 0;
6931}
6932
6933static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
6934 struct dsa_lag lag)
6935{
6936 int err;
6937
6938 err = mv88e6xxx_lag_sync_masks(ds);
6939
6940 if (!err)
6941 err = mv88e6xxx_lag_sync_map(ds, lag);
6942
6943 return err;
6944}
6945
6946static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
6947{
6948 struct mv88e6xxx_chip *chip = ds->priv;
6949 int err;
6950
6951 mv88e6xxx_reg_lock(chip);
6952 err = mv88e6xxx_lag_sync_masks(ds);
6953 mv88e6xxx_reg_unlock(chip);
6954 return err;
6955}
6956
6957static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
6958 struct dsa_lag lag,
6959 struct netdev_lag_upper_info *info,
6960 struct netlink_ext_ack *extack)
6961{
6962 struct mv88e6xxx_chip *chip = ds->priv;
6963 int err, id;
6964
6965 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6966 return -EOPNOTSUPP;
6967
6968 /* DSA LAG IDs are one-based */
6969 id = lag.id - 1;
6970
6971 mv88e6xxx_reg_lock(chip);
6972
6973 err = mv88e6xxx_port_set_trunk(chip, port, true, id);
6974 if (err)
6975 goto err_unlock;
6976
6977 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6978 if (err)
6979 goto err_clear_trunk;
6980
6981 mv88e6xxx_reg_unlock(chip);
6982 return 0;
6983
6984err_clear_trunk:
6985 mv88e6xxx_port_set_trunk(chip, port, false, 0);
6986err_unlock:
6987 mv88e6xxx_reg_unlock(chip);
6988 return err;
6989}
6990
6991static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6992 struct dsa_lag lag)
6993{
6994 struct mv88e6xxx_chip *chip = ds->priv;
6995 int err_sync, err_trunk;
6996
6997 mv88e6xxx_reg_lock(chip);
6998 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6999 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
7000 mv88e6xxx_reg_unlock(chip);
7001 return err_sync ? : err_trunk;
7002}
7003
7004static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
7005 int port)
7006{
7007 struct mv88e6xxx_chip *chip = ds->priv;
7008 int err;
7009
7010 mv88e6xxx_reg_lock(chip);
7011 err = mv88e6xxx_lag_sync_masks(ds);
7012 mv88e6xxx_reg_unlock(chip);
7013 return err;
7014}
7015
7016static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
7017 int port, struct dsa_lag lag,
7018 struct netdev_lag_upper_info *info,
7019 struct netlink_ext_ack *extack)
7020{
7021 struct mv88e6xxx_chip *chip = ds->priv;
7022 int err;
7023
7024 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
7025 return -EOPNOTSUPP;
7026
7027 mv88e6xxx_reg_lock(chip);
7028
7029 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
7030 if (err)
7031 goto unlock;
7032
7033 err = mv88e6xxx_pvt_map(chip, sw_index, port);
7034
7035unlock:
7036 mv88e6xxx_reg_unlock(chip);
7037 return err;
7038}
7039
7040static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
7041 int port, struct dsa_lag lag)
7042{
7043 struct mv88e6xxx_chip *chip = ds->priv;
7044 int err_sync, err_pvt;
7045
7046 mv88e6xxx_reg_lock(chip);
7047 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
7048 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
7049 mv88e6xxx_reg_unlock(chip);
7050 return err_sync ? : err_pvt;
7051}
7052
7053static const struct phylink_mac_ops mv88e6xxx_phylink_mac_ops = {
7054 .mac_select_pcs = mv88e6xxx_mac_select_pcs,
7055 .mac_prepare = mv88e6xxx_mac_prepare,
7056 .mac_config = mv88e6xxx_mac_config,
7057 .mac_finish = mv88e6xxx_mac_finish,
7058 .mac_link_down = mv88e6xxx_mac_link_down,
7059 .mac_link_up = mv88e6xxx_mac_link_up,
7060};
7061
7062static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
7063 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
7064 .change_tag_protocol = mv88e6xxx_change_tag_protocol,
7065 .setup = mv88e6xxx_setup,
7066 .teardown = mv88e6xxx_teardown,
7067 .port_setup = mv88e6xxx_port_setup,
7068 .port_teardown = mv88e6xxx_port_teardown,
7069 .phylink_get_caps = mv88e6xxx_get_caps,
7070 .get_strings = mv88e6xxx_get_strings,
7071 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
7072 .get_eth_mac_stats = mv88e6xxx_get_eth_mac_stats,
7073 .get_rmon_stats = mv88e6xxx_get_rmon_stats,
7074 .get_sset_count = mv88e6xxx_get_sset_count,
7075 .port_max_mtu = mv88e6xxx_get_max_mtu,
7076 .port_change_mtu = mv88e6xxx_change_mtu,
7077 .get_mac_eee = mv88e6xxx_get_mac_eee,
7078 .set_mac_eee = mv88e6xxx_set_mac_eee,
7079 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
7080 .get_eeprom = mv88e6xxx_get_eeprom,
7081 .set_eeprom = mv88e6xxx_set_eeprom,
7082 .get_regs_len = mv88e6xxx_get_regs_len,
7083 .get_regs = mv88e6xxx_get_regs,
7084 .get_rxnfc = mv88e6xxx_get_rxnfc,
7085 .set_rxnfc = mv88e6xxx_set_rxnfc,
7086 .set_ageing_time = mv88e6xxx_set_ageing_time,
7087 .port_bridge_join = mv88e6xxx_port_bridge_join,
7088 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
7089 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags,
7090 .port_bridge_flags = mv88e6xxx_port_bridge_flags,
7091 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
7092 .port_mst_state_set = mv88e6xxx_port_mst_state_set,
7093 .port_fast_age = mv88e6xxx_port_fast_age,
7094 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age,
7095 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
7096 .port_vlan_add = mv88e6xxx_port_vlan_add,
7097 .port_vlan_del = mv88e6xxx_port_vlan_del,
7098 .vlan_msti_set = mv88e6xxx_vlan_msti_set,
7099 .port_fdb_add = mv88e6xxx_port_fdb_add,
7100 .port_fdb_del = mv88e6xxx_port_fdb_del,
7101 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7102 .port_mdb_add = mv88e6xxx_port_mdb_add,
7103 .port_mdb_del = mv88e6xxx_port_mdb_del,
7104 .port_mirror_add = mv88e6xxx_port_mirror_add,
7105 .port_mirror_del = mv88e6xxx_port_mirror_del,
7106 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
7107 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
7108 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
7109 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
7110 .port_txtstamp = mv88e6xxx_port_txtstamp,
7111 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
7112 .get_ts_info = mv88e6xxx_get_ts_info,
7113 .devlink_param_get = mv88e6xxx_devlink_param_get,
7114 .devlink_param_set = mv88e6xxx_devlink_param_set,
7115 .devlink_info_get = mv88e6xxx_devlink_info_get,
7116 .port_lag_change = mv88e6xxx_port_lag_change,
7117 .port_lag_join = mv88e6xxx_port_lag_join,
7118 .port_lag_leave = mv88e6xxx_port_lag_leave,
7119 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change,
7120 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join,
7121 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave,
7122};
7123
7124static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
7125{
7126 struct device *dev = chip->dev;
7127 struct dsa_switch *ds;
7128
7129 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
7130 if (!ds)
7131 return -ENOMEM;
7132
7133 ds->dev = dev;
7134 ds->num_ports = mv88e6xxx_num_ports(chip);
7135 ds->priv = chip;
7136 ds->dev = dev;
7137 ds->ops = &mv88e6xxx_switch_ops;
7138 ds->phylink_mac_ops = &mv88e6xxx_phylink_mac_ops;
7139 ds->ageing_time_min = chip->info->age_time_coeff;
7140 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
7141
7142 /* Some chips support up to 32, but that requires enabling the
7143 * 5-bit port mode, which we do not support. 640k^W16 ought to
7144 * be enough for anyone.
7145 */
7146 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
7147
7148 dev_set_drvdata(dev, ds);
7149
7150 return dsa_register_switch(ds);
7151}
7152
7153static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
7154{
7155 dsa_unregister_switch(chip->ds);
7156}
7157
7158static const void *pdata_device_get_match_data(struct device *dev)
7159{
7160 const struct of_device_id *matches = dev->driver->of_match_table;
7161 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
7162
7163 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
7164 matches++) {
7165 if (!strcmp(pdata->compatible, matches->compatible))
7166 return matches->data;
7167 }
7168 return NULL;
7169}
7170
7171/* There is no suspend to RAM support at DSA level yet, the switch configuration
7172 * would be lost after a power cycle so prevent it to be suspended.
7173 */
7174static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
7175{
7176 return -EOPNOTSUPP;
7177}
7178
7179static int __maybe_unused mv88e6xxx_resume(struct device *dev)
7180{
7181 return 0;
7182}
7183
7184static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
7185
7186static int mv88e6xxx_probe(struct mdio_device *mdiodev)
7187{
7188 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
7189 const struct mv88e6xxx_info *compat_info = NULL;
7190 struct device *dev = &mdiodev->dev;
7191 struct device_node *np = dev->of_node;
7192 struct mv88e6xxx_chip *chip;
7193 int port;
7194 int err;
7195
7196 if (!np && !pdata)
7197 return -EINVAL;
7198
7199 if (np)
7200 compat_info = of_device_get_match_data(dev);
7201
7202 if (pdata) {
7203 compat_info = pdata_device_get_match_data(dev);
7204
7205 if (!pdata->netdev)
7206 return -EINVAL;
7207
7208 for (port = 0; port < DSA_MAX_PORTS; port++) {
7209 if (!(pdata->enabled_ports & (1 << port)))
7210 continue;
7211 if (strcmp(pdata->cd.port_names[port], "cpu"))
7212 continue;
7213 pdata->cd.netdev[port] = &pdata->netdev->dev;
7214 break;
7215 }
7216 }
7217
7218 if (!compat_info)
7219 return -EINVAL;
7220
7221 chip = mv88e6xxx_alloc_chip(dev);
7222 if (!chip) {
7223 err = -ENOMEM;
7224 goto out;
7225 }
7226
7227 chip->info = compat_info;
7228
7229 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
7230 if (IS_ERR(chip->reset)) {
7231 err = PTR_ERR(chip->reset);
7232 goto out;
7233 }
7234 if (chip->reset)
7235 usleep_range(10000, 20000);
7236
7237 /* Detect if the device is configured in single chip addressing mode,
7238 * otherwise continue with address specific smi init/detection.
7239 */
7240 err = mv88e6xxx_single_chip_detect(chip, mdiodev);
7241 if (err) {
7242 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
7243 if (err)
7244 goto out;
7245
7246 err = mv88e6xxx_detect(chip);
7247 if (err)
7248 goto out;
7249 }
7250
7251 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
7252 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
7253 else
7254 chip->tag_protocol = DSA_TAG_PROTO_DSA;
7255
7256 mv88e6xxx_phy_init(chip);
7257
7258 if (chip->info->ops->get_eeprom) {
7259 if (np)
7260 of_property_read_u32(np, "eeprom-length",
7261 &chip->eeprom_len);
7262 else
7263 chip->eeprom_len = pdata->eeprom_len;
7264 }
7265
7266 mv88e6xxx_reg_lock(chip);
7267 err = mv88e6xxx_switch_reset(chip);
7268 mv88e6xxx_reg_unlock(chip);
7269 if (err)
7270 goto out;
7271
7272 if (np) {
7273 chip->irq = of_irq_get(np, 0);
7274 if (chip->irq == -EPROBE_DEFER) {
7275 err = chip->irq;
7276 goto out;
7277 }
7278 }
7279
7280 if (pdata)
7281 chip->irq = pdata->irq;
7282
7283 /* Has to be performed before the MDIO bus is created, because
7284 * the PHYs will link their interrupts to these interrupt
7285 * controllers
7286 */
7287 mv88e6xxx_reg_lock(chip);
7288 if (chip->irq > 0)
7289 err = mv88e6xxx_g1_irq_setup(chip);
7290 else
7291 err = mv88e6xxx_irq_poll_setup(chip);
7292 mv88e6xxx_reg_unlock(chip);
7293
7294 if (err)
7295 goto out;
7296
7297 if (chip->info->g2_irqs > 0) {
7298 err = mv88e6xxx_g2_irq_setup(chip);
7299 if (err)
7300 goto out_g1_irq;
7301 }
7302
7303 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
7304 if (err)
7305 goto out_g2_irq;
7306
7307 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
7308 if (err)
7309 goto out_g1_atu_prob_irq;
7310
7311 err = mv88e6xxx_register_switch(chip);
7312 if (err)
7313 goto out_g1_vtu_prob_irq;
7314
7315 return 0;
7316
7317out_g1_vtu_prob_irq:
7318 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7319out_g1_atu_prob_irq:
7320 mv88e6xxx_g1_atu_prob_irq_free(chip);
7321out_g2_irq:
7322 if (chip->info->g2_irqs > 0)
7323 mv88e6xxx_g2_irq_free(chip);
7324out_g1_irq:
7325 if (chip->irq > 0)
7326 mv88e6xxx_g1_irq_free(chip);
7327 else
7328 mv88e6xxx_irq_poll_free(chip);
7329out:
7330 if (pdata)
7331 dev_put(pdata->netdev);
7332
7333 return err;
7334}
7335
7336static void mv88e6xxx_remove(struct mdio_device *mdiodev)
7337{
7338 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7339 struct mv88e6xxx_chip *chip;
7340
7341 if (!ds)
7342 return;
7343
7344 chip = ds->priv;
7345
7346 if (chip->info->ptp_support) {
7347 mv88e6xxx_hwtstamp_free(chip);
7348 mv88e6xxx_ptp_free(chip);
7349 }
7350
7351 mv88e6xxx_phy_destroy(chip);
7352 mv88e6xxx_unregister_switch(chip);
7353
7354 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7355 mv88e6xxx_g1_atu_prob_irq_free(chip);
7356
7357 if (chip->info->g2_irqs > 0)
7358 mv88e6xxx_g2_irq_free(chip);
7359
7360 if (chip->irq > 0)
7361 mv88e6xxx_g1_irq_free(chip);
7362 else
7363 mv88e6xxx_irq_poll_free(chip);
7364}
7365
7366static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
7367{
7368 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7369
7370 if (!ds)
7371 return;
7372
7373 dsa_switch_shutdown(ds);
7374
7375 dev_set_drvdata(&mdiodev->dev, NULL);
7376}
7377
7378static const struct of_device_id mv88e6xxx_of_match[] = {
7379 {
7380 .compatible = "marvell,mv88e6085",
7381 .data = &mv88e6xxx_table[MV88E6085],
7382 },
7383 {
7384 .compatible = "marvell,mv88e6190",
7385 .data = &mv88e6xxx_table[MV88E6190],
7386 },
7387 {
7388 .compatible = "marvell,mv88e6250",
7389 .data = &mv88e6xxx_table[MV88E6250],
7390 },
7391 { /* sentinel */ },
7392};
7393
7394MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
7395
7396static struct mdio_driver mv88e6xxx_driver = {
7397 .probe = mv88e6xxx_probe,
7398 .remove = mv88e6xxx_remove,
7399 .shutdown = mv88e6xxx_shutdown,
7400 .mdiodrv.driver = {
7401 .name = "mv88e6085",
7402 .of_match_table = mv88e6xxx_of_match,
7403 .pm = &mv88e6xxx_pm_ops,
7404 },
7405};
7406
7407mdio_module_driver(mv88e6xxx_driver);
7408
7409MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
7410MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
7411MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 *
9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 */
12
13#include <linux/bitfield.h>
14#include <linux/delay.h>
15#include <linux/etherdevice.h>
16#include <linux/ethtool.h>
17#include <linux/if_bridge.h>
18#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/irqdomain.h>
21#include <linux/jiffies.h>
22#include <linux/list.h>
23#include <linux/mdio.h>
24#include <linux/module.h>
25#include <linux/of_device.h>
26#include <linux/of_irq.h>
27#include <linux/of_mdio.h>
28#include <linux/platform_data/mv88e6xxx.h>
29#include <linux/netdevice.h>
30#include <linux/gpio/consumer.h>
31#include <linux/phylink.h>
32#include <net/dsa.h>
33
34#include "chip.h"
35#include "devlink.h"
36#include "global1.h"
37#include "global2.h"
38#include "hwtstamp.h"
39#include "phy.h"
40#include "port.h"
41#include "ptp.h"
42#include "serdes.h"
43#include "smi.h"
44
45static void assert_reg_lock(struct mv88e6xxx_chip *chip)
46{
47 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
48 dev_err(chip->dev, "Switch registers lock not held!\n");
49 dump_stack();
50 }
51}
52
53int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
54{
55 int err;
56
57 assert_reg_lock(chip);
58
59 err = mv88e6xxx_smi_read(chip, addr, reg, val);
60 if (err)
61 return err;
62
63 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
64 addr, reg, *val);
65
66 return 0;
67}
68
69int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
70{
71 int err;
72
73 assert_reg_lock(chip);
74
75 err = mv88e6xxx_smi_write(chip, addr, reg, val);
76 if (err)
77 return err;
78
79 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
80 addr, reg, val);
81
82 return 0;
83}
84
85int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
86 u16 mask, u16 val)
87{
88 u16 data;
89 int err;
90 int i;
91
92 /* There's no bus specific operation to wait for a mask */
93 for (i = 0; i < 16; i++) {
94 err = mv88e6xxx_read(chip, addr, reg, &data);
95 if (err)
96 return err;
97
98 if ((data & mask) == val)
99 return 0;
100
101 usleep_range(1000, 2000);
102 }
103
104 dev_err(chip->dev, "Timeout while waiting for switch\n");
105 return -ETIMEDOUT;
106}
107
108int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
109 int bit, int val)
110{
111 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
112 val ? BIT(bit) : 0x0000);
113}
114
115struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
116{
117 struct mv88e6xxx_mdio_bus *mdio_bus;
118
119 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
120 list);
121 if (!mdio_bus)
122 return NULL;
123
124 return mdio_bus->bus;
125}
126
127static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
128{
129 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
130 unsigned int n = d->hwirq;
131
132 chip->g1_irq.masked |= (1 << n);
133}
134
135static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
136{
137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
138 unsigned int n = d->hwirq;
139
140 chip->g1_irq.masked &= ~(1 << n);
141}
142
143static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
144{
145 unsigned int nhandled = 0;
146 unsigned int sub_irq;
147 unsigned int n;
148 u16 reg;
149 u16 ctl1;
150 int err;
151
152 mv88e6xxx_reg_lock(chip);
153 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
154 mv88e6xxx_reg_unlock(chip);
155
156 if (err)
157 goto out;
158
159 do {
160 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
161 if (reg & (1 << n)) {
162 sub_irq = irq_find_mapping(chip->g1_irq.domain,
163 n);
164 handle_nested_irq(sub_irq);
165 ++nhandled;
166 }
167 }
168
169 mv88e6xxx_reg_lock(chip);
170 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
171 if (err)
172 goto unlock;
173 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
174unlock:
175 mv88e6xxx_reg_unlock(chip);
176 if (err)
177 goto out;
178 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
179 } while (reg & ctl1);
180
181out:
182 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
183}
184
185static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
186{
187 struct mv88e6xxx_chip *chip = dev_id;
188
189 return mv88e6xxx_g1_irq_thread_work(chip);
190}
191
192static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
193{
194 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
195
196 mv88e6xxx_reg_lock(chip);
197}
198
199static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
200{
201 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
202 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
203 u16 reg;
204 int err;
205
206 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
207 if (err)
208 goto out;
209
210 reg &= ~mask;
211 reg |= (~chip->g1_irq.masked & mask);
212
213 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
214 if (err)
215 goto out;
216
217out:
218 mv88e6xxx_reg_unlock(chip);
219}
220
221static const struct irq_chip mv88e6xxx_g1_irq_chip = {
222 .name = "mv88e6xxx-g1",
223 .irq_mask = mv88e6xxx_g1_irq_mask,
224 .irq_unmask = mv88e6xxx_g1_irq_unmask,
225 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
226 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
227};
228
229static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
230 unsigned int irq,
231 irq_hw_number_t hwirq)
232{
233 struct mv88e6xxx_chip *chip = d->host_data;
234
235 irq_set_chip_data(irq, d->host_data);
236 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
237 irq_set_noprobe(irq);
238
239 return 0;
240}
241
242static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
243 .map = mv88e6xxx_g1_irq_domain_map,
244 .xlate = irq_domain_xlate_twocell,
245};
246
247/* To be called with reg_lock held */
248static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
249{
250 int irq, virq;
251 u16 mask;
252
253 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
254 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
255 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
256
257 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
258 virq = irq_find_mapping(chip->g1_irq.domain, irq);
259 irq_dispose_mapping(virq);
260 }
261
262 irq_domain_remove(chip->g1_irq.domain);
263}
264
265static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
266{
267 /*
268 * free_irq must be called without reg_lock taken because the irq
269 * handler takes this lock, too.
270 */
271 free_irq(chip->irq, chip);
272
273 mv88e6xxx_reg_lock(chip);
274 mv88e6xxx_g1_irq_free_common(chip);
275 mv88e6xxx_reg_unlock(chip);
276}
277
278static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
279{
280 int err, irq, virq;
281 u16 reg, mask;
282
283 chip->g1_irq.nirqs = chip->info->g1_irqs;
284 chip->g1_irq.domain = irq_domain_add_simple(
285 NULL, chip->g1_irq.nirqs, 0,
286 &mv88e6xxx_g1_irq_domain_ops, chip);
287 if (!chip->g1_irq.domain)
288 return -ENOMEM;
289
290 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
291 irq_create_mapping(chip->g1_irq.domain, irq);
292
293 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
294 chip->g1_irq.masked = ~0;
295
296 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
297 if (err)
298 goto out_mapping;
299
300 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
301
302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
303 if (err)
304 goto out_disable;
305
306 /* Reading the interrupt status clears (most of) them */
307 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
308 if (err)
309 goto out_disable;
310
311 return 0;
312
313out_disable:
314 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
315 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
316
317out_mapping:
318 for (irq = 0; irq < 16; irq++) {
319 virq = irq_find_mapping(chip->g1_irq.domain, irq);
320 irq_dispose_mapping(virq);
321 }
322
323 irq_domain_remove(chip->g1_irq.domain);
324
325 return err;
326}
327
328static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
329{
330 static struct lock_class_key lock_key;
331 static struct lock_class_key request_key;
332 int err;
333
334 err = mv88e6xxx_g1_irq_setup_common(chip);
335 if (err)
336 return err;
337
338 /* These lock classes tells lockdep that global 1 irqs are in
339 * a different category than their parent GPIO, so it won't
340 * report false recursion.
341 */
342 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
343
344 snprintf(chip->irq_name, sizeof(chip->irq_name),
345 "mv88e6xxx-%s", dev_name(chip->dev));
346
347 mv88e6xxx_reg_unlock(chip);
348 err = request_threaded_irq(chip->irq, NULL,
349 mv88e6xxx_g1_irq_thread_fn,
350 IRQF_ONESHOT | IRQF_SHARED,
351 chip->irq_name, chip);
352 mv88e6xxx_reg_lock(chip);
353 if (err)
354 mv88e6xxx_g1_irq_free_common(chip);
355
356 return err;
357}
358
359static void mv88e6xxx_irq_poll(struct kthread_work *work)
360{
361 struct mv88e6xxx_chip *chip = container_of(work,
362 struct mv88e6xxx_chip,
363 irq_poll_work.work);
364 mv88e6xxx_g1_irq_thread_work(chip);
365
366 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
367 msecs_to_jiffies(100));
368}
369
370static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
371{
372 int err;
373
374 err = mv88e6xxx_g1_irq_setup_common(chip);
375 if (err)
376 return err;
377
378 kthread_init_delayed_work(&chip->irq_poll_work,
379 mv88e6xxx_irq_poll);
380
381 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
382 if (IS_ERR(chip->kworker))
383 return PTR_ERR(chip->kworker);
384
385 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
386 msecs_to_jiffies(100));
387
388 return 0;
389}
390
391static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
392{
393 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
394 kthread_destroy_worker(chip->kworker);
395
396 mv88e6xxx_reg_lock(chip);
397 mv88e6xxx_g1_irq_free_common(chip);
398 mv88e6xxx_reg_unlock(chip);
399}
400
401static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
402 int port, phy_interface_t interface)
403{
404 int err;
405
406 if (chip->info->ops->port_set_rgmii_delay) {
407 err = chip->info->ops->port_set_rgmii_delay(chip, port,
408 interface);
409 if (err && err != -EOPNOTSUPP)
410 return err;
411 }
412
413 if (chip->info->ops->port_set_cmode) {
414 err = chip->info->ops->port_set_cmode(chip, port,
415 interface);
416 if (err && err != -EOPNOTSUPP)
417 return err;
418 }
419
420 return 0;
421}
422
423static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
424 int link, int speed, int duplex, int pause,
425 phy_interface_t mode)
426{
427 int err;
428
429 if (!chip->info->ops->port_set_link)
430 return 0;
431
432 /* Port's MAC control must not be changed unless the link is down */
433 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
434 if (err)
435 return err;
436
437 if (chip->info->ops->port_set_speed_duplex) {
438 err = chip->info->ops->port_set_speed_duplex(chip, port,
439 speed, duplex);
440 if (err && err != -EOPNOTSUPP)
441 goto restore_link;
442 }
443
444 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
445 mode = chip->info->ops->port_max_speed_mode(port);
446
447 if (chip->info->ops->port_set_pause) {
448 err = chip->info->ops->port_set_pause(chip, port, pause);
449 if (err)
450 goto restore_link;
451 }
452
453 err = mv88e6xxx_port_config_interface(chip, port, mode);
454restore_link:
455 if (chip->info->ops->port_set_link(chip, port, link))
456 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
457
458 return err;
459}
460
461static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
462{
463 struct mv88e6xxx_chip *chip = ds->priv;
464
465 return port < chip->info->num_internal_phys;
466}
467
468static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
469{
470 u16 reg;
471 int err;
472
473 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
474 if (err) {
475 dev_err(chip->dev,
476 "p%d: %s: failed to read port status\n",
477 port, __func__);
478 return err;
479 }
480
481 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
482}
483
484static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
485 struct phylink_link_state *state)
486{
487 struct mv88e6xxx_chip *chip = ds->priv;
488 int lane;
489 int err;
490
491 mv88e6xxx_reg_lock(chip);
492 lane = mv88e6xxx_serdes_get_lane(chip, port);
493 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state)
494 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
495 state);
496 else
497 err = -EOPNOTSUPP;
498 mv88e6xxx_reg_unlock(chip);
499
500 return err;
501}
502
503static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
504 unsigned int mode,
505 phy_interface_t interface,
506 const unsigned long *advertise)
507{
508 const struct mv88e6xxx_ops *ops = chip->info->ops;
509 int lane;
510
511 if (ops->serdes_pcs_config) {
512 lane = mv88e6xxx_serdes_get_lane(chip, port);
513 if (lane >= 0)
514 return ops->serdes_pcs_config(chip, port, lane, mode,
515 interface, advertise);
516 }
517
518 return 0;
519}
520
521static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
522{
523 struct mv88e6xxx_chip *chip = ds->priv;
524 const struct mv88e6xxx_ops *ops;
525 int err = 0;
526 int lane;
527
528 ops = chip->info->ops;
529
530 if (ops->serdes_pcs_an_restart) {
531 mv88e6xxx_reg_lock(chip);
532 lane = mv88e6xxx_serdes_get_lane(chip, port);
533 if (lane >= 0)
534 err = ops->serdes_pcs_an_restart(chip, port, lane);
535 mv88e6xxx_reg_unlock(chip);
536
537 if (err)
538 dev_err(ds->dev, "p%d: failed to restart AN\n", port);
539 }
540}
541
542static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
543 unsigned int mode,
544 int speed, int duplex)
545{
546 const struct mv88e6xxx_ops *ops = chip->info->ops;
547 int lane;
548
549 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
550 lane = mv88e6xxx_serdes_get_lane(chip, port);
551 if (lane >= 0)
552 return ops->serdes_pcs_link_up(chip, port, lane,
553 speed, duplex);
554 }
555
556 return 0;
557}
558
559static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
560 unsigned long *mask,
561 struct phylink_link_state *state)
562{
563 if (!phy_interface_mode_is_8023z(state->interface)) {
564 /* 10M and 100M are only supported in non-802.3z mode */
565 phylink_set(mask, 10baseT_Half);
566 phylink_set(mask, 10baseT_Full);
567 phylink_set(mask, 100baseT_Half);
568 phylink_set(mask, 100baseT_Full);
569 }
570}
571
572static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
573 unsigned long *mask,
574 struct phylink_link_state *state)
575{
576 /* FIXME: if the port is in 1000Base-X mode, then it only supports
577 * 1000M FD speeds. In this case, CMODE will indicate 5.
578 */
579 phylink_set(mask, 1000baseT_Full);
580 phylink_set(mask, 1000baseX_Full);
581
582 mv88e6065_phylink_validate(chip, port, mask, state);
583}
584
585static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
586 unsigned long *mask,
587 struct phylink_link_state *state)
588{
589 if (port >= 5)
590 phylink_set(mask, 2500baseX_Full);
591
592 /* No ethtool bits for 200Mbps */
593 phylink_set(mask, 1000baseT_Full);
594 phylink_set(mask, 1000baseX_Full);
595
596 mv88e6065_phylink_validate(chip, port, mask, state);
597}
598
599static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
600 unsigned long *mask,
601 struct phylink_link_state *state)
602{
603 /* No ethtool bits for 200Mbps */
604 phylink_set(mask, 1000baseT_Full);
605 phylink_set(mask, 1000baseX_Full);
606
607 mv88e6065_phylink_validate(chip, port, mask, state);
608}
609
610static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
611 unsigned long *mask,
612 struct phylink_link_state *state)
613{
614 if (port >= 9) {
615 phylink_set(mask, 2500baseX_Full);
616 phylink_set(mask, 2500baseT_Full);
617 }
618
619 /* No ethtool bits for 200Mbps */
620 phylink_set(mask, 1000baseT_Full);
621 phylink_set(mask, 1000baseX_Full);
622
623 mv88e6065_phylink_validate(chip, port, mask, state);
624}
625
626static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
627 unsigned long *mask,
628 struct phylink_link_state *state)
629{
630 if (port >= 9) {
631 phylink_set(mask, 10000baseT_Full);
632 phylink_set(mask, 10000baseKR_Full);
633 }
634
635 mv88e6390_phylink_validate(chip, port, mask, state);
636}
637
638static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
639 unsigned long *mask,
640 struct phylink_link_state *state)
641{
642 if (port == 0 || port == 9 || port == 10) {
643 phylink_set(mask, 10000baseT_Full);
644 phylink_set(mask, 10000baseKR_Full);
645 phylink_set(mask, 10000baseCR_Full);
646 phylink_set(mask, 10000baseSR_Full);
647 phylink_set(mask, 10000baseLR_Full);
648 phylink_set(mask, 10000baseLRM_Full);
649 phylink_set(mask, 10000baseER_Full);
650 phylink_set(mask, 5000baseT_Full);
651 phylink_set(mask, 2500baseX_Full);
652 phylink_set(mask, 2500baseT_Full);
653 }
654
655 phylink_set(mask, 1000baseT_Full);
656 phylink_set(mask, 1000baseX_Full);
657
658 mv88e6065_phylink_validate(chip, port, mask, state);
659}
660
661static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
662 unsigned long *supported,
663 struct phylink_link_state *state)
664{
665 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
666 struct mv88e6xxx_chip *chip = ds->priv;
667
668 /* Allow all the expected bits */
669 phylink_set(mask, Autoneg);
670 phylink_set(mask, Pause);
671 phylink_set_port_modes(mask);
672
673 if (chip->info->ops->phylink_validate)
674 chip->info->ops->phylink_validate(chip, port, mask, state);
675
676 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
677 bitmap_and(state->advertising, state->advertising, mask,
678 __ETHTOOL_LINK_MODE_MASK_NBITS);
679
680 /* We can only operate at 2500BaseX or 1000BaseX. If requested
681 * to advertise both, only report advertising at 2500BaseX.
682 */
683 phylink_helper_basex_speed(state);
684}
685
686static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
687 unsigned int mode,
688 const struct phylink_link_state *state)
689{
690 struct mv88e6xxx_chip *chip = ds->priv;
691 struct mv88e6xxx_port *p;
692 int err;
693
694 p = &chip->ports[port];
695
696 /* FIXME: is this the correct test? If we're in fixed mode on an
697 * internal port, why should we process this any different from
698 * PHY mode? On the other hand, the port may be automedia between
699 * an internal PHY and the serdes...
700 */
701 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port))
702 return;
703
704 mv88e6xxx_reg_lock(chip);
705 /* In inband mode, the link may come up at any time while the link
706 * is not forced down. Force the link down while we reconfigure the
707 * interface mode.
708 */
709 if (mode == MLO_AN_INBAND && p->interface != state->interface &&
710 chip->info->ops->port_set_link)
711 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
712
713 err = mv88e6xxx_port_config_interface(chip, port, state->interface);
714 if (err && err != -EOPNOTSUPP)
715 goto err_unlock;
716
717 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface,
718 state->advertising);
719 /* FIXME: we should restart negotiation if something changed - which
720 * is something we get if we convert to using phylinks PCS operations.
721 */
722 if (err > 0)
723 err = 0;
724
725 /* Undo the forced down state above after completing configuration
726 * irrespective of its state on entry, which allows the link to come up.
727 */
728 if (mode == MLO_AN_INBAND && p->interface != state->interface &&
729 chip->info->ops->port_set_link)
730 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
731
732 p->interface = state->interface;
733
734err_unlock:
735 mv88e6xxx_reg_unlock(chip);
736
737 if (err && err != -EOPNOTSUPP)
738 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
739}
740
741static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
742 unsigned int mode,
743 phy_interface_t interface)
744{
745 struct mv88e6xxx_chip *chip = ds->priv;
746 const struct mv88e6xxx_ops *ops;
747 int err = 0;
748
749 ops = chip->info->ops;
750
751 mv88e6xxx_reg_lock(chip);
752 /* Internal PHYs propagate their configuration directly to the MAC.
753 * External PHYs depend on whether the PPU is enabled for this port.
754 */
755 if (((!mv88e6xxx_phy_is_internal(ds, port) &&
756 !mv88e6xxx_port_ppu_updates(chip, port)) ||
757 mode == MLO_AN_FIXED) && ops->port_sync_link)
758 err = ops->port_sync_link(chip, port, mode, false);
759 mv88e6xxx_reg_unlock(chip);
760
761 if (err)
762 dev_err(chip->dev,
763 "p%d: failed to force MAC link down\n", port);
764}
765
766static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
767 unsigned int mode, phy_interface_t interface,
768 struct phy_device *phydev,
769 int speed, int duplex,
770 bool tx_pause, bool rx_pause)
771{
772 struct mv88e6xxx_chip *chip = ds->priv;
773 const struct mv88e6xxx_ops *ops;
774 int err = 0;
775
776 ops = chip->info->ops;
777
778 mv88e6xxx_reg_lock(chip);
779 /* Internal PHYs propagate their configuration directly to the MAC.
780 * External PHYs depend on whether the PPU is enabled for this port.
781 */
782 if ((!mv88e6xxx_phy_is_internal(ds, port) &&
783 !mv88e6xxx_port_ppu_updates(chip, port)) ||
784 mode == MLO_AN_FIXED) {
785 /* FIXME: for an automedia port, should we force the link
786 * down here - what if the link comes up due to "other" media
787 * while we're bringing the port up, how is the exclusivity
788 * handled in the Marvell hardware? E.g. port 2 on 88E6390
789 * shared between internal PHY and Serdes.
790 */
791 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
792 duplex);
793 if (err)
794 goto error;
795
796 if (ops->port_set_speed_duplex) {
797 err = ops->port_set_speed_duplex(chip, port,
798 speed, duplex);
799 if (err && err != -EOPNOTSUPP)
800 goto error;
801 }
802
803 if (ops->port_sync_link)
804 err = ops->port_sync_link(chip, port, mode, true);
805 }
806error:
807 mv88e6xxx_reg_unlock(chip);
808
809 if (err && err != -EOPNOTSUPP)
810 dev_err(ds->dev,
811 "p%d: failed to configure MAC link up\n", port);
812}
813
814static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
815{
816 if (!chip->info->ops->stats_snapshot)
817 return -EOPNOTSUPP;
818
819 return chip->info->ops->stats_snapshot(chip, port);
820}
821
822static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
823 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
824 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
825 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
826 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
827 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
828 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
829 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
830 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
831 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
832 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
833 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
834 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
835 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
836 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
837 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
838 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
839 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
840 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
841 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
842 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
843 { "single", 4, 0x14, STATS_TYPE_BANK0, },
844 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
845 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
846 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
847 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
848 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
849 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
850 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
851 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
852 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
853 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
854 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
855 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
856 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
857 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
858 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
859 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
860 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
861 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
862 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
863 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
864 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
865 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
866 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
867 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
868 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
869 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
870 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
871 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
872 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
873 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
874 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
875 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
876 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
877 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
878 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
879 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
880 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
881 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
882};
883
884static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
885 struct mv88e6xxx_hw_stat *s,
886 int port, u16 bank1_select,
887 u16 histogram)
888{
889 u32 low;
890 u32 high = 0;
891 u16 reg = 0;
892 int err;
893 u64 value;
894
895 switch (s->type) {
896 case STATS_TYPE_PORT:
897 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
898 if (err)
899 return U64_MAX;
900
901 low = reg;
902 if (s->size == 4) {
903 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
904 if (err)
905 return U64_MAX;
906 low |= ((u32)reg) << 16;
907 }
908 break;
909 case STATS_TYPE_BANK1:
910 reg = bank1_select;
911 fallthrough;
912 case STATS_TYPE_BANK0:
913 reg |= s->reg | histogram;
914 mv88e6xxx_g1_stats_read(chip, reg, &low);
915 if (s->size == 8)
916 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
917 break;
918 default:
919 return U64_MAX;
920 }
921 value = (((u64)high) << 32) | low;
922 return value;
923}
924
925static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
926 uint8_t *data, int types)
927{
928 struct mv88e6xxx_hw_stat *stat;
929 int i, j;
930
931 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
932 stat = &mv88e6xxx_hw_stats[i];
933 if (stat->type & types) {
934 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
935 ETH_GSTRING_LEN);
936 j++;
937 }
938 }
939
940 return j;
941}
942
943static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
944 uint8_t *data)
945{
946 return mv88e6xxx_stats_get_strings(chip, data,
947 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
948}
949
950static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
951 uint8_t *data)
952{
953 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
954}
955
956static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
957 uint8_t *data)
958{
959 return mv88e6xxx_stats_get_strings(chip, data,
960 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
961}
962
963static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
964 "atu_member_violation",
965 "atu_miss_violation",
966 "atu_full_violation",
967 "vtu_member_violation",
968 "vtu_miss_violation",
969};
970
971static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
972{
973 unsigned int i;
974
975 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
976 strlcpy(data + i * ETH_GSTRING_LEN,
977 mv88e6xxx_atu_vtu_stats_strings[i],
978 ETH_GSTRING_LEN);
979}
980
981static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
982 u32 stringset, uint8_t *data)
983{
984 struct mv88e6xxx_chip *chip = ds->priv;
985 int count = 0;
986
987 if (stringset != ETH_SS_STATS)
988 return;
989
990 mv88e6xxx_reg_lock(chip);
991
992 if (chip->info->ops->stats_get_strings)
993 count = chip->info->ops->stats_get_strings(chip, data);
994
995 if (chip->info->ops->serdes_get_strings) {
996 data += count * ETH_GSTRING_LEN;
997 count = chip->info->ops->serdes_get_strings(chip, port, data);
998 }
999
1000 data += count * ETH_GSTRING_LEN;
1001 mv88e6xxx_atu_vtu_get_strings(data);
1002
1003 mv88e6xxx_reg_unlock(chip);
1004}
1005
1006static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1007 int types)
1008{
1009 struct mv88e6xxx_hw_stat *stat;
1010 int i, j;
1011
1012 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1013 stat = &mv88e6xxx_hw_stats[i];
1014 if (stat->type & types)
1015 j++;
1016 }
1017 return j;
1018}
1019
1020static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1021{
1022 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1023 STATS_TYPE_PORT);
1024}
1025
1026static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1027{
1028 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1029}
1030
1031static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1032{
1033 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1034 STATS_TYPE_BANK1);
1035}
1036
1037static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1038{
1039 struct mv88e6xxx_chip *chip = ds->priv;
1040 int serdes_count = 0;
1041 int count = 0;
1042
1043 if (sset != ETH_SS_STATS)
1044 return 0;
1045
1046 mv88e6xxx_reg_lock(chip);
1047 if (chip->info->ops->stats_get_sset_count)
1048 count = chip->info->ops->stats_get_sset_count(chip);
1049 if (count < 0)
1050 goto out;
1051
1052 if (chip->info->ops->serdes_get_sset_count)
1053 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1054 port);
1055 if (serdes_count < 0) {
1056 count = serdes_count;
1057 goto out;
1058 }
1059 count += serdes_count;
1060 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1061
1062out:
1063 mv88e6xxx_reg_unlock(chip);
1064
1065 return count;
1066}
1067
1068static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1069 uint64_t *data, int types,
1070 u16 bank1_select, u16 histogram)
1071{
1072 struct mv88e6xxx_hw_stat *stat;
1073 int i, j;
1074
1075 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1076 stat = &mv88e6xxx_hw_stats[i];
1077 if (stat->type & types) {
1078 mv88e6xxx_reg_lock(chip);
1079 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1080 bank1_select,
1081 histogram);
1082 mv88e6xxx_reg_unlock(chip);
1083
1084 j++;
1085 }
1086 }
1087 return j;
1088}
1089
1090static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1091 uint64_t *data)
1092{
1093 return mv88e6xxx_stats_get_stats(chip, port, data,
1094 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1095 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1096}
1097
1098static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1099 uint64_t *data)
1100{
1101 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1102 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1103}
1104
1105static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1106 uint64_t *data)
1107{
1108 return mv88e6xxx_stats_get_stats(chip, port, data,
1109 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1110 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1111 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1112}
1113
1114static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1115 uint64_t *data)
1116{
1117 return mv88e6xxx_stats_get_stats(chip, port, data,
1118 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1119 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1120 0);
1121}
1122
1123static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1124 uint64_t *data)
1125{
1126 *data++ = chip->ports[port].atu_member_violation;
1127 *data++ = chip->ports[port].atu_miss_violation;
1128 *data++ = chip->ports[port].atu_full_violation;
1129 *data++ = chip->ports[port].vtu_member_violation;
1130 *data++ = chip->ports[port].vtu_miss_violation;
1131}
1132
1133static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1134 uint64_t *data)
1135{
1136 int count = 0;
1137
1138 if (chip->info->ops->stats_get_stats)
1139 count = chip->info->ops->stats_get_stats(chip, port, data);
1140
1141 mv88e6xxx_reg_lock(chip);
1142 if (chip->info->ops->serdes_get_stats) {
1143 data += count;
1144 count = chip->info->ops->serdes_get_stats(chip, port, data);
1145 }
1146 data += count;
1147 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1148 mv88e6xxx_reg_unlock(chip);
1149}
1150
1151static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1152 uint64_t *data)
1153{
1154 struct mv88e6xxx_chip *chip = ds->priv;
1155 int ret;
1156
1157 mv88e6xxx_reg_lock(chip);
1158
1159 ret = mv88e6xxx_stats_snapshot(chip, port);
1160 mv88e6xxx_reg_unlock(chip);
1161
1162 if (ret < 0)
1163 return;
1164
1165 mv88e6xxx_get_stats(chip, port, data);
1166
1167}
1168
1169static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1170{
1171 struct mv88e6xxx_chip *chip = ds->priv;
1172 int len;
1173
1174 len = 32 * sizeof(u16);
1175 if (chip->info->ops->serdes_get_regs_len)
1176 len += chip->info->ops->serdes_get_regs_len(chip, port);
1177
1178 return len;
1179}
1180
1181static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1182 struct ethtool_regs *regs, void *_p)
1183{
1184 struct mv88e6xxx_chip *chip = ds->priv;
1185 int err;
1186 u16 reg;
1187 u16 *p = _p;
1188 int i;
1189
1190 regs->version = chip->info->prod_num;
1191
1192 memset(p, 0xff, 32 * sizeof(u16));
1193
1194 mv88e6xxx_reg_lock(chip);
1195
1196 for (i = 0; i < 32; i++) {
1197
1198 err = mv88e6xxx_port_read(chip, port, i, ®);
1199 if (!err)
1200 p[i] = reg;
1201 }
1202
1203 if (chip->info->ops->serdes_get_regs)
1204 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1205
1206 mv88e6xxx_reg_unlock(chip);
1207}
1208
1209static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1210 struct ethtool_eee *e)
1211{
1212 /* Nothing to do on the port's MAC */
1213 return 0;
1214}
1215
1216static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1217 struct ethtool_eee *e)
1218{
1219 /* Nothing to do on the port's MAC */
1220 return 0;
1221}
1222
1223/* Mask of the local ports allowed to receive frames from a given fabric port */
1224static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1225{
1226 struct dsa_switch *ds = chip->ds;
1227 struct dsa_switch_tree *dst = ds->dst;
1228 struct net_device *br;
1229 struct dsa_port *dp;
1230 bool found = false;
1231 u16 pvlan;
1232
1233 list_for_each_entry(dp, &dst->ports, list) {
1234 if (dp->ds->index == dev && dp->index == port) {
1235 found = true;
1236 break;
1237 }
1238 }
1239
1240 /* Prevent frames from unknown switch or port */
1241 if (!found)
1242 return 0;
1243
1244 /* Frames from DSA links and CPU ports can egress any local port */
1245 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1246 return mv88e6xxx_port_mask(chip);
1247
1248 br = dp->bridge_dev;
1249 pvlan = 0;
1250
1251 /* Frames from user ports can egress any local DSA links and CPU ports,
1252 * as well as any local member of their bridge group.
1253 */
1254 list_for_each_entry(dp, &dst->ports, list)
1255 if (dp->ds == ds &&
1256 (dp->type == DSA_PORT_TYPE_CPU ||
1257 dp->type == DSA_PORT_TYPE_DSA ||
1258 (br && dp->bridge_dev == br)))
1259 pvlan |= BIT(dp->index);
1260
1261 return pvlan;
1262}
1263
1264static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1265{
1266 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1267
1268 /* prevent frames from going back out of the port they came in on */
1269 output_ports &= ~BIT(port);
1270
1271 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1272}
1273
1274static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1275 u8 state)
1276{
1277 struct mv88e6xxx_chip *chip = ds->priv;
1278 int err;
1279
1280 mv88e6xxx_reg_lock(chip);
1281 err = mv88e6xxx_port_set_state(chip, port, state);
1282 mv88e6xxx_reg_unlock(chip);
1283
1284 if (err)
1285 dev_err(ds->dev, "p%d: failed to update state\n", port);
1286}
1287
1288static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1289{
1290 int err;
1291
1292 if (chip->info->ops->ieee_pri_map) {
1293 err = chip->info->ops->ieee_pri_map(chip);
1294 if (err)
1295 return err;
1296 }
1297
1298 if (chip->info->ops->ip_pri_map) {
1299 err = chip->info->ops->ip_pri_map(chip);
1300 if (err)
1301 return err;
1302 }
1303
1304 return 0;
1305}
1306
1307static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1308{
1309 struct dsa_switch *ds = chip->ds;
1310 int target, port;
1311 int err;
1312
1313 if (!chip->info->global2_addr)
1314 return 0;
1315
1316 /* Initialize the routing port to the 32 possible target devices */
1317 for (target = 0; target < 32; target++) {
1318 port = dsa_routing_port(ds, target);
1319 if (port == ds->num_ports)
1320 port = 0x1f;
1321
1322 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1323 if (err)
1324 return err;
1325 }
1326
1327 if (chip->info->ops->set_cascade_port) {
1328 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1329 err = chip->info->ops->set_cascade_port(chip, port);
1330 if (err)
1331 return err;
1332 }
1333
1334 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1335 if (err)
1336 return err;
1337
1338 return 0;
1339}
1340
1341static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1342{
1343 /* Clear all trunk masks and mapping */
1344 if (chip->info->global2_addr)
1345 return mv88e6xxx_g2_trunk_clear(chip);
1346
1347 return 0;
1348}
1349
1350static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1351{
1352 if (chip->info->ops->rmu_disable)
1353 return chip->info->ops->rmu_disable(chip);
1354
1355 return 0;
1356}
1357
1358static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1359{
1360 if (chip->info->ops->pot_clear)
1361 return chip->info->ops->pot_clear(chip);
1362
1363 return 0;
1364}
1365
1366static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1367{
1368 if (chip->info->ops->mgmt_rsvd2cpu)
1369 return chip->info->ops->mgmt_rsvd2cpu(chip);
1370
1371 return 0;
1372}
1373
1374static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1375{
1376 int err;
1377
1378 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1379 if (err)
1380 return err;
1381
1382 /* The chips that have a "learn2all" bit in Global1, ATU
1383 * Control are precisely those whose port registers have a
1384 * Message Port bit in Port Control 1 and hence implement
1385 * ->port_setup_message_port.
1386 */
1387 if (chip->info->ops->port_setup_message_port) {
1388 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1389 if (err)
1390 return err;
1391 }
1392
1393 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1394}
1395
1396static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1397{
1398 int port;
1399 int err;
1400
1401 if (!chip->info->ops->irl_init_all)
1402 return 0;
1403
1404 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1405 /* Disable ingress rate limiting by resetting all per port
1406 * ingress rate limit resources to their initial state.
1407 */
1408 err = chip->info->ops->irl_init_all(chip, port);
1409 if (err)
1410 return err;
1411 }
1412
1413 return 0;
1414}
1415
1416static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1417{
1418 if (chip->info->ops->set_switch_mac) {
1419 u8 addr[ETH_ALEN];
1420
1421 eth_random_addr(addr);
1422
1423 return chip->info->ops->set_switch_mac(chip, addr);
1424 }
1425
1426 return 0;
1427}
1428
1429static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1430{
1431 struct dsa_switch_tree *dst = chip->ds->dst;
1432 struct dsa_switch *ds;
1433 struct dsa_port *dp;
1434 u16 pvlan = 0;
1435
1436 if (!mv88e6xxx_has_pvt(chip))
1437 return 0;
1438
1439 /* Skip the local source device, which uses in-chip port VLAN */
1440 if (dev != chip->ds->index) {
1441 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1442
1443 ds = dsa_switch_find(dst->index, dev);
1444 dp = ds ? dsa_to_port(ds, port) : NULL;
1445 if (dp && dp->lag_dev) {
1446 /* As the PVT is used to limit flooding of
1447 * FORWARD frames, which use the LAG ID as the
1448 * source port, we must translate dev/port to
1449 * the special "LAG device" in the PVT, using
1450 * the LAG ID as the port number.
1451 */
1452 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1453 port = dsa_lag_id(dst, dp->lag_dev);
1454 }
1455 }
1456
1457 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1458}
1459
1460static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1461{
1462 int dev, port;
1463 int err;
1464
1465 if (!mv88e6xxx_has_pvt(chip))
1466 return 0;
1467
1468 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1469 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1470 */
1471 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1472 if (err)
1473 return err;
1474
1475 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1476 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1477 err = mv88e6xxx_pvt_map(chip, dev, port);
1478 if (err)
1479 return err;
1480 }
1481 }
1482
1483 return 0;
1484}
1485
1486static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1487{
1488 struct mv88e6xxx_chip *chip = ds->priv;
1489 int err;
1490
1491 if (dsa_to_port(ds, port)->lag_dev)
1492 /* Hardware is incapable of fast-aging a LAG through a
1493 * regular ATU move operation. Until we have something
1494 * more fancy in place this is a no-op.
1495 */
1496 return;
1497
1498 mv88e6xxx_reg_lock(chip);
1499 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1500 mv88e6xxx_reg_unlock(chip);
1501
1502 if (err)
1503 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1504}
1505
1506static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1507{
1508 if (!mv88e6xxx_max_vid(chip))
1509 return 0;
1510
1511 return mv88e6xxx_g1_vtu_flush(chip);
1512}
1513
1514static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1515 struct mv88e6xxx_vtu_entry *entry)
1516{
1517 int err;
1518
1519 if (!chip->info->ops->vtu_getnext)
1520 return -EOPNOTSUPP;
1521
1522 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1523 entry->valid = false;
1524
1525 err = chip->info->ops->vtu_getnext(chip, entry);
1526
1527 if (entry->vid != vid)
1528 entry->valid = false;
1529
1530 return err;
1531}
1532
1533static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1534 int (*cb)(struct mv88e6xxx_chip *chip,
1535 const struct mv88e6xxx_vtu_entry *entry,
1536 void *priv),
1537 void *priv)
1538{
1539 struct mv88e6xxx_vtu_entry entry = {
1540 .vid = mv88e6xxx_max_vid(chip),
1541 .valid = false,
1542 };
1543 int err;
1544
1545 if (!chip->info->ops->vtu_getnext)
1546 return -EOPNOTSUPP;
1547
1548 do {
1549 err = chip->info->ops->vtu_getnext(chip, &entry);
1550 if (err)
1551 return err;
1552
1553 if (!entry.valid)
1554 break;
1555
1556 err = cb(chip, &entry, priv);
1557 if (err)
1558 return err;
1559 } while (entry.vid < mv88e6xxx_max_vid(chip));
1560
1561 return 0;
1562}
1563
1564static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1565 struct mv88e6xxx_vtu_entry *entry)
1566{
1567 if (!chip->info->ops->vtu_loadpurge)
1568 return -EOPNOTSUPP;
1569
1570 return chip->info->ops->vtu_loadpurge(chip, entry);
1571}
1572
1573static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1574 const struct mv88e6xxx_vtu_entry *entry,
1575 void *_fid_bitmap)
1576{
1577 unsigned long *fid_bitmap = _fid_bitmap;
1578
1579 set_bit(entry->fid, fid_bitmap);
1580 return 0;
1581}
1582
1583int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1584{
1585 int i, err;
1586 u16 fid;
1587
1588 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1589
1590 /* Set every FID bit used by the (un)bridged ports */
1591 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1592 err = mv88e6xxx_port_get_fid(chip, i, &fid);
1593 if (err)
1594 return err;
1595
1596 set_bit(fid, fid_bitmap);
1597 }
1598
1599 /* Set every FID bit used by the VLAN entries */
1600 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
1601}
1602
1603static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1604{
1605 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1606 int err;
1607
1608 err = mv88e6xxx_fid_map(chip, fid_bitmap);
1609 if (err)
1610 return err;
1611
1612 /* The reset value 0x000 is used to indicate that multiple address
1613 * databases are not needed. Return the next positive available.
1614 */
1615 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1616 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1617 return -ENOSPC;
1618
1619 /* Clear the database */
1620 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1621}
1622
1623static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1624 u16 vid)
1625{
1626 struct mv88e6xxx_chip *chip = ds->priv;
1627 struct mv88e6xxx_vtu_entry vlan;
1628 int i, err;
1629
1630 /* DSA and CPU ports have to be members of multiple vlans */
1631 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1632 return 0;
1633
1634 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
1635 if (err)
1636 return err;
1637
1638 if (!vlan.valid)
1639 return 0;
1640
1641 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1642 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1643 continue;
1644
1645 if (!dsa_to_port(ds, i)->slave)
1646 continue;
1647
1648 if (vlan.member[i] ==
1649 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1650 continue;
1651
1652 if (dsa_to_port(ds, i)->bridge_dev ==
1653 dsa_to_port(ds, port)->bridge_dev)
1654 break; /* same bridge, check next VLAN */
1655
1656 if (!dsa_to_port(ds, i)->bridge_dev)
1657 continue;
1658
1659 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1660 port, vlan.vid, i,
1661 netdev_name(dsa_to_port(ds, i)->bridge_dev));
1662 return -EOPNOTSUPP;
1663 }
1664
1665 return 0;
1666}
1667
1668static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1669 bool vlan_filtering,
1670 struct netlink_ext_ack *extack)
1671{
1672 struct mv88e6xxx_chip *chip = ds->priv;
1673 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1674 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1675 int err;
1676
1677 if (!mv88e6xxx_max_vid(chip))
1678 return -EOPNOTSUPP;
1679
1680 mv88e6xxx_reg_lock(chip);
1681 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1682 mv88e6xxx_reg_unlock(chip);
1683
1684 return err;
1685}
1686
1687static int
1688mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1689 const struct switchdev_obj_port_vlan *vlan)
1690{
1691 struct mv88e6xxx_chip *chip = ds->priv;
1692 int err;
1693
1694 if (!mv88e6xxx_max_vid(chip))
1695 return -EOPNOTSUPP;
1696
1697 /* If the requested port doesn't belong to the same bridge as the VLAN
1698 * members, do not support it (yet) and fallback to software VLAN.
1699 */
1700 mv88e6xxx_reg_lock(chip);
1701 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
1702 mv88e6xxx_reg_unlock(chip);
1703
1704 return err;
1705}
1706
1707static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1708 const unsigned char *addr, u16 vid,
1709 u8 state)
1710{
1711 struct mv88e6xxx_atu_entry entry;
1712 struct mv88e6xxx_vtu_entry vlan;
1713 u16 fid;
1714 int err;
1715
1716 /* Null VLAN ID corresponds to the port private database */
1717 if (vid == 0) {
1718 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1719 if (err)
1720 return err;
1721 } else {
1722 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
1723 if (err)
1724 return err;
1725
1726 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1727 if (!vlan.valid)
1728 return -EOPNOTSUPP;
1729
1730 fid = vlan.fid;
1731 }
1732
1733 entry.state = 0;
1734 ether_addr_copy(entry.mac, addr);
1735 eth_addr_dec(entry.mac);
1736
1737 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
1738 if (err)
1739 return err;
1740
1741 /* Initialize a fresh ATU entry if it isn't found */
1742 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
1743 memset(&entry, 0, sizeof(entry));
1744 ether_addr_copy(entry.mac, addr);
1745 }
1746
1747 /* Purge the ATU entry only if no port is using it anymore */
1748 if (!state) {
1749 entry.portvec &= ~BIT(port);
1750 if (!entry.portvec)
1751 entry.state = 0;
1752 } else {
1753 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
1754 entry.portvec = BIT(port);
1755 else
1756 entry.portvec |= BIT(port);
1757
1758 entry.state = state;
1759 }
1760
1761 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
1762}
1763
1764static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
1765 const struct mv88e6xxx_policy *policy)
1766{
1767 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
1768 enum mv88e6xxx_policy_action action = policy->action;
1769 const u8 *addr = policy->addr;
1770 u16 vid = policy->vid;
1771 u8 state;
1772 int err;
1773 int id;
1774
1775 if (!chip->info->ops->port_set_policy)
1776 return -EOPNOTSUPP;
1777
1778 switch (mapping) {
1779 case MV88E6XXX_POLICY_MAPPING_DA:
1780 case MV88E6XXX_POLICY_MAPPING_SA:
1781 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1782 state = 0; /* Dissociate the port and address */
1783 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1784 is_multicast_ether_addr(addr))
1785 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
1786 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1787 is_unicast_ether_addr(addr))
1788 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
1789 else
1790 return -EOPNOTSUPP;
1791
1792 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1793 state);
1794 if (err)
1795 return err;
1796 break;
1797 default:
1798 return -EOPNOTSUPP;
1799 }
1800
1801 /* Skip the port's policy clearing if the mapping is still in use */
1802 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1803 idr_for_each_entry(&chip->policies, policy, id)
1804 if (policy->port == port &&
1805 policy->mapping == mapping &&
1806 policy->action != action)
1807 return 0;
1808
1809 return chip->info->ops->port_set_policy(chip, port, mapping, action);
1810}
1811
1812static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
1813 struct ethtool_rx_flow_spec *fs)
1814{
1815 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
1816 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
1817 enum mv88e6xxx_policy_mapping mapping;
1818 enum mv88e6xxx_policy_action action;
1819 struct mv88e6xxx_policy *policy;
1820 u16 vid = 0;
1821 u8 *addr;
1822 int err;
1823 int id;
1824
1825 if (fs->location != RX_CLS_LOC_ANY)
1826 return -EINVAL;
1827
1828 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1829 action = MV88E6XXX_POLICY_ACTION_DISCARD;
1830 else
1831 return -EOPNOTSUPP;
1832
1833 switch (fs->flow_type & ~FLOW_EXT) {
1834 case ETHER_FLOW:
1835 if (!is_zero_ether_addr(mac_mask->h_dest) &&
1836 is_zero_ether_addr(mac_mask->h_source)) {
1837 mapping = MV88E6XXX_POLICY_MAPPING_DA;
1838 addr = mac_entry->h_dest;
1839 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
1840 !is_zero_ether_addr(mac_mask->h_source)) {
1841 mapping = MV88E6XXX_POLICY_MAPPING_SA;
1842 addr = mac_entry->h_source;
1843 } else {
1844 /* Cannot support DA and SA mapping in the same rule */
1845 return -EOPNOTSUPP;
1846 }
1847 break;
1848 default:
1849 return -EOPNOTSUPP;
1850 }
1851
1852 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
1853 if (fs->m_ext.vlan_tci != htons(0xffff))
1854 return -EOPNOTSUPP;
1855 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
1856 }
1857
1858 idr_for_each_entry(&chip->policies, policy, id) {
1859 if (policy->port == port && policy->mapping == mapping &&
1860 policy->action == action && policy->vid == vid &&
1861 ether_addr_equal(policy->addr, addr))
1862 return -EEXIST;
1863 }
1864
1865 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
1866 if (!policy)
1867 return -ENOMEM;
1868
1869 fs->location = 0;
1870 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
1871 GFP_KERNEL);
1872 if (err) {
1873 devm_kfree(chip->dev, policy);
1874 return err;
1875 }
1876
1877 memcpy(&policy->fs, fs, sizeof(*fs));
1878 ether_addr_copy(policy->addr, addr);
1879 policy->mapping = mapping;
1880 policy->action = action;
1881 policy->port = port;
1882 policy->vid = vid;
1883
1884 err = mv88e6xxx_policy_apply(chip, port, policy);
1885 if (err) {
1886 idr_remove(&chip->policies, fs->location);
1887 devm_kfree(chip->dev, policy);
1888 return err;
1889 }
1890
1891 return 0;
1892}
1893
1894static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
1895 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
1896{
1897 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1898 struct mv88e6xxx_chip *chip = ds->priv;
1899 struct mv88e6xxx_policy *policy;
1900 int err;
1901 int id;
1902
1903 mv88e6xxx_reg_lock(chip);
1904
1905 switch (rxnfc->cmd) {
1906 case ETHTOOL_GRXCLSRLCNT:
1907 rxnfc->data = 0;
1908 rxnfc->data |= RX_CLS_LOC_SPECIAL;
1909 rxnfc->rule_cnt = 0;
1910 idr_for_each_entry(&chip->policies, policy, id)
1911 if (policy->port == port)
1912 rxnfc->rule_cnt++;
1913 err = 0;
1914 break;
1915 case ETHTOOL_GRXCLSRULE:
1916 err = -ENOENT;
1917 policy = idr_find(&chip->policies, fs->location);
1918 if (policy) {
1919 memcpy(fs, &policy->fs, sizeof(*fs));
1920 err = 0;
1921 }
1922 break;
1923 case ETHTOOL_GRXCLSRLALL:
1924 rxnfc->data = 0;
1925 rxnfc->rule_cnt = 0;
1926 idr_for_each_entry(&chip->policies, policy, id)
1927 if (policy->port == port)
1928 rule_locs[rxnfc->rule_cnt++] = id;
1929 err = 0;
1930 break;
1931 default:
1932 err = -EOPNOTSUPP;
1933 break;
1934 }
1935
1936 mv88e6xxx_reg_unlock(chip);
1937
1938 return err;
1939}
1940
1941static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
1942 struct ethtool_rxnfc *rxnfc)
1943{
1944 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1945 struct mv88e6xxx_chip *chip = ds->priv;
1946 struct mv88e6xxx_policy *policy;
1947 int err;
1948
1949 mv88e6xxx_reg_lock(chip);
1950
1951 switch (rxnfc->cmd) {
1952 case ETHTOOL_SRXCLSRLINS:
1953 err = mv88e6xxx_policy_insert(chip, port, fs);
1954 break;
1955 case ETHTOOL_SRXCLSRLDEL:
1956 err = -ENOENT;
1957 policy = idr_remove(&chip->policies, fs->location);
1958 if (policy) {
1959 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
1960 err = mv88e6xxx_policy_apply(chip, port, policy);
1961 devm_kfree(chip->dev, policy);
1962 }
1963 break;
1964 default:
1965 err = -EOPNOTSUPP;
1966 break;
1967 }
1968
1969 mv88e6xxx_reg_unlock(chip);
1970
1971 return err;
1972}
1973
1974static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1975 u16 vid)
1976{
1977 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1978 u8 broadcast[ETH_ALEN];
1979
1980 eth_broadcast_addr(broadcast);
1981
1982 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1983}
1984
1985static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1986{
1987 int port;
1988 int err;
1989
1990 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1991 struct dsa_port *dp = dsa_to_port(chip->ds, port);
1992 struct net_device *brport;
1993
1994 if (dsa_is_unused_port(chip->ds, port))
1995 continue;
1996
1997 brport = dsa_port_to_bridge_port(dp);
1998 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
1999 /* Skip bridged user ports where broadcast
2000 * flooding is disabled.
2001 */
2002 continue;
2003
2004 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2005 if (err)
2006 return err;
2007 }
2008
2009 return 0;
2010}
2011
2012struct mv88e6xxx_port_broadcast_sync_ctx {
2013 int port;
2014 bool flood;
2015};
2016
2017static int
2018mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2019 const struct mv88e6xxx_vtu_entry *vlan,
2020 void *_ctx)
2021{
2022 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2023 u8 broadcast[ETH_ALEN];
2024 u8 state;
2025
2026 if (ctx->flood)
2027 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2028 else
2029 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2030
2031 eth_broadcast_addr(broadcast);
2032
2033 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2034 vlan->vid, state);
2035}
2036
2037static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2038 bool flood)
2039{
2040 struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2041 .port = port,
2042 .flood = flood,
2043 };
2044 struct mv88e6xxx_vtu_entry vid0 = {
2045 .vid = 0,
2046 };
2047 int err;
2048
2049 /* Update the port's private database... */
2050 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2051 if (err)
2052 return err;
2053
2054 /* ...and the database for all VLANs. */
2055 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2056 &ctx);
2057}
2058
2059static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2060 u16 vid, u8 member, bool warn)
2061{
2062 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2063 struct mv88e6xxx_vtu_entry vlan;
2064 int i, err;
2065
2066 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2067 if (err)
2068 return err;
2069
2070 if (!vlan.valid) {
2071 memset(&vlan, 0, sizeof(vlan));
2072
2073 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2074 if (err)
2075 return err;
2076
2077 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2078 if (i == port)
2079 vlan.member[i] = member;
2080 else
2081 vlan.member[i] = non_member;
2082
2083 vlan.vid = vid;
2084 vlan.valid = true;
2085
2086 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2087 if (err)
2088 return err;
2089
2090 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2091 if (err)
2092 return err;
2093 } else if (vlan.member[port] != member) {
2094 vlan.member[port] = member;
2095
2096 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2097 if (err)
2098 return err;
2099 } else if (warn) {
2100 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2101 port, vid);
2102 }
2103
2104 return 0;
2105}
2106
2107static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2108 const struct switchdev_obj_port_vlan *vlan,
2109 struct netlink_ext_ack *extack)
2110{
2111 struct mv88e6xxx_chip *chip = ds->priv;
2112 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2113 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2114 bool warn;
2115 u8 member;
2116 int err;
2117
2118 if (!vlan->vid)
2119 return 0;
2120
2121 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2122 if (err)
2123 return err;
2124
2125 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2126 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2127 else if (untagged)
2128 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2129 else
2130 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2131
2132 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
2133 * and then the CPU port. Do not warn for duplicates for the CPU port.
2134 */
2135 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2136
2137 mv88e6xxx_reg_lock(chip);
2138
2139 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2140 if (err) {
2141 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2142 vlan->vid, untagged ? 'u' : 't');
2143 goto out;
2144 }
2145
2146 if (pvid) {
2147 err = mv88e6xxx_port_set_pvid(chip, port, vlan->vid);
2148 if (err) {
2149 dev_err(ds->dev, "p%d: failed to set PVID %d\n",
2150 port, vlan->vid);
2151 goto out;
2152 }
2153 }
2154out:
2155 mv88e6xxx_reg_unlock(chip);
2156
2157 return err;
2158}
2159
2160static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2161 int port, u16 vid)
2162{
2163 struct mv88e6xxx_vtu_entry vlan;
2164 int i, err;
2165
2166 if (!vid)
2167 return 0;
2168
2169 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2170 if (err)
2171 return err;
2172
2173 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2174 * tell switchdev that this VLAN is likely handled in software.
2175 */
2176 if (!vlan.valid ||
2177 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2178 return -EOPNOTSUPP;
2179
2180 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2181
2182 /* keep the VLAN unless all ports are excluded */
2183 vlan.valid = false;
2184 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2185 if (vlan.member[i] !=
2186 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2187 vlan.valid = true;
2188 break;
2189 }
2190 }
2191
2192 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2193 if (err)
2194 return err;
2195
2196 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2197}
2198
2199static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2200 const struct switchdev_obj_port_vlan *vlan)
2201{
2202 struct mv88e6xxx_chip *chip = ds->priv;
2203 int err = 0;
2204 u16 pvid;
2205
2206 if (!mv88e6xxx_max_vid(chip))
2207 return -EOPNOTSUPP;
2208
2209 mv88e6xxx_reg_lock(chip);
2210
2211 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2212 if (err)
2213 goto unlock;
2214
2215 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2216 if (err)
2217 goto unlock;
2218
2219 if (vlan->vid == pvid) {
2220 err = mv88e6xxx_port_set_pvid(chip, port, 0);
2221 if (err)
2222 goto unlock;
2223 }
2224
2225unlock:
2226 mv88e6xxx_reg_unlock(chip);
2227
2228 return err;
2229}
2230
2231static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2232 const unsigned char *addr, u16 vid)
2233{
2234 struct mv88e6xxx_chip *chip = ds->priv;
2235 int err;
2236
2237 mv88e6xxx_reg_lock(chip);
2238 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2239 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2240 mv88e6xxx_reg_unlock(chip);
2241
2242 return err;
2243}
2244
2245static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2246 const unsigned char *addr, u16 vid)
2247{
2248 struct mv88e6xxx_chip *chip = ds->priv;
2249 int err;
2250
2251 mv88e6xxx_reg_lock(chip);
2252 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2253 mv88e6xxx_reg_unlock(chip);
2254
2255 return err;
2256}
2257
2258static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2259 u16 fid, u16 vid, int port,
2260 dsa_fdb_dump_cb_t *cb, void *data)
2261{
2262 struct mv88e6xxx_atu_entry addr;
2263 bool is_static;
2264 int err;
2265
2266 addr.state = 0;
2267 eth_broadcast_addr(addr.mac);
2268
2269 do {
2270 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2271 if (err)
2272 return err;
2273
2274 if (!addr.state)
2275 break;
2276
2277 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2278 continue;
2279
2280 if (!is_unicast_ether_addr(addr.mac))
2281 continue;
2282
2283 is_static = (addr.state ==
2284 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2285 err = cb(addr.mac, vid, is_static, data);
2286 if (err)
2287 return err;
2288 } while (!is_broadcast_ether_addr(addr.mac));
2289
2290 return err;
2291}
2292
2293struct mv88e6xxx_port_db_dump_vlan_ctx {
2294 int port;
2295 dsa_fdb_dump_cb_t *cb;
2296 void *data;
2297};
2298
2299static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2300 const struct mv88e6xxx_vtu_entry *entry,
2301 void *_data)
2302{
2303 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2304
2305 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2306 ctx->port, ctx->cb, ctx->data);
2307}
2308
2309static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2310 dsa_fdb_dump_cb_t *cb, void *data)
2311{
2312 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2313 .port = port,
2314 .cb = cb,
2315 .data = data,
2316 };
2317 u16 fid;
2318 int err;
2319
2320 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2321 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2322 if (err)
2323 return err;
2324
2325 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2326 if (err)
2327 return err;
2328
2329 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
2330}
2331
2332static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2333 dsa_fdb_dump_cb_t *cb, void *data)
2334{
2335 struct mv88e6xxx_chip *chip = ds->priv;
2336 int err;
2337
2338 mv88e6xxx_reg_lock(chip);
2339 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2340 mv88e6xxx_reg_unlock(chip);
2341
2342 return err;
2343}
2344
2345static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2346 struct net_device *br)
2347{
2348 struct dsa_switch *ds = chip->ds;
2349 struct dsa_switch_tree *dst = ds->dst;
2350 struct dsa_port *dp;
2351 int err;
2352
2353 list_for_each_entry(dp, &dst->ports, list) {
2354 if (dp->bridge_dev == br) {
2355 if (dp->ds == ds) {
2356 /* This is a local bridge group member,
2357 * remap its Port VLAN Map.
2358 */
2359 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2360 if (err)
2361 return err;
2362 } else {
2363 /* This is an external bridge group member,
2364 * remap its cross-chip Port VLAN Table entry.
2365 */
2366 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2367 dp->index);
2368 if (err)
2369 return err;
2370 }
2371 }
2372 }
2373
2374 return 0;
2375}
2376
2377static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2378 struct net_device *br)
2379{
2380 struct mv88e6xxx_chip *chip = ds->priv;
2381 int err;
2382
2383 mv88e6xxx_reg_lock(chip);
2384 err = mv88e6xxx_bridge_map(chip, br);
2385 mv88e6xxx_reg_unlock(chip);
2386
2387 return err;
2388}
2389
2390static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2391 struct net_device *br)
2392{
2393 struct mv88e6xxx_chip *chip = ds->priv;
2394
2395 mv88e6xxx_reg_lock(chip);
2396 if (mv88e6xxx_bridge_map(chip, br) ||
2397 mv88e6xxx_port_vlan_map(chip, port))
2398 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2399 mv88e6xxx_reg_unlock(chip);
2400}
2401
2402static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2403 int tree_index, int sw_index,
2404 int port, struct net_device *br)
2405{
2406 struct mv88e6xxx_chip *chip = ds->priv;
2407 int err;
2408
2409 if (tree_index != ds->dst->index)
2410 return 0;
2411
2412 mv88e6xxx_reg_lock(chip);
2413 err = mv88e6xxx_pvt_map(chip, sw_index, port);
2414 mv88e6xxx_reg_unlock(chip);
2415
2416 return err;
2417}
2418
2419static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2420 int tree_index, int sw_index,
2421 int port, struct net_device *br)
2422{
2423 struct mv88e6xxx_chip *chip = ds->priv;
2424
2425 if (tree_index != ds->dst->index)
2426 return;
2427
2428 mv88e6xxx_reg_lock(chip);
2429 if (mv88e6xxx_pvt_map(chip, sw_index, port))
2430 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2431 mv88e6xxx_reg_unlock(chip);
2432}
2433
2434static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2435{
2436 if (chip->info->ops->reset)
2437 return chip->info->ops->reset(chip);
2438
2439 return 0;
2440}
2441
2442static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2443{
2444 struct gpio_desc *gpiod = chip->reset;
2445
2446 /* If there is a GPIO connected to the reset pin, toggle it */
2447 if (gpiod) {
2448 gpiod_set_value_cansleep(gpiod, 1);
2449 usleep_range(10000, 20000);
2450 gpiod_set_value_cansleep(gpiod, 0);
2451 usleep_range(10000, 20000);
2452
2453 mv88e6xxx_g1_wait_eeprom_done(chip);
2454 }
2455}
2456
2457static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2458{
2459 int i, err;
2460
2461 /* Set all ports to the Disabled state */
2462 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2463 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
2464 if (err)
2465 return err;
2466 }
2467
2468 /* Wait for transmit queues to drain,
2469 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2470 */
2471 usleep_range(2000, 4000);
2472
2473 return 0;
2474}
2475
2476static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2477{
2478 int err;
2479
2480 err = mv88e6xxx_disable_ports(chip);
2481 if (err)
2482 return err;
2483
2484 mv88e6xxx_hardware_reset(chip);
2485
2486 return mv88e6xxx_software_reset(chip);
2487}
2488
2489static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2490 enum mv88e6xxx_frame_mode frame,
2491 enum mv88e6xxx_egress_mode egress, u16 etype)
2492{
2493 int err;
2494
2495 if (!chip->info->ops->port_set_frame_mode)
2496 return -EOPNOTSUPP;
2497
2498 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
2499 if (err)
2500 return err;
2501
2502 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2503 if (err)
2504 return err;
2505
2506 if (chip->info->ops->port_set_ether_type)
2507 return chip->info->ops->port_set_ether_type(chip, port, etype);
2508
2509 return 0;
2510}
2511
2512static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2513{
2514 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2515 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2516 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2517}
2518
2519static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2520{
2521 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2522 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2523 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2524}
2525
2526static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2527{
2528 return mv88e6xxx_set_port_mode(chip, port,
2529 MV88E6XXX_FRAME_MODE_ETHERTYPE,
2530 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2531 ETH_P_EDSA);
2532}
2533
2534static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2535{
2536 if (dsa_is_dsa_port(chip->ds, port))
2537 return mv88e6xxx_set_port_mode_dsa(chip, port);
2538
2539 if (dsa_is_user_port(chip->ds, port))
2540 return mv88e6xxx_set_port_mode_normal(chip, port);
2541
2542 /* Setup CPU port mode depending on its supported tag format */
2543 if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
2544 return mv88e6xxx_set_port_mode_dsa(chip, port);
2545
2546 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
2547 return mv88e6xxx_set_port_mode_edsa(chip, port);
2548
2549 return -EINVAL;
2550}
2551
2552static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2553{
2554 bool message = dsa_is_dsa_port(chip->ds, port);
2555
2556 return mv88e6xxx_port_set_message_port(chip, port, message);
2557}
2558
2559static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2560{
2561 int err;
2562
2563 if (chip->info->ops->port_set_ucast_flood) {
2564 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
2565 if (err)
2566 return err;
2567 }
2568 if (chip->info->ops->port_set_mcast_flood) {
2569 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
2570 if (err)
2571 return err;
2572 }
2573
2574 return 0;
2575}
2576
2577static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
2578{
2579 struct mv88e6xxx_port *mvp = dev_id;
2580 struct mv88e6xxx_chip *chip = mvp->chip;
2581 irqreturn_t ret = IRQ_NONE;
2582 int port = mvp->port;
2583 int lane;
2584
2585 mv88e6xxx_reg_lock(chip);
2586 lane = mv88e6xxx_serdes_get_lane(chip, port);
2587 if (lane >= 0)
2588 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
2589 mv88e6xxx_reg_unlock(chip);
2590
2591 return ret;
2592}
2593
2594static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
2595 int lane)
2596{
2597 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2598 unsigned int irq;
2599 int err;
2600
2601 /* Nothing to request if this SERDES port has no IRQ */
2602 irq = mv88e6xxx_serdes_irq_mapping(chip, port);
2603 if (!irq)
2604 return 0;
2605
2606 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
2607 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
2608
2609 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
2610 mv88e6xxx_reg_unlock(chip);
2611 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
2612 IRQF_ONESHOT, dev_id->serdes_irq_name,
2613 dev_id);
2614 mv88e6xxx_reg_lock(chip);
2615 if (err)
2616 return err;
2617
2618 dev_id->serdes_irq = irq;
2619
2620 return mv88e6xxx_serdes_irq_enable(chip, port, lane);
2621}
2622
2623static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
2624 int lane)
2625{
2626 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2627 unsigned int irq = dev_id->serdes_irq;
2628 int err;
2629
2630 /* Nothing to free if no IRQ has been requested */
2631 if (!irq)
2632 return 0;
2633
2634 err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
2635
2636 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
2637 mv88e6xxx_reg_unlock(chip);
2638 free_irq(irq, dev_id);
2639 mv88e6xxx_reg_lock(chip);
2640
2641 dev_id->serdes_irq = 0;
2642
2643 return err;
2644}
2645
2646static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2647 bool on)
2648{
2649 int lane;
2650 int err;
2651
2652 lane = mv88e6xxx_serdes_get_lane(chip, port);
2653 if (lane < 0)
2654 return 0;
2655
2656 if (on) {
2657 err = mv88e6xxx_serdes_power_up(chip, port, lane);
2658 if (err)
2659 return err;
2660
2661 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
2662 } else {
2663 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
2664 if (err)
2665 return err;
2666
2667 err = mv88e6xxx_serdes_power_down(chip, port, lane);
2668 }
2669
2670 return err;
2671}
2672
2673static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
2674 enum mv88e6xxx_egress_direction direction,
2675 int port)
2676{
2677 int err;
2678
2679 if (!chip->info->ops->set_egress_port)
2680 return -EOPNOTSUPP;
2681
2682 err = chip->info->ops->set_egress_port(chip, direction, port);
2683 if (err)
2684 return err;
2685
2686 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
2687 chip->ingress_dest_port = port;
2688 else
2689 chip->egress_dest_port = port;
2690
2691 return 0;
2692}
2693
2694static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2695{
2696 struct dsa_switch *ds = chip->ds;
2697 int upstream_port;
2698 int err;
2699
2700 upstream_port = dsa_upstream_port(ds, port);
2701 if (chip->info->ops->port_set_upstream_port) {
2702 err = chip->info->ops->port_set_upstream_port(chip, port,
2703 upstream_port);
2704 if (err)
2705 return err;
2706 }
2707
2708 if (port == upstream_port) {
2709 if (chip->info->ops->set_cpu_port) {
2710 err = chip->info->ops->set_cpu_port(chip,
2711 upstream_port);
2712 if (err)
2713 return err;
2714 }
2715
2716 err = mv88e6xxx_set_egress_port(chip,
2717 MV88E6XXX_EGRESS_DIR_INGRESS,
2718 upstream_port);
2719 if (err && err != -EOPNOTSUPP)
2720 return err;
2721
2722 err = mv88e6xxx_set_egress_port(chip,
2723 MV88E6XXX_EGRESS_DIR_EGRESS,
2724 upstream_port);
2725 if (err && err != -EOPNOTSUPP)
2726 return err;
2727 }
2728
2729 return 0;
2730}
2731
2732static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2733{
2734 struct dsa_switch *ds = chip->ds;
2735 int err;
2736 u16 reg;
2737
2738 chip->ports[port].chip = chip;
2739 chip->ports[port].port = port;
2740
2741 /* MAC Forcing register: don't force link, speed, duplex or flow control
2742 * state to any particular values on physical ports, but force the CPU
2743 * port and all DSA ports to their maximum bandwidth and full duplex.
2744 */
2745 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2746 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2747 SPEED_MAX, DUPLEX_FULL,
2748 PAUSE_OFF,
2749 PHY_INTERFACE_MODE_NA);
2750 else
2751 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2752 SPEED_UNFORCED, DUPLEX_UNFORCED,
2753 PAUSE_ON,
2754 PHY_INTERFACE_MODE_NA);
2755 if (err)
2756 return err;
2757
2758 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2759 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2760 * tunneling, determine priority by looking at 802.1p and IP
2761 * priority fields (IP prio has precedence), and set STP state
2762 * to Forwarding.
2763 *
2764 * If this is the CPU link, use DSA or EDSA tagging depending
2765 * on which tagging mode was configured.
2766 *
2767 * If this is a link to another switch, use DSA tagging mode.
2768 *
2769 * If this is the upstream port for this switch, enable
2770 * forwarding of unknown unicasts and multicasts.
2771 */
2772 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2773 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2774 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2775 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2776 if (err)
2777 return err;
2778
2779 err = mv88e6xxx_setup_port_mode(chip, port);
2780 if (err)
2781 return err;
2782
2783 err = mv88e6xxx_setup_egress_floods(chip, port);
2784 if (err)
2785 return err;
2786
2787 /* Port Control 2: don't force a good FCS, set the MTU size to
2788 * 10222 bytes, disable 802.1q tags checking, don't discard tagged or
2789 * untagged frames on this port, do a destination address lookup on all
2790 * received packets as usual, disable ARP mirroring and don't send a
2791 * copy of all transmitted/received frames on this port to the CPU.
2792 */
2793 err = mv88e6xxx_port_set_map_da(chip, port);
2794 if (err)
2795 return err;
2796
2797 err = mv88e6xxx_setup_upstream_port(chip, port);
2798 if (err)
2799 return err;
2800
2801 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2802 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2803 if (err)
2804 return err;
2805
2806 if (chip->info->ops->port_set_jumbo_size) {
2807 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
2808 if (err)
2809 return err;
2810 }
2811
2812 /* Port Association Vector: disable automatic address learning
2813 * on all user ports since they start out in standalone
2814 * mode. When joining a bridge, learning will be configured to
2815 * match the bridge port settings. Enable learning on all
2816 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
2817 * learning process.
2818 *
2819 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
2820 * and RefreshLocked. I.e. setup standard automatic learning.
2821 */
2822 if (dsa_is_user_port(ds, port))
2823 reg = 0;
2824 else
2825 reg = 1 << port;
2826
2827 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2828 reg);
2829 if (err)
2830 return err;
2831
2832 /* Egress rate control 2: disable egress rate control. */
2833 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2834 0x0000);
2835 if (err)
2836 return err;
2837
2838 if (chip->info->ops->port_pause_limit) {
2839 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2840 if (err)
2841 return err;
2842 }
2843
2844 if (chip->info->ops->port_disable_learn_limit) {
2845 err = chip->info->ops->port_disable_learn_limit(chip, port);
2846 if (err)
2847 return err;
2848 }
2849
2850 if (chip->info->ops->port_disable_pri_override) {
2851 err = chip->info->ops->port_disable_pri_override(chip, port);
2852 if (err)
2853 return err;
2854 }
2855
2856 if (chip->info->ops->port_tag_remap) {
2857 err = chip->info->ops->port_tag_remap(chip, port);
2858 if (err)
2859 return err;
2860 }
2861
2862 if (chip->info->ops->port_egress_rate_limiting) {
2863 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2864 if (err)
2865 return err;
2866 }
2867
2868 if (chip->info->ops->port_setup_message_port) {
2869 err = chip->info->ops->port_setup_message_port(chip, port);
2870 if (err)
2871 return err;
2872 }
2873
2874 /* Port based VLAN map: give each port the same default address
2875 * database, and allow bidirectional communication between the
2876 * CPU and DSA port(s), and the other ports.
2877 */
2878 err = mv88e6xxx_port_set_fid(chip, port, 0);
2879 if (err)
2880 return err;
2881
2882 err = mv88e6xxx_port_vlan_map(chip, port);
2883 if (err)
2884 return err;
2885
2886 /* Default VLAN ID and priority: don't set a default VLAN
2887 * ID, and set the default packet priority to zero.
2888 */
2889 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2890}
2891
2892static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
2893{
2894 struct mv88e6xxx_chip *chip = ds->priv;
2895
2896 if (chip->info->ops->port_set_jumbo_size)
2897 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
2898 else if (chip->info->ops->set_max_frame_size)
2899 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
2900 return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
2901}
2902
2903static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
2904{
2905 struct mv88e6xxx_chip *chip = ds->priv;
2906 int ret = 0;
2907
2908 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2909 new_mtu += EDSA_HLEN;
2910
2911 mv88e6xxx_reg_lock(chip);
2912 if (chip->info->ops->port_set_jumbo_size)
2913 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
2914 else if (chip->info->ops->set_max_frame_size)
2915 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
2916 else
2917 if (new_mtu > 1522)
2918 ret = -EINVAL;
2919 mv88e6xxx_reg_unlock(chip);
2920
2921 return ret;
2922}
2923
2924static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2925 struct phy_device *phydev)
2926{
2927 struct mv88e6xxx_chip *chip = ds->priv;
2928 int err;
2929
2930 mv88e6xxx_reg_lock(chip);
2931 err = mv88e6xxx_serdes_power(chip, port, true);
2932 mv88e6xxx_reg_unlock(chip);
2933
2934 return err;
2935}
2936
2937static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
2938{
2939 struct mv88e6xxx_chip *chip = ds->priv;
2940
2941 mv88e6xxx_reg_lock(chip);
2942 if (mv88e6xxx_serdes_power(chip, port, false))
2943 dev_err(chip->dev, "failed to power off SERDES\n");
2944 mv88e6xxx_reg_unlock(chip);
2945}
2946
2947static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2948 unsigned int ageing_time)
2949{
2950 struct mv88e6xxx_chip *chip = ds->priv;
2951 int err;
2952
2953 mv88e6xxx_reg_lock(chip);
2954 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2955 mv88e6xxx_reg_unlock(chip);
2956
2957 return err;
2958}
2959
2960static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2961{
2962 int err;
2963
2964 /* Initialize the statistics unit */
2965 if (chip->info->ops->stats_set_histogram) {
2966 err = chip->info->ops->stats_set_histogram(chip);
2967 if (err)
2968 return err;
2969 }
2970
2971 return mv88e6xxx_g1_stats_clear(chip);
2972}
2973
2974/* Check if the errata has already been applied. */
2975static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2976{
2977 int port;
2978 int err;
2979 u16 val;
2980
2981 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2982 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
2983 if (err) {
2984 dev_err(chip->dev,
2985 "Error reading hidden register: %d\n", err);
2986 return false;
2987 }
2988 if (val != 0x01c0)
2989 return false;
2990 }
2991
2992 return true;
2993}
2994
2995/* The 6390 copper ports have an errata which require poking magic
2996 * values into undocumented hidden registers and then performing a
2997 * software reset.
2998 */
2999static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3000{
3001 int port;
3002 int err;
3003
3004 if (mv88e6390_setup_errata_applied(chip))
3005 return 0;
3006
3007 /* Set the ports into blocking mode */
3008 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3009 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3010 if (err)
3011 return err;
3012 }
3013
3014 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3015 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3016 if (err)
3017 return err;
3018 }
3019
3020 return mv88e6xxx_software_reset(chip);
3021}
3022
3023static void mv88e6xxx_teardown(struct dsa_switch *ds)
3024{
3025 mv88e6xxx_teardown_devlink_params(ds);
3026 dsa_devlink_resources_unregister(ds);
3027 mv88e6xxx_teardown_devlink_regions_global(ds);
3028}
3029
3030static int mv88e6xxx_setup(struct dsa_switch *ds)
3031{
3032 struct mv88e6xxx_chip *chip = ds->priv;
3033 u8 cmode;
3034 int err;
3035 int i;
3036
3037 chip->ds = ds;
3038 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3039
3040 mv88e6xxx_reg_lock(chip);
3041
3042 if (chip->info->ops->setup_errata) {
3043 err = chip->info->ops->setup_errata(chip);
3044 if (err)
3045 goto unlock;
3046 }
3047
3048 /* Cache the cmode of each port. */
3049 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3050 if (chip->info->ops->port_get_cmode) {
3051 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3052 if (err)
3053 goto unlock;
3054
3055 chip->ports[i].cmode = cmode;
3056 }
3057 }
3058
3059 /* Setup Switch Port Registers */
3060 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3061 if (dsa_is_unused_port(ds, i))
3062 continue;
3063
3064 /* Prevent the use of an invalid port. */
3065 if (mv88e6xxx_is_invalid_port(chip, i)) {
3066 dev_err(chip->dev, "port %d is invalid\n", i);
3067 err = -EINVAL;
3068 goto unlock;
3069 }
3070
3071 err = mv88e6xxx_setup_port(chip, i);
3072 if (err)
3073 goto unlock;
3074 }
3075
3076 err = mv88e6xxx_irl_setup(chip);
3077 if (err)
3078 goto unlock;
3079
3080 err = mv88e6xxx_mac_setup(chip);
3081 if (err)
3082 goto unlock;
3083
3084 err = mv88e6xxx_phy_setup(chip);
3085 if (err)
3086 goto unlock;
3087
3088 err = mv88e6xxx_vtu_setup(chip);
3089 if (err)
3090 goto unlock;
3091
3092 err = mv88e6xxx_pvt_setup(chip);
3093 if (err)
3094 goto unlock;
3095
3096 err = mv88e6xxx_atu_setup(chip);
3097 if (err)
3098 goto unlock;
3099
3100 err = mv88e6xxx_broadcast_setup(chip, 0);
3101 if (err)
3102 goto unlock;
3103
3104 err = mv88e6xxx_pot_setup(chip);
3105 if (err)
3106 goto unlock;
3107
3108 err = mv88e6xxx_rmu_setup(chip);
3109 if (err)
3110 goto unlock;
3111
3112 err = mv88e6xxx_rsvd2cpu_setup(chip);
3113 if (err)
3114 goto unlock;
3115
3116 err = mv88e6xxx_trunk_setup(chip);
3117 if (err)
3118 goto unlock;
3119
3120 err = mv88e6xxx_devmap_setup(chip);
3121 if (err)
3122 goto unlock;
3123
3124 err = mv88e6xxx_pri_setup(chip);
3125 if (err)
3126 goto unlock;
3127
3128 /* Setup PTP Hardware Clock and timestamping */
3129 if (chip->info->ptp_support) {
3130 err = mv88e6xxx_ptp_setup(chip);
3131 if (err)
3132 goto unlock;
3133
3134 err = mv88e6xxx_hwtstamp_setup(chip);
3135 if (err)
3136 goto unlock;
3137 }
3138
3139 err = mv88e6xxx_stats_setup(chip);
3140 if (err)
3141 goto unlock;
3142
3143unlock:
3144 mv88e6xxx_reg_unlock(chip);
3145
3146 if (err)
3147 return err;
3148
3149 /* Have to be called without holding the register lock, since
3150 * they take the devlink lock, and we later take the locks in
3151 * the reverse order when getting/setting parameters or
3152 * resource occupancy.
3153 */
3154 err = mv88e6xxx_setup_devlink_resources(ds);
3155 if (err)
3156 return err;
3157
3158 err = mv88e6xxx_setup_devlink_params(ds);
3159 if (err)
3160 goto out_resources;
3161
3162 err = mv88e6xxx_setup_devlink_regions_global(ds);
3163 if (err)
3164 goto out_params;
3165
3166 return 0;
3167
3168out_params:
3169 mv88e6xxx_teardown_devlink_params(ds);
3170out_resources:
3171 dsa_devlink_resources_unregister(ds);
3172
3173 return err;
3174}
3175
3176static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
3177{
3178 return mv88e6xxx_setup_devlink_regions_port(ds, port);
3179}
3180
3181static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
3182{
3183 mv88e6xxx_teardown_devlink_regions_port(ds, port);
3184}
3185
3186/* prod_id for switch families which do not have a PHY model number */
3187static const u16 family_prod_id_table[] = {
3188 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3189 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3190 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
3191};
3192
3193static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3194{
3195 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3196 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3197 u16 prod_id;
3198 u16 val;
3199 int err;
3200
3201 if (!chip->info->ops->phy_read)
3202 return -EOPNOTSUPP;
3203
3204 mv88e6xxx_reg_lock(chip);
3205 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3206 mv88e6xxx_reg_unlock(chip);
3207
3208 /* Some internal PHYs don't have a model number. */
3209 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3210 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3211 prod_id = family_prod_id_table[chip->info->family];
3212 if (prod_id)
3213 val |= prod_id >> 4;
3214 }
3215
3216 return err ? err : val;
3217}
3218
3219static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3220{
3221 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3222 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3223 int err;
3224
3225 if (!chip->info->ops->phy_write)
3226 return -EOPNOTSUPP;
3227
3228 mv88e6xxx_reg_lock(chip);
3229 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3230 mv88e6xxx_reg_unlock(chip);
3231
3232 return err;
3233}
3234
3235static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3236 struct device_node *np,
3237 bool external)
3238{
3239 static int index;
3240 struct mv88e6xxx_mdio_bus *mdio_bus;
3241 struct mii_bus *bus;
3242 int err;
3243
3244 if (external) {
3245 mv88e6xxx_reg_lock(chip);
3246 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3247 mv88e6xxx_reg_unlock(chip);
3248
3249 if (err)
3250 return err;
3251 }
3252
3253 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
3254 if (!bus)
3255 return -ENOMEM;
3256
3257 mdio_bus = bus->priv;
3258 mdio_bus->bus = bus;
3259 mdio_bus->chip = chip;
3260 INIT_LIST_HEAD(&mdio_bus->list);
3261 mdio_bus->external = external;
3262
3263 if (np) {
3264 bus->name = np->full_name;
3265 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3266 } else {
3267 bus->name = "mv88e6xxx SMI";
3268 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3269 }
3270
3271 bus->read = mv88e6xxx_mdio_read;
3272 bus->write = mv88e6xxx_mdio_write;
3273 bus->parent = chip->dev;
3274
3275 if (!external) {
3276 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3277 if (err)
3278 return err;
3279 }
3280
3281 err = of_mdiobus_register(bus, np);
3282 if (err) {
3283 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3284 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3285 return err;
3286 }
3287
3288 if (external)
3289 list_add_tail(&mdio_bus->list, &chip->mdios);
3290 else
3291 list_add(&mdio_bus->list, &chip->mdios);
3292
3293 return 0;
3294}
3295
3296static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3297
3298{
3299 struct mv88e6xxx_mdio_bus *mdio_bus;
3300 struct mii_bus *bus;
3301
3302 list_for_each_entry(mdio_bus, &chip->mdios, list) {
3303 bus = mdio_bus->bus;
3304
3305 if (!mdio_bus->external)
3306 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3307
3308 mdiobus_unregister(bus);
3309 }
3310}
3311
3312static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3313 struct device_node *np)
3314{
3315 struct device_node *child;
3316 int err;
3317
3318 /* Always register one mdio bus for the internal/default mdio
3319 * bus. This maybe represented in the device tree, but is
3320 * optional.
3321 */
3322 child = of_get_child_by_name(np, "mdio");
3323 err = mv88e6xxx_mdio_register(chip, child, false);
3324 if (err)
3325 return err;
3326
3327 /* Walk the device tree, and see if there are any other nodes
3328 * which say they are compatible with the external mdio
3329 * bus.
3330 */
3331 for_each_available_child_of_node(np, child) {
3332 if (of_device_is_compatible(
3333 child, "marvell,mv88e6xxx-mdio-external")) {
3334 err = mv88e6xxx_mdio_register(chip, child, true);
3335 if (err) {
3336 mv88e6xxx_mdios_unregister(chip);
3337 of_node_put(child);
3338 return err;
3339 }
3340 }
3341 }
3342
3343 return 0;
3344}
3345
3346static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3347{
3348 struct mv88e6xxx_chip *chip = ds->priv;
3349
3350 return chip->eeprom_len;
3351}
3352
3353static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3354 struct ethtool_eeprom *eeprom, u8 *data)
3355{
3356 struct mv88e6xxx_chip *chip = ds->priv;
3357 int err;
3358
3359 if (!chip->info->ops->get_eeprom)
3360 return -EOPNOTSUPP;
3361
3362 mv88e6xxx_reg_lock(chip);
3363 err = chip->info->ops->get_eeprom(chip, eeprom, data);
3364 mv88e6xxx_reg_unlock(chip);
3365
3366 if (err)
3367 return err;
3368
3369 eeprom->magic = 0xc3ec4951;
3370
3371 return 0;
3372}
3373
3374static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3375 struct ethtool_eeprom *eeprom, u8 *data)
3376{
3377 struct mv88e6xxx_chip *chip = ds->priv;
3378 int err;
3379
3380 if (!chip->info->ops->set_eeprom)
3381 return -EOPNOTSUPP;
3382
3383 if (eeprom->magic != 0xc3ec4951)
3384 return -EINVAL;
3385
3386 mv88e6xxx_reg_lock(chip);
3387 err = chip->info->ops->set_eeprom(chip, eeprom, data);
3388 mv88e6xxx_reg_unlock(chip);
3389
3390 return err;
3391}
3392
3393static const struct mv88e6xxx_ops mv88e6085_ops = {
3394 /* MV88E6XXX_FAMILY_6097 */
3395 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3396 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3397 .irl_init_all = mv88e6352_g2_irl_init_all,
3398 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3399 .phy_read = mv88e6185_phy_ppu_read,
3400 .phy_write = mv88e6185_phy_ppu_write,
3401 .port_set_link = mv88e6xxx_port_set_link,
3402 .port_sync_link = mv88e6xxx_port_sync_link,
3403 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3404 .port_tag_remap = mv88e6095_port_tag_remap,
3405 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3406 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3407 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3408 .port_set_ether_type = mv88e6351_port_set_ether_type,
3409 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3410 .port_pause_limit = mv88e6097_port_pause_limit,
3411 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3412 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3413 .port_get_cmode = mv88e6185_port_get_cmode,
3414 .port_setup_message_port = mv88e6xxx_setup_message_port,
3415 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3416 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3417 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3418 .stats_get_strings = mv88e6095_stats_get_strings,
3419 .stats_get_stats = mv88e6095_stats_get_stats,
3420 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3421 .set_egress_port = mv88e6095_g1_set_egress_port,
3422 .watchdog_ops = &mv88e6097_watchdog_ops,
3423 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3424 .pot_clear = mv88e6xxx_g2_pot_clear,
3425 .ppu_enable = mv88e6185_g1_ppu_enable,
3426 .ppu_disable = mv88e6185_g1_ppu_disable,
3427 .reset = mv88e6185_g1_reset,
3428 .rmu_disable = mv88e6085_g1_rmu_disable,
3429 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3430 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3431 .phylink_validate = mv88e6185_phylink_validate,
3432 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3433};
3434
3435static const struct mv88e6xxx_ops mv88e6095_ops = {
3436 /* MV88E6XXX_FAMILY_6095 */
3437 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3438 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3439 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3440 .phy_read = mv88e6185_phy_ppu_read,
3441 .phy_write = mv88e6185_phy_ppu_write,
3442 .port_set_link = mv88e6xxx_port_set_link,
3443 .port_sync_link = mv88e6185_port_sync_link,
3444 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3445 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3446 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3447 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
3448 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3449 .port_get_cmode = mv88e6185_port_get_cmode,
3450 .port_setup_message_port = mv88e6xxx_setup_message_port,
3451 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3452 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3453 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3454 .stats_get_strings = mv88e6095_stats_get_strings,
3455 .stats_get_stats = mv88e6095_stats_get_stats,
3456 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3457 .serdes_power = mv88e6185_serdes_power,
3458 .serdes_get_lane = mv88e6185_serdes_get_lane,
3459 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
3460 .ppu_enable = mv88e6185_g1_ppu_enable,
3461 .ppu_disable = mv88e6185_g1_ppu_disable,
3462 .reset = mv88e6185_g1_reset,
3463 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3464 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3465 .phylink_validate = mv88e6185_phylink_validate,
3466 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3467};
3468
3469static const struct mv88e6xxx_ops mv88e6097_ops = {
3470 /* MV88E6XXX_FAMILY_6097 */
3471 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3472 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3473 .irl_init_all = mv88e6352_g2_irl_init_all,
3474 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3475 .phy_read = mv88e6xxx_g2_smi_phy_read,
3476 .phy_write = mv88e6xxx_g2_smi_phy_write,
3477 .port_set_link = mv88e6xxx_port_set_link,
3478 .port_sync_link = mv88e6185_port_sync_link,
3479 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3480 .port_tag_remap = mv88e6095_port_tag_remap,
3481 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3482 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3483 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3484 .port_set_ether_type = mv88e6351_port_set_ether_type,
3485 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3486 .port_pause_limit = mv88e6097_port_pause_limit,
3487 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3488 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3489 .port_get_cmode = mv88e6185_port_get_cmode,
3490 .port_setup_message_port = mv88e6xxx_setup_message_port,
3491 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3492 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3493 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3494 .stats_get_strings = mv88e6095_stats_get_strings,
3495 .stats_get_stats = mv88e6095_stats_get_stats,
3496 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3497 .set_egress_port = mv88e6095_g1_set_egress_port,
3498 .watchdog_ops = &mv88e6097_watchdog_ops,
3499 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3500 .serdes_power = mv88e6185_serdes_power,
3501 .serdes_get_lane = mv88e6185_serdes_get_lane,
3502 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
3503 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3504 .serdes_irq_enable = mv88e6097_serdes_irq_enable,
3505 .serdes_irq_status = mv88e6097_serdes_irq_status,
3506 .pot_clear = mv88e6xxx_g2_pot_clear,
3507 .reset = mv88e6352_g1_reset,
3508 .rmu_disable = mv88e6085_g1_rmu_disable,
3509 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3510 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3511 .phylink_validate = mv88e6185_phylink_validate,
3512 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3513};
3514
3515static const struct mv88e6xxx_ops mv88e6123_ops = {
3516 /* MV88E6XXX_FAMILY_6165 */
3517 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3518 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3519 .irl_init_all = mv88e6352_g2_irl_init_all,
3520 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3521 .phy_read = mv88e6xxx_g2_smi_phy_read,
3522 .phy_write = mv88e6xxx_g2_smi_phy_write,
3523 .port_set_link = mv88e6xxx_port_set_link,
3524 .port_sync_link = mv88e6xxx_port_sync_link,
3525 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3526 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3527 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3528 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3529 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3530 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3531 .port_get_cmode = mv88e6185_port_get_cmode,
3532 .port_setup_message_port = mv88e6xxx_setup_message_port,
3533 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3534 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3535 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3536 .stats_get_strings = mv88e6095_stats_get_strings,
3537 .stats_get_stats = mv88e6095_stats_get_stats,
3538 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3539 .set_egress_port = mv88e6095_g1_set_egress_port,
3540 .watchdog_ops = &mv88e6097_watchdog_ops,
3541 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3542 .pot_clear = mv88e6xxx_g2_pot_clear,
3543 .reset = mv88e6352_g1_reset,
3544 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3545 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3546 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3547 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3548 .phylink_validate = mv88e6185_phylink_validate,
3549 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3550};
3551
3552static const struct mv88e6xxx_ops mv88e6131_ops = {
3553 /* MV88E6XXX_FAMILY_6185 */
3554 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3555 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3556 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3557 .phy_read = mv88e6185_phy_ppu_read,
3558 .phy_write = mv88e6185_phy_ppu_write,
3559 .port_set_link = mv88e6xxx_port_set_link,
3560 .port_sync_link = mv88e6xxx_port_sync_link,
3561 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3562 .port_tag_remap = mv88e6095_port_tag_remap,
3563 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3564 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3565 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
3566 .port_set_ether_type = mv88e6351_port_set_ether_type,
3567 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3568 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3569 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3570 .port_pause_limit = mv88e6097_port_pause_limit,
3571 .port_set_pause = mv88e6185_port_set_pause,
3572 .port_get_cmode = mv88e6185_port_get_cmode,
3573 .port_setup_message_port = mv88e6xxx_setup_message_port,
3574 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3575 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3576 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3577 .stats_get_strings = mv88e6095_stats_get_strings,
3578 .stats_get_stats = mv88e6095_stats_get_stats,
3579 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3580 .set_egress_port = mv88e6095_g1_set_egress_port,
3581 .watchdog_ops = &mv88e6097_watchdog_ops,
3582 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3583 .ppu_enable = mv88e6185_g1_ppu_enable,
3584 .set_cascade_port = mv88e6185_g1_set_cascade_port,
3585 .ppu_disable = mv88e6185_g1_ppu_disable,
3586 .reset = mv88e6185_g1_reset,
3587 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3588 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3589 .phylink_validate = mv88e6185_phylink_validate,
3590};
3591
3592static const struct mv88e6xxx_ops mv88e6141_ops = {
3593 /* MV88E6XXX_FAMILY_6341 */
3594 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3595 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3596 .irl_init_all = mv88e6352_g2_irl_init_all,
3597 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3598 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3599 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3600 .phy_read = mv88e6xxx_g2_smi_phy_read,
3601 .phy_write = mv88e6xxx_g2_smi_phy_write,
3602 .port_set_link = mv88e6xxx_port_set_link,
3603 .port_sync_link = mv88e6xxx_port_sync_link,
3604 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3605 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
3606 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
3607 .port_tag_remap = mv88e6095_port_tag_remap,
3608 .port_set_policy = mv88e6352_port_set_policy,
3609 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3610 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3611 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3612 .port_set_ether_type = mv88e6351_port_set_ether_type,
3613 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3614 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3615 .port_pause_limit = mv88e6097_port_pause_limit,
3616 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3617 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3618 .port_get_cmode = mv88e6352_port_get_cmode,
3619 .port_set_cmode = mv88e6341_port_set_cmode,
3620 .port_setup_message_port = mv88e6xxx_setup_message_port,
3621 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3622 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3623 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3624 .stats_get_strings = mv88e6320_stats_get_strings,
3625 .stats_get_stats = mv88e6390_stats_get_stats,
3626 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3627 .set_egress_port = mv88e6390_g1_set_egress_port,
3628 .watchdog_ops = &mv88e6390_watchdog_ops,
3629 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3630 .pot_clear = mv88e6xxx_g2_pot_clear,
3631 .reset = mv88e6352_g1_reset,
3632 .rmu_disable = mv88e6390_g1_rmu_disable,
3633 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3634 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3635 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3636 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3637 .serdes_power = mv88e6390_serdes_power,
3638 .serdes_get_lane = mv88e6341_serdes_get_lane,
3639 /* Check status register pause & lpa register */
3640 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3641 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3642 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3643 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3644 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3645 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3646 .serdes_irq_status = mv88e6390_serdes_irq_status,
3647 .gpio_ops = &mv88e6352_gpio_ops,
3648 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
3649 .serdes_get_strings = mv88e6390_serdes_get_strings,
3650 .serdes_get_stats = mv88e6390_serdes_get_stats,
3651 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3652 .serdes_get_regs = mv88e6390_serdes_get_regs,
3653 .phylink_validate = mv88e6341_phylink_validate,
3654};
3655
3656static const struct mv88e6xxx_ops mv88e6161_ops = {
3657 /* MV88E6XXX_FAMILY_6165 */
3658 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3659 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3660 .irl_init_all = mv88e6352_g2_irl_init_all,
3661 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3662 .phy_read = mv88e6xxx_g2_smi_phy_read,
3663 .phy_write = mv88e6xxx_g2_smi_phy_write,
3664 .port_set_link = mv88e6xxx_port_set_link,
3665 .port_sync_link = mv88e6xxx_port_sync_link,
3666 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3667 .port_tag_remap = mv88e6095_port_tag_remap,
3668 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3669 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3670 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3671 .port_set_ether_type = mv88e6351_port_set_ether_type,
3672 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3673 .port_pause_limit = mv88e6097_port_pause_limit,
3674 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3675 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3676 .port_get_cmode = mv88e6185_port_get_cmode,
3677 .port_setup_message_port = mv88e6xxx_setup_message_port,
3678 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3679 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3680 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3681 .stats_get_strings = mv88e6095_stats_get_strings,
3682 .stats_get_stats = mv88e6095_stats_get_stats,
3683 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3684 .set_egress_port = mv88e6095_g1_set_egress_port,
3685 .watchdog_ops = &mv88e6097_watchdog_ops,
3686 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3687 .pot_clear = mv88e6xxx_g2_pot_clear,
3688 .reset = mv88e6352_g1_reset,
3689 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3690 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3691 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3692 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3693 .avb_ops = &mv88e6165_avb_ops,
3694 .ptp_ops = &mv88e6165_ptp_ops,
3695 .phylink_validate = mv88e6185_phylink_validate,
3696 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3697};
3698
3699static const struct mv88e6xxx_ops mv88e6165_ops = {
3700 /* MV88E6XXX_FAMILY_6165 */
3701 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3702 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3703 .irl_init_all = mv88e6352_g2_irl_init_all,
3704 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3705 .phy_read = mv88e6165_phy_read,
3706 .phy_write = mv88e6165_phy_write,
3707 .port_set_link = mv88e6xxx_port_set_link,
3708 .port_sync_link = mv88e6xxx_port_sync_link,
3709 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3710 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3711 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3712 .port_get_cmode = mv88e6185_port_get_cmode,
3713 .port_setup_message_port = mv88e6xxx_setup_message_port,
3714 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3715 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3716 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3717 .stats_get_strings = mv88e6095_stats_get_strings,
3718 .stats_get_stats = mv88e6095_stats_get_stats,
3719 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3720 .set_egress_port = mv88e6095_g1_set_egress_port,
3721 .watchdog_ops = &mv88e6097_watchdog_ops,
3722 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3723 .pot_clear = mv88e6xxx_g2_pot_clear,
3724 .reset = mv88e6352_g1_reset,
3725 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3726 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3727 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3728 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3729 .avb_ops = &mv88e6165_avb_ops,
3730 .ptp_ops = &mv88e6165_ptp_ops,
3731 .phylink_validate = mv88e6185_phylink_validate,
3732};
3733
3734static const struct mv88e6xxx_ops mv88e6171_ops = {
3735 /* MV88E6XXX_FAMILY_6351 */
3736 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3737 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3738 .irl_init_all = mv88e6352_g2_irl_init_all,
3739 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3740 .phy_read = mv88e6xxx_g2_smi_phy_read,
3741 .phy_write = mv88e6xxx_g2_smi_phy_write,
3742 .port_set_link = mv88e6xxx_port_set_link,
3743 .port_sync_link = mv88e6xxx_port_sync_link,
3744 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3745 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3746 .port_tag_remap = mv88e6095_port_tag_remap,
3747 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3748 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3749 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3750 .port_set_ether_type = mv88e6351_port_set_ether_type,
3751 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3752 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3753 .port_pause_limit = mv88e6097_port_pause_limit,
3754 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3755 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3756 .port_get_cmode = mv88e6352_port_get_cmode,
3757 .port_setup_message_port = mv88e6xxx_setup_message_port,
3758 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3759 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3760 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3761 .stats_get_strings = mv88e6095_stats_get_strings,
3762 .stats_get_stats = mv88e6095_stats_get_stats,
3763 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3764 .set_egress_port = mv88e6095_g1_set_egress_port,
3765 .watchdog_ops = &mv88e6097_watchdog_ops,
3766 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3767 .pot_clear = mv88e6xxx_g2_pot_clear,
3768 .reset = mv88e6352_g1_reset,
3769 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3770 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3771 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3772 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3773 .phylink_validate = mv88e6185_phylink_validate,
3774};
3775
3776static const struct mv88e6xxx_ops mv88e6172_ops = {
3777 /* MV88E6XXX_FAMILY_6352 */
3778 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3779 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3780 .irl_init_all = mv88e6352_g2_irl_init_all,
3781 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3782 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3783 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3784 .phy_read = mv88e6xxx_g2_smi_phy_read,
3785 .phy_write = mv88e6xxx_g2_smi_phy_write,
3786 .port_set_link = mv88e6xxx_port_set_link,
3787 .port_sync_link = mv88e6xxx_port_sync_link,
3788 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3789 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3790 .port_tag_remap = mv88e6095_port_tag_remap,
3791 .port_set_policy = mv88e6352_port_set_policy,
3792 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3793 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3794 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3795 .port_set_ether_type = mv88e6351_port_set_ether_type,
3796 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3797 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3798 .port_pause_limit = mv88e6097_port_pause_limit,
3799 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3800 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3801 .port_get_cmode = mv88e6352_port_get_cmode,
3802 .port_setup_message_port = mv88e6xxx_setup_message_port,
3803 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3804 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3805 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3806 .stats_get_strings = mv88e6095_stats_get_strings,
3807 .stats_get_stats = mv88e6095_stats_get_stats,
3808 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3809 .set_egress_port = mv88e6095_g1_set_egress_port,
3810 .watchdog_ops = &mv88e6097_watchdog_ops,
3811 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3812 .pot_clear = mv88e6xxx_g2_pot_clear,
3813 .reset = mv88e6352_g1_reset,
3814 .rmu_disable = mv88e6352_g1_rmu_disable,
3815 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3816 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3817 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3818 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3819 .serdes_get_lane = mv88e6352_serdes_get_lane,
3820 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3821 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3822 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3823 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3824 .serdes_power = mv88e6352_serdes_power,
3825 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3826 .serdes_get_regs = mv88e6352_serdes_get_regs,
3827 .gpio_ops = &mv88e6352_gpio_ops,
3828 .phylink_validate = mv88e6352_phylink_validate,
3829};
3830
3831static const struct mv88e6xxx_ops mv88e6175_ops = {
3832 /* MV88E6XXX_FAMILY_6351 */
3833 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3834 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3835 .irl_init_all = mv88e6352_g2_irl_init_all,
3836 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3837 .phy_read = mv88e6xxx_g2_smi_phy_read,
3838 .phy_write = mv88e6xxx_g2_smi_phy_write,
3839 .port_set_link = mv88e6xxx_port_set_link,
3840 .port_sync_link = mv88e6xxx_port_sync_link,
3841 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3842 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3843 .port_tag_remap = mv88e6095_port_tag_remap,
3844 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3845 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3846 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3847 .port_set_ether_type = mv88e6351_port_set_ether_type,
3848 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3849 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3850 .port_pause_limit = mv88e6097_port_pause_limit,
3851 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3852 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3853 .port_get_cmode = mv88e6352_port_get_cmode,
3854 .port_setup_message_port = mv88e6xxx_setup_message_port,
3855 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3856 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3857 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3858 .stats_get_strings = mv88e6095_stats_get_strings,
3859 .stats_get_stats = mv88e6095_stats_get_stats,
3860 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3861 .set_egress_port = mv88e6095_g1_set_egress_port,
3862 .watchdog_ops = &mv88e6097_watchdog_ops,
3863 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3864 .pot_clear = mv88e6xxx_g2_pot_clear,
3865 .reset = mv88e6352_g1_reset,
3866 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3867 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3868 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3869 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3870 .phylink_validate = mv88e6185_phylink_validate,
3871};
3872
3873static const struct mv88e6xxx_ops mv88e6176_ops = {
3874 /* MV88E6XXX_FAMILY_6352 */
3875 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3876 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3877 .irl_init_all = mv88e6352_g2_irl_init_all,
3878 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3879 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3880 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3881 .phy_read = mv88e6xxx_g2_smi_phy_read,
3882 .phy_write = mv88e6xxx_g2_smi_phy_write,
3883 .port_set_link = mv88e6xxx_port_set_link,
3884 .port_sync_link = mv88e6xxx_port_sync_link,
3885 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3886 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3887 .port_tag_remap = mv88e6095_port_tag_remap,
3888 .port_set_policy = mv88e6352_port_set_policy,
3889 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3890 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3891 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3892 .port_set_ether_type = mv88e6351_port_set_ether_type,
3893 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3894 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3895 .port_pause_limit = mv88e6097_port_pause_limit,
3896 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3897 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3898 .port_get_cmode = mv88e6352_port_get_cmode,
3899 .port_setup_message_port = mv88e6xxx_setup_message_port,
3900 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3901 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3902 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3903 .stats_get_strings = mv88e6095_stats_get_strings,
3904 .stats_get_stats = mv88e6095_stats_get_stats,
3905 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3906 .set_egress_port = mv88e6095_g1_set_egress_port,
3907 .watchdog_ops = &mv88e6097_watchdog_ops,
3908 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3909 .pot_clear = mv88e6xxx_g2_pot_clear,
3910 .reset = mv88e6352_g1_reset,
3911 .rmu_disable = mv88e6352_g1_rmu_disable,
3912 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3913 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3914 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3915 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3916 .serdes_get_lane = mv88e6352_serdes_get_lane,
3917 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3918 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3919 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3920 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3921 .serdes_power = mv88e6352_serdes_power,
3922 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
3923 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
3924 .serdes_irq_status = mv88e6352_serdes_irq_status,
3925 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3926 .serdes_get_regs = mv88e6352_serdes_get_regs,
3927 .gpio_ops = &mv88e6352_gpio_ops,
3928 .phylink_validate = mv88e6352_phylink_validate,
3929};
3930
3931static const struct mv88e6xxx_ops mv88e6185_ops = {
3932 /* MV88E6XXX_FAMILY_6185 */
3933 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3934 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3935 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3936 .phy_read = mv88e6185_phy_ppu_read,
3937 .phy_write = mv88e6185_phy_ppu_write,
3938 .port_set_link = mv88e6xxx_port_set_link,
3939 .port_sync_link = mv88e6185_port_sync_link,
3940 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3941 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3942 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3943 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
3944 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3945 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3946 .port_set_pause = mv88e6185_port_set_pause,
3947 .port_get_cmode = mv88e6185_port_get_cmode,
3948 .port_setup_message_port = mv88e6xxx_setup_message_port,
3949 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3950 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3951 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3952 .stats_get_strings = mv88e6095_stats_get_strings,
3953 .stats_get_stats = mv88e6095_stats_get_stats,
3954 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3955 .set_egress_port = mv88e6095_g1_set_egress_port,
3956 .watchdog_ops = &mv88e6097_watchdog_ops,
3957 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3958 .serdes_power = mv88e6185_serdes_power,
3959 .serdes_get_lane = mv88e6185_serdes_get_lane,
3960 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
3961 .set_cascade_port = mv88e6185_g1_set_cascade_port,
3962 .ppu_enable = mv88e6185_g1_ppu_enable,
3963 .ppu_disable = mv88e6185_g1_ppu_disable,
3964 .reset = mv88e6185_g1_reset,
3965 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3966 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3967 .phylink_validate = mv88e6185_phylink_validate,
3968 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3969};
3970
3971static const struct mv88e6xxx_ops mv88e6190_ops = {
3972 /* MV88E6XXX_FAMILY_6390 */
3973 .setup_errata = mv88e6390_setup_errata,
3974 .irl_init_all = mv88e6390_g2_irl_init_all,
3975 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3976 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3977 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3978 .phy_read = mv88e6xxx_g2_smi_phy_read,
3979 .phy_write = mv88e6xxx_g2_smi_phy_write,
3980 .port_set_link = mv88e6xxx_port_set_link,
3981 .port_sync_link = mv88e6xxx_port_sync_link,
3982 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3983 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
3984 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3985 .port_tag_remap = mv88e6390_port_tag_remap,
3986 .port_set_policy = mv88e6352_port_set_policy,
3987 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3988 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3989 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3990 .port_set_ether_type = mv88e6351_port_set_ether_type,
3991 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3992 .port_pause_limit = mv88e6390_port_pause_limit,
3993 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3994 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3995 .port_get_cmode = mv88e6352_port_get_cmode,
3996 .port_set_cmode = mv88e6390_port_set_cmode,
3997 .port_setup_message_port = mv88e6xxx_setup_message_port,
3998 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3999 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4000 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4001 .stats_get_strings = mv88e6320_stats_get_strings,
4002 .stats_get_stats = mv88e6390_stats_get_stats,
4003 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4004 .set_egress_port = mv88e6390_g1_set_egress_port,
4005 .watchdog_ops = &mv88e6390_watchdog_ops,
4006 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4007 .pot_clear = mv88e6xxx_g2_pot_clear,
4008 .reset = mv88e6352_g1_reset,
4009 .rmu_disable = mv88e6390_g1_rmu_disable,
4010 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4011 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4012 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4013 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4014 .serdes_power = mv88e6390_serdes_power,
4015 .serdes_get_lane = mv88e6390_serdes_get_lane,
4016 /* Check status register pause & lpa register */
4017 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4018 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4019 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4020 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4021 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4022 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4023 .serdes_irq_status = mv88e6390_serdes_irq_status,
4024 .serdes_get_strings = mv88e6390_serdes_get_strings,
4025 .serdes_get_stats = mv88e6390_serdes_get_stats,
4026 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4027 .serdes_get_regs = mv88e6390_serdes_get_regs,
4028 .gpio_ops = &mv88e6352_gpio_ops,
4029 .phylink_validate = mv88e6390_phylink_validate,
4030};
4031
4032static const struct mv88e6xxx_ops mv88e6190x_ops = {
4033 /* MV88E6XXX_FAMILY_6390 */
4034 .setup_errata = mv88e6390_setup_errata,
4035 .irl_init_all = mv88e6390_g2_irl_init_all,
4036 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4037 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4038 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4039 .phy_read = mv88e6xxx_g2_smi_phy_read,
4040 .phy_write = mv88e6xxx_g2_smi_phy_write,
4041 .port_set_link = mv88e6xxx_port_set_link,
4042 .port_sync_link = mv88e6xxx_port_sync_link,
4043 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4044 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4045 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4046 .port_tag_remap = mv88e6390_port_tag_remap,
4047 .port_set_policy = mv88e6352_port_set_policy,
4048 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4049 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4050 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4051 .port_set_ether_type = mv88e6351_port_set_ether_type,
4052 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4053 .port_pause_limit = mv88e6390_port_pause_limit,
4054 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4055 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4056 .port_get_cmode = mv88e6352_port_get_cmode,
4057 .port_set_cmode = mv88e6390x_port_set_cmode,
4058 .port_setup_message_port = mv88e6xxx_setup_message_port,
4059 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4060 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4061 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4062 .stats_get_strings = mv88e6320_stats_get_strings,
4063 .stats_get_stats = mv88e6390_stats_get_stats,
4064 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4065 .set_egress_port = mv88e6390_g1_set_egress_port,
4066 .watchdog_ops = &mv88e6390_watchdog_ops,
4067 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4068 .pot_clear = mv88e6xxx_g2_pot_clear,
4069 .reset = mv88e6352_g1_reset,
4070 .rmu_disable = mv88e6390_g1_rmu_disable,
4071 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4072 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4073 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4074 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4075 .serdes_power = mv88e6390_serdes_power,
4076 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4077 /* Check status register pause & lpa register */
4078 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4079 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4080 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4081 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4082 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4083 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4084 .serdes_irq_status = mv88e6390_serdes_irq_status,
4085 .serdes_get_strings = mv88e6390_serdes_get_strings,
4086 .serdes_get_stats = mv88e6390_serdes_get_stats,
4087 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4088 .serdes_get_regs = mv88e6390_serdes_get_regs,
4089 .gpio_ops = &mv88e6352_gpio_ops,
4090 .phylink_validate = mv88e6390x_phylink_validate,
4091};
4092
4093static const struct mv88e6xxx_ops mv88e6191_ops = {
4094 /* MV88E6XXX_FAMILY_6390 */
4095 .setup_errata = mv88e6390_setup_errata,
4096 .irl_init_all = mv88e6390_g2_irl_init_all,
4097 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4098 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4099 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4100 .phy_read = mv88e6xxx_g2_smi_phy_read,
4101 .phy_write = mv88e6xxx_g2_smi_phy_write,
4102 .port_set_link = mv88e6xxx_port_set_link,
4103 .port_sync_link = mv88e6xxx_port_sync_link,
4104 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4105 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4106 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4107 .port_tag_remap = mv88e6390_port_tag_remap,
4108 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4109 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4110 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4111 .port_set_ether_type = mv88e6351_port_set_ether_type,
4112 .port_pause_limit = mv88e6390_port_pause_limit,
4113 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4114 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4115 .port_get_cmode = mv88e6352_port_get_cmode,
4116 .port_set_cmode = mv88e6390_port_set_cmode,
4117 .port_setup_message_port = mv88e6xxx_setup_message_port,
4118 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4119 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4120 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4121 .stats_get_strings = mv88e6320_stats_get_strings,
4122 .stats_get_stats = mv88e6390_stats_get_stats,
4123 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4124 .set_egress_port = mv88e6390_g1_set_egress_port,
4125 .watchdog_ops = &mv88e6390_watchdog_ops,
4126 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4127 .pot_clear = mv88e6xxx_g2_pot_clear,
4128 .reset = mv88e6352_g1_reset,
4129 .rmu_disable = mv88e6390_g1_rmu_disable,
4130 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4131 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4132 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4133 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4134 .serdes_power = mv88e6390_serdes_power,
4135 .serdes_get_lane = mv88e6390_serdes_get_lane,
4136 /* Check status register pause & lpa register */
4137 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4138 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4139 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4140 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4141 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4142 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4143 .serdes_irq_status = mv88e6390_serdes_irq_status,
4144 .serdes_get_strings = mv88e6390_serdes_get_strings,
4145 .serdes_get_stats = mv88e6390_serdes_get_stats,
4146 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4147 .serdes_get_regs = mv88e6390_serdes_get_regs,
4148 .avb_ops = &mv88e6390_avb_ops,
4149 .ptp_ops = &mv88e6352_ptp_ops,
4150 .phylink_validate = mv88e6390_phylink_validate,
4151};
4152
4153static const struct mv88e6xxx_ops mv88e6240_ops = {
4154 /* MV88E6XXX_FAMILY_6352 */
4155 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4156 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4157 .irl_init_all = mv88e6352_g2_irl_init_all,
4158 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4159 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4160 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4161 .phy_read = mv88e6xxx_g2_smi_phy_read,
4162 .phy_write = mv88e6xxx_g2_smi_phy_write,
4163 .port_set_link = mv88e6xxx_port_set_link,
4164 .port_sync_link = mv88e6xxx_port_sync_link,
4165 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4166 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4167 .port_tag_remap = mv88e6095_port_tag_remap,
4168 .port_set_policy = mv88e6352_port_set_policy,
4169 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4170 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4171 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4172 .port_set_ether_type = mv88e6351_port_set_ether_type,
4173 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4174 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4175 .port_pause_limit = mv88e6097_port_pause_limit,
4176 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4177 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4178 .port_get_cmode = mv88e6352_port_get_cmode,
4179 .port_setup_message_port = mv88e6xxx_setup_message_port,
4180 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4181 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4182 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4183 .stats_get_strings = mv88e6095_stats_get_strings,
4184 .stats_get_stats = mv88e6095_stats_get_stats,
4185 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4186 .set_egress_port = mv88e6095_g1_set_egress_port,
4187 .watchdog_ops = &mv88e6097_watchdog_ops,
4188 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4189 .pot_clear = mv88e6xxx_g2_pot_clear,
4190 .reset = mv88e6352_g1_reset,
4191 .rmu_disable = mv88e6352_g1_rmu_disable,
4192 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4193 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4194 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4195 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4196 .serdes_get_lane = mv88e6352_serdes_get_lane,
4197 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4198 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4199 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4200 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4201 .serdes_power = mv88e6352_serdes_power,
4202 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4203 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4204 .serdes_irq_status = mv88e6352_serdes_irq_status,
4205 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4206 .serdes_get_regs = mv88e6352_serdes_get_regs,
4207 .gpio_ops = &mv88e6352_gpio_ops,
4208 .avb_ops = &mv88e6352_avb_ops,
4209 .ptp_ops = &mv88e6352_ptp_ops,
4210 .phylink_validate = mv88e6352_phylink_validate,
4211};
4212
4213static const struct mv88e6xxx_ops mv88e6250_ops = {
4214 /* MV88E6XXX_FAMILY_6250 */
4215 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4216 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4217 .irl_init_all = mv88e6352_g2_irl_init_all,
4218 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4219 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4220 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4221 .phy_read = mv88e6xxx_g2_smi_phy_read,
4222 .phy_write = mv88e6xxx_g2_smi_phy_write,
4223 .port_set_link = mv88e6xxx_port_set_link,
4224 .port_sync_link = mv88e6xxx_port_sync_link,
4225 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4226 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
4227 .port_tag_remap = mv88e6095_port_tag_remap,
4228 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4229 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4230 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4231 .port_set_ether_type = mv88e6351_port_set_ether_type,
4232 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4233 .port_pause_limit = mv88e6097_port_pause_limit,
4234 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4235 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4236 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4237 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4238 .stats_get_strings = mv88e6250_stats_get_strings,
4239 .stats_get_stats = mv88e6250_stats_get_stats,
4240 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4241 .set_egress_port = mv88e6095_g1_set_egress_port,
4242 .watchdog_ops = &mv88e6250_watchdog_ops,
4243 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4244 .pot_clear = mv88e6xxx_g2_pot_clear,
4245 .reset = mv88e6250_g1_reset,
4246 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4247 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4248 .avb_ops = &mv88e6352_avb_ops,
4249 .ptp_ops = &mv88e6250_ptp_ops,
4250 .phylink_validate = mv88e6065_phylink_validate,
4251};
4252
4253static const struct mv88e6xxx_ops mv88e6290_ops = {
4254 /* MV88E6XXX_FAMILY_6390 */
4255 .setup_errata = mv88e6390_setup_errata,
4256 .irl_init_all = mv88e6390_g2_irl_init_all,
4257 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4258 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4259 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4260 .phy_read = mv88e6xxx_g2_smi_phy_read,
4261 .phy_write = mv88e6xxx_g2_smi_phy_write,
4262 .port_set_link = mv88e6xxx_port_set_link,
4263 .port_sync_link = mv88e6xxx_port_sync_link,
4264 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4265 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4266 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4267 .port_tag_remap = mv88e6390_port_tag_remap,
4268 .port_set_policy = mv88e6352_port_set_policy,
4269 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4270 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4271 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4272 .port_set_ether_type = mv88e6351_port_set_ether_type,
4273 .port_pause_limit = mv88e6390_port_pause_limit,
4274 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4275 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4276 .port_get_cmode = mv88e6352_port_get_cmode,
4277 .port_set_cmode = mv88e6390_port_set_cmode,
4278 .port_setup_message_port = mv88e6xxx_setup_message_port,
4279 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4280 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4281 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4282 .stats_get_strings = mv88e6320_stats_get_strings,
4283 .stats_get_stats = mv88e6390_stats_get_stats,
4284 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4285 .set_egress_port = mv88e6390_g1_set_egress_port,
4286 .watchdog_ops = &mv88e6390_watchdog_ops,
4287 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4288 .pot_clear = mv88e6xxx_g2_pot_clear,
4289 .reset = mv88e6352_g1_reset,
4290 .rmu_disable = mv88e6390_g1_rmu_disable,
4291 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4292 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4293 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4294 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4295 .serdes_power = mv88e6390_serdes_power,
4296 .serdes_get_lane = mv88e6390_serdes_get_lane,
4297 /* Check status register pause & lpa register */
4298 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4299 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4300 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4301 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4302 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4303 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4304 .serdes_irq_status = mv88e6390_serdes_irq_status,
4305 .serdes_get_strings = mv88e6390_serdes_get_strings,
4306 .serdes_get_stats = mv88e6390_serdes_get_stats,
4307 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4308 .serdes_get_regs = mv88e6390_serdes_get_regs,
4309 .gpio_ops = &mv88e6352_gpio_ops,
4310 .avb_ops = &mv88e6390_avb_ops,
4311 .ptp_ops = &mv88e6352_ptp_ops,
4312 .phylink_validate = mv88e6390_phylink_validate,
4313};
4314
4315static const struct mv88e6xxx_ops mv88e6320_ops = {
4316 /* MV88E6XXX_FAMILY_6320 */
4317 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4318 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4319 .irl_init_all = mv88e6352_g2_irl_init_all,
4320 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4321 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4322 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4323 .phy_read = mv88e6xxx_g2_smi_phy_read,
4324 .phy_write = mv88e6xxx_g2_smi_phy_write,
4325 .port_set_link = mv88e6xxx_port_set_link,
4326 .port_sync_link = mv88e6xxx_port_sync_link,
4327 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4328 .port_tag_remap = mv88e6095_port_tag_remap,
4329 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4330 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4331 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4332 .port_set_ether_type = mv88e6351_port_set_ether_type,
4333 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4334 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4335 .port_pause_limit = mv88e6097_port_pause_limit,
4336 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4337 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4338 .port_get_cmode = mv88e6352_port_get_cmode,
4339 .port_setup_message_port = mv88e6xxx_setup_message_port,
4340 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4341 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4342 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4343 .stats_get_strings = mv88e6320_stats_get_strings,
4344 .stats_get_stats = mv88e6320_stats_get_stats,
4345 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4346 .set_egress_port = mv88e6095_g1_set_egress_port,
4347 .watchdog_ops = &mv88e6390_watchdog_ops,
4348 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4349 .pot_clear = mv88e6xxx_g2_pot_clear,
4350 .reset = mv88e6352_g1_reset,
4351 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4352 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4353 .gpio_ops = &mv88e6352_gpio_ops,
4354 .avb_ops = &mv88e6352_avb_ops,
4355 .ptp_ops = &mv88e6352_ptp_ops,
4356 .phylink_validate = mv88e6185_phylink_validate,
4357};
4358
4359static const struct mv88e6xxx_ops mv88e6321_ops = {
4360 /* MV88E6XXX_FAMILY_6320 */
4361 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4362 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4363 .irl_init_all = mv88e6352_g2_irl_init_all,
4364 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4365 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4366 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4367 .phy_read = mv88e6xxx_g2_smi_phy_read,
4368 .phy_write = mv88e6xxx_g2_smi_phy_write,
4369 .port_set_link = mv88e6xxx_port_set_link,
4370 .port_sync_link = mv88e6xxx_port_sync_link,
4371 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4372 .port_tag_remap = mv88e6095_port_tag_remap,
4373 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4374 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4375 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4376 .port_set_ether_type = mv88e6351_port_set_ether_type,
4377 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4378 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4379 .port_pause_limit = mv88e6097_port_pause_limit,
4380 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4381 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4382 .port_get_cmode = mv88e6352_port_get_cmode,
4383 .port_setup_message_port = mv88e6xxx_setup_message_port,
4384 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4385 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4386 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4387 .stats_get_strings = mv88e6320_stats_get_strings,
4388 .stats_get_stats = mv88e6320_stats_get_stats,
4389 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4390 .set_egress_port = mv88e6095_g1_set_egress_port,
4391 .watchdog_ops = &mv88e6390_watchdog_ops,
4392 .reset = mv88e6352_g1_reset,
4393 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4394 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4395 .gpio_ops = &mv88e6352_gpio_ops,
4396 .avb_ops = &mv88e6352_avb_ops,
4397 .ptp_ops = &mv88e6352_ptp_ops,
4398 .phylink_validate = mv88e6185_phylink_validate,
4399};
4400
4401static const struct mv88e6xxx_ops mv88e6341_ops = {
4402 /* MV88E6XXX_FAMILY_6341 */
4403 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4404 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4405 .irl_init_all = mv88e6352_g2_irl_init_all,
4406 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4407 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4408 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4409 .phy_read = mv88e6xxx_g2_smi_phy_read,
4410 .phy_write = mv88e6xxx_g2_smi_phy_write,
4411 .port_set_link = mv88e6xxx_port_set_link,
4412 .port_sync_link = mv88e6xxx_port_sync_link,
4413 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4414 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4415 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4416 .port_tag_remap = mv88e6095_port_tag_remap,
4417 .port_set_policy = mv88e6352_port_set_policy,
4418 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4419 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4420 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4421 .port_set_ether_type = mv88e6351_port_set_ether_type,
4422 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4423 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4424 .port_pause_limit = mv88e6097_port_pause_limit,
4425 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4426 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4427 .port_get_cmode = mv88e6352_port_get_cmode,
4428 .port_set_cmode = mv88e6341_port_set_cmode,
4429 .port_setup_message_port = mv88e6xxx_setup_message_port,
4430 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4431 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4432 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4433 .stats_get_strings = mv88e6320_stats_get_strings,
4434 .stats_get_stats = mv88e6390_stats_get_stats,
4435 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4436 .set_egress_port = mv88e6390_g1_set_egress_port,
4437 .watchdog_ops = &mv88e6390_watchdog_ops,
4438 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4439 .pot_clear = mv88e6xxx_g2_pot_clear,
4440 .reset = mv88e6352_g1_reset,
4441 .rmu_disable = mv88e6390_g1_rmu_disable,
4442 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4443 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4444 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4445 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4446 .serdes_power = mv88e6390_serdes_power,
4447 .serdes_get_lane = mv88e6341_serdes_get_lane,
4448 /* Check status register pause & lpa register */
4449 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4450 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4451 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4452 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4453 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4454 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4455 .serdes_irq_status = mv88e6390_serdes_irq_status,
4456 .gpio_ops = &mv88e6352_gpio_ops,
4457 .avb_ops = &mv88e6390_avb_ops,
4458 .ptp_ops = &mv88e6352_ptp_ops,
4459 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4460 .serdes_get_strings = mv88e6390_serdes_get_strings,
4461 .serdes_get_stats = mv88e6390_serdes_get_stats,
4462 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4463 .serdes_get_regs = mv88e6390_serdes_get_regs,
4464 .phylink_validate = mv88e6341_phylink_validate,
4465};
4466
4467static const struct mv88e6xxx_ops mv88e6350_ops = {
4468 /* MV88E6XXX_FAMILY_6351 */
4469 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4470 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4471 .irl_init_all = mv88e6352_g2_irl_init_all,
4472 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4473 .phy_read = mv88e6xxx_g2_smi_phy_read,
4474 .phy_write = mv88e6xxx_g2_smi_phy_write,
4475 .port_set_link = mv88e6xxx_port_set_link,
4476 .port_sync_link = mv88e6xxx_port_sync_link,
4477 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4478 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4479 .port_tag_remap = mv88e6095_port_tag_remap,
4480 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4481 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4482 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4483 .port_set_ether_type = mv88e6351_port_set_ether_type,
4484 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4485 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4486 .port_pause_limit = mv88e6097_port_pause_limit,
4487 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4488 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4489 .port_get_cmode = mv88e6352_port_get_cmode,
4490 .port_setup_message_port = mv88e6xxx_setup_message_port,
4491 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4492 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4493 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4494 .stats_get_strings = mv88e6095_stats_get_strings,
4495 .stats_get_stats = mv88e6095_stats_get_stats,
4496 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4497 .set_egress_port = mv88e6095_g1_set_egress_port,
4498 .watchdog_ops = &mv88e6097_watchdog_ops,
4499 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4500 .pot_clear = mv88e6xxx_g2_pot_clear,
4501 .reset = mv88e6352_g1_reset,
4502 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4503 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4504 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4505 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4506 .phylink_validate = mv88e6185_phylink_validate,
4507};
4508
4509static const struct mv88e6xxx_ops mv88e6351_ops = {
4510 /* MV88E6XXX_FAMILY_6351 */
4511 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4512 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4513 .irl_init_all = mv88e6352_g2_irl_init_all,
4514 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4515 .phy_read = mv88e6xxx_g2_smi_phy_read,
4516 .phy_write = mv88e6xxx_g2_smi_phy_write,
4517 .port_set_link = mv88e6xxx_port_set_link,
4518 .port_sync_link = mv88e6xxx_port_sync_link,
4519 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4520 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4521 .port_tag_remap = mv88e6095_port_tag_remap,
4522 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4523 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4524 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4525 .port_set_ether_type = mv88e6351_port_set_ether_type,
4526 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4527 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4528 .port_pause_limit = mv88e6097_port_pause_limit,
4529 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4530 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4531 .port_get_cmode = mv88e6352_port_get_cmode,
4532 .port_setup_message_port = mv88e6xxx_setup_message_port,
4533 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4534 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4535 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4536 .stats_get_strings = mv88e6095_stats_get_strings,
4537 .stats_get_stats = mv88e6095_stats_get_stats,
4538 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4539 .set_egress_port = mv88e6095_g1_set_egress_port,
4540 .watchdog_ops = &mv88e6097_watchdog_ops,
4541 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4542 .pot_clear = mv88e6xxx_g2_pot_clear,
4543 .reset = mv88e6352_g1_reset,
4544 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4545 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4546 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4547 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4548 .avb_ops = &mv88e6352_avb_ops,
4549 .ptp_ops = &mv88e6352_ptp_ops,
4550 .phylink_validate = mv88e6185_phylink_validate,
4551};
4552
4553static const struct mv88e6xxx_ops mv88e6352_ops = {
4554 /* MV88E6XXX_FAMILY_6352 */
4555 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4556 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4557 .irl_init_all = mv88e6352_g2_irl_init_all,
4558 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4559 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4560 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4561 .phy_read = mv88e6xxx_g2_smi_phy_read,
4562 .phy_write = mv88e6xxx_g2_smi_phy_write,
4563 .port_set_link = mv88e6xxx_port_set_link,
4564 .port_sync_link = mv88e6xxx_port_sync_link,
4565 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4566 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4567 .port_tag_remap = mv88e6095_port_tag_remap,
4568 .port_set_policy = mv88e6352_port_set_policy,
4569 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4570 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4571 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4572 .port_set_ether_type = mv88e6351_port_set_ether_type,
4573 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4574 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4575 .port_pause_limit = mv88e6097_port_pause_limit,
4576 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4577 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4578 .port_get_cmode = mv88e6352_port_get_cmode,
4579 .port_setup_message_port = mv88e6xxx_setup_message_port,
4580 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4581 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4582 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4583 .stats_get_strings = mv88e6095_stats_get_strings,
4584 .stats_get_stats = mv88e6095_stats_get_stats,
4585 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4586 .set_egress_port = mv88e6095_g1_set_egress_port,
4587 .watchdog_ops = &mv88e6097_watchdog_ops,
4588 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4589 .pot_clear = mv88e6xxx_g2_pot_clear,
4590 .reset = mv88e6352_g1_reset,
4591 .rmu_disable = mv88e6352_g1_rmu_disable,
4592 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4593 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4594 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4595 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4596 .serdes_get_lane = mv88e6352_serdes_get_lane,
4597 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4598 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4599 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4600 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4601 .serdes_power = mv88e6352_serdes_power,
4602 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4603 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4604 .serdes_irq_status = mv88e6352_serdes_irq_status,
4605 .gpio_ops = &mv88e6352_gpio_ops,
4606 .avb_ops = &mv88e6352_avb_ops,
4607 .ptp_ops = &mv88e6352_ptp_ops,
4608 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
4609 .serdes_get_strings = mv88e6352_serdes_get_strings,
4610 .serdes_get_stats = mv88e6352_serdes_get_stats,
4611 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4612 .serdes_get_regs = mv88e6352_serdes_get_regs,
4613 .phylink_validate = mv88e6352_phylink_validate,
4614};
4615
4616static const struct mv88e6xxx_ops mv88e6390_ops = {
4617 /* MV88E6XXX_FAMILY_6390 */
4618 .setup_errata = mv88e6390_setup_errata,
4619 .irl_init_all = mv88e6390_g2_irl_init_all,
4620 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4621 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4622 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4623 .phy_read = mv88e6xxx_g2_smi_phy_read,
4624 .phy_write = mv88e6xxx_g2_smi_phy_write,
4625 .port_set_link = mv88e6xxx_port_set_link,
4626 .port_sync_link = mv88e6xxx_port_sync_link,
4627 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4628 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4629 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4630 .port_tag_remap = mv88e6390_port_tag_remap,
4631 .port_set_policy = mv88e6352_port_set_policy,
4632 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4633 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4634 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4635 .port_set_ether_type = mv88e6351_port_set_ether_type,
4636 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4637 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4638 .port_pause_limit = mv88e6390_port_pause_limit,
4639 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4640 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4641 .port_get_cmode = mv88e6352_port_get_cmode,
4642 .port_set_cmode = mv88e6390_port_set_cmode,
4643 .port_setup_message_port = mv88e6xxx_setup_message_port,
4644 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4645 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4646 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4647 .stats_get_strings = mv88e6320_stats_get_strings,
4648 .stats_get_stats = mv88e6390_stats_get_stats,
4649 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4650 .set_egress_port = mv88e6390_g1_set_egress_port,
4651 .watchdog_ops = &mv88e6390_watchdog_ops,
4652 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4653 .pot_clear = mv88e6xxx_g2_pot_clear,
4654 .reset = mv88e6352_g1_reset,
4655 .rmu_disable = mv88e6390_g1_rmu_disable,
4656 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4657 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4658 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4659 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4660 .serdes_power = mv88e6390_serdes_power,
4661 .serdes_get_lane = mv88e6390_serdes_get_lane,
4662 /* Check status register pause & lpa register */
4663 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4664 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4665 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4666 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4667 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4668 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4669 .serdes_irq_status = mv88e6390_serdes_irq_status,
4670 .gpio_ops = &mv88e6352_gpio_ops,
4671 .avb_ops = &mv88e6390_avb_ops,
4672 .ptp_ops = &mv88e6352_ptp_ops,
4673 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4674 .serdes_get_strings = mv88e6390_serdes_get_strings,
4675 .serdes_get_stats = mv88e6390_serdes_get_stats,
4676 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4677 .serdes_get_regs = mv88e6390_serdes_get_regs,
4678 .phylink_validate = mv88e6390_phylink_validate,
4679};
4680
4681static const struct mv88e6xxx_ops mv88e6390x_ops = {
4682 /* MV88E6XXX_FAMILY_6390 */
4683 .setup_errata = mv88e6390_setup_errata,
4684 .irl_init_all = mv88e6390_g2_irl_init_all,
4685 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4686 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4687 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4688 .phy_read = mv88e6xxx_g2_smi_phy_read,
4689 .phy_write = mv88e6xxx_g2_smi_phy_write,
4690 .port_set_link = mv88e6xxx_port_set_link,
4691 .port_sync_link = mv88e6xxx_port_sync_link,
4692 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4693 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4694 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4695 .port_tag_remap = mv88e6390_port_tag_remap,
4696 .port_set_policy = mv88e6352_port_set_policy,
4697 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4698 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4699 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4700 .port_set_ether_type = mv88e6351_port_set_ether_type,
4701 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4702 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4703 .port_pause_limit = mv88e6390_port_pause_limit,
4704 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4705 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4706 .port_get_cmode = mv88e6352_port_get_cmode,
4707 .port_set_cmode = mv88e6390x_port_set_cmode,
4708 .port_setup_message_port = mv88e6xxx_setup_message_port,
4709 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4710 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4711 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4712 .stats_get_strings = mv88e6320_stats_get_strings,
4713 .stats_get_stats = mv88e6390_stats_get_stats,
4714 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4715 .set_egress_port = mv88e6390_g1_set_egress_port,
4716 .watchdog_ops = &mv88e6390_watchdog_ops,
4717 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4718 .pot_clear = mv88e6xxx_g2_pot_clear,
4719 .reset = mv88e6352_g1_reset,
4720 .rmu_disable = mv88e6390_g1_rmu_disable,
4721 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4722 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4723 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4724 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4725 .serdes_power = mv88e6390_serdes_power,
4726 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4727 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4728 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4729 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4730 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4731 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4732 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4733 .serdes_irq_status = mv88e6390_serdes_irq_status,
4734 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4735 .serdes_get_strings = mv88e6390_serdes_get_strings,
4736 .serdes_get_stats = mv88e6390_serdes_get_stats,
4737 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4738 .serdes_get_regs = mv88e6390_serdes_get_regs,
4739 .gpio_ops = &mv88e6352_gpio_ops,
4740 .avb_ops = &mv88e6390_avb_ops,
4741 .ptp_ops = &mv88e6352_ptp_ops,
4742 .phylink_validate = mv88e6390x_phylink_validate,
4743};
4744
4745static const struct mv88e6xxx_ops mv88e6393x_ops = {
4746 /* MV88E6XXX_FAMILY_6393 */
4747 .setup_errata = mv88e6393x_serdes_setup_errata,
4748 .irl_init_all = mv88e6390_g2_irl_init_all,
4749 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4750 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4751 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4752 .phy_read = mv88e6xxx_g2_smi_phy_read,
4753 .phy_write = mv88e6xxx_g2_smi_phy_write,
4754 .port_set_link = mv88e6xxx_port_set_link,
4755 .port_sync_link = mv88e6xxx_port_sync_link,
4756 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4757 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
4758 .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
4759 .port_tag_remap = mv88e6390_port_tag_remap,
4760 .port_set_policy = mv88e6393x_port_set_policy,
4761 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4762 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4763 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4764 .port_set_ether_type = mv88e6393x_port_set_ether_type,
4765 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4766 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4767 .port_pause_limit = mv88e6390_port_pause_limit,
4768 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4769 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4770 .port_get_cmode = mv88e6352_port_get_cmode,
4771 .port_set_cmode = mv88e6393x_port_set_cmode,
4772 .port_setup_message_port = mv88e6xxx_setup_message_port,
4773 .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
4774 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4775 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4776 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4777 .stats_get_strings = mv88e6320_stats_get_strings,
4778 .stats_get_stats = mv88e6390_stats_get_stats,
4779 /* .set_cpu_port is missing because this family does not support a global
4780 * CPU port, only per port CPU port which is set via
4781 * .port_set_upstream_port method.
4782 */
4783 .set_egress_port = mv88e6393x_set_egress_port,
4784 .watchdog_ops = &mv88e6390_watchdog_ops,
4785 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
4786 .pot_clear = mv88e6xxx_g2_pot_clear,
4787 .reset = mv88e6352_g1_reset,
4788 .rmu_disable = mv88e6390_g1_rmu_disable,
4789 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4790 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4791 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4792 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4793 .serdes_power = mv88e6393x_serdes_power,
4794 .serdes_get_lane = mv88e6393x_serdes_get_lane,
4795 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state,
4796 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4797 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4798 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4799 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4800 .serdes_irq_enable = mv88e6393x_serdes_irq_enable,
4801 .serdes_irq_status = mv88e6393x_serdes_irq_status,
4802 /* TODO: serdes stats */
4803 .gpio_ops = &mv88e6352_gpio_ops,
4804 .avb_ops = &mv88e6390_avb_ops,
4805 .ptp_ops = &mv88e6352_ptp_ops,
4806 .phylink_validate = mv88e6393x_phylink_validate,
4807};
4808
4809static const struct mv88e6xxx_info mv88e6xxx_table[] = {
4810 [MV88E6085] = {
4811 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
4812 .family = MV88E6XXX_FAMILY_6097,
4813 .name = "Marvell 88E6085",
4814 .num_databases = 4096,
4815 .num_macs = 8192,
4816 .num_ports = 10,
4817 .num_internal_phys = 5,
4818 .max_vid = 4095,
4819 .port_base_addr = 0x10,
4820 .phy_base_addr = 0x0,
4821 .global1_addr = 0x1b,
4822 .global2_addr = 0x1c,
4823 .age_time_coeff = 15000,
4824 .g1_irqs = 8,
4825 .g2_irqs = 10,
4826 .atu_move_port_mask = 0xf,
4827 .pvt = true,
4828 .multi_chip = true,
4829 .ops = &mv88e6085_ops,
4830 },
4831
4832 [MV88E6095] = {
4833 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
4834 .family = MV88E6XXX_FAMILY_6095,
4835 .name = "Marvell 88E6095/88E6095F",
4836 .num_databases = 256,
4837 .num_macs = 8192,
4838 .num_ports = 11,
4839 .num_internal_phys = 0,
4840 .max_vid = 4095,
4841 .port_base_addr = 0x10,
4842 .phy_base_addr = 0x0,
4843 .global1_addr = 0x1b,
4844 .global2_addr = 0x1c,
4845 .age_time_coeff = 15000,
4846 .g1_irqs = 8,
4847 .atu_move_port_mask = 0xf,
4848 .multi_chip = true,
4849 .ops = &mv88e6095_ops,
4850 },
4851
4852 [MV88E6097] = {
4853 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
4854 .family = MV88E6XXX_FAMILY_6097,
4855 .name = "Marvell 88E6097/88E6097F",
4856 .num_databases = 4096,
4857 .num_macs = 8192,
4858 .num_ports = 11,
4859 .num_internal_phys = 8,
4860 .max_vid = 4095,
4861 .port_base_addr = 0x10,
4862 .phy_base_addr = 0x0,
4863 .global1_addr = 0x1b,
4864 .global2_addr = 0x1c,
4865 .age_time_coeff = 15000,
4866 .g1_irqs = 8,
4867 .g2_irqs = 10,
4868 .atu_move_port_mask = 0xf,
4869 .pvt = true,
4870 .multi_chip = true,
4871 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
4872 .ops = &mv88e6097_ops,
4873 },
4874
4875 [MV88E6123] = {
4876 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
4877 .family = MV88E6XXX_FAMILY_6165,
4878 .name = "Marvell 88E6123",
4879 .num_databases = 4096,
4880 .num_macs = 1024,
4881 .num_ports = 3,
4882 .num_internal_phys = 5,
4883 .max_vid = 4095,
4884 .port_base_addr = 0x10,
4885 .phy_base_addr = 0x0,
4886 .global1_addr = 0x1b,
4887 .global2_addr = 0x1c,
4888 .age_time_coeff = 15000,
4889 .g1_irqs = 9,
4890 .g2_irqs = 10,
4891 .atu_move_port_mask = 0xf,
4892 .pvt = true,
4893 .multi_chip = true,
4894 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
4895 .ops = &mv88e6123_ops,
4896 },
4897
4898 [MV88E6131] = {
4899 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
4900 .family = MV88E6XXX_FAMILY_6185,
4901 .name = "Marvell 88E6131",
4902 .num_databases = 256,
4903 .num_macs = 8192,
4904 .num_ports = 8,
4905 .num_internal_phys = 0,
4906 .max_vid = 4095,
4907 .port_base_addr = 0x10,
4908 .phy_base_addr = 0x0,
4909 .global1_addr = 0x1b,
4910 .global2_addr = 0x1c,
4911 .age_time_coeff = 15000,
4912 .g1_irqs = 9,
4913 .atu_move_port_mask = 0xf,
4914 .multi_chip = true,
4915 .ops = &mv88e6131_ops,
4916 },
4917
4918 [MV88E6141] = {
4919 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
4920 .family = MV88E6XXX_FAMILY_6341,
4921 .name = "Marvell 88E6141",
4922 .num_databases = 4096,
4923 .num_macs = 2048,
4924 .num_ports = 6,
4925 .num_internal_phys = 5,
4926 .num_gpio = 11,
4927 .max_vid = 4095,
4928 .port_base_addr = 0x10,
4929 .phy_base_addr = 0x10,
4930 .global1_addr = 0x1b,
4931 .global2_addr = 0x1c,
4932 .age_time_coeff = 3750,
4933 .atu_move_port_mask = 0x1f,
4934 .g1_irqs = 9,
4935 .g2_irqs = 10,
4936 .pvt = true,
4937 .multi_chip = true,
4938 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
4939 .ops = &mv88e6141_ops,
4940 },
4941
4942 [MV88E6161] = {
4943 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
4944 .family = MV88E6XXX_FAMILY_6165,
4945 .name = "Marvell 88E6161",
4946 .num_databases = 4096,
4947 .num_macs = 1024,
4948 .num_ports = 6,
4949 .num_internal_phys = 5,
4950 .max_vid = 4095,
4951 .port_base_addr = 0x10,
4952 .phy_base_addr = 0x0,
4953 .global1_addr = 0x1b,
4954 .global2_addr = 0x1c,
4955 .age_time_coeff = 15000,
4956 .g1_irqs = 9,
4957 .g2_irqs = 10,
4958 .atu_move_port_mask = 0xf,
4959 .pvt = true,
4960 .multi_chip = true,
4961 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
4962 .ptp_support = true,
4963 .ops = &mv88e6161_ops,
4964 },
4965
4966 [MV88E6165] = {
4967 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
4968 .family = MV88E6XXX_FAMILY_6165,
4969 .name = "Marvell 88E6165",
4970 .num_databases = 4096,
4971 .num_macs = 8192,
4972 .num_ports = 6,
4973 .num_internal_phys = 0,
4974 .max_vid = 4095,
4975 .port_base_addr = 0x10,
4976 .phy_base_addr = 0x0,
4977 .global1_addr = 0x1b,
4978 .global2_addr = 0x1c,
4979 .age_time_coeff = 15000,
4980 .g1_irqs = 9,
4981 .g2_irqs = 10,
4982 .atu_move_port_mask = 0xf,
4983 .pvt = true,
4984 .multi_chip = true,
4985 .ptp_support = true,
4986 .ops = &mv88e6165_ops,
4987 },
4988
4989 [MV88E6171] = {
4990 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
4991 .family = MV88E6XXX_FAMILY_6351,
4992 .name = "Marvell 88E6171",
4993 .num_databases = 4096,
4994 .num_macs = 8192,
4995 .num_ports = 7,
4996 .num_internal_phys = 5,
4997 .max_vid = 4095,
4998 .port_base_addr = 0x10,
4999 .phy_base_addr = 0x0,
5000 .global1_addr = 0x1b,
5001 .global2_addr = 0x1c,
5002 .age_time_coeff = 15000,
5003 .g1_irqs = 9,
5004 .g2_irqs = 10,
5005 .atu_move_port_mask = 0xf,
5006 .pvt = true,
5007 .multi_chip = true,
5008 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5009 .ops = &mv88e6171_ops,
5010 },
5011
5012 [MV88E6172] = {
5013 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
5014 .family = MV88E6XXX_FAMILY_6352,
5015 .name = "Marvell 88E6172",
5016 .num_databases = 4096,
5017 .num_macs = 8192,
5018 .num_ports = 7,
5019 .num_internal_phys = 5,
5020 .num_gpio = 15,
5021 .max_vid = 4095,
5022 .port_base_addr = 0x10,
5023 .phy_base_addr = 0x0,
5024 .global1_addr = 0x1b,
5025 .global2_addr = 0x1c,
5026 .age_time_coeff = 15000,
5027 .g1_irqs = 9,
5028 .g2_irqs = 10,
5029 .atu_move_port_mask = 0xf,
5030 .pvt = true,
5031 .multi_chip = true,
5032 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5033 .ops = &mv88e6172_ops,
5034 },
5035
5036 [MV88E6175] = {
5037 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
5038 .family = MV88E6XXX_FAMILY_6351,
5039 .name = "Marvell 88E6175",
5040 .num_databases = 4096,
5041 .num_macs = 8192,
5042 .num_ports = 7,
5043 .num_internal_phys = 5,
5044 .max_vid = 4095,
5045 .port_base_addr = 0x10,
5046 .phy_base_addr = 0x0,
5047 .global1_addr = 0x1b,
5048 .global2_addr = 0x1c,
5049 .age_time_coeff = 15000,
5050 .g1_irqs = 9,
5051 .g2_irqs = 10,
5052 .atu_move_port_mask = 0xf,
5053 .pvt = true,
5054 .multi_chip = true,
5055 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5056 .ops = &mv88e6175_ops,
5057 },
5058
5059 [MV88E6176] = {
5060 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5061 .family = MV88E6XXX_FAMILY_6352,
5062 .name = "Marvell 88E6176",
5063 .num_databases = 4096,
5064 .num_macs = 8192,
5065 .num_ports = 7,
5066 .num_internal_phys = 5,
5067 .num_gpio = 15,
5068 .max_vid = 4095,
5069 .port_base_addr = 0x10,
5070 .phy_base_addr = 0x0,
5071 .global1_addr = 0x1b,
5072 .global2_addr = 0x1c,
5073 .age_time_coeff = 15000,
5074 .g1_irqs = 9,
5075 .g2_irqs = 10,
5076 .atu_move_port_mask = 0xf,
5077 .pvt = true,
5078 .multi_chip = true,
5079 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5080 .ops = &mv88e6176_ops,
5081 },
5082
5083 [MV88E6185] = {
5084 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
5085 .family = MV88E6XXX_FAMILY_6185,
5086 .name = "Marvell 88E6185",
5087 .num_databases = 256,
5088 .num_macs = 8192,
5089 .num_ports = 10,
5090 .num_internal_phys = 0,
5091 .max_vid = 4095,
5092 .port_base_addr = 0x10,
5093 .phy_base_addr = 0x0,
5094 .global1_addr = 0x1b,
5095 .global2_addr = 0x1c,
5096 .age_time_coeff = 15000,
5097 .g1_irqs = 8,
5098 .atu_move_port_mask = 0xf,
5099 .multi_chip = true,
5100 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5101 .ops = &mv88e6185_ops,
5102 },
5103
5104 [MV88E6190] = {
5105 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
5106 .family = MV88E6XXX_FAMILY_6390,
5107 .name = "Marvell 88E6190",
5108 .num_databases = 4096,
5109 .num_macs = 16384,
5110 .num_ports = 11, /* 10 + Z80 */
5111 .num_internal_phys = 9,
5112 .num_gpio = 16,
5113 .max_vid = 8191,
5114 .port_base_addr = 0x0,
5115 .phy_base_addr = 0x0,
5116 .global1_addr = 0x1b,
5117 .global2_addr = 0x1c,
5118 .age_time_coeff = 3750,
5119 .g1_irqs = 9,
5120 .g2_irqs = 14,
5121 .pvt = true,
5122 .multi_chip = true,
5123 .atu_move_port_mask = 0x1f,
5124 .ops = &mv88e6190_ops,
5125 },
5126
5127 [MV88E6190X] = {
5128 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
5129 .family = MV88E6XXX_FAMILY_6390,
5130 .name = "Marvell 88E6190X",
5131 .num_databases = 4096,
5132 .num_macs = 16384,
5133 .num_ports = 11, /* 10 + Z80 */
5134 .num_internal_phys = 9,
5135 .num_gpio = 16,
5136 .max_vid = 8191,
5137 .port_base_addr = 0x0,
5138 .phy_base_addr = 0x0,
5139 .global1_addr = 0x1b,
5140 .global2_addr = 0x1c,
5141 .age_time_coeff = 3750,
5142 .g1_irqs = 9,
5143 .g2_irqs = 14,
5144 .atu_move_port_mask = 0x1f,
5145 .pvt = true,
5146 .multi_chip = true,
5147 .ops = &mv88e6190x_ops,
5148 },
5149
5150 [MV88E6191] = {
5151 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
5152 .family = MV88E6XXX_FAMILY_6390,
5153 .name = "Marvell 88E6191",
5154 .num_databases = 4096,
5155 .num_macs = 16384,
5156 .num_ports = 11, /* 10 + Z80 */
5157 .num_internal_phys = 9,
5158 .max_vid = 8191,
5159 .port_base_addr = 0x0,
5160 .phy_base_addr = 0x0,
5161 .global1_addr = 0x1b,
5162 .global2_addr = 0x1c,
5163 .age_time_coeff = 3750,
5164 .g1_irqs = 9,
5165 .g2_irqs = 14,
5166 .atu_move_port_mask = 0x1f,
5167 .pvt = true,
5168 .multi_chip = true,
5169 .ptp_support = true,
5170 .ops = &mv88e6191_ops,
5171 },
5172
5173 [MV88E6191X] = {
5174 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
5175 .family = MV88E6XXX_FAMILY_6393,
5176 .name = "Marvell 88E6191X",
5177 .num_databases = 4096,
5178 .num_ports = 11, /* 10 + Z80 */
5179 .num_internal_phys = 9,
5180 .max_vid = 8191,
5181 .port_base_addr = 0x0,
5182 .phy_base_addr = 0x0,
5183 .global1_addr = 0x1b,
5184 .global2_addr = 0x1c,
5185 .age_time_coeff = 3750,
5186 .g1_irqs = 10,
5187 .g2_irqs = 14,
5188 .atu_move_port_mask = 0x1f,
5189 .pvt = true,
5190 .multi_chip = true,
5191 .ptp_support = true,
5192 .ops = &mv88e6393x_ops,
5193 },
5194
5195 [MV88E6193X] = {
5196 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
5197 .family = MV88E6XXX_FAMILY_6393,
5198 .name = "Marvell 88E6193X",
5199 .num_databases = 4096,
5200 .num_ports = 11, /* 10 + Z80 */
5201 .num_internal_phys = 9,
5202 .max_vid = 8191,
5203 .port_base_addr = 0x0,
5204 .phy_base_addr = 0x0,
5205 .global1_addr = 0x1b,
5206 .global2_addr = 0x1c,
5207 .age_time_coeff = 3750,
5208 .g1_irqs = 10,
5209 .g2_irqs = 14,
5210 .atu_move_port_mask = 0x1f,
5211 .pvt = true,
5212 .multi_chip = true,
5213 .ptp_support = true,
5214 .ops = &mv88e6393x_ops,
5215 },
5216
5217 [MV88E6220] = {
5218 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
5219 .family = MV88E6XXX_FAMILY_6250,
5220 .name = "Marvell 88E6220",
5221 .num_databases = 64,
5222
5223 /* Ports 2-4 are not routed to pins
5224 * => usable ports 0, 1, 5, 6
5225 */
5226 .num_ports = 7,
5227 .num_internal_phys = 2,
5228 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5229 .max_vid = 4095,
5230 .port_base_addr = 0x08,
5231 .phy_base_addr = 0x00,
5232 .global1_addr = 0x0f,
5233 .global2_addr = 0x07,
5234 .age_time_coeff = 15000,
5235 .g1_irqs = 9,
5236 .g2_irqs = 10,
5237 .atu_move_port_mask = 0xf,
5238 .dual_chip = true,
5239 .ptp_support = true,
5240 .ops = &mv88e6250_ops,
5241 },
5242
5243 [MV88E6240] = {
5244 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
5245 .family = MV88E6XXX_FAMILY_6352,
5246 .name = "Marvell 88E6240",
5247 .num_databases = 4096,
5248 .num_macs = 8192,
5249 .num_ports = 7,
5250 .num_internal_phys = 5,
5251 .num_gpio = 15,
5252 .max_vid = 4095,
5253 .port_base_addr = 0x10,
5254 .phy_base_addr = 0x0,
5255 .global1_addr = 0x1b,
5256 .global2_addr = 0x1c,
5257 .age_time_coeff = 15000,
5258 .g1_irqs = 9,
5259 .g2_irqs = 10,
5260 .atu_move_port_mask = 0xf,
5261 .pvt = true,
5262 .multi_chip = true,
5263 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5264 .ptp_support = true,
5265 .ops = &mv88e6240_ops,
5266 },
5267
5268 [MV88E6250] = {
5269 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
5270 .family = MV88E6XXX_FAMILY_6250,
5271 .name = "Marvell 88E6250",
5272 .num_databases = 64,
5273 .num_ports = 7,
5274 .num_internal_phys = 5,
5275 .max_vid = 4095,
5276 .port_base_addr = 0x08,
5277 .phy_base_addr = 0x00,
5278 .global1_addr = 0x0f,
5279 .global2_addr = 0x07,
5280 .age_time_coeff = 15000,
5281 .g1_irqs = 9,
5282 .g2_irqs = 10,
5283 .atu_move_port_mask = 0xf,
5284 .dual_chip = true,
5285 .ptp_support = true,
5286 .ops = &mv88e6250_ops,
5287 },
5288
5289 [MV88E6290] = {
5290 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
5291 .family = MV88E6XXX_FAMILY_6390,
5292 .name = "Marvell 88E6290",
5293 .num_databases = 4096,
5294 .num_ports = 11, /* 10 + Z80 */
5295 .num_internal_phys = 9,
5296 .num_gpio = 16,
5297 .max_vid = 8191,
5298 .port_base_addr = 0x0,
5299 .phy_base_addr = 0x0,
5300 .global1_addr = 0x1b,
5301 .global2_addr = 0x1c,
5302 .age_time_coeff = 3750,
5303 .g1_irqs = 9,
5304 .g2_irqs = 14,
5305 .atu_move_port_mask = 0x1f,
5306 .pvt = true,
5307 .multi_chip = true,
5308 .ptp_support = true,
5309 .ops = &mv88e6290_ops,
5310 },
5311
5312 [MV88E6320] = {
5313 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
5314 .family = MV88E6XXX_FAMILY_6320,
5315 .name = "Marvell 88E6320",
5316 .num_databases = 4096,
5317 .num_macs = 8192,
5318 .num_ports = 7,
5319 .num_internal_phys = 5,
5320 .num_gpio = 15,
5321 .max_vid = 4095,
5322 .port_base_addr = 0x10,
5323 .phy_base_addr = 0x0,
5324 .global1_addr = 0x1b,
5325 .global2_addr = 0x1c,
5326 .age_time_coeff = 15000,
5327 .g1_irqs = 8,
5328 .g2_irqs = 10,
5329 .atu_move_port_mask = 0xf,
5330 .pvt = true,
5331 .multi_chip = true,
5332 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5333 .ptp_support = true,
5334 .ops = &mv88e6320_ops,
5335 },
5336
5337 [MV88E6321] = {
5338 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
5339 .family = MV88E6XXX_FAMILY_6320,
5340 .name = "Marvell 88E6321",
5341 .num_databases = 4096,
5342 .num_macs = 8192,
5343 .num_ports = 7,
5344 .num_internal_phys = 5,
5345 .num_gpio = 15,
5346 .max_vid = 4095,
5347 .port_base_addr = 0x10,
5348 .phy_base_addr = 0x0,
5349 .global1_addr = 0x1b,
5350 .global2_addr = 0x1c,
5351 .age_time_coeff = 15000,
5352 .g1_irqs = 8,
5353 .g2_irqs = 10,
5354 .atu_move_port_mask = 0xf,
5355 .multi_chip = true,
5356 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5357 .ptp_support = true,
5358 .ops = &mv88e6321_ops,
5359 },
5360
5361 [MV88E6341] = {
5362 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
5363 .family = MV88E6XXX_FAMILY_6341,
5364 .name = "Marvell 88E6341",
5365 .num_databases = 4096,
5366 .num_macs = 2048,
5367 .num_internal_phys = 5,
5368 .num_ports = 6,
5369 .num_gpio = 11,
5370 .max_vid = 4095,
5371 .port_base_addr = 0x10,
5372 .phy_base_addr = 0x10,
5373 .global1_addr = 0x1b,
5374 .global2_addr = 0x1c,
5375 .age_time_coeff = 3750,
5376 .atu_move_port_mask = 0x1f,
5377 .g1_irqs = 9,
5378 .g2_irqs = 10,
5379 .pvt = true,
5380 .multi_chip = true,
5381 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5382 .ptp_support = true,
5383 .ops = &mv88e6341_ops,
5384 },
5385
5386 [MV88E6350] = {
5387 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
5388 .family = MV88E6XXX_FAMILY_6351,
5389 .name = "Marvell 88E6350",
5390 .num_databases = 4096,
5391 .num_macs = 8192,
5392 .num_ports = 7,
5393 .num_internal_phys = 5,
5394 .max_vid = 4095,
5395 .port_base_addr = 0x10,
5396 .phy_base_addr = 0x0,
5397 .global1_addr = 0x1b,
5398 .global2_addr = 0x1c,
5399 .age_time_coeff = 15000,
5400 .g1_irqs = 9,
5401 .g2_irqs = 10,
5402 .atu_move_port_mask = 0xf,
5403 .pvt = true,
5404 .multi_chip = true,
5405 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5406 .ops = &mv88e6350_ops,
5407 },
5408
5409 [MV88E6351] = {
5410 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
5411 .family = MV88E6XXX_FAMILY_6351,
5412 .name = "Marvell 88E6351",
5413 .num_databases = 4096,
5414 .num_macs = 8192,
5415 .num_ports = 7,
5416 .num_internal_phys = 5,
5417 .max_vid = 4095,
5418 .port_base_addr = 0x10,
5419 .phy_base_addr = 0x0,
5420 .global1_addr = 0x1b,
5421 .global2_addr = 0x1c,
5422 .age_time_coeff = 15000,
5423 .g1_irqs = 9,
5424 .g2_irqs = 10,
5425 .atu_move_port_mask = 0xf,
5426 .pvt = true,
5427 .multi_chip = true,
5428 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5429 .ops = &mv88e6351_ops,
5430 },
5431
5432 [MV88E6352] = {
5433 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
5434 .family = MV88E6XXX_FAMILY_6352,
5435 .name = "Marvell 88E6352",
5436 .num_databases = 4096,
5437 .num_macs = 8192,
5438 .num_ports = 7,
5439 .num_internal_phys = 5,
5440 .num_gpio = 15,
5441 .max_vid = 4095,
5442 .port_base_addr = 0x10,
5443 .phy_base_addr = 0x0,
5444 .global1_addr = 0x1b,
5445 .global2_addr = 0x1c,
5446 .age_time_coeff = 15000,
5447 .g1_irqs = 9,
5448 .g2_irqs = 10,
5449 .atu_move_port_mask = 0xf,
5450 .pvt = true,
5451 .multi_chip = true,
5452 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5453 .ptp_support = true,
5454 .ops = &mv88e6352_ops,
5455 },
5456 [MV88E6390] = {
5457 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
5458 .family = MV88E6XXX_FAMILY_6390,
5459 .name = "Marvell 88E6390",
5460 .num_databases = 4096,
5461 .num_macs = 16384,
5462 .num_ports = 11, /* 10 + Z80 */
5463 .num_internal_phys = 9,
5464 .num_gpio = 16,
5465 .max_vid = 8191,
5466 .port_base_addr = 0x0,
5467 .phy_base_addr = 0x0,
5468 .global1_addr = 0x1b,
5469 .global2_addr = 0x1c,
5470 .age_time_coeff = 3750,
5471 .g1_irqs = 9,
5472 .g2_irqs = 14,
5473 .atu_move_port_mask = 0x1f,
5474 .pvt = true,
5475 .multi_chip = true,
5476 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
5477 .ptp_support = true,
5478 .ops = &mv88e6390_ops,
5479 },
5480 [MV88E6390X] = {
5481 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
5482 .family = MV88E6XXX_FAMILY_6390,
5483 .name = "Marvell 88E6390X",
5484 .num_databases = 4096,
5485 .num_macs = 16384,
5486 .num_ports = 11, /* 10 + Z80 */
5487 .num_internal_phys = 9,
5488 .num_gpio = 16,
5489 .max_vid = 8191,
5490 .port_base_addr = 0x0,
5491 .phy_base_addr = 0x0,
5492 .global1_addr = 0x1b,
5493 .global2_addr = 0x1c,
5494 .age_time_coeff = 3750,
5495 .g1_irqs = 9,
5496 .g2_irqs = 14,
5497 .atu_move_port_mask = 0x1f,
5498 .pvt = true,
5499 .multi_chip = true,
5500 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
5501 .ptp_support = true,
5502 .ops = &mv88e6390x_ops,
5503 },
5504
5505 [MV88E6393X] = {
5506 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
5507 .family = MV88E6XXX_FAMILY_6393,
5508 .name = "Marvell 88E6393X",
5509 .num_databases = 4096,
5510 .num_ports = 11, /* 10 + Z80 */
5511 .num_internal_phys = 9,
5512 .max_vid = 8191,
5513 .port_base_addr = 0x0,
5514 .phy_base_addr = 0x0,
5515 .global1_addr = 0x1b,
5516 .global2_addr = 0x1c,
5517 .age_time_coeff = 3750,
5518 .g1_irqs = 10,
5519 .g2_irqs = 14,
5520 .atu_move_port_mask = 0x1f,
5521 .pvt = true,
5522 .multi_chip = true,
5523 .ptp_support = true,
5524 .ops = &mv88e6393x_ops,
5525 },
5526};
5527
5528static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
5529{
5530 int i;
5531
5532 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
5533 if (mv88e6xxx_table[i].prod_num == prod_num)
5534 return &mv88e6xxx_table[i];
5535
5536 return NULL;
5537}
5538
5539static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
5540{
5541 const struct mv88e6xxx_info *info;
5542 unsigned int prod_num, rev;
5543 u16 id;
5544 int err;
5545
5546 mv88e6xxx_reg_lock(chip);
5547 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
5548 mv88e6xxx_reg_unlock(chip);
5549 if (err)
5550 return err;
5551
5552 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
5553 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
5554
5555 info = mv88e6xxx_lookup_info(prod_num);
5556 if (!info)
5557 return -ENODEV;
5558
5559 /* Update the compatible info with the probed one */
5560 chip->info = info;
5561
5562 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
5563 chip->info->prod_num, chip->info->name, rev);
5564
5565 return 0;
5566}
5567
5568static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
5569{
5570 struct mv88e6xxx_chip *chip;
5571
5572 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
5573 if (!chip)
5574 return NULL;
5575
5576 chip->dev = dev;
5577
5578 mutex_init(&chip->reg_lock);
5579 INIT_LIST_HEAD(&chip->mdios);
5580 idr_init(&chip->policies);
5581
5582 return chip;
5583}
5584
5585static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
5586 int port,
5587 enum dsa_tag_protocol m)
5588{
5589 struct mv88e6xxx_chip *chip = ds->priv;
5590
5591 return chip->tag_protocol;
5592}
5593
5594static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port,
5595 enum dsa_tag_protocol proto)
5596{
5597 struct mv88e6xxx_chip *chip = ds->priv;
5598 enum dsa_tag_protocol old_protocol;
5599 int err;
5600
5601 switch (proto) {
5602 case DSA_TAG_PROTO_EDSA:
5603 switch (chip->info->edsa_support) {
5604 case MV88E6XXX_EDSA_UNSUPPORTED:
5605 return -EPROTONOSUPPORT;
5606 case MV88E6XXX_EDSA_UNDOCUMENTED:
5607 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
5608 fallthrough;
5609 case MV88E6XXX_EDSA_SUPPORTED:
5610 break;
5611 }
5612 break;
5613 case DSA_TAG_PROTO_DSA:
5614 break;
5615 default:
5616 return -EPROTONOSUPPORT;
5617 }
5618
5619 old_protocol = chip->tag_protocol;
5620 chip->tag_protocol = proto;
5621
5622 mv88e6xxx_reg_lock(chip);
5623 err = mv88e6xxx_setup_port_mode(chip, port);
5624 mv88e6xxx_reg_unlock(chip);
5625
5626 if (err)
5627 chip->tag_protocol = old_protocol;
5628
5629 return err;
5630}
5631
5632static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
5633 const struct switchdev_obj_port_mdb *mdb)
5634{
5635 struct mv88e6xxx_chip *chip = ds->priv;
5636 int err;
5637
5638 mv88e6xxx_reg_lock(chip);
5639 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
5640 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
5641 mv88e6xxx_reg_unlock(chip);
5642
5643 return err;
5644}
5645
5646static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
5647 const struct switchdev_obj_port_mdb *mdb)
5648{
5649 struct mv88e6xxx_chip *chip = ds->priv;
5650 int err;
5651
5652 mv88e6xxx_reg_lock(chip);
5653 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
5654 mv88e6xxx_reg_unlock(chip);
5655
5656 return err;
5657}
5658
5659static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
5660 struct dsa_mall_mirror_tc_entry *mirror,
5661 bool ingress)
5662{
5663 enum mv88e6xxx_egress_direction direction = ingress ?
5664 MV88E6XXX_EGRESS_DIR_INGRESS :
5665 MV88E6XXX_EGRESS_DIR_EGRESS;
5666 struct mv88e6xxx_chip *chip = ds->priv;
5667 bool other_mirrors = false;
5668 int i;
5669 int err;
5670
5671 mutex_lock(&chip->reg_lock);
5672 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
5673 mirror->to_local_port) {
5674 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5675 other_mirrors |= ingress ?
5676 chip->ports[i].mirror_ingress :
5677 chip->ports[i].mirror_egress;
5678
5679 /* Can't change egress port when other mirror is active */
5680 if (other_mirrors) {
5681 err = -EBUSY;
5682 goto out;
5683 }
5684
5685 err = mv88e6xxx_set_egress_port(chip, direction,
5686 mirror->to_local_port);
5687 if (err)
5688 goto out;
5689 }
5690
5691 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
5692out:
5693 mutex_unlock(&chip->reg_lock);
5694
5695 return err;
5696}
5697
5698static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
5699 struct dsa_mall_mirror_tc_entry *mirror)
5700{
5701 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
5702 MV88E6XXX_EGRESS_DIR_INGRESS :
5703 MV88E6XXX_EGRESS_DIR_EGRESS;
5704 struct mv88e6xxx_chip *chip = ds->priv;
5705 bool other_mirrors = false;
5706 int i;
5707
5708 mutex_lock(&chip->reg_lock);
5709 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
5710 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
5711
5712 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5713 other_mirrors |= mirror->ingress ?
5714 chip->ports[i].mirror_ingress :
5715 chip->ports[i].mirror_egress;
5716
5717 /* Reset egress port when no other mirror is active */
5718 if (!other_mirrors) {
5719 if (mv88e6xxx_set_egress_port(chip, direction,
5720 dsa_upstream_port(ds, port)))
5721 dev_err(ds->dev, "failed to set egress port\n");
5722 }
5723
5724 mutex_unlock(&chip->reg_lock);
5725}
5726
5727static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
5728 struct switchdev_brport_flags flags,
5729 struct netlink_ext_ack *extack)
5730{
5731 struct mv88e6xxx_chip *chip = ds->priv;
5732 const struct mv88e6xxx_ops *ops;
5733
5734 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
5735 BR_BCAST_FLOOD))
5736 return -EINVAL;
5737
5738 ops = chip->info->ops;
5739
5740 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
5741 return -EINVAL;
5742
5743 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
5744 return -EINVAL;
5745
5746 return 0;
5747}
5748
5749static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
5750 struct switchdev_brport_flags flags,
5751 struct netlink_ext_ack *extack)
5752{
5753 struct mv88e6xxx_chip *chip = ds->priv;
5754 bool do_fast_age = false;
5755 int err = -EOPNOTSUPP;
5756
5757 mv88e6xxx_reg_lock(chip);
5758
5759 if (flags.mask & BR_LEARNING) {
5760 bool learning = !!(flags.val & BR_LEARNING);
5761 u16 pav = learning ? (1 << port) : 0;
5762
5763 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
5764 if (err)
5765 goto out;
5766
5767 if (!learning)
5768 do_fast_age = true;
5769 }
5770
5771 if (flags.mask & BR_FLOOD) {
5772 bool unicast = !!(flags.val & BR_FLOOD);
5773
5774 err = chip->info->ops->port_set_ucast_flood(chip, port,
5775 unicast);
5776 if (err)
5777 goto out;
5778 }
5779
5780 if (flags.mask & BR_MCAST_FLOOD) {
5781 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
5782
5783 err = chip->info->ops->port_set_mcast_flood(chip, port,
5784 multicast);
5785 if (err)
5786 goto out;
5787 }
5788
5789 if (flags.mask & BR_BCAST_FLOOD) {
5790 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
5791
5792 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
5793 if (err)
5794 goto out;
5795 }
5796
5797out:
5798 mv88e6xxx_reg_unlock(chip);
5799
5800 if (do_fast_age)
5801 mv88e6xxx_port_fast_age(ds, port);
5802
5803 return err;
5804}
5805
5806static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
5807 struct net_device *lag,
5808 struct netdev_lag_upper_info *info)
5809{
5810 struct mv88e6xxx_chip *chip = ds->priv;
5811 struct dsa_port *dp;
5812 int id, members = 0;
5813
5814 if (!mv88e6xxx_has_lag(chip))
5815 return false;
5816
5817 id = dsa_lag_id(ds->dst, lag);
5818 if (id < 0 || id >= ds->num_lag_ids)
5819 return false;
5820
5821 dsa_lag_foreach_port(dp, ds->dst, lag)
5822 /* Includes the port joining the LAG */
5823 members++;
5824
5825 if (members > 8)
5826 return false;
5827
5828 /* We could potentially relax this to include active
5829 * backup in the future.
5830 */
5831 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
5832 return false;
5833
5834 /* Ideally we would also validate that the hash type matches
5835 * the hardware. Alas, this is always set to unknown on team
5836 * interfaces.
5837 */
5838 return true;
5839}
5840
5841static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag)
5842{
5843 struct mv88e6xxx_chip *chip = ds->priv;
5844 struct dsa_port *dp;
5845 u16 map = 0;
5846 int id;
5847
5848 id = dsa_lag_id(ds->dst, lag);
5849
5850 /* Build the map of all ports to distribute flows destined for
5851 * this LAG. This can be either a local user port, or a DSA
5852 * port if the LAG port is on a remote chip.
5853 */
5854 dsa_lag_foreach_port(dp, ds->dst, lag)
5855 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
5856
5857 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
5858}
5859
5860static const u8 mv88e6xxx_lag_mask_table[8][8] = {
5861 /* Row number corresponds to the number of active members in a
5862 * LAG. Each column states which of the eight hash buckets are
5863 * mapped to the column:th port in the LAG.
5864 *
5865 * Example: In a LAG with three active ports, the second port
5866 * ([2][1]) would be selected for traffic mapped to buckets
5867 * 3,4,5 (0x38).
5868 */
5869 { 0xff, 0, 0, 0, 0, 0, 0, 0 },
5870 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 },
5871 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 },
5872 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 },
5873 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 },
5874 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 },
5875 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 },
5876 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
5877};
5878
5879static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
5880 int num_tx, int nth)
5881{
5882 u8 active = 0;
5883 int i;
5884
5885 num_tx = num_tx <= 8 ? num_tx : 8;
5886 if (nth < num_tx)
5887 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
5888
5889 for (i = 0; i < 8; i++) {
5890 if (BIT(i) & active)
5891 mask[i] |= BIT(port);
5892 }
5893}
5894
5895static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
5896{
5897 struct mv88e6xxx_chip *chip = ds->priv;
5898 unsigned int id, num_tx;
5899 struct net_device *lag;
5900 struct dsa_port *dp;
5901 int i, err, nth;
5902 u16 mask[8];
5903 u16 ivec;
5904
5905 /* Assume no port is a member of any LAG. */
5906 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
5907
5908 /* Disable all masks for ports that _are_ members of a LAG. */
5909 list_for_each_entry(dp, &ds->dst->ports, list) {
5910 if (!dp->lag_dev || dp->ds != ds)
5911 continue;
5912
5913 ivec &= ~BIT(dp->index);
5914 }
5915
5916 for (i = 0; i < 8; i++)
5917 mask[i] = ivec;
5918
5919 /* Enable the correct subset of masks for all LAG ports that
5920 * are in the Tx set.
5921 */
5922 dsa_lags_foreach_id(id, ds->dst) {
5923 lag = dsa_lag_dev(ds->dst, id);
5924 if (!lag)
5925 continue;
5926
5927 num_tx = 0;
5928 dsa_lag_foreach_port(dp, ds->dst, lag) {
5929 if (dp->lag_tx_enabled)
5930 num_tx++;
5931 }
5932
5933 if (!num_tx)
5934 continue;
5935
5936 nth = 0;
5937 dsa_lag_foreach_port(dp, ds->dst, lag) {
5938 if (!dp->lag_tx_enabled)
5939 continue;
5940
5941 if (dp->ds == ds)
5942 mv88e6xxx_lag_set_port_mask(mask, dp->index,
5943 num_tx, nth);
5944
5945 nth++;
5946 }
5947 }
5948
5949 for (i = 0; i < 8; i++) {
5950 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
5951 if (err)
5952 return err;
5953 }
5954
5955 return 0;
5956}
5957
5958static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
5959 struct net_device *lag)
5960{
5961 int err;
5962
5963 err = mv88e6xxx_lag_sync_masks(ds);
5964
5965 if (!err)
5966 err = mv88e6xxx_lag_sync_map(ds, lag);
5967
5968 return err;
5969}
5970
5971static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
5972{
5973 struct mv88e6xxx_chip *chip = ds->priv;
5974 int err;
5975
5976 mv88e6xxx_reg_lock(chip);
5977 err = mv88e6xxx_lag_sync_masks(ds);
5978 mv88e6xxx_reg_unlock(chip);
5979 return err;
5980}
5981
5982static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
5983 struct net_device *lag,
5984 struct netdev_lag_upper_info *info)
5985{
5986 struct mv88e6xxx_chip *chip = ds->priv;
5987 int err, id;
5988
5989 if (!mv88e6xxx_lag_can_offload(ds, lag, info))
5990 return -EOPNOTSUPP;
5991
5992 id = dsa_lag_id(ds->dst, lag);
5993
5994 mv88e6xxx_reg_lock(chip);
5995
5996 err = mv88e6xxx_port_set_trunk(chip, port, true, id);
5997 if (err)
5998 goto err_unlock;
5999
6000 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6001 if (err)
6002 goto err_clear_trunk;
6003
6004 mv88e6xxx_reg_unlock(chip);
6005 return 0;
6006
6007err_clear_trunk:
6008 mv88e6xxx_port_set_trunk(chip, port, false, 0);
6009err_unlock:
6010 mv88e6xxx_reg_unlock(chip);
6011 return err;
6012}
6013
6014static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6015 struct net_device *lag)
6016{
6017 struct mv88e6xxx_chip *chip = ds->priv;
6018 int err_sync, err_trunk;
6019
6020 mv88e6xxx_reg_lock(chip);
6021 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6022 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
6023 mv88e6xxx_reg_unlock(chip);
6024 return err_sync ? : err_trunk;
6025}
6026
6027static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
6028 int port)
6029{
6030 struct mv88e6xxx_chip *chip = ds->priv;
6031 int err;
6032
6033 mv88e6xxx_reg_lock(chip);
6034 err = mv88e6xxx_lag_sync_masks(ds);
6035 mv88e6xxx_reg_unlock(chip);
6036 return err;
6037}
6038
6039static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6040 int port, struct net_device *lag,
6041 struct netdev_lag_upper_info *info)
6042{
6043 struct mv88e6xxx_chip *chip = ds->priv;
6044 int err;
6045
6046 if (!mv88e6xxx_lag_can_offload(ds, lag, info))
6047 return -EOPNOTSUPP;
6048
6049 mv88e6xxx_reg_lock(chip);
6050
6051 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6052 if (err)
6053 goto unlock;
6054
6055 err = mv88e6xxx_pvt_map(chip, sw_index, port);
6056
6057unlock:
6058 mv88e6xxx_reg_unlock(chip);
6059 return err;
6060}
6061
6062static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6063 int port, struct net_device *lag)
6064{
6065 struct mv88e6xxx_chip *chip = ds->priv;
6066 int err_sync, err_pvt;
6067
6068 mv88e6xxx_reg_lock(chip);
6069 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6070 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
6071 mv88e6xxx_reg_unlock(chip);
6072 return err_sync ? : err_pvt;
6073}
6074
6075static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
6076 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
6077 .change_tag_protocol = mv88e6xxx_change_tag_protocol,
6078 .setup = mv88e6xxx_setup,
6079 .teardown = mv88e6xxx_teardown,
6080 .port_setup = mv88e6xxx_port_setup,
6081 .port_teardown = mv88e6xxx_port_teardown,
6082 .phylink_validate = mv88e6xxx_validate,
6083 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
6084 .phylink_mac_config = mv88e6xxx_mac_config,
6085 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
6086 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
6087 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
6088 .get_strings = mv88e6xxx_get_strings,
6089 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
6090 .get_sset_count = mv88e6xxx_get_sset_count,
6091 .port_enable = mv88e6xxx_port_enable,
6092 .port_disable = mv88e6xxx_port_disable,
6093 .port_max_mtu = mv88e6xxx_get_max_mtu,
6094 .port_change_mtu = mv88e6xxx_change_mtu,
6095 .get_mac_eee = mv88e6xxx_get_mac_eee,
6096 .set_mac_eee = mv88e6xxx_set_mac_eee,
6097 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
6098 .get_eeprom = mv88e6xxx_get_eeprom,
6099 .set_eeprom = mv88e6xxx_set_eeprom,
6100 .get_regs_len = mv88e6xxx_get_regs_len,
6101 .get_regs = mv88e6xxx_get_regs,
6102 .get_rxnfc = mv88e6xxx_get_rxnfc,
6103 .set_rxnfc = mv88e6xxx_set_rxnfc,
6104 .set_ageing_time = mv88e6xxx_set_ageing_time,
6105 .port_bridge_join = mv88e6xxx_port_bridge_join,
6106 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
6107 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags,
6108 .port_bridge_flags = mv88e6xxx_port_bridge_flags,
6109 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
6110 .port_fast_age = mv88e6xxx_port_fast_age,
6111 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
6112 .port_vlan_add = mv88e6xxx_port_vlan_add,
6113 .port_vlan_del = mv88e6xxx_port_vlan_del,
6114 .port_fdb_add = mv88e6xxx_port_fdb_add,
6115 .port_fdb_del = mv88e6xxx_port_fdb_del,
6116 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
6117 .port_mdb_add = mv88e6xxx_port_mdb_add,
6118 .port_mdb_del = mv88e6xxx_port_mdb_del,
6119 .port_mirror_add = mv88e6xxx_port_mirror_add,
6120 .port_mirror_del = mv88e6xxx_port_mirror_del,
6121 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
6122 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
6123 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
6124 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
6125 .port_txtstamp = mv88e6xxx_port_txtstamp,
6126 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
6127 .get_ts_info = mv88e6xxx_get_ts_info,
6128 .devlink_param_get = mv88e6xxx_devlink_param_get,
6129 .devlink_param_set = mv88e6xxx_devlink_param_set,
6130 .devlink_info_get = mv88e6xxx_devlink_info_get,
6131 .port_lag_change = mv88e6xxx_port_lag_change,
6132 .port_lag_join = mv88e6xxx_port_lag_join,
6133 .port_lag_leave = mv88e6xxx_port_lag_leave,
6134 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change,
6135 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join,
6136 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave,
6137};
6138
6139static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
6140{
6141 struct device *dev = chip->dev;
6142 struct dsa_switch *ds;
6143
6144 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
6145 if (!ds)
6146 return -ENOMEM;
6147
6148 ds->dev = dev;
6149 ds->num_ports = mv88e6xxx_num_ports(chip);
6150 ds->priv = chip;
6151 ds->dev = dev;
6152 ds->ops = &mv88e6xxx_switch_ops;
6153 ds->ageing_time_min = chip->info->age_time_coeff;
6154 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
6155
6156 /* Some chips support up to 32, but that requires enabling the
6157 * 5-bit port mode, which we do not support. 640k^W16 ought to
6158 * be enough for anyone.
6159 */
6160 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
6161
6162 dev_set_drvdata(dev, ds);
6163
6164 return dsa_register_switch(ds);
6165}
6166
6167static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
6168{
6169 dsa_unregister_switch(chip->ds);
6170}
6171
6172static const void *pdata_device_get_match_data(struct device *dev)
6173{
6174 const struct of_device_id *matches = dev->driver->of_match_table;
6175 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
6176
6177 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
6178 matches++) {
6179 if (!strcmp(pdata->compatible, matches->compatible))
6180 return matches->data;
6181 }
6182 return NULL;
6183}
6184
6185/* There is no suspend to RAM support at DSA level yet, the switch configuration
6186 * would be lost after a power cycle so prevent it to be suspended.
6187 */
6188static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
6189{
6190 return -EOPNOTSUPP;
6191}
6192
6193static int __maybe_unused mv88e6xxx_resume(struct device *dev)
6194{
6195 return 0;
6196}
6197
6198static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
6199
6200static int mv88e6xxx_probe(struct mdio_device *mdiodev)
6201{
6202 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
6203 const struct mv88e6xxx_info *compat_info = NULL;
6204 struct device *dev = &mdiodev->dev;
6205 struct device_node *np = dev->of_node;
6206 struct mv88e6xxx_chip *chip;
6207 int port;
6208 int err;
6209
6210 if (!np && !pdata)
6211 return -EINVAL;
6212
6213 if (np)
6214 compat_info = of_device_get_match_data(dev);
6215
6216 if (pdata) {
6217 compat_info = pdata_device_get_match_data(dev);
6218
6219 if (!pdata->netdev)
6220 return -EINVAL;
6221
6222 for (port = 0; port < DSA_MAX_PORTS; port++) {
6223 if (!(pdata->enabled_ports & (1 << port)))
6224 continue;
6225 if (strcmp(pdata->cd.port_names[port], "cpu"))
6226 continue;
6227 pdata->cd.netdev[port] = &pdata->netdev->dev;
6228 break;
6229 }
6230 }
6231
6232 if (!compat_info)
6233 return -EINVAL;
6234
6235 chip = mv88e6xxx_alloc_chip(dev);
6236 if (!chip) {
6237 err = -ENOMEM;
6238 goto out;
6239 }
6240
6241 chip->info = compat_info;
6242
6243 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
6244 if (err)
6245 goto out;
6246
6247 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
6248 if (IS_ERR(chip->reset)) {
6249 err = PTR_ERR(chip->reset);
6250 goto out;
6251 }
6252 if (chip->reset)
6253 usleep_range(1000, 2000);
6254
6255 err = mv88e6xxx_detect(chip);
6256 if (err)
6257 goto out;
6258
6259 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
6260 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
6261 else
6262 chip->tag_protocol = DSA_TAG_PROTO_DSA;
6263
6264 mv88e6xxx_phy_init(chip);
6265
6266 if (chip->info->ops->get_eeprom) {
6267 if (np)
6268 of_property_read_u32(np, "eeprom-length",
6269 &chip->eeprom_len);
6270 else
6271 chip->eeprom_len = pdata->eeprom_len;
6272 }
6273
6274 mv88e6xxx_reg_lock(chip);
6275 err = mv88e6xxx_switch_reset(chip);
6276 mv88e6xxx_reg_unlock(chip);
6277 if (err)
6278 goto out;
6279
6280 if (np) {
6281 chip->irq = of_irq_get(np, 0);
6282 if (chip->irq == -EPROBE_DEFER) {
6283 err = chip->irq;
6284 goto out;
6285 }
6286 }
6287
6288 if (pdata)
6289 chip->irq = pdata->irq;
6290
6291 /* Has to be performed before the MDIO bus is created, because
6292 * the PHYs will link their interrupts to these interrupt
6293 * controllers
6294 */
6295 mv88e6xxx_reg_lock(chip);
6296 if (chip->irq > 0)
6297 err = mv88e6xxx_g1_irq_setup(chip);
6298 else
6299 err = mv88e6xxx_irq_poll_setup(chip);
6300 mv88e6xxx_reg_unlock(chip);
6301
6302 if (err)
6303 goto out;
6304
6305 if (chip->info->g2_irqs > 0) {
6306 err = mv88e6xxx_g2_irq_setup(chip);
6307 if (err)
6308 goto out_g1_irq;
6309 }
6310
6311 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
6312 if (err)
6313 goto out_g2_irq;
6314
6315 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
6316 if (err)
6317 goto out_g1_atu_prob_irq;
6318
6319 err = mv88e6xxx_mdios_register(chip, np);
6320 if (err)
6321 goto out_g1_vtu_prob_irq;
6322
6323 err = mv88e6xxx_register_switch(chip);
6324 if (err)
6325 goto out_mdio;
6326
6327 return 0;
6328
6329out_mdio:
6330 mv88e6xxx_mdios_unregister(chip);
6331out_g1_vtu_prob_irq:
6332 mv88e6xxx_g1_vtu_prob_irq_free(chip);
6333out_g1_atu_prob_irq:
6334 mv88e6xxx_g1_atu_prob_irq_free(chip);
6335out_g2_irq:
6336 if (chip->info->g2_irqs > 0)
6337 mv88e6xxx_g2_irq_free(chip);
6338out_g1_irq:
6339 if (chip->irq > 0)
6340 mv88e6xxx_g1_irq_free(chip);
6341 else
6342 mv88e6xxx_irq_poll_free(chip);
6343out:
6344 if (pdata)
6345 dev_put(pdata->netdev);
6346
6347 return err;
6348}
6349
6350static void mv88e6xxx_remove(struct mdio_device *mdiodev)
6351{
6352 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
6353 struct mv88e6xxx_chip *chip = ds->priv;
6354
6355 if (chip->info->ptp_support) {
6356 mv88e6xxx_hwtstamp_free(chip);
6357 mv88e6xxx_ptp_free(chip);
6358 }
6359
6360 mv88e6xxx_phy_destroy(chip);
6361 mv88e6xxx_unregister_switch(chip);
6362 mv88e6xxx_mdios_unregister(chip);
6363
6364 mv88e6xxx_g1_vtu_prob_irq_free(chip);
6365 mv88e6xxx_g1_atu_prob_irq_free(chip);
6366
6367 if (chip->info->g2_irqs > 0)
6368 mv88e6xxx_g2_irq_free(chip);
6369
6370 if (chip->irq > 0)
6371 mv88e6xxx_g1_irq_free(chip);
6372 else
6373 mv88e6xxx_irq_poll_free(chip);
6374}
6375
6376static const struct of_device_id mv88e6xxx_of_match[] = {
6377 {
6378 .compatible = "marvell,mv88e6085",
6379 .data = &mv88e6xxx_table[MV88E6085],
6380 },
6381 {
6382 .compatible = "marvell,mv88e6190",
6383 .data = &mv88e6xxx_table[MV88E6190],
6384 },
6385 {
6386 .compatible = "marvell,mv88e6250",
6387 .data = &mv88e6xxx_table[MV88E6250],
6388 },
6389 { /* sentinel */ },
6390};
6391
6392MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
6393
6394static struct mdio_driver mv88e6xxx_driver = {
6395 .probe = mv88e6xxx_probe,
6396 .remove = mv88e6xxx_remove,
6397 .mdiodrv.driver = {
6398 .name = "mv88e6085",
6399 .of_match_table = mv88e6xxx_of_match,
6400 .pm = &mv88e6xxx_pm_ops,
6401 },
6402};
6403
6404mdio_module_driver(mv88e6xxx_driver);
6405
6406MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
6407MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
6408MODULE_LICENSE("GPL");