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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 *
9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 */
12
13#include <linux/bitfield.h>
14#include <linux/delay.h>
15#include <linux/dsa/mv88e6xxx.h>
16#include <linux/etherdevice.h>
17#include <linux/ethtool.h>
18#include <linux/if_bridge.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/irqdomain.h>
22#include <linux/jiffies.h>
23#include <linux/list.h>
24#include <linux/mdio.h>
25#include <linux/module.h>
26#include <linux/of.h>
27#include <linux/of_irq.h>
28#include <linux/of_mdio.h>
29#include <linux/platform_data/mv88e6xxx.h>
30#include <linux/property.h>
31#include <linux/netdevice.h>
32#include <linux/gpio/consumer.h>
33#include <linux/phylink.h>
34#include <net/dsa.h>
35
36#include "chip.h"
37#include "devlink.h"
38#include "global1.h"
39#include "global2.h"
40#include "hwtstamp.h"
41#include "phy.h"
42#include "port.h"
43#include "ptp.h"
44#include "serdes.h"
45#include "smi.h"
46
47static void assert_reg_lock(struct mv88e6xxx_chip *chip)
48{
49 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
50 dev_err(chip->dev, "Switch registers lock not held!\n");
51 dump_stack();
52 }
53}
54
55int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
56{
57 int err;
58
59 assert_reg_lock(chip);
60
61 err = mv88e6xxx_smi_read(chip, addr, reg, val);
62 if (err)
63 return err;
64
65 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
66 addr, reg, *val);
67
68 return 0;
69}
70
71int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
72{
73 int err;
74
75 assert_reg_lock(chip);
76
77 err = mv88e6xxx_smi_write(chip, addr, reg, val);
78 if (err)
79 return err;
80
81 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
82 addr, reg, val);
83
84 return 0;
85}
86
87int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
88 u16 mask, u16 val)
89{
90 const unsigned long timeout = jiffies + msecs_to_jiffies(50);
91 u16 data;
92 int err;
93 int i;
94
95 /* There's no bus specific operation to wait for a mask. Even
96 * if the initial poll takes longer than 50ms, always do at
97 * least one more attempt.
98 */
99 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) {
100 err = mv88e6xxx_read(chip, addr, reg, &data);
101 if (err)
102 return err;
103
104 if ((data & mask) == val)
105 return 0;
106
107 if (i < 2)
108 cpu_relax();
109 else
110 usleep_range(1000, 2000);
111 }
112
113 err = mv88e6xxx_read(chip, addr, reg, &data);
114 if (err)
115 return err;
116
117 if ((data & mask) == val)
118 return 0;
119
120 dev_err(chip->dev, "Timeout while waiting for switch\n");
121 return -ETIMEDOUT;
122}
123
124int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
125 int bit, int val)
126{
127 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
128 val ? BIT(bit) : 0x0000);
129}
130
131struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
132{
133 struct mv88e6xxx_mdio_bus *mdio_bus;
134
135 mdio_bus = list_first_entry_or_null(&chip->mdios,
136 struct mv88e6xxx_mdio_bus, list);
137 if (!mdio_bus)
138 return NULL;
139
140 return mdio_bus->bus;
141}
142
143static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
144{
145 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
146 unsigned int n = d->hwirq;
147
148 chip->g1_irq.masked |= (1 << n);
149}
150
151static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
152{
153 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
154 unsigned int n = d->hwirq;
155
156 chip->g1_irq.masked &= ~(1 << n);
157}
158
159static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
160{
161 unsigned int nhandled = 0;
162 unsigned int sub_irq;
163 unsigned int n;
164 u16 reg;
165 u16 ctl1;
166 int err;
167
168 mv88e6xxx_reg_lock(chip);
169 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
170 mv88e6xxx_reg_unlock(chip);
171
172 if (err)
173 goto out;
174
175 do {
176 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
177 if (reg & (1 << n)) {
178 sub_irq = irq_find_mapping(chip->g1_irq.domain,
179 n);
180 handle_nested_irq(sub_irq);
181 ++nhandled;
182 }
183 }
184
185 mv88e6xxx_reg_lock(chip);
186 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
187 if (err)
188 goto unlock;
189 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
190unlock:
191 mv88e6xxx_reg_unlock(chip);
192 if (err)
193 goto out;
194 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
195 } while (reg & ctl1);
196
197out:
198 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
199}
200
201static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
202{
203 struct mv88e6xxx_chip *chip = dev_id;
204
205 return mv88e6xxx_g1_irq_thread_work(chip);
206}
207
208static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
209{
210 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
211
212 mv88e6xxx_reg_lock(chip);
213}
214
215static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
216{
217 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
218 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
219 u16 reg;
220 int err;
221
222 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
223 if (err)
224 goto out;
225
226 reg &= ~mask;
227 reg |= (~chip->g1_irq.masked & mask);
228
229 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
230 if (err)
231 goto out;
232
233out:
234 mv88e6xxx_reg_unlock(chip);
235}
236
237static const struct irq_chip mv88e6xxx_g1_irq_chip = {
238 .name = "mv88e6xxx-g1",
239 .irq_mask = mv88e6xxx_g1_irq_mask,
240 .irq_unmask = mv88e6xxx_g1_irq_unmask,
241 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
242 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
243};
244
245static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
246 unsigned int irq,
247 irq_hw_number_t hwirq)
248{
249 struct mv88e6xxx_chip *chip = d->host_data;
250
251 irq_set_chip_data(irq, d->host_data);
252 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
253 irq_set_noprobe(irq);
254
255 return 0;
256}
257
258static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
259 .map = mv88e6xxx_g1_irq_domain_map,
260 .xlate = irq_domain_xlate_twocell,
261};
262
263/* To be called with reg_lock held */
264static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
265{
266 int irq, virq;
267 u16 mask;
268
269 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
270 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
271 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
272
273 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
274 virq = irq_find_mapping(chip->g1_irq.domain, irq);
275 irq_dispose_mapping(virq);
276 }
277
278 irq_domain_remove(chip->g1_irq.domain);
279}
280
281static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
282{
283 /*
284 * free_irq must be called without reg_lock taken because the irq
285 * handler takes this lock, too.
286 */
287 free_irq(chip->irq, chip);
288
289 mv88e6xxx_reg_lock(chip);
290 mv88e6xxx_g1_irq_free_common(chip);
291 mv88e6xxx_reg_unlock(chip);
292}
293
294static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
295{
296 int err, irq, virq;
297 u16 reg, mask;
298
299 chip->g1_irq.nirqs = chip->info->g1_irqs;
300 chip->g1_irq.domain = irq_domain_add_simple(
301 NULL, chip->g1_irq.nirqs, 0,
302 &mv88e6xxx_g1_irq_domain_ops, chip);
303 if (!chip->g1_irq.domain)
304 return -ENOMEM;
305
306 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
307 irq_create_mapping(chip->g1_irq.domain, irq);
308
309 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
310 chip->g1_irq.masked = ~0;
311
312 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
313 if (err)
314 goto out_mapping;
315
316 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
317
318 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
319 if (err)
320 goto out_disable;
321
322 /* Reading the interrupt status clears (most of) them */
323 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
324 if (err)
325 goto out_disable;
326
327 return 0;
328
329out_disable:
330 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
331 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
332
333out_mapping:
334 for (irq = 0; irq < 16; irq++) {
335 virq = irq_find_mapping(chip->g1_irq.domain, irq);
336 irq_dispose_mapping(virq);
337 }
338
339 irq_domain_remove(chip->g1_irq.domain);
340
341 return err;
342}
343
344static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
345{
346 static struct lock_class_key lock_key;
347 static struct lock_class_key request_key;
348 int err;
349
350 err = mv88e6xxx_g1_irq_setup_common(chip);
351 if (err)
352 return err;
353
354 /* These lock classes tells lockdep that global 1 irqs are in
355 * a different category than their parent GPIO, so it won't
356 * report false recursion.
357 */
358 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
359
360 snprintf(chip->irq_name, sizeof(chip->irq_name),
361 "mv88e6xxx-%s", dev_name(chip->dev));
362
363 mv88e6xxx_reg_unlock(chip);
364 err = request_threaded_irq(chip->irq, NULL,
365 mv88e6xxx_g1_irq_thread_fn,
366 IRQF_ONESHOT | IRQF_SHARED,
367 chip->irq_name, chip);
368 mv88e6xxx_reg_lock(chip);
369 if (err)
370 mv88e6xxx_g1_irq_free_common(chip);
371
372 return err;
373}
374
375static void mv88e6xxx_irq_poll(struct kthread_work *work)
376{
377 struct mv88e6xxx_chip *chip = container_of(work,
378 struct mv88e6xxx_chip,
379 irq_poll_work.work);
380 mv88e6xxx_g1_irq_thread_work(chip);
381
382 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
383 msecs_to_jiffies(100));
384}
385
386static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
387{
388 int err;
389
390 err = mv88e6xxx_g1_irq_setup_common(chip);
391 if (err)
392 return err;
393
394 kthread_init_delayed_work(&chip->irq_poll_work,
395 mv88e6xxx_irq_poll);
396
397 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
398 if (IS_ERR(chip->kworker))
399 return PTR_ERR(chip->kworker);
400
401 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
402 msecs_to_jiffies(100));
403
404 return 0;
405}
406
407static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
408{
409 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
410 kthread_destroy_worker(chip->kworker);
411
412 mv88e6xxx_reg_lock(chip);
413 mv88e6xxx_g1_irq_free_common(chip);
414 mv88e6xxx_reg_unlock(chip);
415}
416
417static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
418 int port, phy_interface_t interface)
419{
420 int err;
421
422 if (chip->info->ops->port_set_rgmii_delay) {
423 err = chip->info->ops->port_set_rgmii_delay(chip, port,
424 interface);
425 if (err && err != -EOPNOTSUPP)
426 return err;
427 }
428
429 if (chip->info->ops->port_set_cmode) {
430 err = chip->info->ops->port_set_cmode(chip, port,
431 interface);
432 if (err && err != -EOPNOTSUPP)
433 return err;
434 }
435
436 return 0;
437}
438
439static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
440 int link, int speed, int duplex, int pause,
441 phy_interface_t mode)
442{
443 int err;
444
445 if (!chip->info->ops->port_set_link)
446 return 0;
447
448 /* Port's MAC control must not be changed unless the link is down */
449 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
450 if (err)
451 return err;
452
453 if (chip->info->ops->port_set_speed_duplex) {
454 err = chip->info->ops->port_set_speed_duplex(chip, port,
455 speed, duplex);
456 if (err && err != -EOPNOTSUPP)
457 goto restore_link;
458 }
459
460 if (chip->info->ops->port_set_pause) {
461 err = chip->info->ops->port_set_pause(chip, port, pause);
462 if (err)
463 goto restore_link;
464 }
465
466 err = mv88e6xxx_port_config_interface(chip, port, mode);
467restore_link:
468 if (chip->info->ops->port_set_link(chip, port, link))
469 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
470
471 return err;
472}
473
474static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
475{
476 return port >= chip->info->internal_phys_offset &&
477 port < chip->info->num_internal_phys +
478 chip->info->internal_phys_offset;
479}
480
481static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
482{
483 u16 reg;
484 int err;
485
486 /* The 88e6250 family does not have the PHY detect bit. Instead,
487 * report whether the port is internal.
488 */
489 if (chip->info->family == MV88E6XXX_FAMILY_6250)
490 return mv88e6xxx_phy_is_internal(chip, port);
491
492 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
493 if (err) {
494 dev_err(chip->dev,
495 "p%d: %s: failed to read port status\n",
496 port, __func__);
497 return err;
498 }
499
500 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
501}
502
503static const u8 mv88e6185_phy_interface_modes[] = {
504 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII,
505 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII,
506 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII,
507 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII,
508 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX,
509 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX,
510 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII,
511};
512
513static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
514 struct phylink_config *config)
515{
516 u8 cmode = chip->ports[port].cmode;
517
518 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
519
520 if (mv88e6xxx_phy_is_internal(chip, port)) {
521 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
522 } else {
523 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
524 mv88e6185_phy_interface_modes[cmode])
525 __set_bit(mv88e6185_phy_interface_modes[cmode],
526 config->supported_interfaces);
527
528 config->mac_capabilities |= MAC_1000FD;
529 }
530}
531
532static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
533 struct phylink_config *config)
534{
535 u8 cmode = chip->ports[port].cmode;
536
537 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
538 mv88e6185_phy_interface_modes[cmode])
539 __set_bit(mv88e6185_phy_interface_modes[cmode],
540 config->supported_interfaces);
541
542 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
543 MAC_1000FD;
544}
545
546static const u8 mv88e6xxx_phy_interface_modes[] = {
547 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII,
548 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII,
549 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII,
550 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII,
551 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII,
552 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX,
553 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX,
554 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII,
555 /* higher interface modes are not needed here, since ports supporting
556 * them are writable, and so the supported interfaces are filled in the
557 * corresponding .phylink_set_interfaces() implementation below
558 */
559};
560
561static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported)
562{
563 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) &&
564 mv88e6xxx_phy_interface_modes[cmode])
565 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported);
566 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII)
567 phy_interface_set_rgmii(supported);
568}
569
570static void
571mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port,
572 struct phylink_config *config)
573{
574 unsigned long *supported = config->supported_interfaces;
575 int err;
576 u16 reg;
577
578 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
579 if (err) {
580 dev_err(chip->dev, "p%d: failed to read port status\n", port);
581 return;
582 }
583
584 switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) {
585 case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY:
586 case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY:
587 case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY:
588 case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY:
589 __set_bit(PHY_INTERFACE_MODE_REVMII, supported);
590 break;
591
592 case MV88E6250_PORT_STS_PORTMODE_MII_HALF:
593 case MV88E6250_PORT_STS_PORTMODE_MII_FULL:
594 __set_bit(PHY_INTERFACE_MODE_MII, supported);
595 break;
596
597 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY:
598 case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY:
599 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY:
600 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY:
601 __set_bit(PHY_INTERFACE_MODE_REVRMII, supported);
602 break;
603
604 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL:
605 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL:
606 __set_bit(PHY_INTERFACE_MODE_RMII, supported);
607 break;
608
609 case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII:
610 __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
611 break;
612
613 default:
614 dev_err(chip->dev,
615 "p%d: invalid port mode in status register: %04x\n",
616 port, reg);
617 }
618}
619
620static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
621 struct phylink_config *config)
622{
623 if (!mv88e6xxx_phy_is_internal(chip, port))
624 mv88e6250_setup_supported_interfaces(chip, port, config);
625
626 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
627}
628
629static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
630 struct phylink_config *config)
631{
632 unsigned long *supported = config->supported_interfaces;
633
634 /* Translate the default cmode */
635 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
636
637 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
638 MAC_1000FD;
639}
640
641static int mv88e63xx_get_port_serdes_cmode(struct mv88e6xxx_chip *chip, int port)
642{
643 u16 reg, val;
644 int err;
645
646 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
647 if (err)
648 return err;
649
650 /* If PHY_DETECT is zero, then we are not in auto-media mode */
651 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT))
652 return 0xf;
653
654 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT;
655 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, val);
656 if (err)
657 return err;
658
659 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &val);
660 if (err)
661 return err;
662
663 /* Restore PHY_DETECT value */
664 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
665 if (err)
666 return err;
667
668 return val & MV88E6XXX_PORT_STS_CMODE_MASK;
669}
670
671static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
672 struct phylink_config *config)
673{
674 unsigned long *supported = config->supported_interfaces;
675 int err, cmode;
676
677 /* Translate the default cmode */
678 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
679
680 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
681 MAC_1000FD;
682
683 /* Port 4 supports automedia if the serdes is associated with it. */
684 if (port == 4) {
685 err = mv88e6352_g2_scratch_port_has_serdes(chip, port);
686 if (err < 0)
687 dev_err(chip->dev, "p%d: failed to read scratch\n",
688 port);
689 if (err <= 0)
690 return;
691
692 cmode = mv88e63xx_get_port_serdes_cmode(chip, port);
693 if (cmode < 0)
694 dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
695 port);
696 else
697 mv88e6xxx_translate_cmode(cmode, supported);
698 }
699}
700
701static void mv88e632x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
702 struct phylink_config *config)
703{
704 unsigned long *supported = config->supported_interfaces;
705 int cmode;
706
707 /* Translate the default cmode */
708 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
709
710 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
711 MAC_1000FD;
712
713 /* Port 0/1 are serdes only ports */
714 if (port == 0 || port == 1) {
715 cmode = mv88e63xx_get_port_serdes_cmode(chip, port);
716 if (cmode < 0)
717 dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
718 port);
719 else
720 mv88e6xxx_translate_cmode(cmode, supported);
721 }
722}
723
724static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
725 struct phylink_config *config)
726{
727 unsigned long *supported = config->supported_interfaces;
728
729 /* Translate the default cmode */
730 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
731
732 /* No ethtool bits for 200Mbps */
733 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
734 MAC_1000FD;
735
736 /* The C_Mode field is programmable on port 5 */
737 if (port == 5) {
738 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
739 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
740 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
741
742 config->mac_capabilities |= MAC_2500FD;
743 }
744}
745
746static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
747 struct phylink_config *config)
748{
749 unsigned long *supported = config->supported_interfaces;
750
751 /* Translate the default cmode */
752 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
753
754 /* No ethtool bits for 200Mbps */
755 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
756 MAC_1000FD;
757
758 /* The C_Mode field is programmable on ports 9 and 10 */
759 if (port == 9 || port == 10) {
760 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
761 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
762 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
763
764 config->mac_capabilities |= MAC_2500FD;
765 }
766}
767
768static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
769 struct phylink_config *config)
770{
771 unsigned long *supported = config->supported_interfaces;
772
773 mv88e6390_phylink_get_caps(chip, port, config);
774
775 /* For the 6x90X, ports 2-7 can be in automedia mode.
776 * (Note that 6x90 doesn't support RXAUI nor XAUI).
777 *
778 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is
779 * configured for 1000BASE-X, SGMII or 2500BASE-X.
780 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is
781 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
782 *
783 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is
784 * configured for 1000BASE-X, SGMII or 2500BASE-X.
785 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is
786 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
787 *
788 * For now, be permissive (as the old code was) and allow 1000BASE-X
789 * on ports 2..7.
790 */
791 if (port >= 2 && port <= 7)
792 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
793
794 /* The C_Mode field can also be programmed for 10G speeds */
795 if (port == 9 || port == 10) {
796 __set_bit(PHY_INTERFACE_MODE_XAUI, supported);
797 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported);
798
799 config->mac_capabilities |= MAC_10000FD;
800 }
801}
802
803static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
804 struct phylink_config *config)
805{
806 unsigned long *supported = config->supported_interfaces;
807 bool is_6191x =
808 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
809 bool is_6361 =
810 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361;
811
812 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
813
814 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
815 MAC_1000FD;
816
817 /* The C_Mode field can be programmed for ports 0, 9 and 10 */
818 if (port == 0 || port == 9 || port == 10) {
819 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
820 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
821
822 /* 6191X supports >1G modes only on port 10 */
823 if (!is_6191x || port == 10) {
824 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
825 config->mac_capabilities |= MAC_2500FD;
826
827 /* 6361 only supports up to 2500BaseX */
828 if (!is_6361) {
829 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
830 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
831 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported);
832 config->mac_capabilities |= MAC_5000FD |
833 MAC_10000FD;
834 }
835 }
836 }
837
838 if (port == 0) {
839 __set_bit(PHY_INTERFACE_MODE_RMII, supported);
840 __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
841 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported);
842 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported);
843 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported);
844 }
845}
846
847static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port,
848 struct phylink_config *config)
849{
850 struct mv88e6xxx_chip *chip = ds->priv;
851
852 mv88e6xxx_reg_lock(chip);
853 chip->info->ops->phylink_get_caps(chip, port, config);
854 mv88e6xxx_reg_unlock(chip);
855
856 if (mv88e6xxx_phy_is_internal(chip, port)) {
857 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
858 config->supported_interfaces);
859 /* Internal ports with no phy-mode need GMII for PHYLIB */
860 __set_bit(PHY_INTERFACE_MODE_GMII,
861 config->supported_interfaces);
862 }
863}
864
865static struct phylink_pcs *
866mv88e6xxx_mac_select_pcs(struct phylink_config *config,
867 phy_interface_t interface)
868{
869 struct dsa_port *dp = dsa_phylink_to_port(config);
870 struct mv88e6xxx_chip *chip = dp->ds->priv;
871 struct phylink_pcs *pcs = NULL;
872
873 if (chip->info->ops->pcs_ops)
874 pcs = chip->info->ops->pcs_ops->pcs_select(chip, dp->index,
875 interface);
876
877 return pcs;
878}
879
880static int mv88e6xxx_mac_prepare(struct phylink_config *config,
881 unsigned int mode, phy_interface_t interface)
882{
883 struct dsa_port *dp = dsa_phylink_to_port(config);
884 struct mv88e6xxx_chip *chip = dp->ds->priv;
885 int port = dp->index;
886 int err = 0;
887
888 /* In inband mode, the link may come up at any time while the link
889 * is not forced down. Force the link down while we reconfigure the
890 * interface mode.
891 */
892 if (mode == MLO_AN_INBAND &&
893 chip->ports[port].interface != interface &&
894 chip->info->ops->port_set_link) {
895 mv88e6xxx_reg_lock(chip);
896 err = chip->info->ops->port_set_link(chip, port,
897 LINK_FORCED_DOWN);
898 mv88e6xxx_reg_unlock(chip);
899 }
900
901 return err;
902}
903
904static void mv88e6xxx_mac_config(struct phylink_config *config,
905 unsigned int mode,
906 const struct phylink_link_state *state)
907{
908 struct dsa_port *dp = dsa_phylink_to_port(config);
909 struct mv88e6xxx_chip *chip = dp->ds->priv;
910 int port = dp->index;
911 int err = 0;
912
913 mv88e6xxx_reg_lock(chip);
914
915 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) {
916 err = mv88e6xxx_port_config_interface(chip, port,
917 state->interface);
918 if (err && err != -EOPNOTSUPP)
919 goto err_unlock;
920 }
921
922err_unlock:
923 mv88e6xxx_reg_unlock(chip);
924
925 if (err && err != -EOPNOTSUPP)
926 dev_err(chip->dev, "p%d: failed to configure MAC/PCS\n", port);
927}
928
929static int mv88e6xxx_mac_finish(struct phylink_config *config,
930 unsigned int mode, phy_interface_t interface)
931{
932 struct dsa_port *dp = dsa_phylink_to_port(config);
933 struct mv88e6xxx_chip *chip = dp->ds->priv;
934 int port = dp->index;
935 int err = 0;
936
937 /* Undo the forced down state above after completing configuration
938 * irrespective of its state on entry, which allows the link to come
939 * up in the in-band case where there is no separate SERDES. Also
940 * ensure that the link can come up if the PPU is in use and we are
941 * in PHY mode (we treat the PPU as an effective in-band mechanism.)
942 */
943 mv88e6xxx_reg_lock(chip);
944
945 if (chip->info->ops->port_set_link &&
946 ((mode == MLO_AN_INBAND &&
947 chip->ports[port].interface != interface) ||
948 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
949 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
950
951 mv88e6xxx_reg_unlock(chip);
952
953 chip->ports[port].interface = interface;
954
955 return err;
956}
957
958static void mv88e6xxx_mac_link_down(struct phylink_config *config,
959 unsigned int mode,
960 phy_interface_t interface)
961{
962 struct dsa_port *dp = dsa_phylink_to_port(config);
963 struct mv88e6xxx_chip *chip = dp->ds->priv;
964 const struct mv88e6xxx_ops *ops;
965 int port = dp->index;
966 int err = 0;
967
968 ops = chip->info->ops;
969
970 mv88e6xxx_reg_lock(chip);
971 /* Force the link down if we know the port may not be automatically
972 * updated by the switch or if we are using fixed-link mode.
973 */
974 if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
975 mode == MLO_AN_FIXED) && ops->port_sync_link)
976 err = ops->port_sync_link(chip, port, mode, false);
977
978 if (!err && ops->port_set_speed_duplex)
979 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED,
980 DUPLEX_UNFORCED);
981 mv88e6xxx_reg_unlock(chip);
982
983 if (err)
984 dev_err(chip->dev,
985 "p%d: failed to force MAC link down\n", port);
986}
987
988static void mv88e6xxx_mac_link_up(struct phylink_config *config,
989 struct phy_device *phydev,
990 unsigned int mode, phy_interface_t interface,
991 int speed, int duplex,
992 bool tx_pause, bool rx_pause)
993{
994 struct dsa_port *dp = dsa_phylink_to_port(config);
995 struct mv88e6xxx_chip *chip = dp->ds->priv;
996 const struct mv88e6xxx_ops *ops;
997 int port = dp->index;
998 int err = 0;
999
1000 ops = chip->info->ops;
1001
1002 mv88e6xxx_reg_lock(chip);
1003 /* Configure and force the link up if we know that the port may not
1004 * automatically updated by the switch or if we are using fixed-link
1005 * mode.
1006 */
1007 if (!mv88e6xxx_port_ppu_updates(chip, port) ||
1008 mode == MLO_AN_FIXED) {
1009 if (ops->port_set_speed_duplex) {
1010 err = ops->port_set_speed_duplex(chip, port,
1011 speed, duplex);
1012 if (err && err != -EOPNOTSUPP)
1013 goto error;
1014 }
1015
1016 if (ops->port_sync_link)
1017 err = ops->port_sync_link(chip, port, mode, true);
1018 }
1019error:
1020 mv88e6xxx_reg_unlock(chip);
1021
1022 if (err && err != -EOPNOTSUPP)
1023 dev_err(chip->dev,
1024 "p%d: failed to configure MAC link up\n", port);
1025}
1026
1027static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
1028{
1029 int err;
1030
1031 if (!chip->info->ops->stats_snapshot)
1032 return -EOPNOTSUPP;
1033
1034 mv88e6xxx_reg_lock(chip);
1035 err = chip->info->ops->stats_snapshot(chip, port);
1036 mv88e6xxx_reg_unlock(chip);
1037
1038 return err;
1039}
1040
1041#define MV88E6XXX_HW_STAT_MAPPER(_fn) \
1042 _fn(in_good_octets, 8, 0x00, STATS_TYPE_BANK0), \
1043 _fn(in_bad_octets, 4, 0x02, STATS_TYPE_BANK0), \
1044 _fn(in_unicast, 4, 0x04, STATS_TYPE_BANK0), \
1045 _fn(in_broadcasts, 4, 0x06, STATS_TYPE_BANK0), \
1046 _fn(in_multicasts, 4, 0x07, STATS_TYPE_BANK0), \
1047 _fn(in_pause, 4, 0x16, STATS_TYPE_BANK0), \
1048 _fn(in_undersize, 4, 0x18, STATS_TYPE_BANK0), \
1049 _fn(in_fragments, 4, 0x19, STATS_TYPE_BANK0), \
1050 _fn(in_oversize, 4, 0x1a, STATS_TYPE_BANK0), \
1051 _fn(in_jabber, 4, 0x1b, STATS_TYPE_BANK0), \
1052 _fn(in_rx_error, 4, 0x1c, STATS_TYPE_BANK0), \
1053 _fn(in_fcs_error, 4, 0x1d, STATS_TYPE_BANK0), \
1054 _fn(out_octets, 8, 0x0e, STATS_TYPE_BANK0), \
1055 _fn(out_unicast, 4, 0x10, STATS_TYPE_BANK0), \
1056 _fn(out_broadcasts, 4, 0x13, STATS_TYPE_BANK0), \
1057 _fn(out_multicasts, 4, 0x12, STATS_TYPE_BANK0), \
1058 _fn(out_pause, 4, 0x15, STATS_TYPE_BANK0), \
1059 _fn(excessive, 4, 0x11, STATS_TYPE_BANK0), \
1060 _fn(collisions, 4, 0x1e, STATS_TYPE_BANK0), \
1061 _fn(deferred, 4, 0x05, STATS_TYPE_BANK0), \
1062 _fn(single, 4, 0x14, STATS_TYPE_BANK0), \
1063 _fn(multiple, 4, 0x17, STATS_TYPE_BANK0), \
1064 _fn(out_fcs_error, 4, 0x03, STATS_TYPE_BANK0), \
1065 _fn(late, 4, 0x1f, STATS_TYPE_BANK0), \
1066 _fn(hist_64bytes, 4, 0x08, STATS_TYPE_BANK0), \
1067 _fn(hist_65_127bytes, 4, 0x09, STATS_TYPE_BANK0), \
1068 _fn(hist_128_255bytes, 4, 0x0a, STATS_TYPE_BANK0), \
1069 _fn(hist_256_511bytes, 4, 0x0b, STATS_TYPE_BANK0), \
1070 _fn(hist_512_1023bytes, 4, 0x0c, STATS_TYPE_BANK0), \
1071 _fn(hist_1024_max_bytes, 4, 0x0d, STATS_TYPE_BANK0), \
1072 _fn(sw_in_discards, 4, 0x10, STATS_TYPE_PORT), \
1073 _fn(sw_in_filtered, 2, 0x12, STATS_TYPE_PORT), \
1074 _fn(sw_out_filtered, 2, 0x13, STATS_TYPE_PORT), \
1075 _fn(in_discards, 4, 0x00, STATS_TYPE_BANK1), \
1076 _fn(in_filtered, 4, 0x01, STATS_TYPE_BANK1), \
1077 _fn(in_accepted, 4, 0x02, STATS_TYPE_BANK1), \
1078 _fn(in_bad_accepted, 4, 0x03, STATS_TYPE_BANK1), \
1079 _fn(in_good_avb_class_a, 4, 0x04, STATS_TYPE_BANK1), \
1080 _fn(in_good_avb_class_b, 4, 0x05, STATS_TYPE_BANK1), \
1081 _fn(in_bad_avb_class_a, 4, 0x06, STATS_TYPE_BANK1), \
1082 _fn(in_bad_avb_class_b, 4, 0x07, STATS_TYPE_BANK1), \
1083 _fn(tcam_counter_0, 4, 0x08, STATS_TYPE_BANK1), \
1084 _fn(tcam_counter_1, 4, 0x09, STATS_TYPE_BANK1), \
1085 _fn(tcam_counter_2, 4, 0x0a, STATS_TYPE_BANK1), \
1086 _fn(tcam_counter_3, 4, 0x0b, STATS_TYPE_BANK1), \
1087 _fn(in_da_unknown, 4, 0x0e, STATS_TYPE_BANK1), \
1088 _fn(in_management, 4, 0x0f, STATS_TYPE_BANK1), \
1089 _fn(out_queue_0, 4, 0x10, STATS_TYPE_BANK1), \
1090 _fn(out_queue_1, 4, 0x11, STATS_TYPE_BANK1), \
1091 _fn(out_queue_2, 4, 0x12, STATS_TYPE_BANK1), \
1092 _fn(out_queue_3, 4, 0x13, STATS_TYPE_BANK1), \
1093 _fn(out_queue_4, 4, 0x14, STATS_TYPE_BANK1), \
1094 _fn(out_queue_5, 4, 0x15, STATS_TYPE_BANK1), \
1095 _fn(out_queue_6, 4, 0x16, STATS_TYPE_BANK1), \
1096 _fn(out_queue_7, 4, 0x17, STATS_TYPE_BANK1), \
1097 _fn(out_cut_through, 4, 0x18, STATS_TYPE_BANK1), \
1098 _fn(out_octets_a, 4, 0x1a, STATS_TYPE_BANK1), \
1099 _fn(out_octets_b, 4, 0x1b, STATS_TYPE_BANK1), \
1100 _fn(out_management, 4, 0x1f, STATS_TYPE_BANK1), \
1101 /* */
1102
1103#define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \
1104 { #_string, _size, _reg, _type }
1105static const struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
1106 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENTRY)
1107};
1108
1109#define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \
1110 MV88E6XXX_HW_STAT_ID_ ## _string
1111enum mv88e6xxx_hw_stat_id {
1112 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENUM)
1113};
1114
1115static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
1116 const struct mv88e6xxx_hw_stat *s,
1117 int port, u16 bank1_select,
1118 u16 histogram)
1119{
1120 u32 low;
1121 u32 high = 0;
1122 u16 reg = 0;
1123 int err;
1124 u64 value;
1125
1126 switch (s->type) {
1127 case STATS_TYPE_PORT:
1128 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
1129 if (err)
1130 return U64_MAX;
1131
1132 low = reg;
1133 if (s->size == 4) {
1134 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
1135 if (err)
1136 return U64_MAX;
1137 low |= ((u32)reg) << 16;
1138 }
1139 break;
1140 case STATS_TYPE_BANK1:
1141 reg = bank1_select;
1142 fallthrough;
1143 case STATS_TYPE_BANK0:
1144 reg |= s->reg | histogram;
1145 mv88e6xxx_g1_stats_read(chip, reg, &low);
1146 if (s->size == 8)
1147 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
1148 break;
1149 default:
1150 return U64_MAX;
1151 }
1152 value = (((u64)high) << 32) | low;
1153 return value;
1154}
1155
1156static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
1157 uint8_t **data, int types)
1158{
1159 const struct mv88e6xxx_hw_stat *stat;
1160 int i;
1161
1162 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1163 stat = &mv88e6xxx_hw_stats[i];
1164 if (stat->type & types)
1165 ethtool_puts(data, stat->string);
1166 }
1167}
1168
1169static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
1170 uint8_t **data)
1171{
1172 mv88e6xxx_stats_get_strings(chip, data,
1173 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
1174}
1175
1176static void mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
1177 uint8_t **data)
1178{
1179 mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
1180}
1181
1182static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
1183 uint8_t **data)
1184{
1185 mv88e6xxx_stats_get_strings(chip, data,
1186 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
1187}
1188
1189static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
1190 "atu_member_violation",
1191 "atu_miss_violation",
1192 "atu_full_violation",
1193 "vtu_member_violation",
1194 "vtu_miss_violation",
1195};
1196
1197static void mv88e6xxx_atu_vtu_get_strings(uint8_t **data)
1198{
1199 unsigned int i;
1200
1201 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
1202 ethtool_puts(data, mv88e6xxx_atu_vtu_stats_strings[i]);
1203}
1204
1205static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
1206 u32 stringset, uint8_t *data)
1207{
1208 struct mv88e6xxx_chip *chip = ds->priv;
1209
1210 if (stringset != ETH_SS_STATS)
1211 return;
1212
1213 mv88e6xxx_reg_lock(chip);
1214
1215 if (chip->info->ops->stats_get_strings)
1216 chip->info->ops->stats_get_strings(chip, &data);
1217
1218 if (chip->info->ops->serdes_get_strings)
1219 chip->info->ops->serdes_get_strings(chip, port, &data);
1220
1221 mv88e6xxx_atu_vtu_get_strings(&data);
1222
1223 mv88e6xxx_reg_unlock(chip);
1224}
1225
1226static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1227 int types)
1228{
1229 const struct mv88e6xxx_hw_stat *stat;
1230 int i, j;
1231
1232 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1233 stat = &mv88e6xxx_hw_stats[i];
1234 if (stat->type & types)
1235 j++;
1236 }
1237 return j;
1238}
1239
1240static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1241{
1242 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1243 STATS_TYPE_PORT);
1244}
1245
1246static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1247{
1248 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1249}
1250
1251static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1252{
1253 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1254 STATS_TYPE_BANK1);
1255}
1256
1257static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1258{
1259 struct mv88e6xxx_chip *chip = ds->priv;
1260 int serdes_count = 0;
1261 int count = 0;
1262
1263 if (sset != ETH_SS_STATS)
1264 return 0;
1265
1266 mv88e6xxx_reg_lock(chip);
1267 if (chip->info->ops->stats_get_sset_count)
1268 count = chip->info->ops->stats_get_sset_count(chip);
1269 if (count < 0)
1270 goto out;
1271
1272 if (chip->info->ops->serdes_get_sset_count)
1273 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1274 port);
1275 if (serdes_count < 0) {
1276 count = serdes_count;
1277 goto out;
1278 }
1279 count += serdes_count;
1280 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1281
1282out:
1283 mv88e6xxx_reg_unlock(chip);
1284
1285 return count;
1286}
1287
1288static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1289 const struct mv88e6xxx_hw_stat *stat,
1290 uint64_t *data)
1291{
1292 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_PORT)))
1293 return 0;
1294
1295 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0,
1296 MV88E6XXX_G1_STATS_OP_HIST_RX);
1297 return 1;
1298}
1299
1300static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1301 const struct mv88e6xxx_hw_stat *stat,
1302 uint64_t *data)
1303{
1304 if (!(stat->type & STATS_TYPE_BANK0))
1305 return 0;
1306
1307 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0,
1308 MV88E6XXX_G1_STATS_OP_HIST_RX);
1309 return 1;
1310}
1311
1312static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1313 const struct mv88e6xxx_hw_stat *stat,
1314 uint64_t *data)
1315{
1316 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1)))
1317 return 0;
1318
1319 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1320 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1321 MV88E6XXX_G1_STATS_OP_HIST_RX);
1322 return 1;
1323}
1324
1325static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1326 const struct mv88e6xxx_hw_stat *stat,
1327 uint64_t *data)
1328{
1329 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1)))
1330 return 0;
1331
1332 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1333 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1334 0);
1335 return 1;
1336}
1337
1338static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1339 const struct mv88e6xxx_hw_stat *stat,
1340 uint64_t *data)
1341{
1342 int ret = 0;
1343
1344 if (chip->info->ops->stats_get_stat) {
1345 mv88e6xxx_reg_lock(chip);
1346 ret = chip->info->ops->stats_get_stat(chip, port, stat, data);
1347 mv88e6xxx_reg_unlock(chip);
1348 }
1349
1350 return ret;
1351}
1352
1353static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1354 uint64_t *data)
1355{
1356 const struct mv88e6xxx_hw_stat *stat;
1357 size_t i, j;
1358
1359 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1360 stat = &mv88e6xxx_hw_stats[i];
1361 j += mv88e6xxx_stats_get_stat(chip, port, stat, &data[j]);
1362 }
1363 return j;
1364}
1365
1366static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1367 uint64_t *data)
1368{
1369 *data++ = chip->ports[port].atu_member_violation;
1370 *data++ = chip->ports[port].atu_miss_violation;
1371 *data++ = chip->ports[port].atu_full_violation;
1372 *data++ = chip->ports[port].vtu_member_violation;
1373 *data++ = chip->ports[port].vtu_miss_violation;
1374}
1375
1376static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1377 uint64_t *data)
1378{
1379 size_t count;
1380
1381 count = mv88e6xxx_stats_get_stats(chip, port, data);
1382
1383 mv88e6xxx_reg_lock(chip);
1384 if (chip->info->ops->serdes_get_stats) {
1385 data += count;
1386 count = chip->info->ops->serdes_get_stats(chip, port, data);
1387 }
1388 data += count;
1389 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1390 mv88e6xxx_reg_unlock(chip);
1391}
1392
1393static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1394 uint64_t *data)
1395{
1396 struct mv88e6xxx_chip *chip = ds->priv;
1397 int ret;
1398
1399 ret = mv88e6xxx_stats_snapshot(chip, port);
1400 if (ret < 0)
1401 return;
1402
1403 mv88e6xxx_get_stats(chip, port, data);
1404}
1405
1406static void mv88e6xxx_get_eth_mac_stats(struct dsa_switch *ds, int port,
1407 struct ethtool_eth_mac_stats *mac_stats)
1408{
1409 struct mv88e6xxx_chip *chip = ds->priv;
1410 int ret;
1411
1412 ret = mv88e6xxx_stats_snapshot(chip, port);
1413 if (ret < 0)
1414 return;
1415
1416#define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member) \
1417 mv88e6xxx_stats_get_stat(chip, port, \
1418 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \
1419 &mac_stats->stats._member)
1420
1421 MV88E6XXX_ETH_MAC_STAT_MAP(out_unicast, FramesTransmittedOK);
1422 MV88E6XXX_ETH_MAC_STAT_MAP(single, SingleCollisionFrames);
1423 MV88E6XXX_ETH_MAC_STAT_MAP(multiple, MultipleCollisionFrames);
1424 MV88E6XXX_ETH_MAC_STAT_MAP(in_unicast, FramesReceivedOK);
1425 MV88E6XXX_ETH_MAC_STAT_MAP(in_fcs_error, FrameCheckSequenceErrors);
1426 MV88E6XXX_ETH_MAC_STAT_MAP(out_octets, OctetsTransmittedOK);
1427 MV88E6XXX_ETH_MAC_STAT_MAP(deferred, FramesWithDeferredXmissions);
1428 MV88E6XXX_ETH_MAC_STAT_MAP(late, LateCollisions);
1429 MV88E6XXX_ETH_MAC_STAT_MAP(in_good_octets, OctetsReceivedOK);
1430 MV88E6XXX_ETH_MAC_STAT_MAP(out_multicasts, MulticastFramesXmittedOK);
1431 MV88E6XXX_ETH_MAC_STAT_MAP(out_broadcasts, BroadcastFramesXmittedOK);
1432 MV88E6XXX_ETH_MAC_STAT_MAP(excessive, FramesWithExcessiveDeferral);
1433 MV88E6XXX_ETH_MAC_STAT_MAP(in_multicasts, MulticastFramesReceivedOK);
1434 MV88E6XXX_ETH_MAC_STAT_MAP(in_broadcasts, BroadcastFramesReceivedOK);
1435
1436#undef MV88E6XXX_ETH_MAC_STAT_MAP
1437
1438 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.MulticastFramesXmittedOK;
1439 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.BroadcastFramesXmittedOK;
1440 mac_stats->stats.FramesReceivedOK += mac_stats->stats.MulticastFramesReceivedOK;
1441 mac_stats->stats.FramesReceivedOK += mac_stats->stats.BroadcastFramesReceivedOK;
1442}
1443
1444static void mv88e6xxx_get_rmon_stats(struct dsa_switch *ds, int port,
1445 struct ethtool_rmon_stats *rmon_stats,
1446 const struct ethtool_rmon_hist_range **ranges)
1447{
1448 static const struct ethtool_rmon_hist_range rmon_ranges[] = {
1449 { 64, 64 },
1450 { 65, 127 },
1451 { 128, 255 },
1452 { 256, 511 },
1453 { 512, 1023 },
1454 { 1024, 65535 },
1455 {}
1456 };
1457 struct mv88e6xxx_chip *chip = ds->priv;
1458 int ret;
1459
1460 ret = mv88e6xxx_stats_snapshot(chip, port);
1461 if (ret < 0)
1462 return;
1463
1464#define MV88E6XXX_RMON_STAT_MAP(_id, _member) \
1465 mv88e6xxx_stats_get_stat(chip, port, \
1466 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \
1467 &rmon_stats->stats._member)
1468
1469 MV88E6XXX_RMON_STAT_MAP(in_undersize, undersize_pkts);
1470 MV88E6XXX_RMON_STAT_MAP(in_oversize, oversize_pkts);
1471 MV88E6XXX_RMON_STAT_MAP(in_fragments, fragments);
1472 MV88E6XXX_RMON_STAT_MAP(in_jabber, jabbers);
1473 MV88E6XXX_RMON_STAT_MAP(hist_64bytes, hist[0]);
1474 MV88E6XXX_RMON_STAT_MAP(hist_65_127bytes, hist[1]);
1475 MV88E6XXX_RMON_STAT_MAP(hist_128_255bytes, hist[2]);
1476 MV88E6XXX_RMON_STAT_MAP(hist_256_511bytes, hist[3]);
1477 MV88E6XXX_RMON_STAT_MAP(hist_512_1023bytes, hist[4]);
1478 MV88E6XXX_RMON_STAT_MAP(hist_1024_max_bytes, hist[5]);
1479
1480#undef MV88E6XXX_RMON_STAT_MAP
1481
1482 *ranges = rmon_ranges;
1483}
1484
1485static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1486{
1487 struct mv88e6xxx_chip *chip = ds->priv;
1488 int len;
1489
1490 len = 32 * sizeof(u16);
1491 if (chip->info->ops->serdes_get_regs_len)
1492 len += chip->info->ops->serdes_get_regs_len(chip, port);
1493
1494 return len;
1495}
1496
1497static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1498 struct ethtool_regs *regs, void *_p)
1499{
1500 struct mv88e6xxx_chip *chip = ds->priv;
1501 int err;
1502 u16 reg;
1503 u16 *p = _p;
1504 int i;
1505
1506 regs->version = chip->info->prod_num;
1507
1508 memset(p, 0xff, 32 * sizeof(u16));
1509
1510 mv88e6xxx_reg_lock(chip);
1511
1512 for (i = 0; i < 32; i++) {
1513
1514 err = mv88e6xxx_port_read(chip, port, i, ®);
1515 if (!err)
1516 p[i] = reg;
1517 }
1518
1519 if (chip->info->ops->serdes_get_regs)
1520 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1521
1522 mv88e6xxx_reg_unlock(chip);
1523}
1524
1525static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1526 struct ethtool_keee *e)
1527{
1528 /* Nothing to do on the port's MAC */
1529 return 0;
1530}
1531
1532static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1533 struct ethtool_keee *e)
1534{
1535 /* Nothing to do on the port's MAC */
1536 return 0;
1537}
1538
1539/* Mask of the local ports allowed to receive frames from a given fabric port */
1540static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1541{
1542 struct dsa_switch *ds = chip->ds;
1543 struct dsa_switch_tree *dst = ds->dst;
1544 struct dsa_port *dp, *other_dp;
1545 bool found = false;
1546 u16 pvlan;
1547
1548 /* dev is a physical switch */
1549 if (dev <= dst->last_switch) {
1550 list_for_each_entry(dp, &dst->ports, list) {
1551 if (dp->ds->index == dev && dp->index == port) {
1552 /* dp might be a DSA link or a user port, so it
1553 * might or might not have a bridge.
1554 * Use the "found" variable for both cases.
1555 */
1556 found = true;
1557 break;
1558 }
1559 }
1560 /* dev is a virtual bridge */
1561 } else {
1562 list_for_each_entry(dp, &dst->ports, list) {
1563 unsigned int bridge_num = dsa_port_bridge_num_get(dp);
1564
1565 if (!bridge_num)
1566 continue;
1567
1568 if (bridge_num + dst->last_switch != dev)
1569 continue;
1570
1571 found = true;
1572 break;
1573 }
1574 }
1575
1576 /* Prevent frames from unknown switch or virtual bridge */
1577 if (!found)
1578 return 0;
1579
1580 /* Frames from DSA links and CPU ports can egress any local port */
1581 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1582 return mv88e6xxx_port_mask(chip);
1583
1584 pvlan = 0;
1585
1586 /* Frames from standalone user ports can only egress on the
1587 * upstream port.
1588 */
1589 if (!dsa_port_bridge_dev_get(dp))
1590 return BIT(dsa_switch_upstream_port(ds));
1591
1592 /* Frames from bridged user ports can egress any local DSA
1593 * links and CPU ports, as well as any local member of their
1594 * bridge group.
1595 */
1596 dsa_switch_for_each_port(other_dp, ds)
1597 if (other_dp->type == DSA_PORT_TYPE_CPU ||
1598 other_dp->type == DSA_PORT_TYPE_DSA ||
1599 dsa_port_bridge_same(dp, other_dp))
1600 pvlan |= BIT(other_dp->index);
1601
1602 return pvlan;
1603}
1604
1605static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1606{
1607 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1608
1609 /* prevent frames from going back out of the port they came in on */
1610 output_ports &= ~BIT(port);
1611
1612 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1613}
1614
1615static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1616 u8 state)
1617{
1618 struct mv88e6xxx_chip *chip = ds->priv;
1619 int err;
1620
1621 mv88e6xxx_reg_lock(chip);
1622 err = mv88e6xxx_port_set_state(chip, port, state);
1623 mv88e6xxx_reg_unlock(chip);
1624
1625 if (err)
1626 dev_err(ds->dev, "p%d: failed to update state\n", port);
1627}
1628
1629static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1630{
1631 int err;
1632
1633 if (chip->info->ops->ieee_pri_map) {
1634 err = chip->info->ops->ieee_pri_map(chip);
1635 if (err)
1636 return err;
1637 }
1638
1639 if (chip->info->ops->ip_pri_map) {
1640 err = chip->info->ops->ip_pri_map(chip);
1641 if (err)
1642 return err;
1643 }
1644
1645 return 0;
1646}
1647
1648static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1649{
1650 struct dsa_switch *ds = chip->ds;
1651 int target, port;
1652 int err;
1653
1654 if (!chip->info->global2_addr)
1655 return 0;
1656
1657 /* Initialize the routing port to the 32 possible target devices */
1658 for (target = 0; target < 32; target++) {
1659 port = dsa_routing_port(ds, target);
1660 if (port == ds->num_ports)
1661 port = 0x1f;
1662
1663 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1664 if (err)
1665 return err;
1666 }
1667
1668 if (chip->info->ops->set_cascade_port) {
1669 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1670 err = chip->info->ops->set_cascade_port(chip, port);
1671 if (err)
1672 return err;
1673 }
1674
1675 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1676 if (err)
1677 return err;
1678
1679 return 0;
1680}
1681
1682static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1683{
1684 /* Clear all trunk masks and mapping */
1685 if (chip->info->global2_addr)
1686 return mv88e6xxx_g2_trunk_clear(chip);
1687
1688 return 0;
1689}
1690
1691static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1692{
1693 if (chip->info->ops->rmu_disable)
1694 return chip->info->ops->rmu_disable(chip);
1695
1696 return 0;
1697}
1698
1699static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1700{
1701 if (chip->info->ops->pot_clear)
1702 return chip->info->ops->pot_clear(chip);
1703
1704 return 0;
1705}
1706
1707static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1708{
1709 if (chip->info->ops->mgmt_rsvd2cpu)
1710 return chip->info->ops->mgmt_rsvd2cpu(chip);
1711
1712 return 0;
1713}
1714
1715static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1716{
1717 int err;
1718
1719 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1720 if (err)
1721 return err;
1722
1723 /* The chips that have a "learn2all" bit in Global1, ATU
1724 * Control are precisely those whose port registers have a
1725 * Message Port bit in Port Control 1 and hence implement
1726 * ->port_setup_message_port.
1727 */
1728 if (chip->info->ops->port_setup_message_port) {
1729 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1730 if (err)
1731 return err;
1732 }
1733
1734 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1735}
1736
1737static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1738{
1739 int port;
1740 int err;
1741
1742 if (!chip->info->ops->irl_init_all)
1743 return 0;
1744
1745 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1746 /* Disable ingress rate limiting by resetting all per port
1747 * ingress rate limit resources to their initial state.
1748 */
1749 err = chip->info->ops->irl_init_all(chip, port);
1750 if (err)
1751 return err;
1752 }
1753
1754 return 0;
1755}
1756
1757static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1758{
1759 if (chip->info->ops->set_switch_mac) {
1760 u8 addr[ETH_ALEN];
1761
1762 eth_random_addr(addr);
1763
1764 return chip->info->ops->set_switch_mac(chip, addr);
1765 }
1766
1767 return 0;
1768}
1769
1770static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1771{
1772 struct dsa_switch_tree *dst = chip->ds->dst;
1773 struct dsa_switch *ds;
1774 struct dsa_port *dp;
1775 u16 pvlan = 0;
1776
1777 if (!mv88e6xxx_has_pvt(chip))
1778 return 0;
1779
1780 /* Skip the local source device, which uses in-chip port VLAN */
1781 if (dev != chip->ds->index) {
1782 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1783
1784 ds = dsa_switch_find(dst->index, dev);
1785 dp = ds ? dsa_to_port(ds, port) : NULL;
1786 if (dp && dp->lag) {
1787 /* As the PVT is used to limit flooding of
1788 * FORWARD frames, which use the LAG ID as the
1789 * source port, we must translate dev/port to
1790 * the special "LAG device" in the PVT, using
1791 * the LAG ID (one-based) as the port number
1792 * (zero-based).
1793 */
1794 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1795 port = dsa_port_lag_id_get(dp) - 1;
1796 }
1797 }
1798
1799 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1800}
1801
1802static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1803{
1804 int dev, port;
1805 int err;
1806
1807 if (!mv88e6xxx_has_pvt(chip))
1808 return 0;
1809
1810 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1811 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1812 */
1813 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1814 if (err)
1815 return err;
1816
1817 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1818 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1819 err = mv88e6xxx_pvt_map(chip, dev, port);
1820 if (err)
1821 return err;
1822 }
1823 }
1824
1825 return 0;
1826}
1827
1828static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port,
1829 u16 fid)
1830{
1831 if (dsa_to_port(chip->ds, port)->lag)
1832 /* Hardware is incapable of fast-aging a LAG through a
1833 * regular ATU move operation. Until we have something
1834 * more fancy in place this is a no-op.
1835 */
1836 return -EOPNOTSUPP;
1837
1838 return mv88e6xxx_g1_atu_remove(chip, fid, port, false);
1839}
1840
1841static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1842{
1843 struct mv88e6xxx_chip *chip = ds->priv;
1844 int err;
1845
1846 mv88e6xxx_reg_lock(chip);
1847 err = mv88e6xxx_port_fast_age_fid(chip, port, 0);
1848 mv88e6xxx_reg_unlock(chip);
1849
1850 if (err)
1851 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n",
1852 port, err);
1853}
1854
1855static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1856{
1857 if (!mv88e6xxx_max_vid(chip))
1858 return 0;
1859
1860 return mv88e6xxx_g1_vtu_flush(chip);
1861}
1862
1863static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1864 struct mv88e6xxx_vtu_entry *entry)
1865{
1866 int err;
1867
1868 if (!chip->info->ops->vtu_getnext)
1869 return -EOPNOTSUPP;
1870
1871 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1872 entry->valid = false;
1873
1874 err = chip->info->ops->vtu_getnext(chip, entry);
1875
1876 if (entry->vid != vid)
1877 entry->valid = false;
1878
1879 return err;
1880}
1881
1882int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1883 int (*cb)(struct mv88e6xxx_chip *chip,
1884 const struct mv88e6xxx_vtu_entry *entry,
1885 void *priv),
1886 void *priv)
1887{
1888 struct mv88e6xxx_vtu_entry entry = {
1889 .vid = mv88e6xxx_max_vid(chip),
1890 .valid = false,
1891 };
1892 int err;
1893
1894 if (!chip->info->ops->vtu_getnext)
1895 return -EOPNOTSUPP;
1896
1897 do {
1898 err = chip->info->ops->vtu_getnext(chip, &entry);
1899 if (err)
1900 return err;
1901
1902 if (!entry.valid)
1903 break;
1904
1905 err = cb(chip, &entry, priv);
1906 if (err)
1907 return err;
1908 } while (entry.vid < mv88e6xxx_max_vid(chip));
1909
1910 return 0;
1911}
1912
1913static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1914 struct mv88e6xxx_vtu_entry *entry)
1915{
1916 if (!chip->info->ops->vtu_loadpurge)
1917 return -EOPNOTSUPP;
1918
1919 return chip->info->ops->vtu_loadpurge(chip, entry);
1920}
1921
1922static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1923{
1924 *fid = find_first_zero_bit(chip->fid_bitmap, MV88E6XXX_N_FID);
1925 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1926 return -ENOSPC;
1927
1928 /* Clear the database */
1929 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1930}
1931
1932static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1933 struct mv88e6xxx_stu_entry *entry)
1934{
1935 if (!chip->info->ops->stu_loadpurge)
1936 return -EOPNOTSUPP;
1937
1938 return chip->info->ops->stu_loadpurge(chip, entry);
1939}
1940
1941static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip)
1942{
1943 struct mv88e6xxx_stu_entry stu = {
1944 .valid = true,
1945 .sid = 0
1946 };
1947
1948 if (!mv88e6xxx_has_stu(chip))
1949 return 0;
1950
1951 /* Make sure that SID 0 is always valid. This is used by VTU
1952 * entries that do not make use of the STU, e.g. when creating
1953 * a VLAN upper on a port that is also part of a VLAN
1954 * filtering bridge.
1955 */
1956 return mv88e6xxx_stu_loadpurge(chip, &stu);
1957}
1958
1959static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid)
1960{
1961 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 };
1962 struct mv88e6xxx_mst *mst;
1963
1964 __set_bit(0, busy);
1965
1966 list_for_each_entry(mst, &chip->msts, node)
1967 __set_bit(mst->stu.sid, busy);
1968
1969 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID);
1970
1971 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0;
1972}
1973
1974static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid)
1975{
1976 struct mv88e6xxx_mst *mst, *tmp;
1977 int err;
1978
1979 if (!sid)
1980 return 0;
1981
1982 list_for_each_entry_safe(mst, tmp, &chip->msts, node) {
1983 if (mst->stu.sid != sid)
1984 continue;
1985
1986 if (!refcount_dec_and_test(&mst->refcnt))
1987 return 0;
1988
1989 mst->stu.valid = false;
1990 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1991 if (err) {
1992 refcount_set(&mst->refcnt, 1);
1993 return err;
1994 }
1995
1996 list_del(&mst->node);
1997 kfree(mst);
1998 return 0;
1999 }
2000
2001 return -ENOENT;
2002}
2003
2004static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br,
2005 u16 msti, u8 *sid)
2006{
2007 struct mv88e6xxx_mst *mst;
2008 int err, i;
2009
2010 if (!mv88e6xxx_has_stu(chip)) {
2011 err = -EOPNOTSUPP;
2012 goto err;
2013 }
2014
2015 if (!msti) {
2016 *sid = 0;
2017 return 0;
2018 }
2019
2020 list_for_each_entry(mst, &chip->msts, node) {
2021 if (mst->br == br && mst->msti == msti) {
2022 refcount_inc(&mst->refcnt);
2023 *sid = mst->stu.sid;
2024 return 0;
2025 }
2026 }
2027
2028 err = mv88e6xxx_sid_get(chip, sid);
2029 if (err)
2030 goto err;
2031
2032 mst = kzalloc(sizeof(*mst), GFP_KERNEL);
2033 if (!mst) {
2034 err = -ENOMEM;
2035 goto err;
2036 }
2037
2038 INIT_LIST_HEAD(&mst->node);
2039 refcount_set(&mst->refcnt, 1);
2040 mst->br = br;
2041 mst->msti = msti;
2042 mst->stu.valid = true;
2043 mst->stu.sid = *sid;
2044
2045 /* The bridge starts out all ports in the disabled state. But
2046 * a STU state of disabled means to go by the port-global
2047 * state. So we set all user port's initial state to blocking,
2048 * to match the bridge's behavior.
2049 */
2050 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
2051 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ?
2052 MV88E6XXX_PORT_CTL0_STATE_BLOCKING :
2053 MV88E6XXX_PORT_CTL0_STATE_DISABLED;
2054
2055 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2056 if (err)
2057 goto err_free;
2058
2059 list_add_tail(&mst->node, &chip->msts);
2060 return 0;
2061
2062err_free:
2063 kfree(mst);
2064err:
2065 return err;
2066}
2067
2068static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port,
2069 const struct switchdev_mst_state *st)
2070{
2071 struct dsa_port *dp = dsa_to_port(ds, port);
2072 struct mv88e6xxx_chip *chip = ds->priv;
2073 struct mv88e6xxx_mst *mst;
2074 u8 state;
2075 int err;
2076
2077 if (!mv88e6xxx_has_stu(chip))
2078 return -EOPNOTSUPP;
2079
2080 switch (st->state) {
2081 case BR_STATE_DISABLED:
2082 case BR_STATE_BLOCKING:
2083 case BR_STATE_LISTENING:
2084 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
2085 break;
2086 case BR_STATE_LEARNING:
2087 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
2088 break;
2089 case BR_STATE_FORWARDING:
2090 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2091 break;
2092 default:
2093 return -EINVAL;
2094 }
2095
2096 list_for_each_entry(mst, &chip->msts, node) {
2097 if (mst->br == dsa_port_bridge_dev_get(dp) &&
2098 mst->msti == st->msti) {
2099 if (mst->stu.state[port] == state)
2100 return 0;
2101
2102 mst->stu.state[port] = state;
2103 mv88e6xxx_reg_lock(chip);
2104 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2105 mv88e6xxx_reg_unlock(chip);
2106 return err;
2107 }
2108 }
2109
2110 return -ENOENT;
2111}
2112
2113static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
2114 u16 vid)
2115{
2116 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
2117 struct mv88e6xxx_chip *chip = ds->priv;
2118 struct mv88e6xxx_vtu_entry vlan;
2119 int err;
2120
2121 /* DSA and CPU ports have to be members of multiple vlans */
2122 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp))
2123 return 0;
2124
2125 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2126 if (err)
2127 return err;
2128
2129 if (!vlan.valid)
2130 return 0;
2131
2132 dsa_switch_for_each_user_port(other_dp, ds) {
2133 struct net_device *other_br;
2134
2135 if (vlan.member[other_dp->index] ==
2136 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2137 continue;
2138
2139 if (dsa_port_bridge_same(dp, other_dp))
2140 break; /* same bridge, check next VLAN */
2141
2142 other_br = dsa_port_bridge_dev_get(other_dp);
2143 if (!other_br)
2144 continue;
2145
2146 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
2147 port, vlan.vid, other_dp->index, netdev_name(other_br));
2148 return -EOPNOTSUPP;
2149 }
2150
2151 return 0;
2152}
2153
2154static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
2155{
2156 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2157 struct net_device *br = dsa_port_bridge_dev_get(dp);
2158 struct mv88e6xxx_port *p = &chip->ports[port];
2159 u16 pvid = MV88E6XXX_VID_STANDALONE;
2160 bool drop_untagged = false;
2161 int err;
2162
2163 if (br) {
2164 if (br_vlan_enabled(br)) {
2165 pvid = p->bridge_pvid.vid;
2166 drop_untagged = !p->bridge_pvid.valid;
2167 } else {
2168 pvid = MV88E6XXX_VID_BRIDGED;
2169 }
2170 }
2171
2172 err = mv88e6xxx_port_set_pvid(chip, port, pvid);
2173 if (err)
2174 return err;
2175
2176 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
2177}
2178
2179static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2180 bool vlan_filtering,
2181 struct netlink_ext_ack *extack)
2182{
2183 struct mv88e6xxx_chip *chip = ds->priv;
2184 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
2185 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
2186 int err;
2187
2188 if (!mv88e6xxx_max_vid(chip))
2189 return -EOPNOTSUPP;
2190
2191 mv88e6xxx_reg_lock(chip);
2192
2193 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
2194 if (err)
2195 goto unlock;
2196
2197 err = mv88e6xxx_port_commit_pvid(chip, port);
2198 if (err)
2199 goto unlock;
2200
2201unlock:
2202 mv88e6xxx_reg_unlock(chip);
2203
2204 return err;
2205}
2206
2207static int
2208mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2209 const struct switchdev_obj_port_vlan *vlan)
2210{
2211 struct mv88e6xxx_chip *chip = ds->priv;
2212 int err;
2213
2214 if (!mv88e6xxx_max_vid(chip))
2215 return -EOPNOTSUPP;
2216
2217 /* If the requested port doesn't belong to the same bridge as the VLAN
2218 * members, do not support it (yet) and fallback to software VLAN.
2219 */
2220 mv88e6xxx_reg_lock(chip);
2221 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
2222 mv88e6xxx_reg_unlock(chip);
2223
2224 return err;
2225}
2226
2227static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2228 const unsigned char *addr, u16 vid,
2229 u8 state)
2230{
2231 struct mv88e6xxx_atu_entry entry;
2232 struct mv88e6xxx_vtu_entry vlan;
2233 u16 fid;
2234 int err;
2235
2236 /* Ports have two private address databases: one for when the port is
2237 * standalone and one for when the port is under a bridge and the
2238 * 802.1Q mode is disabled. When the port is standalone, DSA wants its
2239 * address database to remain 100% empty, so we never load an ATU entry
2240 * into a standalone port's database. Therefore, translate the null
2241 * VLAN ID into the port's database used for VLAN-unaware bridging.
2242 */
2243 if (vid == 0) {
2244 fid = MV88E6XXX_FID_BRIDGED;
2245 } else {
2246 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2247 if (err)
2248 return err;
2249
2250 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
2251 if (!vlan.valid)
2252 return -EOPNOTSUPP;
2253
2254 fid = vlan.fid;
2255 }
2256
2257 entry.state = 0;
2258 ether_addr_copy(entry.mac, addr);
2259 eth_addr_dec(entry.mac);
2260
2261 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
2262 if (err)
2263 return err;
2264
2265 /* Initialize a fresh ATU entry if it isn't found */
2266 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
2267 memset(&entry, 0, sizeof(entry));
2268 ether_addr_copy(entry.mac, addr);
2269 }
2270
2271 /* Purge the ATU entry only if no port is using it anymore */
2272 if (!state) {
2273 entry.portvec &= ~BIT(port);
2274 if (!entry.portvec)
2275 entry.state = 0;
2276 } else {
2277 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
2278 entry.portvec = BIT(port);
2279 else
2280 entry.portvec |= BIT(port);
2281
2282 entry.state = state;
2283 }
2284
2285 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
2286}
2287
2288static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
2289 const struct mv88e6xxx_policy *policy)
2290{
2291 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
2292 enum mv88e6xxx_policy_action action = policy->action;
2293 const u8 *addr = policy->addr;
2294 u16 vid = policy->vid;
2295 u8 state;
2296 int err;
2297 int id;
2298
2299 if (!chip->info->ops->port_set_policy)
2300 return -EOPNOTSUPP;
2301
2302 switch (mapping) {
2303 case MV88E6XXX_POLICY_MAPPING_DA:
2304 case MV88E6XXX_POLICY_MAPPING_SA:
2305 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2306 state = 0; /* Dissociate the port and address */
2307 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2308 is_multicast_ether_addr(addr))
2309 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
2310 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2311 is_unicast_ether_addr(addr))
2312 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
2313 else
2314 return -EOPNOTSUPP;
2315
2316 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2317 state);
2318 if (err)
2319 return err;
2320 break;
2321 default:
2322 return -EOPNOTSUPP;
2323 }
2324
2325 /* Skip the port's policy clearing if the mapping is still in use */
2326 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2327 idr_for_each_entry(&chip->policies, policy, id)
2328 if (policy->port == port &&
2329 policy->mapping == mapping &&
2330 policy->action != action)
2331 return 0;
2332
2333 return chip->info->ops->port_set_policy(chip, port, mapping, action);
2334}
2335
2336static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
2337 struct ethtool_rx_flow_spec *fs)
2338{
2339 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
2340 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
2341 enum mv88e6xxx_policy_mapping mapping;
2342 enum mv88e6xxx_policy_action action;
2343 struct mv88e6xxx_policy *policy;
2344 u16 vid = 0;
2345 u8 *addr;
2346 int err;
2347 int id;
2348
2349 if (fs->location != RX_CLS_LOC_ANY)
2350 return -EINVAL;
2351
2352 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
2353 action = MV88E6XXX_POLICY_ACTION_DISCARD;
2354 else
2355 return -EOPNOTSUPP;
2356
2357 switch (fs->flow_type & ~FLOW_EXT) {
2358 case ETHER_FLOW:
2359 if (!is_zero_ether_addr(mac_mask->h_dest) &&
2360 is_zero_ether_addr(mac_mask->h_source)) {
2361 mapping = MV88E6XXX_POLICY_MAPPING_DA;
2362 addr = mac_entry->h_dest;
2363 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
2364 !is_zero_ether_addr(mac_mask->h_source)) {
2365 mapping = MV88E6XXX_POLICY_MAPPING_SA;
2366 addr = mac_entry->h_source;
2367 } else {
2368 /* Cannot support DA and SA mapping in the same rule */
2369 return -EOPNOTSUPP;
2370 }
2371 break;
2372 default:
2373 return -EOPNOTSUPP;
2374 }
2375
2376 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
2377 if (fs->m_ext.vlan_tci != htons(0xffff))
2378 return -EOPNOTSUPP;
2379 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
2380 }
2381
2382 idr_for_each_entry(&chip->policies, policy, id) {
2383 if (policy->port == port && policy->mapping == mapping &&
2384 policy->action == action && policy->vid == vid &&
2385 ether_addr_equal(policy->addr, addr))
2386 return -EEXIST;
2387 }
2388
2389 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
2390 if (!policy)
2391 return -ENOMEM;
2392
2393 fs->location = 0;
2394 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
2395 GFP_KERNEL);
2396 if (err) {
2397 devm_kfree(chip->dev, policy);
2398 return err;
2399 }
2400
2401 memcpy(&policy->fs, fs, sizeof(*fs));
2402 ether_addr_copy(policy->addr, addr);
2403 policy->mapping = mapping;
2404 policy->action = action;
2405 policy->port = port;
2406 policy->vid = vid;
2407
2408 err = mv88e6xxx_policy_apply(chip, port, policy);
2409 if (err) {
2410 idr_remove(&chip->policies, fs->location);
2411 devm_kfree(chip->dev, policy);
2412 return err;
2413 }
2414
2415 return 0;
2416}
2417
2418static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
2419 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
2420{
2421 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2422 struct mv88e6xxx_chip *chip = ds->priv;
2423 struct mv88e6xxx_policy *policy;
2424 int err;
2425 int id;
2426
2427 mv88e6xxx_reg_lock(chip);
2428
2429 switch (rxnfc->cmd) {
2430 case ETHTOOL_GRXCLSRLCNT:
2431 rxnfc->data = 0;
2432 rxnfc->data |= RX_CLS_LOC_SPECIAL;
2433 rxnfc->rule_cnt = 0;
2434 idr_for_each_entry(&chip->policies, policy, id)
2435 if (policy->port == port)
2436 rxnfc->rule_cnt++;
2437 err = 0;
2438 break;
2439 case ETHTOOL_GRXCLSRULE:
2440 err = -ENOENT;
2441 policy = idr_find(&chip->policies, fs->location);
2442 if (policy) {
2443 memcpy(fs, &policy->fs, sizeof(*fs));
2444 err = 0;
2445 }
2446 break;
2447 case ETHTOOL_GRXCLSRLALL:
2448 rxnfc->data = 0;
2449 rxnfc->rule_cnt = 0;
2450 idr_for_each_entry(&chip->policies, policy, id)
2451 if (policy->port == port)
2452 rule_locs[rxnfc->rule_cnt++] = id;
2453 err = 0;
2454 break;
2455 default:
2456 err = -EOPNOTSUPP;
2457 break;
2458 }
2459
2460 mv88e6xxx_reg_unlock(chip);
2461
2462 return err;
2463}
2464
2465static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
2466 struct ethtool_rxnfc *rxnfc)
2467{
2468 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2469 struct mv88e6xxx_chip *chip = ds->priv;
2470 struct mv88e6xxx_policy *policy;
2471 int err;
2472
2473 mv88e6xxx_reg_lock(chip);
2474
2475 switch (rxnfc->cmd) {
2476 case ETHTOOL_SRXCLSRLINS:
2477 err = mv88e6xxx_policy_insert(chip, port, fs);
2478 break;
2479 case ETHTOOL_SRXCLSRLDEL:
2480 err = -ENOENT;
2481 policy = idr_remove(&chip->policies, fs->location);
2482 if (policy) {
2483 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
2484 err = mv88e6xxx_policy_apply(chip, port, policy);
2485 devm_kfree(chip->dev, policy);
2486 }
2487 break;
2488 default:
2489 err = -EOPNOTSUPP;
2490 break;
2491 }
2492
2493 mv88e6xxx_reg_unlock(chip);
2494
2495 return err;
2496}
2497
2498static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
2499 u16 vid)
2500{
2501 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2502 u8 broadcast[ETH_ALEN];
2503
2504 eth_broadcast_addr(broadcast);
2505
2506 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
2507}
2508
2509static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
2510{
2511 int port;
2512 int err;
2513
2514 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2515 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2516 struct net_device *brport;
2517
2518 if (dsa_is_unused_port(chip->ds, port))
2519 continue;
2520
2521 brport = dsa_port_to_bridge_port(dp);
2522 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
2523 /* Skip bridged user ports where broadcast
2524 * flooding is disabled.
2525 */
2526 continue;
2527
2528 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2529 if (err)
2530 return err;
2531 }
2532
2533 return 0;
2534}
2535
2536struct mv88e6xxx_port_broadcast_sync_ctx {
2537 int port;
2538 bool flood;
2539};
2540
2541static int
2542mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2543 const struct mv88e6xxx_vtu_entry *vlan,
2544 void *_ctx)
2545{
2546 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2547 u8 broadcast[ETH_ALEN];
2548 u8 state;
2549
2550 if (ctx->flood)
2551 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2552 else
2553 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2554
2555 eth_broadcast_addr(broadcast);
2556
2557 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2558 vlan->vid, state);
2559}
2560
2561static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2562 bool flood)
2563{
2564 struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2565 .port = port,
2566 .flood = flood,
2567 };
2568 struct mv88e6xxx_vtu_entry vid0 = {
2569 .vid = 0,
2570 };
2571 int err;
2572
2573 /* Update the port's private database... */
2574 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2575 if (err)
2576 return err;
2577
2578 /* ...and the database for all VLANs. */
2579 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2580 &ctx);
2581}
2582
2583static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2584 u16 vid, u8 member, bool warn)
2585{
2586 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2587 struct mv88e6xxx_vtu_entry vlan;
2588 int i, err;
2589
2590 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2591 if (err)
2592 return err;
2593
2594 if (!vlan.valid) {
2595 memset(&vlan, 0, sizeof(vlan));
2596
2597 if (vid == MV88E6XXX_VID_STANDALONE)
2598 vlan.policy = true;
2599
2600 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2601 if (err)
2602 return err;
2603
2604 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2605 if (i == port)
2606 vlan.member[i] = member;
2607 else
2608 vlan.member[i] = non_member;
2609
2610 vlan.vid = vid;
2611 vlan.valid = true;
2612
2613 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2614 if (err)
2615 return err;
2616
2617 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2618 if (err)
2619 return err;
2620 } else if (vlan.member[port] != member) {
2621 vlan.member[port] = member;
2622
2623 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2624 if (err)
2625 return err;
2626 } else if (warn) {
2627 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2628 port, vid);
2629 }
2630
2631 /* Record FID used in SW FID map */
2632 bitmap_set(chip->fid_bitmap, vlan.fid, 1);
2633
2634 return 0;
2635}
2636
2637static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2638 const struct switchdev_obj_port_vlan *vlan,
2639 struct netlink_ext_ack *extack)
2640{
2641 struct mv88e6xxx_chip *chip = ds->priv;
2642 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2643 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2644 struct mv88e6xxx_port *p = &chip->ports[port];
2645 bool warn;
2646 u8 member;
2647 int err;
2648
2649 if (!vlan->vid)
2650 return 0;
2651
2652 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2653 if (err)
2654 return err;
2655
2656 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2657 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2658 else if (untagged)
2659 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2660 else
2661 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2662
2663 /* net/dsa/user.c will call dsa_port_vlan_add() for the affected port
2664 * and then the CPU port. Do not warn for duplicates for the CPU port.
2665 */
2666 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2667
2668 mv88e6xxx_reg_lock(chip);
2669
2670 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2671 if (err) {
2672 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2673 vlan->vid, untagged ? 'u' : 't');
2674 goto out;
2675 }
2676
2677 if (pvid) {
2678 p->bridge_pvid.vid = vlan->vid;
2679 p->bridge_pvid.valid = true;
2680
2681 err = mv88e6xxx_port_commit_pvid(chip, port);
2682 if (err)
2683 goto out;
2684 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) {
2685 /* The old pvid was reinstalled as a non-pvid VLAN */
2686 p->bridge_pvid.valid = false;
2687
2688 err = mv88e6xxx_port_commit_pvid(chip, port);
2689 if (err)
2690 goto out;
2691 }
2692
2693out:
2694 mv88e6xxx_reg_unlock(chip);
2695
2696 return err;
2697}
2698
2699static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2700 int port, u16 vid)
2701{
2702 struct mv88e6xxx_vtu_entry vlan;
2703 int i, err;
2704
2705 if (!vid)
2706 return 0;
2707
2708 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2709 if (err)
2710 return err;
2711
2712 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2713 * tell switchdev that this VLAN is likely handled in software.
2714 */
2715 if (!vlan.valid ||
2716 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2717 return -EOPNOTSUPP;
2718
2719 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2720
2721 /* keep the VLAN unless all ports are excluded */
2722 vlan.valid = false;
2723 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2724 if (vlan.member[i] !=
2725 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2726 vlan.valid = true;
2727 break;
2728 }
2729 }
2730
2731 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2732 if (err)
2733 return err;
2734
2735 if (!vlan.valid) {
2736 err = mv88e6xxx_mst_put(chip, vlan.sid);
2737 if (err)
2738 return err;
2739
2740 /* Record FID freed in SW FID map */
2741 bitmap_clear(chip->fid_bitmap, vlan.fid, 1);
2742 }
2743
2744 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2745}
2746
2747static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2748 const struct switchdev_obj_port_vlan *vlan)
2749{
2750 struct mv88e6xxx_chip *chip = ds->priv;
2751 struct mv88e6xxx_port *p = &chip->ports[port];
2752 int err = 0;
2753 u16 pvid;
2754
2755 if (!mv88e6xxx_max_vid(chip))
2756 return -EOPNOTSUPP;
2757
2758 /* The ATU removal procedure needs the FID to be mapped in the VTU,
2759 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA
2760 * switchdev workqueue to ensure that all FDB entries are deleted
2761 * before we remove the VLAN.
2762 */
2763 dsa_flush_workqueue();
2764
2765 mv88e6xxx_reg_lock(chip);
2766
2767 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2768 if (err)
2769 goto unlock;
2770
2771 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2772 if (err)
2773 goto unlock;
2774
2775 if (vlan->vid == pvid) {
2776 p->bridge_pvid.valid = false;
2777
2778 err = mv88e6xxx_port_commit_pvid(chip, port);
2779 if (err)
2780 goto unlock;
2781 }
2782
2783unlock:
2784 mv88e6xxx_reg_unlock(chip);
2785
2786 return err;
2787}
2788
2789static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid)
2790{
2791 struct mv88e6xxx_chip *chip = ds->priv;
2792 struct mv88e6xxx_vtu_entry vlan;
2793 int err;
2794
2795 mv88e6xxx_reg_lock(chip);
2796
2797 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2798 if (err)
2799 goto unlock;
2800
2801 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid);
2802
2803unlock:
2804 mv88e6xxx_reg_unlock(chip);
2805
2806 return err;
2807}
2808
2809static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds,
2810 struct dsa_bridge bridge,
2811 const struct switchdev_vlan_msti *msti)
2812{
2813 struct mv88e6xxx_chip *chip = ds->priv;
2814 struct mv88e6xxx_vtu_entry vlan;
2815 u8 old_sid, new_sid;
2816 int err;
2817
2818 if (!mv88e6xxx_has_stu(chip))
2819 return -EOPNOTSUPP;
2820
2821 mv88e6xxx_reg_lock(chip);
2822
2823 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan);
2824 if (err)
2825 goto unlock;
2826
2827 if (!vlan.valid) {
2828 err = -EINVAL;
2829 goto unlock;
2830 }
2831
2832 old_sid = vlan.sid;
2833
2834 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid);
2835 if (err)
2836 goto unlock;
2837
2838 if (new_sid != old_sid) {
2839 vlan.sid = new_sid;
2840
2841 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2842 if (err) {
2843 mv88e6xxx_mst_put(chip, new_sid);
2844 goto unlock;
2845 }
2846 }
2847
2848 err = mv88e6xxx_mst_put(chip, old_sid);
2849
2850unlock:
2851 mv88e6xxx_reg_unlock(chip);
2852 return err;
2853}
2854
2855static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2856 const unsigned char *addr, u16 vid,
2857 struct dsa_db db)
2858{
2859 struct mv88e6xxx_chip *chip = ds->priv;
2860 int err;
2861
2862 mv88e6xxx_reg_lock(chip);
2863 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2864 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2865 mv88e6xxx_reg_unlock(chip);
2866
2867 return err;
2868}
2869
2870static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2871 const unsigned char *addr, u16 vid,
2872 struct dsa_db db)
2873{
2874 struct mv88e6xxx_chip *chip = ds->priv;
2875 int err;
2876
2877 mv88e6xxx_reg_lock(chip);
2878 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2879 mv88e6xxx_reg_unlock(chip);
2880
2881 return err;
2882}
2883
2884static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2885 u16 fid, u16 vid, int port,
2886 dsa_fdb_dump_cb_t *cb, void *data)
2887{
2888 struct mv88e6xxx_atu_entry addr;
2889 bool is_static;
2890 int err;
2891
2892 addr.state = 0;
2893 eth_broadcast_addr(addr.mac);
2894
2895 do {
2896 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2897 if (err)
2898 return err;
2899
2900 if (!addr.state)
2901 break;
2902
2903 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2904 continue;
2905
2906 if (!is_unicast_ether_addr(addr.mac))
2907 continue;
2908
2909 is_static = (addr.state ==
2910 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2911 err = cb(addr.mac, vid, is_static, data);
2912 if (err)
2913 return err;
2914 } while (!is_broadcast_ether_addr(addr.mac));
2915
2916 return err;
2917}
2918
2919struct mv88e6xxx_port_db_dump_vlan_ctx {
2920 int port;
2921 dsa_fdb_dump_cb_t *cb;
2922 void *data;
2923};
2924
2925static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2926 const struct mv88e6xxx_vtu_entry *entry,
2927 void *_data)
2928{
2929 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2930
2931 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2932 ctx->port, ctx->cb, ctx->data);
2933}
2934
2935static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2936 dsa_fdb_dump_cb_t *cb, void *data)
2937{
2938 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2939 .port = port,
2940 .cb = cb,
2941 .data = data,
2942 };
2943 u16 fid;
2944 int err;
2945
2946 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2947 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2948 if (err)
2949 return err;
2950
2951 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2952 if (err)
2953 return err;
2954
2955 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
2956}
2957
2958static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2959 dsa_fdb_dump_cb_t *cb, void *data)
2960{
2961 struct mv88e6xxx_chip *chip = ds->priv;
2962 int err;
2963
2964 mv88e6xxx_reg_lock(chip);
2965 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2966 mv88e6xxx_reg_unlock(chip);
2967
2968 return err;
2969}
2970
2971static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2972 struct dsa_bridge bridge)
2973{
2974 struct dsa_switch *ds = chip->ds;
2975 struct dsa_switch_tree *dst = ds->dst;
2976 struct dsa_port *dp;
2977 int err;
2978
2979 list_for_each_entry(dp, &dst->ports, list) {
2980 if (dsa_port_offloads_bridge(dp, &bridge)) {
2981 if (dp->ds == ds) {
2982 /* This is a local bridge group member,
2983 * remap its Port VLAN Map.
2984 */
2985 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2986 if (err)
2987 return err;
2988 } else {
2989 /* This is an external bridge group member,
2990 * remap its cross-chip Port VLAN Table entry.
2991 */
2992 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2993 dp->index);
2994 if (err)
2995 return err;
2996 }
2997 }
2998 }
2999
3000 return 0;
3001}
3002
3003/* Treat the software bridge as a virtual single-port switch behind the
3004 * CPU and map in the PVT. First dst->last_switch elements are taken by
3005 * physical switches, so start from beyond that range.
3006 */
3007static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
3008 unsigned int bridge_num)
3009{
3010 u8 dev = bridge_num + ds->dst->last_switch;
3011 struct mv88e6xxx_chip *chip = ds->priv;
3012
3013 return mv88e6xxx_pvt_map(chip, dev, 0);
3014}
3015
3016static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
3017 struct dsa_bridge bridge,
3018 bool *tx_fwd_offload,
3019 struct netlink_ext_ack *extack)
3020{
3021 struct mv88e6xxx_chip *chip = ds->priv;
3022 int err;
3023
3024 mv88e6xxx_reg_lock(chip);
3025
3026 err = mv88e6xxx_bridge_map(chip, bridge);
3027 if (err)
3028 goto unlock;
3029
3030 err = mv88e6xxx_port_set_map_da(chip, port, true);
3031 if (err)
3032 goto unlock;
3033
3034 err = mv88e6xxx_port_commit_pvid(chip, port);
3035 if (err)
3036 goto unlock;
3037
3038 if (mv88e6xxx_has_pvt(chip)) {
3039 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
3040 if (err)
3041 goto unlock;
3042
3043 *tx_fwd_offload = true;
3044 }
3045
3046unlock:
3047 mv88e6xxx_reg_unlock(chip);
3048
3049 return err;
3050}
3051
3052static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
3053 struct dsa_bridge bridge)
3054{
3055 struct mv88e6xxx_chip *chip = ds->priv;
3056 int err;
3057
3058 mv88e6xxx_reg_lock(chip);
3059
3060 if (bridge.tx_fwd_offload &&
3061 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
3062 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3063
3064 if (mv88e6xxx_bridge_map(chip, bridge) ||
3065 mv88e6xxx_port_vlan_map(chip, port))
3066 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
3067
3068 err = mv88e6xxx_port_set_map_da(chip, port, false);
3069 if (err)
3070 dev_err(ds->dev,
3071 "port %d failed to restore map-DA: %pe\n",
3072 port, ERR_PTR(err));
3073
3074 err = mv88e6xxx_port_commit_pvid(chip, port);
3075 if (err)
3076 dev_err(ds->dev,
3077 "port %d failed to restore standalone pvid: %pe\n",
3078 port, ERR_PTR(err));
3079
3080 mv88e6xxx_reg_unlock(chip);
3081}
3082
3083static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
3084 int tree_index, int sw_index,
3085 int port, struct dsa_bridge bridge,
3086 struct netlink_ext_ack *extack)
3087{
3088 struct mv88e6xxx_chip *chip = ds->priv;
3089 int err;
3090
3091 if (tree_index != ds->dst->index)
3092 return 0;
3093
3094 mv88e6xxx_reg_lock(chip);
3095 err = mv88e6xxx_pvt_map(chip, sw_index, port);
3096 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
3097 mv88e6xxx_reg_unlock(chip);
3098
3099 return err;
3100}
3101
3102static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
3103 int tree_index, int sw_index,
3104 int port, struct dsa_bridge bridge)
3105{
3106 struct mv88e6xxx_chip *chip = ds->priv;
3107
3108 if (tree_index != ds->dst->index)
3109 return;
3110
3111 mv88e6xxx_reg_lock(chip);
3112 if (mv88e6xxx_pvt_map(chip, sw_index, port) ||
3113 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
3114 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3115 mv88e6xxx_reg_unlock(chip);
3116}
3117
3118static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
3119{
3120 if (chip->info->ops->reset)
3121 return chip->info->ops->reset(chip);
3122
3123 return 0;
3124}
3125
3126static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
3127{
3128 struct gpio_desc *gpiod = chip->reset;
3129 int err;
3130
3131 /* If there is a GPIO connected to the reset pin, toggle it */
3132 if (gpiod) {
3133 /* If the switch has just been reset and not yet completed
3134 * loading EEPROM, the reset may interrupt the I2C transaction
3135 * mid-byte, causing the first EEPROM read after the reset
3136 * from the wrong location resulting in the switch booting
3137 * to wrong mode and inoperable.
3138 * For this reason, switch families with EEPROM support
3139 * generally wait for EEPROM loads to complete as their pre-
3140 * and post-reset handlers.
3141 */
3142 if (chip->info->ops->hardware_reset_pre) {
3143 err = chip->info->ops->hardware_reset_pre(chip);
3144 if (err)
3145 dev_err(chip->dev, "pre-reset error: %d\n", err);
3146 }
3147
3148 gpiod_set_value_cansleep(gpiod, 1);
3149 usleep_range(10000, 20000);
3150 gpiod_set_value_cansleep(gpiod, 0);
3151 usleep_range(10000, 20000);
3152
3153 if (chip->info->ops->hardware_reset_post) {
3154 err = chip->info->ops->hardware_reset_post(chip);
3155 if (err)
3156 dev_err(chip->dev, "post-reset error: %d\n", err);
3157 }
3158 }
3159}
3160
3161static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
3162{
3163 int i, err;
3164
3165 /* Set all ports to the Disabled state */
3166 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3167 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
3168 if (err)
3169 return err;
3170 }
3171
3172 /* Wait for transmit queues to drain,
3173 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
3174 */
3175 usleep_range(2000, 4000);
3176
3177 return 0;
3178}
3179
3180static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
3181{
3182 int err;
3183
3184 err = mv88e6xxx_disable_ports(chip);
3185 if (err)
3186 return err;
3187
3188 mv88e6xxx_hardware_reset(chip);
3189
3190 return mv88e6xxx_software_reset(chip);
3191}
3192
3193static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
3194 enum mv88e6xxx_frame_mode frame,
3195 enum mv88e6xxx_egress_mode egress, u16 etype)
3196{
3197 int err;
3198
3199 if (!chip->info->ops->port_set_frame_mode)
3200 return -EOPNOTSUPP;
3201
3202 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
3203 if (err)
3204 return err;
3205
3206 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
3207 if (err)
3208 return err;
3209
3210 if (chip->info->ops->port_set_ether_type)
3211 return chip->info->ops->port_set_ether_type(chip, port, etype);
3212
3213 return 0;
3214}
3215
3216static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
3217{
3218 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
3219 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3220 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3221}
3222
3223static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
3224{
3225 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
3226 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3227 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3228}
3229
3230static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
3231{
3232 return mv88e6xxx_set_port_mode(chip, port,
3233 MV88E6XXX_FRAME_MODE_ETHERTYPE,
3234 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
3235 ETH_P_EDSA);
3236}
3237
3238static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
3239{
3240 if (dsa_is_dsa_port(chip->ds, port))
3241 return mv88e6xxx_set_port_mode_dsa(chip, port);
3242
3243 if (dsa_is_user_port(chip->ds, port))
3244 return mv88e6xxx_set_port_mode_normal(chip, port);
3245
3246 /* Setup CPU port mode depending on its supported tag format */
3247 if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
3248 return mv88e6xxx_set_port_mode_dsa(chip, port);
3249
3250 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
3251 return mv88e6xxx_set_port_mode_edsa(chip, port);
3252
3253 return -EINVAL;
3254}
3255
3256static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
3257{
3258 bool message = dsa_is_dsa_port(chip->ds, port);
3259
3260 return mv88e6xxx_port_set_message_port(chip, port, message);
3261}
3262
3263static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
3264{
3265 int err;
3266
3267 if (chip->info->ops->port_set_ucast_flood) {
3268 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
3269 if (err)
3270 return err;
3271 }
3272 if (chip->info->ops->port_set_mcast_flood) {
3273 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
3274 if (err)
3275 return err;
3276 }
3277
3278 return 0;
3279}
3280
3281static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
3282 enum mv88e6xxx_egress_direction direction,
3283 int port)
3284{
3285 int err;
3286
3287 if (!chip->info->ops->set_egress_port)
3288 return -EOPNOTSUPP;
3289
3290 err = chip->info->ops->set_egress_port(chip, direction, port);
3291 if (err)
3292 return err;
3293
3294 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
3295 chip->ingress_dest_port = port;
3296 else
3297 chip->egress_dest_port = port;
3298
3299 return 0;
3300}
3301
3302static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
3303{
3304 struct dsa_switch *ds = chip->ds;
3305 int upstream_port;
3306 int err;
3307
3308 upstream_port = dsa_upstream_port(ds, port);
3309 if (chip->info->ops->port_set_upstream_port) {
3310 err = chip->info->ops->port_set_upstream_port(chip, port,
3311 upstream_port);
3312 if (err)
3313 return err;
3314 }
3315
3316 if (port == upstream_port) {
3317 if (chip->info->ops->set_cpu_port) {
3318 err = chip->info->ops->set_cpu_port(chip,
3319 upstream_port);
3320 if (err)
3321 return err;
3322 }
3323
3324 err = mv88e6xxx_set_egress_port(chip,
3325 MV88E6XXX_EGRESS_DIR_INGRESS,
3326 upstream_port);
3327 if (err && err != -EOPNOTSUPP)
3328 return err;
3329
3330 err = mv88e6xxx_set_egress_port(chip,
3331 MV88E6XXX_EGRESS_DIR_EGRESS,
3332 upstream_port);
3333 if (err && err != -EOPNOTSUPP)
3334 return err;
3335 }
3336
3337 return 0;
3338}
3339
3340static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
3341{
3342 struct device_node *phy_handle = NULL;
3343 struct fwnode_handle *ports_fwnode;
3344 struct fwnode_handle *port_fwnode;
3345 struct dsa_switch *ds = chip->ds;
3346 struct mv88e6xxx_port *p;
3347 struct dsa_port *dp;
3348 int tx_amp;
3349 int err;
3350 u16 reg;
3351 u32 val;
3352
3353 p = &chip->ports[port];
3354 p->chip = chip;
3355 p->port = port;
3356
3357 /* Look up corresponding fwnode if any */
3358 ports_fwnode = device_get_named_child_node(chip->dev, "ethernet-ports");
3359 if (!ports_fwnode)
3360 ports_fwnode = device_get_named_child_node(chip->dev, "ports");
3361 if (ports_fwnode) {
3362 fwnode_for_each_child_node(ports_fwnode, port_fwnode) {
3363 if (fwnode_property_read_u32(port_fwnode, "reg", &val))
3364 continue;
3365 if (val == port) {
3366 p->fwnode = port_fwnode;
3367 p->fiber = fwnode_property_present(port_fwnode, "sfp");
3368 break;
3369 }
3370 }
3371 fwnode_handle_put(ports_fwnode);
3372 } else {
3373 dev_dbg(chip->dev, "no ethernet ports node defined for the device\n");
3374 }
3375
3376 if (chip->info->ops->port_setup_leds) {
3377 err = chip->info->ops->port_setup_leds(chip, port);
3378 if (err && err != -EOPNOTSUPP)
3379 return err;
3380 }
3381
3382 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
3383 SPEED_UNFORCED, DUPLEX_UNFORCED,
3384 PAUSE_ON, PHY_INTERFACE_MODE_NA);
3385 if (err)
3386 return err;
3387
3388 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
3389 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
3390 * tunneling, determine priority by looking at 802.1p and IP
3391 * priority fields (IP prio has precedence), and set STP state
3392 * to Forwarding.
3393 *
3394 * If this is the CPU link, use DSA or EDSA tagging depending
3395 * on which tagging mode was configured.
3396 *
3397 * If this is a link to another switch, use DSA tagging mode.
3398 *
3399 * If this is the upstream port for this switch, enable
3400 * forwarding of unknown unicasts and multicasts.
3401 */
3402 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
3403 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
3404 /* Forward any IPv4 IGMP or IPv6 MLD frames received
3405 * by a USER port to the CPU port to allow snooping.
3406 */
3407 if (dsa_is_user_port(ds, port))
3408 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP;
3409
3410 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
3411 if (err)
3412 return err;
3413
3414 err = mv88e6xxx_setup_port_mode(chip, port);
3415 if (err)
3416 return err;
3417
3418 err = mv88e6xxx_setup_egress_floods(chip, port);
3419 if (err)
3420 return err;
3421
3422 /* Port Control 2: don't force a good FCS, set the MTU size to
3423 * 10222 bytes, disable 802.1q tags checking, don't discard
3424 * tagged or untagged frames on this port, skip destination
3425 * address lookup on user ports, disable ARP mirroring and don't
3426 * send a copy of all transmitted/received frames on this port
3427 * to the CPU.
3428 */
3429 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port));
3430 if (err)
3431 return err;
3432
3433 err = mv88e6xxx_setup_upstream_port(chip, port);
3434 if (err)
3435 return err;
3436
3437 /* On chips that support it, set all downstream DSA ports'
3438 * VLAN policy to TRAP. In combination with loading
3439 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this
3440 * provides a better isolation barrier between standalone
3441 * ports, as the ATU is bypassed on any intermediate switches
3442 * between the incoming port and the CPU.
3443 */
3444 if (dsa_is_downstream_port(ds, port) &&
3445 chip->info->ops->port_set_policy) {
3446 err = chip->info->ops->port_set_policy(chip, port,
3447 MV88E6XXX_POLICY_MAPPING_VTU,
3448 MV88E6XXX_POLICY_ACTION_TRAP);
3449 if (err)
3450 return err;
3451 }
3452
3453 /* User ports start out in standalone mode and 802.1Q is
3454 * therefore disabled. On DSA ports, all valid VIDs are always
3455 * loaded in the VTU - therefore, enable 802.1Q in order to take
3456 * advantage of VLAN policy on chips that supports it.
3457 */
3458 err = mv88e6xxx_port_set_8021q_mode(chip, port,
3459 dsa_is_user_port(ds, port) ?
3460 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED :
3461 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE);
3462 if (err)
3463 return err;
3464
3465 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by
3466 * virtue of the fact that mv88e6xxx_atu_new() will pick it as
3467 * the first free FID. This will be used as the private PVID for
3468 * unbridged ports. Shared (DSA and CPU) ports must also be
3469 * members of this VID, in order to trap all frames assigned to
3470 * it to the CPU.
3471 */
3472 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE,
3473 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3474 false);
3475 if (err)
3476 return err;
3477
3478 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the
3479 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as
3480 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used
3481 * as the private PVID on ports under a VLAN-unaware bridge.
3482 * Shared (DSA and CPU) ports must also be members of it, to translate
3483 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of
3484 * relying on their port default FID.
3485 */
3486 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
3487 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3488 false);
3489 if (err)
3490 return err;
3491
3492 if (chip->info->ops->port_set_jumbo_size) {
3493 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
3494 if (err)
3495 return err;
3496 }
3497
3498 /* Port Association Vector: disable automatic address learning
3499 * on all user ports since they start out in standalone
3500 * mode. When joining a bridge, learning will be configured to
3501 * match the bridge port settings. Enable learning on all
3502 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
3503 * learning process.
3504 *
3505 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
3506 * and RefreshLocked. I.e. setup standard automatic learning.
3507 */
3508 if (dsa_is_user_port(ds, port))
3509 reg = 0;
3510 else
3511 reg = 1 << port;
3512
3513 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
3514 reg);
3515 if (err)
3516 return err;
3517
3518 /* Egress rate control 2: disable egress rate control. */
3519 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
3520 0x0000);
3521 if (err)
3522 return err;
3523
3524 if (chip->info->ops->port_pause_limit) {
3525 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
3526 if (err)
3527 return err;
3528 }
3529
3530 if (chip->info->ops->port_disable_learn_limit) {
3531 err = chip->info->ops->port_disable_learn_limit(chip, port);
3532 if (err)
3533 return err;
3534 }
3535
3536 if (chip->info->ops->port_disable_pri_override) {
3537 err = chip->info->ops->port_disable_pri_override(chip, port);
3538 if (err)
3539 return err;
3540 }
3541
3542 if (chip->info->ops->port_tag_remap) {
3543 err = chip->info->ops->port_tag_remap(chip, port);
3544 if (err)
3545 return err;
3546 }
3547
3548 if (chip->info->ops->port_egress_rate_limiting) {
3549 err = chip->info->ops->port_egress_rate_limiting(chip, port);
3550 if (err)
3551 return err;
3552 }
3553
3554 if (chip->info->ops->port_setup_message_port) {
3555 err = chip->info->ops->port_setup_message_port(chip, port);
3556 if (err)
3557 return err;
3558 }
3559
3560 if (chip->info->ops->serdes_set_tx_amplitude) {
3561 dp = dsa_to_port(ds, port);
3562 if (dp)
3563 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0);
3564
3565 if (phy_handle && !of_property_read_u32(phy_handle,
3566 "tx-p2p-microvolt",
3567 &tx_amp))
3568 err = chip->info->ops->serdes_set_tx_amplitude(chip,
3569 port, tx_amp);
3570 if (phy_handle) {
3571 of_node_put(phy_handle);
3572 if (err)
3573 return err;
3574 }
3575 }
3576
3577 /* Port based VLAN map: give each port the same default address
3578 * database, and allow bidirectional communication between the
3579 * CPU and DSA port(s), and the other ports.
3580 */
3581 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
3582 if (err)
3583 return err;
3584
3585 err = mv88e6xxx_port_vlan_map(chip, port);
3586 if (err)
3587 return err;
3588
3589 /* Default VLAN ID and priority: don't set a default VLAN
3590 * ID, and set the default packet priority to zero.
3591 */
3592 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
3593}
3594
3595static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
3596{
3597 struct mv88e6xxx_chip *chip = ds->priv;
3598
3599 if (chip->info->ops->port_set_jumbo_size)
3600 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3601 else if (chip->info->ops->set_max_frame_size)
3602 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3603 return ETH_DATA_LEN;
3604}
3605
3606static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
3607{
3608 struct mv88e6xxx_chip *chip = ds->priv;
3609 int ret = 0;
3610
3611 /* For families where we don't know how to alter the MTU,
3612 * just accept any value up to ETH_DATA_LEN
3613 */
3614 if (!chip->info->ops->port_set_jumbo_size &&
3615 !chip->info->ops->set_max_frame_size) {
3616 if (new_mtu > ETH_DATA_LEN)
3617 return -EINVAL;
3618
3619 return 0;
3620 }
3621
3622 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
3623 new_mtu += EDSA_HLEN;
3624
3625 mv88e6xxx_reg_lock(chip);
3626 if (chip->info->ops->port_set_jumbo_size)
3627 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
3628 else if (chip->info->ops->set_max_frame_size &&
3629 dsa_is_cpu_port(ds, port))
3630 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
3631 mv88e6xxx_reg_unlock(chip);
3632
3633 return ret;
3634}
3635
3636static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
3637 unsigned int ageing_time)
3638{
3639 struct mv88e6xxx_chip *chip = ds->priv;
3640 int err;
3641
3642 mv88e6xxx_reg_lock(chip);
3643 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
3644 mv88e6xxx_reg_unlock(chip);
3645
3646 return err;
3647}
3648
3649static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
3650{
3651 int err;
3652
3653 /* Initialize the statistics unit */
3654 if (chip->info->ops->stats_set_histogram) {
3655 err = chip->info->ops->stats_set_histogram(chip);
3656 if (err)
3657 return err;
3658 }
3659
3660 return mv88e6xxx_g1_stats_clear(chip);
3661}
3662
3663/* Check if the errata has already been applied. */
3664static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3665{
3666 int port;
3667 int err;
3668 u16 val;
3669
3670 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3671 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
3672 if (err) {
3673 dev_err(chip->dev,
3674 "Error reading hidden register: %d\n", err);
3675 return false;
3676 }
3677 if (val != 0x01c0)
3678 return false;
3679 }
3680
3681 return true;
3682}
3683
3684/* The 6390 copper ports have an errata which require poking magic
3685 * values into undocumented hidden registers and then performing a
3686 * software reset.
3687 */
3688static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3689{
3690 int port;
3691 int err;
3692
3693 if (mv88e6390_setup_errata_applied(chip))
3694 return 0;
3695
3696 /* Set the ports into blocking mode */
3697 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3698 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3699 if (err)
3700 return err;
3701 }
3702
3703 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3704 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3705 if (err)
3706 return err;
3707 }
3708
3709 return mv88e6xxx_software_reset(chip);
3710}
3711
3712/* prod_id for switch families which do not have a PHY model number */
3713static const u16 family_prod_id_table[] = {
3714 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3715 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3716 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
3717};
3718
3719static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3720{
3721 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3722 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3723 u16 prod_id;
3724 u16 val;
3725 int err;
3726
3727 if (!chip->info->ops->phy_read)
3728 return -EOPNOTSUPP;
3729
3730 mv88e6xxx_reg_lock(chip);
3731 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3732 mv88e6xxx_reg_unlock(chip);
3733
3734 /* Some internal PHYs don't have a model number. */
3735 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3736 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3737 prod_id = family_prod_id_table[chip->info->family];
3738 if (prod_id)
3739 val |= prod_id >> 4;
3740 }
3741
3742 return err ? err : val;
3743}
3744
3745static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad,
3746 int reg)
3747{
3748 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3749 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3750 u16 val;
3751 int err;
3752
3753 if (!chip->info->ops->phy_read_c45)
3754 return -ENODEV;
3755
3756 mv88e6xxx_reg_lock(chip);
3757 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val);
3758 mv88e6xxx_reg_unlock(chip);
3759
3760 return err ? err : val;
3761}
3762
3763static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3764{
3765 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3766 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3767 int err;
3768
3769 if (!chip->info->ops->phy_write)
3770 return -EOPNOTSUPP;
3771
3772 mv88e6xxx_reg_lock(chip);
3773 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3774 mv88e6xxx_reg_unlock(chip);
3775
3776 return err;
3777}
3778
3779static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad,
3780 int reg, u16 val)
3781{
3782 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3783 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3784 int err;
3785
3786 if (!chip->info->ops->phy_write_c45)
3787 return -EOPNOTSUPP;
3788
3789 mv88e6xxx_reg_lock(chip);
3790 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val);
3791 mv88e6xxx_reg_unlock(chip);
3792
3793 return err;
3794}
3795
3796static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3797 struct device_node *np,
3798 bool external)
3799{
3800 static int index;
3801 struct mv88e6xxx_mdio_bus *mdio_bus;
3802 struct mii_bus *bus;
3803 int err;
3804
3805 if (external) {
3806 mv88e6xxx_reg_lock(chip);
3807 if (chip->info->family == MV88E6XXX_FAMILY_6393)
3808 err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true);
3809 else
3810 err = mv88e6390_g2_scratch_gpio_set_smi(chip, true);
3811 mv88e6xxx_reg_unlock(chip);
3812
3813 if (err)
3814 return err;
3815 }
3816
3817 bus = mdiobus_alloc_size(sizeof(*mdio_bus));
3818 if (!bus)
3819 return -ENOMEM;
3820
3821 mdio_bus = bus->priv;
3822 mdio_bus->bus = bus;
3823 mdio_bus->chip = chip;
3824 INIT_LIST_HEAD(&mdio_bus->list);
3825 mdio_bus->external = external;
3826
3827 if (np) {
3828 bus->name = np->full_name;
3829 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3830 } else {
3831 bus->name = "mv88e6xxx SMI";
3832 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3833 }
3834
3835 bus->read = mv88e6xxx_mdio_read;
3836 bus->write = mv88e6xxx_mdio_write;
3837 bus->read_c45 = mv88e6xxx_mdio_read_c45;
3838 bus->write_c45 = mv88e6xxx_mdio_write_c45;
3839 bus->parent = chip->dev;
3840 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr +
3841 mv88e6xxx_num_ports(chip) - 1,
3842 chip->info->phy_base_addr);
3843
3844 if (!external) {
3845 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3846 if (err)
3847 goto out;
3848 }
3849
3850 err = of_mdiobus_register(bus, np);
3851 if (err) {
3852 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3853 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3854 goto out;
3855 }
3856
3857 if (external)
3858 list_add_tail(&mdio_bus->list, &chip->mdios);
3859 else
3860 list_add(&mdio_bus->list, &chip->mdios);
3861
3862 return 0;
3863
3864out:
3865 mdiobus_free(bus);
3866 return err;
3867}
3868
3869static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3870
3871{
3872 struct mv88e6xxx_mdio_bus *mdio_bus, *p;
3873 struct mii_bus *bus;
3874
3875 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) {
3876 bus = mdio_bus->bus;
3877
3878 if (!mdio_bus->external)
3879 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3880
3881 mdiobus_unregister(bus);
3882 mdiobus_free(bus);
3883 }
3884}
3885
3886static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip)
3887{
3888 struct device_node *np = chip->dev->of_node;
3889 struct device_node *child;
3890 int err;
3891
3892 /* Always register one mdio bus for the internal/default mdio
3893 * bus. This maybe represented in the device tree, but is
3894 * optional.
3895 */
3896 child = of_get_child_by_name(np, "mdio");
3897 err = mv88e6xxx_mdio_register(chip, child, false);
3898 of_node_put(child);
3899 if (err)
3900 return err;
3901
3902 /* Walk the device tree, and see if there are any other nodes
3903 * which say they are compatible with the external mdio
3904 * bus.
3905 */
3906 for_each_available_child_of_node(np, child) {
3907 if (of_device_is_compatible(
3908 child, "marvell,mv88e6xxx-mdio-external")) {
3909 err = mv88e6xxx_mdio_register(chip, child, true);
3910 if (err) {
3911 mv88e6xxx_mdios_unregister(chip);
3912 of_node_put(child);
3913 return err;
3914 }
3915 }
3916 }
3917
3918 return 0;
3919}
3920
3921static void mv88e6xxx_teardown(struct dsa_switch *ds)
3922{
3923 struct mv88e6xxx_chip *chip = ds->priv;
3924
3925 mv88e6xxx_teardown_devlink_params(ds);
3926 dsa_devlink_resources_unregister(ds);
3927 mv88e6xxx_teardown_devlink_regions_global(ds);
3928 mv88e6xxx_mdios_unregister(chip);
3929}
3930
3931static int mv88e6xxx_setup(struct dsa_switch *ds)
3932{
3933 struct mv88e6xxx_chip *chip = ds->priv;
3934 u8 cmode;
3935 int err;
3936 int i;
3937
3938 err = mv88e6xxx_mdios_register(chip);
3939 if (err)
3940 return err;
3941
3942 chip->ds = ds;
3943 ds->user_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3944
3945 /* Since virtual bridges are mapped in the PVT, the number we support
3946 * depends on the physical switch topology. We need to let DSA figure
3947 * that out and therefore we cannot set this at dsa_register_switch()
3948 * time.
3949 */
3950 if (mv88e6xxx_has_pvt(chip))
3951 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
3952 ds->dst->last_switch - 1;
3953
3954 mv88e6xxx_reg_lock(chip);
3955
3956 if (chip->info->ops->setup_errata) {
3957 err = chip->info->ops->setup_errata(chip);
3958 if (err)
3959 goto unlock;
3960 }
3961
3962 /* Cache the cmode of each port. */
3963 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3964 if (chip->info->ops->port_get_cmode) {
3965 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3966 if (err)
3967 goto unlock;
3968
3969 chip->ports[i].cmode = cmode;
3970 }
3971 }
3972
3973 err = mv88e6xxx_vtu_setup(chip);
3974 if (err)
3975 goto unlock;
3976
3977 /* Must be called after mv88e6xxx_vtu_setup (which flushes the
3978 * VTU, thereby also flushing the STU).
3979 */
3980 err = mv88e6xxx_stu_setup(chip);
3981 if (err)
3982 goto unlock;
3983
3984 /* Setup Switch Port Registers */
3985 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3986 if (dsa_is_unused_port(ds, i))
3987 continue;
3988
3989 /* Prevent the use of an invalid port. */
3990 if (mv88e6xxx_is_invalid_port(chip, i)) {
3991 dev_err(chip->dev, "port %d is invalid\n", i);
3992 err = -EINVAL;
3993 goto unlock;
3994 }
3995
3996 err = mv88e6xxx_setup_port(chip, i);
3997 if (err)
3998 goto unlock;
3999 }
4000
4001 err = mv88e6xxx_irl_setup(chip);
4002 if (err)
4003 goto unlock;
4004
4005 err = mv88e6xxx_mac_setup(chip);
4006 if (err)
4007 goto unlock;
4008
4009 err = mv88e6xxx_phy_setup(chip);
4010 if (err)
4011 goto unlock;
4012
4013 err = mv88e6xxx_pvt_setup(chip);
4014 if (err)
4015 goto unlock;
4016
4017 err = mv88e6xxx_atu_setup(chip);
4018 if (err)
4019 goto unlock;
4020
4021 err = mv88e6xxx_broadcast_setup(chip, 0);
4022 if (err)
4023 goto unlock;
4024
4025 err = mv88e6xxx_pot_setup(chip);
4026 if (err)
4027 goto unlock;
4028
4029 err = mv88e6xxx_rmu_setup(chip);
4030 if (err)
4031 goto unlock;
4032
4033 err = mv88e6xxx_rsvd2cpu_setup(chip);
4034 if (err)
4035 goto unlock;
4036
4037 err = mv88e6xxx_trunk_setup(chip);
4038 if (err)
4039 goto unlock;
4040
4041 err = mv88e6xxx_devmap_setup(chip);
4042 if (err)
4043 goto unlock;
4044
4045 err = mv88e6xxx_pri_setup(chip);
4046 if (err)
4047 goto unlock;
4048
4049 /* Setup PTP Hardware Clock and timestamping */
4050 if (chip->info->ptp_support) {
4051 err = mv88e6xxx_ptp_setup(chip);
4052 if (err)
4053 goto unlock;
4054
4055 err = mv88e6xxx_hwtstamp_setup(chip);
4056 if (err)
4057 goto unlock;
4058 }
4059
4060 err = mv88e6xxx_stats_setup(chip);
4061 if (err)
4062 goto unlock;
4063
4064unlock:
4065 mv88e6xxx_reg_unlock(chip);
4066
4067 if (err)
4068 goto out_mdios;
4069
4070 /* Have to be called without holding the register lock, since
4071 * they take the devlink lock, and we later take the locks in
4072 * the reverse order when getting/setting parameters or
4073 * resource occupancy.
4074 */
4075 err = mv88e6xxx_setup_devlink_resources(ds);
4076 if (err)
4077 goto out_mdios;
4078
4079 err = mv88e6xxx_setup_devlink_params(ds);
4080 if (err)
4081 goto out_resources;
4082
4083 err = mv88e6xxx_setup_devlink_regions_global(ds);
4084 if (err)
4085 goto out_params;
4086
4087 return 0;
4088
4089out_params:
4090 mv88e6xxx_teardown_devlink_params(ds);
4091out_resources:
4092 dsa_devlink_resources_unregister(ds);
4093out_mdios:
4094 mv88e6xxx_mdios_unregister(chip);
4095
4096 return err;
4097}
4098
4099static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
4100{
4101 struct mv88e6xxx_chip *chip = ds->priv;
4102 int err;
4103
4104 if (chip->info->ops->pcs_ops &&
4105 chip->info->ops->pcs_ops->pcs_init) {
4106 err = chip->info->ops->pcs_ops->pcs_init(chip, port);
4107 if (err)
4108 return err;
4109 }
4110
4111 return mv88e6xxx_setup_devlink_regions_port(ds, port);
4112}
4113
4114static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
4115{
4116 struct mv88e6xxx_chip *chip = ds->priv;
4117
4118 mv88e6xxx_teardown_devlink_regions_port(ds, port);
4119
4120 if (chip->info->ops->pcs_ops &&
4121 chip->info->ops->pcs_ops->pcs_teardown)
4122 chip->info->ops->pcs_ops->pcs_teardown(chip, port);
4123}
4124
4125static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
4126{
4127 struct mv88e6xxx_chip *chip = ds->priv;
4128
4129 return chip->eeprom_len;
4130}
4131
4132static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
4133 struct ethtool_eeprom *eeprom, u8 *data)
4134{
4135 struct mv88e6xxx_chip *chip = ds->priv;
4136 int err;
4137
4138 if (!chip->info->ops->get_eeprom)
4139 return -EOPNOTSUPP;
4140
4141 mv88e6xxx_reg_lock(chip);
4142 err = chip->info->ops->get_eeprom(chip, eeprom, data);
4143 mv88e6xxx_reg_unlock(chip);
4144
4145 if (err)
4146 return err;
4147
4148 eeprom->magic = 0xc3ec4951;
4149
4150 return 0;
4151}
4152
4153static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
4154 struct ethtool_eeprom *eeprom, u8 *data)
4155{
4156 struct mv88e6xxx_chip *chip = ds->priv;
4157 int err;
4158
4159 if (!chip->info->ops->set_eeprom)
4160 return -EOPNOTSUPP;
4161
4162 if (eeprom->magic != 0xc3ec4951)
4163 return -EINVAL;
4164
4165 mv88e6xxx_reg_lock(chip);
4166 err = chip->info->ops->set_eeprom(chip, eeprom, data);
4167 mv88e6xxx_reg_unlock(chip);
4168
4169 return err;
4170}
4171
4172static const struct mv88e6xxx_ops mv88e6085_ops = {
4173 /* MV88E6XXX_FAMILY_6097 */
4174 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4175 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4176 .irl_init_all = mv88e6352_g2_irl_init_all,
4177 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4178 .phy_read = mv88e6185_phy_ppu_read,
4179 .phy_write = mv88e6185_phy_ppu_write,
4180 .port_set_link = mv88e6xxx_port_set_link,
4181 .port_sync_link = mv88e6xxx_port_sync_link,
4182 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4183 .port_tag_remap = mv88e6095_port_tag_remap,
4184 .port_set_policy = mv88e6352_port_set_policy,
4185 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4186 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4187 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4188 .port_set_ether_type = mv88e6351_port_set_ether_type,
4189 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4190 .port_pause_limit = mv88e6097_port_pause_limit,
4191 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4192 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4193 .port_get_cmode = mv88e6185_port_get_cmode,
4194 .port_setup_message_port = mv88e6xxx_setup_message_port,
4195 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4196 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4197 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4198 .stats_get_strings = mv88e6095_stats_get_strings,
4199 .stats_get_stat = mv88e6095_stats_get_stat,
4200 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4201 .set_egress_port = mv88e6095_g1_set_egress_port,
4202 .watchdog_ops = &mv88e6097_watchdog_ops,
4203 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4204 .pot_clear = mv88e6xxx_g2_pot_clear,
4205 .ppu_enable = mv88e6185_g1_ppu_enable,
4206 .ppu_disable = mv88e6185_g1_ppu_disable,
4207 .reset = mv88e6185_g1_reset,
4208 .rmu_disable = mv88e6085_g1_rmu_disable,
4209 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4210 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4211 .stu_getnext = mv88e6352_g1_stu_getnext,
4212 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4213 .phylink_get_caps = mv88e6185_phylink_get_caps,
4214 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4215};
4216
4217static const struct mv88e6xxx_ops mv88e6095_ops = {
4218 /* MV88E6XXX_FAMILY_6095 */
4219 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4220 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4221 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4222 .phy_read = mv88e6185_phy_ppu_read,
4223 .phy_write = mv88e6185_phy_ppu_write,
4224 .port_set_link = mv88e6xxx_port_set_link,
4225 .port_sync_link = mv88e6185_port_sync_link,
4226 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4227 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4228 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4229 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4230 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4231 .port_get_cmode = mv88e6185_port_get_cmode,
4232 .port_setup_message_port = mv88e6xxx_setup_message_port,
4233 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4234 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4235 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4236 .stats_get_strings = mv88e6095_stats_get_strings,
4237 .stats_get_stat = mv88e6095_stats_get_stat,
4238 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4239 .ppu_enable = mv88e6185_g1_ppu_enable,
4240 .ppu_disable = mv88e6185_g1_ppu_disable,
4241 .reset = mv88e6185_g1_reset,
4242 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4243 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4244 .phylink_get_caps = mv88e6095_phylink_get_caps,
4245 .pcs_ops = &mv88e6185_pcs_ops,
4246 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4247};
4248
4249static const struct mv88e6xxx_ops mv88e6097_ops = {
4250 /* MV88E6XXX_FAMILY_6097 */
4251 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4252 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4253 .irl_init_all = mv88e6352_g2_irl_init_all,
4254 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4255 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4256 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4257 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4258 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4259 .port_set_link = mv88e6xxx_port_set_link,
4260 .port_sync_link = mv88e6185_port_sync_link,
4261 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4262 .port_tag_remap = mv88e6095_port_tag_remap,
4263 .port_set_policy = mv88e6352_port_set_policy,
4264 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4265 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4266 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4267 .port_set_ether_type = mv88e6351_port_set_ether_type,
4268 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4269 .port_pause_limit = mv88e6097_port_pause_limit,
4270 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4271 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4272 .port_get_cmode = mv88e6185_port_get_cmode,
4273 .port_setup_message_port = mv88e6xxx_setup_message_port,
4274 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4275 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4276 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4277 .stats_get_strings = mv88e6095_stats_get_strings,
4278 .stats_get_stat = mv88e6095_stats_get_stat,
4279 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4280 .set_egress_port = mv88e6095_g1_set_egress_port,
4281 .watchdog_ops = &mv88e6097_watchdog_ops,
4282 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4283 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4284 .pot_clear = mv88e6xxx_g2_pot_clear,
4285 .reset = mv88e6352_g1_reset,
4286 .rmu_disable = mv88e6085_g1_rmu_disable,
4287 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4288 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4289 .phylink_get_caps = mv88e6095_phylink_get_caps,
4290 .pcs_ops = &mv88e6185_pcs_ops,
4291 .stu_getnext = mv88e6352_g1_stu_getnext,
4292 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4293 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4294};
4295
4296static const struct mv88e6xxx_ops mv88e6123_ops = {
4297 /* MV88E6XXX_FAMILY_6165 */
4298 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4299 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4300 .irl_init_all = mv88e6352_g2_irl_init_all,
4301 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4302 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4303 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4304 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4305 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4306 .port_set_link = mv88e6xxx_port_set_link,
4307 .port_sync_link = mv88e6xxx_port_sync_link,
4308 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4309 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4310 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4311 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4312 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4313 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4314 .port_get_cmode = mv88e6185_port_get_cmode,
4315 .port_setup_message_port = mv88e6xxx_setup_message_port,
4316 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4317 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4318 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4319 .stats_get_strings = mv88e6095_stats_get_strings,
4320 .stats_get_stat = mv88e6095_stats_get_stat,
4321 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4322 .set_egress_port = mv88e6095_g1_set_egress_port,
4323 .watchdog_ops = &mv88e6097_watchdog_ops,
4324 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4325 .pot_clear = mv88e6xxx_g2_pot_clear,
4326 .reset = mv88e6352_g1_reset,
4327 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4328 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4329 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4330 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4331 .stu_getnext = mv88e6352_g1_stu_getnext,
4332 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4333 .phylink_get_caps = mv88e6185_phylink_get_caps,
4334 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4335};
4336
4337static const struct mv88e6xxx_ops mv88e6131_ops = {
4338 /* MV88E6XXX_FAMILY_6185 */
4339 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4340 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4341 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4342 .phy_read = mv88e6185_phy_ppu_read,
4343 .phy_write = mv88e6185_phy_ppu_write,
4344 .port_set_link = mv88e6xxx_port_set_link,
4345 .port_sync_link = mv88e6xxx_port_sync_link,
4346 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4347 .port_tag_remap = mv88e6095_port_tag_remap,
4348 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4349 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4350 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4351 .port_set_ether_type = mv88e6351_port_set_ether_type,
4352 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4353 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4354 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4355 .port_pause_limit = mv88e6097_port_pause_limit,
4356 .port_set_pause = mv88e6185_port_set_pause,
4357 .port_get_cmode = mv88e6185_port_get_cmode,
4358 .port_setup_message_port = mv88e6xxx_setup_message_port,
4359 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4360 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4361 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4362 .stats_get_strings = mv88e6095_stats_get_strings,
4363 .stats_get_stat = mv88e6095_stats_get_stat,
4364 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4365 .set_egress_port = mv88e6095_g1_set_egress_port,
4366 .watchdog_ops = &mv88e6097_watchdog_ops,
4367 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4368 .ppu_enable = mv88e6185_g1_ppu_enable,
4369 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4370 .ppu_disable = mv88e6185_g1_ppu_disable,
4371 .reset = mv88e6185_g1_reset,
4372 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4373 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4374 .phylink_get_caps = mv88e6185_phylink_get_caps,
4375};
4376
4377static const struct mv88e6xxx_ops mv88e6141_ops = {
4378 /* MV88E6XXX_FAMILY_6341 */
4379 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4380 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4381 .irl_init_all = mv88e6352_g2_irl_init_all,
4382 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4383 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4384 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4385 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4386 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4387 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4388 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4389 .port_set_link = mv88e6xxx_port_set_link,
4390 .port_sync_link = mv88e6xxx_port_sync_link,
4391 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4392 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4393 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4394 .port_tag_remap = mv88e6095_port_tag_remap,
4395 .port_set_policy = mv88e6352_port_set_policy,
4396 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4397 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4398 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4399 .port_set_ether_type = mv88e6351_port_set_ether_type,
4400 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4401 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4402 .port_pause_limit = mv88e6097_port_pause_limit,
4403 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4404 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4405 .port_get_cmode = mv88e6352_port_get_cmode,
4406 .port_set_cmode = mv88e6341_port_set_cmode,
4407 .port_setup_message_port = mv88e6xxx_setup_message_port,
4408 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4409 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4410 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4411 .stats_get_strings = mv88e6320_stats_get_strings,
4412 .stats_get_stat = mv88e6390_stats_get_stat,
4413 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4414 .set_egress_port = mv88e6390_g1_set_egress_port,
4415 .watchdog_ops = &mv88e6390_watchdog_ops,
4416 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4417 .pot_clear = mv88e6xxx_g2_pot_clear,
4418 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4419 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4420 .reset = mv88e6352_g1_reset,
4421 .rmu_disable = mv88e6390_g1_rmu_disable,
4422 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4423 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4424 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4425 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4426 .stu_getnext = mv88e6352_g1_stu_getnext,
4427 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4428 .serdes_get_lane = mv88e6341_serdes_get_lane,
4429 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4430 .gpio_ops = &mv88e6352_gpio_ops,
4431 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4432 .serdes_get_strings = mv88e6390_serdes_get_strings,
4433 .serdes_get_stats = mv88e6390_serdes_get_stats,
4434 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4435 .serdes_get_regs = mv88e6390_serdes_get_regs,
4436 .phylink_get_caps = mv88e6341_phylink_get_caps,
4437 .pcs_ops = &mv88e6390_pcs_ops,
4438};
4439
4440static const struct mv88e6xxx_ops mv88e6161_ops = {
4441 /* MV88E6XXX_FAMILY_6165 */
4442 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4443 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4444 .irl_init_all = mv88e6352_g2_irl_init_all,
4445 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4446 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4447 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4448 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4449 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4450 .port_set_link = mv88e6xxx_port_set_link,
4451 .port_sync_link = mv88e6xxx_port_sync_link,
4452 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4453 .port_tag_remap = mv88e6095_port_tag_remap,
4454 .port_set_policy = mv88e6352_port_set_policy,
4455 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4456 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4457 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4458 .port_set_ether_type = mv88e6351_port_set_ether_type,
4459 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4460 .port_pause_limit = mv88e6097_port_pause_limit,
4461 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4462 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4463 .port_get_cmode = mv88e6185_port_get_cmode,
4464 .port_setup_message_port = mv88e6xxx_setup_message_port,
4465 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4466 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4467 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4468 .stats_get_strings = mv88e6095_stats_get_strings,
4469 .stats_get_stat = mv88e6095_stats_get_stat,
4470 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4471 .set_egress_port = mv88e6095_g1_set_egress_port,
4472 .watchdog_ops = &mv88e6097_watchdog_ops,
4473 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4474 .pot_clear = mv88e6xxx_g2_pot_clear,
4475 .reset = mv88e6352_g1_reset,
4476 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4477 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4478 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4479 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4480 .stu_getnext = mv88e6352_g1_stu_getnext,
4481 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4482 .avb_ops = &mv88e6165_avb_ops,
4483 .ptp_ops = &mv88e6165_ptp_ops,
4484 .phylink_get_caps = mv88e6185_phylink_get_caps,
4485 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4486};
4487
4488static const struct mv88e6xxx_ops mv88e6165_ops = {
4489 /* MV88E6XXX_FAMILY_6165 */
4490 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4491 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4492 .irl_init_all = mv88e6352_g2_irl_init_all,
4493 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4494 .phy_read = mv88e6165_phy_read,
4495 .phy_write = mv88e6165_phy_write,
4496 .port_set_link = mv88e6xxx_port_set_link,
4497 .port_sync_link = mv88e6xxx_port_sync_link,
4498 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4499 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4500 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4501 .port_get_cmode = mv88e6185_port_get_cmode,
4502 .port_setup_message_port = mv88e6xxx_setup_message_port,
4503 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4504 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4505 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4506 .stats_get_strings = mv88e6095_stats_get_strings,
4507 .stats_get_stat = mv88e6095_stats_get_stat,
4508 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4509 .set_egress_port = mv88e6095_g1_set_egress_port,
4510 .watchdog_ops = &mv88e6097_watchdog_ops,
4511 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4512 .pot_clear = mv88e6xxx_g2_pot_clear,
4513 .reset = mv88e6352_g1_reset,
4514 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4515 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4516 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4517 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4518 .stu_getnext = mv88e6352_g1_stu_getnext,
4519 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4520 .avb_ops = &mv88e6165_avb_ops,
4521 .ptp_ops = &mv88e6165_ptp_ops,
4522 .phylink_get_caps = mv88e6185_phylink_get_caps,
4523};
4524
4525static const struct mv88e6xxx_ops mv88e6171_ops = {
4526 /* MV88E6XXX_FAMILY_6351 */
4527 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4528 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4529 .irl_init_all = mv88e6352_g2_irl_init_all,
4530 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4531 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4532 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4533 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4534 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4535 .port_set_link = mv88e6xxx_port_set_link,
4536 .port_sync_link = mv88e6xxx_port_sync_link,
4537 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4538 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4539 .port_tag_remap = mv88e6095_port_tag_remap,
4540 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4541 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4542 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4543 .port_set_ether_type = mv88e6351_port_set_ether_type,
4544 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4545 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4546 .port_pause_limit = mv88e6097_port_pause_limit,
4547 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4548 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4549 .port_get_cmode = mv88e6352_port_get_cmode,
4550 .port_setup_message_port = mv88e6xxx_setup_message_port,
4551 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4552 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4553 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4554 .stats_get_strings = mv88e6095_stats_get_strings,
4555 .stats_get_stat = mv88e6095_stats_get_stat,
4556 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4557 .set_egress_port = mv88e6095_g1_set_egress_port,
4558 .watchdog_ops = &mv88e6097_watchdog_ops,
4559 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4560 .pot_clear = mv88e6xxx_g2_pot_clear,
4561 .reset = mv88e6352_g1_reset,
4562 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4563 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4564 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4565 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4566 .stu_getnext = mv88e6352_g1_stu_getnext,
4567 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4568 .phylink_get_caps = mv88e6351_phylink_get_caps,
4569};
4570
4571static const struct mv88e6xxx_ops mv88e6172_ops = {
4572 /* MV88E6XXX_FAMILY_6352 */
4573 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4574 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4575 .irl_init_all = mv88e6352_g2_irl_init_all,
4576 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4577 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4578 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4579 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4580 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4581 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4582 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4583 .port_set_link = mv88e6xxx_port_set_link,
4584 .port_sync_link = mv88e6xxx_port_sync_link,
4585 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4586 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4587 .port_tag_remap = mv88e6095_port_tag_remap,
4588 .port_set_policy = mv88e6352_port_set_policy,
4589 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4590 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4591 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4592 .port_set_ether_type = mv88e6351_port_set_ether_type,
4593 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4594 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4595 .port_pause_limit = mv88e6097_port_pause_limit,
4596 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4597 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4598 .port_get_cmode = mv88e6352_port_get_cmode,
4599 .port_setup_leds = mv88e6xxx_port_setup_leds,
4600 .port_setup_message_port = mv88e6xxx_setup_message_port,
4601 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4602 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4603 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4604 .stats_get_strings = mv88e6095_stats_get_strings,
4605 .stats_get_stat = mv88e6095_stats_get_stat,
4606 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4607 .set_egress_port = mv88e6095_g1_set_egress_port,
4608 .watchdog_ops = &mv88e6097_watchdog_ops,
4609 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4610 .pot_clear = mv88e6xxx_g2_pot_clear,
4611 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4612 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4613 .reset = mv88e6352_g1_reset,
4614 .rmu_disable = mv88e6352_g1_rmu_disable,
4615 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4616 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4617 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4618 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4619 .stu_getnext = mv88e6352_g1_stu_getnext,
4620 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4621 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4622 .serdes_get_regs = mv88e6352_serdes_get_regs,
4623 .gpio_ops = &mv88e6352_gpio_ops,
4624 .phylink_get_caps = mv88e6352_phylink_get_caps,
4625 .pcs_ops = &mv88e6352_pcs_ops,
4626};
4627
4628static const struct mv88e6xxx_ops mv88e6175_ops = {
4629 /* MV88E6XXX_FAMILY_6351 */
4630 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4631 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4632 .irl_init_all = mv88e6352_g2_irl_init_all,
4633 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4634 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4635 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4636 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4637 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4638 .port_set_link = mv88e6xxx_port_set_link,
4639 .port_sync_link = mv88e6xxx_port_sync_link,
4640 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4641 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4642 .port_tag_remap = mv88e6095_port_tag_remap,
4643 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4644 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4645 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4646 .port_set_ether_type = mv88e6351_port_set_ether_type,
4647 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4648 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4649 .port_pause_limit = mv88e6097_port_pause_limit,
4650 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4651 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4652 .port_get_cmode = mv88e6352_port_get_cmode,
4653 .port_setup_message_port = mv88e6xxx_setup_message_port,
4654 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4655 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4656 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4657 .stats_get_strings = mv88e6095_stats_get_strings,
4658 .stats_get_stat = mv88e6095_stats_get_stat,
4659 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4660 .set_egress_port = mv88e6095_g1_set_egress_port,
4661 .watchdog_ops = &mv88e6097_watchdog_ops,
4662 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4663 .pot_clear = mv88e6xxx_g2_pot_clear,
4664 .reset = mv88e6352_g1_reset,
4665 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4666 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4667 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4668 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4669 .stu_getnext = mv88e6352_g1_stu_getnext,
4670 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4671 .phylink_get_caps = mv88e6351_phylink_get_caps,
4672};
4673
4674static const struct mv88e6xxx_ops mv88e6176_ops = {
4675 /* MV88E6XXX_FAMILY_6352 */
4676 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4677 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4678 .irl_init_all = mv88e6352_g2_irl_init_all,
4679 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4680 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4681 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4682 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4683 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4684 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4685 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4686 .port_set_link = mv88e6xxx_port_set_link,
4687 .port_sync_link = mv88e6xxx_port_sync_link,
4688 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4689 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4690 .port_tag_remap = mv88e6095_port_tag_remap,
4691 .port_set_policy = mv88e6352_port_set_policy,
4692 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4693 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4694 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4695 .port_set_ether_type = mv88e6351_port_set_ether_type,
4696 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4697 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4698 .port_pause_limit = mv88e6097_port_pause_limit,
4699 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4700 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4701 .port_get_cmode = mv88e6352_port_get_cmode,
4702 .port_setup_leds = mv88e6xxx_port_setup_leds,
4703 .port_setup_message_port = mv88e6xxx_setup_message_port,
4704 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4705 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4706 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4707 .stats_get_strings = mv88e6095_stats_get_strings,
4708 .stats_get_stat = mv88e6095_stats_get_stat,
4709 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4710 .set_egress_port = mv88e6095_g1_set_egress_port,
4711 .watchdog_ops = &mv88e6097_watchdog_ops,
4712 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4713 .pot_clear = mv88e6xxx_g2_pot_clear,
4714 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4715 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4716 .reset = mv88e6352_g1_reset,
4717 .rmu_disable = mv88e6352_g1_rmu_disable,
4718 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4719 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4720 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4721 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4722 .stu_getnext = mv88e6352_g1_stu_getnext,
4723 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4724 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4725 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4726 .serdes_get_regs = mv88e6352_serdes_get_regs,
4727 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4728 .gpio_ops = &mv88e6352_gpio_ops,
4729 .phylink_get_caps = mv88e6352_phylink_get_caps,
4730 .pcs_ops = &mv88e6352_pcs_ops,
4731};
4732
4733static const struct mv88e6xxx_ops mv88e6185_ops = {
4734 /* MV88E6XXX_FAMILY_6185 */
4735 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4736 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4737 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4738 .phy_read = mv88e6185_phy_ppu_read,
4739 .phy_write = mv88e6185_phy_ppu_write,
4740 .port_set_link = mv88e6xxx_port_set_link,
4741 .port_sync_link = mv88e6185_port_sync_link,
4742 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4743 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4744 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4745 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4746 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4747 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4748 .port_set_pause = mv88e6185_port_set_pause,
4749 .port_get_cmode = mv88e6185_port_get_cmode,
4750 .port_setup_message_port = mv88e6xxx_setup_message_port,
4751 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4752 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4753 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4754 .stats_get_strings = mv88e6095_stats_get_strings,
4755 .stats_get_stat = mv88e6095_stats_get_stat,
4756 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4757 .set_egress_port = mv88e6095_g1_set_egress_port,
4758 .watchdog_ops = &mv88e6097_watchdog_ops,
4759 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4760 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4761 .ppu_enable = mv88e6185_g1_ppu_enable,
4762 .ppu_disable = mv88e6185_g1_ppu_disable,
4763 .reset = mv88e6185_g1_reset,
4764 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4765 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4766 .phylink_get_caps = mv88e6185_phylink_get_caps,
4767 .pcs_ops = &mv88e6185_pcs_ops,
4768 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4769};
4770
4771static const struct mv88e6xxx_ops mv88e6190_ops = {
4772 /* MV88E6XXX_FAMILY_6390 */
4773 .setup_errata = mv88e6390_setup_errata,
4774 .irl_init_all = mv88e6390_g2_irl_init_all,
4775 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4776 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4777 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4778 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4779 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4780 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4781 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4782 .port_set_link = mv88e6xxx_port_set_link,
4783 .port_sync_link = mv88e6xxx_port_sync_link,
4784 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4785 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4786 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4787 .port_tag_remap = mv88e6390_port_tag_remap,
4788 .port_set_policy = mv88e6352_port_set_policy,
4789 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4790 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4791 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4792 .port_set_ether_type = mv88e6351_port_set_ether_type,
4793 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4794 .port_pause_limit = mv88e6390_port_pause_limit,
4795 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4796 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4797 .port_get_cmode = mv88e6352_port_get_cmode,
4798 .port_set_cmode = mv88e6390_port_set_cmode,
4799 .port_setup_message_port = mv88e6xxx_setup_message_port,
4800 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4801 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4802 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4803 .stats_get_strings = mv88e6320_stats_get_strings,
4804 .stats_get_stat = mv88e6390_stats_get_stat,
4805 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4806 .set_egress_port = mv88e6390_g1_set_egress_port,
4807 .watchdog_ops = &mv88e6390_watchdog_ops,
4808 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4809 .pot_clear = mv88e6xxx_g2_pot_clear,
4810 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4811 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4812 .reset = mv88e6352_g1_reset,
4813 .rmu_disable = mv88e6390_g1_rmu_disable,
4814 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4815 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4816 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4817 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4818 .stu_getnext = mv88e6390_g1_stu_getnext,
4819 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4820 .serdes_get_lane = mv88e6390_serdes_get_lane,
4821 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4822 .serdes_get_strings = mv88e6390_serdes_get_strings,
4823 .serdes_get_stats = mv88e6390_serdes_get_stats,
4824 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4825 .serdes_get_regs = mv88e6390_serdes_get_regs,
4826 .gpio_ops = &mv88e6352_gpio_ops,
4827 .phylink_get_caps = mv88e6390_phylink_get_caps,
4828 .pcs_ops = &mv88e6390_pcs_ops,
4829};
4830
4831static const struct mv88e6xxx_ops mv88e6190x_ops = {
4832 /* MV88E6XXX_FAMILY_6390 */
4833 .setup_errata = mv88e6390_setup_errata,
4834 .irl_init_all = mv88e6390_g2_irl_init_all,
4835 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4836 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4837 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4838 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4839 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4840 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4841 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4842 .port_set_link = mv88e6xxx_port_set_link,
4843 .port_sync_link = mv88e6xxx_port_sync_link,
4844 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4845 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4846 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4847 .port_tag_remap = mv88e6390_port_tag_remap,
4848 .port_set_policy = mv88e6352_port_set_policy,
4849 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4850 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4851 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4852 .port_set_ether_type = mv88e6351_port_set_ether_type,
4853 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4854 .port_pause_limit = mv88e6390_port_pause_limit,
4855 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4856 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4857 .port_get_cmode = mv88e6352_port_get_cmode,
4858 .port_set_cmode = mv88e6390x_port_set_cmode,
4859 .port_setup_message_port = mv88e6xxx_setup_message_port,
4860 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4861 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4862 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4863 .stats_get_strings = mv88e6320_stats_get_strings,
4864 .stats_get_stat = mv88e6390_stats_get_stat,
4865 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4866 .set_egress_port = mv88e6390_g1_set_egress_port,
4867 .watchdog_ops = &mv88e6390_watchdog_ops,
4868 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4869 .pot_clear = mv88e6xxx_g2_pot_clear,
4870 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4871 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4872 .reset = mv88e6352_g1_reset,
4873 .rmu_disable = mv88e6390_g1_rmu_disable,
4874 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4875 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4876 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4877 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4878 .stu_getnext = mv88e6390_g1_stu_getnext,
4879 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4880 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4881 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4882 .serdes_get_strings = mv88e6390_serdes_get_strings,
4883 .serdes_get_stats = mv88e6390_serdes_get_stats,
4884 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4885 .serdes_get_regs = mv88e6390_serdes_get_regs,
4886 .gpio_ops = &mv88e6352_gpio_ops,
4887 .phylink_get_caps = mv88e6390x_phylink_get_caps,
4888 .pcs_ops = &mv88e6390_pcs_ops,
4889};
4890
4891static const struct mv88e6xxx_ops mv88e6191_ops = {
4892 /* MV88E6XXX_FAMILY_6390 */
4893 .setup_errata = mv88e6390_setup_errata,
4894 .irl_init_all = mv88e6390_g2_irl_init_all,
4895 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4896 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4897 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4898 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4899 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4900 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4901 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4902 .port_set_link = mv88e6xxx_port_set_link,
4903 .port_sync_link = mv88e6xxx_port_sync_link,
4904 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4905 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4906 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4907 .port_tag_remap = mv88e6390_port_tag_remap,
4908 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4909 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4910 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4911 .port_set_ether_type = mv88e6351_port_set_ether_type,
4912 .port_pause_limit = mv88e6390_port_pause_limit,
4913 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4914 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4915 .port_get_cmode = mv88e6352_port_get_cmode,
4916 .port_set_cmode = mv88e6390_port_set_cmode,
4917 .port_setup_message_port = mv88e6xxx_setup_message_port,
4918 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4919 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4920 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4921 .stats_get_strings = mv88e6320_stats_get_strings,
4922 .stats_get_stat = mv88e6390_stats_get_stat,
4923 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4924 .set_egress_port = mv88e6390_g1_set_egress_port,
4925 .watchdog_ops = &mv88e6390_watchdog_ops,
4926 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4927 .pot_clear = mv88e6xxx_g2_pot_clear,
4928 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4929 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4930 .reset = mv88e6352_g1_reset,
4931 .rmu_disable = mv88e6390_g1_rmu_disable,
4932 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4933 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4934 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4935 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4936 .stu_getnext = mv88e6390_g1_stu_getnext,
4937 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4938 .serdes_get_lane = mv88e6390_serdes_get_lane,
4939 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4940 .serdes_get_strings = mv88e6390_serdes_get_strings,
4941 .serdes_get_stats = mv88e6390_serdes_get_stats,
4942 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4943 .serdes_get_regs = mv88e6390_serdes_get_regs,
4944 .avb_ops = &mv88e6390_avb_ops,
4945 .ptp_ops = &mv88e6352_ptp_ops,
4946 .phylink_get_caps = mv88e6390_phylink_get_caps,
4947 .pcs_ops = &mv88e6390_pcs_ops,
4948};
4949
4950static const struct mv88e6xxx_ops mv88e6240_ops = {
4951 /* MV88E6XXX_FAMILY_6352 */
4952 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4953 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4954 .irl_init_all = mv88e6352_g2_irl_init_all,
4955 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4956 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4957 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4958 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4959 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4960 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4961 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4962 .port_set_link = mv88e6xxx_port_set_link,
4963 .port_sync_link = mv88e6xxx_port_sync_link,
4964 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4965 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4966 .port_tag_remap = mv88e6095_port_tag_remap,
4967 .port_set_policy = mv88e6352_port_set_policy,
4968 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4969 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4970 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4971 .port_set_ether_type = mv88e6351_port_set_ether_type,
4972 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4973 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4974 .port_pause_limit = mv88e6097_port_pause_limit,
4975 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4976 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4977 .port_get_cmode = mv88e6352_port_get_cmode,
4978 .port_setup_leds = mv88e6xxx_port_setup_leds,
4979 .port_setup_message_port = mv88e6xxx_setup_message_port,
4980 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4981 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4982 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4983 .stats_get_strings = mv88e6095_stats_get_strings,
4984 .stats_get_stat = mv88e6095_stats_get_stat,
4985 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4986 .set_egress_port = mv88e6095_g1_set_egress_port,
4987 .watchdog_ops = &mv88e6097_watchdog_ops,
4988 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4989 .pot_clear = mv88e6xxx_g2_pot_clear,
4990 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4991 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4992 .reset = mv88e6352_g1_reset,
4993 .rmu_disable = mv88e6352_g1_rmu_disable,
4994 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4995 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4996 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4997 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4998 .stu_getnext = mv88e6352_g1_stu_getnext,
4999 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5000 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5001 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5002 .serdes_get_regs = mv88e6352_serdes_get_regs,
5003 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5004 .gpio_ops = &mv88e6352_gpio_ops,
5005 .avb_ops = &mv88e6352_avb_ops,
5006 .ptp_ops = &mv88e6352_ptp_ops,
5007 .phylink_get_caps = mv88e6352_phylink_get_caps,
5008 .pcs_ops = &mv88e6352_pcs_ops,
5009};
5010
5011static const struct mv88e6xxx_ops mv88e6250_ops = {
5012 /* MV88E6XXX_FAMILY_6250 */
5013 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
5014 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5015 .irl_init_all = mv88e6352_g2_irl_init_all,
5016 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5017 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5018 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5019 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5020 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5021 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5022 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5023 .port_set_link = mv88e6xxx_port_set_link,
5024 .port_sync_link = mv88e6xxx_port_sync_link,
5025 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5026 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
5027 .port_tag_remap = mv88e6095_port_tag_remap,
5028 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5029 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5030 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5031 .port_set_ether_type = mv88e6351_port_set_ether_type,
5032 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5033 .port_pause_limit = mv88e6097_port_pause_limit,
5034 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5035 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5036 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5037 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
5038 .stats_get_strings = mv88e6250_stats_get_strings,
5039 .stats_get_stat = mv88e6250_stats_get_stat,
5040 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5041 .set_egress_port = mv88e6095_g1_set_egress_port,
5042 .watchdog_ops = &mv88e6250_watchdog_ops,
5043 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5044 .pot_clear = mv88e6xxx_g2_pot_clear,
5045 .hardware_reset_pre = mv88e6250_g1_wait_eeprom_done_prereset,
5046 .hardware_reset_post = mv88e6xxx_g1_wait_eeprom_done,
5047 .reset = mv88e6250_g1_reset,
5048 .vtu_getnext = mv88e6185_g1_vtu_getnext,
5049 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5050 .avb_ops = &mv88e6352_avb_ops,
5051 .ptp_ops = &mv88e6250_ptp_ops,
5052 .phylink_get_caps = mv88e6250_phylink_get_caps,
5053 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
5054};
5055
5056static const struct mv88e6xxx_ops mv88e6290_ops = {
5057 /* MV88E6XXX_FAMILY_6390 */
5058 .setup_errata = mv88e6390_setup_errata,
5059 .irl_init_all = mv88e6390_g2_irl_init_all,
5060 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5061 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5062 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5063 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5064 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5065 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5066 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5067 .port_set_link = mv88e6xxx_port_set_link,
5068 .port_sync_link = mv88e6xxx_port_sync_link,
5069 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5070 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5071 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5072 .port_tag_remap = mv88e6390_port_tag_remap,
5073 .port_set_policy = mv88e6352_port_set_policy,
5074 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5075 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5076 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5077 .port_set_ether_type = mv88e6351_port_set_ether_type,
5078 .port_pause_limit = mv88e6390_port_pause_limit,
5079 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5080 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5081 .port_get_cmode = mv88e6352_port_get_cmode,
5082 .port_set_cmode = mv88e6390_port_set_cmode,
5083 .port_setup_message_port = mv88e6xxx_setup_message_port,
5084 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5085 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5086 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5087 .stats_get_strings = mv88e6320_stats_get_strings,
5088 .stats_get_stat = mv88e6390_stats_get_stat,
5089 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5090 .set_egress_port = mv88e6390_g1_set_egress_port,
5091 .watchdog_ops = &mv88e6390_watchdog_ops,
5092 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5093 .pot_clear = mv88e6xxx_g2_pot_clear,
5094 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5095 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5096 .reset = mv88e6352_g1_reset,
5097 .rmu_disable = mv88e6390_g1_rmu_disable,
5098 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5099 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5100 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5101 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5102 .stu_getnext = mv88e6390_g1_stu_getnext,
5103 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5104 .serdes_get_lane = mv88e6390_serdes_get_lane,
5105 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5106 .serdes_get_strings = mv88e6390_serdes_get_strings,
5107 .serdes_get_stats = mv88e6390_serdes_get_stats,
5108 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5109 .serdes_get_regs = mv88e6390_serdes_get_regs,
5110 .gpio_ops = &mv88e6352_gpio_ops,
5111 .avb_ops = &mv88e6390_avb_ops,
5112 .ptp_ops = &mv88e6390_ptp_ops,
5113 .phylink_get_caps = mv88e6390_phylink_get_caps,
5114 .pcs_ops = &mv88e6390_pcs_ops,
5115};
5116
5117static const struct mv88e6xxx_ops mv88e6320_ops = {
5118 /* MV88E6XXX_FAMILY_6320 */
5119 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5120 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5121 .irl_init_all = mv88e6352_g2_irl_init_all,
5122 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5123 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5124 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5125 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5126 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5127 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5128 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5129 .port_set_link = mv88e6xxx_port_set_link,
5130 .port_sync_link = mv88e6xxx_port_sync_link,
5131 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5132 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5133 .port_tag_remap = mv88e6095_port_tag_remap,
5134 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5135 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5136 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5137 .port_set_ether_type = mv88e6351_port_set_ether_type,
5138 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5139 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5140 .port_pause_limit = mv88e6097_port_pause_limit,
5141 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5142 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5143 .port_get_cmode = mv88e6352_port_get_cmode,
5144 .port_setup_message_port = mv88e6xxx_setup_message_port,
5145 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5146 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5147 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5148 .stats_get_strings = mv88e6320_stats_get_strings,
5149 .stats_get_stat = mv88e6320_stats_get_stat,
5150 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5151 .set_egress_port = mv88e6095_g1_set_egress_port,
5152 .watchdog_ops = &mv88e6390_watchdog_ops,
5153 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5154 .pot_clear = mv88e6xxx_g2_pot_clear,
5155 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5156 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5157 .reset = mv88e6352_g1_reset,
5158 .vtu_getnext = mv88e6185_g1_vtu_getnext,
5159 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5160 .gpio_ops = &mv88e6352_gpio_ops,
5161 .avb_ops = &mv88e6352_avb_ops,
5162 .ptp_ops = &mv88e6352_ptp_ops,
5163 .phylink_get_caps = mv88e632x_phylink_get_caps,
5164};
5165
5166static const struct mv88e6xxx_ops mv88e6321_ops = {
5167 /* MV88E6XXX_FAMILY_6320 */
5168 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5169 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5170 .irl_init_all = mv88e6352_g2_irl_init_all,
5171 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5172 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5173 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5174 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5175 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5176 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5177 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5178 .port_set_link = mv88e6xxx_port_set_link,
5179 .port_sync_link = mv88e6xxx_port_sync_link,
5180 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5181 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5182 .port_tag_remap = mv88e6095_port_tag_remap,
5183 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5184 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5185 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5186 .port_set_ether_type = mv88e6351_port_set_ether_type,
5187 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5188 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5189 .port_pause_limit = mv88e6097_port_pause_limit,
5190 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5191 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5192 .port_get_cmode = mv88e6352_port_get_cmode,
5193 .port_setup_message_port = mv88e6xxx_setup_message_port,
5194 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5195 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5196 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5197 .stats_get_strings = mv88e6320_stats_get_strings,
5198 .stats_get_stat = mv88e6320_stats_get_stat,
5199 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5200 .set_egress_port = mv88e6095_g1_set_egress_port,
5201 .watchdog_ops = &mv88e6390_watchdog_ops,
5202 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5203 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5204 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5205 .reset = mv88e6352_g1_reset,
5206 .vtu_getnext = mv88e6185_g1_vtu_getnext,
5207 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5208 .gpio_ops = &mv88e6352_gpio_ops,
5209 .avb_ops = &mv88e6352_avb_ops,
5210 .ptp_ops = &mv88e6352_ptp_ops,
5211 .phylink_get_caps = mv88e632x_phylink_get_caps,
5212};
5213
5214static const struct mv88e6xxx_ops mv88e6341_ops = {
5215 /* MV88E6XXX_FAMILY_6341 */
5216 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5217 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5218 .irl_init_all = mv88e6352_g2_irl_init_all,
5219 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5220 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5221 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5222 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5223 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5224 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5225 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5226 .port_set_link = mv88e6xxx_port_set_link,
5227 .port_sync_link = mv88e6xxx_port_sync_link,
5228 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5229 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
5230 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
5231 .port_tag_remap = mv88e6095_port_tag_remap,
5232 .port_set_policy = mv88e6352_port_set_policy,
5233 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5234 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5235 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5236 .port_set_ether_type = mv88e6351_port_set_ether_type,
5237 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5238 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5239 .port_pause_limit = mv88e6097_port_pause_limit,
5240 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5241 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5242 .port_get_cmode = mv88e6352_port_get_cmode,
5243 .port_set_cmode = mv88e6341_port_set_cmode,
5244 .port_setup_message_port = mv88e6xxx_setup_message_port,
5245 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5246 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5247 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5248 .stats_get_strings = mv88e6320_stats_get_strings,
5249 .stats_get_stat = mv88e6390_stats_get_stat,
5250 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5251 .set_egress_port = mv88e6390_g1_set_egress_port,
5252 .watchdog_ops = &mv88e6390_watchdog_ops,
5253 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5254 .pot_clear = mv88e6xxx_g2_pot_clear,
5255 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5256 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5257 .reset = mv88e6352_g1_reset,
5258 .rmu_disable = mv88e6390_g1_rmu_disable,
5259 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5260 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5261 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5262 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5263 .stu_getnext = mv88e6352_g1_stu_getnext,
5264 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5265 .serdes_get_lane = mv88e6341_serdes_get_lane,
5266 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5267 .gpio_ops = &mv88e6352_gpio_ops,
5268 .avb_ops = &mv88e6390_avb_ops,
5269 .ptp_ops = &mv88e6352_ptp_ops,
5270 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5271 .serdes_get_strings = mv88e6390_serdes_get_strings,
5272 .serdes_get_stats = mv88e6390_serdes_get_stats,
5273 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5274 .serdes_get_regs = mv88e6390_serdes_get_regs,
5275 .phylink_get_caps = mv88e6341_phylink_get_caps,
5276 .pcs_ops = &mv88e6390_pcs_ops,
5277};
5278
5279static const struct mv88e6xxx_ops mv88e6350_ops = {
5280 /* MV88E6XXX_FAMILY_6351 */
5281 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5282 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5283 .irl_init_all = mv88e6352_g2_irl_init_all,
5284 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5285 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5286 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5287 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5288 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5289 .port_set_link = mv88e6xxx_port_set_link,
5290 .port_sync_link = mv88e6xxx_port_sync_link,
5291 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5292 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5293 .port_tag_remap = mv88e6095_port_tag_remap,
5294 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5295 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5296 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5297 .port_set_ether_type = mv88e6351_port_set_ether_type,
5298 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5299 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5300 .port_pause_limit = mv88e6097_port_pause_limit,
5301 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5302 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5303 .port_get_cmode = mv88e6352_port_get_cmode,
5304 .port_setup_message_port = mv88e6xxx_setup_message_port,
5305 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5306 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5307 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5308 .stats_get_strings = mv88e6095_stats_get_strings,
5309 .stats_get_stat = mv88e6095_stats_get_stat,
5310 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5311 .set_egress_port = mv88e6095_g1_set_egress_port,
5312 .watchdog_ops = &mv88e6097_watchdog_ops,
5313 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5314 .pot_clear = mv88e6xxx_g2_pot_clear,
5315 .reset = mv88e6352_g1_reset,
5316 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5317 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5318 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5319 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5320 .stu_getnext = mv88e6352_g1_stu_getnext,
5321 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5322 .phylink_get_caps = mv88e6351_phylink_get_caps,
5323};
5324
5325static const struct mv88e6xxx_ops mv88e6351_ops = {
5326 /* MV88E6XXX_FAMILY_6351 */
5327 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5328 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5329 .irl_init_all = mv88e6352_g2_irl_init_all,
5330 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5331 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5332 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5333 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5334 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5335 .port_set_link = mv88e6xxx_port_set_link,
5336 .port_sync_link = mv88e6xxx_port_sync_link,
5337 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5338 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5339 .port_tag_remap = mv88e6095_port_tag_remap,
5340 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5341 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5342 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5343 .port_set_ether_type = mv88e6351_port_set_ether_type,
5344 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5345 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5346 .port_pause_limit = mv88e6097_port_pause_limit,
5347 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5348 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5349 .port_get_cmode = mv88e6352_port_get_cmode,
5350 .port_setup_message_port = mv88e6xxx_setup_message_port,
5351 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5352 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5353 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5354 .stats_get_strings = mv88e6095_stats_get_strings,
5355 .stats_get_stat = mv88e6095_stats_get_stat,
5356 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5357 .set_egress_port = mv88e6095_g1_set_egress_port,
5358 .watchdog_ops = &mv88e6097_watchdog_ops,
5359 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5360 .pot_clear = mv88e6xxx_g2_pot_clear,
5361 .reset = mv88e6352_g1_reset,
5362 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5363 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5364 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5365 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5366 .stu_getnext = mv88e6352_g1_stu_getnext,
5367 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5368 .avb_ops = &mv88e6352_avb_ops,
5369 .ptp_ops = &mv88e6352_ptp_ops,
5370 .phylink_get_caps = mv88e6351_phylink_get_caps,
5371};
5372
5373static const struct mv88e6xxx_ops mv88e6352_ops = {
5374 /* MV88E6XXX_FAMILY_6352 */
5375 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5376 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5377 .irl_init_all = mv88e6352_g2_irl_init_all,
5378 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5379 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5380 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5381 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5382 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5383 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5384 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5385 .port_set_link = mv88e6xxx_port_set_link,
5386 .port_sync_link = mv88e6xxx_port_sync_link,
5387 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5388 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
5389 .port_tag_remap = mv88e6095_port_tag_remap,
5390 .port_set_policy = mv88e6352_port_set_policy,
5391 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5392 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5393 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5394 .port_set_ether_type = mv88e6351_port_set_ether_type,
5395 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5396 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5397 .port_pause_limit = mv88e6097_port_pause_limit,
5398 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5399 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5400 .port_get_cmode = mv88e6352_port_get_cmode,
5401 .port_setup_leds = mv88e6xxx_port_setup_leds,
5402 .port_setup_message_port = mv88e6xxx_setup_message_port,
5403 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5404 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5405 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5406 .stats_get_strings = mv88e6095_stats_get_strings,
5407 .stats_get_stat = mv88e6095_stats_get_stat,
5408 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5409 .set_egress_port = mv88e6095_g1_set_egress_port,
5410 .watchdog_ops = &mv88e6097_watchdog_ops,
5411 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5412 .pot_clear = mv88e6xxx_g2_pot_clear,
5413 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5414 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5415 .reset = mv88e6352_g1_reset,
5416 .rmu_disable = mv88e6352_g1_rmu_disable,
5417 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5418 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5419 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5420 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5421 .stu_getnext = mv88e6352_g1_stu_getnext,
5422 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5423 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5424 .gpio_ops = &mv88e6352_gpio_ops,
5425 .avb_ops = &mv88e6352_avb_ops,
5426 .ptp_ops = &mv88e6352_ptp_ops,
5427 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
5428 .serdes_get_strings = mv88e6352_serdes_get_strings,
5429 .serdes_get_stats = mv88e6352_serdes_get_stats,
5430 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5431 .serdes_get_regs = mv88e6352_serdes_get_regs,
5432 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5433 .phylink_get_caps = mv88e6352_phylink_get_caps,
5434 .pcs_ops = &mv88e6352_pcs_ops,
5435};
5436
5437static const struct mv88e6xxx_ops mv88e6390_ops = {
5438 /* MV88E6XXX_FAMILY_6390 */
5439 .setup_errata = mv88e6390_setup_errata,
5440 .irl_init_all = mv88e6390_g2_irl_init_all,
5441 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5442 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5443 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5444 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5445 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5446 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5447 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5448 .port_set_link = mv88e6xxx_port_set_link,
5449 .port_sync_link = mv88e6xxx_port_sync_link,
5450 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5451 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5452 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5453 .port_tag_remap = mv88e6390_port_tag_remap,
5454 .port_set_policy = mv88e6352_port_set_policy,
5455 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5456 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5457 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5458 .port_set_ether_type = mv88e6351_port_set_ether_type,
5459 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5460 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5461 .port_pause_limit = mv88e6390_port_pause_limit,
5462 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5463 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5464 .port_get_cmode = mv88e6352_port_get_cmode,
5465 .port_set_cmode = mv88e6390_port_set_cmode,
5466 .port_setup_message_port = mv88e6xxx_setup_message_port,
5467 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5468 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5469 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5470 .stats_get_strings = mv88e6320_stats_get_strings,
5471 .stats_get_stat = mv88e6390_stats_get_stat,
5472 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5473 .set_egress_port = mv88e6390_g1_set_egress_port,
5474 .watchdog_ops = &mv88e6390_watchdog_ops,
5475 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5476 .pot_clear = mv88e6xxx_g2_pot_clear,
5477 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5478 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5479 .reset = mv88e6352_g1_reset,
5480 .rmu_disable = mv88e6390_g1_rmu_disable,
5481 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5482 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5483 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5484 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5485 .stu_getnext = mv88e6390_g1_stu_getnext,
5486 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5487 .serdes_get_lane = mv88e6390_serdes_get_lane,
5488 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5489 .gpio_ops = &mv88e6352_gpio_ops,
5490 .avb_ops = &mv88e6390_avb_ops,
5491 .ptp_ops = &mv88e6390_ptp_ops,
5492 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5493 .serdes_get_strings = mv88e6390_serdes_get_strings,
5494 .serdes_get_stats = mv88e6390_serdes_get_stats,
5495 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5496 .serdes_get_regs = mv88e6390_serdes_get_regs,
5497 .phylink_get_caps = mv88e6390_phylink_get_caps,
5498 .pcs_ops = &mv88e6390_pcs_ops,
5499};
5500
5501static const struct mv88e6xxx_ops mv88e6390x_ops = {
5502 /* MV88E6XXX_FAMILY_6390 */
5503 .setup_errata = mv88e6390_setup_errata,
5504 .irl_init_all = mv88e6390_g2_irl_init_all,
5505 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5506 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5507 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5508 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5509 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5510 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5511 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5512 .port_set_link = mv88e6xxx_port_set_link,
5513 .port_sync_link = mv88e6xxx_port_sync_link,
5514 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5515 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
5516 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
5517 .port_tag_remap = mv88e6390_port_tag_remap,
5518 .port_set_policy = mv88e6352_port_set_policy,
5519 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5520 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5521 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5522 .port_set_ether_type = mv88e6351_port_set_ether_type,
5523 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5524 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5525 .port_pause_limit = mv88e6390_port_pause_limit,
5526 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5527 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5528 .port_get_cmode = mv88e6352_port_get_cmode,
5529 .port_set_cmode = mv88e6390x_port_set_cmode,
5530 .port_setup_message_port = mv88e6xxx_setup_message_port,
5531 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5532 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5533 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5534 .stats_get_strings = mv88e6320_stats_get_strings,
5535 .stats_get_stat = mv88e6390_stats_get_stat,
5536 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5537 .set_egress_port = mv88e6390_g1_set_egress_port,
5538 .watchdog_ops = &mv88e6390_watchdog_ops,
5539 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5540 .pot_clear = mv88e6xxx_g2_pot_clear,
5541 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5542 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5543 .reset = mv88e6352_g1_reset,
5544 .rmu_disable = mv88e6390_g1_rmu_disable,
5545 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5546 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5547 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5548 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5549 .stu_getnext = mv88e6390_g1_stu_getnext,
5550 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5551 .serdes_get_lane = mv88e6390x_serdes_get_lane,
5552 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5553 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5554 .serdes_get_strings = mv88e6390_serdes_get_strings,
5555 .serdes_get_stats = mv88e6390_serdes_get_stats,
5556 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5557 .serdes_get_regs = mv88e6390_serdes_get_regs,
5558 .gpio_ops = &mv88e6352_gpio_ops,
5559 .avb_ops = &mv88e6390_avb_ops,
5560 .ptp_ops = &mv88e6390_ptp_ops,
5561 .phylink_get_caps = mv88e6390x_phylink_get_caps,
5562 .pcs_ops = &mv88e6390_pcs_ops,
5563};
5564
5565static const struct mv88e6xxx_ops mv88e6393x_ops = {
5566 /* MV88E6XXX_FAMILY_6393 */
5567 .irl_init_all = mv88e6390_g2_irl_init_all,
5568 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5569 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5570 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5571 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5572 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5573 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5574 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5575 .port_set_link = mv88e6xxx_port_set_link,
5576 .port_sync_link = mv88e6xxx_port_sync_link,
5577 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5578 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
5579 .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
5580 .port_tag_remap = mv88e6390_port_tag_remap,
5581 .port_set_policy = mv88e6393x_port_set_policy,
5582 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5583 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5584 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5585 .port_set_ether_type = mv88e6393x_port_set_ether_type,
5586 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5587 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5588 .port_pause_limit = mv88e6390_port_pause_limit,
5589 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5590 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5591 .port_get_cmode = mv88e6352_port_get_cmode,
5592 .port_set_cmode = mv88e6393x_port_set_cmode,
5593 .port_setup_message_port = mv88e6xxx_setup_message_port,
5594 .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
5595 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5596 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5597 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5598 .stats_get_strings = mv88e6320_stats_get_strings,
5599 .stats_get_stat = mv88e6390_stats_get_stat,
5600 /* .set_cpu_port is missing because this family does not support a global
5601 * CPU port, only per port CPU port which is set via
5602 * .port_set_upstream_port method.
5603 */
5604 .set_egress_port = mv88e6393x_set_egress_port,
5605 .watchdog_ops = &mv88e6393x_watchdog_ops,
5606 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
5607 .pot_clear = mv88e6xxx_g2_pot_clear,
5608 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5609 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5610 .reset = mv88e6352_g1_reset,
5611 .rmu_disable = mv88e6390_g1_rmu_disable,
5612 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5613 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5614 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5615 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5616 .stu_getnext = mv88e6390_g1_stu_getnext,
5617 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5618 .serdes_get_lane = mv88e6393x_serdes_get_lane,
5619 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5620 /* TODO: serdes stats */
5621 .gpio_ops = &mv88e6352_gpio_ops,
5622 .avb_ops = &mv88e6390_avb_ops,
5623 .ptp_ops = &mv88e6352_ptp_ops,
5624 .phylink_get_caps = mv88e6393x_phylink_get_caps,
5625 .pcs_ops = &mv88e6393x_pcs_ops,
5626};
5627
5628static const struct mv88e6xxx_info mv88e6xxx_table[] = {
5629 [MV88E6020] = {
5630 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020,
5631 .family = MV88E6XXX_FAMILY_6250,
5632 .name = "Marvell 88E6020",
5633 .num_databases = 64,
5634 /* Ports 2-4 are not routed to pins
5635 * => usable ports 0, 1, 5, 6
5636 */
5637 .num_ports = 7,
5638 .num_internal_phys = 2,
5639 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5640 .max_vid = 4095,
5641 .port_base_addr = 0x8,
5642 .phy_base_addr = 0x0,
5643 .global1_addr = 0xf,
5644 .global2_addr = 0x7,
5645 .age_time_coeff = 15000,
5646 .g1_irqs = 9,
5647 .g2_irqs = 5,
5648 .atu_move_port_mask = 0xf,
5649 .dual_chip = true,
5650 .ops = &mv88e6250_ops,
5651 },
5652
5653 [MV88E6071] = {
5654 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071,
5655 .family = MV88E6XXX_FAMILY_6250,
5656 .name = "Marvell 88E6071",
5657 .num_databases = 64,
5658 .num_ports = 7,
5659 .num_internal_phys = 5,
5660 .max_vid = 4095,
5661 .port_base_addr = 0x08,
5662 .phy_base_addr = 0x00,
5663 .global1_addr = 0x0f,
5664 .global2_addr = 0x07,
5665 .age_time_coeff = 15000,
5666 .g1_irqs = 9,
5667 .g2_irqs = 5,
5668 .atu_move_port_mask = 0xf,
5669 .dual_chip = true,
5670 .ops = &mv88e6250_ops,
5671 },
5672
5673 [MV88E6085] = {
5674 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
5675 .family = MV88E6XXX_FAMILY_6097,
5676 .name = "Marvell 88E6085",
5677 .num_databases = 4096,
5678 .num_macs = 8192,
5679 .num_ports = 10,
5680 .num_internal_phys = 5,
5681 .max_vid = 4095,
5682 .max_sid = 63,
5683 .port_base_addr = 0x10,
5684 .phy_base_addr = 0x0,
5685 .global1_addr = 0x1b,
5686 .global2_addr = 0x1c,
5687 .age_time_coeff = 15000,
5688 .g1_irqs = 8,
5689 .g2_irqs = 10,
5690 .atu_move_port_mask = 0xf,
5691 .pvt = true,
5692 .multi_chip = true,
5693 .ops = &mv88e6085_ops,
5694 },
5695
5696 [MV88E6095] = {
5697 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
5698 .family = MV88E6XXX_FAMILY_6095,
5699 .name = "Marvell 88E6095/88E6095F",
5700 .num_databases = 256,
5701 .num_macs = 8192,
5702 .num_ports = 11,
5703 .num_internal_phys = 0,
5704 .max_vid = 4095,
5705 .port_base_addr = 0x10,
5706 .phy_base_addr = 0x0,
5707 .global1_addr = 0x1b,
5708 .global2_addr = 0x1c,
5709 .age_time_coeff = 15000,
5710 .g1_irqs = 8,
5711 .atu_move_port_mask = 0xf,
5712 .multi_chip = true,
5713 .ops = &mv88e6095_ops,
5714 },
5715
5716 [MV88E6097] = {
5717 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
5718 .family = MV88E6XXX_FAMILY_6097,
5719 .name = "Marvell 88E6097/88E6097F",
5720 .num_databases = 4096,
5721 .num_macs = 8192,
5722 .num_ports = 11,
5723 .num_internal_phys = 8,
5724 .max_vid = 4095,
5725 .max_sid = 63,
5726 .port_base_addr = 0x10,
5727 .phy_base_addr = 0x0,
5728 .global1_addr = 0x1b,
5729 .global2_addr = 0x1c,
5730 .age_time_coeff = 15000,
5731 .g1_irqs = 8,
5732 .g2_irqs = 10,
5733 .atu_move_port_mask = 0xf,
5734 .pvt = true,
5735 .multi_chip = true,
5736 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5737 .ops = &mv88e6097_ops,
5738 },
5739
5740 [MV88E6123] = {
5741 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
5742 .family = MV88E6XXX_FAMILY_6165,
5743 .name = "Marvell 88E6123",
5744 .num_databases = 4096,
5745 .num_macs = 1024,
5746 .num_ports = 3,
5747 .num_internal_phys = 5,
5748 .max_vid = 4095,
5749 .max_sid = 63,
5750 .port_base_addr = 0x10,
5751 .phy_base_addr = 0x0,
5752 .global1_addr = 0x1b,
5753 .global2_addr = 0x1c,
5754 .age_time_coeff = 15000,
5755 .g1_irqs = 9,
5756 .g2_irqs = 10,
5757 .atu_move_port_mask = 0xf,
5758 .pvt = true,
5759 .multi_chip = true,
5760 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5761 .ops = &mv88e6123_ops,
5762 },
5763
5764 [MV88E6131] = {
5765 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
5766 .family = MV88E6XXX_FAMILY_6185,
5767 .name = "Marvell 88E6131",
5768 .num_databases = 256,
5769 .num_macs = 8192,
5770 .num_ports = 8,
5771 .num_internal_phys = 0,
5772 .max_vid = 4095,
5773 .port_base_addr = 0x10,
5774 .phy_base_addr = 0x0,
5775 .global1_addr = 0x1b,
5776 .global2_addr = 0x1c,
5777 .age_time_coeff = 15000,
5778 .g1_irqs = 9,
5779 .atu_move_port_mask = 0xf,
5780 .multi_chip = true,
5781 .ops = &mv88e6131_ops,
5782 },
5783
5784 [MV88E6141] = {
5785 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
5786 .family = MV88E6XXX_FAMILY_6341,
5787 .name = "Marvell 88E6141",
5788 .num_databases = 256,
5789 .num_macs = 2048,
5790 .num_ports = 6,
5791 .num_internal_phys = 5,
5792 .num_gpio = 11,
5793 .max_vid = 4095,
5794 .max_sid = 63,
5795 .port_base_addr = 0x10,
5796 .phy_base_addr = 0x10,
5797 .global1_addr = 0x1b,
5798 .global2_addr = 0x1c,
5799 .age_time_coeff = 3750,
5800 .atu_move_port_mask = 0x1f,
5801 .g1_irqs = 9,
5802 .g2_irqs = 10,
5803 .pvt = true,
5804 .multi_chip = true,
5805 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5806 .ops = &mv88e6141_ops,
5807 },
5808
5809 [MV88E6161] = {
5810 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
5811 .family = MV88E6XXX_FAMILY_6165,
5812 .name = "Marvell 88E6161",
5813 .num_databases = 4096,
5814 .num_macs = 1024,
5815 .num_ports = 6,
5816 .num_internal_phys = 5,
5817 .max_vid = 4095,
5818 .max_sid = 63,
5819 .port_base_addr = 0x10,
5820 .phy_base_addr = 0x0,
5821 .global1_addr = 0x1b,
5822 .global2_addr = 0x1c,
5823 .age_time_coeff = 15000,
5824 .g1_irqs = 9,
5825 .g2_irqs = 10,
5826 .atu_move_port_mask = 0xf,
5827 .pvt = true,
5828 .multi_chip = true,
5829 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5830 .ptp_support = true,
5831 .ops = &mv88e6161_ops,
5832 },
5833
5834 [MV88E6165] = {
5835 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
5836 .family = MV88E6XXX_FAMILY_6165,
5837 .name = "Marvell 88E6165",
5838 .num_databases = 4096,
5839 .num_macs = 8192,
5840 .num_ports = 6,
5841 .num_internal_phys = 0,
5842 .max_vid = 4095,
5843 .max_sid = 63,
5844 .port_base_addr = 0x10,
5845 .phy_base_addr = 0x0,
5846 .global1_addr = 0x1b,
5847 .global2_addr = 0x1c,
5848 .age_time_coeff = 15000,
5849 .g1_irqs = 9,
5850 .g2_irqs = 10,
5851 .atu_move_port_mask = 0xf,
5852 .pvt = true,
5853 .multi_chip = true,
5854 .ptp_support = true,
5855 .ops = &mv88e6165_ops,
5856 },
5857
5858 [MV88E6171] = {
5859 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
5860 .family = MV88E6XXX_FAMILY_6351,
5861 .name = "Marvell 88E6171",
5862 .num_databases = 4096,
5863 .num_macs = 8192,
5864 .num_ports = 7,
5865 .num_internal_phys = 5,
5866 .max_vid = 4095,
5867 .max_sid = 63,
5868 .port_base_addr = 0x10,
5869 .phy_base_addr = 0x0,
5870 .global1_addr = 0x1b,
5871 .global2_addr = 0x1c,
5872 .age_time_coeff = 15000,
5873 .g1_irqs = 9,
5874 .g2_irqs = 10,
5875 .atu_move_port_mask = 0xf,
5876 .pvt = true,
5877 .multi_chip = true,
5878 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5879 .ops = &mv88e6171_ops,
5880 },
5881
5882 [MV88E6172] = {
5883 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
5884 .family = MV88E6XXX_FAMILY_6352,
5885 .name = "Marvell 88E6172",
5886 .num_databases = 4096,
5887 .num_macs = 8192,
5888 .num_ports = 7,
5889 .num_internal_phys = 5,
5890 .num_gpio = 15,
5891 .max_vid = 4095,
5892 .max_sid = 63,
5893 .port_base_addr = 0x10,
5894 .phy_base_addr = 0x0,
5895 .global1_addr = 0x1b,
5896 .global2_addr = 0x1c,
5897 .age_time_coeff = 15000,
5898 .g1_irqs = 9,
5899 .g2_irqs = 10,
5900 .atu_move_port_mask = 0xf,
5901 .pvt = true,
5902 .multi_chip = true,
5903 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5904 .ops = &mv88e6172_ops,
5905 },
5906
5907 [MV88E6175] = {
5908 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
5909 .family = MV88E6XXX_FAMILY_6351,
5910 .name = "Marvell 88E6175",
5911 .num_databases = 4096,
5912 .num_macs = 8192,
5913 .num_ports = 7,
5914 .num_internal_phys = 5,
5915 .max_vid = 4095,
5916 .max_sid = 63,
5917 .port_base_addr = 0x10,
5918 .phy_base_addr = 0x0,
5919 .global1_addr = 0x1b,
5920 .global2_addr = 0x1c,
5921 .age_time_coeff = 15000,
5922 .g1_irqs = 9,
5923 .g2_irqs = 10,
5924 .atu_move_port_mask = 0xf,
5925 .pvt = true,
5926 .multi_chip = true,
5927 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5928 .ops = &mv88e6175_ops,
5929 },
5930
5931 [MV88E6176] = {
5932 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5933 .family = MV88E6XXX_FAMILY_6352,
5934 .name = "Marvell 88E6176",
5935 .num_databases = 4096,
5936 .num_macs = 8192,
5937 .num_ports = 7,
5938 .num_internal_phys = 5,
5939 .num_gpio = 15,
5940 .max_vid = 4095,
5941 .max_sid = 63,
5942 .port_base_addr = 0x10,
5943 .phy_base_addr = 0x0,
5944 .global1_addr = 0x1b,
5945 .global2_addr = 0x1c,
5946 .age_time_coeff = 15000,
5947 .g1_irqs = 9,
5948 .g2_irqs = 10,
5949 .atu_move_port_mask = 0xf,
5950 .pvt = true,
5951 .multi_chip = true,
5952 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5953 .ops = &mv88e6176_ops,
5954 },
5955
5956 [MV88E6185] = {
5957 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
5958 .family = MV88E6XXX_FAMILY_6185,
5959 .name = "Marvell 88E6185",
5960 .num_databases = 256,
5961 .num_macs = 8192,
5962 .num_ports = 10,
5963 .num_internal_phys = 0,
5964 .max_vid = 4095,
5965 .port_base_addr = 0x10,
5966 .phy_base_addr = 0x0,
5967 .global1_addr = 0x1b,
5968 .global2_addr = 0x1c,
5969 .age_time_coeff = 15000,
5970 .g1_irqs = 8,
5971 .atu_move_port_mask = 0xf,
5972 .multi_chip = true,
5973 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5974 .ops = &mv88e6185_ops,
5975 },
5976
5977 [MV88E6190] = {
5978 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
5979 .family = MV88E6XXX_FAMILY_6390,
5980 .name = "Marvell 88E6190",
5981 .num_databases = 4096,
5982 .num_macs = 16384,
5983 .num_ports = 11, /* 10 + Z80 */
5984 .num_internal_phys = 9,
5985 .num_gpio = 16,
5986 .max_vid = 8191,
5987 .max_sid = 63,
5988 .port_base_addr = 0x0,
5989 .phy_base_addr = 0x0,
5990 .global1_addr = 0x1b,
5991 .global2_addr = 0x1c,
5992 .age_time_coeff = 3750,
5993 .g1_irqs = 9,
5994 .g2_irqs = 14,
5995 .pvt = true,
5996 .multi_chip = true,
5997 .atu_move_port_mask = 0x1f,
5998 .ops = &mv88e6190_ops,
5999 },
6000
6001 [MV88E6190X] = {
6002 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
6003 .family = MV88E6XXX_FAMILY_6390,
6004 .name = "Marvell 88E6190X",
6005 .num_databases = 4096,
6006 .num_macs = 16384,
6007 .num_ports = 11, /* 10 + Z80 */
6008 .num_internal_phys = 9,
6009 .num_gpio = 16,
6010 .max_vid = 8191,
6011 .max_sid = 63,
6012 .port_base_addr = 0x0,
6013 .phy_base_addr = 0x0,
6014 .global1_addr = 0x1b,
6015 .global2_addr = 0x1c,
6016 .age_time_coeff = 3750,
6017 .g1_irqs = 9,
6018 .g2_irqs = 14,
6019 .atu_move_port_mask = 0x1f,
6020 .pvt = true,
6021 .multi_chip = true,
6022 .ops = &mv88e6190x_ops,
6023 },
6024
6025 [MV88E6191] = {
6026 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
6027 .family = MV88E6XXX_FAMILY_6390,
6028 .name = "Marvell 88E6191",
6029 .num_databases = 4096,
6030 .num_macs = 16384,
6031 .num_ports = 11, /* 10 + Z80 */
6032 .num_internal_phys = 9,
6033 .max_vid = 8191,
6034 .max_sid = 63,
6035 .port_base_addr = 0x0,
6036 .phy_base_addr = 0x0,
6037 .global1_addr = 0x1b,
6038 .global2_addr = 0x1c,
6039 .age_time_coeff = 3750,
6040 .g1_irqs = 9,
6041 .g2_irqs = 14,
6042 .atu_move_port_mask = 0x1f,
6043 .pvt = true,
6044 .multi_chip = true,
6045 .ptp_support = true,
6046 .ops = &mv88e6191_ops,
6047 },
6048
6049 [MV88E6191X] = {
6050 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
6051 .family = MV88E6XXX_FAMILY_6393,
6052 .name = "Marvell 88E6191X",
6053 .num_databases = 4096,
6054 .num_ports = 11, /* 10 + Z80 */
6055 .num_internal_phys = 8,
6056 .internal_phys_offset = 1,
6057 .max_vid = 8191,
6058 .max_sid = 63,
6059 .port_base_addr = 0x0,
6060 .phy_base_addr = 0x0,
6061 .global1_addr = 0x1b,
6062 .global2_addr = 0x1c,
6063 .age_time_coeff = 3750,
6064 .g1_irqs = 10,
6065 .g2_irqs = 14,
6066 .atu_move_port_mask = 0x1f,
6067 .pvt = true,
6068 .multi_chip = true,
6069 .ptp_support = true,
6070 .ops = &mv88e6393x_ops,
6071 },
6072
6073 [MV88E6193X] = {
6074 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
6075 .family = MV88E6XXX_FAMILY_6393,
6076 .name = "Marvell 88E6193X",
6077 .num_databases = 4096,
6078 .num_ports = 11, /* 10 + Z80 */
6079 .num_internal_phys = 8,
6080 .internal_phys_offset = 1,
6081 .max_vid = 8191,
6082 .max_sid = 63,
6083 .port_base_addr = 0x0,
6084 .phy_base_addr = 0x0,
6085 .global1_addr = 0x1b,
6086 .global2_addr = 0x1c,
6087 .age_time_coeff = 3750,
6088 .g1_irqs = 10,
6089 .g2_irqs = 14,
6090 .atu_move_port_mask = 0x1f,
6091 .pvt = true,
6092 .multi_chip = true,
6093 .ptp_support = true,
6094 .ops = &mv88e6393x_ops,
6095 },
6096
6097 [MV88E6220] = {
6098 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
6099 .family = MV88E6XXX_FAMILY_6250,
6100 .name = "Marvell 88E6220",
6101 .num_databases = 64,
6102
6103 /* Ports 2-4 are not routed to pins
6104 * => usable ports 0, 1, 5, 6
6105 */
6106 .num_ports = 7,
6107 .num_internal_phys = 2,
6108 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
6109 .max_vid = 4095,
6110 .port_base_addr = 0x08,
6111 .phy_base_addr = 0x00,
6112 .global1_addr = 0x0f,
6113 .global2_addr = 0x07,
6114 .age_time_coeff = 15000,
6115 .g1_irqs = 9,
6116 .g2_irqs = 10,
6117 .atu_move_port_mask = 0xf,
6118 .dual_chip = true,
6119 .ptp_support = true,
6120 .ops = &mv88e6250_ops,
6121 },
6122
6123 [MV88E6240] = {
6124 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
6125 .family = MV88E6XXX_FAMILY_6352,
6126 .name = "Marvell 88E6240",
6127 .num_databases = 4096,
6128 .num_macs = 8192,
6129 .num_ports = 7,
6130 .num_internal_phys = 5,
6131 .num_gpio = 15,
6132 .max_vid = 4095,
6133 .max_sid = 63,
6134 .port_base_addr = 0x10,
6135 .phy_base_addr = 0x0,
6136 .global1_addr = 0x1b,
6137 .global2_addr = 0x1c,
6138 .age_time_coeff = 15000,
6139 .g1_irqs = 9,
6140 .g2_irqs = 10,
6141 .atu_move_port_mask = 0xf,
6142 .pvt = true,
6143 .multi_chip = true,
6144 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6145 .ptp_support = true,
6146 .ops = &mv88e6240_ops,
6147 },
6148
6149 [MV88E6250] = {
6150 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
6151 .family = MV88E6XXX_FAMILY_6250,
6152 .name = "Marvell 88E6250",
6153 .num_databases = 64,
6154 .num_ports = 7,
6155 .num_internal_phys = 5,
6156 .max_vid = 4095,
6157 .port_base_addr = 0x08,
6158 .phy_base_addr = 0x00,
6159 .global1_addr = 0x0f,
6160 .global2_addr = 0x07,
6161 .age_time_coeff = 15000,
6162 .g1_irqs = 9,
6163 .g2_irqs = 10,
6164 .atu_move_port_mask = 0xf,
6165 .dual_chip = true,
6166 .ptp_support = true,
6167 .ops = &mv88e6250_ops,
6168 },
6169
6170 [MV88E6290] = {
6171 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
6172 .family = MV88E6XXX_FAMILY_6390,
6173 .name = "Marvell 88E6290",
6174 .num_databases = 4096,
6175 .num_ports = 11, /* 10 + Z80 */
6176 .num_internal_phys = 9,
6177 .num_gpio = 16,
6178 .max_vid = 8191,
6179 .max_sid = 63,
6180 .port_base_addr = 0x0,
6181 .phy_base_addr = 0x0,
6182 .global1_addr = 0x1b,
6183 .global2_addr = 0x1c,
6184 .age_time_coeff = 3750,
6185 .g1_irqs = 9,
6186 .g2_irqs = 14,
6187 .atu_move_port_mask = 0x1f,
6188 .pvt = true,
6189 .multi_chip = true,
6190 .ptp_support = true,
6191 .ops = &mv88e6290_ops,
6192 },
6193
6194 [MV88E6320] = {
6195 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
6196 .family = MV88E6XXX_FAMILY_6320,
6197 .name = "Marvell 88E6320",
6198 .num_databases = 4096,
6199 .num_macs = 8192,
6200 .num_ports = 7,
6201 .num_internal_phys = 5,
6202 .num_gpio = 15,
6203 .max_vid = 4095,
6204 .port_base_addr = 0x10,
6205 .phy_base_addr = 0x0,
6206 .global1_addr = 0x1b,
6207 .global2_addr = 0x1c,
6208 .age_time_coeff = 15000,
6209 .g1_irqs = 8,
6210 .g2_irqs = 10,
6211 .atu_move_port_mask = 0xf,
6212 .pvt = true,
6213 .multi_chip = true,
6214 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6215 .ptp_support = true,
6216 .ops = &mv88e6320_ops,
6217 },
6218
6219 [MV88E6321] = {
6220 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
6221 .family = MV88E6XXX_FAMILY_6320,
6222 .name = "Marvell 88E6321",
6223 .num_databases = 4096,
6224 .num_macs = 8192,
6225 .num_ports = 7,
6226 .num_internal_phys = 5,
6227 .num_gpio = 15,
6228 .max_vid = 4095,
6229 .port_base_addr = 0x10,
6230 .phy_base_addr = 0x0,
6231 .global1_addr = 0x1b,
6232 .global2_addr = 0x1c,
6233 .age_time_coeff = 15000,
6234 .g1_irqs = 8,
6235 .g2_irqs = 10,
6236 .atu_move_port_mask = 0xf,
6237 .multi_chip = true,
6238 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6239 .ptp_support = true,
6240 .ops = &mv88e6321_ops,
6241 },
6242
6243 [MV88E6341] = {
6244 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
6245 .family = MV88E6XXX_FAMILY_6341,
6246 .name = "Marvell 88E6341",
6247 .num_databases = 256,
6248 .num_macs = 2048,
6249 .num_internal_phys = 5,
6250 .num_ports = 6,
6251 .num_gpio = 11,
6252 .max_vid = 4095,
6253 .max_sid = 63,
6254 .port_base_addr = 0x10,
6255 .phy_base_addr = 0x10,
6256 .global1_addr = 0x1b,
6257 .global2_addr = 0x1c,
6258 .age_time_coeff = 3750,
6259 .atu_move_port_mask = 0x1f,
6260 .g1_irqs = 9,
6261 .g2_irqs = 10,
6262 .pvt = true,
6263 .multi_chip = true,
6264 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6265 .ptp_support = true,
6266 .ops = &mv88e6341_ops,
6267 },
6268
6269 [MV88E6350] = {
6270 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
6271 .family = MV88E6XXX_FAMILY_6351,
6272 .name = "Marvell 88E6350",
6273 .num_databases = 4096,
6274 .num_macs = 8192,
6275 .num_ports = 7,
6276 .num_internal_phys = 5,
6277 .max_vid = 4095,
6278 .max_sid = 63,
6279 .port_base_addr = 0x10,
6280 .phy_base_addr = 0x0,
6281 .global1_addr = 0x1b,
6282 .global2_addr = 0x1c,
6283 .age_time_coeff = 15000,
6284 .g1_irqs = 9,
6285 .g2_irqs = 10,
6286 .atu_move_port_mask = 0xf,
6287 .pvt = true,
6288 .multi_chip = true,
6289 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6290 .ops = &mv88e6350_ops,
6291 },
6292
6293 [MV88E6351] = {
6294 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
6295 .family = MV88E6XXX_FAMILY_6351,
6296 .name = "Marvell 88E6351",
6297 .num_databases = 4096,
6298 .num_macs = 8192,
6299 .num_ports = 7,
6300 .num_internal_phys = 5,
6301 .max_vid = 4095,
6302 .max_sid = 63,
6303 .port_base_addr = 0x10,
6304 .phy_base_addr = 0x0,
6305 .global1_addr = 0x1b,
6306 .global2_addr = 0x1c,
6307 .age_time_coeff = 15000,
6308 .g1_irqs = 9,
6309 .g2_irqs = 10,
6310 .atu_move_port_mask = 0xf,
6311 .pvt = true,
6312 .multi_chip = true,
6313 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6314 .ops = &mv88e6351_ops,
6315 },
6316
6317 [MV88E6352] = {
6318 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
6319 .family = MV88E6XXX_FAMILY_6352,
6320 .name = "Marvell 88E6352",
6321 .num_databases = 4096,
6322 .num_macs = 8192,
6323 .num_ports = 7,
6324 .num_internal_phys = 5,
6325 .num_gpio = 15,
6326 .max_vid = 4095,
6327 .max_sid = 63,
6328 .port_base_addr = 0x10,
6329 .phy_base_addr = 0x0,
6330 .global1_addr = 0x1b,
6331 .global2_addr = 0x1c,
6332 .age_time_coeff = 15000,
6333 .g1_irqs = 9,
6334 .g2_irqs = 10,
6335 .atu_move_port_mask = 0xf,
6336 .pvt = true,
6337 .multi_chip = true,
6338 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6339 .ptp_support = true,
6340 .ops = &mv88e6352_ops,
6341 },
6342 [MV88E6361] = {
6343 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361,
6344 .family = MV88E6XXX_FAMILY_6393,
6345 .name = "Marvell 88E6361",
6346 .num_databases = 4096,
6347 .num_macs = 16384,
6348 .num_ports = 11,
6349 /* Ports 1, 2 and 8 are not routed */
6350 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8),
6351 .num_internal_phys = 5,
6352 .internal_phys_offset = 3,
6353 .max_vid = 8191,
6354 .max_sid = 63,
6355 .port_base_addr = 0x0,
6356 .phy_base_addr = 0x0,
6357 .global1_addr = 0x1b,
6358 .global2_addr = 0x1c,
6359 .age_time_coeff = 3750,
6360 .g1_irqs = 10,
6361 .g2_irqs = 14,
6362 .atu_move_port_mask = 0x1f,
6363 .pvt = true,
6364 .multi_chip = true,
6365 .ptp_support = true,
6366 .ops = &mv88e6393x_ops,
6367 },
6368 [MV88E6390] = {
6369 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
6370 .family = MV88E6XXX_FAMILY_6390,
6371 .name = "Marvell 88E6390",
6372 .num_databases = 4096,
6373 .num_macs = 16384,
6374 .num_ports = 11, /* 10 + Z80 */
6375 .num_internal_phys = 9,
6376 .num_gpio = 16,
6377 .max_vid = 8191,
6378 .max_sid = 63,
6379 .port_base_addr = 0x0,
6380 .phy_base_addr = 0x0,
6381 .global1_addr = 0x1b,
6382 .global2_addr = 0x1c,
6383 .age_time_coeff = 3750,
6384 .g1_irqs = 9,
6385 .g2_irqs = 14,
6386 .atu_move_port_mask = 0x1f,
6387 .pvt = true,
6388 .multi_chip = true,
6389 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6390 .ptp_support = true,
6391 .ops = &mv88e6390_ops,
6392 },
6393 [MV88E6390X] = {
6394 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
6395 .family = MV88E6XXX_FAMILY_6390,
6396 .name = "Marvell 88E6390X",
6397 .num_databases = 4096,
6398 .num_macs = 16384,
6399 .num_ports = 11, /* 10 + Z80 */
6400 .num_internal_phys = 9,
6401 .num_gpio = 16,
6402 .max_vid = 8191,
6403 .max_sid = 63,
6404 .port_base_addr = 0x0,
6405 .phy_base_addr = 0x0,
6406 .global1_addr = 0x1b,
6407 .global2_addr = 0x1c,
6408 .age_time_coeff = 3750,
6409 .g1_irqs = 9,
6410 .g2_irqs = 14,
6411 .atu_move_port_mask = 0x1f,
6412 .pvt = true,
6413 .multi_chip = true,
6414 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6415 .ptp_support = true,
6416 .ops = &mv88e6390x_ops,
6417 },
6418
6419 [MV88E6393X] = {
6420 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
6421 .family = MV88E6XXX_FAMILY_6393,
6422 .name = "Marvell 88E6393X",
6423 .num_databases = 4096,
6424 .num_ports = 11, /* 10 + Z80 */
6425 .num_internal_phys = 8,
6426 .internal_phys_offset = 1,
6427 .max_vid = 8191,
6428 .max_sid = 63,
6429 .port_base_addr = 0x0,
6430 .phy_base_addr = 0x0,
6431 .global1_addr = 0x1b,
6432 .global2_addr = 0x1c,
6433 .age_time_coeff = 3750,
6434 .g1_irqs = 10,
6435 .g2_irqs = 14,
6436 .atu_move_port_mask = 0x1f,
6437 .pvt = true,
6438 .multi_chip = true,
6439 .ptp_support = true,
6440 .ops = &mv88e6393x_ops,
6441 },
6442};
6443
6444static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
6445{
6446 int i;
6447
6448 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
6449 if (mv88e6xxx_table[i].prod_num == prod_num)
6450 return &mv88e6xxx_table[i];
6451
6452 return NULL;
6453}
6454
6455static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
6456{
6457 const struct mv88e6xxx_info *info;
6458 unsigned int prod_num, rev;
6459 u16 id;
6460 int err;
6461
6462 mv88e6xxx_reg_lock(chip);
6463 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
6464 mv88e6xxx_reg_unlock(chip);
6465 if (err)
6466 return err;
6467
6468 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
6469 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
6470
6471 info = mv88e6xxx_lookup_info(prod_num);
6472 if (!info)
6473 return -ENODEV;
6474
6475 /* Update the compatible info with the probed one */
6476 chip->info = info;
6477
6478 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
6479 chip->info->prod_num, chip->info->name, rev);
6480
6481 return 0;
6482}
6483
6484static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip,
6485 struct mdio_device *mdiodev)
6486{
6487 int err;
6488
6489 /* dual_chip takes precedence over single/multi-chip modes */
6490 if (chip->info->dual_chip)
6491 return -EINVAL;
6492
6493 /* If the mdio addr is 16 indicating the first port address of a switch
6494 * (e.g. mv88e6*41) in single chip addressing mode the device may be
6495 * configured in single chip addressing mode. Setup the smi access as
6496 * single chip addressing mode and attempt to detect the model of the
6497 * switch, if this fails the device is not configured in single chip
6498 * addressing mode.
6499 */
6500 if (mdiodev->addr != 16)
6501 return -EINVAL;
6502
6503 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0);
6504 if (err)
6505 return err;
6506
6507 return mv88e6xxx_detect(chip);
6508}
6509
6510static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
6511{
6512 struct mv88e6xxx_chip *chip;
6513
6514 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
6515 if (!chip)
6516 return NULL;
6517
6518 chip->dev = dev;
6519
6520 mutex_init(&chip->reg_lock);
6521 INIT_LIST_HEAD(&chip->mdios);
6522 idr_init(&chip->policies);
6523 INIT_LIST_HEAD(&chip->msts);
6524
6525 return chip;
6526}
6527
6528static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
6529 int port,
6530 enum dsa_tag_protocol m)
6531{
6532 struct mv88e6xxx_chip *chip = ds->priv;
6533
6534 return chip->tag_protocol;
6535}
6536
6537static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds,
6538 enum dsa_tag_protocol proto)
6539{
6540 struct mv88e6xxx_chip *chip = ds->priv;
6541 enum dsa_tag_protocol old_protocol;
6542 struct dsa_port *cpu_dp;
6543 int err;
6544
6545 switch (proto) {
6546 case DSA_TAG_PROTO_EDSA:
6547 switch (chip->info->edsa_support) {
6548 case MV88E6XXX_EDSA_UNSUPPORTED:
6549 return -EPROTONOSUPPORT;
6550 case MV88E6XXX_EDSA_UNDOCUMENTED:
6551 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
6552 fallthrough;
6553 case MV88E6XXX_EDSA_SUPPORTED:
6554 break;
6555 }
6556 break;
6557 case DSA_TAG_PROTO_DSA:
6558 break;
6559 default:
6560 return -EPROTONOSUPPORT;
6561 }
6562
6563 old_protocol = chip->tag_protocol;
6564 chip->tag_protocol = proto;
6565
6566 mv88e6xxx_reg_lock(chip);
6567 dsa_switch_for_each_cpu_port(cpu_dp, ds) {
6568 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6569 if (err) {
6570 mv88e6xxx_reg_unlock(chip);
6571 goto unwind;
6572 }
6573 }
6574 mv88e6xxx_reg_unlock(chip);
6575
6576 return 0;
6577
6578unwind:
6579 chip->tag_protocol = old_protocol;
6580
6581 mv88e6xxx_reg_lock(chip);
6582 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds)
6583 mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6584 mv88e6xxx_reg_unlock(chip);
6585
6586 return err;
6587}
6588
6589static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
6590 const struct switchdev_obj_port_mdb *mdb,
6591 struct dsa_db db)
6592{
6593 struct mv88e6xxx_chip *chip = ds->priv;
6594 int err;
6595
6596 mv88e6xxx_reg_lock(chip);
6597 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
6598 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
6599 mv88e6xxx_reg_unlock(chip);
6600
6601 return err;
6602}
6603
6604static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
6605 const struct switchdev_obj_port_mdb *mdb,
6606 struct dsa_db db)
6607{
6608 struct mv88e6xxx_chip *chip = ds->priv;
6609 int err;
6610
6611 mv88e6xxx_reg_lock(chip);
6612 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
6613 mv88e6xxx_reg_unlock(chip);
6614
6615 return err;
6616}
6617
6618static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
6619 struct dsa_mall_mirror_tc_entry *mirror,
6620 bool ingress,
6621 struct netlink_ext_ack *extack)
6622{
6623 enum mv88e6xxx_egress_direction direction = ingress ?
6624 MV88E6XXX_EGRESS_DIR_INGRESS :
6625 MV88E6XXX_EGRESS_DIR_EGRESS;
6626 struct mv88e6xxx_chip *chip = ds->priv;
6627 bool other_mirrors = false;
6628 int i;
6629 int err;
6630
6631 mutex_lock(&chip->reg_lock);
6632 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
6633 mirror->to_local_port) {
6634 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6635 other_mirrors |= ingress ?
6636 chip->ports[i].mirror_ingress :
6637 chip->ports[i].mirror_egress;
6638
6639 /* Can't change egress port when other mirror is active */
6640 if (other_mirrors) {
6641 err = -EBUSY;
6642 goto out;
6643 }
6644
6645 err = mv88e6xxx_set_egress_port(chip, direction,
6646 mirror->to_local_port);
6647 if (err)
6648 goto out;
6649 }
6650
6651 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
6652out:
6653 mutex_unlock(&chip->reg_lock);
6654
6655 return err;
6656}
6657
6658static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
6659 struct dsa_mall_mirror_tc_entry *mirror)
6660{
6661 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
6662 MV88E6XXX_EGRESS_DIR_INGRESS :
6663 MV88E6XXX_EGRESS_DIR_EGRESS;
6664 struct mv88e6xxx_chip *chip = ds->priv;
6665 bool other_mirrors = false;
6666 int i;
6667
6668 mutex_lock(&chip->reg_lock);
6669 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
6670 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
6671
6672 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6673 other_mirrors |= mirror->ingress ?
6674 chip->ports[i].mirror_ingress :
6675 chip->ports[i].mirror_egress;
6676
6677 /* Reset egress port when no other mirror is active */
6678 if (!other_mirrors) {
6679 if (mv88e6xxx_set_egress_port(chip, direction,
6680 dsa_upstream_port(ds, port)))
6681 dev_err(ds->dev, "failed to set egress port\n");
6682 }
6683
6684 mutex_unlock(&chip->reg_lock);
6685}
6686
6687static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
6688 struct switchdev_brport_flags flags,
6689 struct netlink_ext_ack *extack)
6690{
6691 struct mv88e6xxx_chip *chip = ds->priv;
6692 const struct mv88e6xxx_ops *ops;
6693
6694 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
6695 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB))
6696 return -EINVAL;
6697
6698 ops = chip->info->ops;
6699
6700 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
6701 return -EINVAL;
6702
6703 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
6704 return -EINVAL;
6705
6706 return 0;
6707}
6708
6709static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
6710 struct switchdev_brport_flags flags,
6711 struct netlink_ext_ack *extack)
6712{
6713 struct mv88e6xxx_chip *chip = ds->priv;
6714 int err = 0;
6715
6716 mv88e6xxx_reg_lock(chip);
6717
6718 if (flags.mask & BR_LEARNING) {
6719 bool learning = !!(flags.val & BR_LEARNING);
6720 u16 pav = learning ? (1 << port) : 0;
6721
6722 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
6723 if (err)
6724 goto out;
6725 }
6726
6727 if (flags.mask & BR_FLOOD) {
6728 bool unicast = !!(flags.val & BR_FLOOD);
6729
6730 err = chip->info->ops->port_set_ucast_flood(chip, port,
6731 unicast);
6732 if (err)
6733 goto out;
6734 }
6735
6736 if (flags.mask & BR_MCAST_FLOOD) {
6737 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
6738
6739 err = chip->info->ops->port_set_mcast_flood(chip, port,
6740 multicast);
6741 if (err)
6742 goto out;
6743 }
6744
6745 if (flags.mask & BR_BCAST_FLOOD) {
6746 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
6747
6748 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
6749 if (err)
6750 goto out;
6751 }
6752
6753 if (flags.mask & BR_PORT_MAB) {
6754 bool mab = !!(flags.val & BR_PORT_MAB);
6755
6756 mv88e6xxx_port_set_mab(chip, port, mab);
6757 }
6758
6759 if (flags.mask & BR_PORT_LOCKED) {
6760 bool locked = !!(flags.val & BR_PORT_LOCKED);
6761
6762 err = mv88e6xxx_port_set_lock(chip, port, locked);
6763 if (err)
6764 goto out;
6765 }
6766out:
6767 mv88e6xxx_reg_unlock(chip);
6768
6769 return err;
6770}
6771
6772static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
6773 struct dsa_lag lag,
6774 struct netdev_lag_upper_info *info,
6775 struct netlink_ext_ack *extack)
6776{
6777 struct mv88e6xxx_chip *chip = ds->priv;
6778 struct dsa_port *dp;
6779 int members = 0;
6780
6781 if (!mv88e6xxx_has_lag(chip)) {
6782 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload");
6783 return false;
6784 }
6785
6786 if (!lag.id)
6787 return false;
6788
6789 dsa_lag_foreach_port(dp, ds->dst, &lag)
6790 /* Includes the port joining the LAG */
6791 members++;
6792
6793 if (members > 8) {
6794 NL_SET_ERR_MSG_MOD(extack,
6795 "Cannot offload more than 8 LAG ports");
6796 return false;
6797 }
6798
6799 /* We could potentially relax this to include active
6800 * backup in the future.
6801 */
6802 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
6803 NL_SET_ERR_MSG_MOD(extack,
6804 "Can only offload LAG using hash TX type");
6805 return false;
6806 }
6807
6808 /* Ideally we would also validate that the hash type matches
6809 * the hardware. Alas, this is always set to unknown on team
6810 * interfaces.
6811 */
6812 return true;
6813}
6814
6815static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag)
6816{
6817 struct mv88e6xxx_chip *chip = ds->priv;
6818 struct dsa_port *dp;
6819 u16 map = 0;
6820 int id;
6821
6822 /* DSA LAG IDs are one-based, hardware is zero-based */
6823 id = lag.id - 1;
6824
6825 /* Build the map of all ports to distribute flows destined for
6826 * this LAG. This can be either a local user port, or a DSA
6827 * port if the LAG port is on a remote chip.
6828 */
6829 dsa_lag_foreach_port(dp, ds->dst, &lag)
6830 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
6831
6832 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
6833}
6834
6835static const u8 mv88e6xxx_lag_mask_table[8][8] = {
6836 /* Row number corresponds to the number of active members in a
6837 * LAG. Each column states which of the eight hash buckets are
6838 * mapped to the column:th port in the LAG.
6839 *
6840 * Example: In a LAG with three active ports, the second port
6841 * ([2][1]) would be selected for traffic mapped to buckets
6842 * 3,4,5 (0x38).
6843 */
6844 { 0xff, 0, 0, 0, 0, 0, 0, 0 },
6845 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 },
6846 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 },
6847 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 },
6848 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 },
6849 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 },
6850 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 },
6851 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
6852};
6853
6854static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
6855 int num_tx, int nth)
6856{
6857 u8 active = 0;
6858 int i;
6859
6860 num_tx = num_tx <= 8 ? num_tx : 8;
6861 if (nth < num_tx)
6862 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
6863
6864 for (i = 0; i < 8; i++) {
6865 if (BIT(i) & active)
6866 mask[i] |= BIT(port);
6867 }
6868}
6869
6870static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
6871{
6872 struct mv88e6xxx_chip *chip = ds->priv;
6873 unsigned int id, num_tx;
6874 struct dsa_port *dp;
6875 struct dsa_lag *lag;
6876 int i, err, nth;
6877 u16 mask[8];
6878 u16 ivec;
6879
6880 /* Assume no port is a member of any LAG. */
6881 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
6882
6883 /* Disable all masks for ports that _are_ members of a LAG. */
6884 dsa_switch_for_each_port(dp, ds) {
6885 if (!dp->lag)
6886 continue;
6887
6888 ivec &= ~BIT(dp->index);
6889 }
6890
6891 for (i = 0; i < 8; i++)
6892 mask[i] = ivec;
6893
6894 /* Enable the correct subset of masks for all LAG ports that
6895 * are in the Tx set.
6896 */
6897 dsa_lags_foreach_id(id, ds->dst) {
6898 lag = dsa_lag_by_id(ds->dst, id);
6899 if (!lag)
6900 continue;
6901
6902 num_tx = 0;
6903 dsa_lag_foreach_port(dp, ds->dst, lag) {
6904 if (dp->lag_tx_enabled)
6905 num_tx++;
6906 }
6907
6908 if (!num_tx)
6909 continue;
6910
6911 nth = 0;
6912 dsa_lag_foreach_port(dp, ds->dst, lag) {
6913 if (!dp->lag_tx_enabled)
6914 continue;
6915
6916 if (dp->ds == ds)
6917 mv88e6xxx_lag_set_port_mask(mask, dp->index,
6918 num_tx, nth);
6919
6920 nth++;
6921 }
6922 }
6923
6924 for (i = 0; i < 8; i++) {
6925 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
6926 if (err)
6927 return err;
6928 }
6929
6930 return 0;
6931}
6932
6933static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
6934 struct dsa_lag lag)
6935{
6936 int err;
6937
6938 err = mv88e6xxx_lag_sync_masks(ds);
6939
6940 if (!err)
6941 err = mv88e6xxx_lag_sync_map(ds, lag);
6942
6943 return err;
6944}
6945
6946static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
6947{
6948 struct mv88e6xxx_chip *chip = ds->priv;
6949 int err;
6950
6951 mv88e6xxx_reg_lock(chip);
6952 err = mv88e6xxx_lag_sync_masks(ds);
6953 mv88e6xxx_reg_unlock(chip);
6954 return err;
6955}
6956
6957static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
6958 struct dsa_lag lag,
6959 struct netdev_lag_upper_info *info,
6960 struct netlink_ext_ack *extack)
6961{
6962 struct mv88e6xxx_chip *chip = ds->priv;
6963 int err, id;
6964
6965 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6966 return -EOPNOTSUPP;
6967
6968 /* DSA LAG IDs are one-based */
6969 id = lag.id - 1;
6970
6971 mv88e6xxx_reg_lock(chip);
6972
6973 err = mv88e6xxx_port_set_trunk(chip, port, true, id);
6974 if (err)
6975 goto err_unlock;
6976
6977 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6978 if (err)
6979 goto err_clear_trunk;
6980
6981 mv88e6xxx_reg_unlock(chip);
6982 return 0;
6983
6984err_clear_trunk:
6985 mv88e6xxx_port_set_trunk(chip, port, false, 0);
6986err_unlock:
6987 mv88e6xxx_reg_unlock(chip);
6988 return err;
6989}
6990
6991static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6992 struct dsa_lag lag)
6993{
6994 struct mv88e6xxx_chip *chip = ds->priv;
6995 int err_sync, err_trunk;
6996
6997 mv88e6xxx_reg_lock(chip);
6998 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6999 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
7000 mv88e6xxx_reg_unlock(chip);
7001 return err_sync ? : err_trunk;
7002}
7003
7004static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
7005 int port)
7006{
7007 struct mv88e6xxx_chip *chip = ds->priv;
7008 int err;
7009
7010 mv88e6xxx_reg_lock(chip);
7011 err = mv88e6xxx_lag_sync_masks(ds);
7012 mv88e6xxx_reg_unlock(chip);
7013 return err;
7014}
7015
7016static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
7017 int port, struct dsa_lag lag,
7018 struct netdev_lag_upper_info *info,
7019 struct netlink_ext_ack *extack)
7020{
7021 struct mv88e6xxx_chip *chip = ds->priv;
7022 int err;
7023
7024 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
7025 return -EOPNOTSUPP;
7026
7027 mv88e6xxx_reg_lock(chip);
7028
7029 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
7030 if (err)
7031 goto unlock;
7032
7033 err = mv88e6xxx_pvt_map(chip, sw_index, port);
7034
7035unlock:
7036 mv88e6xxx_reg_unlock(chip);
7037 return err;
7038}
7039
7040static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
7041 int port, struct dsa_lag lag)
7042{
7043 struct mv88e6xxx_chip *chip = ds->priv;
7044 int err_sync, err_pvt;
7045
7046 mv88e6xxx_reg_lock(chip);
7047 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
7048 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
7049 mv88e6xxx_reg_unlock(chip);
7050 return err_sync ? : err_pvt;
7051}
7052
7053static const struct phylink_mac_ops mv88e6xxx_phylink_mac_ops = {
7054 .mac_select_pcs = mv88e6xxx_mac_select_pcs,
7055 .mac_prepare = mv88e6xxx_mac_prepare,
7056 .mac_config = mv88e6xxx_mac_config,
7057 .mac_finish = mv88e6xxx_mac_finish,
7058 .mac_link_down = mv88e6xxx_mac_link_down,
7059 .mac_link_up = mv88e6xxx_mac_link_up,
7060};
7061
7062static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
7063 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
7064 .change_tag_protocol = mv88e6xxx_change_tag_protocol,
7065 .setup = mv88e6xxx_setup,
7066 .teardown = mv88e6xxx_teardown,
7067 .port_setup = mv88e6xxx_port_setup,
7068 .port_teardown = mv88e6xxx_port_teardown,
7069 .phylink_get_caps = mv88e6xxx_get_caps,
7070 .get_strings = mv88e6xxx_get_strings,
7071 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
7072 .get_eth_mac_stats = mv88e6xxx_get_eth_mac_stats,
7073 .get_rmon_stats = mv88e6xxx_get_rmon_stats,
7074 .get_sset_count = mv88e6xxx_get_sset_count,
7075 .port_max_mtu = mv88e6xxx_get_max_mtu,
7076 .port_change_mtu = mv88e6xxx_change_mtu,
7077 .get_mac_eee = mv88e6xxx_get_mac_eee,
7078 .set_mac_eee = mv88e6xxx_set_mac_eee,
7079 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
7080 .get_eeprom = mv88e6xxx_get_eeprom,
7081 .set_eeprom = mv88e6xxx_set_eeprom,
7082 .get_regs_len = mv88e6xxx_get_regs_len,
7083 .get_regs = mv88e6xxx_get_regs,
7084 .get_rxnfc = mv88e6xxx_get_rxnfc,
7085 .set_rxnfc = mv88e6xxx_set_rxnfc,
7086 .set_ageing_time = mv88e6xxx_set_ageing_time,
7087 .port_bridge_join = mv88e6xxx_port_bridge_join,
7088 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
7089 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags,
7090 .port_bridge_flags = mv88e6xxx_port_bridge_flags,
7091 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
7092 .port_mst_state_set = mv88e6xxx_port_mst_state_set,
7093 .port_fast_age = mv88e6xxx_port_fast_age,
7094 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age,
7095 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
7096 .port_vlan_add = mv88e6xxx_port_vlan_add,
7097 .port_vlan_del = mv88e6xxx_port_vlan_del,
7098 .vlan_msti_set = mv88e6xxx_vlan_msti_set,
7099 .port_fdb_add = mv88e6xxx_port_fdb_add,
7100 .port_fdb_del = mv88e6xxx_port_fdb_del,
7101 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7102 .port_mdb_add = mv88e6xxx_port_mdb_add,
7103 .port_mdb_del = mv88e6xxx_port_mdb_del,
7104 .port_mirror_add = mv88e6xxx_port_mirror_add,
7105 .port_mirror_del = mv88e6xxx_port_mirror_del,
7106 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
7107 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
7108 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
7109 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
7110 .port_txtstamp = mv88e6xxx_port_txtstamp,
7111 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
7112 .get_ts_info = mv88e6xxx_get_ts_info,
7113 .devlink_param_get = mv88e6xxx_devlink_param_get,
7114 .devlink_param_set = mv88e6xxx_devlink_param_set,
7115 .devlink_info_get = mv88e6xxx_devlink_info_get,
7116 .port_lag_change = mv88e6xxx_port_lag_change,
7117 .port_lag_join = mv88e6xxx_port_lag_join,
7118 .port_lag_leave = mv88e6xxx_port_lag_leave,
7119 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change,
7120 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join,
7121 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave,
7122};
7123
7124static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
7125{
7126 struct device *dev = chip->dev;
7127 struct dsa_switch *ds;
7128
7129 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
7130 if (!ds)
7131 return -ENOMEM;
7132
7133 ds->dev = dev;
7134 ds->num_ports = mv88e6xxx_num_ports(chip);
7135 ds->priv = chip;
7136 ds->dev = dev;
7137 ds->ops = &mv88e6xxx_switch_ops;
7138 ds->phylink_mac_ops = &mv88e6xxx_phylink_mac_ops;
7139 ds->ageing_time_min = chip->info->age_time_coeff;
7140 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
7141
7142 /* Some chips support up to 32, but that requires enabling the
7143 * 5-bit port mode, which we do not support. 640k^W16 ought to
7144 * be enough for anyone.
7145 */
7146 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
7147
7148 dev_set_drvdata(dev, ds);
7149
7150 return dsa_register_switch(ds);
7151}
7152
7153static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
7154{
7155 dsa_unregister_switch(chip->ds);
7156}
7157
7158static const void *pdata_device_get_match_data(struct device *dev)
7159{
7160 const struct of_device_id *matches = dev->driver->of_match_table;
7161 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
7162
7163 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
7164 matches++) {
7165 if (!strcmp(pdata->compatible, matches->compatible))
7166 return matches->data;
7167 }
7168 return NULL;
7169}
7170
7171/* There is no suspend to RAM support at DSA level yet, the switch configuration
7172 * would be lost after a power cycle so prevent it to be suspended.
7173 */
7174static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
7175{
7176 return -EOPNOTSUPP;
7177}
7178
7179static int __maybe_unused mv88e6xxx_resume(struct device *dev)
7180{
7181 return 0;
7182}
7183
7184static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
7185
7186static int mv88e6xxx_probe(struct mdio_device *mdiodev)
7187{
7188 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
7189 const struct mv88e6xxx_info *compat_info = NULL;
7190 struct device *dev = &mdiodev->dev;
7191 struct device_node *np = dev->of_node;
7192 struct mv88e6xxx_chip *chip;
7193 int port;
7194 int err;
7195
7196 if (!np && !pdata)
7197 return -EINVAL;
7198
7199 if (np)
7200 compat_info = of_device_get_match_data(dev);
7201
7202 if (pdata) {
7203 compat_info = pdata_device_get_match_data(dev);
7204
7205 if (!pdata->netdev)
7206 return -EINVAL;
7207
7208 for (port = 0; port < DSA_MAX_PORTS; port++) {
7209 if (!(pdata->enabled_ports & (1 << port)))
7210 continue;
7211 if (strcmp(pdata->cd.port_names[port], "cpu"))
7212 continue;
7213 pdata->cd.netdev[port] = &pdata->netdev->dev;
7214 break;
7215 }
7216 }
7217
7218 if (!compat_info)
7219 return -EINVAL;
7220
7221 chip = mv88e6xxx_alloc_chip(dev);
7222 if (!chip) {
7223 err = -ENOMEM;
7224 goto out;
7225 }
7226
7227 chip->info = compat_info;
7228
7229 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
7230 if (IS_ERR(chip->reset)) {
7231 err = PTR_ERR(chip->reset);
7232 goto out;
7233 }
7234 if (chip->reset)
7235 usleep_range(10000, 20000);
7236
7237 /* Detect if the device is configured in single chip addressing mode,
7238 * otherwise continue with address specific smi init/detection.
7239 */
7240 err = mv88e6xxx_single_chip_detect(chip, mdiodev);
7241 if (err) {
7242 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
7243 if (err)
7244 goto out;
7245
7246 err = mv88e6xxx_detect(chip);
7247 if (err)
7248 goto out;
7249 }
7250
7251 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
7252 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
7253 else
7254 chip->tag_protocol = DSA_TAG_PROTO_DSA;
7255
7256 mv88e6xxx_phy_init(chip);
7257
7258 if (chip->info->ops->get_eeprom) {
7259 if (np)
7260 of_property_read_u32(np, "eeprom-length",
7261 &chip->eeprom_len);
7262 else
7263 chip->eeprom_len = pdata->eeprom_len;
7264 }
7265
7266 mv88e6xxx_reg_lock(chip);
7267 err = mv88e6xxx_switch_reset(chip);
7268 mv88e6xxx_reg_unlock(chip);
7269 if (err)
7270 goto out;
7271
7272 if (np) {
7273 chip->irq = of_irq_get(np, 0);
7274 if (chip->irq == -EPROBE_DEFER) {
7275 err = chip->irq;
7276 goto out;
7277 }
7278 }
7279
7280 if (pdata)
7281 chip->irq = pdata->irq;
7282
7283 /* Has to be performed before the MDIO bus is created, because
7284 * the PHYs will link their interrupts to these interrupt
7285 * controllers
7286 */
7287 mv88e6xxx_reg_lock(chip);
7288 if (chip->irq > 0)
7289 err = mv88e6xxx_g1_irq_setup(chip);
7290 else
7291 err = mv88e6xxx_irq_poll_setup(chip);
7292 mv88e6xxx_reg_unlock(chip);
7293
7294 if (err)
7295 goto out;
7296
7297 if (chip->info->g2_irqs > 0) {
7298 err = mv88e6xxx_g2_irq_setup(chip);
7299 if (err)
7300 goto out_g1_irq;
7301 }
7302
7303 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
7304 if (err)
7305 goto out_g2_irq;
7306
7307 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
7308 if (err)
7309 goto out_g1_atu_prob_irq;
7310
7311 err = mv88e6xxx_register_switch(chip);
7312 if (err)
7313 goto out_g1_vtu_prob_irq;
7314
7315 return 0;
7316
7317out_g1_vtu_prob_irq:
7318 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7319out_g1_atu_prob_irq:
7320 mv88e6xxx_g1_atu_prob_irq_free(chip);
7321out_g2_irq:
7322 if (chip->info->g2_irqs > 0)
7323 mv88e6xxx_g2_irq_free(chip);
7324out_g1_irq:
7325 if (chip->irq > 0)
7326 mv88e6xxx_g1_irq_free(chip);
7327 else
7328 mv88e6xxx_irq_poll_free(chip);
7329out:
7330 if (pdata)
7331 dev_put(pdata->netdev);
7332
7333 return err;
7334}
7335
7336static void mv88e6xxx_remove(struct mdio_device *mdiodev)
7337{
7338 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7339 struct mv88e6xxx_chip *chip;
7340
7341 if (!ds)
7342 return;
7343
7344 chip = ds->priv;
7345
7346 if (chip->info->ptp_support) {
7347 mv88e6xxx_hwtstamp_free(chip);
7348 mv88e6xxx_ptp_free(chip);
7349 }
7350
7351 mv88e6xxx_phy_destroy(chip);
7352 mv88e6xxx_unregister_switch(chip);
7353
7354 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7355 mv88e6xxx_g1_atu_prob_irq_free(chip);
7356
7357 if (chip->info->g2_irqs > 0)
7358 mv88e6xxx_g2_irq_free(chip);
7359
7360 if (chip->irq > 0)
7361 mv88e6xxx_g1_irq_free(chip);
7362 else
7363 mv88e6xxx_irq_poll_free(chip);
7364}
7365
7366static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
7367{
7368 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7369
7370 if (!ds)
7371 return;
7372
7373 dsa_switch_shutdown(ds);
7374
7375 dev_set_drvdata(&mdiodev->dev, NULL);
7376}
7377
7378static const struct of_device_id mv88e6xxx_of_match[] = {
7379 {
7380 .compatible = "marvell,mv88e6085",
7381 .data = &mv88e6xxx_table[MV88E6085],
7382 },
7383 {
7384 .compatible = "marvell,mv88e6190",
7385 .data = &mv88e6xxx_table[MV88E6190],
7386 },
7387 {
7388 .compatible = "marvell,mv88e6250",
7389 .data = &mv88e6xxx_table[MV88E6250],
7390 },
7391 { /* sentinel */ },
7392};
7393
7394MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
7395
7396static struct mdio_driver mv88e6xxx_driver = {
7397 .probe = mv88e6xxx_probe,
7398 .remove = mv88e6xxx_remove,
7399 .shutdown = mv88e6xxx_shutdown,
7400 .mdiodrv.driver = {
7401 .name = "mv88e6085",
7402 .of_match_table = mv88e6xxx_of_match,
7403 .pm = &mv88e6xxx_pm_ops,
7404 },
7405};
7406
7407mdio_module_driver(mv88e6xxx_driver);
7408
7409MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
7410MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
7411MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 *
9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 */
12
13#include <linux/bitfield.h>
14#include <linux/delay.h>
15#include <linux/dsa/mv88e6xxx.h>
16#include <linux/etherdevice.h>
17#include <linux/ethtool.h>
18#include <linux/if_bridge.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/irqdomain.h>
22#include <linux/jiffies.h>
23#include <linux/list.h>
24#include <linux/mdio.h>
25#include <linux/module.h>
26#include <linux/of.h>
27#include <linux/of_irq.h>
28#include <linux/of_mdio.h>
29#include <linux/platform_data/mv88e6xxx.h>
30#include <linux/netdevice.h>
31#include <linux/gpio/consumer.h>
32#include <linux/phylink.h>
33#include <net/dsa.h>
34
35#include "chip.h"
36#include "devlink.h"
37#include "global1.h"
38#include "global2.h"
39#include "hwtstamp.h"
40#include "phy.h"
41#include "port.h"
42#include "ptp.h"
43#include "serdes.h"
44#include "smi.h"
45
46static void assert_reg_lock(struct mv88e6xxx_chip *chip)
47{
48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
49 dev_err(chip->dev, "Switch registers lock not held!\n");
50 dump_stack();
51 }
52}
53
54int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
55{
56 int err;
57
58 assert_reg_lock(chip);
59
60 err = mv88e6xxx_smi_read(chip, addr, reg, val);
61 if (err)
62 return err;
63
64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
65 addr, reg, *val);
66
67 return 0;
68}
69
70int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
71{
72 int err;
73
74 assert_reg_lock(chip);
75
76 err = mv88e6xxx_smi_write(chip, addr, reg, val);
77 if (err)
78 return err;
79
80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
81 addr, reg, val);
82
83 return 0;
84}
85
86int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
87 u16 mask, u16 val)
88{
89 const unsigned long timeout = jiffies + msecs_to_jiffies(50);
90 u16 data;
91 int err;
92 int i;
93
94 /* There's no bus specific operation to wait for a mask. Even
95 * if the initial poll takes longer than 50ms, always do at
96 * least one more attempt.
97 */
98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) {
99 err = mv88e6xxx_read(chip, addr, reg, &data);
100 if (err)
101 return err;
102
103 if ((data & mask) == val)
104 return 0;
105
106 if (i < 2)
107 cpu_relax();
108 else
109 usleep_range(1000, 2000);
110 }
111
112 err = mv88e6xxx_read(chip, addr, reg, &data);
113 if (err)
114 return err;
115
116 if ((data & mask) == val)
117 return 0;
118
119 dev_err(chip->dev, "Timeout while waiting for switch\n");
120 return -ETIMEDOUT;
121}
122
123int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
124 int bit, int val)
125{
126 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
127 val ? BIT(bit) : 0x0000);
128}
129
130struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
131{
132 struct mv88e6xxx_mdio_bus *mdio_bus;
133
134 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
135 list);
136 if (!mdio_bus)
137 return NULL;
138
139 return mdio_bus->bus;
140}
141
142static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
143{
144 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
145 unsigned int n = d->hwirq;
146
147 chip->g1_irq.masked |= (1 << n);
148}
149
150static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
151{
152 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
153 unsigned int n = d->hwirq;
154
155 chip->g1_irq.masked &= ~(1 << n);
156}
157
158static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
159{
160 unsigned int nhandled = 0;
161 unsigned int sub_irq;
162 unsigned int n;
163 u16 reg;
164 u16 ctl1;
165 int err;
166
167 mv88e6xxx_reg_lock(chip);
168 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
169 mv88e6xxx_reg_unlock(chip);
170
171 if (err)
172 goto out;
173
174 do {
175 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
176 if (reg & (1 << n)) {
177 sub_irq = irq_find_mapping(chip->g1_irq.domain,
178 n);
179 handle_nested_irq(sub_irq);
180 ++nhandled;
181 }
182 }
183
184 mv88e6xxx_reg_lock(chip);
185 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
186 if (err)
187 goto unlock;
188 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
189unlock:
190 mv88e6xxx_reg_unlock(chip);
191 if (err)
192 goto out;
193 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
194 } while (reg & ctl1);
195
196out:
197 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
198}
199
200static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
201{
202 struct mv88e6xxx_chip *chip = dev_id;
203
204 return mv88e6xxx_g1_irq_thread_work(chip);
205}
206
207static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
208{
209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
210
211 mv88e6xxx_reg_lock(chip);
212}
213
214static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
215{
216 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
217 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
218 u16 reg;
219 int err;
220
221 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
222 if (err)
223 goto out;
224
225 reg &= ~mask;
226 reg |= (~chip->g1_irq.masked & mask);
227
228 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
229 if (err)
230 goto out;
231
232out:
233 mv88e6xxx_reg_unlock(chip);
234}
235
236static const struct irq_chip mv88e6xxx_g1_irq_chip = {
237 .name = "mv88e6xxx-g1",
238 .irq_mask = mv88e6xxx_g1_irq_mask,
239 .irq_unmask = mv88e6xxx_g1_irq_unmask,
240 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
241 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
242};
243
244static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
245 unsigned int irq,
246 irq_hw_number_t hwirq)
247{
248 struct mv88e6xxx_chip *chip = d->host_data;
249
250 irq_set_chip_data(irq, d->host_data);
251 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
252 irq_set_noprobe(irq);
253
254 return 0;
255}
256
257static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
258 .map = mv88e6xxx_g1_irq_domain_map,
259 .xlate = irq_domain_xlate_twocell,
260};
261
262/* To be called with reg_lock held */
263static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
264{
265 int irq, virq;
266 u16 mask;
267
268 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
269 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
270 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
271
272 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
273 virq = irq_find_mapping(chip->g1_irq.domain, irq);
274 irq_dispose_mapping(virq);
275 }
276
277 irq_domain_remove(chip->g1_irq.domain);
278}
279
280static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
281{
282 /*
283 * free_irq must be called without reg_lock taken because the irq
284 * handler takes this lock, too.
285 */
286 free_irq(chip->irq, chip);
287
288 mv88e6xxx_reg_lock(chip);
289 mv88e6xxx_g1_irq_free_common(chip);
290 mv88e6xxx_reg_unlock(chip);
291}
292
293static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
294{
295 int err, irq, virq;
296 u16 reg, mask;
297
298 chip->g1_irq.nirqs = chip->info->g1_irqs;
299 chip->g1_irq.domain = irq_domain_add_simple(
300 NULL, chip->g1_irq.nirqs, 0,
301 &mv88e6xxx_g1_irq_domain_ops, chip);
302 if (!chip->g1_irq.domain)
303 return -ENOMEM;
304
305 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
306 irq_create_mapping(chip->g1_irq.domain, irq);
307
308 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
309 chip->g1_irq.masked = ~0;
310
311 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
312 if (err)
313 goto out_mapping;
314
315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
316
317 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
318 if (err)
319 goto out_disable;
320
321 /* Reading the interrupt status clears (most of) them */
322 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
323 if (err)
324 goto out_disable;
325
326 return 0;
327
328out_disable:
329 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
330 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
331
332out_mapping:
333 for (irq = 0; irq < 16; irq++) {
334 virq = irq_find_mapping(chip->g1_irq.domain, irq);
335 irq_dispose_mapping(virq);
336 }
337
338 irq_domain_remove(chip->g1_irq.domain);
339
340 return err;
341}
342
343static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
344{
345 static struct lock_class_key lock_key;
346 static struct lock_class_key request_key;
347 int err;
348
349 err = mv88e6xxx_g1_irq_setup_common(chip);
350 if (err)
351 return err;
352
353 /* These lock classes tells lockdep that global 1 irqs are in
354 * a different category than their parent GPIO, so it won't
355 * report false recursion.
356 */
357 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
358
359 snprintf(chip->irq_name, sizeof(chip->irq_name),
360 "mv88e6xxx-%s", dev_name(chip->dev));
361
362 mv88e6xxx_reg_unlock(chip);
363 err = request_threaded_irq(chip->irq, NULL,
364 mv88e6xxx_g1_irq_thread_fn,
365 IRQF_ONESHOT | IRQF_SHARED,
366 chip->irq_name, chip);
367 mv88e6xxx_reg_lock(chip);
368 if (err)
369 mv88e6xxx_g1_irq_free_common(chip);
370
371 return err;
372}
373
374static void mv88e6xxx_irq_poll(struct kthread_work *work)
375{
376 struct mv88e6xxx_chip *chip = container_of(work,
377 struct mv88e6xxx_chip,
378 irq_poll_work.work);
379 mv88e6xxx_g1_irq_thread_work(chip);
380
381 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
382 msecs_to_jiffies(100));
383}
384
385static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
386{
387 int err;
388
389 err = mv88e6xxx_g1_irq_setup_common(chip);
390 if (err)
391 return err;
392
393 kthread_init_delayed_work(&chip->irq_poll_work,
394 mv88e6xxx_irq_poll);
395
396 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
397 if (IS_ERR(chip->kworker))
398 return PTR_ERR(chip->kworker);
399
400 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
401 msecs_to_jiffies(100));
402
403 return 0;
404}
405
406static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
407{
408 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
409 kthread_destroy_worker(chip->kworker);
410
411 mv88e6xxx_reg_lock(chip);
412 mv88e6xxx_g1_irq_free_common(chip);
413 mv88e6xxx_reg_unlock(chip);
414}
415
416static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
417 int port, phy_interface_t interface)
418{
419 int err;
420
421 if (chip->info->ops->port_set_rgmii_delay) {
422 err = chip->info->ops->port_set_rgmii_delay(chip, port,
423 interface);
424 if (err && err != -EOPNOTSUPP)
425 return err;
426 }
427
428 if (chip->info->ops->port_set_cmode) {
429 err = chip->info->ops->port_set_cmode(chip, port,
430 interface);
431 if (err && err != -EOPNOTSUPP)
432 return err;
433 }
434
435 return 0;
436}
437
438static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
439 int link, int speed, int duplex, int pause,
440 phy_interface_t mode)
441{
442 int err;
443
444 if (!chip->info->ops->port_set_link)
445 return 0;
446
447 /* Port's MAC control must not be changed unless the link is down */
448 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
449 if (err)
450 return err;
451
452 if (chip->info->ops->port_set_speed_duplex) {
453 err = chip->info->ops->port_set_speed_duplex(chip, port,
454 speed, duplex);
455 if (err && err != -EOPNOTSUPP)
456 goto restore_link;
457 }
458
459 if (chip->info->ops->port_set_pause) {
460 err = chip->info->ops->port_set_pause(chip, port, pause);
461 if (err)
462 goto restore_link;
463 }
464
465 err = mv88e6xxx_port_config_interface(chip, port, mode);
466restore_link:
467 if (chip->info->ops->port_set_link(chip, port, link))
468 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
469
470 return err;
471}
472
473static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
474{
475 return port >= chip->info->internal_phys_offset &&
476 port < chip->info->num_internal_phys +
477 chip->info->internal_phys_offset;
478}
479
480static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
481{
482 u16 reg;
483 int err;
484
485 /* The 88e6250 family does not have the PHY detect bit. Instead,
486 * report whether the port is internal.
487 */
488 if (chip->info->family == MV88E6XXX_FAMILY_6250)
489 return mv88e6xxx_phy_is_internal(chip, port);
490
491 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
492 if (err) {
493 dev_err(chip->dev,
494 "p%d: %s: failed to read port status\n",
495 port, __func__);
496 return err;
497 }
498
499 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
500}
501
502static const u8 mv88e6185_phy_interface_modes[] = {
503 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII,
504 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII,
505 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII,
506 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII,
507 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX,
508 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX,
509 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII,
510};
511
512static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
513 struct phylink_config *config)
514{
515 u8 cmode = chip->ports[port].cmode;
516
517 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
518
519 if (mv88e6xxx_phy_is_internal(chip, port)) {
520 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
521 } else {
522 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
523 mv88e6185_phy_interface_modes[cmode])
524 __set_bit(mv88e6185_phy_interface_modes[cmode],
525 config->supported_interfaces);
526
527 config->mac_capabilities |= MAC_1000FD;
528 }
529}
530
531static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
532 struct phylink_config *config)
533{
534 u8 cmode = chip->ports[port].cmode;
535
536 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
537 mv88e6185_phy_interface_modes[cmode])
538 __set_bit(mv88e6185_phy_interface_modes[cmode],
539 config->supported_interfaces);
540
541 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
542 MAC_1000FD;
543}
544
545static const u8 mv88e6xxx_phy_interface_modes[] = {
546 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII,
547 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII,
548 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII,
549 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII,
550 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII,
551 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX,
552 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX,
553 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII,
554 /* higher interface modes are not needed here, since ports supporting
555 * them are writable, and so the supported interfaces are filled in the
556 * corresponding .phylink_set_interfaces() implementation below
557 */
558};
559
560static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported)
561{
562 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) &&
563 mv88e6xxx_phy_interface_modes[cmode])
564 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported);
565 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII)
566 phy_interface_set_rgmii(supported);
567}
568
569static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
570 struct phylink_config *config)
571{
572 unsigned long *supported = config->supported_interfaces;
573
574 /* Translate the default cmode */
575 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
576
577 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
578}
579
580static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
581 struct phylink_config *config)
582{
583 unsigned long *supported = config->supported_interfaces;
584
585 /* Translate the default cmode */
586 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
587
588 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
589 MAC_1000FD;
590}
591
592static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip)
593{
594 u16 reg, val;
595 int err;
596
597 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®);
598 if (err)
599 return err;
600
601 /* If PHY_DETECT is zero, then we are not in auto-media mode */
602 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT))
603 return 0xf;
604
605 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT;
606 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val);
607 if (err)
608 return err;
609
610 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val);
611 if (err)
612 return err;
613
614 /* Restore PHY_DETECT value */
615 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg);
616 if (err)
617 return err;
618
619 return val & MV88E6XXX_PORT_STS_CMODE_MASK;
620}
621
622static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
623 struct phylink_config *config)
624{
625 unsigned long *supported = config->supported_interfaces;
626 int err, cmode;
627
628 /* Translate the default cmode */
629 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
630
631 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
632 MAC_1000FD;
633
634 /* Port 4 supports automedia if the serdes is associated with it. */
635 if (port == 4) {
636 err = mv88e6352_g2_scratch_port_has_serdes(chip, port);
637 if (err < 0)
638 dev_err(chip->dev, "p%d: failed to read scratch\n",
639 port);
640 if (err <= 0)
641 return;
642
643 cmode = mv88e6352_get_port4_serdes_cmode(chip);
644 if (cmode < 0)
645 dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
646 port);
647 else
648 mv88e6xxx_translate_cmode(cmode, supported);
649 }
650}
651
652static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
653 struct phylink_config *config)
654{
655 unsigned long *supported = config->supported_interfaces;
656
657 /* Translate the default cmode */
658 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
659
660 /* No ethtool bits for 200Mbps */
661 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
662 MAC_1000FD;
663
664 /* The C_Mode field is programmable on port 5 */
665 if (port == 5) {
666 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
667 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
668 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
669
670 config->mac_capabilities |= MAC_2500FD;
671 }
672}
673
674static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
675 struct phylink_config *config)
676{
677 unsigned long *supported = config->supported_interfaces;
678
679 /* Translate the default cmode */
680 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
681
682 /* No ethtool bits for 200Mbps */
683 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
684 MAC_1000FD;
685
686 /* The C_Mode field is programmable on ports 9 and 10 */
687 if (port == 9 || port == 10) {
688 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
689 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
690 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
691
692 config->mac_capabilities |= MAC_2500FD;
693 }
694}
695
696static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
697 struct phylink_config *config)
698{
699 unsigned long *supported = config->supported_interfaces;
700
701 mv88e6390_phylink_get_caps(chip, port, config);
702
703 /* For the 6x90X, ports 2-7 can be in automedia mode.
704 * (Note that 6x90 doesn't support RXAUI nor XAUI).
705 *
706 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is
707 * configured for 1000BASE-X, SGMII or 2500BASE-X.
708 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is
709 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
710 *
711 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is
712 * configured for 1000BASE-X, SGMII or 2500BASE-X.
713 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is
714 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
715 *
716 * For now, be permissive (as the old code was) and allow 1000BASE-X
717 * on ports 2..7.
718 */
719 if (port >= 2 && port <= 7)
720 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
721
722 /* The C_Mode field can also be programmed for 10G speeds */
723 if (port == 9 || port == 10) {
724 __set_bit(PHY_INTERFACE_MODE_XAUI, supported);
725 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported);
726
727 config->mac_capabilities |= MAC_10000FD;
728 }
729}
730
731static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
732 struct phylink_config *config)
733{
734 unsigned long *supported = config->supported_interfaces;
735 bool is_6191x =
736 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
737 bool is_6361 =
738 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361;
739
740 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
741
742 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
743 MAC_1000FD;
744
745 /* The C_Mode field can be programmed for ports 0, 9 and 10 */
746 if (port == 0 || port == 9 || port == 10) {
747 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
748 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
749
750 /* 6191X supports >1G modes only on port 10 */
751 if (!is_6191x || port == 10) {
752 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
753 config->mac_capabilities |= MAC_2500FD;
754
755 /* 6361 only supports up to 2500BaseX */
756 if (!is_6361) {
757 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
758 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
759 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported);
760 config->mac_capabilities |= MAC_5000FD |
761 MAC_10000FD;
762 }
763 }
764 }
765
766 if (port == 0) {
767 __set_bit(PHY_INTERFACE_MODE_RMII, supported);
768 __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
769 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported);
770 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported);
771 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported);
772 }
773}
774
775static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port,
776 struct phylink_config *config)
777{
778 struct mv88e6xxx_chip *chip = ds->priv;
779
780 mv88e6xxx_reg_lock(chip);
781 chip->info->ops->phylink_get_caps(chip, port, config);
782 mv88e6xxx_reg_unlock(chip);
783
784 if (mv88e6xxx_phy_is_internal(chip, port)) {
785 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
786 config->supported_interfaces);
787 /* Internal ports with no phy-mode need GMII for PHYLIB */
788 __set_bit(PHY_INTERFACE_MODE_GMII,
789 config->supported_interfaces);
790 }
791}
792
793static struct phylink_pcs *mv88e6xxx_mac_select_pcs(struct dsa_switch *ds,
794 int port,
795 phy_interface_t interface)
796{
797 struct mv88e6xxx_chip *chip = ds->priv;
798 struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP);
799
800 if (chip->info->ops->pcs_ops)
801 pcs = chip->info->ops->pcs_ops->pcs_select(chip, port,
802 interface);
803
804 return pcs;
805}
806
807static int mv88e6xxx_mac_prepare(struct dsa_switch *ds, int port,
808 unsigned int mode, phy_interface_t interface)
809{
810 struct mv88e6xxx_chip *chip = ds->priv;
811 int err = 0;
812
813 /* In inband mode, the link may come up at any time while the link
814 * is not forced down. Force the link down while we reconfigure the
815 * interface mode.
816 */
817 if (mode == MLO_AN_INBAND &&
818 chip->ports[port].interface != interface &&
819 chip->info->ops->port_set_link) {
820 mv88e6xxx_reg_lock(chip);
821 err = chip->info->ops->port_set_link(chip, port,
822 LINK_FORCED_DOWN);
823 mv88e6xxx_reg_unlock(chip);
824 }
825
826 return err;
827}
828
829static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
830 unsigned int mode,
831 const struct phylink_link_state *state)
832{
833 struct mv88e6xxx_chip *chip = ds->priv;
834 int err = 0;
835
836 mv88e6xxx_reg_lock(chip);
837
838 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) {
839 err = mv88e6xxx_port_config_interface(chip, port,
840 state->interface);
841 if (err && err != -EOPNOTSUPP)
842 goto err_unlock;
843 }
844
845err_unlock:
846 mv88e6xxx_reg_unlock(chip);
847
848 if (err && err != -EOPNOTSUPP)
849 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
850}
851
852static int mv88e6xxx_mac_finish(struct dsa_switch *ds, int port,
853 unsigned int mode, phy_interface_t interface)
854{
855 struct mv88e6xxx_chip *chip = ds->priv;
856 int err = 0;
857
858 /* Undo the forced down state above after completing configuration
859 * irrespective of its state on entry, which allows the link to come
860 * up in the in-band case where there is no separate SERDES. Also
861 * ensure that the link can come up if the PPU is in use and we are
862 * in PHY mode (we treat the PPU as an effective in-band mechanism.)
863 */
864 mv88e6xxx_reg_lock(chip);
865
866 if (chip->info->ops->port_set_link &&
867 ((mode == MLO_AN_INBAND &&
868 chip->ports[port].interface != interface) ||
869 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
870 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
871
872 mv88e6xxx_reg_unlock(chip);
873
874 chip->ports[port].interface = interface;
875
876 return err;
877}
878
879static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
880 unsigned int mode,
881 phy_interface_t interface)
882{
883 struct mv88e6xxx_chip *chip = ds->priv;
884 const struct mv88e6xxx_ops *ops;
885 int err = 0;
886
887 ops = chip->info->ops;
888
889 mv88e6xxx_reg_lock(chip);
890 /* Force the link down if we know the port may not be automatically
891 * updated by the switch or if we are using fixed-link mode.
892 */
893 if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
894 mode == MLO_AN_FIXED) && ops->port_sync_link)
895 err = ops->port_sync_link(chip, port, mode, false);
896
897 if (!err && ops->port_set_speed_duplex)
898 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED,
899 DUPLEX_UNFORCED);
900 mv88e6xxx_reg_unlock(chip);
901
902 if (err)
903 dev_err(chip->dev,
904 "p%d: failed to force MAC link down\n", port);
905}
906
907static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
908 unsigned int mode, phy_interface_t interface,
909 struct phy_device *phydev,
910 int speed, int duplex,
911 bool tx_pause, bool rx_pause)
912{
913 struct mv88e6xxx_chip *chip = ds->priv;
914 const struct mv88e6xxx_ops *ops;
915 int err = 0;
916
917 ops = chip->info->ops;
918
919 mv88e6xxx_reg_lock(chip);
920 /* Configure and force the link up if we know that the port may not
921 * automatically updated by the switch or if we are using fixed-link
922 * mode.
923 */
924 if (!mv88e6xxx_port_ppu_updates(chip, port) ||
925 mode == MLO_AN_FIXED) {
926 if (ops->port_set_speed_duplex) {
927 err = ops->port_set_speed_duplex(chip, port,
928 speed, duplex);
929 if (err && err != -EOPNOTSUPP)
930 goto error;
931 }
932
933 if (ops->port_sync_link)
934 err = ops->port_sync_link(chip, port, mode, true);
935 }
936error:
937 mv88e6xxx_reg_unlock(chip);
938
939 if (err && err != -EOPNOTSUPP)
940 dev_err(ds->dev,
941 "p%d: failed to configure MAC link up\n", port);
942}
943
944static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
945{
946 int err;
947
948 if (!chip->info->ops->stats_snapshot)
949 return -EOPNOTSUPP;
950
951 mv88e6xxx_reg_lock(chip);
952 err = chip->info->ops->stats_snapshot(chip, port);
953 mv88e6xxx_reg_unlock(chip);
954
955 return err;
956}
957
958#define MV88E6XXX_HW_STAT_MAPPER(_fn) \
959 _fn(in_good_octets, 8, 0x00, STATS_TYPE_BANK0), \
960 _fn(in_bad_octets, 4, 0x02, STATS_TYPE_BANK0), \
961 _fn(in_unicast, 4, 0x04, STATS_TYPE_BANK0), \
962 _fn(in_broadcasts, 4, 0x06, STATS_TYPE_BANK0), \
963 _fn(in_multicasts, 4, 0x07, STATS_TYPE_BANK0), \
964 _fn(in_pause, 4, 0x16, STATS_TYPE_BANK0), \
965 _fn(in_undersize, 4, 0x18, STATS_TYPE_BANK0), \
966 _fn(in_fragments, 4, 0x19, STATS_TYPE_BANK0), \
967 _fn(in_oversize, 4, 0x1a, STATS_TYPE_BANK0), \
968 _fn(in_jabber, 4, 0x1b, STATS_TYPE_BANK0), \
969 _fn(in_rx_error, 4, 0x1c, STATS_TYPE_BANK0), \
970 _fn(in_fcs_error, 4, 0x1d, STATS_TYPE_BANK0), \
971 _fn(out_octets, 8, 0x0e, STATS_TYPE_BANK0), \
972 _fn(out_unicast, 4, 0x10, STATS_TYPE_BANK0), \
973 _fn(out_broadcasts, 4, 0x13, STATS_TYPE_BANK0), \
974 _fn(out_multicasts, 4, 0x12, STATS_TYPE_BANK0), \
975 _fn(out_pause, 4, 0x15, STATS_TYPE_BANK0), \
976 _fn(excessive, 4, 0x11, STATS_TYPE_BANK0), \
977 _fn(collisions, 4, 0x1e, STATS_TYPE_BANK0), \
978 _fn(deferred, 4, 0x05, STATS_TYPE_BANK0), \
979 _fn(single, 4, 0x14, STATS_TYPE_BANK0), \
980 _fn(multiple, 4, 0x17, STATS_TYPE_BANK0), \
981 _fn(out_fcs_error, 4, 0x03, STATS_TYPE_BANK0), \
982 _fn(late, 4, 0x1f, STATS_TYPE_BANK0), \
983 _fn(hist_64bytes, 4, 0x08, STATS_TYPE_BANK0), \
984 _fn(hist_65_127bytes, 4, 0x09, STATS_TYPE_BANK0), \
985 _fn(hist_128_255bytes, 4, 0x0a, STATS_TYPE_BANK0), \
986 _fn(hist_256_511bytes, 4, 0x0b, STATS_TYPE_BANK0), \
987 _fn(hist_512_1023bytes, 4, 0x0c, STATS_TYPE_BANK0), \
988 _fn(hist_1024_max_bytes, 4, 0x0d, STATS_TYPE_BANK0), \
989 _fn(sw_in_discards, 4, 0x10, STATS_TYPE_PORT), \
990 _fn(sw_in_filtered, 2, 0x12, STATS_TYPE_PORT), \
991 _fn(sw_out_filtered, 2, 0x13, STATS_TYPE_PORT), \
992 _fn(in_discards, 4, 0x00, STATS_TYPE_BANK1), \
993 _fn(in_filtered, 4, 0x01, STATS_TYPE_BANK1), \
994 _fn(in_accepted, 4, 0x02, STATS_TYPE_BANK1), \
995 _fn(in_bad_accepted, 4, 0x03, STATS_TYPE_BANK1), \
996 _fn(in_good_avb_class_a, 4, 0x04, STATS_TYPE_BANK1), \
997 _fn(in_good_avb_class_b, 4, 0x05, STATS_TYPE_BANK1), \
998 _fn(in_bad_avb_class_a, 4, 0x06, STATS_TYPE_BANK1), \
999 _fn(in_bad_avb_class_b, 4, 0x07, STATS_TYPE_BANK1), \
1000 _fn(tcam_counter_0, 4, 0x08, STATS_TYPE_BANK1), \
1001 _fn(tcam_counter_1, 4, 0x09, STATS_TYPE_BANK1), \
1002 _fn(tcam_counter_2, 4, 0x0a, STATS_TYPE_BANK1), \
1003 _fn(tcam_counter_3, 4, 0x0b, STATS_TYPE_BANK1), \
1004 _fn(in_da_unknown, 4, 0x0e, STATS_TYPE_BANK1), \
1005 _fn(in_management, 4, 0x0f, STATS_TYPE_BANK1), \
1006 _fn(out_queue_0, 4, 0x10, STATS_TYPE_BANK1), \
1007 _fn(out_queue_1, 4, 0x11, STATS_TYPE_BANK1), \
1008 _fn(out_queue_2, 4, 0x12, STATS_TYPE_BANK1), \
1009 _fn(out_queue_3, 4, 0x13, STATS_TYPE_BANK1), \
1010 _fn(out_queue_4, 4, 0x14, STATS_TYPE_BANK1), \
1011 _fn(out_queue_5, 4, 0x15, STATS_TYPE_BANK1), \
1012 _fn(out_queue_6, 4, 0x16, STATS_TYPE_BANK1), \
1013 _fn(out_queue_7, 4, 0x17, STATS_TYPE_BANK1), \
1014 _fn(out_cut_through, 4, 0x18, STATS_TYPE_BANK1), \
1015 _fn(out_octets_a, 4, 0x1a, STATS_TYPE_BANK1), \
1016 _fn(out_octets_b, 4, 0x1b, STATS_TYPE_BANK1), \
1017 _fn(out_management, 4, 0x1f, STATS_TYPE_BANK1), \
1018 /* */
1019
1020#define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \
1021 { #_string, _size, _reg, _type }
1022static const struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
1023 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENTRY)
1024};
1025
1026#define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \
1027 MV88E6XXX_HW_STAT_ID_ ## _string
1028enum mv88e6xxx_hw_stat_id {
1029 MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENUM)
1030};
1031
1032static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
1033 const struct mv88e6xxx_hw_stat *s,
1034 int port, u16 bank1_select,
1035 u16 histogram)
1036{
1037 u32 low;
1038 u32 high = 0;
1039 u16 reg = 0;
1040 int err;
1041 u64 value;
1042
1043 switch (s->type) {
1044 case STATS_TYPE_PORT:
1045 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
1046 if (err)
1047 return U64_MAX;
1048
1049 low = reg;
1050 if (s->size == 4) {
1051 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
1052 if (err)
1053 return U64_MAX;
1054 low |= ((u32)reg) << 16;
1055 }
1056 break;
1057 case STATS_TYPE_BANK1:
1058 reg = bank1_select;
1059 fallthrough;
1060 case STATS_TYPE_BANK0:
1061 reg |= s->reg | histogram;
1062 mv88e6xxx_g1_stats_read(chip, reg, &low);
1063 if (s->size == 8)
1064 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
1065 break;
1066 default:
1067 return U64_MAX;
1068 }
1069 value = (((u64)high) << 32) | low;
1070 return value;
1071}
1072
1073static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
1074 uint8_t *data, int types)
1075{
1076 const struct mv88e6xxx_hw_stat *stat;
1077 int i, j;
1078
1079 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1080 stat = &mv88e6xxx_hw_stats[i];
1081 if (stat->type & types) {
1082 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
1083 ETH_GSTRING_LEN);
1084 j++;
1085 }
1086 }
1087
1088 return j;
1089}
1090
1091static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
1092 uint8_t *data)
1093{
1094 return mv88e6xxx_stats_get_strings(chip, data,
1095 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
1096}
1097
1098static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
1099 uint8_t *data)
1100{
1101 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
1102}
1103
1104static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
1105 uint8_t *data)
1106{
1107 return mv88e6xxx_stats_get_strings(chip, data,
1108 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
1109}
1110
1111static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
1112 "atu_member_violation",
1113 "atu_miss_violation",
1114 "atu_full_violation",
1115 "vtu_member_violation",
1116 "vtu_miss_violation",
1117};
1118
1119static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
1120{
1121 unsigned int i;
1122
1123 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
1124 strscpy(data + i * ETH_GSTRING_LEN,
1125 mv88e6xxx_atu_vtu_stats_strings[i],
1126 ETH_GSTRING_LEN);
1127}
1128
1129static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
1130 u32 stringset, uint8_t *data)
1131{
1132 struct mv88e6xxx_chip *chip = ds->priv;
1133 int count = 0;
1134
1135 if (stringset != ETH_SS_STATS)
1136 return;
1137
1138 mv88e6xxx_reg_lock(chip);
1139
1140 if (chip->info->ops->stats_get_strings)
1141 count = chip->info->ops->stats_get_strings(chip, data);
1142
1143 if (chip->info->ops->serdes_get_strings) {
1144 data += count * ETH_GSTRING_LEN;
1145 count = chip->info->ops->serdes_get_strings(chip, port, data);
1146 }
1147
1148 data += count * ETH_GSTRING_LEN;
1149 mv88e6xxx_atu_vtu_get_strings(data);
1150
1151 mv88e6xxx_reg_unlock(chip);
1152}
1153
1154static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1155 int types)
1156{
1157 const struct mv88e6xxx_hw_stat *stat;
1158 int i, j;
1159
1160 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1161 stat = &mv88e6xxx_hw_stats[i];
1162 if (stat->type & types)
1163 j++;
1164 }
1165 return j;
1166}
1167
1168static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1169{
1170 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1171 STATS_TYPE_PORT);
1172}
1173
1174static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1175{
1176 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1177}
1178
1179static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1180{
1181 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1182 STATS_TYPE_BANK1);
1183}
1184
1185static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1186{
1187 struct mv88e6xxx_chip *chip = ds->priv;
1188 int serdes_count = 0;
1189 int count = 0;
1190
1191 if (sset != ETH_SS_STATS)
1192 return 0;
1193
1194 mv88e6xxx_reg_lock(chip);
1195 if (chip->info->ops->stats_get_sset_count)
1196 count = chip->info->ops->stats_get_sset_count(chip);
1197 if (count < 0)
1198 goto out;
1199
1200 if (chip->info->ops->serdes_get_sset_count)
1201 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1202 port);
1203 if (serdes_count < 0) {
1204 count = serdes_count;
1205 goto out;
1206 }
1207 count += serdes_count;
1208 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1209
1210out:
1211 mv88e6xxx_reg_unlock(chip);
1212
1213 return count;
1214}
1215
1216static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1217 const struct mv88e6xxx_hw_stat *stat,
1218 uint64_t *data)
1219{
1220 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_PORT)))
1221 return 0;
1222
1223 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0,
1224 MV88E6XXX_G1_STATS_OP_HIST_RX);
1225 return 1;
1226}
1227
1228static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1229 const struct mv88e6xxx_hw_stat *stat,
1230 uint64_t *data)
1231{
1232 if (!(stat->type & STATS_TYPE_BANK0))
1233 return 0;
1234
1235 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 0,
1236 MV88E6XXX_G1_STATS_OP_HIST_RX);
1237 return 1;
1238}
1239
1240static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1241 const struct mv88e6xxx_hw_stat *stat,
1242 uint64_t *data)
1243{
1244 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1)))
1245 return 0;
1246
1247 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1248 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1249 MV88E6XXX_G1_STATS_OP_HIST_RX);
1250 return 1;
1251}
1252
1253static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1254 const struct mv88e6xxx_hw_stat *stat,
1255 uint64_t *data)
1256{
1257 if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1)))
1258 return 0;
1259
1260 *data = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1261 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1262 0);
1263 return 1;
1264}
1265
1266static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port,
1267 const struct mv88e6xxx_hw_stat *stat,
1268 uint64_t *data)
1269{
1270 int ret = 0;
1271
1272 if (chip->info->ops->stats_get_stat) {
1273 mv88e6xxx_reg_lock(chip);
1274 ret = chip->info->ops->stats_get_stat(chip, port, stat, data);
1275 mv88e6xxx_reg_unlock(chip);
1276 }
1277
1278 return ret;
1279}
1280
1281static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1282 uint64_t *data)
1283{
1284 const struct mv88e6xxx_hw_stat *stat;
1285 size_t i, j;
1286
1287 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1288 stat = &mv88e6xxx_hw_stats[i];
1289 j += mv88e6xxx_stats_get_stat(chip, port, stat, &data[j]);
1290 }
1291 return j;
1292}
1293
1294static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1295 uint64_t *data)
1296{
1297 *data++ = chip->ports[port].atu_member_violation;
1298 *data++ = chip->ports[port].atu_miss_violation;
1299 *data++ = chip->ports[port].atu_full_violation;
1300 *data++ = chip->ports[port].vtu_member_violation;
1301 *data++ = chip->ports[port].vtu_miss_violation;
1302}
1303
1304static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1305 uint64_t *data)
1306{
1307 size_t count;
1308
1309 count = mv88e6xxx_stats_get_stats(chip, port, data);
1310
1311 mv88e6xxx_reg_lock(chip);
1312 if (chip->info->ops->serdes_get_stats) {
1313 data += count;
1314 count = chip->info->ops->serdes_get_stats(chip, port, data);
1315 }
1316 data += count;
1317 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1318 mv88e6xxx_reg_unlock(chip);
1319}
1320
1321static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1322 uint64_t *data)
1323{
1324 struct mv88e6xxx_chip *chip = ds->priv;
1325 int ret;
1326
1327 ret = mv88e6xxx_stats_snapshot(chip, port);
1328 if (ret < 0)
1329 return;
1330
1331 mv88e6xxx_get_stats(chip, port, data);
1332}
1333
1334static void mv88e6xxx_get_eth_mac_stats(struct dsa_switch *ds, int port,
1335 struct ethtool_eth_mac_stats *mac_stats)
1336{
1337 struct mv88e6xxx_chip *chip = ds->priv;
1338 int ret;
1339
1340 ret = mv88e6xxx_stats_snapshot(chip, port);
1341 if (ret < 0)
1342 return;
1343
1344#define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member) \
1345 mv88e6xxx_stats_get_stat(chip, port, \
1346 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \
1347 &mac_stats->stats._member)
1348
1349 MV88E6XXX_ETH_MAC_STAT_MAP(out_unicast, FramesTransmittedOK);
1350 MV88E6XXX_ETH_MAC_STAT_MAP(single, SingleCollisionFrames);
1351 MV88E6XXX_ETH_MAC_STAT_MAP(multiple, MultipleCollisionFrames);
1352 MV88E6XXX_ETH_MAC_STAT_MAP(in_unicast, FramesReceivedOK);
1353 MV88E6XXX_ETH_MAC_STAT_MAP(in_fcs_error, FrameCheckSequenceErrors);
1354 MV88E6XXX_ETH_MAC_STAT_MAP(out_octets, OctetsTransmittedOK);
1355 MV88E6XXX_ETH_MAC_STAT_MAP(deferred, FramesWithDeferredXmissions);
1356 MV88E6XXX_ETH_MAC_STAT_MAP(late, LateCollisions);
1357 MV88E6XXX_ETH_MAC_STAT_MAP(in_good_octets, OctetsReceivedOK);
1358 MV88E6XXX_ETH_MAC_STAT_MAP(out_multicasts, MulticastFramesXmittedOK);
1359 MV88E6XXX_ETH_MAC_STAT_MAP(out_broadcasts, BroadcastFramesXmittedOK);
1360 MV88E6XXX_ETH_MAC_STAT_MAP(excessive, FramesWithExcessiveDeferral);
1361 MV88E6XXX_ETH_MAC_STAT_MAP(in_multicasts, MulticastFramesReceivedOK);
1362 MV88E6XXX_ETH_MAC_STAT_MAP(in_broadcasts, BroadcastFramesReceivedOK);
1363
1364#undef MV88E6XXX_ETH_MAC_STAT_MAP
1365
1366 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.MulticastFramesXmittedOK;
1367 mac_stats->stats.FramesTransmittedOK += mac_stats->stats.BroadcastFramesXmittedOK;
1368 mac_stats->stats.FramesReceivedOK += mac_stats->stats.MulticastFramesReceivedOK;
1369 mac_stats->stats.FramesReceivedOK += mac_stats->stats.BroadcastFramesReceivedOK;
1370}
1371
1372static void mv88e6xxx_get_rmon_stats(struct dsa_switch *ds, int port,
1373 struct ethtool_rmon_stats *rmon_stats,
1374 const struct ethtool_rmon_hist_range **ranges)
1375{
1376 static const struct ethtool_rmon_hist_range rmon_ranges[] = {
1377 { 64, 64 },
1378 { 65, 127 },
1379 { 128, 255 },
1380 { 256, 511 },
1381 { 512, 1023 },
1382 { 1024, 65535 },
1383 {}
1384 };
1385 struct mv88e6xxx_chip *chip = ds->priv;
1386 int ret;
1387
1388 ret = mv88e6xxx_stats_snapshot(chip, port);
1389 if (ret < 0)
1390 return;
1391
1392#define MV88E6XXX_RMON_STAT_MAP(_id, _member) \
1393 mv88e6xxx_stats_get_stat(chip, port, \
1394 &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \
1395 &rmon_stats->stats._member)
1396
1397 MV88E6XXX_RMON_STAT_MAP(in_undersize, undersize_pkts);
1398 MV88E6XXX_RMON_STAT_MAP(in_oversize, oversize_pkts);
1399 MV88E6XXX_RMON_STAT_MAP(in_fragments, fragments);
1400 MV88E6XXX_RMON_STAT_MAP(in_jabber, jabbers);
1401 MV88E6XXX_RMON_STAT_MAP(hist_64bytes, hist[0]);
1402 MV88E6XXX_RMON_STAT_MAP(hist_65_127bytes, hist[1]);
1403 MV88E6XXX_RMON_STAT_MAP(hist_128_255bytes, hist[2]);
1404 MV88E6XXX_RMON_STAT_MAP(hist_256_511bytes, hist[3]);
1405 MV88E6XXX_RMON_STAT_MAP(hist_512_1023bytes, hist[4]);
1406 MV88E6XXX_RMON_STAT_MAP(hist_1024_max_bytes, hist[5]);
1407
1408#undef MV88E6XXX_RMON_STAT_MAP
1409
1410 *ranges = rmon_ranges;
1411}
1412
1413static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1414{
1415 struct mv88e6xxx_chip *chip = ds->priv;
1416 int len;
1417
1418 len = 32 * sizeof(u16);
1419 if (chip->info->ops->serdes_get_regs_len)
1420 len += chip->info->ops->serdes_get_regs_len(chip, port);
1421
1422 return len;
1423}
1424
1425static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1426 struct ethtool_regs *regs, void *_p)
1427{
1428 struct mv88e6xxx_chip *chip = ds->priv;
1429 int err;
1430 u16 reg;
1431 u16 *p = _p;
1432 int i;
1433
1434 regs->version = chip->info->prod_num;
1435
1436 memset(p, 0xff, 32 * sizeof(u16));
1437
1438 mv88e6xxx_reg_lock(chip);
1439
1440 for (i = 0; i < 32; i++) {
1441
1442 err = mv88e6xxx_port_read(chip, port, i, ®);
1443 if (!err)
1444 p[i] = reg;
1445 }
1446
1447 if (chip->info->ops->serdes_get_regs)
1448 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1449
1450 mv88e6xxx_reg_unlock(chip);
1451}
1452
1453static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1454 struct ethtool_eee *e)
1455{
1456 /* Nothing to do on the port's MAC */
1457 return 0;
1458}
1459
1460static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1461 struct ethtool_eee *e)
1462{
1463 /* Nothing to do on the port's MAC */
1464 return 0;
1465}
1466
1467/* Mask of the local ports allowed to receive frames from a given fabric port */
1468static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1469{
1470 struct dsa_switch *ds = chip->ds;
1471 struct dsa_switch_tree *dst = ds->dst;
1472 struct dsa_port *dp, *other_dp;
1473 bool found = false;
1474 u16 pvlan;
1475
1476 /* dev is a physical switch */
1477 if (dev <= dst->last_switch) {
1478 list_for_each_entry(dp, &dst->ports, list) {
1479 if (dp->ds->index == dev && dp->index == port) {
1480 /* dp might be a DSA link or a user port, so it
1481 * might or might not have a bridge.
1482 * Use the "found" variable for both cases.
1483 */
1484 found = true;
1485 break;
1486 }
1487 }
1488 /* dev is a virtual bridge */
1489 } else {
1490 list_for_each_entry(dp, &dst->ports, list) {
1491 unsigned int bridge_num = dsa_port_bridge_num_get(dp);
1492
1493 if (!bridge_num)
1494 continue;
1495
1496 if (bridge_num + dst->last_switch != dev)
1497 continue;
1498
1499 found = true;
1500 break;
1501 }
1502 }
1503
1504 /* Prevent frames from unknown switch or virtual bridge */
1505 if (!found)
1506 return 0;
1507
1508 /* Frames from DSA links and CPU ports can egress any local port */
1509 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1510 return mv88e6xxx_port_mask(chip);
1511
1512 pvlan = 0;
1513
1514 /* Frames from standalone user ports can only egress on the
1515 * upstream port.
1516 */
1517 if (!dsa_port_bridge_dev_get(dp))
1518 return BIT(dsa_switch_upstream_port(ds));
1519
1520 /* Frames from bridged user ports can egress any local DSA
1521 * links and CPU ports, as well as any local member of their
1522 * bridge group.
1523 */
1524 dsa_switch_for_each_port(other_dp, ds)
1525 if (other_dp->type == DSA_PORT_TYPE_CPU ||
1526 other_dp->type == DSA_PORT_TYPE_DSA ||
1527 dsa_port_bridge_same(dp, other_dp))
1528 pvlan |= BIT(other_dp->index);
1529
1530 return pvlan;
1531}
1532
1533static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1534{
1535 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1536
1537 /* prevent frames from going back out of the port they came in on */
1538 output_ports &= ~BIT(port);
1539
1540 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1541}
1542
1543static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1544 u8 state)
1545{
1546 struct mv88e6xxx_chip *chip = ds->priv;
1547 int err;
1548
1549 mv88e6xxx_reg_lock(chip);
1550 err = mv88e6xxx_port_set_state(chip, port, state);
1551 mv88e6xxx_reg_unlock(chip);
1552
1553 if (err)
1554 dev_err(ds->dev, "p%d: failed to update state\n", port);
1555}
1556
1557static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1558{
1559 int err;
1560
1561 if (chip->info->ops->ieee_pri_map) {
1562 err = chip->info->ops->ieee_pri_map(chip);
1563 if (err)
1564 return err;
1565 }
1566
1567 if (chip->info->ops->ip_pri_map) {
1568 err = chip->info->ops->ip_pri_map(chip);
1569 if (err)
1570 return err;
1571 }
1572
1573 return 0;
1574}
1575
1576static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1577{
1578 struct dsa_switch *ds = chip->ds;
1579 int target, port;
1580 int err;
1581
1582 if (!chip->info->global2_addr)
1583 return 0;
1584
1585 /* Initialize the routing port to the 32 possible target devices */
1586 for (target = 0; target < 32; target++) {
1587 port = dsa_routing_port(ds, target);
1588 if (port == ds->num_ports)
1589 port = 0x1f;
1590
1591 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1592 if (err)
1593 return err;
1594 }
1595
1596 if (chip->info->ops->set_cascade_port) {
1597 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1598 err = chip->info->ops->set_cascade_port(chip, port);
1599 if (err)
1600 return err;
1601 }
1602
1603 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1604 if (err)
1605 return err;
1606
1607 return 0;
1608}
1609
1610static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1611{
1612 /* Clear all trunk masks and mapping */
1613 if (chip->info->global2_addr)
1614 return mv88e6xxx_g2_trunk_clear(chip);
1615
1616 return 0;
1617}
1618
1619static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1620{
1621 if (chip->info->ops->rmu_disable)
1622 return chip->info->ops->rmu_disable(chip);
1623
1624 return 0;
1625}
1626
1627static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1628{
1629 if (chip->info->ops->pot_clear)
1630 return chip->info->ops->pot_clear(chip);
1631
1632 return 0;
1633}
1634
1635static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1636{
1637 if (chip->info->ops->mgmt_rsvd2cpu)
1638 return chip->info->ops->mgmt_rsvd2cpu(chip);
1639
1640 return 0;
1641}
1642
1643static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1644{
1645 int err;
1646
1647 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1648 if (err)
1649 return err;
1650
1651 /* The chips that have a "learn2all" bit in Global1, ATU
1652 * Control are precisely those whose port registers have a
1653 * Message Port bit in Port Control 1 and hence implement
1654 * ->port_setup_message_port.
1655 */
1656 if (chip->info->ops->port_setup_message_port) {
1657 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1658 if (err)
1659 return err;
1660 }
1661
1662 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1663}
1664
1665static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1666{
1667 int port;
1668 int err;
1669
1670 if (!chip->info->ops->irl_init_all)
1671 return 0;
1672
1673 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1674 /* Disable ingress rate limiting by resetting all per port
1675 * ingress rate limit resources to their initial state.
1676 */
1677 err = chip->info->ops->irl_init_all(chip, port);
1678 if (err)
1679 return err;
1680 }
1681
1682 return 0;
1683}
1684
1685static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1686{
1687 if (chip->info->ops->set_switch_mac) {
1688 u8 addr[ETH_ALEN];
1689
1690 eth_random_addr(addr);
1691
1692 return chip->info->ops->set_switch_mac(chip, addr);
1693 }
1694
1695 return 0;
1696}
1697
1698static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1699{
1700 struct dsa_switch_tree *dst = chip->ds->dst;
1701 struct dsa_switch *ds;
1702 struct dsa_port *dp;
1703 u16 pvlan = 0;
1704
1705 if (!mv88e6xxx_has_pvt(chip))
1706 return 0;
1707
1708 /* Skip the local source device, which uses in-chip port VLAN */
1709 if (dev != chip->ds->index) {
1710 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1711
1712 ds = dsa_switch_find(dst->index, dev);
1713 dp = ds ? dsa_to_port(ds, port) : NULL;
1714 if (dp && dp->lag) {
1715 /* As the PVT is used to limit flooding of
1716 * FORWARD frames, which use the LAG ID as the
1717 * source port, we must translate dev/port to
1718 * the special "LAG device" in the PVT, using
1719 * the LAG ID (one-based) as the port number
1720 * (zero-based).
1721 */
1722 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1723 port = dsa_port_lag_id_get(dp) - 1;
1724 }
1725 }
1726
1727 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1728}
1729
1730static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1731{
1732 int dev, port;
1733 int err;
1734
1735 if (!mv88e6xxx_has_pvt(chip))
1736 return 0;
1737
1738 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1739 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1740 */
1741 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1742 if (err)
1743 return err;
1744
1745 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1746 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1747 err = mv88e6xxx_pvt_map(chip, dev, port);
1748 if (err)
1749 return err;
1750 }
1751 }
1752
1753 return 0;
1754}
1755
1756static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port,
1757 u16 fid)
1758{
1759 if (dsa_to_port(chip->ds, port)->lag)
1760 /* Hardware is incapable of fast-aging a LAG through a
1761 * regular ATU move operation. Until we have something
1762 * more fancy in place this is a no-op.
1763 */
1764 return -EOPNOTSUPP;
1765
1766 return mv88e6xxx_g1_atu_remove(chip, fid, port, false);
1767}
1768
1769static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1770{
1771 struct mv88e6xxx_chip *chip = ds->priv;
1772 int err;
1773
1774 mv88e6xxx_reg_lock(chip);
1775 err = mv88e6xxx_port_fast_age_fid(chip, port, 0);
1776 mv88e6xxx_reg_unlock(chip);
1777
1778 if (err)
1779 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n",
1780 port, err);
1781}
1782
1783static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1784{
1785 if (!mv88e6xxx_max_vid(chip))
1786 return 0;
1787
1788 return mv88e6xxx_g1_vtu_flush(chip);
1789}
1790
1791static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1792 struct mv88e6xxx_vtu_entry *entry)
1793{
1794 int err;
1795
1796 if (!chip->info->ops->vtu_getnext)
1797 return -EOPNOTSUPP;
1798
1799 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1800 entry->valid = false;
1801
1802 err = chip->info->ops->vtu_getnext(chip, entry);
1803
1804 if (entry->vid != vid)
1805 entry->valid = false;
1806
1807 return err;
1808}
1809
1810int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1811 int (*cb)(struct mv88e6xxx_chip *chip,
1812 const struct mv88e6xxx_vtu_entry *entry,
1813 void *priv),
1814 void *priv)
1815{
1816 struct mv88e6xxx_vtu_entry entry = {
1817 .vid = mv88e6xxx_max_vid(chip),
1818 .valid = false,
1819 };
1820 int err;
1821
1822 if (!chip->info->ops->vtu_getnext)
1823 return -EOPNOTSUPP;
1824
1825 do {
1826 err = chip->info->ops->vtu_getnext(chip, &entry);
1827 if (err)
1828 return err;
1829
1830 if (!entry.valid)
1831 break;
1832
1833 err = cb(chip, &entry, priv);
1834 if (err)
1835 return err;
1836 } while (entry.vid < mv88e6xxx_max_vid(chip));
1837
1838 return 0;
1839}
1840
1841static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1842 struct mv88e6xxx_vtu_entry *entry)
1843{
1844 if (!chip->info->ops->vtu_loadpurge)
1845 return -EOPNOTSUPP;
1846
1847 return chip->info->ops->vtu_loadpurge(chip, entry);
1848}
1849
1850static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1851 const struct mv88e6xxx_vtu_entry *entry,
1852 void *_fid_bitmap)
1853{
1854 unsigned long *fid_bitmap = _fid_bitmap;
1855
1856 set_bit(entry->fid, fid_bitmap);
1857 return 0;
1858}
1859
1860int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1861{
1862 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1863
1864 /* Every FID has an associated VID, so walking the VTU
1865 * will discover the full set of FIDs in use.
1866 */
1867 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
1868}
1869
1870static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1871{
1872 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1873 int err;
1874
1875 err = mv88e6xxx_fid_map(chip, fid_bitmap);
1876 if (err)
1877 return err;
1878
1879 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID);
1880 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1881 return -ENOSPC;
1882
1883 /* Clear the database */
1884 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1885}
1886
1887static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1888 struct mv88e6xxx_stu_entry *entry)
1889{
1890 if (!chip->info->ops->stu_loadpurge)
1891 return -EOPNOTSUPP;
1892
1893 return chip->info->ops->stu_loadpurge(chip, entry);
1894}
1895
1896static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip)
1897{
1898 struct mv88e6xxx_stu_entry stu = {
1899 .valid = true,
1900 .sid = 0
1901 };
1902
1903 if (!mv88e6xxx_has_stu(chip))
1904 return 0;
1905
1906 /* Make sure that SID 0 is always valid. This is used by VTU
1907 * entries that do not make use of the STU, e.g. when creating
1908 * a VLAN upper on a port that is also part of a VLAN
1909 * filtering bridge.
1910 */
1911 return mv88e6xxx_stu_loadpurge(chip, &stu);
1912}
1913
1914static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid)
1915{
1916 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 };
1917 struct mv88e6xxx_mst *mst;
1918
1919 __set_bit(0, busy);
1920
1921 list_for_each_entry(mst, &chip->msts, node)
1922 __set_bit(mst->stu.sid, busy);
1923
1924 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID);
1925
1926 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0;
1927}
1928
1929static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid)
1930{
1931 struct mv88e6xxx_mst *mst, *tmp;
1932 int err;
1933
1934 if (!sid)
1935 return 0;
1936
1937 list_for_each_entry_safe(mst, tmp, &chip->msts, node) {
1938 if (mst->stu.sid != sid)
1939 continue;
1940
1941 if (!refcount_dec_and_test(&mst->refcnt))
1942 return 0;
1943
1944 mst->stu.valid = false;
1945 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1946 if (err) {
1947 refcount_set(&mst->refcnt, 1);
1948 return err;
1949 }
1950
1951 list_del(&mst->node);
1952 kfree(mst);
1953 return 0;
1954 }
1955
1956 return -ENOENT;
1957}
1958
1959static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br,
1960 u16 msti, u8 *sid)
1961{
1962 struct mv88e6xxx_mst *mst;
1963 int err, i;
1964
1965 if (!mv88e6xxx_has_stu(chip)) {
1966 err = -EOPNOTSUPP;
1967 goto err;
1968 }
1969
1970 if (!msti) {
1971 *sid = 0;
1972 return 0;
1973 }
1974
1975 list_for_each_entry(mst, &chip->msts, node) {
1976 if (mst->br == br && mst->msti == msti) {
1977 refcount_inc(&mst->refcnt);
1978 *sid = mst->stu.sid;
1979 return 0;
1980 }
1981 }
1982
1983 err = mv88e6xxx_sid_get(chip, sid);
1984 if (err)
1985 goto err;
1986
1987 mst = kzalloc(sizeof(*mst), GFP_KERNEL);
1988 if (!mst) {
1989 err = -ENOMEM;
1990 goto err;
1991 }
1992
1993 INIT_LIST_HEAD(&mst->node);
1994 refcount_set(&mst->refcnt, 1);
1995 mst->br = br;
1996 mst->msti = msti;
1997 mst->stu.valid = true;
1998 mst->stu.sid = *sid;
1999
2000 /* The bridge starts out all ports in the disabled state. But
2001 * a STU state of disabled means to go by the port-global
2002 * state. So we set all user port's initial state to blocking,
2003 * to match the bridge's behavior.
2004 */
2005 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
2006 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ?
2007 MV88E6XXX_PORT_CTL0_STATE_BLOCKING :
2008 MV88E6XXX_PORT_CTL0_STATE_DISABLED;
2009
2010 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2011 if (err)
2012 goto err_free;
2013
2014 list_add_tail(&mst->node, &chip->msts);
2015 return 0;
2016
2017err_free:
2018 kfree(mst);
2019err:
2020 return err;
2021}
2022
2023static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port,
2024 const struct switchdev_mst_state *st)
2025{
2026 struct dsa_port *dp = dsa_to_port(ds, port);
2027 struct mv88e6xxx_chip *chip = ds->priv;
2028 struct mv88e6xxx_mst *mst;
2029 u8 state;
2030 int err;
2031
2032 if (!mv88e6xxx_has_stu(chip))
2033 return -EOPNOTSUPP;
2034
2035 switch (st->state) {
2036 case BR_STATE_DISABLED:
2037 case BR_STATE_BLOCKING:
2038 case BR_STATE_LISTENING:
2039 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
2040 break;
2041 case BR_STATE_LEARNING:
2042 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
2043 break;
2044 case BR_STATE_FORWARDING:
2045 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2046 break;
2047 default:
2048 return -EINVAL;
2049 }
2050
2051 list_for_each_entry(mst, &chip->msts, node) {
2052 if (mst->br == dsa_port_bridge_dev_get(dp) &&
2053 mst->msti == st->msti) {
2054 if (mst->stu.state[port] == state)
2055 return 0;
2056
2057 mst->stu.state[port] = state;
2058 mv88e6xxx_reg_lock(chip);
2059 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2060 mv88e6xxx_reg_unlock(chip);
2061 return err;
2062 }
2063 }
2064
2065 return -ENOENT;
2066}
2067
2068static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
2069 u16 vid)
2070{
2071 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
2072 struct mv88e6xxx_chip *chip = ds->priv;
2073 struct mv88e6xxx_vtu_entry vlan;
2074 int err;
2075
2076 /* DSA and CPU ports have to be members of multiple vlans */
2077 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp))
2078 return 0;
2079
2080 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2081 if (err)
2082 return err;
2083
2084 if (!vlan.valid)
2085 return 0;
2086
2087 dsa_switch_for_each_user_port(other_dp, ds) {
2088 struct net_device *other_br;
2089
2090 if (vlan.member[other_dp->index] ==
2091 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2092 continue;
2093
2094 if (dsa_port_bridge_same(dp, other_dp))
2095 break; /* same bridge, check next VLAN */
2096
2097 other_br = dsa_port_bridge_dev_get(other_dp);
2098 if (!other_br)
2099 continue;
2100
2101 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
2102 port, vlan.vid, other_dp->index, netdev_name(other_br));
2103 return -EOPNOTSUPP;
2104 }
2105
2106 return 0;
2107}
2108
2109static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
2110{
2111 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2112 struct net_device *br = dsa_port_bridge_dev_get(dp);
2113 struct mv88e6xxx_port *p = &chip->ports[port];
2114 u16 pvid = MV88E6XXX_VID_STANDALONE;
2115 bool drop_untagged = false;
2116 int err;
2117
2118 if (br) {
2119 if (br_vlan_enabled(br)) {
2120 pvid = p->bridge_pvid.vid;
2121 drop_untagged = !p->bridge_pvid.valid;
2122 } else {
2123 pvid = MV88E6XXX_VID_BRIDGED;
2124 }
2125 }
2126
2127 err = mv88e6xxx_port_set_pvid(chip, port, pvid);
2128 if (err)
2129 return err;
2130
2131 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
2132}
2133
2134static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2135 bool vlan_filtering,
2136 struct netlink_ext_ack *extack)
2137{
2138 struct mv88e6xxx_chip *chip = ds->priv;
2139 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
2140 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
2141 int err;
2142
2143 if (!mv88e6xxx_max_vid(chip))
2144 return -EOPNOTSUPP;
2145
2146 mv88e6xxx_reg_lock(chip);
2147
2148 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
2149 if (err)
2150 goto unlock;
2151
2152 err = mv88e6xxx_port_commit_pvid(chip, port);
2153 if (err)
2154 goto unlock;
2155
2156unlock:
2157 mv88e6xxx_reg_unlock(chip);
2158
2159 return err;
2160}
2161
2162static int
2163mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2164 const struct switchdev_obj_port_vlan *vlan)
2165{
2166 struct mv88e6xxx_chip *chip = ds->priv;
2167 int err;
2168
2169 if (!mv88e6xxx_max_vid(chip))
2170 return -EOPNOTSUPP;
2171
2172 /* If the requested port doesn't belong to the same bridge as the VLAN
2173 * members, do not support it (yet) and fallback to software VLAN.
2174 */
2175 mv88e6xxx_reg_lock(chip);
2176 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
2177 mv88e6xxx_reg_unlock(chip);
2178
2179 return err;
2180}
2181
2182static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2183 const unsigned char *addr, u16 vid,
2184 u8 state)
2185{
2186 struct mv88e6xxx_atu_entry entry;
2187 struct mv88e6xxx_vtu_entry vlan;
2188 u16 fid;
2189 int err;
2190
2191 /* Ports have two private address databases: one for when the port is
2192 * standalone and one for when the port is under a bridge and the
2193 * 802.1Q mode is disabled. When the port is standalone, DSA wants its
2194 * address database to remain 100% empty, so we never load an ATU entry
2195 * into a standalone port's database. Therefore, translate the null
2196 * VLAN ID into the port's database used for VLAN-unaware bridging.
2197 */
2198 if (vid == 0) {
2199 fid = MV88E6XXX_FID_BRIDGED;
2200 } else {
2201 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2202 if (err)
2203 return err;
2204
2205 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
2206 if (!vlan.valid)
2207 return -EOPNOTSUPP;
2208
2209 fid = vlan.fid;
2210 }
2211
2212 entry.state = 0;
2213 ether_addr_copy(entry.mac, addr);
2214 eth_addr_dec(entry.mac);
2215
2216 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
2217 if (err)
2218 return err;
2219
2220 /* Initialize a fresh ATU entry if it isn't found */
2221 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
2222 memset(&entry, 0, sizeof(entry));
2223 ether_addr_copy(entry.mac, addr);
2224 }
2225
2226 /* Purge the ATU entry only if no port is using it anymore */
2227 if (!state) {
2228 entry.portvec &= ~BIT(port);
2229 if (!entry.portvec)
2230 entry.state = 0;
2231 } else {
2232 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
2233 entry.portvec = BIT(port);
2234 else
2235 entry.portvec |= BIT(port);
2236
2237 entry.state = state;
2238 }
2239
2240 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
2241}
2242
2243static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
2244 const struct mv88e6xxx_policy *policy)
2245{
2246 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
2247 enum mv88e6xxx_policy_action action = policy->action;
2248 const u8 *addr = policy->addr;
2249 u16 vid = policy->vid;
2250 u8 state;
2251 int err;
2252 int id;
2253
2254 if (!chip->info->ops->port_set_policy)
2255 return -EOPNOTSUPP;
2256
2257 switch (mapping) {
2258 case MV88E6XXX_POLICY_MAPPING_DA:
2259 case MV88E6XXX_POLICY_MAPPING_SA:
2260 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2261 state = 0; /* Dissociate the port and address */
2262 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2263 is_multicast_ether_addr(addr))
2264 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
2265 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2266 is_unicast_ether_addr(addr))
2267 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
2268 else
2269 return -EOPNOTSUPP;
2270
2271 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2272 state);
2273 if (err)
2274 return err;
2275 break;
2276 default:
2277 return -EOPNOTSUPP;
2278 }
2279
2280 /* Skip the port's policy clearing if the mapping is still in use */
2281 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2282 idr_for_each_entry(&chip->policies, policy, id)
2283 if (policy->port == port &&
2284 policy->mapping == mapping &&
2285 policy->action != action)
2286 return 0;
2287
2288 return chip->info->ops->port_set_policy(chip, port, mapping, action);
2289}
2290
2291static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
2292 struct ethtool_rx_flow_spec *fs)
2293{
2294 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
2295 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
2296 enum mv88e6xxx_policy_mapping mapping;
2297 enum mv88e6xxx_policy_action action;
2298 struct mv88e6xxx_policy *policy;
2299 u16 vid = 0;
2300 u8 *addr;
2301 int err;
2302 int id;
2303
2304 if (fs->location != RX_CLS_LOC_ANY)
2305 return -EINVAL;
2306
2307 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
2308 action = MV88E6XXX_POLICY_ACTION_DISCARD;
2309 else
2310 return -EOPNOTSUPP;
2311
2312 switch (fs->flow_type & ~FLOW_EXT) {
2313 case ETHER_FLOW:
2314 if (!is_zero_ether_addr(mac_mask->h_dest) &&
2315 is_zero_ether_addr(mac_mask->h_source)) {
2316 mapping = MV88E6XXX_POLICY_MAPPING_DA;
2317 addr = mac_entry->h_dest;
2318 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
2319 !is_zero_ether_addr(mac_mask->h_source)) {
2320 mapping = MV88E6XXX_POLICY_MAPPING_SA;
2321 addr = mac_entry->h_source;
2322 } else {
2323 /* Cannot support DA and SA mapping in the same rule */
2324 return -EOPNOTSUPP;
2325 }
2326 break;
2327 default:
2328 return -EOPNOTSUPP;
2329 }
2330
2331 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
2332 if (fs->m_ext.vlan_tci != htons(0xffff))
2333 return -EOPNOTSUPP;
2334 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
2335 }
2336
2337 idr_for_each_entry(&chip->policies, policy, id) {
2338 if (policy->port == port && policy->mapping == mapping &&
2339 policy->action == action && policy->vid == vid &&
2340 ether_addr_equal(policy->addr, addr))
2341 return -EEXIST;
2342 }
2343
2344 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
2345 if (!policy)
2346 return -ENOMEM;
2347
2348 fs->location = 0;
2349 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
2350 GFP_KERNEL);
2351 if (err) {
2352 devm_kfree(chip->dev, policy);
2353 return err;
2354 }
2355
2356 memcpy(&policy->fs, fs, sizeof(*fs));
2357 ether_addr_copy(policy->addr, addr);
2358 policy->mapping = mapping;
2359 policy->action = action;
2360 policy->port = port;
2361 policy->vid = vid;
2362
2363 err = mv88e6xxx_policy_apply(chip, port, policy);
2364 if (err) {
2365 idr_remove(&chip->policies, fs->location);
2366 devm_kfree(chip->dev, policy);
2367 return err;
2368 }
2369
2370 return 0;
2371}
2372
2373static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
2374 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
2375{
2376 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2377 struct mv88e6xxx_chip *chip = ds->priv;
2378 struct mv88e6xxx_policy *policy;
2379 int err;
2380 int id;
2381
2382 mv88e6xxx_reg_lock(chip);
2383
2384 switch (rxnfc->cmd) {
2385 case ETHTOOL_GRXCLSRLCNT:
2386 rxnfc->data = 0;
2387 rxnfc->data |= RX_CLS_LOC_SPECIAL;
2388 rxnfc->rule_cnt = 0;
2389 idr_for_each_entry(&chip->policies, policy, id)
2390 if (policy->port == port)
2391 rxnfc->rule_cnt++;
2392 err = 0;
2393 break;
2394 case ETHTOOL_GRXCLSRULE:
2395 err = -ENOENT;
2396 policy = idr_find(&chip->policies, fs->location);
2397 if (policy) {
2398 memcpy(fs, &policy->fs, sizeof(*fs));
2399 err = 0;
2400 }
2401 break;
2402 case ETHTOOL_GRXCLSRLALL:
2403 rxnfc->data = 0;
2404 rxnfc->rule_cnt = 0;
2405 idr_for_each_entry(&chip->policies, policy, id)
2406 if (policy->port == port)
2407 rule_locs[rxnfc->rule_cnt++] = id;
2408 err = 0;
2409 break;
2410 default:
2411 err = -EOPNOTSUPP;
2412 break;
2413 }
2414
2415 mv88e6xxx_reg_unlock(chip);
2416
2417 return err;
2418}
2419
2420static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
2421 struct ethtool_rxnfc *rxnfc)
2422{
2423 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2424 struct mv88e6xxx_chip *chip = ds->priv;
2425 struct mv88e6xxx_policy *policy;
2426 int err;
2427
2428 mv88e6xxx_reg_lock(chip);
2429
2430 switch (rxnfc->cmd) {
2431 case ETHTOOL_SRXCLSRLINS:
2432 err = mv88e6xxx_policy_insert(chip, port, fs);
2433 break;
2434 case ETHTOOL_SRXCLSRLDEL:
2435 err = -ENOENT;
2436 policy = idr_remove(&chip->policies, fs->location);
2437 if (policy) {
2438 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
2439 err = mv88e6xxx_policy_apply(chip, port, policy);
2440 devm_kfree(chip->dev, policy);
2441 }
2442 break;
2443 default:
2444 err = -EOPNOTSUPP;
2445 break;
2446 }
2447
2448 mv88e6xxx_reg_unlock(chip);
2449
2450 return err;
2451}
2452
2453static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
2454 u16 vid)
2455{
2456 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2457 u8 broadcast[ETH_ALEN];
2458
2459 eth_broadcast_addr(broadcast);
2460
2461 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
2462}
2463
2464static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
2465{
2466 int port;
2467 int err;
2468
2469 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2470 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2471 struct net_device *brport;
2472
2473 if (dsa_is_unused_port(chip->ds, port))
2474 continue;
2475
2476 brport = dsa_port_to_bridge_port(dp);
2477 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
2478 /* Skip bridged user ports where broadcast
2479 * flooding is disabled.
2480 */
2481 continue;
2482
2483 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2484 if (err)
2485 return err;
2486 }
2487
2488 return 0;
2489}
2490
2491struct mv88e6xxx_port_broadcast_sync_ctx {
2492 int port;
2493 bool flood;
2494};
2495
2496static int
2497mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2498 const struct mv88e6xxx_vtu_entry *vlan,
2499 void *_ctx)
2500{
2501 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2502 u8 broadcast[ETH_ALEN];
2503 u8 state;
2504
2505 if (ctx->flood)
2506 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2507 else
2508 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2509
2510 eth_broadcast_addr(broadcast);
2511
2512 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2513 vlan->vid, state);
2514}
2515
2516static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2517 bool flood)
2518{
2519 struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2520 .port = port,
2521 .flood = flood,
2522 };
2523 struct mv88e6xxx_vtu_entry vid0 = {
2524 .vid = 0,
2525 };
2526 int err;
2527
2528 /* Update the port's private database... */
2529 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2530 if (err)
2531 return err;
2532
2533 /* ...and the database for all VLANs. */
2534 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2535 &ctx);
2536}
2537
2538static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2539 u16 vid, u8 member, bool warn)
2540{
2541 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2542 struct mv88e6xxx_vtu_entry vlan;
2543 int i, err;
2544
2545 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2546 if (err)
2547 return err;
2548
2549 if (!vlan.valid) {
2550 memset(&vlan, 0, sizeof(vlan));
2551
2552 if (vid == MV88E6XXX_VID_STANDALONE)
2553 vlan.policy = true;
2554
2555 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2556 if (err)
2557 return err;
2558
2559 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2560 if (i == port)
2561 vlan.member[i] = member;
2562 else
2563 vlan.member[i] = non_member;
2564
2565 vlan.vid = vid;
2566 vlan.valid = true;
2567
2568 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2569 if (err)
2570 return err;
2571
2572 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2573 if (err)
2574 return err;
2575 } else if (vlan.member[port] != member) {
2576 vlan.member[port] = member;
2577
2578 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2579 if (err)
2580 return err;
2581 } else if (warn) {
2582 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2583 port, vid);
2584 }
2585
2586 return 0;
2587}
2588
2589static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2590 const struct switchdev_obj_port_vlan *vlan,
2591 struct netlink_ext_ack *extack)
2592{
2593 struct mv88e6xxx_chip *chip = ds->priv;
2594 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2595 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2596 struct mv88e6xxx_port *p = &chip->ports[port];
2597 bool warn;
2598 u8 member;
2599 int err;
2600
2601 if (!vlan->vid)
2602 return 0;
2603
2604 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2605 if (err)
2606 return err;
2607
2608 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2609 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2610 else if (untagged)
2611 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2612 else
2613 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2614
2615 /* net/dsa/user.c will call dsa_port_vlan_add() for the affected port
2616 * and then the CPU port. Do not warn for duplicates for the CPU port.
2617 */
2618 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2619
2620 mv88e6xxx_reg_lock(chip);
2621
2622 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2623 if (err) {
2624 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2625 vlan->vid, untagged ? 'u' : 't');
2626 goto out;
2627 }
2628
2629 if (pvid) {
2630 p->bridge_pvid.vid = vlan->vid;
2631 p->bridge_pvid.valid = true;
2632
2633 err = mv88e6xxx_port_commit_pvid(chip, port);
2634 if (err)
2635 goto out;
2636 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) {
2637 /* The old pvid was reinstalled as a non-pvid VLAN */
2638 p->bridge_pvid.valid = false;
2639
2640 err = mv88e6xxx_port_commit_pvid(chip, port);
2641 if (err)
2642 goto out;
2643 }
2644
2645out:
2646 mv88e6xxx_reg_unlock(chip);
2647
2648 return err;
2649}
2650
2651static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2652 int port, u16 vid)
2653{
2654 struct mv88e6xxx_vtu_entry vlan;
2655 int i, err;
2656
2657 if (!vid)
2658 return 0;
2659
2660 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2661 if (err)
2662 return err;
2663
2664 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2665 * tell switchdev that this VLAN is likely handled in software.
2666 */
2667 if (!vlan.valid ||
2668 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2669 return -EOPNOTSUPP;
2670
2671 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2672
2673 /* keep the VLAN unless all ports are excluded */
2674 vlan.valid = false;
2675 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2676 if (vlan.member[i] !=
2677 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2678 vlan.valid = true;
2679 break;
2680 }
2681 }
2682
2683 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2684 if (err)
2685 return err;
2686
2687 if (!vlan.valid) {
2688 err = mv88e6xxx_mst_put(chip, vlan.sid);
2689 if (err)
2690 return err;
2691 }
2692
2693 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2694}
2695
2696static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2697 const struct switchdev_obj_port_vlan *vlan)
2698{
2699 struct mv88e6xxx_chip *chip = ds->priv;
2700 struct mv88e6xxx_port *p = &chip->ports[port];
2701 int err = 0;
2702 u16 pvid;
2703
2704 if (!mv88e6xxx_max_vid(chip))
2705 return -EOPNOTSUPP;
2706
2707 /* The ATU removal procedure needs the FID to be mapped in the VTU,
2708 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA
2709 * switchdev workqueue to ensure that all FDB entries are deleted
2710 * before we remove the VLAN.
2711 */
2712 dsa_flush_workqueue();
2713
2714 mv88e6xxx_reg_lock(chip);
2715
2716 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2717 if (err)
2718 goto unlock;
2719
2720 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2721 if (err)
2722 goto unlock;
2723
2724 if (vlan->vid == pvid) {
2725 p->bridge_pvid.valid = false;
2726
2727 err = mv88e6xxx_port_commit_pvid(chip, port);
2728 if (err)
2729 goto unlock;
2730 }
2731
2732unlock:
2733 mv88e6xxx_reg_unlock(chip);
2734
2735 return err;
2736}
2737
2738static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid)
2739{
2740 struct mv88e6xxx_chip *chip = ds->priv;
2741 struct mv88e6xxx_vtu_entry vlan;
2742 int err;
2743
2744 mv88e6xxx_reg_lock(chip);
2745
2746 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2747 if (err)
2748 goto unlock;
2749
2750 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid);
2751
2752unlock:
2753 mv88e6xxx_reg_unlock(chip);
2754
2755 return err;
2756}
2757
2758static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds,
2759 struct dsa_bridge bridge,
2760 const struct switchdev_vlan_msti *msti)
2761{
2762 struct mv88e6xxx_chip *chip = ds->priv;
2763 struct mv88e6xxx_vtu_entry vlan;
2764 u8 old_sid, new_sid;
2765 int err;
2766
2767 if (!mv88e6xxx_has_stu(chip))
2768 return -EOPNOTSUPP;
2769
2770 mv88e6xxx_reg_lock(chip);
2771
2772 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan);
2773 if (err)
2774 goto unlock;
2775
2776 if (!vlan.valid) {
2777 err = -EINVAL;
2778 goto unlock;
2779 }
2780
2781 old_sid = vlan.sid;
2782
2783 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid);
2784 if (err)
2785 goto unlock;
2786
2787 if (new_sid != old_sid) {
2788 vlan.sid = new_sid;
2789
2790 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2791 if (err) {
2792 mv88e6xxx_mst_put(chip, new_sid);
2793 goto unlock;
2794 }
2795 }
2796
2797 err = mv88e6xxx_mst_put(chip, old_sid);
2798
2799unlock:
2800 mv88e6xxx_reg_unlock(chip);
2801 return err;
2802}
2803
2804static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2805 const unsigned char *addr, u16 vid,
2806 struct dsa_db db)
2807{
2808 struct mv88e6xxx_chip *chip = ds->priv;
2809 int err;
2810
2811 mv88e6xxx_reg_lock(chip);
2812 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2813 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2814 mv88e6xxx_reg_unlock(chip);
2815
2816 return err;
2817}
2818
2819static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2820 const unsigned char *addr, u16 vid,
2821 struct dsa_db db)
2822{
2823 struct mv88e6xxx_chip *chip = ds->priv;
2824 int err;
2825
2826 mv88e6xxx_reg_lock(chip);
2827 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2828 mv88e6xxx_reg_unlock(chip);
2829
2830 return err;
2831}
2832
2833static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2834 u16 fid, u16 vid, int port,
2835 dsa_fdb_dump_cb_t *cb, void *data)
2836{
2837 struct mv88e6xxx_atu_entry addr;
2838 bool is_static;
2839 int err;
2840
2841 addr.state = 0;
2842 eth_broadcast_addr(addr.mac);
2843
2844 do {
2845 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2846 if (err)
2847 return err;
2848
2849 if (!addr.state)
2850 break;
2851
2852 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2853 continue;
2854
2855 if (!is_unicast_ether_addr(addr.mac))
2856 continue;
2857
2858 is_static = (addr.state ==
2859 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2860 err = cb(addr.mac, vid, is_static, data);
2861 if (err)
2862 return err;
2863 } while (!is_broadcast_ether_addr(addr.mac));
2864
2865 return err;
2866}
2867
2868struct mv88e6xxx_port_db_dump_vlan_ctx {
2869 int port;
2870 dsa_fdb_dump_cb_t *cb;
2871 void *data;
2872};
2873
2874static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2875 const struct mv88e6xxx_vtu_entry *entry,
2876 void *_data)
2877{
2878 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2879
2880 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2881 ctx->port, ctx->cb, ctx->data);
2882}
2883
2884static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2885 dsa_fdb_dump_cb_t *cb, void *data)
2886{
2887 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2888 .port = port,
2889 .cb = cb,
2890 .data = data,
2891 };
2892 u16 fid;
2893 int err;
2894
2895 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2896 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2897 if (err)
2898 return err;
2899
2900 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2901 if (err)
2902 return err;
2903
2904 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
2905}
2906
2907static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2908 dsa_fdb_dump_cb_t *cb, void *data)
2909{
2910 struct mv88e6xxx_chip *chip = ds->priv;
2911 int err;
2912
2913 mv88e6xxx_reg_lock(chip);
2914 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2915 mv88e6xxx_reg_unlock(chip);
2916
2917 return err;
2918}
2919
2920static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2921 struct dsa_bridge bridge)
2922{
2923 struct dsa_switch *ds = chip->ds;
2924 struct dsa_switch_tree *dst = ds->dst;
2925 struct dsa_port *dp;
2926 int err;
2927
2928 list_for_each_entry(dp, &dst->ports, list) {
2929 if (dsa_port_offloads_bridge(dp, &bridge)) {
2930 if (dp->ds == ds) {
2931 /* This is a local bridge group member,
2932 * remap its Port VLAN Map.
2933 */
2934 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2935 if (err)
2936 return err;
2937 } else {
2938 /* This is an external bridge group member,
2939 * remap its cross-chip Port VLAN Table entry.
2940 */
2941 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2942 dp->index);
2943 if (err)
2944 return err;
2945 }
2946 }
2947 }
2948
2949 return 0;
2950}
2951
2952/* Treat the software bridge as a virtual single-port switch behind the
2953 * CPU and map in the PVT. First dst->last_switch elements are taken by
2954 * physical switches, so start from beyond that range.
2955 */
2956static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
2957 unsigned int bridge_num)
2958{
2959 u8 dev = bridge_num + ds->dst->last_switch;
2960 struct mv88e6xxx_chip *chip = ds->priv;
2961
2962 return mv88e6xxx_pvt_map(chip, dev, 0);
2963}
2964
2965static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2966 struct dsa_bridge bridge,
2967 bool *tx_fwd_offload,
2968 struct netlink_ext_ack *extack)
2969{
2970 struct mv88e6xxx_chip *chip = ds->priv;
2971 int err;
2972
2973 mv88e6xxx_reg_lock(chip);
2974
2975 err = mv88e6xxx_bridge_map(chip, bridge);
2976 if (err)
2977 goto unlock;
2978
2979 err = mv88e6xxx_port_set_map_da(chip, port, true);
2980 if (err)
2981 goto unlock;
2982
2983 err = mv88e6xxx_port_commit_pvid(chip, port);
2984 if (err)
2985 goto unlock;
2986
2987 if (mv88e6xxx_has_pvt(chip)) {
2988 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
2989 if (err)
2990 goto unlock;
2991
2992 *tx_fwd_offload = true;
2993 }
2994
2995unlock:
2996 mv88e6xxx_reg_unlock(chip);
2997
2998 return err;
2999}
3000
3001static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
3002 struct dsa_bridge bridge)
3003{
3004 struct mv88e6xxx_chip *chip = ds->priv;
3005 int err;
3006
3007 mv88e6xxx_reg_lock(chip);
3008
3009 if (bridge.tx_fwd_offload &&
3010 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
3011 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3012
3013 if (mv88e6xxx_bridge_map(chip, bridge) ||
3014 mv88e6xxx_port_vlan_map(chip, port))
3015 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
3016
3017 err = mv88e6xxx_port_set_map_da(chip, port, false);
3018 if (err)
3019 dev_err(ds->dev,
3020 "port %d failed to restore map-DA: %pe\n",
3021 port, ERR_PTR(err));
3022
3023 err = mv88e6xxx_port_commit_pvid(chip, port);
3024 if (err)
3025 dev_err(ds->dev,
3026 "port %d failed to restore standalone pvid: %pe\n",
3027 port, ERR_PTR(err));
3028
3029 mv88e6xxx_reg_unlock(chip);
3030}
3031
3032static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
3033 int tree_index, int sw_index,
3034 int port, struct dsa_bridge bridge,
3035 struct netlink_ext_ack *extack)
3036{
3037 struct mv88e6xxx_chip *chip = ds->priv;
3038 int err;
3039
3040 if (tree_index != ds->dst->index)
3041 return 0;
3042
3043 mv88e6xxx_reg_lock(chip);
3044 err = mv88e6xxx_pvt_map(chip, sw_index, port);
3045 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
3046 mv88e6xxx_reg_unlock(chip);
3047
3048 return err;
3049}
3050
3051static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
3052 int tree_index, int sw_index,
3053 int port, struct dsa_bridge bridge)
3054{
3055 struct mv88e6xxx_chip *chip = ds->priv;
3056
3057 if (tree_index != ds->dst->index)
3058 return;
3059
3060 mv88e6xxx_reg_lock(chip);
3061 if (mv88e6xxx_pvt_map(chip, sw_index, port) ||
3062 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
3063 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3064 mv88e6xxx_reg_unlock(chip);
3065}
3066
3067static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
3068{
3069 if (chip->info->ops->reset)
3070 return chip->info->ops->reset(chip);
3071
3072 return 0;
3073}
3074
3075static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
3076{
3077 struct gpio_desc *gpiod = chip->reset;
3078
3079 /* If there is a GPIO connected to the reset pin, toggle it */
3080 if (gpiod) {
3081 /* If the switch has just been reset and not yet completed
3082 * loading EEPROM, the reset may interrupt the I2C transaction
3083 * mid-byte, causing the first EEPROM read after the reset
3084 * from the wrong location resulting in the switch booting
3085 * to wrong mode and inoperable.
3086 */
3087 if (chip->info->ops->get_eeprom)
3088 mv88e6xxx_g2_eeprom_wait(chip);
3089
3090 gpiod_set_value_cansleep(gpiod, 1);
3091 usleep_range(10000, 20000);
3092 gpiod_set_value_cansleep(gpiod, 0);
3093 usleep_range(10000, 20000);
3094
3095 if (chip->info->ops->get_eeprom)
3096 mv88e6xxx_g2_eeprom_wait(chip);
3097 }
3098}
3099
3100static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
3101{
3102 int i, err;
3103
3104 /* Set all ports to the Disabled state */
3105 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3106 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
3107 if (err)
3108 return err;
3109 }
3110
3111 /* Wait for transmit queues to drain,
3112 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
3113 */
3114 usleep_range(2000, 4000);
3115
3116 return 0;
3117}
3118
3119static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
3120{
3121 int err;
3122
3123 err = mv88e6xxx_disable_ports(chip);
3124 if (err)
3125 return err;
3126
3127 mv88e6xxx_hardware_reset(chip);
3128
3129 return mv88e6xxx_software_reset(chip);
3130}
3131
3132static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
3133 enum mv88e6xxx_frame_mode frame,
3134 enum mv88e6xxx_egress_mode egress, u16 etype)
3135{
3136 int err;
3137
3138 if (!chip->info->ops->port_set_frame_mode)
3139 return -EOPNOTSUPP;
3140
3141 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
3142 if (err)
3143 return err;
3144
3145 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
3146 if (err)
3147 return err;
3148
3149 if (chip->info->ops->port_set_ether_type)
3150 return chip->info->ops->port_set_ether_type(chip, port, etype);
3151
3152 return 0;
3153}
3154
3155static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
3156{
3157 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
3158 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3159 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3160}
3161
3162static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
3163{
3164 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
3165 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3166 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3167}
3168
3169static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
3170{
3171 return mv88e6xxx_set_port_mode(chip, port,
3172 MV88E6XXX_FRAME_MODE_ETHERTYPE,
3173 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
3174 ETH_P_EDSA);
3175}
3176
3177static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
3178{
3179 if (dsa_is_dsa_port(chip->ds, port))
3180 return mv88e6xxx_set_port_mode_dsa(chip, port);
3181
3182 if (dsa_is_user_port(chip->ds, port))
3183 return mv88e6xxx_set_port_mode_normal(chip, port);
3184
3185 /* Setup CPU port mode depending on its supported tag format */
3186 if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
3187 return mv88e6xxx_set_port_mode_dsa(chip, port);
3188
3189 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
3190 return mv88e6xxx_set_port_mode_edsa(chip, port);
3191
3192 return -EINVAL;
3193}
3194
3195static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
3196{
3197 bool message = dsa_is_dsa_port(chip->ds, port);
3198
3199 return mv88e6xxx_port_set_message_port(chip, port, message);
3200}
3201
3202static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
3203{
3204 int err;
3205
3206 if (chip->info->ops->port_set_ucast_flood) {
3207 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
3208 if (err)
3209 return err;
3210 }
3211 if (chip->info->ops->port_set_mcast_flood) {
3212 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
3213 if (err)
3214 return err;
3215 }
3216
3217 return 0;
3218}
3219
3220static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
3221 enum mv88e6xxx_egress_direction direction,
3222 int port)
3223{
3224 int err;
3225
3226 if (!chip->info->ops->set_egress_port)
3227 return -EOPNOTSUPP;
3228
3229 err = chip->info->ops->set_egress_port(chip, direction, port);
3230 if (err)
3231 return err;
3232
3233 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
3234 chip->ingress_dest_port = port;
3235 else
3236 chip->egress_dest_port = port;
3237
3238 return 0;
3239}
3240
3241static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
3242{
3243 struct dsa_switch *ds = chip->ds;
3244 int upstream_port;
3245 int err;
3246
3247 upstream_port = dsa_upstream_port(ds, port);
3248 if (chip->info->ops->port_set_upstream_port) {
3249 err = chip->info->ops->port_set_upstream_port(chip, port,
3250 upstream_port);
3251 if (err)
3252 return err;
3253 }
3254
3255 if (port == upstream_port) {
3256 if (chip->info->ops->set_cpu_port) {
3257 err = chip->info->ops->set_cpu_port(chip,
3258 upstream_port);
3259 if (err)
3260 return err;
3261 }
3262
3263 err = mv88e6xxx_set_egress_port(chip,
3264 MV88E6XXX_EGRESS_DIR_INGRESS,
3265 upstream_port);
3266 if (err && err != -EOPNOTSUPP)
3267 return err;
3268
3269 err = mv88e6xxx_set_egress_port(chip,
3270 MV88E6XXX_EGRESS_DIR_EGRESS,
3271 upstream_port);
3272 if (err && err != -EOPNOTSUPP)
3273 return err;
3274 }
3275
3276 return 0;
3277}
3278
3279static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
3280{
3281 struct device_node *phy_handle = NULL;
3282 struct dsa_switch *ds = chip->ds;
3283 struct dsa_port *dp;
3284 int tx_amp;
3285 int err;
3286 u16 reg;
3287
3288 chip->ports[port].chip = chip;
3289 chip->ports[port].port = port;
3290
3291 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
3292 SPEED_UNFORCED, DUPLEX_UNFORCED,
3293 PAUSE_ON, PHY_INTERFACE_MODE_NA);
3294 if (err)
3295 return err;
3296
3297 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
3298 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
3299 * tunneling, determine priority by looking at 802.1p and IP
3300 * priority fields (IP prio has precedence), and set STP state
3301 * to Forwarding.
3302 *
3303 * If this is the CPU link, use DSA or EDSA tagging depending
3304 * on which tagging mode was configured.
3305 *
3306 * If this is a link to another switch, use DSA tagging mode.
3307 *
3308 * If this is the upstream port for this switch, enable
3309 * forwarding of unknown unicasts and multicasts.
3310 */
3311 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
3312 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
3313 /* Forward any IPv4 IGMP or IPv6 MLD frames received
3314 * by a USER port to the CPU port to allow snooping.
3315 */
3316 if (dsa_is_user_port(ds, port))
3317 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP;
3318
3319 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
3320 if (err)
3321 return err;
3322
3323 err = mv88e6xxx_setup_port_mode(chip, port);
3324 if (err)
3325 return err;
3326
3327 err = mv88e6xxx_setup_egress_floods(chip, port);
3328 if (err)
3329 return err;
3330
3331 /* Port Control 2: don't force a good FCS, set the MTU size to
3332 * 10222 bytes, disable 802.1q tags checking, don't discard
3333 * tagged or untagged frames on this port, skip destination
3334 * address lookup on user ports, disable ARP mirroring and don't
3335 * send a copy of all transmitted/received frames on this port
3336 * to the CPU.
3337 */
3338 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port));
3339 if (err)
3340 return err;
3341
3342 err = mv88e6xxx_setup_upstream_port(chip, port);
3343 if (err)
3344 return err;
3345
3346 /* On chips that support it, set all downstream DSA ports'
3347 * VLAN policy to TRAP. In combination with loading
3348 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this
3349 * provides a better isolation barrier between standalone
3350 * ports, as the ATU is bypassed on any intermediate switches
3351 * between the incoming port and the CPU.
3352 */
3353 if (dsa_is_downstream_port(ds, port) &&
3354 chip->info->ops->port_set_policy) {
3355 err = chip->info->ops->port_set_policy(chip, port,
3356 MV88E6XXX_POLICY_MAPPING_VTU,
3357 MV88E6XXX_POLICY_ACTION_TRAP);
3358 if (err)
3359 return err;
3360 }
3361
3362 /* User ports start out in standalone mode and 802.1Q is
3363 * therefore disabled. On DSA ports, all valid VIDs are always
3364 * loaded in the VTU - therefore, enable 802.1Q in order to take
3365 * advantage of VLAN policy on chips that supports it.
3366 */
3367 err = mv88e6xxx_port_set_8021q_mode(chip, port,
3368 dsa_is_user_port(ds, port) ?
3369 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED :
3370 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE);
3371 if (err)
3372 return err;
3373
3374 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by
3375 * virtue of the fact that mv88e6xxx_atu_new() will pick it as
3376 * the first free FID. This will be used as the private PVID for
3377 * unbridged ports. Shared (DSA and CPU) ports must also be
3378 * members of this VID, in order to trap all frames assigned to
3379 * it to the CPU.
3380 */
3381 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE,
3382 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3383 false);
3384 if (err)
3385 return err;
3386
3387 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the
3388 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as
3389 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used
3390 * as the private PVID on ports under a VLAN-unaware bridge.
3391 * Shared (DSA and CPU) ports must also be members of it, to translate
3392 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of
3393 * relying on their port default FID.
3394 */
3395 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
3396 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3397 false);
3398 if (err)
3399 return err;
3400
3401 if (chip->info->ops->port_set_jumbo_size) {
3402 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
3403 if (err)
3404 return err;
3405 }
3406
3407 /* Port Association Vector: disable automatic address learning
3408 * on all user ports since they start out in standalone
3409 * mode. When joining a bridge, learning will be configured to
3410 * match the bridge port settings. Enable learning on all
3411 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
3412 * learning process.
3413 *
3414 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
3415 * and RefreshLocked. I.e. setup standard automatic learning.
3416 */
3417 if (dsa_is_user_port(ds, port))
3418 reg = 0;
3419 else
3420 reg = 1 << port;
3421
3422 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
3423 reg);
3424 if (err)
3425 return err;
3426
3427 /* Egress rate control 2: disable egress rate control. */
3428 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
3429 0x0000);
3430 if (err)
3431 return err;
3432
3433 if (chip->info->ops->port_pause_limit) {
3434 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
3435 if (err)
3436 return err;
3437 }
3438
3439 if (chip->info->ops->port_disable_learn_limit) {
3440 err = chip->info->ops->port_disable_learn_limit(chip, port);
3441 if (err)
3442 return err;
3443 }
3444
3445 if (chip->info->ops->port_disable_pri_override) {
3446 err = chip->info->ops->port_disable_pri_override(chip, port);
3447 if (err)
3448 return err;
3449 }
3450
3451 if (chip->info->ops->port_tag_remap) {
3452 err = chip->info->ops->port_tag_remap(chip, port);
3453 if (err)
3454 return err;
3455 }
3456
3457 if (chip->info->ops->port_egress_rate_limiting) {
3458 err = chip->info->ops->port_egress_rate_limiting(chip, port);
3459 if (err)
3460 return err;
3461 }
3462
3463 if (chip->info->ops->port_setup_message_port) {
3464 err = chip->info->ops->port_setup_message_port(chip, port);
3465 if (err)
3466 return err;
3467 }
3468
3469 if (chip->info->ops->serdes_set_tx_amplitude) {
3470 dp = dsa_to_port(ds, port);
3471 if (dp)
3472 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0);
3473
3474 if (phy_handle && !of_property_read_u32(phy_handle,
3475 "tx-p2p-microvolt",
3476 &tx_amp))
3477 err = chip->info->ops->serdes_set_tx_amplitude(chip,
3478 port, tx_amp);
3479 if (phy_handle) {
3480 of_node_put(phy_handle);
3481 if (err)
3482 return err;
3483 }
3484 }
3485
3486 /* Port based VLAN map: give each port the same default address
3487 * database, and allow bidirectional communication between the
3488 * CPU and DSA port(s), and the other ports.
3489 */
3490 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
3491 if (err)
3492 return err;
3493
3494 err = mv88e6xxx_port_vlan_map(chip, port);
3495 if (err)
3496 return err;
3497
3498 /* Default VLAN ID and priority: don't set a default VLAN
3499 * ID, and set the default packet priority to zero.
3500 */
3501 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
3502}
3503
3504static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
3505{
3506 struct mv88e6xxx_chip *chip = ds->priv;
3507
3508 if (chip->info->ops->port_set_jumbo_size)
3509 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3510 else if (chip->info->ops->set_max_frame_size)
3511 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3512 return ETH_DATA_LEN;
3513}
3514
3515static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
3516{
3517 struct mv88e6xxx_chip *chip = ds->priv;
3518 int ret = 0;
3519
3520 /* For families where we don't know how to alter the MTU,
3521 * just accept any value up to ETH_DATA_LEN
3522 */
3523 if (!chip->info->ops->port_set_jumbo_size &&
3524 !chip->info->ops->set_max_frame_size) {
3525 if (new_mtu > ETH_DATA_LEN)
3526 return -EINVAL;
3527
3528 return 0;
3529 }
3530
3531 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
3532 new_mtu += EDSA_HLEN;
3533
3534 mv88e6xxx_reg_lock(chip);
3535 if (chip->info->ops->port_set_jumbo_size)
3536 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
3537 else if (chip->info->ops->set_max_frame_size)
3538 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
3539 mv88e6xxx_reg_unlock(chip);
3540
3541 return ret;
3542}
3543
3544static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
3545 unsigned int ageing_time)
3546{
3547 struct mv88e6xxx_chip *chip = ds->priv;
3548 int err;
3549
3550 mv88e6xxx_reg_lock(chip);
3551 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
3552 mv88e6xxx_reg_unlock(chip);
3553
3554 return err;
3555}
3556
3557static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
3558{
3559 int err;
3560
3561 /* Initialize the statistics unit */
3562 if (chip->info->ops->stats_set_histogram) {
3563 err = chip->info->ops->stats_set_histogram(chip);
3564 if (err)
3565 return err;
3566 }
3567
3568 return mv88e6xxx_g1_stats_clear(chip);
3569}
3570
3571/* Check if the errata has already been applied. */
3572static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3573{
3574 int port;
3575 int err;
3576 u16 val;
3577
3578 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3579 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
3580 if (err) {
3581 dev_err(chip->dev,
3582 "Error reading hidden register: %d\n", err);
3583 return false;
3584 }
3585 if (val != 0x01c0)
3586 return false;
3587 }
3588
3589 return true;
3590}
3591
3592/* The 6390 copper ports have an errata which require poking magic
3593 * values into undocumented hidden registers and then performing a
3594 * software reset.
3595 */
3596static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3597{
3598 int port;
3599 int err;
3600
3601 if (mv88e6390_setup_errata_applied(chip))
3602 return 0;
3603
3604 /* Set the ports into blocking mode */
3605 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3606 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3607 if (err)
3608 return err;
3609 }
3610
3611 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3612 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3613 if (err)
3614 return err;
3615 }
3616
3617 return mv88e6xxx_software_reset(chip);
3618}
3619
3620/* prod_id for switch families which do not have a PHY model number */
3621static const u16 family_prod_id_table[] = {
3622 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3623 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3624 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
3625};
3626
3627static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3628{
3629 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3630 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3631 u16 prod_id;
3632 u16 val;
3633 int err;
3634
3635 if (!chip->info->ops->phy_read)
3636 return -EOPNOTSUPP;
3637
3638 mv88e6xxx_reg_lock(chip);
3639 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3640 mv88e6xxx_reg_unlock(chip);
3641
3642 /* Some internal PHYs don't have a model number. */
3643 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3644 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3645 prod_id = family_prod_id_table[chip->info->family];
3646 if (prod_id)
3647 val |= prod_id >> 4;
3648 }
3649
3650 return err ? err : val;
3651}
3652
3653static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad,
3654 int reg)
3655{
3656 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3657 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3658 u16 val;
3659 int err;
3660
3661 if (!chip->info->ops->phy_read_c45)
3662 return 0xffff;
3663
3664 mv88e6xxx_reg_lock(chip);
3665 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val);
3666 mv88e6xxx_reg_unlock(chip);
3667
3668 return err ? err : val;
3669}
3670
3671static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3672{
3673 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3674 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3675 int err;
3676
3677 if (!chip->info->ops->phy_write)
3678 return -EOPNOTSUPP;
3679
3680 mv88e6xxx_reg_lock(chip);
3681 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3682 mv88e6xxx_reg_unlock(chip);
3683
3684 return err;
3685}
3686
3687static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad,
3688 int reg, u16 val)
3689{
3690 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3691 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3692 int err;
3693
3694 if (!chip->info->ops->phy_write_c45)
3695 return -EOPNOTSUPP;
3696
3697 mv88e6xxx_reg_lock(chip);
3698 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val);
3699 mv88e6xxx_reg_unlock(chip);
3700
3701 return err;
3702}
3703
3704static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3705 struct device_node *np,
3706 bool external)
3707{
3708 static int index;
3709 struct mv88e6xxx_mdio_bus *mdio_bus;
3710 struct mii_bus *bus;
3711 int err;
3712
3713 if (external) {
3714 mv88e6xxx_reg_lock(chip);
3715 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3716 mv88e6xxx_reg_unlock(chip);
3717
3718 if (err)
3719 return err;
3720 }
3721
3722 bus = mdiobus_alloc_size(sizeof(*mdio_bus));
3723 if (!bus)
3724 return -ENOMEM;
3725
3726 mdio_bus = bus->priv;
3727 mdio_bus->bus = bus;
3728 mdio_bus->chip = chip;
3729 INIT_LIST_HEAD(&mdio_bus->list);
3730 mdio_bus->external = external;
3731
3732 if (np) {
3733 bus->name = np->full_name;
3734 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3735 } else {
3736 bus->name = "mv88e6xxx SMI";
3737 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3738 }
3739
3740 bus->read = mv88e6xxx_mdio_read;
3741 bus->write = mv88e6xxx_mdio_write;
3742 bus->read_c45 = mv88e6xxx_mdio_read_c45;
3743 bus->write_c45 = mv88e6xxx_mdio_write_c45;
3744 bus->parent = chip->dev;
3745 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr +
3746 mv88e6xxx_num_ports(chip) - 1,
3747 chip->info->phy_base_addr);
3748
3749 if (!external) {
3750 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3751 if (err)
3752 goto out;
3753 }
3754
3755 err = of_mdiobus_register(bus, np);
3756 if (err) {
3757 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3758 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3759 goto out;
3760 }
3761
3762 if (external)
3763 list_add_tail(&mdio_bus->list, &chip->mdios);
3764 else
3765 list_add(&mdio_bus->list, &chip->mdios);
3766
3767 return 0;
3768
3769out:
3770 mdiobus_free(bus);
3771 return err;
3772}
3773
3774static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3775
3776{
3777 struct mv88e6xxx_mdio_bus *mdio_bus, *p;
3778 struct mii_bus *bus;
3779
3780 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) {
3781 bus = mdio_bus->bus;
3782
3783 if (!mdio_bus->external)
3784 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3785
3786 mdiobus_unregister(bus);
3787 mdiobus_free(bus);
3788 }
3789}
3790
3791static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip)
3792{
3793 struct device_node *np = chip->dev->of_node;
3794 struct device_node *child;
3795 int err;
3796
3797 /* Always register one mdio bus for the internal/default mdio
3798 * bus. This maybe represented in the device tree, but is
3799 * optional.
3800 */
3801 child = of_get_child_by_name(np, "mdio");
3802 err = mv88e6xxx_mdio_register(chip, child, false);
3803 of_node_put(child);
3804 if (err)
3805 return err;
3806
3807 /* Walk the device tree, and see if there are any other nodes
3808 * which say they are compatible with the external mdio
3809 * bus.
3810 */
3811 for_each_available_child_of_node(np, child) {
3812 if (of_device_is_compatible(
3813 child, "marvell,mv88e6xxx-mdio-external")) {
3814 err = mv88e6xxx_mdio_register(chip, child, true);
3815 if (err) {
3816 mv88e6xxx_mdios_unregister(chip);
3817 of_node_put(child);
3818 return err;
3819 }
3820 }
3821 }
3822
3823 return 0;
3824}
3825
3826static void mv88e6xxx_teardown(struct dsa_switch *ds)
3827{
3828 struct mv88e6xxx_chip *chip = ds->priv;
3829
3830 mv88e6xxx_teardown_devlink_params(ds);
3831 dsa_devlink_resources_unregister(ds);
3832 mv88e6xxx_teardown_devlink_regions_global(ds);
3833 mv88e6xxx_mdios_unregister(chip);
3834}
3835
3836static int mv88e6xxx_setup(struct dsa_switch *ds)
3837{
3838 struct mv88e6xxx_chip *chip = ds->priv;
3839 u8 cmode;
3840 int err;
3841 int i;
3842
3843 err = mv88e6xxx_mdios_register(chip);
3844 if (err)
3845 return err;
3846
3847 chip->ds = ds;
3848 ds->user_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3849
3850 /* Since virtual bridges are mapped in the PVT, the number we support
3851 * depends on the physical switch topology. We need to let DSA figure
3852 * that out and therefore we cannot set this at dsa_register_switch()
3853 * time.
3854 */
3855 if (mv88e6xxx_has_pvt(chip))
3856 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
3857 ds->dst->last_switch - 1;
3858
3859 mv88e6xxx_reg_lock(chip);
3860
3861 if (chip->info->ops->setup_errata) {
3862 err = chip->info->ops->setup_errata(chip);
3863 if (err)
3864 goto unlock;
3865 }
3866
3867 /* Cache the cmode of each port. */
3868 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3869 if (chip->info->ops->port_get_cmode) {
3870 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3871 if (err)
3872 goto unlock;
3873
3874 chip->ports[i].cmode = cmode;
3875 }
3876 }
3877
3878 err = mv88e6xxx_vtu_setup(chip);
3879 if (err)
3880 goto unlock;
3881
3882 /* Must be called after mv88e6xxx_vtu_setup (which flushes the
3883 * VTU, thereby also flushing the STU).
3884 */
3885 err = mv88e6xxx_stu_setup(chip);
3886 if (err)
3887 goto unlock;
3888
3889 /* Setup Switch Port Registers */
3890 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3891 if (dsa_is_unused_port(ds, i))
3892 continue;
3893
3894 /* Prevent the use of an invalid port. */
3895 if (mv88e6xxx_is_invalid_port(chip, i)) {
3896 dev_err(chip->dev, "port %d is invalid\n", i);
3897 err = -EINVAL;
3898 goto unlock;
3899 }
3900
3901 err = mv88e6xxx_setup_port(chip, i);
3902 if (err)
3903 goto unlock;
3904 }
3905
3906 err = mv88e6xxx_irl_setup(chip);
3907 if (err)
3908 goto unlock;
3909
3910 err = mv88e6xxx_mac_setup(chip);
3911 if (err)
3912 goto unlock;
3913
3914 err = mv88e6xxx_phy_setup(chip);
3915 if (err)
3916 goto unlock;
3917
3918 err = mv88e6xxx_pvt_setup(chip);
3919 if (err)
3920 goto unlock;
3921
3922 err = mv88e6xxx_atu_setup(chip);
3923 if (err)
3924 goto unlock;
3925
3926 err = mv88e6xxx_broadcast_setup(chip, 0);
3927 if (err)
3928 goto unlock;
3929
3930 err = mv88e6xxx_pot_setup(chip);
3931 if (err)
3932 goto unlock;
3933
3934 err = mv88e6xxx_rmu_setup(chip);
3935 if (err)
3936 goto unlock;
3937
3938 err = mv88e6xxx_rsvd2cpu_setup(chip);
3939 if (err)
3940 goto unlock;
3941
3942 err = mv88e6xxx_trunk_setup(chip);
3943 if (err)
3944 goto unlock;
3945
3946 err = mv88e6xxx_devmap_setup(chip);
3947 if (err)
3948 goto unlock;
3949
3950 err = mv88e6xxx_pri_setup(chip);
3951 if (err)
3952 goto unlock;
3953
3954 /* Setup PTP Hardware Clock and timestamping */
3955 if (chip->info->ptp_support) {
3956 err = mv88e6xxx_ptp_setup(chip);
3957 if (err)
3958 goto unlock;
3959
3960 err = mv88e6xxx_hwtstamp_setup(chip);
3961 if (err)
3962 goto unlock;
3963 }
3964
3965 err = mv88e6xxx_stats_setup(chip);
3966 if (err)
3967 goto unlock;
3968
3969unlock:
3970 mv88e6xxx_reg_unlock(chip);
3971
3972 if (err)
3973 goto out_mdios;
3974
3975 /* Have to be called without holding the register lock, since
3976 * they take the devlink lock, and we later take the locks in
3977 * the reverse order when getting/setting parameters or
3978 * resource occupancy.
3979 */
3980 err = mv88e6xxx_setup_devlink_resources(ds);
3981 if (err)
3982 goto out_mdios;
3983
3984 err = mv88e6xxx_setup_devlink_params(ds);
3985 if (err)
3986 goto out_resources;
3987
3988 err = mv88e6xxx_setup_devlink_regions_global(ds);
3989 if (err)
3990 goto out_params;
3991
3992 return 0;
3993
3994out_params:
3995 mv88e6xxx_teardown_devlink_params(ds);
3996out_resources:
3997 dsa_devlink_resources_unregister(ds);
3998out_mdios:
3999 mv88e6xxx_mdios_unregister(chip);
4000
4001 return err;
4002}
4003
4004static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
4005{
4006 struct mv88e6xxx_chip *chip = ds->priv;
4007 int err;
4008
4009 if (chip->info->ops->pcs_ops &&
4010 chip->info->ops->pcs_ops->pcs_init) {
4011 err = chip->info->ops->pcs_ops->pcs_init(chip, port);
4012 if (err)
4013 return err;
4014 }
4015
4016 return mv88e6xxx_setup_devlink_regions_port(ds, port);
4017}
4018
4019static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
4020{
4021 struct mv88e6xxx_chip *chip = ds->priv;
4022
4023 mv88e6xxx_teardown_devlink_regions_port(ds, port);
4024
4025 if (chip->info->ops->pcs_ops &&
4026 chip->info->ops->pcs_ops->pcs_teardown)
4027 chip->info->ops->pcs_ops->pcs_teardown(chip, port);
4028}
4029
4030static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
4031{
4032 struct mv88e6xxx_chip *chip = ds->priv;
4033
4034 return chip->eeprom_len;
4035}
4036
4037static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
4038 struct ethtool_eeprom *eeprom, u8 *data)
4039{
4040 struct mv88e6xxx_chip *chip = ds->priv;
4041 int err;
4042
4043 if (!chip->info->ops->get_eeprom)
4044 return -EOPNOTSUPP;
4045
4046 mv88e6xxx_reg_lock(chip);
4047 err = chip->info->ops->get_eeprom(chip, eeprom, data);
4048 mv88e6xxx_reg_unlock(chip);
4049
4050 if (err)
4051 return err;
4052
4053 eeprom->magic = 0xc3ec4951;
4054
4055 return 0;
4056}
4057
4058static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
4059 struct ethtool_eeprom *eeprom, u8 *data)
4060{
4061 struct mv88e6xxx_chip *chip = ds->priv;
4062 int err;
4063
4064 if (!chip->info->ops->set_eeprom)
4065 return -EOPNOTSUPP;
4066
4067 if (eeprom->magic != 0xc3ec4951)
4068 return -EINVAL;
4069
4070 mv88e6xxx_reg_lock(chip);
4071 err = chip->info->ops->set_eeprom(chip, eeprom, data);
4072 mv88e6xxx_reg_unlock(chip);
4073
4074 return err;
4075}
4076
4077static const struct mv88e6xxx_ops mv88e6085_ops = {
4078 /* MV88E6XXX_FAMILY_6097 */
4079 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4080 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4081 .irl_init_all = mv88e6352_g2_irl_init_all,
4082 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4083 .phy_read = mv88e6185_phy_ppu_read,
4084 .phy_write = mv88e6185_phy_ppu_write,
4085 .port_set_link = mv88e6xxx_port_set_link,
4086 .port_sync_link = mv88e6xxx_port_sync_link,
4087 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4088 .port_tag_remap = mv88e6095_port_tag_remap,
4089 .port_set_policy = mv88e6352_port_set_policy,
4090 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4091 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4092 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4093 .port_set_ether_type = mv88e6351_port_set_ether_type,
4094 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4095 .port_pause_limit = mv88e6097_port_pause_limit,
4096 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4097 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4098 .port_get_cmode = mv88e6185_port_get_cmode,
4099 .port_setup_message_port = mv88e6xxx_setup_message_port,
4100 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4101 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4102 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4103 .stats_get_strings = mv88e6095_stats_get_strings,
4104 .stats_get_stat = mv88e6095_stats_get_stat,
4105 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4106 .set_egress_port = mv88e6095_g1_set_egress_port,
4107 .watchdog_ops = &mv88e6097_watchdog_ops,
4108 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4109 .pot_clear = mv88e6xxx_g2_pot_clear,
4110 .ppu_enable = mv88e6185_g1_ppu_enable,
4111 .ppu_disable = mv88e6185_g1_ppu_disable,
4112 .reset = mv88e6185_g1_reset,
4113 .rmu_disable = mv88e6085_g1_rmu_disable,
4114 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4115 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4116 .stu_getnext = mv88e6352_g1_stu_getnext,
4117 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4118 .phylink_get_caps = mv88e6185_phylink_get_caps,
4119 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4120};
4121
4122static const struct mv88e6xxx_ops mv88e6095_ops = {
4123 /* MV88E6XXX_FAMILY_6095 */
4124 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4125 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4126 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4127 .phy_read = mv88e6185_phy_ppu_read,
4128 .phy_write = mv88e6185_phy_ppu_write,
4129 .port_set_link = mv88e6xxx_port_set_link,
4130 .port_sync_link = mv88e6185_port_sync_link,
4131 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4132 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4133 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4134 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4135 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4136 .port_get_cmode = mv88e6185_port_get_cmode,
4137 .port_setup_message_port = mv88e6xxx_setup_message_port,
4138 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4139 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4140 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4141 .stats_get_strings = mv88e6095_stats_get_strings,
4142 .stats_get_stat = mv88e6095_stats_get_stat,
4143 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4144 .ppu_enable = mv88e6185_g1_ppu_enable,
4145 .ppu_disable = mv88e6185_g1_ppu_disable,
4146 .reset = mv88e6185_g1_reset,
4147 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4148 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4149 .phylink_get_caps = mv88e6095_phylink_get_caps,
4150 .pcs_ops = &mv88e6185_pcs_ops,
4151 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4152};
4153
4154static const struct mv88e6xxx_ops mv88e6097_ops = {
4155 /* MV88E6XXX_FAMILY_6097 */
4156 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4157 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4158 .irl_init_all = mv88e6352_g2_irl_init_all,
4159 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4160 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4161 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4162 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4163 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4164 .port_set_link = mv88e6xxx_port_set_link,
4165 .port_sync_link = mv88e6185_port_sync_link,
4166 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4167 .port_tag_remap = mv88e6095_port_tag_remap,
4168 .port_set_policy = mv88e6352_port_set_policy,
4169 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4170 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4171 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4172 .port_set_ether_type = mv88e6351_port_set_ether_type,
4173 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4174 .port_pause_limit = mv88e6097_port_pause_limit,
4175 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4176 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4177 .port_get_cmode = mv88e6185_port_get_cmode,
4178 .port_setup_message_port = mv88e6xxx_setup_message_port,
4179 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4180 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4181 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4182 .stats_get_strings = mv88e6095_stats_get_strings,
4183 .stats_get_stat = mv88e6095_stats_get_stat,
4184 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4185 .set_egress_port = mv88e6095_g1_set_egress_port,
4186 .watchdog_ops = &mv88e6097_watchdog_ops,
4187 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4188 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4189 .pot_clear = mv88e6xxx_g2_pot_clear,
4190 .reset = mv88e6352_g1_reset,
4191 .rmu_disable = mv88e6085_g1_rmu_disable,
4192 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4193 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4194 .phylink_get_caps = mv88e6095_phylink_get_caps,
4195 .pcs_ops = &mv88e6185_pcs_ops,
4196 .stu_getnext = mv88e6352_g1_stu_getnext,
4197 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4198 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4199};
4200
4201static const struct mv88e6xxx_ops mv88e6123_ops = {
4202 /* MV88E6XXX_FAMILY_6165 */
4203 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4204 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4205 .irl_init_all = mv88e6352_g2_irl_init_all,
4206 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4207 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4208 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4209 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4210 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4211 .port_set_link = mv88e6xxx_port_set_link,
4212 .port_sync_link = mv88e6xxx_port_sync_link,
4213 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4214 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4215 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4216 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4217 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4218 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4219 .port_get_cmode = mv88e6185_port_get_cmode,
4220 .port_setup_message_port = mv88e6xxx_setup_message_port,
4221 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4222 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4223 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4224 .stats_get_strings = mv88e6095_stats_get_strings,
4225 .stats_get_stat = mv88e6095_stats_get_stat,
4226 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4227 .set_egress_port = mv88e6095_g1_set_egress_port,
4228 .watchdog_ops = &mv88e6097_watchdog_ops,
4229 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4230 .pot_clear = mv88e6xxx_g2_pot_clear,
4231 .reset = mv88e6352_g1_reset,
4232 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4233 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4234 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4235 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4236 .stu_getnext = mv88e6352_g1_stu_getnext,
4237 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4238 .phylink_get_caps = mv88e6185_phylink_get_caps,
4239 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4240};
4241
4242static const struct mv88e6xxx_ops mv88e6131_ops = {
4243 /* MV88E6XXX_FAMILY_6185 */
4244 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4245 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4246 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4247 .phy_read = mv88e6185_phy_ppu_read,
4248 .phy_write = mv88e6185_phy_ppu_write,
4249 .port_set_link = mv88e6xxx_port_set_link,
4250 .port_sync_link = mv88e6xxx_port_sync_link,
4251 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4252 .port_tag_remap = mv88e6095_port_tag_remap,
4253 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4254 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4255 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4256 .port_set_ether_type = mv88e6351_port_set_ether_type,
4257 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4258 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4259 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4260 .port_pause_limit = mv88e6097_port_pause_limit,
4261 .port_set_pause = mv88e6185_port_set_pause,
4262 .port_get_cmode = mv88e6185_port_get_cmode,
4263 .port_setup_message_port = mv88e6xxx_setup_message_port,
4264 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4265 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4266 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4267 .stats_get_strings = mv88e6095_stats_get_strings,
4268 .stats_get_stat = mv88e6095_stats_get_stat,
4269 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4270 .set_egress_port = mv88e6095_g1_set_egress_port,
4271 .watchdog_ops = &mv88e6097_watchdog_ops,
4272 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4273 .ppu_enable = mv88e6185_g1_ppu_enable,
4274 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4275 .ppu_disable = mv88e6185_g1_ppu_disable,
4276 .reset = mv88e6185_g1_reset,
4277 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4278 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4279 .phylink_get_caps = mv88e6185_phylink_get_caps,
4280};
4281
4282static const struct mv88e6xxx_ops mv88e6141_ops = {
4283 /* MV88E6XXX_FAMILY_6341 */
4284 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4285 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4286 .irl_init_all = mv88e6352_g2_irl_init_all,
4287 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4288 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4289 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4290 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4291 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4292 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4293 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4294 .port_set_link = mv88e6xxx_port_set_link,
4295 .port_sync_link = mv88e6xxx_port_sync_link,
4296 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4297 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4298 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4299 .port_tag_remap = mv88e6095_port_tag_remap,
4300 .port_set_policy = mv88e6352_port_set_policy,
4301 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4302 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4303 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4304 .port_set_ether_type = mv88e6351_port_set_ether_type,
4305 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4306 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4307 .port_pause_limit = mv88e6097_port_pause_limit,
4308 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4309 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4310 .port_get_cmode = mv88e6352_port_get_cmode,
4311 .port_set_cmode = mv88e6341_port_set_cmode,
4312 .port_setup_message_port = mv88e6xxx_setup_message_port,
4313 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4314 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4315 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4316 .stats_get_strings = mv88e6320_stats_get_strings,
4317 .stats_get_stat = mv88e6390_stats_get_stat,
4318 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4319 .set_egress_port = mv88e6390_g1_set_egress_port,
4320 .watchdog_ops = &mv88e6390_watchdog_ops,
4321 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4322 .pot_clear = mv88e6xxx_g2_pot_clear,
4323 .reset = mv88e6352_g1_reset,
4324 .rmu_disable = mv88e6390_g1_rmu_disable,
4325 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4326 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4327 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4328 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4329 .stu_getnext = mv88e6352_g1_stu_getnext,
4330 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4331 .serdes_get_lane = mv88e6341_serdes_get_lane,
4332 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4333 .gpio_ops = &mv88e6352_gpio_ops,
4334 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4335 .serdes_get_strings = mv88e6390_serdes_get_strings,
4336 .serdes_get_stats = mv88e6390_serdes_get_stats,
4337 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4338 .serdes_get_regs = mv88e6390_serdes_get_regs,
4339 .phylink_get_caps = mv88e6341_phylink_get_caps,
4340 .pcs_ops = &mv88e6390_pcs_ops,
4341};
4342
4343static const struct mv88e6xxx_ops mv88e6161_ops = {
4344 /* MV88E6XXX_FAMILY_6165 */
4345 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4346 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4347 .irl_init_all = mv88e6352_g2_irl_init_all,
4348 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4349 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4350 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4351 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4352 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4353 .port_set_link = mv88e6xxx_port_set_link,
4354 .port_sync_link = mv88e6xxx_port_sync_link,
4355 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4356 .port_tag_remap = mv88e6095_port_tag_remap,
4357 .port_set_policy = mv88e6352_port_set_policy,
4358 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4359 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4360 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4361 .port_set_ether_type = mv88e6351_port_set_ether_type,
4362 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4363 .port_pause_limit = mv88e6097_port_pause_limit,
4364 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4365 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4366 .port_get_cmode = mv88e6185_port_get_cmode,
4367 .port_setup_message_port = mv88e6xxx_setup_message_port,
4368 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4369 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4370 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4371 .stats_get_strings = mv88e6095_stats_get_strings,
4372 .stats_get_stat = mv88e6095_stats_get_stat,
4373 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4374 .set_egress_port = mv88e6095_g1_set_egress_port,
4375 .watchdog_ops = &mv88e6097_watchdog_ops,
4376 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4377 .pot_clear = mv88e6xxx_g2_pot_clear,
4378 .reset = mv88e6352_g1_reset,
4379 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4380 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4381 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4382 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4383 .stu_getnext = mv88e6352_g1_stu_getnext,
4384 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4385 .avb_ops = &mv88e6165_avb_ops,
4386 .ptp_ops = &mv88e6165_ptp_ops,
4387 .phylink_get_caps = mv88e6185_phylink_get_caps,
4388 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4389};
4390
4391static const struct mv88e6xxx_ops mv88e6165_ops = {
4392 /* MV88E6XXX_FAMILY_6165 */
4393 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4394 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4395 .irl_init_all = mv88e6352_g2_irl_init_all,
4396 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4397 .phy_read = mv88e6165_phy_read,
4398 .phy_write = mv88e6165_phy_write,
4399 .port_set_link = mv88e6xxx_port_set_link,
4400 .port_sync_link = mv88e6xxx_port_sync_link,
4401 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4402 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4403 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4404 .port_get_cmode = mv88e6185_port_get_cmode,
4405 .port_setup_message_port = mv88e6xxx_setup_message_port,
4406 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4407 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4408 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4409 .stats_get_strings = mv88e6095_stats_get_strings,
4410 .stats_get_stat = mv88e6095_stats_get_stat,
4411 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4412 .set_egress_port = mv88e6095_g1_set_egress_port,
4413 .watchdog_ops = &mv88e6097_watchdog_ops,
4414 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4415 .pot_clear = mv88e6xxx_g2_pot_clear,
4416 .reset = mv88e6352_g1_reset,
4417 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4418 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4419 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4420 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4421 .stu_getnext = mv88e6352_g1_stu_getnext,
4422 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4423 .avb_ops = &mv88e6165_avb_ops,
4424 .ptp_ops = &mv88e6165_ptp_ops,
4425 .phylink_get_caps = mv88e6185_phylink_get_caps,
4426};
4427
4428static const struct mv88e6xxx_ops mv88e6171_ops = {
4429 /* MV88E6XXX_FAMILY_6351 */
4430 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4431 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4432 .irl_init_all = mv88e6352_g2_irl_init_all,
4433 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4434 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4435 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4436 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4437 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4438 .port_set_link = mv88e6xxx_port_set_link,
4439 .port_sync_link = mv88e6xxx_port_sync_link,
4440 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4441 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4442 .port_tag_remap = mv88e6095_port_tag_remap,
4443 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4444 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4445 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4446 .port_set_ether_type = mv88e6351_port_set_ether_type,
4447 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4448 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4449 .port_pause_limit = mv88e6097_port_pause_limit,
4450 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4451 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4452 .port_get_cmode = mv88e6352_port_get_cmode,
4453 .port_setup_message_port = mv88e6xxx_setup_message_port,
4454 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4455 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4456 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4457 .stats_get_strings = mv88e6095_stats_get_strings,
4458 .stats_get_stat = mv88e6095_stats_get_stat,
4459 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4460 .set_egress_port = mv88e6095_g1_set_egress_port,
4461 .watchdog_ops = &mv88e6097_watchdog_ops,
4462 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4463 .pot_clear = mv88e6xxx_g2_pot_clear,
4464 .reset = mv88e6352_g1_reset,
4465 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4466 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4467 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4468 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4469 .stu_getnext = mv88e6352_g1_stu_getnext,
4470 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4471 .phylink_get_caps = mv88e6351_phylink_get_caps,
4472};
4473
4474static const struct mv88e6xxx_ops mv88e6172_ops = {
4475 /* MV88E6XXX_FAMILY_6352 */
4476 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4477 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4478 .irl_init_all = mv88e6352_g2_irl_init_all,
4479 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4480 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4481 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4482 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4483 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4484 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4485 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4486 .port_set_link = mv88e6xxx_port_set_link,
4487 .port_sync_link = mv88e6xxx_port_sync_link,
4488 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4489 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4490 .port_tag_remap = mv88e6095_port_tag_remap,
4491 .port_set_policy = mv88e6352_port_set_policy,
4492 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4493 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4494 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4495 .port_set_ether_type = mv88e6351_port_set_ether_type,
4496 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4497 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4498 .port_pause_limit = mv88e6097_port_pause_limit,
4499 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4500 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4501 .port_get_cmode = mv88e6352_port_get_cmode,
4502 .port_setup_message_port = mv88e6xxx_setup_message_port,
4503 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4504 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4505 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4506 .stats_get_strings = mv88e6095_stats_get_strings,
4507 .stats_get_stat = mv88e6095_stats_get_stat,
4508 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4509 .set_egress_port = mv88e6095_g1_set_egress_port,
4510 .watchdog_ops = &mv88e6097_watchdog_ops,
4511 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4512 .pot_clear = mv88e6xxx_g2_pot_clear,
4513 .reset = mv88e6352_g1_reset,
4514 .rmu_disable = mv88e6352_g1_rmu_disable,
4515 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4516 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4517 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4518 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4519 .stu_getnext = mv88e6352_g1_stu_getnext,
4520 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4521 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4522 .serdes_get_regs = mv88e6352_serdes_get_regs,
4523 .gpio_ops = &mv88e6352_gpio_ops,
4524 .phylink_get_caps = mv88e6352_phylink_get_caps,
4525 .pcs_ops = &mv88e6352_pcs_ops,
4526};
4527
4528static const struct mv88e6xxx_ops mv88e6175_ops = {
4529 /* MV88E6XXX_FAMILY_6351 */
4530 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4531 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4532 .irl_init_all = mv88e6352_g2_irl_init_all,
4533 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4534 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4535 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4536 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4537 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4538 .port_set_link = mv88e6xxx_port_set_link,
4539 .port_sync_link = mv88e6xxx_port_sync_link,
4540 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4541 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4542 .port_tag_remap = mv88e6095_port_tag_remap,
4543 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4544 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4545 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4546 .port_set_ether_type = mv88e6351_port_set_ether_type,
4547 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4548 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4549 .port_pause_limit = mv88e6097_port_pause_limit,
4550 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4551 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4552 .port_get_cmode = mv88e6352_port_get_cmode,
4553 .port_setup_message_port = mv88e6xxx_setup_message_port,
4554 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4555 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4556 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4557 .stats_get_strings = mv88e6095_stats_get_strings,
4558 .stats_get_stat = mv88e6095_stats_get_stat,
4559 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4560 .set_egress_port = mv88e6095_g1_set_egress_port,
4561 .watchdog_ops = &mv88e6097_watchdog_ops,
4562 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4563 .pot_clear = mv88e6xxx_g2_pot_clear,
4564 .reset = mv88e6352_g1_reset,
4565 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4566 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4567 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4568 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4569 .stu_getnext = mv88e6352_g1_stu_getnext,
4570 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4571 .phylink_get_caps = mv88e6351_phylink_get_caps,
4572};
4573
4574static const struct mv88e6xxx_ops mv88e6176_ops = {
4575 /* MV88E6XXX_FAMILY_6352 */
4576 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4577 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4578 .irl_init_all = mv88e6352_g2_irl_init_all,
4579 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4580 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4581 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4582 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4583 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4584 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4585 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4586 .port_set_link = mv88e6xxx_port_set_link,
4587 .port_sync_link = mv88e6xxx_port_sync_link,
4588 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4589 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4590 .port_tag_remap = mv88e6095_port_tag_remap,
4591 .port_set_policy = mv88e6352_port_set_policy,
4592 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4593 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4594 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4595 .port_set_ether_type = mv88e6351_port_set_ether_type,
4596 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4597 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4598 .port_pause_limit = mv88e6097_port_pause_limit,
4599 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4600 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4601 .port_get_cmode = mv88e6352_port_get_cmode,
4602 .port_setup_message_port = mv88e6xxx_setup_message_port,
4603 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4604 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4605 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4606 .stats_get_strings = mv88e6095_stats_get_strings,
4607 .stats_get_stat = mv88e6095_stats_get_stat,
4608 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4609 .set_egress_port = mv88e6095_g1_set_egress_port,
4610 .watchdog_ops = &mv88e6097_watchdog_ops,
4611 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4612 .pot_clear = mv88e6xxx_g2_pot_clear,
4613 .reset = mv88e6352_g1_reset,
4614 .rmu_disable = mv88e6352_g1_rmu_disable,
4615 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4616 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4617 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4618 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4619 .stu_getnext = mv88e6352_g1_stu_getnext,
4620 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4621 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4622 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4623 .serdes_get_regs = mv88e6352_serdes_get_regs,
4624 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4625 .gpio_ops = &mv88e6352_gpio_ops,
4626 .phylink_get_caps = mv88e6352_phylink_get_caps,
4627 .pcs_ops = &mv88e6352_pcs_ops,
4628};
4629
4630static const struct mv88e6xxx_ops mv88e6185_ops = {
4631 /* MV88E6XXX_FAMILY_6185 */
4632 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4633 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4634 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4635 .phy_read = mv88e6185_phy_ppu_read,
4636 .phy_write = mv88e6185_phy_ppu_write,
4637 .port_set_link = mv88e6xxx_port_set_link,
4638 .port_sync_link = mv88e6185_port_sync_link,
4639 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4640 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4641 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4642 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4643 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4644 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4645 .port_set_pause = mv88e6185_port_set_pause,
4646 .port_get_cmode = mv88e6185_port_get_cmode,
4647 .port_setup_message_port = mv88e6xxx_setup_message_port,
4648 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4649 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4650 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4651 .stats_get_strings = mv88e6095_stats_get_strings,
4652 .stats_get_stat = mv88e6095_stats_get_stat,
4653 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4654 .set_egress_port = mv88e6095_g1_set_egress_port,
4655 .watchdog_ops = &mv88e6097_watchdog_ops,
4656 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4657 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4658 .ppu_enable = mv88e6185_g1_ppu_enable,
4659 .ppu_disable = mv88e6185_g1_ppu_disable,
4660 .reset = mv88e6185_g1_reset,
4661 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4662 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4663 .phylink_get_caps = mv88e6185_phylink_get_caps,
4664 .pcs_ops = &mv88e6185_pcs_ops,
4665 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4666};
4667
4668static const struct mv88e6xxx_ops mv88e6190_ops = {
4669 /* MV88E6XXX_FAMILY_6390 */
4670 .setup_errata = mv88e6390_setup_errata,
4671 .irl_init_all = mv88e6390_g2_irl_init_all,
4672 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4673 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4674 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4675 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4676 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4677 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4678 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4679 .port_set_link = mv88e6xxx_port_set_link,
4680 .port_sync_link = mv88e6xxx_port_sync_link,
4681 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4682 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4683 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4684 .port_tag_remap = mv88e6390_port_tag_remap,
4685 .port_set_policy = mv88e6352_port_set_policy,
4686 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4687 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4688 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4689 .port_set_ether_type = mv88e6351_port_set_ether_type,
4690 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4691 .port_pause_limit = mv88e6390_port_pause_limit,
4692 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4693 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4694 .port_get_cmode = mv88e6352_port_get_cmode,
4695 .port_set_cmode = mv88e6390_port_set_cmode,
4696 .port_setup_message_port = mv88e6xxx_setup_message_port,
4697 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4698 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4699 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4700 .stats_get_strings = mv88e6320_stats_get_strings,
4701 .stats_get_stat = mv88e6390_stats_get_stat,
4702 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4703 .set_egress_port = mv88e6390_g1_set_egress_port,
4704 .watchdog_ops = &mv88e6390_watchdog_ops,
4705 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4706 .pot_clear = mv88e6xxx_g2_pot_clear,
4707 .reset = mv88e6352_g1_reset,
4708 .rmu_disable = mv88e6390_g1_rmu_disable,
4709 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4710 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4711 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4712 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4713 .stu_getnext = mv88e6390_g1_stu_getnext,
4714 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4715 .serdes_get_lane = mv88e6390_serdes_get_lane,
4716 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4717 .serdes_get_strings = mv88e6390_serdes_get_strings,
4718 .serdes_get_stats = mv88e6390_serdes_get_stats,
4719 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4720 .serdes_get_regs = mv88e6390_serdes_get_regs,
4721 .gpio_ops = &mv88e6352_gpio_ops,
4722 .phylink_get_caps = mv88e6390_phylink_get_caps,
4723 .pcs_ops = &mv88e6390_pcs_ops,
4724};
4725
4726static const struct mv88e6xxx_ops mv88e6190x_ops = {
4727 /* MV88E6XXX_FAMILY_6390 */
4728 .setup_errata = mv88e6390_setup_errata,
4729 .irl_init_all = mv88e6390_g2_irl_init_all,
4730 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4731 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4732 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4733 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4734 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4735 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4736 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4737 .port_set_link = mv88e6xxx_port_set_link,
4738 .port_sync_link = mv88e6xxx_port_sync_link,
4739 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4740 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4741 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4742 .port_tag_remap = mv88e6390_port_tag_remap,
4743 .port_set_policy = mv88e6352_port_set_policy,
4744 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4745 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4746 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4747 .port_set_ether_type = mv88e6351_port_set_ether_type,
4748 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4749 .port_pause_limit = mv88e6390_port_pause_limit,
4750 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4751 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4752 .port_get_cmode = mv88e6352_port_get_cmode,
4753 .port_set_cmode = mv88e6390x_port_set_cmode,
4754 .port_setup_message_port = mv88e6xxx_setup_message_port,
4755 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4756 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4757 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4758 .stats_get_strings = mv88e6320_stats_get_strings,
4759 .stats_get_stat = mv88e6390_stats_get_stat,
4760 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4761 .set_egress_port = mv88e6390_g1_set_egress_port,
4762 .watchdog_ops = &mv88e6390_watchdog_ops,
4763 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4764 .pot_clear = mv88e6xxx_g2_pot_clear,
4765 .reset = mv88e6352_g1_reset,
4766 .rmu_disable = mv88e6390_g1_rmu_disable,
4767 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4768 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4769 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4770 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4771 .stu_getnext = mv88e6390_g1_stu_getnext,
4772 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4773 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4774 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4775 .serdes_get_strings = mv88e6390_serdes_get_strings,
4776 .serdes_get_stats = mv88e6390_serdes_get_stats,
4777 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4778 .serdes_get_regs = mv88e6390_serdes_get_regs,
4779 .gpio_ops = &mv88e6352_gpio_ops,
4780 .phylink_get_caps = mv88e6390x_phylink_get_caps,
4781 .pcs_ops = &mv88e6390_pcs_ops,
4782};
4783
4784static const struct mv88e6xxx_ops mv88e6191_ops = {
4785 /* MV88E6XXX_FAMILY_6390 */
4786 .setup_errata = mv88e6390_setup_errata,
4787 .irl_init_all = mv88e6390_g2_irl_init_all,
4788 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4789 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4790 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4791 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4792 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4793 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4794 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4795 .port_set_link = mv88e6xxx_port_set_link,
4796 .port_sync_link = mv88e6xxx_port_sync_link,
4797 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4798 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4799 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4800 .port_tag_remap = mv88e6390_port_tag_remap,
4801 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4802 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4803 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4804 .port_set_ether_type = mv88e6351_port_set_ether_type,
4805 .port_pause_limit = mv88e6390_port_pause_limit,
4806 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4807 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4808 .port_get_cmode = mv88e6352_port_get_cmode,
4809 .port_set_cmode = mv88e6390_port_set_cmode,
4810 .port_setup_message_port = mv88e6xxx_setup_message_port,
4811 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4812 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4813 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4814 .stats_get_strings = mv88e6320_stats_get_strings,
4815 .stats_get_stat = mv88e6390_stats_get_stat,
4816 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4817 .set_egress_port = mv88e6390_g1_set_egress_port,
4818 .watchdog_ops = &mv88e6390_watchdog_ops,
4819 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4820 .pot_clear = mv88e6xxx_g2_pot_clear,
4821 .reset = mv88e6352_g1_reset,
4822 .rmu_disable = mv88e6390_g1_rmu_disable,
4823 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4824 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4825 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4826 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4827 .stu_getnext = mv88e6390_g1_stu_getnext,
4828 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4829 .serdes_get_lane = mv88e6390_serdes_get_lane,
4830 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4831 .serdes_get_strings = mv88e6390_serdes_get_strings,
4832 .serdes_get_stats = mv88e6390_serdes_get_stats,
4833 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4834 .serdes_get_regs = mv88e6390_serdes_get_regs,
4835 .avb_ops = &mv88e6390_avb_ops,
4836 .ptp_ops = &mv88e6352_ptp_ops,
4837 .phylink_get_caps = mv88e6390_phylink_get_caps,
4838 .pcs_ops = &mv88e6390_pcs_ops,
4839};
4840
4841static const struct mv88e6xxx_ops mv88e6240_ops = {
4842 /* MV88E6XXX_FAMILY_6352 */
4843 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4844 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4845 .irl_init_all = mv88e6352_g2_irl_init_all,
4846 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4847 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4848 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4849 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4850 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4851 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4852 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4853 .port_set_link = mv88e6xxx_port_set_link,
4854 .port_sync_link = mv88e6xxx_port_sync_link,
4855 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4856 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4857 .port_tag_remap = mv88e6095_port_tag_remap,
4858 .port_set_policy = mv88e6352_port_set_policy,
4859 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4860 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4861 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4862 .port_set_ether_type = mv88e6351_port_set_ether_type,
4863 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4864 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4865 .port_pause_limit = mv88e6097_port_pause_limit,
4866 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4867 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4868 .port_get_cmode = mv88e6352_port_get_cmode,
4869 .port_setup_message_port = mv88e6xxx_setup_message_port,
4870 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4871 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4872 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4873 .stats_get_strings = mv88e6095_stats_get_strings,
4874 .stats_get_stat = mv88e6095_stats_get_stat,
4875 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4876 .set_egress_port = mv88e6095_g1_set_egress_port,
4877 .watchdog_ops = &mv88e6097_watchdog_ops,
4878 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4879 .pot_clear = mv88e6xxx_g2_pot_clear,
4880 .reset = mv88e6352_g1_reset,
4881 .rmu_disable = mv88e6352_g1_rmu_disable,
4882 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4883 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4884 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4885 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4886 .stu_getnext = mv88e6352_g1_stu_getnext,
4887 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4888 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4889 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4890 .serdes_get_regs = mv88e6352_serdes_get_regs,
4891 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4892 .gpio_ops = &mv88e6352_gpio_ops,
4893 .avb_ops = &mv88e6352_avb_ops,
4894 .ptp_ops = &mv88e6352_ptp_ops,
4895 .phylink_get_caps = mv88e6352_phylink_get_caps,
4896 .pcs_ops = &mv88e6352_pcs_ops,
4897};
4898
4899static const struct mv88e6xxx_ops mv88e6250_ops = {
4900 /* MV88E6XXX_FAMILY_6250 */
4901 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4902 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4903 .irl_init_all = mv88e6352_g2_irl_init_all,
4904 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4905 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4906 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4907 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4908 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4909 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4910 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4911 .port_set_link = mv88e6xxx_port_set_link,
4912 .port_sync_link = mv88e6xxx_port_sync_link,
4913 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4914 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
4915 .port_tag_remap = mv88e6095_port_tag_remap,
4916 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4917 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4918 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4919 .port_set_ether_type = mv88e6351_port_set_ether_type,
4920 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4921 .port_pause_limit = mv88e6097_port_pause_limit,
4922 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4923 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4924 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4925 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4926 .stats_get_strings = mv88e6250_stats_get_strings,
4927 .stats_get_stat = mv88e6250_stats_get_stat,
4928 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4929 .set_egress_port = mv88e6095_g1_set_egress_port,
4930 .watchdog_ops = &mv88e6250_watchdog_ops,
4931 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4932 .pot_clear = mv88e6xxx_g2_pot_clear,
4933 .reset = mv88e6250_g1_reset,
4934 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4935 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4936 .avb_ops = &mv88e6352_avb_ops,
4937 .ptp_ops = &mv88e6250_ptp_ops,
4938 .phylink_get_caps = mv88e6250_phylink_get_caps,
4939 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4940};
4941
4942static const struct mv88e6xxx_ops mv88e6290_ops = {
4943 /* MV88E6XXX_FAMILY_6390 */
4944 .setup_errata = mv88e6390_setup_errata,
4945 .irl_init_all = mv88e6390_g2_irl_init_all,
4946 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4947 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4948 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4949 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4950 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4951 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4952 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4953 .port_set_link = mv88e6xxx_port_set_link,
4954 .port_sync_link = mv88e6xxx_port_sync_link,
4955 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4956 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4957 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4958 .port_tag_remap = mv88e6390_port_tag_remap,
4959 .port_set_policy = mv88e6352_port_set_policy,
4960 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4961 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4962 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4963 .port_set_ether_type = mv88e6351_port_set_ether_type,
4964 .port_pause_limit = mv88e6390_port_pause_limit,
4965 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4966 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4967 .port_get_cmode = mv88e6352_port_get_cmode,
4968 .port_set_cmode = mv88e6390_port_set_cmode,
4969 .port_setup_message_port = mv88e6xxx_setup_message_port,
4970 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4971 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4972 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4973 .stats_get_strings = mv88e6320_stats_get_strings,
4974 .stats_get_stat = mv88e6390_stats_get_stat,
4975 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4976 .set_egress_port = mv88e6390_g1_set_egress_port,
4977 .watchdog_ops = &mv88e6390_watchdog_ops,
4978 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4979 .pot_clear = mv88e6xxx_g2_pot_clear,
4980 .reset = mv88e6352_g1_reset,
4981 .rmu_disable = mv88e6390_g1_rmu_disable,
4982 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4983 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4984 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4985 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4986 .stu_getnext = mv88e6390_g1_stu_getnext,
4987 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4988 .serdes_get_lane = mv88e6390_serdes_get_lane,
4989 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4990 .serdes_get_strings = mv88e6390_serdes_get_strings,
4991 .serdes_get_stats = mv88e6390_serdes_get_stats,
4992 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4993 .serdes_get_regs = mv88e6390_serdes_get_regs,
4994 .gpio_ops = &mv88e6352_gpio_ops,
4995 .avb_ops = &mv88e6390_avb_ops,
4996 .ptp_ops = &mv88e6390_ptp_ops,
4997 .phylink_get_caps = mv88e6390_phylink_get_caps,
4998 .pcs_ops = &mv88e6390_pcs_ops,
4999};
5000
5001static const struct mv88e6xxx_ops mv88e6320_ops = {
5002 /* MV88E6XXX_FAMILY_6320 */
5003 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5004 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5005 .irl_init_all = mv88e6352_g2_irl_init_all,
5006 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5007 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5008 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5009 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5010 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5011 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5012 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5013 .port_set_link = mv88e6xxx_port_set_link,
5014 .port_sync_link = mv88e6xxx_port_sync_link,
5015 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5016 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5017 .port_tag_remap = mv88e6095_port_tag_remap,
5018 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5019 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5020 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5021 .port_set_ether_type = mv88e6351_port_set_ether_type,
5022 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5023 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5024 .port_pause_limit = mv88e6097_port_pause_limit,
5025 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5026 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5027 .port_get_cmode = mv88e6352_port_get_cmode,
5028 .port_setup_message_port = mv88e6xxx_setup_message_port,
5029 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5030 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5031 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5032 .stats_get_strings = mv88e6320_stats_get_strings,
5033 .stats_get_stat = mv88e6320_stats_get_stat,
5034 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5035 .set_egress_port = mv88e6095_g1_set_egress_port,
5036 .watchdog_ops = &mv88e6390_watchdog_ops,
5037 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5038 .pot_clear = mv88e6xxx_g2_pot_clear,
5039 .reset = mv88e6352_g1_reset,
5040 .vtu_getnext = mv88e6185_g1_vtu_getnext,
5041 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5042 .gpio_ops = &mv88e6352_gpio_ops,
5043 .avb_ops = &mv88e6352_avb_ops,
5044 .ptp_ops = &mv88e6352_ptp_ops,
5045 .phylink_get_caps = mv88e6185_phylink_get_caps,
5046};
5047
5048static const struct mv88e6xxx_ops mv88e6321_ops = {
5049 /* MV88E6XXX_FAMILY_6320 */
5050 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5051 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5052 .irl_init_all = mv88e6352_g2_irl_init_all,
5053 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5054 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5055 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5056 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5057 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5058 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5059 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5060 .port_set_link = mv88e6xxx_port_set_link,
5061 .port_sync_link = mv88e6xxx_port_sync_link,
5062 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5063 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5064 .port_tag_remap = mv88e6095_port_tag_remap,
5065 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5066 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5067 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5068 .port_set_ether_type = mv88e6351_port_set_ether_type,
5069 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5070 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5071 .port_pause_limit = mv88e6097_port_pause_limit,
5072 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5073 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5074 .port_get_cmode = mv88e6352_port_get_cmode,
5075 .port_setup_message_port = mv88e6xxx_setup_message_port,
5076 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5077 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5078 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5079 .stats_get_strings = mv88e6320_stats_get_strings,
5080 .stats_get_stat = mv88e6320_stats_get_stat,
5081 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5082 .set_egress_port = mv88e6095_g1_set_egress_port,
5083 .watchdog_ops = &mv88e6390_watchdog_ops,
5084 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5085 .reset = mv88e6352_g1_reset,
5086 .vtu_getnext = mv88e6185_g1_vtu_getnext,
5087 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5088 .gpio_ops = &mv88e6352_gpio_ops,
5089 .avb_ops = &mv88e6352_avb_ops,
5090 .ptp_ops = &mv88e6352_ptp_ops,
5091 .phylink_get_caps = mv88e6185_phylink_get_caps,
5092};
5093
5094static const struct mv88e6xxx_ops mv88e6341_ops = {
5095 /* MV88E6XXX_FAMILY_6341 */
5096 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5097 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5098 .irl_init_all = mv88e6352_g2_irl_init_all,
5099 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5100 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5101 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5102 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5103 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5104 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5105 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5106 .port_set_link = mv88e6xxx_port_set_link,
5107 .port_sync_link = mv88e6xxx_port_sync_link,
5108 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5109 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
5110 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
5111 .port_tag_remap = mv88e6095_port_tag_remap,
5112 .port_set_policy = mv88e6352_port_set_policy,
5113 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5114 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5115 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5116 .port_set_ether_type = mv88e6351_port_set_ether_type,
5117 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5118 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5119 .port_pause_limit = mv88e6097_port_pause_limit,
5120 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5121 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5122 .port_get_cmode = mv88e6352_port_get_cmode,
5123 .port_set_cmode = mv88e6341_port_set_cmode,
5124 .port_setup_message_port = mv88e6xxx_setup_message_port,
5125 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5126 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5127 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5128 .stats_get_strings = mv88e6320_stats_get_strings,
5129 .stats_get_stat = mv88e6390_stats_get_stat,
5130 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5131 .set_egress_port = mv88e6390_g1_set_egress_port,
5132 .watchdog_ops = &mv88e6390_watchdog_ops,
5133 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5134 .pot_clear = mv88e6xxx_g2_pot_clear,
5135 .reset = mv88e6352_g1_reset,
5136 .rmu_disable = mv88e6390_g1_rmu_disable,
5137 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5138 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5139 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5140 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5141 .stu_getnext = mv88e6352_g1_stu_getnext,
5142 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5143 .serdes_get_lane = mv88e6341_serdes_get_lane,
5144 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5145 .gpio_ops = &mv88e6352_gpio_ops,
5146 .avb_ops = &mv88e6390_avb_ops,
5147 .ptp_ops = &mv88e6352_ptp_ops,
5148 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5149 .serdes_get_strings = mv88e6390_serdes_get_strings,
5150 .serdes_get_stats = mv88e6390_serdes_get_stats,
5151 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5152 .serdes_get_regs = mv88e6390_serdes_get_regs,
5153 .phylink_get_caps = mv88e6341_phylink_get_caps,
5154 .pcs_ops = &mv88e6390_pcs_ops,
5155};
5156
5157static const struct mv88e6xxx_ops mv88e6350_ops = {
5158 /* MV88E6XXX_FAMILY_6351 */
5159 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5160 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5161 .irl_init_all = mv88e6352_g2_irl_init_all,
5162 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5163 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5164 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5165 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5166 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5167 .port_set_link = mv88e6xxx_port_set_link,
5168 .port_sync_link = mv88e6xxx_port_sync_link,
5169 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5170 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5171 .port_tag_remap = mv88e6095_port_tag_remap,
5172 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5173 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5174 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5175 .port_set_ether_type = mv88e6351_port_set_ether_type,
5176 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5177 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5178 .port_pause_limit = mv88e6097_port_pause_limit,
5179 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5180 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5181 .port_get_cmode = mv88e6352_port_get_cmode,
5182 .port_setup_message_port = mv88e6xxx_setup_message_port,
5183 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5184 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5185 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5186 .stats_get_strings = mv88e6095_stats_get_strings,
5187 .stats_get_stat = mv88e6095_stats_get_stat,
5188 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5189 .set_egress_port = mv88e6095_g1_set_egress_port,
5190 .watchdog_ops = &mv88e6097_watchdog_ops,
5191 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5192 .pot_clear = mv88e6xxx_g2_pot_clear,
5193 .reset = mv88e6352_g1_reset,
5194 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5195 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5196 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5197 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5198 .stu_getnext = mv88e6352_g1_stu_getnext,
5199 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5200 .phylink_get_caps = mv88e6351_phylink_get_caps,
5201};
5202
5203static const struct mv88e6xxx_ops mv88e6351_ops = {
5204 /* MV88E6XXX_FAMILY_6351 */
5205 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5206 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5207 .irl_init_all = mv88e6352_g2_irl_init_all,
5208 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5209 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5210 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5211 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5212 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5213 .port_set_link = mv88e6xxx_port_set_link,
5214 .port_sync_link = mv88e6xxx_port_sync_link,
5215 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5216 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5217 .port_tag_remap = mv88e6095_port_tag_remap,
5218 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5219 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5220 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5221 .port_set_ether_type = mv88e6351_port_set_ether_type,
5222 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5223 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5224 .port_pause_limit = mv88e6097_port_pause_limit,
5225 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5226 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5227 .port_get_cmode = mv88e6352_port_get_cmode,
5228 .port_setup_message_port = mv88e6xxx_setup_message_port,
5229 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5230 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5231 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5232 .stats_get_strings = mv88e6095_stats_get_strings,
5233 .stats_get_stat = mv88e6095_stats_get_stat,
5234 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5235 .set_egress_port = mv88e6095_g1_set_egress_port,
5236 .watchdog_ops = &mv88e6097_watchdog_ops,
5237 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5238 .pot_clear = mv88e6xxx_g2_pot_clear,
5239 .reset = mv88e6352_g1_reset,
5240 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5241 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5242 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5243 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5244 .stu_getnext = mv88e6352_g1_stu_getnext,
5245 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5246 .avb_ops = &mv88e6352_avb_ops,
5247 .ptp_ops = &mv88e6352_ptp_ops,
5248 .phylink_get_caps = mv88e6351_phylink_get_caps,
5249};
5250
5251static const struct mv88e6xxx_ops mv88e6352_ops = {
5252 /* MV88E6XXX_FAMILY_6352 */
5253 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5254 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5255 .irl_init_all = mv88e6352_g2_irl_init_all,
5256 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5257 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5258 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5259 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5260 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5261 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5262 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5263 .port_set_link = mv88e6xxx_port_set_link,
5264 .port_sync_link = mv88e6xxx_port_sync_link,
5265 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5266 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
5267 .port_tag_remap = mv88e6095_port_tag_remap,
5268 .port_set_policy = mv88e6352_port_set_policy,
5269 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5270 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5271 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5272 .port_set_ether_type = mv88e6351_port_set_ether_type,
5273 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5274 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5275 .port_pause_limit = mv88e6097_port_pause_limit,
5276 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5277 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5278 .port_get_cmode = mv88e6352_port_get_cmode,
5279 .port_setup_message_port = mv88e6xxx_setup_message_port,
5280 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5281 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5282 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5283 .stats_get_strings = mv88e6095_stats_get_strings,
5284 .stats_get_stat = mv88e6095_stats_get_stat,
5285 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5286 .set_egress_port = mv88e6095_g1_set_egress_port,
5287 .watchdog_ops = &mv88e6097_watchdog_ops,
5288 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5289 .pot_clear = mv88e6xxx_g2_pot_clear,
5290 .reset = mv88e6352_g1_reset,
5291 .rmu_disable = mv88e6352_g1_rmu_disable,
5292 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5293 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5294 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5295 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5296 .stu_getnext = mv88e6352_g1_stu_getnext,
5297 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5298 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5299 .gpio_ops = &mv88e6352_gpio_ops,
5300 .avb_ops = &mv88e6352_avb_ops,
5301 .ptp_ops = &mv88e6352_ptp_ops,
5302 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
5303 .serdes_get_strings = mv88e6352_serdes_get_strings,
5304 .serdes_get_stats = mv88e6352_serdes_get_stats,
5305 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5306 .serdes_get_regs = mv88e6352_serdes_get_regs,
5307 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5308 .phylink_get_caps = mv88e6352_phylink_get_caps,
5309 .pcs_ops = &mv88e6352_pcs_ops,
5310};
5311
5312static const struct mv88e6xxx_ops mv88e6390_ops = {
5313 /* MV88E6XXX_FAMILY_6390 */
5314 .setup_errata = mv88e6390_setup_errata,
5315 .irl_init_all = mv88e6390_g2_irl_init_all,
5316 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5317 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5318 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5319 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5320 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5321 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5322 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5323 .port_set_link = mv88e6xxx_port_set_link,
5324 .port_sync_link = mv88e6xxx_port_sync_link,
5325 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5326 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5327 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5328 .port_tag_remap = mv88e6390_port_tag_remap,
5329 .port_set_policy = mv88e6352_port_set_policy,
5330 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5331 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5332 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5333 .port_set_ether_type = mv88e6351_port_set_ether_type,
5334 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5335 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5336 .port_pause_limit = mv88e6390_port_pause_limit,
5337 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5338 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5339 .port_get_cmode = mv88e6352_port_get_cmode,
5340 .port_set_cmode = mv88e6390_port_set_cmode,
5341 .port_setup_message_port = mv88e6xxx_setup_message_port,
5342 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5343 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5344 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5345 .stats_get_strings = mv88e6320_stats_get_strings,
5346 .stats_get_stat = mv88e6390_stats_get_stat,
5347 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5348 .set_egress_port = mv88e6390_g1_set_egress_port,
5349 .watchdog_ops = &mv88e6390_watchdog_ops,
5350 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5351 .pot_clear = mv88e6xxx_g2_pot_clear,
5352 .reset = mv88e6352_g1_reset,
5353 .rmu_disable = mv88e6390_g1_rmu_disable,
5354 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5355 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5356 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5357 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5358 .stu_getnext = mv88e6390_g1_stu_getnext,
5359 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5360 .serdes_get_lane = mv88e6390_serdes_get_lane,
5361 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5362 .gpio_ops = &mv88e6352_gpio_ops,
5363 .avb_ops = &mv88e6390_avb_ops,
5364 .ptp_ops = &mv88e6390_ptp_ops,
5365 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5366 .serdes_get_strings = mv88e6390_serdes_get_strings,
5367 .serdes_get_stats = mv88e6390_serdes_get_stats,
5368 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5369 .serdes_get_regs = mv88e6390_serdes_get_regs,
5370 .phylink_get_caps = mv88e6390_phylink_get_caps,
5371 .pcs_ops = &mv88e6390_pcs_ops,
5372};
5373
5374static const struct mv88e6xxx_ops mv88e6390x_ops = {
5375 /* MV88E6XXX_FAMILY_6390 */
5376 .setup_errata = mv88e6390_setup_errata,
5377 .irl_init_all = mv88e6390_g2_irl_init_all,
5378 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5379 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5380 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5381 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5382 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5383 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5384 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5385 .port_set_link = mv88e6xxx_port_set_link,
5386 .port_sync_link = mv88e6xxx_port_sync_link,
5387 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5388 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
5389 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
5390 .port_tag_remap = mv88e6390_port_tag_remap,
5391 .port_set_policy = mv88e6352_port_set_policy,
5392 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5393 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5394 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5395 .port_set_ether_type = mv88e6351_port_set_ether_type,
5396 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5397 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5398 .port_pause_limit = mv88e6390_port_pause_limit,
5399 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5400 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5401 .port_get_cmode = mv88e6352_port_get_cmode,
5402 .port_set_cmode = mv88e6390x_port_set_cmode,
5403 .port_setup_message_port = mv88e6xxx_setup_message_port,
5404 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5405 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5406 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5407 .stats_get_strings = mv88e6320_stats_get_strings,
5408 .stats_get_stat = mv88e6390_stats_get_stat,
5409 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5410 .set_egress_port = mv88e6390_g1_set_egress_port,
5411 .watchdog_ops = &mv88e6390_watchdog_ops,
5412 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5413 .pot_clear = mv88e6xxx_g2_pot_clear,
5414 .reset = mv88e6352_g1_reset,
5415 .rmu_disable = mv88e6390_g1_rmu_disable,
5416 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5417 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5418 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5419 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5420 .stu_getnext = mv88e6390_g1_stu_getnext,
5421 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5422 .serdes_get_lane = mv88e6390x_serdes_get_lane,
5423 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5424 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5425 .serdes_get_strings = mv88e6390_serdes_get_strings,
5426 .serdes_get_stats = mv88e6390_serdes_get_stats,
5427 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5428 .serdes_get_regs = mv88e6390_serdes_get_regs,
5429 .gpio_ops = &mv88e6352_gpio_ops,
5430 .avb_ops = &mv88e6390_avb_ops,
5431 .ptp_ops = &mv88e6390_ptp_ops,
5432 .phylink_get_caps = mv88e6390x_phylink_get_caps,
5433 .pcs_ops = &mv88e6390_pcs_ops,
5434};
5435
5436static const struct mv88e6xxx_ops mv88e6393x_ops = {
5437 /* MV88E6XXX_FAMILY_6393 */
5438 .irl_init_all = mv88e6390_g2_irl_init_all,
5439 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5440 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5441 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5442 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5443 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5444 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5445 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5446 .port_set_link = mv88e6xxx_port_set_link,
5447 .port_sync_link = mv88e6xxx_port_sync_link,
5448 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5449 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
5450 .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
5451 .port_tag_remap = mv88e6390_port_tag_remap,
5452 .port_set_policy = mv88e6393x_port_set_policy,
5453 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5454 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5455 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5456 .port_set_ether_type = mv88e6393x_port_set_ether_type,
5457 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5458 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5459 .port_pause_limit = mv88e6390_port_pause_limit,
5460 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5461 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5462 .port_get_cmode = mv88e6352_port_get_cmode,
5463 .port_set_cmode = mv88e6393x_port_set_cmode,
5464 .port_setup_message_port = mv88e6xxx_setup_message_port,
5465 .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
5466 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5467 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5468 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5469 .stats_get_strings = mv88e6320_stats_get_strings,
5470 .stats_get_stat = mv88e6390_stats_get_stat,
5471 /* .set_cpu_port is missing because this family does not support a global
5472 * CPU port, only per port CPU port which is set via
5473 * .port_set_upstream_port method.
5474 */
5475 .set_egress_port = mv88e6393x_set_egress_port,
5476 .watchdog_ops = &mv88e6393x_watchdog_ops,
5477 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
5478 .pot_clear = mv88e6xxx_g2_pot_clear,
5479 .reset = mv88e6352_g1_reset,
5480 .rmu_disable = mv88e6390_g1_rmu_disable,
5481 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5482 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5483 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5484 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5485 .stu_getnext = mv88e6390_g1_stu_getnext,
5486 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5487 .serdes_get_lane = mv88e6393x_serdes_get_lane,
5488 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5489 /* TODO: serdes stats */
5490 .gpio_ops = &mv88e6352_gpio_ops,
5491 .avb_ops = &mv88e6390_avb_ops,
5492 .ptp_ops = &mv88e6352_ptp_ops,
5493 .phylink_get_caps = mv88e6393x_phylink_get_caps,
5494 .pcs_ops = &mv88e6393x_pcs_ops,
5495};
5496
5497static const struct mv88e6xxx_info mv88e6xxx_table[] = {
5498 [MV88E6020] = {
5499 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020,
5500 .family = MV88E6XXX_FAMILY_6250,
5501 .name = "Marvell 88E6020",
5502 .num_databases = 64,
5503 .num_ports = 4,
5504 .num_internal_phys = 2,
5505 .max_vid = 4095,
5506 .port_base_addr = 0x8,
5507 .phy_base_addr = 0x0,
5508 .global1_addr = 0xf,
5509 .global2_addr = 0x7,
5510 .age_time_coeff = 15000,
5511 .g1_irqs = 9,
5512 .g2_irqs = 5,
5513 .atu_move_port_mask = 0xf,
5514 .dual_chip = true,
5515 .ops = &mv88e6250_ops,
5516 },
5517
5518 [MV88E6071] = {
5519 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071,
5520 .family = MV88E6XXX_FAMILY_6250,
5521 .name = "Marvell 88E6071",
5522 .num_databases = 64,
5523 .num_ports = 7,
5524 .num_internal_phys = 5,
5525 .max_vid = 4095,
5526 .port_base_addr = 0x08,
5527 .phy_base_addr = 0x00,
5528 .global1_addr = 0x0f,
5529 .global2_addr = 0x07,
5530 .age_time_coeff = 15000,
5531 .g1_irqs = 9,
5532 .g2_irqs = 5,
5533 .atu_move_port_mask = 0xf,
5534 .dual_chip = true,
5535 .ops = &mv88e6250_ops,
5536 },
5537
5538 [MV88E6085] = {
5539 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
5540 .family = MV88E6XXX_FAMILY_6097,
5541 .name = "Marvell 88E6085",
5542 .num_databases = 4096,
5543 .num_macs = 8192,
5544 .num_ports = 10,
5545 .num_internal_phys = 5,
5546 .max_vid = 4095,
5547 .max_sid = 63,
5548 .port_base_addr = 0x10,
5549 .phy_base_addr = 0x0,
5550 .global1_addr = 0x1b,
5551 .global2_addr = 0x1c,
5552 .age_time_coeff = 15000,
5553 .g1_irqs = 8,
5554 .g2_irqs = 10,
5555 .atu_move_port_mask = 0xf,
5556 .pvt = true,
5557 .multi_chip = true,
5558 .ops = &mv88e6085_ops,
5559 },
5560
5561 [MV88E6095] = {
5562 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
5563 .family = MV88E6XXX_FAMILY_6095,
5564 .name = "Marvell 88E6095/88E6095F",
5565 .num_databases = 256,
5566 .num_macs = 8192,
5567 .num_ports = 11,
5568 .num_internal_phys = 0,
5569 .max_vid = 4095,
5570 .port_base_addr = 0x10,
5571 .phy_base_addr = 0x0,
5572 .global1_addr = 0x1b,
5573 .global2_addr = 0x1c,
5574 .age_time_coeff = 15000,
5575 .g1_irqs = 8,
5576 .atu_move_port_mask = 0xf,
5577 .multi_chip = true,
5578 .ops = &mv88e6095_ops,
5579 },
5580
5581 [MV88E6097] = {
5582 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
5583 .family = MV88E6XXX_FAMILY_6097,
5584 .name = "Marvell 88E6097/88E6097F",
5585 .num_databases = 4096,
5586 .num_macs = 8192,
5587 .num_ports = 11,
5588 .num_internal_phys = 8,
5589 .max_vid = 4095,
5590 .max_sid = 63,
5591 .port_base_addr = 0x10,
5592 .phy_base_addr = 0x0,
5593 .global1_addr = 0x1b,
5594 .global2_addr = 0x1c,
5595 .age_time_coeff = 15000,
5596 .g1_irqs = 8,
5597 .g2_irqs = 10,
5598 .atu_move_port_mask = 0xf,
5599 .pvt = true,
5600 .multi_chip = true,
5601 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5602 .ops = &mv88e6097_ops,
5603 },
5604
5605 [MV88E6123] = {
5606 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
5607 .family = MV88E6XXX_FAMILY_6165,
5608 .name = "Marvell 88E6123",
5609 .num_databases = 4096,
5610 .num_macs = 1024,
5611 .num_ports = 3,
5612 .num_internal_phys = 5,
5613 .max_vid = 4095,
5614 .max_sid = 63,
5615 .port_base_addr = 0x10,
5616 .phy_base_addr = 0x0,
5617 .global1_addr = 0x1b,
5618 .global2_addr = 0x1c,
5619 .age_time_coeff = 15000,
5620 .g1_irqs = 9,
5621 .g2_irqs = 10,
5622 .atu_move_port_mask = 0xf,
5623 .pvt = true,
5624 .multi_chip = true,
5625 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5626 .ops = &mv88e6123_ops,
5627 },
5628
5629 [MV88E6131] = {
5630 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
5631 .family = MV88E6XXX_FAMILY_6185,
5632 .name = "Marvell 88E6131",
5633 .num_databases = 256,
5634 .num_macs = 8192,
5635 .num_ports = 8,
5636 .num_internal_phys = 0,
5637 .max_vid = 4095,
5638 .port_base_addr = 0x10,
5639 .phy_base_addr = 0x0,
5640 .global1_addr = 0x1b,
5641 .global2_addr = 0x1c,
5642 .age_time_coeff = 15000,
5643 .g1_irqs = 9,
5644 .atu_move_port_mask = 0xf,
5645 .multi_chip = true,
5646 .ops = &mv88e6131_ops,
5647 },
5648
5649 [MV88E6141] = {
5650 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
5651 .family = MV88E6XXX_FAMILY_6341,
5652 .name = "Marvell 88E6141",
5653 .num_databases = 4096,
5654 .num_macs = 2048,
5655 .num_ports = 6,
5656 .num_internal_phys = 5,
5657 .num_gpio = 11,
5658 .max_vid = 4095,
5659 .max_sid = 63,
5660 .port_base_addr = 0x10,
5661 .phy_base_addr = 0x10,
5662 .global1_addr = 0x1b,
5663 .global2_addr = 0x1c,
5664 .age_time_coeff = 3750,
5665 .atu_move_port_mask = 0x1f,
5666 .g1_irqs = 9,
5667 .g2_irqs = 10,
5668 .pvt = true,
5669 .multi_chip = true,
5670 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5671 .ops = &mv88e6141_ops,
5672 },
5673
5674 [MV88E6161] = {
5675 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
5676 .family = MV88E6XXX_FAMILY_6165,
5677 .name = "Marvell 88E6161",
5678 .num_databases = 4096,
5679 .num_macs = 1024,
5680 .num_ports = 6,
5681 .num_internal_phys = 5,
5682 .max_vid = 4095,
5683 .max_sid = 63,
5684 .port_base_addr = 0x10,
5685 .phy_base_addr = 0x0,
5686 .global1_addr = 0x1b,
5687 .global2_addr = 0x1c,
5688 .age_time_coeff = 15000,
5689 .g1_irqs = 9,
5690 .g2_irqs = 10,
5691 .atu_move_port_mask = 0xf,
5692 .pvt = true,
5693 .multi_chip = true,
5694 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5695 .ptp_support = true,
5696 .ops = &mv88e6161_ops,
5697 },
5698
5699 [MV88E6165] = {
5700 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
5701 .family = MV88E6XXX_FAMILY_6165,
5702 .name = "Marvell 88E6165",
5703 .num_databases = 4096,
5704 .num_macs = 8192,
5705 .num_ports = 6,
5706 .num_internal_phys = 0,
5707 .max_vid = 4095,
5708 .max_sid = 63,
5709 .port_base_addr = 0x10,
5710 .phy_base_addr = 0x0,
5711 .global1_addr = 0x1b,
5712 .global2_addr = 0x1c,
5713 .age_time_coeff = 15000,
5714 .g1_irqs = 9,
5715 .g2_irqs = 10,
5716 .atu_move_port_mask = 0xf,
5717 .pvt = true,
5718 .multi_chip = true,
5719 .ptp_support = true,
5720 .ops = &mv88e6165_ops,
5721 },
5722
5723 [MV88E6171] = {
5724 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
5725 .family = MV88E6XXX_FAMILY_6351,
5726 .name = "Marvell 88E6171",
5727 .num_databases = 4096,
5728 .num_macs = 8192,
5729 .num_ports = 7,
5730 .num_internal_phys = 5,
5731 .max_vid = 4095,
5732 .max_sid = 63,
5733 .port_base_addr = 0x10,
5734 .phy_base_addr = 0x0,
5735 .global1_addr = 0x1b,
5736 .global2_addr = 0x1c,
5737 .age_time_coeff = 15000,
5738 .g1_irqs = 9,
5739 .g2_irqs = 10,
5740 .atu_move_port_mask = 0xf,
5741 .pvt = true,
5742 .multi_chip = true,
5743 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5744 .ops = &mv88e6171_ops,
5745 },
5746
5747 [MV88E6172] = {
5748 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
5749 .family = MV88E6XXX_FAMILY_6352,
5750 .name = "Marvell 88E6172",
5751 .num_databases = 4096,
5752 .num_macs = 8192,
5753 .num_ports = 7,
5754 .num_internal_phys = 5,
5755 .num_gpio = 15,
5756 .max_vid = 4095,
5757 .max_sid = 63,
5758 .port_base_addr = 0x10,
5759 .phy_base_addr = 0x0,
5760 .global1_addr = 0x1b,
5761 .global2_addr = 0x1c,
5762 .age_time_coeff = 15000,
5763 .g1_irqs = 9,
5764 .g2_irqs = 10,
5765 .atu_move_port_mask = 0xf,
5766 .pvt = true,
5767 .multi_chip = true,
5768 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5769 .ops = &mv88e6172_ops,
5770 },
5771
5772 [MV88E6175] = {
5773 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
5774 .family = MV88E6XXX_FAMILY_6351,
5775 .name = "Marvell 88E6175",
5776 .num_databases = 4096,
5777 .num_macs = 8192,
5778 .num_ports = 7,
5779 .num_internal_phys = 5,
5780 .max_vid = 4095,
5781 .max_sid = 63,
5782 .port_base_addr = 0x10,
5783 .phy_base_addr = 0x0,
5784 .global1_addr = 0x1b,
5785 .global2_addr = 0x1c,
5786 .age_time_coeff = 15000,
5787 .g1_irqs = 9,
5788 .g2_irqs = 10,
5789 .atu_move_port_mask = 0xf,
5790 .pvt = true,
5791 .multi_chip = true,
5792 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5793 .ops = &mv88e6175_ops,
5794 },
5795
5796 [MV88E6176] = {
5797 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5798 .family = MV88E6XXX_FAMILY_6352,
5799 .name = "Marvell 88E6176",
5800 .num_databases = 4096,
5801 .num_macs = 8192,
5802 .num_ports = 7,
5803 .num_internal_phys = 5,
5804 .num_gpio = 15,
5805 .max_vid = 4095,
5806 .max_sid = 63,
5807 .port_base_addr = 0x10,
5808 .phy_base_addr = 0x0,
5809 .global1_addr = 0x1b,
5810 .global2_addr = 0x1c,
5811 .age_time_coeff = 15000,
5812 .g1_irqs = 9,
5813 .g2_irqs = 10,
5814 .atu_move_port_mask = 0xf,
5815 .pvt = true,
5816 .multi_chip = true,
5817 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5818 .ops = &mv88e6176_ops,
5819 },
5820
5821 [MV88E6185] = {
5822 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
5823 .family = MV88E6XXX_FAMILY_6185,
5824 .name = "Marvell 88E6185",
5825 .num_databases = 256,
5826 .num_macs = 8192,
5827 .num_ports = 10,
5828 .num_internal_phys = 0,
5829 .max_vid = 4095,
5830 .port_base_addr = 0x10,
5831 .phy_base_addr = 0x0,
5832 .global1_addr = 0x1b,
5833 .global2_addr = 0x1c,
5834 .age_time_coeff = 15000,
5835 .g1_irqs = 8,
5836 .atu_move_port_mask = 0xf,
5837 .multi_chip = true,
5838 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5839 .ops = &mv88e6185_ops,
5840 },
5841
5842 [MV88E6190] = {
5843 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
5844 .family = MV88E6XXX_FAMILY_6390,
5845 .name = "Marvell 88E6190",
5846 .num_databases = 4096,
5847 .num_macs = 16384,
5848 .num_ports = 11, /* 10 + Z80 */
5849 .num_internal_phys = 9,
5850 .num_gpio = 16,
5851 .max_vid = 8191,
5852 .max_sid = 63,
5853 .port_base_addr = 0x0,
5854 .phy_base_addr = 0x0,
5855 .global1_addr = 0x1b,
5856 .global2_addr = 0x1c,
5857 .age_time_coeff = 3750,
5858 .g1_irqs = 9,
5859 .g2_irqs = 14,
5860 .pvt = true,
5861 .multi_chip = true,
5862 .atu_move_port_mask = 0x1f,
5863 .ops = &mv88e6190_ops,
5864 },
5865
5866 [MV88E6190X] = {
5867 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
5868 .family = MV88E6XXX_FAMILY_6390,
5869 .name = "Marvell 88E6190X",
5870 .num_databases = 4096,
5871 .num_macs = 16384,
5872 .num_ports = 11, /* 10 + Z80 */
5873 .num_internal_phys = 9,
5874 .num_gpio = 16,
5875 .max_vid = 8191,
5876 .max_sid = 63,
5877 .port_base_addr = 0x0,
5878 .phy_base_addr = 0x0,
5879 .global1_addr = 0x1b,
5880 .global2_addr = 0x1c,
5881 .age_time_coeff = 3750,
5882 .g1_irqs = 9,
5883 .g2_irqs = 14,
5884 .atu_move_port_mask = 0x1f,
5885 .pvt = true,
5886 .multi_chip = true,
5887 .ops = &mv88e6190x_ops,
5888 },
5889
5890 [MV88E6191] = {
5891 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
5892 .family = MV88E6XXX_FAMILY_6390,
5893 .name = "Marvell 88E6191",
5894 .num_databases = 4096,
5895 .num_macs = 16384,
5896 .num_ports = 11, /* 10 + Z80 */
5897 .num_internal_phys = 9,
5898 .max_vid = 8191,
5899 .max_sid = 63,
5900 .port_base_addr = 0x0,
5901 .phy_base_addr = 0x0,
5902 .global1_addr = 0x1b,
5903 .global2_addr = 0x1c,
5904 .age_time_coeff = 3750,
5905 .g1_irqs = 9,
5906 .g2_irqs = 14,
5907 .atu_move_port_mask = 0x1f,
5908 .pvt = true,
5909 .multi_chip = true,
5910 .ptp_support = true,
5911 .ops = &mv88e6191_ops,
5912 },
5913
5914 [MV88E6191X] = {
5915 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
5916 .family = MV88E6XXX_FAMILY_6393,
5917 .name = "Marvell 88E6191X",
5918 .num_databases = 4096,
5919 .num_ports = 11, /* 10 + Z80 */
5920 .num_internal_phys = 8,
5921 .internal_phys_offset = 1,
5922 .max_vid = 8191,
5923 .max_sid = 63,
5924 .port_base_addr = 0x0,
5925 .phy_base_addr = 0x0,
5926 .global1_addr = 0x1b,
5927 .global2_addr = 0x1c,
5928 .age_time_coeff = 3750,
5929 .g1_irqs = 10,
5930 .g2_irqs = 14,
5931 .atu_move_port_mask = 0x1f,
5932 .pvt = true,
5933 .multi_chip = true,
5934 .ptp_support = true,
5935 .ops = &mv88e6393x_ops,
5936 },
5937
5938 [MV88E6193X] = {
5939 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
5940 .family = MV88E6XXX_FAMILY_6393,
5941 .name = "Marvell 88E6193X",
5942 .num_databases = 4096,
5943 .num_ports = 11, /* 10 + Z80 */
5944 .num_internal_phys = 8,
5945 .internal_phys_offset = 1,
5946 .max_vid = 8191,
5947 .max_sid = 63,
5948 .port_base_addr = 0x0,
5949 .phy_base_addr = 0x0,
5950 .global1_addr = 0x1b,
5951 .global2_addr = 0x1c,
5952 .age_time_coeff = 3750,
5953 .g1_irqs = 10,
5954 .g2_irqs = 14,
5955 .atu_move_port_mask = 0x1f,
5956 .pvt = true,
5957 .multi_chip = true,
5958 .ptp_support = true,
5959 .ops = &mv88e6393x_ops,
5960 },
5961
5962 [MV88E6220] = {
5963 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
5964 .family = MV88E6XXX_FAMILY_6250,
5965 .name = "Marvell 88E6220",
5966 .num_databases = 64,
5967
5968 /* Ports 2-4 are not routed to pins
5969 * => usable ports 0, 1, 5, 6
5970 */
5971 .num_ports = 7,
5972 .num_internal_phys = 2,
5973 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5974 .max_vid = 4095,
5975 .port_base_addr = 0x08,
5976 .phy_base_addr = 0x00,
5977 .global1_addr = 0x0f,
5978 .global2_addr = 0x07,
5979 .age_time_coeff = 15000,
5980 .g1_irqs = 9,
5981 .g2_irqs = 10,
5982 .atu_move_port_mask = 0xf,
5983 .dual_chip = true,
5984 .ptp_support = true,
5985 .ops = &mv88e6250_ops,
5986 },
5987
5988 [MV88E6240] = {
5989 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
5990 .family = MV88E6XXX_FAMILY_6352,
5991 .name = "Marvell 88E6240",
5992 .num_databases = 4096,
5993 .num_macs = 8192,
5994 .num_ports = 7,
5995 .num_internal_phys = 5,
5996 .num_gpio = 15,
5997 .max_vid = 4095,
5998 .max_sid = 63,
5999 .port_base_addr = 0x10,
6000 .phy_base_addr = 0x0,
6001 .global1_addr = 0x1b,
6002 .global2_addr = 0x1c,
6003 .age_time_coeff = 15000,
6004 .g1_irqs = 9,
6005 .g2_irqs = 10,
6006 .atu_move_port_mask = 0xf,
6007 .pvt = true,
6008 .multi_chip = true,
6009 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6010 .ptp_support = true,
6011 .ops = &mv88e6240_ops,
6012 },
6013
6014 [MV88E6250] = {
6015 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
6016 .family = MV88E6XXX_FAMILY_6250,
6017 .name = "Marvell 88E6250",
6018 .num_databases = 64,
6019 .num_ports = 7,
6020 .num_internal_phys = 5,
6021 .max_vid = 4095,
6022 .port_base_addr = 0x08,
6023 .phy_base_addr = 0x00,
6024 .global1_addr = 0x0f,
6025 .global2_addr = 0x07,
6026 .age_time_coeff = 15000,
6027 .g1_irqs = 9,
6028 .g2_irqs = 10,
6029 .atu_move_port_mask = 0xf,
6030 .dual_chip = true,
6031 .ptp_support = true,
6032 .ops = &mv88e6250_ops,
6033 },
6034
6035 [MV88E6290] = {
6036 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
6037 .family = MV88E6XXX_FAMILY_6390,
6038 .name = "Marvell 88E6290",
6039 .num_databases = 4096,
6040 .num_ports = 11, /* 10 + Z80 */
6041 .num_internal_phys = 9,
6042 .num_gpio = 16,
6043 .max_vid = 8191,
6044 .max_sid = 63,
6045 .port_base_addr = 0x0,
6046 .phy_base_addr = 0x0,
6047 .global1_addr = 0x1b,
6048 .global2_addr = 0x1c,
6049 .age_time_coeff = 3750,
6050 .g1_irqs = 9,
6051 .g2_irqs = 14,
6052 .atu_move_port_mask = 0x1f,
6053 .pvt = true,
6054 .multi_chip = true,
6055 .ptp_support = true,
6056 .ops = &mv88e6290_ops,
6057 },
6058
6059 [MV88E6320] = {
6060 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
6061 .family = MV88E6XXX_FAMILY_6320,
6062 .name = "Marvell 88E6320",
6063 .num_databases = 4096,
6064 .num_macs = 8192,
6065 .num_ports = 7,
6066 .num_internal_phys = 5,
6067 .num_gpio = 15,
6068 .max_vid = 4095,
6069 .port_base_addr = 0x10,
6070 .phy_base_addr = 0x0,
6071 .global1_addr = 0x1b,
6072 .global2_addr = 0x1c,
6073 .age_time_coeff = 15000,
6074 .g1_irqs = 8,
6075 .g2_irqs = 10,
6076 .atu_move_port_mask = 0xf,
6077 .pvt = true,
6078 .multi_chip = true,
6079 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6080 .ptp_support = true,
6081 .ops = &mv88e6320_ops,
6082 },
6083
6084 [MV88E6321] = {
6085 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
6086 .family = MV88E6XXX_FAMILY_6320,
6087 .name = "Marvell 88E6321",
6088 .num_databases = 4096,
6089 .num_macs = 8192,
6090 .num_ports = 7,
6091 .num_internal_phys = 5,
6092 .num_gpio = 15,
6093 .max_vid = 4095,
6094 .port_base_addr = 0x10,
6095 .phy_base_addr = 0x0,
6096 .global1_addr = 0x1b,
6097 .global2_addr = 0x1c,
6098 .age_time_coeff = 15000,
6099 .g1_irqs = 8,
6100 .g2_irqs = 10,
6101 .atu_move_port_mask = 0xf,
6102 .multi_chip = true,
6103 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6104 .ptp_support = true,
6105 .ops = &mv88e6321_ops,
6106 },
6107
6108 [MV88E6341] = {
6109 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
6110 .family = MV88E6XXX_FAMILY_6341,
6111 .name = "Marvell 88E6341",
6112 .num_databases = 4096,
6113 .num_macs = 2048,
6114 .num_internal_phys = 5,
6115 .num_ports = 6,
6116 .num_gpio = 11,
6117 .max_vid = 4095,
6118 .max_sid = 63,
6119 .port_base_addr = 0x10,
6120 .phy_base_addr = 0x10,
6121 .global1_addr = 0x1b,
6122 .global2_addr = 0x1c,
6123 .age_time_coeff = 3750,
6124 .atu_move_port_mask = 0x1f,
6125 .g1_irqs = 9,
6126 .g2_irqs = 10,
6127 .pvt = true,
6128 .multi_chip = true,
6129 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6130 .ptp_support = true,
6131 .ops = &mv88e6341_ops,
6132 },
6133
6134 [MV88E6350] = {
6135 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
6136 .family = MV88E6XXX_FAMILY_6351,
6137 .name = "Marvell 88E6350",
6138 .num_databases = 4096,
6139 .num_macs = 8192,
6140 .num_ports = 7,
6141 .num_internal_phys = 5,
6142 .max_vid = 4095,
6143 .max_sid = 63,
6144 .port_base_addr = 0x10,
6145 .phy_base_addr = 0x0,
6146 .global1_addr = 0x1b,
6147 .global2_addr = 0x1c,
6148 .age_time_coeff = 15000,
6149 .g1_irqs = 9,
6150 .g2_irqs = 10,
6151 .atu_move_port_mask = 0xf,
6152 .pvt = true,
6153 .multi_chip = true,
6154 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6155 .ops = &mv88e6350_ops,
6156 },
6157
6158 [MV88E6351] = {
6159 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
6160 .family = MV88E6XXX_FAMILY_6351,
6161 .name = "Marvell 88E6351",
6162 .num_databases = 4096,
6163 .num_macs = 8192,
6164 .num_ports = 7,
6165 .num_internal_phys = 5,
6166 .max_vid = 4095,
6167 .max_sid = 63,
6168 .port_base_addr = 0x10,
6169 .phy_base_addr = 0x0,
6170 .global1_addr = 0x1b,
6171 .global2_addr = 0x1c,
6172 .age_time_coeff = 15000,
6173 .g1_irqs = 9,
6174 .g2_irqs = 10,
6175 .atu_move_port_mask = 0xf,
6176 .pvt = true,
6177 .multi_chip = true,
6178 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6179 .ops = &mv88e6351_ops,
6180 },
6181
6182 [MV88E6352] = {
6183 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
6184 .family = MV88E6XXX_FAMILY_6352,
6185 .name = "Marvell 88E6352",
6186 .num_databases = 4096,
6187 .num_macs = 8192,
6188 .num_ports = 7,
6189 .num_internal_phys = 5,
6190 .num_gpio = 15,
6191 .max_vid = 4095,
6192 .max_sid = 63,
6193 .port_base_addr = 0x10,
6194 .phy_base_addr = 0x0,
6195 .global1_addr = 0x1b,
6196 .global2_addr = 0x1c,
6197 .age_time_coeff = 15000,
6198 .g1_irqs = 9,
6199 .g2_irqs = 10,
6200 .atu_move_port_mask = 0xf,
6201 .pvt = true,
6202 .multi_chip = true,
6203 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6204 .ptp_support = true,
6205 .ops = &mv88e6352_ops,
6206 },
6207 [MV88E6361] = {
6208 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361,
6209 .family = MV88E6XXX_FAMILY_6393,
6210 .name = "Marvell 88E6361",
6211 .num_databases = 4096,
6212 .num_macs = 16384,
6213 .num_ports = 11,
6214 /* Ports 1, 2 and 8 are not routed */
6215 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8),
6216 .num_internal_phys = 5,
6217 .internal_phys_offset = 3,
6218 .max_vid = 4095,
6219 .max_sid = 63,
6220 .port_base_addr = 0x0,
6221 .phy_base_addr = 0x0,
6222 .global1_addr = 0x1b,
6223 .global2_addr = 0x1c,
6224 .age_time_coeff = 3750,
6225 .g1_irqs = 10,
6226 .g2_irqs = 14,
6227 .atu_move_port_mask = 0x1f,
6228 .pvt = true,
6229 .multi_chip = true,
6230 .ptp_support = true,
6231 .ops = &mv88e6393x_ops,
6232 },
6233 [MV88E6390] = {
6234 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
6235 .family = MV88E6XXX_FAMILY_6390,
6236 .name = "Marvell 88E6390",
6237 .num_databases = 4096,
6238 .num_macs = 16384,
6239 .num_ports = 11, /* 10 + Z80 */
6240 .num_internal_phys = 9,
6241 .num_gpio = 16,
6242 .max_vid = 8191,
6243 .max_sid = 63,
6244 .port_base_addr = 0x0,
6245 .phy_base_addr = 0x0,
6246 .global1_addr = 0x1b,
6247 .global2_addr = 0x1c,
6248 .age_time_coeff = 3750,
6249 .g1_irqs = 9,
6250 .g2_irqs = 14,
6251 .atu_move_port_mask = 0x1f,
6252 .pvt = true,
6253 .multi_chip = true,
6254 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6255 .ptp_support = true,
6256 .ops = &mv88e6390_ops,
6257 },
6258 [MV88E6390X] = {
6259 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
6260 .family = MV88E6XXX_FAMILY_6390,
6261 .name = "Marvell 88E6390X",
6262 .num_databases = 4096,
6263 .num_macs = 16384,
6264 .num_ports = 11, /* 10 + Z80 */
6265 .num_internal_phys = 9,
6266 .num_gpio = 16,
6267 .max_vid = 8191,
6268 .max_sid = 63,
6269 .port_base_addr = 0x0,
6270 .phy_base_addr = 0x0,
6271 .global1_addr = 0x1b,
6272 .global2_addr = 0x1c,
6273 .age_time_coeff = 3750,
6274 .g1_irqs = 9,
6275 .g2_irqs = 14,
6276 .atu_move_port_mask = 0x1f,
6277 .pvt = true,
6278 .multi_chip = true,
6279 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6280 .ptp_support = true,
6281 .ops = &mv88e6390x_ops,
6282 },
6283
6284 [MV88E6393X] = {
6285 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
6286 .family = MV88E6XXX_FAMILY_6393,
6287 .name = "Marvell 88E6393X",
6288 .num_databases = 4096,
6289 .num_ports = 11, /* 10 + Z80 */
6290 .num_internal_phys = 8,
6291 .internal_phys_offset = 1,
6292 .max_vid = 8191,
6293 .max_sid = 63,
6294 .port_base_addr = 0x0,
6295 .phy_base_addr = 0x0,
6296 .global1_addr = 0x1b,
6297 .global2_addr = 0x1c,
6298 .age_time_coeff = 3750,
6299 .g1_irqs = 10,
6300 .g2_irqs = 14,
6301 .atu_move_port_mask = 0x1f,
6302 .pvt = true,
6303 .multi_chip = true,
6304 .ptp_support = true,
6305 .ops = &mv88e6393x_ops,
6306 },
6307};
6308
6309static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
6310{
6311 int i;
6312
6313 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
6314 if (mv88e6xxx_table[i].prod_num == prod_num)
6315 return &mv88e6xxx_table[i];
6316
6317 return NULL;
6318}
6319
6320static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
6321{
6322 const struct mv88e6xxx_info *info;
6323 unsigned int prod_num, rev;
6324 u16 id;
6325 int err;
6326
6327 mv88e6xxx_reg_lock(chip);
6328 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
6329 mv88e6xxx_reg_unlock(chip);
6330 if (err)
6331 return err;
6332
6333 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
6334 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
6335
6336 info = mv88e6xxx_lookup_info(prod_num);
6337 if (!info)
6338 return -ENODEV;
6339
6340 /* Update the compatible info with the probed one */
6341 chip->info = info;
6342
6343 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
6344 chip->info->prod_num, chip->info->name, rev);
6345
6346 return 0;
6347}
6348
6349static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip,
6350 struct mdio_device *mdiodev)
6351{
6352 int err;
6353
6354 /* dual_chip takes precedence over single/multi-chip modes */
6355 if (chip->info->dual_chip)
6356 return -EINVAL;
6357
6358 /* If the mdio addr is 16 indicating the first port address of a switch
6359 * (e.g. mv88e6*41) in single chip addressing mode the device may be
6360 * configured in single chip addressing mode. Setup the smi access as
6361 * single chip addressing mode and attempt to detect the model of the
6362 * switch, if this fails the device is not configured in single chip
6363 * addressing mode.
6364 */
6365 if (mdiodev->addr != 16)
6366 return -EINVAL;
6367
6368 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0);
6369 if (err)
6370 return err;
6371
6372 return mv88e6xxx_detect(chip);
6373}
6374
6375static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
6376{
6377 struct mv88e6xxx_chip *chip;
6378
6379 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
6380 if (!chip)
6381 return NULL;
6382
6383 chip->dev = dev;
6384
6385 mutex_init(&chip->reg_lock);
6386 INIT_LIST_HEAD(&chip->mdios);
6387 idr_init(&chip->policies);
6388 INIT_LIST_HEAD(&chip->msts);
6389
6390 return chip;
6391}
6392
6393static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
6394 int port,
6395 enum dsa_tag_protocol m)
6396{
6397 struct mv88e6xxx_chip *chip = ds->priv;
6398
6399 return chip->tag_protocol;
6400}
6401
6402static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds,
6403 enum dsa_tag_protocol proto)
6404{
6405 struct mv88e6xxx_chip *chip = ds->priv;
6406 enum dsa_tag_protocol old_protocol;
6407 struct dsa_port *cpu_dp;
6408 int err;
6409
6410 switch (proto) {
6411 case DSA_TAG_PROTO_EDSA:
6412 switch (chip->info->edsa_support) {
6413 case MV88E6XXX_EDSA_UNSUPPORTED:
6414 return -EPROTONOSUPPORT;
6415 case MV88E6XXX_EDSA_UNDOCUMENTED:
6416 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
6417 fallthrough;
6418 case MV88E6XXX_EDSA_SUPPORTED:
6419 break;
6420 }
6421 break;
6422 case DSA_TAG_PROTO_DSA:
6423 break;
6424 default:
6425 return -EPROTONOSUPPORT;
6426 }
6427
6428 old_protocol = chip->tag_protocol;
6429 chip->tag_protocol = proto;
6430
6431 mv88e6xxx_reg_lock(chip);
6432 dsa_switch_for_each_cpu_port(cpu_dp, ds) {
6433 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6434 if (err) {
6435 mv88e6xxx_reg_unlock(chip);
6436 goto unwind;
6437 }
6438 }
6439 mv88e6xxx_reg_unlock(chip);
6440
6441 return 0;
6442
6443unwind:
6444 chip->tag_protocol = old_protocol;
6445
6446 mv88e6xxx_reg_lock(chip);
6447 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds)
6448 mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6449 mv88e6xxx_reg_unlock(chip);
6450
6451 return err;
6452}
6453
6454static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
6455 const struct switchdev_obj_port_mdb *mdb,
6456 struct dsa_db db)
6457{
6458 struct mv88e6xxx_chip *chip = ds->priv;
6459 int err;
6460
6461 mv88e6xxx_reg_lock(chip);
6462 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
6463 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
6464 mv88e6xxx_reg_unlock(chip);
6465
6466 return err;
6467}
6468
6469static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
6470 const struct switchdev_obj_port_mdb *mdb,
6471 struct dsa_db db)
6472{
6473 struct mv88e6xxx_chip *chip = ds->priv;
6474 int err;
6475
6476 mv88e6xxx_reg_lock(chip);
6477 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
6478 mv88e6xxx_reg_unlock(chip);
6479
6480 return err;
6481}
6482
6483static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
6484 struct dsa_mall_mirror_tc_entry *mirror,
6485 bool ingress,
6486 struct netlink_ext_ack *extack)
6487{
6488 enum mv88e6xxx_egress_direction direction = ingress ?
6489 MV88E6XXX_EGRESS_DIR_INGRESS :
6490 MV88E6XXX_EGRESS_DIR_EGRESS;
6491 struct mv88e6xxx_chip *chip = ds->priv;
6492 bool other_mirrors = false;
6493 int i;
6494 int err;
6495
6496 mutex_lock(&chip->reg_lock);
6497 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
6498 mirror->to_local_port) {
6499 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6500 other_mirrors |= ingress ?
6501 chip->ports[i].mirror_ingress :
6502 chip->ports[i].mirror_egress;
6503
6504 /* Can't change egress port when other mirror is active */
6505 if (other_mirrors) {
6506 err = -EBUSY;
6507 goto out;
6508 }
6509
6510 err = mv88e6xxx_set_egress_port(chip, direction,
6511 mirror->to_local_port);
6512 if (err)
6513 goto out;
6514 }
6515
6516 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
6517out:
6518 mutex_unlock(&chip->reg_lock);
6519
6520 return err;
6521}
6522
6523static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
6524 struct dsa_mall_mirror_tc_entry *mirror)
6525{
6526 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
6527 MV88E6XXX_EGRESS_DIR_INGRESS :
6528 MV88E6XXX_EGRESS_DIR_EGRESS;
6529 struct mv88e6xxx_chip *chip = ds->priv;
6530 bool other_mirrors = false;
6531 int i;
6532
6533 mutex_lock(&chip->reg_lock);
6534 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
6535 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
6536
6537 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6538 other_mirrors |= mirror->ingress ?
6539 chip->ports[i].mirror_ingress :
6540 chip->ports[i].mirror_egress;
6541
6542 /* Reset egress port when no other mirror is active */
6543 if (!other_mirrors) {
6544 if (mv88e6xxx_set_egress_port(chip, direction,
6545 dsa_upstream_port(ds, port)))
6546 dev_err(ds->dev, "failed to set egress port\n");
6547 }
6548
6549 mutex_unlock(&chip->reg_lock);
6550}
6551
6552static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
6553 struct switchdev_brport_flags flags,
6554 struct netlink_ext_ack *extack)
6555{
6556 struct mv88e6xxx_chip *chip = ds->priv;
6557 const struct mv88e6xxx_ops *ops;
6558
6559 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
6560 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB))
6561 return -EINVAL;
6562
6563 ops = chip->info->ops;
6564
6565 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
6566 return -EINVAL;
6567
6568 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
6569 return -EINVAL;
6570
6571 return 0;
6572}
6573
6574static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
6575 struct switchdev_brport_flags flags,
6576 struct netlink_ext_ack *extack)
6577{
6578 struct mv88e6xxx_chip *chip = ds->priv;
6579 int err = 0;
6580
6581 mv88e6xxx_reg_lock(chip);
6582
6583 if (flags.mask & BR_LEARNING) {
6584 bool learning = !!(flags.val & BR_LEARNING);
6585 u16 pav = learning ? (1 << port) : 0;
6586
6587 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
6588 if (err)
6589 goto out;
6590 }
6591
6592 if (flags.mask & BR_FLOOD) {
6593 bool unicast = !!(flags.val & BR_FLOOD);
6594
6595 err = chip->info->ops->port_set_ucast_flood(chip, port,
6596 unicast);
6597 if (err)
6598 goto out;
6599 }
6600
6601 if (flags.mask & BR_MCAST_FLOOD) {
6602 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
6603
6604 err = chip->info->ops->port_set_mcast_flood(chip, port,
6605 multicast);
6606 if (err)
6607 goto out;
6608 }
6609
6610 if (flags.mask & BR_BCAST_FLOOD) {
6611 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
6612
6613 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
6614 if (err)
6615 goto out;
6616 }
6617
6618 if (flags.mask & BR_PORT_MAB) {
6619 bool mab = !!(flags.val & BR_PORT_MAB);
6620
6621 mv88e6xxx_port_set_mab(chip, port, mab);
6622 }
6623
6624 if (flags.mask & BR_PORT_LOCKED) {
6625 bool locked = !!(flags.val & BR_PORT_LOCKED);
6626
6627 err = mv88e6xxx_port_set_lock(chip, port, locked);
6628 if (err)
6629 goto out;
6630 }
6631out:
6632 mv88e6xxx_reg_unlock(chip);
6633
6634 return err;
6635}
6636
6637static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
6638 struct dsa_lag lag,
6639 struct netdev_lag_upper_info *info,
6640 struct netlink_ext_ack *extack)
6641{
6642 struct mv88e6xxx_chip *chip = ds->priv;
6643 struct dsa_port *dp;
6644 int members = 0;
6645
6646 if (!mv88e6xxx_has_lag(chip)) {
6647 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload");
6648 return false;
6649 }
6650
6651 if (!lag.id)
6652 return false;
6653
6654 dsa_lag_foreach_port(dp, ds->dst, &lag)
6655 /* Includes the port joining the LAG */
6656 members++;
6657
6658 if (members > 8) {
6659 NL_SET_ERR_MSG_MOD(extack,
6660 "Cannot offload more than 8 LAG ports");
6661 return false;
6662 }
6663
6664 /* We could potentially relax this to include active
6665 * backup in the future.
6666 */
6667 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
6668 NL_SET_ERR_MSG_MOD(extack,
6669 "Can only offload LAG using hash TX type");
6670 return false;
6671 }
6672
6673 /* Ideally we would also validate that the hash type matches
6674 * the hardware. Alas, this is always set to unknown on team
6675 * interfaces.
6676 */
6677 return true;
6678}
6679
6680static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag)
6681{
6682 struct mv88e6xxx_chip *chip = ds->priv;
6683 struct dsa_port *dp;
6684 u16 map = 0;
6685 int id;
6686
6687 /* DSA LAG IDs are one-based, hardware is zero-based */
6688 id = lag.id - 1;
6689
6690 /* Build the map of all ports to distribute flows destined for
6691 * this LAG. This can be either a local user port, or a DSA
6692 * port if the LAG port is on a remote chip.
6693 */
6694 dsa_lag_foreach_port(dp, ds->dst, &lag)
6695 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
6696
6697 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
6698}
6699
6700static const u8 mv88e6xxx_lag_mask_table[8][8] = {
6701 /* Row number corresponds to the number of active members in a
6702 * LAG. Each column states which of the eight hash buckets are
6703 * mapped to the column:th port in the LAG.
6704 *
6705 * Example: In a LAG with three active ports, the second port
6706 * ([2][1]) would be selected for traffic mapped to buckets
6707 * 3,4,5 (0x38).
6708 */
6709 { 0xff, 0, 0, 0, 0, 0, 0, 0 },
6710 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 },
6711 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 },
6712 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 },
6713 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 },
6714 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 },
6715 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 },
6716 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
6717};
6718
6719static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
6720 int num_tx, int nth)
6721{
6722 u8 active = 0;
6723 int i;
6724
6725 num_tx = num_tx <= 8 ? num_tx : 8;
6726 if (nth < num_tx)
6727 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
6728
6729 for (i = 0; i < 8; i++) {
6730 if (BIT(i) & active)
6731 mask[i] |= BIT(port);
6732 }
6733}
6734
6735static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
6736{
6737 struct mv88e6xxx_chip *chip = ds->priv;
6738 unsigned int id, num_tx;
6739 struct dsa_port *dp;
6740 struct dsa_lag *lag;
6741 int i, err, nth;
6742 u16 mask[8];
6743 u16 ivec;
6744
6745 /* Assume no port is a member of any LAG. */
6746 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
6747
6748 /* Disable all masks for ports that _are_ members of a LAG. */
6749 dsa_switch_for_each_port(dp, ds) {
6750 if (!dp->lag)
6751 continue;
6752
6753 ivec &= ~BIT(dp->index);
6754 }
6755
6756 for (i = 0; i < 8; i++)
6757 mask[i] = ivec;
6758
6759 /* Enable the correct subset of masks for all LAG ports that
6760 * are in the Tx set.
6761 */
6762 dsa_lags_foreach_id(id, ds->dst) {
6763 lag = dsa_lag_by_id(ds->dst, id);
6764 if (!lag)
6765 continue;
6766
6767 num_tx = 0;
6768 dsa_lag_foreach_port(dp, ds->dst, lag) {
6769 if (dp->lag_tx_enabled)
6770 num_tx++;
6771 }
6772
6773 if (!num_tx)
6774 continue;
6775
6776 nth = 0;
6777 dsa_lag_foreach_port(dp, ds->dst, lag) {
6778 if (!dp->lag_tx_enabled)
6779 continue;
6780
6781 if (dp->ds == ds)
6782 mv88e6xxx_lag_set_port_mask(mask, dp->index,
6783 num_tx, nth);
6784
6785 nth++;
6786 }
6787 }
6788
6789 for (i = 0; i < 8; i++) {
6790 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
6791 if (err)
6792 return err;
6793 }
6794
6795 return 0;
6796}
6797
6798static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
6799 struct dsa_lag lag)
6800{
6801 int err;
6802
6803 err = mv88e6xxx_lag_sync_masks(ds);
6804
6805 if (!err)
6806 err = mv88e6xxx_lag_sync_map(ds, lag);
6807
6808 return err;
6809}
6810
6811static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
6812{
6813 struct mv88e6xxx_chip *chip = ds->priv;
6814 int err;
6815
6816 mv88e6xxx_reg_lock(chip);
6817 err = mv88e6xxx_lag_sync_masks(ds);
6818 mv88e6xxx_reg_unlock(chip);
6819 return err;
6820}
6821
6822static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
6823 struct dsa_lag lag,
6824 struct netdev_lag_upper_info *info,
6825 struct netlink_ext_ack *extack)
6826{
6827 struct mv88e6xxx_chip *chip = ds->priv;
6828 int err, id;
6829
6830 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6831 return -EOPNOTSUPP;
6832
6833 /* DSA LAG IDs are one-based */
6834 id = lag.id - 1;
6835
6836 mv88e6xxx_reg_lock(chip);
6837
6838 err = mv88e6xxx_port_set_trunk(chip, port, true, id);
6839 if (err)
6840 goto err_unlock;
6841
6842 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6843 if (err)
6844 goto err_clear_trunk;
6845
6846 mv88e6xxx_reg_unlock(chip);
6847 return 0;
6848
6849err_clear_trunk:
6850 mv88e6xxx_port_set_trunk(chip, port, false, 0);
6851err_unlock:
6852 mv88e6xxx_reg_unlock(chip);
6853 return err;
6854}
6855
6856static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6857 struct dsa_lag lag)
6858{
6859 struct mv88e6xxx_chip *chip = ds->priv;
6860 int err_sync, err_trunk;
6861
6862 mv88e6xxx_reg_lock(chip);
6863 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6864 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
6865 mv88e6xxx_reg_unlock(chip);
6866 return err_sync ? : err_trunk;
6867}
6868
6869static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
6870 int port)
6871{
6872 struct mv88e6xxx_chip *chip = ds->priv;
6873 int err;
6874
6875 mv88e6xxx_reg_lock(chip);
6876 err = mv88e6xxx_lag_sync_masks(ds);
6877 mv88e6xxx_reg_unlock(chip);
6878 return err;
6879}
6880
6881static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6882 int port, struct dsa_lag lag,
6883 struct netdev_lag_upper_info *info,
6884 struct netlink_ext_ack *extack)
6885{
6886 struct mv88e6xxx_chip *chip = ds->priv;
6887 int err;
6888
6889 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6890 return -EOPNOTSUPP;
6891
6892 mv88e6xxx_reg_lock(chip);
6893
6894 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6895 if (err)
6896 goto unlock;
6897
6898 err = mv88e6xxx_pvt_map(chip, sw_index, port);
6899
6900unlock:
6901 mv88e6xxx_reg_unlock(chip);
6902 return err;
6903}
6904
6905static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6906 int port, struct dsa_lag lag)
6907{
6908 struct mv88e6xxx_chip *chip = ds->priv;
6909 int err_sync, err_pvt;
6910
6911 mv88e6xxx_reg_lock(chip);
6912 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6913 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
6914 mv88e6xxx_reg_unlock(chip);
6915 return err_sync ? : err_pvt;
6916}
6917
6918static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
6919 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
6920 .change_tag_protocol = mv88e6xxx_change_tag_protocol,
6921 .setup = mv88e6xxx_setup,
6922 .teardown = mv88e6xxx_teardown,
6923 .port_setup = mv88e6xxx_port_setup,
6924 .port_teardown = mv88e6xxx_port_teardown,
6925 .phylink_get_caps = mv88e6xxx_get_caps,
6926 .phylink_mac_select_pcs = mv88e6xxx_mac_select_pcs,
6927 .phylink_mac_prepare = mv88e6xxx_mac_prepare,
6928 .phylink_mac_config = mv88e6xxx_mac_config,
6929 .phylink_mac_finish = mv88e6xxx_mac_finish,
6930 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
6931 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
6932 .get_strings = mv88e6xxx_get_strings,
6933 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
6934 .get_eth_mac_stats = mv88e6xxx_get_eth_mac_stats,
6935 .get_rmon_stats = mv88e6xxx_get_rmon_stats,
6936 .get_sset_count = mv88e6xxx_get_sset_count,
6937 .port_max_mtu = mv88e6xxx_get_max_mtu,
6938 .port_change_mtu = mv88e6xxx_change_mtu,
6939 .get_mac_eee = mv88e6xxx_get_mac_eee,
6940 .set_mac_eee = mv88e6xxx_set_mac_eee,
6941 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
6942 .get_eeprom = mv88e6xxx_get_eeprom,
6943 .set_eeprom = mv88e6xxx_set_eeprom,
6944 .get_regs_len = mv88e6xxx_get_regs_len,
6945 .get_regs = mv88e6xxx_get_regs,
6946 .get_rxnfc = mv88e6xxx_get_rxnfc,
6947 .set_rxnfc = mv88e6xxx_set_rxnfc,
6948 .set_ageing_time = mv88e6xxx_set_ageing_time,
6949 .port_bridge_join = mv88e6xxx_port_bridge_join,
6950 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
6951 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags,
6952 .port_bridge_flags = mv88e6xxx_port_bridge_flags,
6953 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
6954 .port_mst_state_set = mv88e6xxx_port_mst_state_set,
6955 .port_fast_age = mv88e6xxx_port_fast_age,
6956 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age,
6957 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
6958 .port_vlan_add = mv88e6xxx_port_vlan_add,
6959 .port_vlan_del = mv88e6xxx_port_vlan_del,
6960 .vlan_msti_set = mv88e6xxx_vlan_msti_set,
6961 .port_fdb_add = mv88e6xxx_port_fdb_add,
6962 .port_fdb_del = mv88e6xxx_port_fdb_del,
6963 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
6964 .port_mdb_add = mv88e6xxx_port_mdb_add,
6965 .port_mdb_del = mv88e6xxx_port_mdb_del,
6966 .port_mirror_add = mv88e6xxx_port_mirror_add,
6967 .port_mirror_del = mv88e6xxx_port_mirror_del,
6968 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
6969 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
6970 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
6971 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
6972 .port_txtstamp = mv88e6xxx_port_txtstamp,
6973 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
6974 .get_ts_info = mv88e6xxx_get_ts_info,
6975 .devlink_param_get = mv88e6xxx_devlink_param_get,
6976 .devlink_param_set = mv88e6xxx_devlink_param_set,
6977 .devlink_info_get = mv88e6xxx_devlink_info_get,
6978 .port_lag_change = mv88e6xxx_port_lag_change,
6979 .port_lag_join = mv88e6xxx_port_lag_join,
6980 .port_lag_leave = mv88e6xxx_port_lag_leave,
6981 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change,
6982 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join,
6983 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave,
6984};
6985
6986static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
6987{
6988 struct device *dev = chip->dev;
6989 struct dsa_switch *ds;
6990
6991 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
6992 if (!ds)
6993 return -ENOMEM;
6994
6995 ds->dev = dev;
6996 ds->num_ports = mv88e6xxx_num_ports(chip);
6997 ds->priv = chip;
6998 ds->dev = dev;
6999 ds->ops = &mv88e6xxx_switch_ops;
7000 ds->ageing_time_min = chip->info->age_time_coeff;
7001 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
7002
7003 /* Some chips support up to 32, but that requires enabling the
7004 * 5-bit port mode, which we do not support. 640k^W16 ought to
7005 * be enough for anyone.
7006 */
7007 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
7008
7009 dev_set_drvdata(dev, ds);
7010
7011 return dsa_register_switch(ds);
7012}
7013
7014static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
7015{
7016 dsa_unregister_switch(chip->ds);
7017}
7018
7019static const void *pdata_device_get_match_data(struct device *dev)
7020{
7021 const struct of_device_id *matches = dev->driver->of_match_table;
7022 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
7023
7024 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
7025 matches++) {
7026 if (!strcmp(pdata->compatible, matches->compatible))
7027 return matches->data;
7028 }
7029 return NULL;
7030}
7031
7032/* There is no suspend to RAM support at DSA level yet, the switch configuration
7033 * would be lost after a power cycle so prevent it to be suspended.
7034 */
7035static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
7036{
7037 return -EOPNOTSUPP;
7038}
7039
7040static int __maybe_unused mv88e6xxx_resume(struct device *dev)
7041{
7042 return 0;
7043}
7044
7045static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
7046
7047static int mv88e6xxx_probe(struct mdio_device *mdiodev)
7048{
7049 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
7050 const struct mv88e6xxx_info *compat_info = NULL;
7051 struct device *dev = &mdiodev->dev;
7052 struct device_node *np = dev->of_node;
7053 struct mv88e6xxx_chip *chip;
7054 int port;
7055 int err;
7056
7057 if (!np && !pdata)
7058 return -EINVAL;
7059
7060 if (np)
7061 compat_info = of_device_get_match_data(dev);
7062
7063 if (pdata) {
7064 compat_info = pdata_device_get_match_data(dev);
7065
7066 if (!pdata->netdev)
7067 return -EINVAL;
7068
7069 for (port = 0; port < DSA_MAX_PORTS; port++) {
7070 if (!(pdata->enabled_ports & (1 << port)))
7071 continue;
7072 if (strcmp(pdata->cd.port_names[port], "cpu"))
7073 continue;
7074 pdata->cd.netdev[port] = &pdata->netdev->dev;
7075 break;
7076 }
7077 }
7078
7079 if (!compat_info)
7080 return -EINVAL;
7081
7082 chip = mv88e6xxx_alloc_chip(dev);
7083 if (!chip) {
7084 err = -ENOMEM;
7085 goto out;
7086 }
7087
7088 chip->info = compat_info;
7089
7090 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
7091 if (IS_ERR(chip->reset)) {
7092 err = PTR_ERR(chip->reset);
7093 goto out;
7094 }
7095 if (chip->reset)
7096 usleep_range(10000, 20000);
7097
7098 /* Detect if the device is configured in single chip addressing mode,
7099 * otherwise continue with address specific smi init/detection.
7100 */
7101 err = mv88e6xxx_single_chip_detect(chip, mdiodev);
7102 if (err) {
7103 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
7104 if (err)
7105 goto out;
7106
7107 err = mv88e6xxx_detect(chip);
7108 if (err)
7109 goto out;
7110 }
7111
7112 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
7113 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
7114 else
7115 chip->tag_protocol = DSA_TAG_PROTO_DSA;
7116
7117 mv88e6xxx_phy_init(chip);
7118
7119 if (chip->info->ops->get_eeprom) {
7120 if (np)
7121 of_property_read_u32(np, "eeprom-length",
7122 &chip->eeprom_len);
7123 else
7124 chip->eeprom_len = pdata->eeprom_len;
7125 }
7126
7127 mv88e6xxx_reg_lock(chip);
7128 err = mv88e6xxx_switch_reset(chip);
7129 mv88e6xxx_reg_unlock(chip);
7130 if (err)
7131 goto out;
7132
7133 if (np) {
7134 chip->irq = of_irq_get(np, 0);
7135 if (chip->irq == -EPROBE_DEFER) {
7136 err = chip->irq;
7137 goto out;
7138 }
7139 }
7140
7141 if (pdata)
7142 chip->irq = pdata->irq;
7143
7144 /* Has to be performed before the MDIO bus is created, because
7145 * the PHYs will link their interrupts to these interrupt
7146 * controllers
7147 */
7148 mv88e6xxx_reg_lock(chip);
7149 if (chip->irq > 0)
7150 err = mv88e6xxx_g1_irq_setup(chip);
7151 else
7152 err = mv88e6xxx_irq_poll_setup(chip);
7153 mv88e6xxx_reg_unlock(chip);
7154
7155 if (err)
7156 goto out;
7157
7158 if (chip->info->g2_irqs > 0) {
7159 err = mv88e6xxx_g2_irq_setup(chip);
7160 if (err)
7161 goto out_g1_irq;
7162 }
7163
7164 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
7165 if (err)
7166 goto out_g2_irq;
7167
7168 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
7169 if (err)
7170 goto out_g1_atu_prob_irq;
7171
7172 err = mv88e6xxx_register_switch(chip);
7173 if (err)
7174 goto out_g1_vtu_prob_irq;
7175
7176 return 0;
7177
7178out_g1_vtu_prob_irq:
7179 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7180out_g1_atu_prob_irq:
7181 mv88e6xxx_g1_atu_prob_irq_free(chip);
7182out_g2_irq:
7183 if (chip->info->g2_irqs > 0)
7184 mv88e6xxx_g2_irq_free(chip);
7185out_g1_irq:
7186 if (chip->irq > 0)
7187 mv88e6xxx_g1_irq_free(chip);
7188 else
7189 mv88e6xxx_irq_poll_free(chip);
7190out:
7191 if (pdata)
7192 dev_put(pdata->netdev);
7193
7194 return err;
7195}
7196
7197static void mv88e6xxx_remove(struct mdio_device *mdiodev)
7198{
7199 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7200 struct mv88e6xxx_chip *chip;
7201
7202 if (!ds)
7203 return;
7204
7205 chip = ds->priv;
7206
7207 if (chip->info->ptp_support) {
7208 mv88e6xxx_hwtstamp_free(chip);
7209 mv88e6xxx_ptp_free(chip);
7210 }
7211
7212 mv88e6xxx_phy_destroy(chip);
7213 mv88e6xxx_unregister_switch(chip);
7214
7215 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7216 mv88e6xxx_g1_atu_prob_irq_free(chip);
7217
7218 if (chip->info->g2_irqs > 0)
7219 mv88e6xxx_g2_irq_free(chip);
7220
7221 if (chip->irq > 0)
7222 mv88e6xxx_g1_irq_free(chip);
7223 else
7224 mv88e6xxx_irq_poll_free(chip);
7225}
7226
7227static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
7228{
7229 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7230
7231 if (!ds)
7232 return;
7233
7234 dsa_switch_shutdown(ds);
7235
7236 dev_set_drvdata(&mdiodev->dev, NULL);
7237}
7238
7239static const struct of_device_id mv88e6xxx_of_match[] = {
7240 {
7241 .compatible = "marvell,mv88e6085",
7242 .data = &mv88e6xxx_table[MV88E6085],
7243 },
7244 {
7245 .compatible = "marvell,mv88e6190",
7246 .data = &mv88e6xxx_table[MV88E6190],
7247 },
7248 {
7249 .compatible = "marvell,mv88e6250",
7250 .data = &mv88e6xxx_table[MV88E6250],
7251 },
7252 { /* sentinel */ },
7253};
7254
7255MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
7256
7257static struct mdio_driver mv88e6xxx_driver = {
7258 .probe = mv88e6xxx_probe,
7259 .remove = mv88e6xxx_remove,
7260 .shutdown = mv88e6xxx_shutdown,
7261 .mdiodrv.driver = {
7262 .name = "mv88e6085",
7263 .of_match_table = mv88e6xxx_of_match,
7264 .pm = &mv88e6xxx_pm_ops,
7265 },
7266};
7267
7268mdio_module_driver(mv88e6xxx_driver);
7269
7270MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
7271MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
7272MODULE_LICENSE("GPL");