1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Samsung Exynos5422 SoC cpu device tree source
  4 *
  5 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
  6 *		http://www.samsung.com
  7 *
  8 * This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
  9 *
 10 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
 11 * but particular boards choose different booting order.
 12 *
 13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
 14 * booting cluster (big or LITTLE) is chosen by IROM code by reading
 15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
 16 * from the LITTLE: Cortex-A7.
 17 */
 18
 19/ {
 20	cpus {
 21		#address-cells = <1>;
 22		#size-cells = <0>;
 23
 24		cpu0: cpu@100 {
 25			device_type = "cpu";
 26			compatible = "arm,cortex-a7";
 27			reg = <0x100>;
 28			clocks = <&clock CLK_KFC_CLK>;
 29			clock-frequency = <1000000000>;
 30			cci-control-port = <&cci_control0>;
 31			operating-points-v2 = <&cluster_a7_opp_table>;
 32			#cooling-cells = <2>; /* min followed by max */
 33			capacity-dmips-mhz = <539>;
 34			dynamic-power-coefficient = <90>;
 35		};
 36
 37		cpu1: cpu@101 {
 38			device_type = "cpu";
 39			compatible = "arm,cortex-a7";
 40			reg = <0x101>;
 41			clocks = <&clock CLK_KFC_CLK>;
 42			clock-frequency = <1000000000>;
 43			cci-control-port = <&cci_control0>;
 44			operating-points-v2 = <&cluster_a7_opp_table>;
 45			#cooling-cells = <2>; /* min followed by max */
 46			capacity-dmips-mhz = <539>;
 47			dynamic-power-coefficient = <90>;
 48		};
 49
 50		cpu2: cpu@102 {
 51			device_type = "cpu";
 52			compatible = "arm,cortex-a7";
 53			reg = <0x102>;
 54			clocks = <&clock CLK_KFC_CLK>;
 55			clock-frequency = <1000000000>;
 56			cci-control-port = <&cci_control0>;
 57			operating-points-v2 = <&cluster_a7_opp_table>;
 58			#cooling-cells = <2>; /* min followed by max */
 59			capacity-dmips-mhz = <539>;
 60			dynamic-power-coefficient = <90>;
 61		};
 62
 63		cpu3: cpu@103 {
 64			device_type = "cpu";
 65			compatible = "arm,cortex-a7";
 66			reg = <0x103>;
 67			clocks = <&clock CLK_KFC_CLK>;
 68			clock-frequency = <1000000000>;
 69			cci-control-port = <&cci_control0>;
 70			operating-points-v2 = <&cluster_a7_opp_table>;
 71			#cooling-cells = <2>; /* min followed by max */
 72			capacity-dmips-mhz = <539>;
 73			dynamic-power-coefficient = <90>;
 74		};
 75
 76		cpu4: cpu@0 {
 77			device_type = "cpu";
 78			compatible = "arm,cortex-a15";
 79			reg = <0x0>;
 80			clocks = <&clock CLK_ARM_CLK>;
 81			clock-frequency = <1800000000>;
 82			cci-control-port = <&cci_control1>;
 83			operating-points-v2 = <&cluster_a15_opp_table>;
 84			#cooling-cells = <2>; /* min followed by max */
 85			capacity-dmips-mhz = <1024>;
 86			dynamic-power-coefficient = <310>;
 87		};
 88
 89		cpu5: cpu@1 {
 90			device_type = "cpu";
 91			compatible = "arm,cortex-a15";
 92			reg = <0x1>;
 93			clocks = <&clock CLK_ARM_CLK>;
 94			clock-frequency = <1800000000>;
 95			cci-control-port = <&cci_control1>;
 96			operating-points-v2 = <&cluster_a15_opp_table>;
 97			#cooling-cells = <2>; /* min followed by max */
 98			capacity-dmips-mhz = <1024>;
 99			dynamic-power-coefficient = <310>;
100		};
101
102		cpu6: cpu@2 {
103			device_type = "cpu";
104			compatible = "arm,cortex-a15";
105			reg = <0x2>;
106			clocks = <&clock CLK_ARM_CLK>;
107			clock-frequency = <1800000000>;
108			cci-control-port = <&cci_control1>;
109			operating-points-v2 = <&cluster_a15_opp_table>;
110			#cooling-cells = <2>; /* min followed by max */
111			capacity-dmips-mhz = <1024>;
112			dynamic-power-coefficient = <310>;
113		};
114
115		cpu7: cpu@3 {
116			device_type = "cpu";
117			compatible = "arm,cortex-a15";
118			reg = <0x3>;
119			clocks = <&clock CLK_ARM_CLK>;
120			clock-frequency = <1800000000>;
121			cci-control-port = <&cci_control1>;
122			operating-points-v2 = <&cluster_a15_opp_table>;
123			#cooling-cells = <2>; /* min followed by max */
124			capacity-dmips-mhz = <1024>;
125			dynamic-power-coefficient = <310>;
126		};
127	};
128};
129
130&arm_a7_pmu {
131	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
132	status = "okay";
133};
134
135&arm_a15_pmu {
136	interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
137	status = "okay";
138};