1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * SAMSUNG EXYNOS5422 SoC cpu device tree source
  4 *
  5 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
  6 *		http://www.samsung.com
  7 *
  8 * This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
  9 *
 10 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
 11 * but particular boards choose different booting order.
 12 *
 13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
 14 * booting cluster (big or LITTLE) is chosen by IROM code by reading
 15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
 16 * from the LITTLE: Cortex-A7.
 17 */
 18
 19/ {
 20	cpus {
 21		#address-cells = <1>;
 22		#size-cells = <0>;
 23
 24		cpu0: cpu@100 {
 25			device_type = "cpu";
 26			compatible = "arm,cortex-a7";
 27			reg = <0x100>;
 28			clocks = <&clock CLK_KFC_CLK>;
 29			clock-frequency = <1000000000>;
 30			cci-control-port = <&cci_control0>;
 31			operating-points-v2 = <&cluster_a7_opp_table>;
 32			#cooling-cells = <2>; /* min followed by max */
 33			capacity-dmips-mhz = <539>;
 34		};
 35
 36		cpu1: cpu@101 {
 37			device_type = "cpu";
 38			compatible = "arm,cortex-a7";
 39			reg = <0x101>;
 40			clocks = <&clock CLK_KFC_CLK>;
 41			clock-frequency = <1000000000>;
 42			cci-control-port = <&cci_control0>;
 43			operating-points-v2 = <&cluster_a7_opp_table>;
 44			#cooling-cells = <2>; /* min followed by max */
 45			capacity-dmips-mhz = <539>;
 46		};
 47
 48		cpu2: cpu@102 {
 49			device_type = "cpu";
 50			compatible = "arm,cortex-a7";
 51			reg = <0x102>;
 52			clocks = <&clock CLK_KFC_CLK>;
 53			clock-frequency = <1000000000>;
 54			cci-control-port = <&cci_control0>;
 55			operating-points-v2 = <&cluster_a7_opp_table>;
 56			#cooling-cells = <2>; /* min followed by max */
 57			capacity-dmips-mhz = <539>;
 58		};
 59
 60		cpu3: cpu@103 {
 61			device_type = "cpu";
 62			compatible = "arm,cortex-a7";
 63			reg = <0x103>;
 64			clocks = <&clock CLK_KFC_CLK>;
 65			clock-frequency = <1000000000>;
 66			cci-control-port = <&cci_control0>;
 67			operating-points-v2 = <&cluster_a7_opp_table>;
 68			#cooling-cells = <2>; /* min followed by max */
 69			capacity-dmips-mhz = <539>;
 70		};
 71
 72		cpu4: cpu@0 {
 73			device_type = "cpu";
 74			compatible = "arm,cortex-a15";
 75			reg = <0x0>;
 76			clocks = <&clock CLK_ARM_CLK>;
 77			clock-frequency = <1800000000>;
 78			cci-control-port = <&cci_control1>;
 79			operating-points-v2 = <&cluster_a15_opp_table>;
 80			#cooling-cells = <2>; /* min followed by max */
 81			capacity-dmips-mhz = <1024>;
 82		};
 83
 84		cpu5: cpu@1 {
 85			device_type = "cpu";
 86			compatible = "arm,cortex-a15";
 87			reg = <0x1>;
 88			clocks = <&clock CLK_ARM_CLK>;
 89			clock-frequency = <1800000000>;
 90			cci-control-port = <&cci_control1>;
 91			operating-points-v2 = <&cluster_a15_opp_table>;
 92			#cooling-cells = <2>; /* min followed by max */
 93			capacity-dmips-mhz = <1024>;
 94		};
 95
 96		cpu6: cpu@2 {
 97			device_type = "cpu";
 98			compatible = "arm,cortex-a15";
 99			reg = <0x2>;
100			clocks = <&clock CLK_ARM_CLK>;
101			clock-frequency = <1800000000>;
102			cci-control-port = <&cci_control1>;
103			operating-points-v2 = <&cluster_a15_opp_table>;
104			#cooling-cells = <2>; /* min followed by max */
105			capacity-dmips-mhz = <1024>;
106		};
107
108		cpu7: cpu@3 {
109			device_type = "cpu";
110			compatible = "arm,cortex-a15";
111			reg = <0x3>;
112			clocks = <&clock CLK_ARM_CLK>;
113			clock-frequency = <1800000000>;
114			cci-control-port = <&cci_control1>;
115			operating-points-v2 = <&cluster_a15_opp_table>;
116			#cooling-cells = <2>; /* min followed by max */
117			capacity-dmips-mhz = <1024>;
118		};
119	};
120};
121
122&arm_a7_pmu {
123	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
124	status = "okay";
125};
126
127&arm_a15_pmu {
128	interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
129	status = "okay";
130};