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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2019, Intel Corporation. */
3
4#include <net/xdp_sock_drv.h>
5#include "ice_base.h"
6#include "ice_lib.h"
7#include "ice_dcb_lib.h"
8#include "ice_sriov.h"
9
10/**
11 * __ice_vsi_get_qs_contig - Assign a contiguous chunk of queues to VSI
12 * @qs_cfg: gathered variables needed for PF->VSI queues assignment
13 *
14 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap
15 */
16static int __ice_vsi_get_qs_contig(struct ice_qs_cfg *qs_cfg)
17{
18 unsigned int offset, i;
19
20 mutex_lock(qs_cfg->qs_mutex);
21 offset = bitmap_find_next_zero_area(qs_cfg->pf_map, qs_cfg->pf_map_size,
22 0, qs_cfg->q_count, 0);
23 if (offset >= qs_cfg->pf_map_size) {
24 mutex_unlock(qs_cfg->qs_mutex);
25 return -ENOMEM;
26 }
27
28 bitmap_set(qs_cfg->pf_map, offset, qs_cfg->q_count);
29 for (i = 0; i < qs_cfg->q_count; i++)
30 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = (u16)(i + offset);
31 mutex_unlock(qs_cfg->qs_mutex);
32
33 return 0;
34}
35
36/**
37 * __ice_vsi_get_qs_sc - Assign a scattered queues from PF to VSI
38 * @qs_cfg: gathered variables needed for pf->vsi queues assignment
39 *
40 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap
41 */
42static int __ice_vsi_get_qs_sc(struct ice_qs_cfg *qs_cfg)
43{
44 unsigned int i, index = 0;
45
46 mutex_lock(qs_cfg->qs_mutex);
47 for (i = 0; i < qs_cfg->q_count; i++) {
48 index = find_next_zero_bit(qs_cfg->pf_map,
49 qs_cfg->pf_map_size, index);
50 if (index >= qs_cfg->pf_map_size)
51 goto err_scatter;
52 set_bit(index, qs_cfg->pf_map);
53 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = (u16)index;
54 }
55 mutex_unlock(qs_cfg->qs_mutex);
56
57 return 0;
58err_scatter:
59 for (index = 0; index < i; index++) {
60 clear_bit(qs_cfg->vsi_map[index], qs_cfg->pf_map);
61 qs_cfg->vsi_map[index + qs_cfg->vsi_map_offset] = 0;
62 }
63 mutex_unlock(qs_cfg->qs_mutex);
64
65 return -ENOMEM;
66}
67
68/**
69 * ice_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
70 * @pf: the PF being configured
71 * @pf_q: the PF queue
72 * @ena: enable or disable state of the queue
73 *
74 * This routine will wait for the given Rx queue of the PF to reach the
75 * enabled or disabled state.
76 * Returns -ETIMEDOUT in case of failing to reach the requested state after
77 * multiple retries; else will return 0 in case of success.
78 */
79static int ice_pf_rxq_wait(struct ice_pf *pf, int pf_q, bool ena)
80{
81 int i;
82
83 for (i = 0; i < ICE_Q_WAIT_MAX_RETRY; i++) {
84 if (ena == !!(rd32(&pf->hw, QRX_CTRL(pf_q)) &
85 QRX_CTRL_QENA_STAT_M))
86 return 0;
87
88 usleep_range(20, 40);
89 }
90
91 return -ETIMEDOUT;
92}
93
94/**
95 * ice_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
96 * @vsi: the VSI being configured
97 * @v_idx: index of the vector in the VSI struct
98 *
99 * We allocate one q_vector and set default value for ITR setting associated
100 * with this q_vector. If allocation fails we return -ENOMEM.
101 */
102static int ice_vsi_alloc_q_vector(struct ice_vsi *vsi, u16 v_idx)
103{
104 struct ice_pf *pf = vsi->back;
105 struct ice_q_vector *q_vector;
106 int err;
107
108 /* allocate q_vector */
109 q_vector = kzalloc(sizeof(*q_vector), GFP_KERNEL);
110 if (!q_vector)
111 return -ENOMEM;
112
113 q_vector->vsi = vsi;
114 q_vector->v_idx = v_idx;
115 q_vector->tx.itr_setting = ICE_DFLT_TX_ITR;
116 q_vector->rx.itr_setting = ICE_DFLT_RX_ITR;
117 q_vector->tx.itr_mode = ITR_DYNAMIC;
118 q_vector->rx.itr_mode = ITR_DYNAMIC;
119 q_vector->tx.type = ICE_TX_CONTAINER;
120 q_vector->rx.type = ICE_RX_CONTAINER;
121 q_vector->irq.index = -ENOENT;
122
123 if (vsi->type == ICE_VSI_VF) {
124 ice_calc_vf_reg_idx(vsi->vf, q_vector);
125 goto out;
126 } else if (vsi->type == ICE_VSI_CTRL && vsi->vf) {
127 struct ice_vsi *ctrl_vsi = ice_get_vf_ctrl_vsi(pf, vsi);
128
129 if (ctrl_vsi) {
130 if (unlikely(!ctrl_vsi->q_vectors)) {
131 err = -ENOENT;
132 goto err_free_q_vector;
133 }
134
135 q_vector->irq = ctrl_vsi->q_vectors[0]->irq;
136 goto skip_alloc;
137 }
138 }
139
140 q_vector->irq = ice_alloc_irq(pf, vsi->irq_dyn_alloc);
141 if (q_vector->irq.index < 0) {
142 err = -ENOMEM;
143 goto err_free_q_vector;
144 }
145
146skip_alloc:
147 q_vector->reg_idx = q_vector->irq.index;
148 q_vector->vf_reg_idx = q_vector->irq.index;
149
150 /* only set affinity_mask if the CPU is online */
151 if (cpu_online(v_idx))
152 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
153
154 /* This will not be called in the driver load path because the netdev
155 * will not be created yet. All other cases with register the NAPI
156 * handler here (i.e. resume, reset/rebuild, etc.)
157 */
158 if (vsi->netdev)
159 netif_napi_add_config(vsi->netdev, &q_vector->napi,
160 ice_napi_poll, v_idx);
161
162out:
163 /* tie q_vector and VSI together */
164 vsi->q_vectors[v_idx] = q_vector;
165
166 return 0;
167
168err_free_q_vector:
169 kfree(q_vector);
170
171 return err;
172}
173
174/**
175 * ice_free_q_vector - Free memory allocated for a specific interrupt vector
176 * @vsi: VSI having the memory freed
177 * @v_idx: index of the vector to be freed
178 */
179static void ice_free_q_vector(struct ice_vsi *vsi, int v_idx)
180{
181 struct ice_q_vector *q_vector;
182 struct ice_pf *pf = vsi->back;
183 struct ice_tx_ring *tx_ring;
184 struct ice_rx_ring *rx_ring;
185 struct device *dev;
186
187 dev = ice_pf_to_dev(pf);
188 if (!vsi->q_vectors[v_idx]) {
189 dev_dbg(dev, "Queue vector at index %d not found\n", v_idx);
190 return;
191 }
192 q_vector = vsi->q_vectors[v_idx];
193
194 ice_for_each_tx_ring(tx_ring, vsi->q_vectors[v_idx]->tx)
195 tx_ring->q_vector = NULL;
196
197 ice_for_each_rx_ring(rx_ring, vsi->q_vectors[v_idx]->rx)
198 rx_ring->q_vector = NULL;
199
200 /* only VSI with an associated netdev is set up with NAPI */
201 if (vsi->netdev)
202 netif_napi_del(&q_vector->napi);
203
204 /* release MSIX interrupt if q_vector had interrupt allocated */
205 if (q_vector->irq.index < 0)
206 goto free_q_vector;
207
208 /* only free last VF ctrl vsi interrupt */
209 if (vsi->type == ICE_VSI_CTRL && vsi->vf &&
210 ice_get_vf_ctrl_vsi(pf, vsi))
211 goto free_q_vector;
212
213 ice_free_irq(pf, q_vector->irq);
214
215free_q_vector:
216 kfree(q_vector);
217 vsi->q_vectors[v_idx] = NULL;
218}
219
220/**
221 * ice_cfg_itr_gran - set the ITR granularity to 2 usecs if not already set
222 * @hw: board specific structure
223 */
224static void ice_cfg_itr_gran(struct ice_hw *hw)
225{
226 u32 regval = rd32(hw, GLINT_CTL);
227
228 /* no need to update global register if ITR gran is already set */
229 if (!(regval & GLINT_CTL_DIS_AUTOMASK_M) &&
230 (FIELD_GET(GLINT_CTL_ITR_GRAN_200_M, regval) == ICE_ITR_GRAN_US) &&
231 (FIELD_GET(GLINT_CTL_ITR_GRAN_100_M, regval) == ICE_ITR_GRAN_US) &&
232 (FIELD_GET(GLINT_CTL_ITR_GRAN_50_M, regval) == ICE_ITR_GRAN_US) &&
233 (FIELD_GET(GLINT_CTL_ITR_GRAN_25_M, regval) == ICE_ITR_GRAN_US))
234 return;
235
236 regval = FIELD_PREP(GLINT_CTL_ITR_GRAN_200_M, ICE_ITR_GRAN_US) |
237 FIELD_PREP(GLINT_CTL_ITR_GRAN_100_M, ICE_ITR_GRAN_US) |
238 FIELD_PREP(GLINT_CTL_ITR_GRAN_50_M, ICE_ITR_GRAN_US) |
239 FIELD_PREP(GLINT_CTL_ITR_GRAN_25_M, ICE_ITR_GRAN_US);
240 wr32(hw, GLINT_CTL, regval);
241}
242
243/**
244 * ice_calc_txq_handle - calculate the queue handle
245 * @vsi: VSI that ring belongs to
246 * @ring: ring to get the absolute queue index
247 * @tc: traffic class number
248 */
249static u16 ice_calc_txq_handle(struct ice_vsi *vsi, struct ice_tx_ring *ring, u8 tc)
250{
251 WARN_ONCE(ice_ring_is_xdp(ring) && tc, "XDP ring can't belong to TC other than 0\n");
252
253 if (ring->ch)
254 return ring->q_index - ring->ch->base_q;
255
256 /* Idea here for calculation is that we subtract the number of queue
257 * count from TC that ring belongs to from it's absolute queue index
258 * and as a result we get the queue's index within TC.
259 */
260 return ring->q_index - vsi->tc_cfg.tc_info[tc].qoffset;
261}
262
263/**
264 * ice_cfg_xps_tx_ring - Configure XPS for a Tx ring
265 * @ring: The Tx ring to configure
266 *
267 * This enables/disables XPS for a given Tx descriptor ring
268 * based on the TCs enabled for the VSI that ring belongs to.
269 */
270static void ice_cfg_xps_tx_ring(struct ice_tx_ring *ring)
271{
272 if (!ring->q_vector || !ring->netdev)
273 return;
274
275 /* We only initialize XPS once, so as not to overwrite user settings */
276 if (test_and_set_bit(ICE_TX_XPS_INIT_DONE, ring->xps_state))
277 return;
278
279 netif_set_xps_queue(ring->netdev, &ring->q_vector->affinity_mask,
280 ring->q_index);
281}
282
283/**
284 * ice_setup_tx_ctx - setup a struct ice_tlan_ctx instance
285 * @ring: The Tx ring to configure
286 * @tlan_ctx: Pointer to the Tx LAN queue context structure to be initialized
287 * @pf_q: queue index in the PF space
288 *
289 * Configure the Tx descriptor ring in TLAN context.
290 */
291static void
292ice_setup_tx_ctx(struct ice_tx_ring *ring, struct ice_tlan_ctx *tlan_ctx, u16 pf_q)
293{
294 struct ice_vsi *vsi = ring->vsi;
295 struct ice_hw *hw = &vsi->back->hw;
296
297 tlan_ctx->base = ring->dma >> ICE_TLAN_CTX_BASE_S;
298
299 tlan_ctx->port_num = vsi->port_info->lport;
300
301 /* Transmit Queue Length */
302 tlan_ctx->qlen = ring->count;
303
304 ice_set_cgd_num(tlan_ctx, ring->dcb_tc);
305
306 /* PF number */
307 tlan_ctx->pf_num = hw->pf_id;
308
309 /* queue belongs to a specific VSI type
310 * VF / VM index should be programmed per vmvf_type setting:
311 * for vmvf_type = VF, it is VF number between 0-256
312 * for vmvf_type = VM, it is VM number between 0-767
313 * for PF or EMP this field should be set to zero
314 */
315 switch (vsi->type) {
316 case ICE_VSI_LB:
317 case ICE_VSI_CTRL:
318 case ICE_VSI_PF:
319 if (ring->ch)
320 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VMQ;
321 else
322 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
323 break;
324 case ICE_VSI_VF:
325 /* Firmware expects vmvf_num to be absolute VF ID */
326 tlan_ctx->vmvf_num = hw->func_caps.vf_base_id + vsi->vf->vf_id;
327 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VF;
328 break;
329 case ICE_VSI_SF:
330 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VMQ;
331 break;
332 default:
333 return;
334 }
335
336 /* make sure the context is associated with the right VSI */
337 if (ring->ch)
338 tlan_ctx->src_vsi = ring->ch->vsi_num;
339 else
340 tlan_ctx->src_vsi = ice_get_hw_vsi_num(hw, vsi->idx);
341
342 /* Restrict Tx timestamps to the PF VSI */
343 switch (vsi->type) {
344 case ICE_VSI_PF:
345 tlan_ctx->tsyn_ena = 1;
346 break;
347 default:
348 break;
349 }
350
351 tlan_ctx->quanta_prof_idx = ring->quanta_prof_id;
352
353 tlan_ctx->tso_ena = ICE_TX_LEGACY;
354 tlan_ctx->tso_qnum = pf_q;
355
356 /* Legacy or Advanced Host Interface:
357 * 0: Advanced Host Interface
358 * 1: Legacy Host Interface
359 */
360 tlan_ctx->legacy_int = ICE_TX_LEGACY;
361}
362
363/**
364 * ice_rx_offset - Return expected offset into page to access data
365 * @rx_ring: Ring we are requesting offset of
366 *
367 * Returns the offset value for ring into the data buffer.
368 */
369static unsigned int ice_rx_offset(struct ice_rx_ring *rx_ring)
370{
371 if (ice_ring_uses_build_skb(rx_ring))
372 return ICE_SKB_PAD;
373 return 0;
374}
375
376/**
377 * ice_setup_rx_ctx - Configure a receive ring context
378 * @ring: The Rx ring to configure
379 *
380 * Configure the Rx descriptor ring in RLAN context.
381 */
382static int ice_setup_rx_ctx(struct ice_rx_ring *ring)
383{
384 struct ice_vsi *vsi = ring->vsi;
385 u32 rxdid = ICE_RXDID_FLEX_NIC;
386 struct ice_rlan_ctx rlan_ctx;
387 struct ice_hw *hw;
388 u16 pf_q;
389 int err;
390
391 hw = &vsi->back->hw;
392
393 /* what is Rx queue number in global space of 2K Rx queues */
394 pf_q = vsi->rxq_map[ring->q_index];
395
396 /* clear the context structure first */
397 memset(&rlan_ctx, 0, sizeof(rlan_ctx));
398
399 /* Receive Queue Base Address.
400 * Indicates the starting address of the descriptor queue defined in
401 * 128 Byte units.
402 */
403 rlan_ctx.base = ring->dma >> ICE_RLAN_BASE_S;
404
405 rlan_ctx.qlen = ring->count;
406
407 /* Receive Packet Data Buffer Size.
408 * The Packet Data Buffer Size is defined in 128 byte units.
409 */
410 rlan_ctx.dbuf = DIV_ROUND_UP(ring->rx_buf_len,
411 BIT_ULL(ICE_RLAN_CTX_DBUF_S));
412
413 /* use 32 byte descriptors */
414 rlan_ctx.dsize = 1;
415
416 /* Strip the Ethernet CRC bytes before the packet is posted to host
417 * memory.
418 */
419 rlan_ctx.crcstrip = !(ring->flags & ICE_RX_FLAGS_CRC_STRIP_DIS);
420
421 /* L2TSEL flag defines the reported L2 Tags in the receive descriptor
422 * and it needs to remain 1 for non-DVM capable configurations to not
423 * break backward compatibility for VF drivers. Setting this field to 0
424 * will cause the single/outer VLAN tag to be stripped to the L2TAG2_2ND
425 * field in the Rx descriptor. Setting it to 1 allows the VLAN tag to
426 * be stripped in L2TAG1 of the Rx descriptor, which is where VFs will
427 * check for the tag
428 */
429 if (ice_is_dvm_ena(hw))
430 if (vsi->type == ICE_VSI_VF &&
431 ice_vf_is_port_vlan_ena(vsi->vf))
432 rlan_ctx.l2tsel = 1;
433 else
434 rlan_ctx.l2tsel = 0;
435 else
436 rlan_ctx.l2tsel = 1;
437
438 rlan_ctx.dtype = ICE_RX_DTYPE_NO_SPLIT;
439 rlan_ctx.hsplit_0 = ICE_RLAN_RX_HSPLIT_0_NO_SPLIT;
440 rlan_ctx.hsplit_1 = ICE_RLAN_RX_HSPLIT_1_NO_SPLIT;
441
442 /* This controls whether VLAN is stripped from inner headers
443 * The VLAN in the inner L2 header is stripped to the receive
444 * descriptor if enabled by this flag.
445 */
446 rlan_ctx.showiv = 0;
447
448 /* Max packet size for this queue - must not be set to a larger value
449 * than 5 x DBUF
450 */
451 rlan_ctx.rxmax = min_t(u32, ring->max_frame,
452 ICE_MAX_CHAINED_RX_BUFS * ring->rx_buf_len);
453
454 /* Rx queue threshold in units of 64 */
455 rlan_ctx.lrxqthresh = 1;
456
457 /* PF acts as uplink for switchdev; set flex descriptor with src_vsi
458 * metadata and flags to allow redirecting to PR netdev
459 */
460 if (ice_is_eswitch_mode_switchdev(vsi->back)) {
461 ring->flags |= ICE_RX_FLAGS_MULTIDEV;
462 rxdid = ICE_RXDID_FLEX_NIC_2;
463 }
464
465 /* Enable Flexible Descriptors in the queue context which
466 * allows this driver to select a specific receive descriptor format
467 * increasing context priority to pick up profile ID; default is 0x01;
468 * setting to 0x03 to ensure profile is programming if prev context is
469 * of same priority
470 */
471 if (vsi->type != ICE_VSI_VF)
472 ice_write_qrxflxp_cntxt(hw, pf_q, rxdid, 0x3, true);
473 else
474 ice_write_qrxflxp_cntxt(hw, pf_q, ICE_RXDID_LEGACY_1, 0x3,
475 false);
476
477 /* Absolute queue number out of 2K needs to be passed */
478 err = ice_write_rxq_ctx(hw, &rlan_ctx, pf_q);
479 if (err) {
480 dev_err(ice_pf_to_dev(vsi->back), "Failed to set LAN Rx queue context for absolute Rx queue %d error: %d\n",
481 pf_q, err);
482 return -EIO;
483 }
484
485 if (vsi->type == ICE_VSI_VF)
486 return 0;
487
488 /* configure Rx buffer alignment */
489 if (!vsi->netdev || test_bit(ICE_FLAG_LEGACY_RX, vsi->back->flags))
490 ice_clear_ring_build_skb_ena(ring);
491 else
492 ice_set_ring_build_skb_ena(ring);
493
494 ring->rx_offset = ice_rx_offset(ring);
495
496 /* init queue specific tail register */
497 ring->tail = hw->hw_addr + QRX_TAIL(pf_q);
498 writel(0, ring->tail);
499
500 return 0;
501}
502
503static void ice_xsk_pool_fill_cb(struct ice_rx_ring *ring)
504{
505 void *ctx_ptr = &ring->pkt_ctx;
506 struct xsk_cb_desc desc = {};
507
508 XSK_CHECK_PRIV_TYPE(struct ice_xdp_buff);
509 desc.src = &ctx_ptr;
510 desc.off = offsetof(struct ice_xdp_buff, pkt_ctx) -
511 sizeof(struct xdp_buff);
512 desc.bytes = sizeof(ctx_ptr);
513 xsk_pool_fill_cb(ring->xsk_pool, &desc);
514}
515
516/**
517 * ice_get_frame_sz - calculate xdp_buff::frame_sz
518 * @rx_ring: the ring being configured
519 *
520 * Return frame size based on underlying PAGE_SIZE
521 */
522static unsigned int ice_get_frame_sz(struct ice_rx_ring *rx_ring)
523{
524 unsigned int frame_sz;
525
526#if (PAGE_SIZE >= 8192)
527 frame_sz = rx_ring->rx_buf_len;
528#else
529 frame_sz = ice_rx_pg_size(rx_ring) / 2;
530#endif
531
532 return frame_sz;
533}
534
535/**
536 * ice_vsi_cfg_rxq - Configure an Rx queue
537 * @ring: the ring being configured
538 *
539 * Return 0 on success and a negative value on error.
540 */
541static int ice_vsi_cfg_rxq(struct ice_rx_ring *ring)
542{
543 struct device *dev = ice_pf_to_dev(ring->vsi->back);
544 u32 num_bufs = ICE_RX_DESC_UNUSED(ring);
545 int err;
546
547 if (ring->vsi->type == ICE_VSI_PF || ring->vsi->type == ICE_VSI_SF) {
548 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq)) {
549 err = __xdp_rxq_info_reg(&ring->xdp_rxq, ring->netdev,
550 ring->q_index,
551 ring->q_vector->napi.napi_id,
552 ring->rx_buf_len);
553 if (err)
554 return err;
555 }
556
557 ice_rx_xsk_pool(ring);
558 if (ring->xsk_pool) {
559 xdp_rxq_info_unreg(&ring->xdp_rxq);
560
561 ring->rx_buf_len =
562 xsk_pool_get_rx_frame_size(ring->xsk_pool);
563 err = __xdp_rxq_info_reg(&ring->xdp_rxq, ring->netdev,
564 ring->q_index,
565 ring->q_vector->napi.napi_id,
566 ring->rx_buf_len);
567 if (err)
568 return err;
569 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
570 MEM_TYPE_XSK_BUFF_POOL,
571 NULL);
572 if (err)
573 return err;
574 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq);
575 ice_xsk_pool_fill_cb(ring);
576
577 dev_info(dev, "Registered XDP mem model MEM_TYPE_XSK_BUFF_POOL on Rx ring %d\n",
578 ring->q_index);
579 } else {
580 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq)) {
581 err = __xdp_rxq_info_reg(&ring->xdp_rxq, ring->netdev,
582 ring->q_index,
583 ring->q_vector->napi.napi_id,
584 ring->rx_buf_len);
585 if (err)
586 return err;
587 }
588
589 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
590 MEM_TYPE_PAGE_SHARED,
591 NULL);
592 if (err)
593 return err;
594 }
595 }
596
597 xdp_init_buff(&ring->xdp, ice_get_frame_sz(ring), &ring->xdp_rxq);
598 ring->xdp.data = NULL;
599 ring->xdp_ext.pkt_ctx = &ring->pkt_ctx;
600 err = ice_setup_rx_ctx(ring);
601 if (err) {
602 dev_err(dev, "ice_setup_rx_ctx failed for RxQ %d, err %d\n",
603 ring->q_index, err);
604 return err;
605 }
606
607 if (ring->xsk_pool) {
608 bool ok;
609
610 if (!xsk_buff_can_alloc(ring->xsk_pool, num_bufs)) {
611 dev_warn(dev, "XSK buffer pool does not provide enough addresses to fill %d buffers on Rx ring %d\n",
612 num_bufs, ring->q_index);
613 dev_warn(dev, "Change Rx ring/fill queue size to avoid performance issues\n");
614
615 return 0;
616 }
617
618 ok = ice_alloc_rx_bufs_zc(ring, ring->xsk_pool, num_bufs);
619 if (!ok) {
620 u16 pf_q = ring->vsi->rxq_map[ring->q_index];
621
622 dev_info(dev, "Failed to allocate some buffers on XSK buffer pool enabled Rx ring %d (pf_q %d)\n",
623 ring->q_index, pf_q);
624 }
625
626 return 0;
627 }
628
629 ice_alloc_rx_bufs(ring, num_bufs);
630
631 return 0;
632}
633
634int ice_vsi_cfg_single_rxq(struct ice_vsi *vsi, u16 q_idx)
635{
636 if (q_idx >= vsi->num_rxq)
637 return -EINVAL;
638
639 return ice_vsi_cfg_rxq(vsi->rx_rings[q_idx]);
640}
641
642/**
643 * ice_vsi_cfg_frame_size - setup max frame size and Rx buffer length
644 * @vsi: VSI
645 * @ring: Rx ring to configure
646 *
647 * Determine the maximum frame size and Rx buffer length to use for a PF VSI.
648 * Set these in the associated Rx ring structure.
649 */
650static void ice_vsi_cfg_frame_size(struct ice_vsi *vsi, struct ice_rx_ring *ring)
651{
652 if (!vsi->netdev || test_bit(ICE_FLAG_LEGACY_RX, vsi->back->flags)) {
653 ring->max_frame = ICE_MAX_FRAME_LEGACY_RX;
654 ring->rx_buf_len = ICE_RXBUF_1664;
655#if (PAGE_SIZE < 8192)
656 } else if (!ICE_2K_TOO_SMALL_WITH_PADDING &&
657 (vsi->netdev->mtu <= ETH_DATA_LEN)) {
658 ring->max_frame = ICE_RXBUF_1536 - NET_IP_ALIGN;
659 ring->rx_buf_len = ICE_RXBUF_1536 - NET_IP_ALIGN;
660#endif
661 } else {
662 ring->max_frame = ICE_AQ_SET_MAC_FRAME_SIZE_MAX;
663 ring->rx_buf_len = ICE_RXBUF_3072;
664 }
665}
666
667/**
668 * ice_vsi_cfg_rxqs - Configure the VSI for Rx
669 * @vsi: the VSI being configured
670 *
671 * Return 0 on success and a negative value on error
672 * Configure the Rx VSI for operation.
673 */
674int ice_vsi_cfg_rxqs(struct ice_vsi *vsi)
675{
676 u16 i;
677
678 /* set up individual rings */
679 ice_for_each_rxq(vsi, i) {
680 struct ice_rx_ring *ring = vsi->rx_rings[i];
681 int err;
682
683 if (vsi->type != ICE_VSI_VF)
684 ice_vsi_cfg_frame_size(vsi, ring);
685
686 err = ice_vsi_cfg_rxq(ring);
687 if (err)
688 return err;
689 }
690
691 return 0;
692}
693
694/**
695 * __ice_vsi_get_qs - helper function for assigning queues from PF to VSI
696 * @qs_cfg: gathered variables needed for pf->vsi queues assignment
697 *
698 * This function first tries to find contiguous space. If it is not successful,
699 * it tries with the scatter approach.
700 *
701 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap
702 */
703int __ice_vsi_get_qs(struct ice_qs_cfg *qs_cfg)
704{
705 int ret = 0;
706
707 ret = __ice_vsi_get_qs_contig(qs_cfg);
708 if (ret) {
709 /* contig failed, so try with scatter approach */
710 qs_cfg->mapping_mode = ICE_VSI_MAP_SCATTER;
711 qs_cfg->q_count = min_t(unsigned int, qs_cfg->q_count,
712 qs_cfg->scatter_count);
713 ret = __ice_vsi_get_qs_sc(qs_cfg);
714 }
715 return ret;
716}
717
718/**
719 * ice_vsi_ctrl_one_rx_ring - start/stop VSI's Rx ring with no busy wait
720 * @vsi: the VSI being configured
721 * @ena: start or stop the Rx ring
722 * @rxq_idx: 0-based Rx queue index for the VSI passed in
723 * @wait: wait or don't wait for configuration to finish in hardware
724 *
725 * Return 0 on success and negative on error.
726 */
727int
728ice_vsi_ctrl_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx, bool wait)
729{
730 int pf_q = vsi->rxq_map[rxq_idx];
731 struct ice_pf *pf = vsi->back;
732 struct ice_hw *hw = &pf->hw;
733 u32 rx_reg;
734
735 rx_reg = rd32(hw, QRX_CTRL(pf_q));
736
737 /* Skip if the queue is already in the requested state */
738 if (ena == !!(rx_reg & QRX_CTRL_QENA_STAT_M))
739 return 0;
740
741 /* turn on/off the queue */
742 if (ena)
743 rx_reg |= QRX_CTRL_QENA_REQ_M;
744 else
745 rx_reg &= ~QRX_CTRL_QENA_REQ_M;
746 wr32(hw, QRX_CTRL(pf_q), rx_reg);
747
748 if (!wait)
749 return 0;
750
751 ice_flush(hw);
752 return ice_pf_rxq_wait(pf, pf_q, ena);
753}
754
755/**
756 * ice_vsi_wait_one_rx_ring - wait for a VSI's Rx ring to be stopped/started
757 * @vsi: the VSI being configured
758 * @ena: true/false to verify Rx ring has been enabled/disabled respectively
759 * @rxq_idx: 0-based Rx queue index for the VSI passed in
760 *
761 * This routine will wait for the given Rx queue of the VSI to reach the
762 * enabled or disabled state. Returns -ETIMEDOUT in case of failing to reach
763 * the requested state after multiple retries; else will return 0 in case of
764 * success.
765 */
766int ice_vsi_wait_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx)
767{
768 int pf_q = vsi->rxq_map[rxq_idx];
769 struct ice_pf *pf = vsi->back;
770
771 return ice_pf_rxq_wait(pf, pf_q, ena);
772}
773
774/**
775 * ice_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
776 * @vsi: the VSI being configured
777 *
778 * We allocate one q_vector per queue interrupt. If allocation fails we
779 * return -ENOMEM.
780 */
781int ice_vsi_alloc_q_vectors(struct ice_vsi *vsi)
782{
783 struct device *dev = ice_pf_to_dev(vsi->back);
784 u16 v_idx;
785 int err;
786
787 if (vsi->q_vectors[0]) {
788 dev_dbg(dev, "VSI %d has existing q_vectors\n", vsi->vsi_num);
789 return -EEXIST;
790 }
791
792 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++) {
793 err = ice_vsi_alloc_q_vector(vsi, v_idx);
794 if (err)
795 goto err_out;
796 }
797
798 return 0;
799
800err_out:
801 while (v_idx--)
802 ice_free_q_vector(vsi, v_idx);
803
804 dev_err(dev, "Failed to allocate %d q_vector for VSI %d, ret=%d\n",
805 vsi->num_q_vectors, vsi->vsi_num, err);
806 vsi->num_q_vectors = 0;
807 return err;
808}
809
810/**
811 * ice_vsi_map_rings_to_vectors - Map VSI rings to interrupt vectors
812 * @vsi: the VSI being configured
813 *
814 * This function maps descriptor rings to the queue-specific vectors allotted
815 * through the MSI-X enabling code. On a constrained vector budget, we map Tx
816 * and Rx rings to the vector as "efficiently" as possible.
817 */
818void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi)
819{
820 int q_vectors = vsi->num_q_vectors;
821 u16 tx_rings_rem, rx_rings_rem;
822 int v_id;
823
824 /* initially assigning remaining rings count to VSIs num queue value */
825 tx_rings_rem = vsi->num_txq;
826 rx_rings_rem = vsi->num_rxq;
827
828 for (v_id = 0; v_id < q_vectors; v_id++) {
829 struct ice_q_vector *q_vector = vsi->q_vectors[v_id];
830 u8 tx_rings_per_v, rx_rings_per_v;
831 u16 q_id, q_base;
832
833 /* Tx rings mapping to vector */
834 tx_rings_per_v = (u8)DIV_ROUND_UP(tx_rings_rem,
835 q_vectors - v_id);
836 q_vector->num_ring_tx = tx_rings_per_v;
837 q_vector->tx.tx_ring = NULL;
838 q_vector->tx.itr_idx = ICE_TX_ITR;
839 q_base = vsi->num_txq - tx_rings_rem;
840
841 for (q_id = q_base; q_id < (q_base + tx_rings_per_v); q_id++) {
842 struct ice_tx_ring *tx_ring = vsi->tx_rings[q_id];
843
844 tx_ring->q_vector = q_vector;
845 tx_ring->next = q_vector->tx.tx_ring;
846 q_vector->tx.tx_ring = tx_ring;
847 }
848 tx_rings_rem -= tx_rings_per_v;
849
850 /* Rx rings mapping to vector */
851 rx_rings_per_v = (u8)DIV_ROUND_UP(rx_rings_rem,
852 q_vectors - v_id);
853 q_vector->num_ring_rx = rx_rings_per_v;
854 q_vector->rx.rx_ring = NULL;
855 q_vector->rx.itr_idx = ICE_RX_ITR;
856 q_base = vsi->num_rxq - rx_rings_rem;
857
858 for (q_id = q_base; q_id < (q_base + rx_rings_per_v); q_id++) {
859 struct ice_rx_ring *rx_ring = vsi->rx_rings[q_id];
860
861 rx_ring->q_vector = q_vector;
862 rx_ring->next = q_vector->rx.rx_ring;
863 q_vector->rx.rx_ring = rx_ring;
864 }
865 rx_rings_rem -= rx_rings_per_v;
866 }
867
868 if (ice_is_xdp_ena_vsi(vsi))
869 ice_map_xdp_rings(vsi);
870}
871
872/**
873 * ice_vsi_free_q_vectors - Free memory allocated for interrupt vectors
874 * @vsi: the VSI having memory freed
875 */
876void ice_vsi_free_q_vectors(struct ice_vsi *vsi)
877{
878 int v_idx;
879
880 ice_for_each_q_vector(vsi, v_idx)
881 ice_free_q_vector(vsi, v_idx);
882
883 vsi->num_q_vectors = 0;
884}
885
886/**
887 * ice_vsi_cfg_txq - Configure single Tx queue
888 * @vsi: the VSI that queue belongs to
889 * @ring: Tx ring to be configured
890 * @qg_buf: queue group buffer
891 */
892static int
893ice_vsi_cfg_txq(struct ice_vsi *vsi, struct ice_tx_ring *ring,
894 struct ice_aqc_add_tx_qgrp *qg_buf)
895{
896 u8 buf_len = struct_size(qg_buf, txqs, 1);
897 struct ice_tlan_ctx tlan_ctx = { 0 };
898 struct ice_aqc_add_txqs_perq *txq;
899 struct ice_channel *ch = ring->ch;
900 struct ice_pf *pf = vsi->back;
901 struct ice_hw *hw = &pf->hw;
902 int status;
903 u16 pf_q;
904 u8 tc;
905
906 /* Configure XPS */
907 ice_cfg_xps_tx_ring(ring);
908
909 pf_q = ring->reg_idx;
910 ice_setup_tx_ctx(ring, &tlan_ctx, pf_q);
911 /* copy context contents into the qg_buf */
912 qg_buf->txqs[0].txq_id = cpu_to_le16(pf_q);
913 ice_set_ctx(hw, (u8 *)&tlan_ctx, qg_buf->txqs[0].txq_ctx,
914 ice_tlan_ctx_info);
915
916 /* init queue specific tail reg. It is referred as
917 * transmit comm scheduler queue doorbell.
918 */
919 ring->tail = hw->hw_addr + QTX_COMM_DBELL(pf_q);
920
921 if (IS_ENABLED(CONFIG_DCB))
922 tc = ring->dcb_tc;
923 else
924 tc = 0;
925
926 /* Add unique software queue handle of the Tx queue per
927 * TC into the VSI Tx ring
928 */
929 ring->q_handle = ice_calc_txq_handle(vsi, ring, tc);
930
931 if (ch)
932 status = ice_ena_vsi_txq(vsi->port_info, ch->ch_vsi->idx, 0,
933 ring->q_handle, 1, qg_buf, buf_len,
934 NULL);
935 else
936 status = ice_ena_vsi_txq(vsi->port_info, vsi->idx, tc,
937 ring->q_handle, 1, qg_buf, buf_len,
938 NULL);
939 if (status) {
940 dev_err(ice_pf_to_dev(pf), "Failed to set LAN Tx queue context, error: %d\n",
941 status);
942 return status;
943 }
944
945 /* Add Tx Queue TEID into the VSI Tx ring from the
946 * response. This will complete configuring and
947 * enabling the queue.
948 */
949 txq = &qg_buf->txqs[0];
950 if (pf_q == le16_to_cpu(txq->txq_id))
951 ring->txq_teid = le32_to_cpu(txq->q_teid);
952
953 return 0;
954}
955
956int ice_vsi_cfg_single_txq(struct ice_vsi *vsi, struct ice_tx_ring **tx_rings,
957 u16 q_idx)
958{
959 DEFINE_RAW_FLEX(struct ice_aqc_add_tx_qgrp, qg_buf, txqs, 1);
960
961 if (q_idx >= vsi->alloc_txq || !tx_rings || !tx_rings[q_idx])
962 return -EINVAL;
963
964 qg_buf->num_txqs = 1;
965
966 return ice_vsi_cfg_txq(vsi, tx_rings[q_idx], qg_buf);
967}
968
969/**
970 * ice_vsi_cfg_txqs - Configure the VSI for Tx
971 * @vsi: the VSI being configured
972 * @rings: Tx ring array to be configured
973 * @count: number of Tx ring array elements
974 *
975 * Return 0 on success and a negative value on error
976 * Configure the Tx VSI for operation.
977 */
978static int
979ice_vsi_cfg_txqs(struct ice_vsi *vsi, struct ice_tx_ring **rings, u16 count)
980{
981 DEFINE_RAW_FLEX(struct ice_aqc_add_tx_qgrp, qg_buf, txqs, 1);
982 int err = 0;
983 u16 q_idx;
984
985 qg_buf->num_txqs = 1;
986
987 for (q_idx = 0; q_idx < count; q_idx++) {
988 err = ice_vsi_cfg_txq(vsi, rings[q_idx], qg_buf);
989 if (err)
990 break;
991 }
992
993 return err;
994}
995
996/**
997 * ice_vsi_cfg_lan_txqs - Configure the VSI for Tx
998 * @vsi: the VSI being configured
999 *
1000 * Return 0 on success and a negative value on error
1001 * Configure the Tx VSI for operation.
1002 */
1003int ice_vsi_cfg_lan_txqs(struct ice_vsi *vsi)
1004{
1005 return ice_vsi_cfg_txqs(vsi, vsi->tx_rings, vsi->num_txq);
1006}
1007
1008/**
1009 * ice_vsi_cfg_xdp_txqs - Configure Tx queues dedicated for XDP in given VSI
1010 * @vsi: the VSI being configured
1011 *
1012 * Return 0 on success and a negative value on error
1013 * Configure the Tx queues dedicated for XDP in given VSI for operation.
1014 */
1015int ice_vsi_cfg_xdp_txqs(struct ice_vsi *vsi)
1016{
1017 int ret;
1018 int i;
1019
1020 ret = ice_vsi_cfg_txqs(vsi, vsi->xdp_rings, vsi->num_xdp_txq);
1021 if (ret)
1022 return ret;
1023
1024 ice_for_each_rxq(vsi, i)
1025 ice_tx_xsk_pool(vsi, i);
1026
1027 return 0;
1028}
1029
1030/**
1031 * ice_cfg_itr - configure the initial interrupt throttle values
1032 * @hw: pointer to the HW structure
1033 * @q_vector: interrupt vector that's being configured
1034 *
1035 * Configure interrupt throttling values for the ring containers that are
1036 * associated with the interrupt vector passed in.
1037 */
1038void ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector)
1039{
1040 ice_cfg_itr_gran(hw);
1041
1042 if (q_vector->num_ring_rx)
1043 ice_write_itr(&q_vector->rx, q_vector->rx.itr_setting);
1044
1045 if (q_vector->num_ring_tx)
1046 ice_write_itr(&q_vector->tx, q_vector->tx.itr_setting);
1047
1048 ice_write_intrl(q_vector, q_vector->intrl);
1049}
1050
1051/**
1052 * ice_cfg_txq_interrupt - configure interrupt on Tx queue
1053 * @vsi: the VSI being configured
1054 * @txq: Tx queue being mapped to MSI-X vector
1055 * @msix_idx: MSI-X vector index within the function
1056 * @itr_idx: ITR index of the interrupt cause
1057 *
1058 * Configure interrupt on Tx queue by associating Tx queue to MSI-X vector
1059 * within the function space.
1060 */
1061void
1062ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx)
1063{
1064 struct ice_pf *pf = vsi->back;
1065 struct ice_hw *hw = &pf->hw;
1066 u32 val;
1067
1068 itr_idx = FIELD_PREP(QINT_TQCTL_ITR_INDX_M, itr_idx);
1069
1070 val = QINT_TQCTL_CAUSE_ENA_M | itr_idx |
1071 FIELD_PREP(QINT_TQCTL_MSIX_INDX_M, msix_idx);
1072
1073 wr32(hw, QINT_TQCTL(vsi->txq_map[txq]), val);
1074 if (ice_is_xdp_ena_vsi(vsi)) {
1075 u32 xdp_txq = txq + vsi->num_xdp_txq;
1076
1077 wr32(hw, QINT_TQCTL(vsi->txq_map[xdp_txq]),
1078 val);
1079 }
1080 ice_flush(hw);
1081}
1082
1083/**
1084 * ice_cfg_rxq_interrupt - configure interrupt on Rx queue
1085 * @vsi: the VSI being configured
1086 * @rxq: Rx queue being mapped to MSI-X vector
1087 * @msix_idx: MSI-X vector index within the function
1088 * @itr_idx: ITR index of the interrupt cause
1089 *
1090 * Configure interrupt on Rx queue by associating Rx queue to MSI-X vector
1091 * within the function space.
1092 */
1093void
1094ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx)
1095{
1096 struct ice_pf *pf = vsi->back;
1097 struct ice_hw *hw = &pf->hw;
1098 u32 val;
1099
1100 itr_idx = FIELD_PREP(QINT_RQCTL_ITR_INDX_M, itr_idx);
1101
1102 val = QINT_RQCTL_CAUSE_ENA_M | itr_idx |
1103 FIELD_PREP(QINT_RQCTL_MSIX_INDX_M, msix_idx);
1104
1105 wr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), val);
1106
1107 ice_flush(hw);
1108}
1109
1110/**
1111 * ice_trigger_sw_intr - trigger a software interrupt
1112 * @hw: pointer to the HW structure
1113 * @q_vector: interrupt vector to trigger the software interrupt for
1114 */
1115void ice_trigger_sw_intr(struct ice_hw *hw, const struct ice_q_vector *q_vector)
1116{
1117 wr32(hw, GLINT_DYN_CTL(q_vector->reg_idx),
1118 (ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S) |
1119 GLINT_DYN_CTL_SWINT_TRIG_M |
1120 GLINT_DYN_CTL_INTENA_M);
1121}
1122
1123/**
1124 * ice_vsi_stop_tx_ring - Disable single Tx ring
1125 * @vsi: the VSI being configured
1126 * @rst_src: reset source
1127 * @rel_vmvf_num: Relative ID of VF/VM
1128 * @ring: Tx ring to be stopped
1129 * @txq_meta: Meta data of Tx ring to be stopped
1130 */
1131int
1132ice_vsi_stop_tx_ring(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src,
1133 u16 rel_vmvf_num, struct ice_tx_ring *ring,
1134 struct ice_txq_meta *txq_meta)
1135{
1136 struct ice_pf *pf = vsi->back;
1137 struct ice_q_vector *q_vector;
1138 struct ice_hw *hw = &pf->hw;
1139 int status;
1140 u32 val;
1141
1142 /* clear cause_ena bit for disabled queues */
1143 val = rd32(hw, QINT_TQCTL(ring->reg_idx));
1144 val &= ~QINT_TQCTL_CAUSE_ENA_M;
1145 wr32(hw, QINT_TQCTL(ring->reg_idx), val);
1146
1147 /* software is expected to wait for 100 ns */
1148 ndelay(100);
1149
1150 /* trigger a software interrupt for the vector
1151 * associated to the queue to schedule NAPI handler
1152 */
1153 q_vector = ring->q_vector;
1154 if (q_vector && !(vsi->vf && ice_is_vf_disabled(vsi->vf)))
1155 ice_trigger_sw_intr(hw, q_vector);
1156
1157 status = ice_dis_vsi_txq(vsi->port_info, txq_meta->vsi_idx,
1158 txq_meta->tc, 1, &txq_meta->q_handle,
1159 &txq_meta->q_id, &txq_meta->q_teid, rst_src,
1160 rel_vmvf_num, NULL);
1161
1162 /* if the disable queue command was exercised during an
1163 * active reset flow, -EBUSY is returned.
1164 * This is not an error as the reset operation disables
1165 * queues at the hardware level anyway.
1166 */
1167 if (status == -EBUSY) {
1168 dev_dbg(ice_pf_to_dev(vsi->back), "Reset in progress. LAN Tx queues already disabled\n");
1169 } else if (status == -ENOENT) {
1170 dev_dbg(ice_pf_to_dev(vsi->back), "LAN Tx queues do not exist, nothing to disable\n");
1171 } else if (status) {
1172 dev_dbg(ice_pf_to_dev(vsi->back), "Failed to disable LAN Tx queues, error: %d\n",
1173 status);
1174 return status;
1175 }
1176
1177 return 0;
1178}
1179
1180/**
1181 * ice_fill_txq_meta - Prepare the Tx queue's meta data
1182 * @vsi: VSI that ring belongs to
1183 * @ring: ring that txq_meta will be based on
1184 * @txq_meta: a helper struct that wraps Tx queue's information
1185 *
1186 * Set up a helper struct that will contain all the necessary fields that
1187 * are needed for stopping Tx queue
1188 */
1189void
1190ice_fill_txq_meta(const struct ice_vsi *vsi, struct ice_tx_ring *ring,
1191 struct ice_txq_meta *txq_meta)
1192{
1193 struct ice_channel *ch = ring->ch;
1194 u8 tc;
1195
1196 if (IS_ENABLED(CONFIG_DCB))
1197 tc = ring->dcb_tc;
1198 else
1199 tc = 0;
1200
1201 txq_meta->q_id = ring->reg_idx;
1202 txq_meta->q_teid = ring->txq_teid;
1203 txq_meta->q_handle = ring->q_handle;
1204 if (ch) {
1205 txq_meta->vsi_idx = ch->ch_vsi->idx;
1206 txq_meta->tc = 0;
1207 } else {
1208 txq_meta->vsi_idx = vsi->idx;
1209 txq_meta->tc = tc;
1210 }
1211}
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2019, Intel Corporation. */
3
4#include <net/xdp_sock_drv.h>
5#include "ice_base.h"
6#include "ice_lib.h"
7#include "ice_dcb_lib.h"
8
9/**
10 * __ice_vsi_get_qs_contig - Assign a contiguous chunk of queues to VSI
11 * @qs_cfg: gathered variables needed for PF->VSI queues assignment
12 *
13 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap
14 */
15static int __ice_vsi_get_qs_contig(struct ice_qs_cfg *qs_cfg)
16{
17 unsigned int offset, i;
18
19 mutex_lock(qs_cfg->qs_mutex);
20 offset = bitmap_find_next_zero_area(qs_cfg->pf_map, qs_cfg->pf_map_size,
21 0, qs_cfg->q_count, 0);
22 if (offset >= qs_cfg->pf_map_size) {
23 mutex_unlock(qs_cfg->qs_mutex);
24 return -ENOMEM;
25 }
26
27 bitmap_set(qs_cfg->pf_map, offset, qs_cfg->q_count);
28 for (i = 0; i < qs_cfg->q_count; i++)
29 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = (u16)(i + offset);
30 mutex_unlock(qs_cfg->qs_mutex);
31
32 return 0;
33}
34
35/**
36 * __ice_vsi_get_qs_sc - Assign a scattered queues from PF to VSI
37 * @qs_cfg: gathered variables needed for pf->vsi queues assignment
38 *
39 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap
40 */
41static int __ice_vsi_get_qs_sc(struct ice_qs_cfg *qs_cfg)
42{
43 unsigned int i, index = 0;
44
45 mutex_lock(qs_cfg->qs_mutex);
46 for (i = 0; i < qs_cfg->q_count; i++) {
47 index = find_next_zero_bit(qs_cfg->pf_map,
48 qs_cfg->pf_map_size, index);
49 if (index >= qs_cfg->pf_map_size)
50 goto err_scatter;
51 set_bit(index, qs_cfg->pf_map);
52 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = (u16)index;
53 }
54 mutex_unlock(qs_cfg->qs_mutex);
55
56 return 0;
57err_scatter:
58 for (index = 0; index < i; index++) {
59 clear_bit(qs_cfg->vsi_map[index], qs_cfg->pf_map);
60 qs_cfg->vsi_map[index + qs_cfg->vsi_map_offset] = 0;
61 }
62 mutex_unlock(qs_cfg->qs_mutex);
63
64 return -ENOMEM;
65}
66
67/**
68 * ice_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
69 * @pf: the PF being configured
70 * @pf_q: the PF queue
71 * @ena: enable or disable state of the queue
72 *
73 * This routine will wait for the given Rx queue of the PF to reach the
74 * enabled or disabled state.
75 * Returns -ETIMEDOUT in case of failing to reach the requested state after
76 * multiple retries; else will return 0 in case of success.
77 */
78static int ice_pf_rxq_wait(struct ice_pf *pf, int pf_q, bool ena)
79{
80 int i;
81
82 for (i = 0; i < ICE_Q_WAIT_MAX_RETRY; i++) {
83 if (ena == !!(rd32(&pf->hw, QRX_CTRL(pf_q)) &
84 QRX_CTRL_QENA_STAT_M))
85 return 0;
86
87 usleep_range(20, 40);
88 }
89
90 return -ETIMEDOUT;
91}
92
93/**
94 * ice_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
95 * @vsi: the VSI being configured
96 * @v_idx: index of the vector in the VSI struct
97 *
98 * We allocate one q_vector and set default value for ITR setting associated
99 * with this q_vector. If allocation fails we return -ENOMEM.
100 */
101static int ice_vsi_alloc_q_vector(struct ice_vsi *vsi, u16 v_idx)
102{
103 struct ice_pf *pf = vsi->back;
104 struct ice_q_vector *q_vector;
105
106 /* allocate q_vector */
107 q_vector = devm_kzalloc(ice_pf_to_dev(pf), sizeof(*q_vector),
108 GFP_KERNEL);
109 if (!q_vector)
110 return -ENOMEM;
111
112 q_vector->vsi = vsi;
113 q_vector->v_idx = v_idx;
114 q_vector->tx.itr_setting = ICE_DFLT_TX_ITR;
115 q_vector->rx.itr_setting = ICE_DFLT_RX_ITR;
116 q_vector->tx.itr_mode = ITR_DYNAMIC;
117 q_vector->rx.itr_mode = ITR_DYNAMIC;
118
119 if (vsi->type == ICE_VSI_VF)
120 goto out;
121 /* only set affinity_mask if the CPU is online */
122 if (cpu_online(v_idx))
123 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
124
125 /* This will not be called in the driver load path because the netdev
126 * will not be created yet. All other cases with register the NAPI
127 * handler here (i.e. resume, reset/rebuild, etc.)
128 */
129 if (vsi->netdev)
130 netif_napi_add(vsi->netdev, &q_vector->napi, ice_napi_poll,
131 NAPI_POLL_WEIGHT);
132
133out:
134 /* tie q_vector and VSI together */
135 vsi->q_vectors[v_idx] = q_vector;
136
137 return 0;
138}
139
140/**
141 * ice_free_q_vector - Free memory allocated for a specific interrupt vector
142 * @vsi: VSI having the memory freed
143 * @v_idx: index of the vector to be freed
144 */
145static void ice_free_q_vector(struct ice_vsi *vsi, int v_idx)
146{
147 struct ice_q_vector *q_vector;
148 struct ice_pf *pf = vsi->back;
149 struct ice_ring *ring;
150 struct device *dev;
151
152 dev = ice_pf_to_dev(pf);
153 if (!vsi->q_vectors[v_idx]) {
154 dev_dbg(dev, "Queue vector at index %d not found\n", v_idx);
155 return;
156 }
157 q_vector = vsi->q_vectors[v_idx];
158
159 ice_for_each_ring(ring, q_vector->tx)
160 ring->q_vector = NULL;
161 ice_for_each_ring(ring, q_vector->rx)
162 ring->q_vector = NULL;
163
164 /* only VSI with an associated netdev is set up with NAPI */
165 if (vsi->netdev)
166 netif_napi_del(&q_vector->napi);
167
168 devm_kfree(dev, q_vector);
169 vsi->q_vectors[v_idx] = NULL;
170}
171
172/**
173 * ice_cfg_itr_gran - set the ITR granularity to 2 usecs if not already set
174 * @hw: board specific structure
175 */
176static void ice_cfg_itr_gran(struct ice_hw *hw)
177{
178 u32 regval = rd32(hw, GLINT_CTL);
179
180 /* no need to update global register if ITR gran is already set */
181 if (!(regval & GLINT_CTL_DIS_AUTOMASK_M) &&
182 (((regval & GLINT_CTL_ITR_GRAN_200_M) >>
183 GLINT_CTL_ITR_GRAN_200_S) == ICE_ITR_GRAN_US) &&
184 (((regval & GLINT_CTL_ITR_GRAN_100_M) >>
185 GLINT_CTL_ITR_GRAN_100_S) == ICE_ITR_GRAN_US) &&
186 (((regval & GLINT_CTL_ITR_GRAN_50_M) >>
187 GLINT_CTL_ITR_GRAN_50_S) == ICE_ITR_GRAN_US) &&
188 (((regval & GLINT_CTL_ITR_GRAN_25_M) >>
189 GLINT_CTL_ITR_GRAN_25_S) == ICE_ITR_GRAN_US))
190 return;
191
192 regval = ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_200_S) &
193 GLINT_CTL_ITR_GRAN_200_M) |
194 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_100_S) &
195 GLINT_CTL_ITR_GRAN_100_M) |
196 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_50_S) &
197 GLINT_CTL_ITR_GRAN_50_M) |
198 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_25_S) &
199 GLINT_CTL_ITR_GRAN_25_M);
200 wr32(hw, GLINT_CTL, regval);
201}
202
203/**
204 * ice_calc_q_handle - calculate the queue handle
205 * @vsi: VSI that ring belongs to
206 * @ring: ring to get the absolute queue index
207 * @tc: traffic class number
208 */
209static u16 ice_calc_q_handle(struct ice_vsi *vsi, struct ice_ring *ring, u8 tc)
210{
211 WARN_ONCE(ice_ring_is_xdp(ring) && tc, "XDP ring can't belong to TC other than 0\n");
212
213 /* Idea here for calculation is that we subtract the number of queue
214 * count from TC that ring belongs to from it's absolute queue index
215 * and as a result we get the queue's index within TC.
216 */
217 return ring->q_index - vsi->tc_cfg.tc_info[tc].qoffset;
218}
219
220/**
221 * ice_cfg_xps_tx_ring - Configure XPS for a Tx ring
222 * @ring: The Tx ring to configure
223 *
224 * This enables/disables XPS for a given Tx descriptor ring
225 * based on the TCs enabled for the VSI that ring belongs to.
226 */
227static void ice_cfg_xps_tx_ring(struct ice_ring *ring)
228{
229 if (!ring->q_vector || !ring->netdev)
230 return;
231
232 /* We only initialize XPS once, so as not to overwrite user settings */
233 if (test_and_set_bit(ICE_TX_XPS_INIT_DONE, ring->xps_state))
234 return;
235
236 netif_set_xps_queue(ring->netdev, &ring->q_vector->affinity_mask,
237 ring->q_index);
238}
239
240/**
241 * ice_setup_tx_ctx - setup a struct ice_tlan_ctx instance
242 * @ring: The Tx ring to configure
243 * @tlan_ctx: Pointer to the Tx LAN queue context structure to be initialized
244 * @pf_q: queue index in the PF space
245 *
246 * Configure the Tx descriptor ring in TLAN context.
247 */
248static void
249ice_setup_tx_ctx(struct ice_ring *ring, struct ice_tlan_ctx *tlan_ctx, u16 pf_q)
250{
251 struct ice_vsi *vsi = ring->vsi;
252 struct ice_hw *hw = &vsi->back->hw;
253
254 tlan_ctx->base = ring->dma >> ICE_TLAN_CTX_BASE_S;
255
256 tlan_ctx->port_num = vsi->port_info->lport;
257
258 /* Transmit Queue Length */
259 tlan_ctx->qlen = ring->count;
260
261 ice_set_cgd_num(tlan_ctx, ring);
262
263 /* PF number */
264 tlan_ctx->pf_num = hw->pf_id;
265
266 /* queue belongs to a specific VSI type
267 * VF / VM index should be programmed per vmvf_type setting:
268 * for vmvf_type = VF, it is VF number between 0-256
269 * for vmvf_type = VM, it is VM number between 0-767
270 * for PF or EMP this field should be set to zero
271 */
272 switch (vsi->type) {
273 case ICE_VSI_LB:
274 case ICE_VSI_CTRL:
275 case ICE_VSI_PF:
276 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
277 break;
278 case ICE_VSI_VF:
279 /* Firmware expects vmvf_num to be absolute VF ID */
280 tlan_ctx->vmvf_num = hw->func_caps.vf_base_id + vsi->vf_id;
281 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VF;
282 break;
283 default:
284 return;
285 }
286
287 /* make sure the context is associated with the right VSI */
288 tlan_ctx->src_vsi = ice_get_hw_vsi_num(hw, vsi->idx);
289
290 /* Restrict Tx timestamps to the PF VSI */
291 switch (vsi->type) {
292 case ICE_VSI_PF:
293 tlan_ctx->tsyn_ena = 1;
294 break;
295 default:
296 break;
297 }
298
299 tlan_ctx->tso_ena = ICE_TX_LEGACY;
300 tlan_ctx->tso_qnum = pf_q;
301
302 /* Legacy or Advanced Host Interface:
303 * 0: Advanced Host Interface
304 * 1: Legacy Host Interface
305 */
306 tlan_ctx->legacy_int = ICE_TX_LEGACY;
307}
308
309/**
310 * ice_rx_offset - Return expected offset into page to access data
311 * @rx_ring: Ring we are requesting offset of
312 *
313 * Returns the offset value for ring into the data buffer.
314 */
315static unsigned int ice_rx_offset(struct ice_ring *rx_ring)
316{
317 if (ice_ring_uses_build_skb(rx_ring))
318 return ICE_SKB_PAD;
319 else if (ice_is_xdp_ena_vsi(rx_ring->vsi))
320 return XDP_PACKET_HEADROOM;
321
322 return 0;
323}
324
325/**
326 * ice_setup_rx_ctx - Configure a receive ring context
327 * @ring: The Rx ring to configure
328 *
329 * Configure the Rx descriptor ring in RLAN context.
330 */
331static int ice_setup_rx_ctx(struct ice_ring *ring)
332{
333 int chain_len = ICE_MAX_CHAINED_RX_BUFS;
334 struct ice_vsi *vsi = ring->vsi;
335 u32 rxdid = ICE_RXDID_FLEX_NIC;
336 struct ice_rlan_ctx rlan_ctx;
337 struct ice_hw *hw;
338 u16 pf_q;
339 int err;
340
341 hw = &vsi->back->hw;
342
343 /* what is Rx queue number in global space of 2K Rx queues */
344 pf_q = vsi->rxq_map[ring->q_index];
345
346 /* clear the context structure first */
347 memset(&rlan_ctx, 0, sizeof(rlan_ctx));
348
349 /* Receive Queue Base Address.
350 * Indicates the starting address of the descriptor queue defined in
351 * 128 Byte units.
352 */
353 rlan_ctx.base = ring->dma >> 7;
354
355 rlan_ctx.qlen = ring->count;
356
357 /* Receive Packet Data Buffer Size.
358 * The Packet Data Buffer Size is defined in 128 byte units.
359 */
360 rlan_ctx.dbuf = ring->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
361
362 /* use 32 byte descriptors */
363 rlan_ctx.dsize = 1;
364
365 /* Strip the Ethernet CRC bytes before the packet is posted to host
366 * memory.
367 */
368 rlan_ctx.crcstrip = 1;
369
370 /* L2TSEL flag defines the reported L2 Tags in the receive descriptor */
371 rlan_ctx.l2tsel = 1;
372
373 rlan_ctx.dtype = ICE_RX_DTYPE_NO_SPLIT;
374 rlan_ctx.hsplit_0 = ICE_RLAN_RX_HSPLIT_0_NO_SPLIT;
375 rlan_ctx.hsplit_1 = ICE_RLAN_RX_HSPLIT_1_NO_SPLIT;
376
377 /* This controls whether VLAN is stripped from inner headers
378 * The VLAN in the inner L2 header is stripped to the receive
379 * descriptor if enabled by this flag.
380 */
381 rlan_ctx.showiv = 0;
382
383 /* For AF_XDP ZC, we disallow packets to span on
384 * multiple buffers, thus letting us skip that
385 * handling in the fast-path.
386 */
387 if (ring->xsk_pool)
388 chain_len = 1;
389 /* Max packet size for this queue - must not be set to a larger value
390 * than 5 x DBUF
391 */
392 rlan_ctx.rxmax = min_t(u32, vsi->max_frame,
393 chain_len * ring->rx_buf_len);
394
395 /* Rx queue threshold in units of 64 */
396 rlan_ctx.lrxqthresh = 1;
397
398 /* Enable Flexible Descriptors in the queue context which
399 * allows this driver to select a specific receive descriptor format
400 * increasing context priority to pick up profile ID; default is 0x01;
401 * setting to 0x03 to ensure profile is programming if prev context is
402 * of same priority
403 */
404 if (vsi->type != ICE_VSI_VF)
405 ice_write_qrxflxp_cntxt(hw, pf_q, rxdid, 0x3, true);
406 else
407 ice_write_qrxflxp_cntxt(hw, pf_q, ICE_RXDID_LEGACY_1, 0x3,
408 false);
409
410 /* Absolute queue number out of 2K needs to be passed */
411 err = ice_write_rxq_ctx(hw, &rlan_ctx, pf_q);
412 if (err) {
413 dev_err(ice_pf_to_dev(vsi->back), "Failed to set LAN Rx queue context for absolute Rx queue %d error: %d\n",
414 pf_q, err);
415 return -EIO;
416 }
417
418 if (vsi->type == ICE_VSI_VF)
419 return 0;
420
421 /* configure Rx buffer alignment */
422 if (!vsi->netdev || test_bit(ICE_FLAG_LEGACY_RX, vsi->back->flags))
423 ice_clear_ring_build_skb_ena(ring);
424 else
425 ice_set_ring_build_skb_ena(ring);
426
427 ring->rx_offset = ice_rx_offset(ring);
428
429 /* init queue specific tail register */
430 ring->tail = hw->hw_addr + QRX_TAIL(pf_q);
431 writel(0, ring->tail);
432
433 return 0;
434}
435
436/**
437 * ice_vsi_cfg_rxq - Configure an Rx queue
438 * @ring: the ring being configured
439 *
440 * Return 0 on success and a negative value on error.
441 */
442int ice_vsi_cfg_rxq(struct ice_ring *ring)
443{
444 struct device *dev = ice_pf_to_dev(ring->vsi->back);
445 u16 num_bufs = ICE_DESC_UNUSED(ring);
446 int err;
447
448 ring->rx_buf_len = ring->vsi->rx_buf_len;
449
450 if (ring->vsi->type == ICE_VSI_PF) {
451 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq))
452 /* coverity[check_return] */
453 xdp_rxq_info_reg(&ring->xdp_rxq, ring->netdev,
454 ring->q_index, ring->q_vector->napi.napi_id);
455
456 ring->xsk_pool = ice_xsk_pool(ring);
457 if (ring->xsk_pool) {
458 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq);
459
460 ring->rx_buf_len =
461 xsk_pool_get_rx_frame_size(ring->xsk_pool);
462 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
463 MEM_TYPE_XSK_BUFF_POOL,
464 NULL);
465 if (err)
466 return err;
467 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq);
468
469 dev_info(dev, "Registered XDP mem model MEM_TYPE_XSK_BUFF_POOL on Rx ring %d\n",
470 ring->q_index);
471 } else {
472 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq))
473 /* coverity[check_return] */
474 xdp_rxq_info_reg(&ring->xdp_rxq,
475 ring->netdev,
476 ring->q_index, ring->q_vector->napi.napi_id);
477
478 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
479 MEM_TYPE_PAGE_SHARED,
480 NULL);
481 if (err)
482 return err;
483 }
484 }
485
486 err = ice_setup_rx_ctx(ring);
487 if (err) {
488 dev_err(dev, "ice_setup_rx_ctx failed for RxQ %d, err %d\n",
489 ring->q_index, err);
490 return err;
491 }
492
493 if (ring->xsk_pool) {
494 bool ok;
495
496 if (!xsk_buff_can_alloc(ring->xsk_pool, num_bufs)) {
497 dev_warn(dev, "XSK buffer pool does not provide enough addresses to fill %d buffers on Rx ring %d\n",
498 num_bufs, ring->q_index);
499 dev_warn(dev, "Change Rx ring/fill queue size to avoid performance issues\n");
500
501 return 0;
502 }
503
504 ok = ice_alloc_rx_bufs_zc(ring, num_bufs);
505 if (!ok) {
506 u16 pf_q = ring->vsi->rxq_map[ring->q_index];
507
508 dev_info(dev, "Failed to allocate some buffers on XSK buffer pool enabled Rx ring %d (pf_q %d)\n",
509 ring->q_index, pf_q);
510 }
511
512 return 0;
513 }
514
515 ice_alloc_rx_bufs(ring, num_bufs);
516
517 return 0;
518}
519
520/**
521 * __ice_vsi_get_qs - helper function for assigning queues from PF to VSI
522 * @qs_cfg: gathered variables needed for pf->vsi queues assignment
523 *
524 * This function first tries to find contiguous space. If it is not successful,
525 * it tries with the scatter approach.
526 *
527 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap
528 */
529int __ice_vsi_get_qs(struct ice_qs_cfg *qs_cfg)
530{
531 int ret = 0;
532
533 ret = __ice_vsi_get_qs_contig(qs_cfg);
534 if (ret) {
535 /* contig failed, so try with scatter approach */
536 qs_cfg->mapping_mode = ICE_VSI_MAP_SCATTER;
537 qs_cfg->q_count = min_t(unsigned int, qs_cfg->q_count,
538 qs_cfg->scatter_count);
539 ret = __ice_vsi_get_qs_sc(qs_cfg);
540 }
541 return ret;
542}
543
544/**
545 * ice_vsi_ctrl_one_rx_ring - start/stop VSI's Rx ring with no busy wait
546 * @vsi: the VSI being configured
547 * @ena: start or stop the Rx ring
548 * @rxq_idx: 0-based Rx queue index for the VSI passed in
549 * @wait: wait or don't wait for configuration to finish in hardware
550 *
551 * Return 0 on success and negative on error.
552 */
553int
554ice_vsi_ctrl_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx, bool wait)
555{
556 int pf_q = vsi->rxq_map[rxq_idx];
557 struct ice_pf *pf = vsi->back;
558 struct ice_hw *hw = &pf->hw;
559 u32 rx_reg;
560
561 rx_reg = rd32(hw, QRX_CTRL(pf_q));
562
563 /* Skip if the queue is already in the requested state */
564 if (ena == !!(rx_reg & QRX_CTRL_QENA_STAT_M))
565 return 0;
566
567 /* turn on/off the queue */
568 if (ena)
569 rx_reg |= QRX_CTRL_QENA_REQ_M;
570 else
571 rx_reg &= ~QRX_CTRL_QENA_REQ_M;
572 wr32(hw, QRX_CTRL(pf_q), rx_reg);
573
574 if (!wait)
575 return 0;
576
577 ice_flush(hw);
578 return ice_pf_rxq_wait(pf, pf_q, ena);
579}
580
581/**
582 * ice_vsi_wait_one_rx_ring - wait for a VSI's Rx ring to be stopped/started
583 * @vsi: the VSI being configured
584 * @ena: true/false to verify Rx ring has been enabled/disabled respectively
585 * @rxq_idx: 0-based Rx queue index for the VSI passed in
586 *
587 * This routine will wait for the given Rx queue of the VSI to reach the
588 * enabled or disabled state. Returns -ETIMEDOUT in case of failing to reach
589 * the requested state after multiple retries; else will return 0 in case of
590 * success.
591 */
592int ice_vsi_wait_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx)
593{
594 int pf_q = vsi->rxq_map[rxq_idx];
595 struct ice_pf *pf = vsi->back;
596
597 return ice_pf_rxq_wait(pf, pf_q, ena);
598}
599
600/**
601 * ice_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
602 * @vsi: the VSI being configured
603 *
604 * We allocate one q_vector per queue interrupt. If allocation fails we
605 * return -ENOMEM.
606 */
607int ice_vsi_alloc_q_vectors(struct ice_vsi *vsi)
608{
609 struct device *dev = ice_pf_to_dev(vsi->back);
610 u16 v_idx;
611 int err;
612
613 if (vsi->q_vectors[0]) {
614 dev_dbg(dev, "VSI %d has existing q_vectors\n", vsi->vsi_num);
615 return -EEXIST;
616 }
617
618 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++) {
619 err = ice_vsi_alloc_q_vector(vsi, v_idx);
620 if (err)
621 goto err_out;
622 }
623
624 return 0;
625
626err_out:
627 while (v_idx--)
628 ice_free_q_vector(vsi, v_idx);
629
630 dev_err(dev, "Failed to allocate %d q_vector for VSI %d, ret=%d\n",
631 vsi->num_q_vectors, vsi->vsi_num, err);
632 vsi->num_q_vectors = 0;
633 return err;
634}
635
636/**
637 * ice_vsi_map_rings_to_vectors - Map VSI rings to interrupt vectors
638 * @vsi: the VSI being configured
639 *
640 * This function maps descriptor rings to the queue-specific vectors allotted
641 * through the MSI-X enabling code. On a constrained vector budget, we map Tx
642 * and Rx rings to the vector as "efficiently" as possible.
643 */
644void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi)
645{
646 int q_vectors = vsi->num_q_vectors;
647 u16 tx_rings_rem, rx_rings_rem;
648 int v_id;
649
650 /* initially assigning remaining rings count to VSIs num queue value */
651 tx_rings_rem = vsi->num_txq;
652 rx_rings_rem = vsi->num_rxq;
653
654 for (v_id = 0; v_id < q_vectors; v_id++) {
655 struct ice_q_vector *q_vector = vsi->q_vectors[v_id];
656 u8 tx_rings_per_v, rx_rings_per_v;
657 u16 q_id, q_base;
658
659 /* Tx rings mapping to vector */
660 tx_rings_per_v = (u8)DIV_ROUND_UP(tx_rings_rem,
661 q_vectors - v_id);
662 q_vector->num_ring_tx = tx_rings_per_v;
663 q_vector->tx.ring = NULL;
664 q_vector->tx.itr_idx = ICE_TX_ITR;
665 q_base = vsi->num_txq - tx_rings_rem;
666
667 for (q_id = q_base; q_id < (q_base + tx_rings_per_v); q_id++) {
668 struct ice_ring *tx_ring = vsi->tx_rings[q_id];
669
670 tx_ring->q_vector = q_vector;
671 tx_ring->next = q_vector->tx.ring;
672 q_vector->tx.ring = tx_ring;
673 }
674 tx_rings_rem -= tx_rings_per_v;
675
676 /* Rx rings mapping to vector */
677 rx_rings_per_v = (u8)DIV_ROUND_UP(rx_rings_rem,
678 q_vectors - v_id);
679 q_vector->num_ring_rx = rx_rings_per_v;
680 q_vector->rx.ring = NULL;
681 q_vector->rx.itr_idx = ICE_RX_ITR;
682 q_base = vsi->num_rxq - rx_rings_rem;
683
684 for (q_id = q_base; q_id < (q_base + rx_rings_per_v); q_id++) {
685 struct ice_ring *rx_ring = vsi->rx_rings[q_id];
686
687 rx_ring->q_vector = q_vector;
688 rx_ring->next = q_vector->rx.ring;
689 q_vector->rx.ring = rx_ring;
690 }
691 rx_rings_rem -= rx_rings_per_v;
692 }
693}
694
695/**
696 * ice_vsi_free_q_vectors - Free memory allocated for interrupt vectors
697 * @vsi: the VSI having memory freed
698 */
699void ice_vsi_free_q_vectors(struct ice_vsi *vsi)
700{
701 int v_idx;
702
703 ice_for_each_q_vector(vsi, v_idx)
704 ice_free_q_vector(vsi, v_idx);
705}
706
707/**
708 * ice_vsi_cfg_txq - Configure single Tx queue
709 * @vsi: the VSI that queue belongs to
710 * @ring: Tx ring to be configured
711 * @qg_buf: queue group buffer
712 */
713int
714ice_vsi_cfg_txq(struct ice_vsi *vsi, struct ice_ring *ring,
715 struct ice_aqc_add_tx_qgrp *qg_buf)
716{
717 u8 buf_len = struct_size(qg_buf, txqs, 1);
718 struct ice_tlan_ctx tlan_ctx = { 0 };
719 struct ice_aqc_add_txqs_perq *txq;
720 struct ice_pf *pf = vsi->back;
721 struct ice_hw *hw = &pf->hw;
722 enum ice_status status;
723 u16 pf_q;
724 u8 tc;
725
726 /* Configure XPS */
727 ice_cfg_xps_tx_ring(ring);
728
729 pf_q = ring->reg_idx;
730 ice_setup_tx_ctx(ring, &tlan_ctx, pf_q);
731 /* copy context contents into the qg_buf */
732 qg_buf->txqs[0].txq_id = cpu_to_le16(pf_q);
733 ice_set_ctx(hw, (u8 *)&tlan_ctx, qg_buf->txqs[0].txq_ctx,
734 ice_tlan_ctx_info);
735
736 /* init queue specific tail reg. It is referred as
737 * transmit comm scheduler queue doorbell.
738 */
739 ring->tail = hw->hw_addr + QTX_COMM_DBELL(pf_q);
740
741 if (IS_ENABLED(CONFIG_DCB))
742 tc = ring->dcb_tc;
743 else
744 tc = 0;
745
746 /* Add unique software queue handle of the Tx queue per
747 * TC into the VSI Tx ring
748 */
749 ring->q_handle = ice_calc_q_handle(vsi, ring, tc);
750
751 status = ice_ena_vsi_txq(vsi->port_info, vsi->idx, tc, ring->q_handle,
752 1, qg_buf, buf_len, NULL);
753 if (status) {
754 dev_err(ice_pf_to_dev(pf), "Failed to set LAN Tx queue context, error: %s\n",
755 ice_stat_str(status));
756 return -ENODEV;
757 }
758
759 /* Add Tx Queue TEID into the VSI Tx ring from the
760 * response. This will complete configuring and
761 * enabling the queue.
762 */
763 txq = &qg_buf->txqs[0];
764 if (pf_q == le16_to_cpu(txq->txq_id))
765 ring->txq_teid = le32_to_cpu(txq->q_teid);
766
767 return 0;
768}
769
770/**
771 * ice_cfg_itr - configure the initial interrupt throttle values
772 * @hw: pointer to the HW structure
773 * @q_vector: interrupt vector that's being configured
774 *
775 * Configure interrupt throttling values for the ring containers that are
776 * associated with the interrupt vector passed in.
777 */
778void ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector)
779{
780 ice_cfg_itr_gran(hw);
781
782 if (q_vector->num_ring_rx)
783 ice_write_itr(&q_vector->rx, q_vector->rx.itr_setting);
784
785 if (q_vector->num_ring_tx)
786 ice_write_itr(&q_vector->tx, q_vector->tx.itr_setting);
787
788 ice_write_intrl(q_vector, q_vector->intrl);
789}
790
791/**
792 * ice_cfg_txq_interrupt - configure interrupt on Tx queue
793 * @vsi: the VSI being configured
794 * @txq: Tx queue being mapped to MSI-X vector
795 * @msix_idx: MSI-X vector index within the function
796 * @itr_idx: ITR index of the interrupt cause
797 *
798 * Configure interrupt on Tx queue by associating Tx queue to MSI-X vector
799 * within the function space.
800 */
801void
802ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx)
803{
804 struct ice_pf *pf = vsi->back;
805 struct ice_hw *hw = &pf->hw;
806 u32 val;
807
808 itr_idx = (itr_idx << QINT_TQCTL_ITR_INDX_S) & QINT_TQCTL_ITR_INDX_M;
809
810 val = QINT_TQCTL_CAUSE_ENA_M | itr_idx |
811 ((msix_idx << QINT_TQCTL_MSIX_INDX_S) & QINT_TQCTL_MSIX_INDX_M);
812
813 wr32(hw, QINT_TQCTL(vsi->txq_map[txq]), val);
814 if (ice_is_xdp_ena_vsi(vsi)) {
815 u32 xdp_txq = txq + vsi->num_xdp_txq;
816
817 wr32(hw, QINT_TQCTL(vsi->txq_map[xdp_txq]),
818 val);
819 }
820 ice_flush(hw);
821}
822
823/**
824 * ice_cfg_rxq_interrupt - configure interrupt on Rx queue
825 * @vsi: the VSI being configured
826 * @rxq: Rx queue being mapped to MSI-X vector
827 * @msix_idx: MSI-X vector index within the function
828 * @itr_idx: ITR index of the interrupt cause
829 *
830 * Configure interrupt on Rx queue by associating Rx queue to MSI-X vector
831 * within the function space.
832 */
833void
834ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx)
835{
836 struct ice_pf *pf = vsi->back;
837 struct ice_hw *hw = &pf->hw;
838 u32 val;
839
840 itr_idx = (itr_idx << QINT_RQCTL_ITR_INDX_S) & QINT_RQCTL_ITR_INDX_M;
841
842 val = QINT_RQCTL_CAUSE_ENA_M | itr_idx |
843 ((msix_idx << QINT_RQCTL_MSIX_INDX_S) & QINT_RQCTL_MSIX_INDX_M);
844
845 wr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), val);
846
847 ice_flush(hw);
848}
849
850/**
851 * ice_trigger_sw_intr - trigger a software interrupt
852 * @hw: pointer to the HW structure
853 * @q_vector: interrupt vector to trigger the software interrupt for
854 */
855void ice_trigger_sw_intr(struct ice_hw *hw, struct ice_q_vector *q_vector)
856{
857 wr32(hw, GLINT_DYN_CTL(q_vector->reg_idx),
858 (ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S) |
859 GLINT_DYN_CTL_SWINT_TRIG_M |
860 GLINT_DYN_CTL_INTENA_M);
861}
862
863/**
864 * ice_vsi_stop_tx_ring - Disable single Tx ring
865 * @vsi: the VSI being configured
866 * @rst_src: reset source
867 * @rel_vmvf_num: Relative ID of VF/VM
868 * @ring: Tx ring to be stopped
869 * @txq_meta: Meta data of Tx ring to be stopped
870 */
871int
872ice_vsi_stop_tx_ring(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src,
873 u16 rel_vmvf_num, struct ice_ring *ring,
874 struct ice_txq_meta *txq_meta)
875{
876 struct ice_pf *pf = vsi->back;
877 struct ice_q_vector *q_vector;
878 struct ice_hw *hw = &pf->hw;
879 enum ice_status status;
880 u32 val;
881
882 /* clear cause_ena bit for disabled queues */
883 val = rd32(hw, QINT_TQCTL(ring->reg_idx));
884 val &= ~QINT_TQCTL_CAUSE_ENA_M;
885 wr32(hw, QINT_TQCTL(ring->reg_idx), val);
886
887 /* software is expected to wait for 100 ns */
888 ndelay(100);
889
890 /* trigger a software interrupt for the vector
891 * associated to the queue to schedule NAPI handler
892 */
893 q_vector = ring->q_vector;
894 if (q_vector)
895 ice_trigger_sw_intr(hw, q_vector);
896
897 status = ice_dis_vsi_txq(vsi->port_info, txq_meta->vsi_idx,
898 txq_meta->tc, 1, &txq_meta->q_handle,
899 &txq_meta->q_id, &txq_meta->q_teid, rst_src,
900 rel_vmvf_num, NULL);
901
902 /* if the disable queue command was exercised during an
903 * active reset flow, ICE_ERR_RESET_ONGOING is returned.
904 * This is not an error as the reset operation disables
905 * queues at the hardware level anyway.
906 */
907 if (status == ICE_ERR_RESET_ONGOING) {
908 dev_dbg(ice_pf_to_dev(vsi->back), "Reset in progress. LAN Tx queues already disabled\n");
909 } else if (status == ICE_ERR_DOES_NOT_EXIST) {
910 dev_dbg(ice_pf_to_dev(vsi->back), "LAN Tx queues do not exist, nothing to disable\n");
911 } else if (status) {
912 dev_err(ice_pf_to_dev(vsi->back), "Failed to disable LAN Tx queues, error: %s\n",
913 ice_stat_str(status));
914 return -ENODEV;
915 }
916
917 return 0;
918}
919
920/**
921 * ice_fill_txq_meta - Prepare the Tx queue's meta data
922 * @vsi: VSI that ring belongs to
923 * @ring: ring that txq_meta will be based on
924 * @txq_meta: a helper struct that wraps Tx queue's information
925 *
926 * Set up a helper struct that will contain all the necessary fields that
927 * are needed for stopping Tx queue
928 */
929void
930ice_fill_txq_meta(struct ice_vsi *vsi, struct ice_ring *ring,
931 struct ice_txq_meta *txq_meta)
932{
933 u8 tc;
934
935 if (IS_ENABLED(CONFIG_DCB))
936 tc = ring->dcb_tc;
937 else
938 tc = 0;
939
940 txq_meta->q_id = ring->reg_idx;
941 txq_meta->q_teid = ring->txq_teid;
942 txq_meta->q_handle = ring->q_handle;
943 txq_meta->vsi_idx = vsi->idx;
944 txq_meta->tc = tc;
945}