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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Support of MSI, HPET and DMAR interrupts.
4 *
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Moved from arch/x86/kernel/apic/io_apic.c.
7 * Jiang Liu <jiang.liu@linux.intel.com>
8 * Convert to hierarchical irqdomain
9 */
10#include <linux/mm.h>
11#include <linux/interrupt.h>
12#include <linux/irq.h>
13#include <linux/pci.h>
14#include <linux/dmar.h>
15#include <linux/hpet.h>
16#include <linux/msi.h>
17#include <asm/irqdomain.h>
18#include <asm/hpet.h>
19#include <asm/hw_irq.h>
20#include <asm/apic.h>
21#include <asm/irq_remapping.h>
22#include <asm/xen/hypervisor.h>
23
24struct irq_domain *x86_pci_msi_default_domain __ro_after_init;
25
26static void irq_msi_update_msg(struct irq_data *irqd, struct irq_cfg *cfg)
27{
28 struct msi_msg msg[2] = { [1] = { }, };
29
30 __irq_msi_compose_msg(cfg, msg, false);
31 irq_data_get_irq_chip(irqd)->irq_write_msi_msg(irqd, msg);
32}
33
34static int
35msi_set_affinity(struct irq_data *irqd, const struct cpumask *mask, bool force)
36{
37 struct irq_cfg old_cfg, *cfg = irqd_cfg(irqd);
38 struct irq_data *parent = irqd->parent_data;
39 unsigned int cpu;
40 int ret;
41
42 /* Save the current configuration */
43 cpu = cpumask_first(irq_data_get_effective_affinity_mask(irqd));
44 old_cfg = *cfg;
45
46 /* Allocate a new target vector */
47 ret = parent->chip->irq_set_affinity(parent, mask, force);
48 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
49 return ret;
50
51 /*
52 * For non-maskable and non-remapped MSI interrupts the migration
53 * to a different destination CPU and a different vector has to be
54 * done careful to handle the possible stray interrupt which can be
55 * caused by the non-atomic update of the address/data pair.
56 *
57 * Direct update is possible when:
58 * - The MSI is maskable (remapped MSI does not use this code path).
59 * The reservation mode bit is set in this case.
60 * - The new vector is the same as the old vector
61 * - The old vector is MANAGED_IRQ_SHUTDOWN_VECTOR (interrupt starts up)
62 * - The interrupt is not yet started up
63 * - The new destination CPU is the same as the old destination CPU
64 */
65 if (!irqd_can_reserve(irqd) ||
66 cfg->vector == old_cfg.vector ||
67 old_cfg.vector == MANAGED_IRQ_SHUTDOWN_VECTOR ||
68 !irqd_is_started(irqd) ||
69 cfg->dest_apicid == old_cfg.dest_apicid) {
70 irq_msi_update_msg(irqd, cfg);
71 return ret;
72 }
73
74 /*
75 * Paranoia: Validate that the interrupt target is the local
76 * CPU.
77 */
78 if (WARN_ON_ONCE(cpu != smp_processor_id())) {
79 irq_msi_update_msg(irqd, cfg);
80 return ret;
81 }
82
83 /*
84 * Redirect the interrupt to the new vector on the current CPU
85 * first. This might cause a spurious interrupt on this vector if
86 * the device raises an interrupt right between this update and the
87 * update to the final destination CPU.
88 *
89 * If the vector is in use then the installed device handler will
90 * denote it as spurious which is no harm as this is a rare event
91 * and interrupt handlers have to cope with spurious interrupts
92 * anyway. If the vector is unused, then it is marked so it won't
93 * trigger the 'No irq handler for vector' warning in
94 * common_interrupt().
95 *
96 * This requires to hold vector lock to prevent concurrent updates to
97 * the affected vector.
98 */
99 lock_vector_lock();
100
101 /*
102 * Mark the new target vector on the local CPU if it is currently
103 * unused. Reuse the VECTOR_RETRIGGERED state which is also used in
104 * the CPU hotplug path for a similar purpose. This cannot be
105 * undone here as the current CPU has interrupts disabled and
106 * cannot handle the interrupt before the whole set_affinity()
107 * section is done. In the CPU unplug case, the current CPU is
108 * about to vanish and will not handle any interrupts anymore. The
109 * vector is cleaned up when the CPU comes online again.
110 */
111 if (IS_ERR_OR_NULL(this_cpu_read(vector_irq[cfg->vector])))
112 this_cpu_write(vector_irq[cfg->vector], VECTOR_RETRIGGERED);
113
114 /* Redirect it to the new vector on the local CPU temporarily */
115 old_cfg.vector = cfg->vector;
116 irq_msi_update_msg(irqd, &old_cfg);
117
118 /* Now transition it to the target CPU */
119 irq_msi_update_msg(irqd, cfg);
120
121 /*
122 * All interrupts after this point are now targeted at the new
123 * vector/CPU.
124 *
125 * Drop vector lock before testing whether the temporary assignment
126 * to the local CPU was hit by an interrupt raised in the device,
127 * because the retrigger function acquires vector lock again.
128 */
129 unlock_vector_lock();
130
131 /*
132 * Check whether the transition raced with a device interrupt and
133 * is pending in the local APICs IRR. It is safe to do this outside
134 * of vector lock as the irq_desc::lock of this interrupt is still
135 * held and interrupts are disabled: The check is not accessing the
136 * underlying vector store. It's just checking the local APIC's
137 * IRR.
138 */
139 if (lapic_vector_set_in_irr(cfg->vector))
140 irq_data_get_irq_chip(irqd)->irq_retrigger(irqd);
141
142 return ret;
143}
144
145/**
146 * pci_dev_has_default_msi_parent_domain - Check whether the device has the default
147 * MSI parent domain associated
148 * @dev: Pointer to the PCI device
149 */
150bool pci_dev_has_default_msi_parent_domain(struct pci_dev *dev)
151{
152 struct irq_domain *domain = dev_get_msi_domain(&dev->dev);
153
154 if (!domain)
155 domain = dev_get_msi_domain(&dev->bus->dev);
156 if (!domain)
157 return false;
158
159 return domain == x86_vector_domain;
160}
161
162/**
163 * x86_msi_prepare - Setup of msi_alloc_info_t for allocations
164 * @domain: The domain for which this setup happens
165 * @dev: The device for which interrupts are allocated
166 * @nvec: The number of vectors to allocate
167 * @alloc: The allocation info structure to initialize
168 *
169 * This function is to be used for all types of MSI domains above the x86
170 * vector domain and any intermediates. It is always invoked from the
171 * top level interrupt domain. The domain specific allocation
172 * functionality is determined via the @domain's bus token which allows to
173 * map the X86 specific allocation type.
174 */
175static int x86_msi_prepare(struct irq_domain *domain, struct device *dev,
176 int nvec, msi_alloc_info_t *alloc)
177{
178 struct msi_domain_info *info = domain->host_data;
179
180 init_irq_alloc_info(alloc, NULL);
181
182 switch (info->bus_token) {
183 case DOMAIN_BUS_PCI_DEVICE_MSI:
184 alloc->type = X86_IRQ_ALLOC_TYPE_PCI_MSI;
185 return 0;
186 case DOMAIN_BUS_PCI_DEVICE_MSIX:
187 alloc->type = X86_IRQ_ALLOC_TYPE_PCI_MSIX;
188 return 0;
189 default:
190 return -EINVAL;
191 }
192}
193
194/**
195 * x86_init_dev_msi_info - Domain info setup for MSI domains
196 * @dev: The device for which the domain should be created
197 * @domain: The (root) domain providing this callback
198 * @real_parent: The real parent domain of the to initialize domain
199 * @info: The domain info for the to initialize domain
200 *
201 * This function is to be used for all types of MSI domains above the x86
202 * vector domain and any intermediates. The domain specific functionality
203 * is determined via the @real_parent.
204 */
205static bool x86_init_dev_msi_info(struct device *dev, struct irq_domain *domain,
206 struct irq_domain *real_parent, struct msi_domain_info *info)
207{
208 const struct msi_parent_ops *pops = real_parent->msi_parent_ops;
209
210 /* MSI parent domain specific settings */
211 switch (real_parent->bus_token) {
212 case DOMAIN_BUS_ANY:
213 /* Only the vector domain can have the ANY token */
214 if (WARN_ON_ONCE(domain != real_parent))
215 return false;
216 info->chip->irq_set_affinity = msi_set_affinity;
217 break;
218 case DOMAIN_BUS_DMAR:
219 case DOMAIN_BUS_AMDVI:
220 break;
221 default:
222 WARN_ON_ONCE(1);
223 return false;
224 }
225
226 /* Is the target supported? */
227 switch(info->bus_token) {
228 case DOMAIN_BUS_PCI_DEVICE_MSI:
229 case DOMAIN_BUS_PCI_DEVICE_MSIX:
230 break;
231 default:
232 WARN_ON_ONCE(1);
233 return false;
234 }
235
236 /*
237 * Mask out the domain specific MSI feature flags which are not
238 * supported by the real parent.
239 */
240 info->flags &= pops->supported_flags;
241 /* Enforce the required flags */
242 info->flags |= X86_VECTOR_MSI_FLAGS_REQUIRED;
243
244 /* This is always invoked from the top level MSI domain! */
245 info->ops->msi_prepare = x86_msi_prepare;
246
247 info->chip->irq_ack = irq_chip_ack_parent;
248 info->chip->irq_retrigger = irq_chip_retrigger_hierarchy;
249 info->chip->flags |= IRQCHIP_SKIP_SET_WAKE |
250 IRQCHIP_AFFINITY_PRE_STARTUP;
251
252 info->handler = handle_edge_irq;
253 info->handler_name = "edge";
254
255 return true;
256}
257
258static const struct msi_parent_ops x86_vector_msi_parent_ops = {
259 .supported_flags = X86_VECTOR_MSI_FLAGS_SUPPORTED,
260 .init_dev_msi_info = x86_init_dev_msi_info,
261};
262
263struct irq_domain * __init native_create_pci_msi_domain(void)
264{
265 if (apic_is_disabled)
266 return NULL;
267
268 x86_vector_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT;
269 x86_vector_domain->msi_parent_ops = &x86_vector_msi_parent_ops;
270 return x86_vector_domain;
271}
272
273void __init x86_create_pci_msi_domain(void)
274{
275 x86_pci_msi_default_domain = x86_init.irqs.create_pci_msi_domain();
276}
277
278/* Keep around for hyperV */
279int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,
280 msi_alloc_info_t *arg)
281{
282 init_irq_alloc_info(arg, NULL);
283
284 if (to_pci_dev(dev)->msix_enabled)
285 arg->type = X86_IRQ_ALLOC_TYPE_PCI_MSIX;
286 else
287 arg->type = X86_IRQ_ALLOC_TYPE_PCI_MSI;
288 return 0;
289}
290EXPORT_SYMBOL_GPL(pci_msi_prepare);
291
292#ifdef CONFIG_DMAR_TABLE
293/*
294 * The Intel IOMMU (ab)uses the high bits of the MSI address to contain the
295 * high bits of the destination APIC ID. This can't be done in the general
296 * case for MSIs as it would be targeting real memory above 4GiB not the
297 * APIC.
298 */
299static void dmar_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
300{
301 __irq_msi_compose_msg(irqd_cfg(data), msg, true);
302}
303
304static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
305{
306 dmar_msi_write(data->irq, msg);
307}
308
309static struct irq_chip dmar_msi_controller = {
310 .name = "DMAR-MSI",
311 .irq_unmask = dmar_msi_unmask,
312 .irq_mask = dmar_msi_mask,
313 .irq_ack = irq_chip_ack_parent,
314 .irq_set_affinity = msi_domain_set_affinity,
315 .irq_retrigger = irq_chip_retrigger_hierarchy,
316 .irq_compose_msi_msg = dmar_msi_compose_msg,
317 .irq_write_msi_msg = dmar_msi_write_msg,
318 .flags = IRQCHIP_SKIP_SET_WAKE |
319 IRQCHIP_AFFINITY_PRE_STARTUP,
320};
321
322static int dmar_msi_init(struct irq_domain *domain,
323 struct msi_domain_info *info, unsigned int virq,
324 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
325{
326 irq_domain_set_info(domain, virq, arg->devid, info->chip, NULL,
327 handle_edge_irq, arg->data, "edge");
328
329 return 0;
330}
331
332static struct msi_domain_ops dmar_msi_domain_ops = {
333 .msi_init = dmar_msi_init,
334};
335
336static struct msi_domain_info dmar_msi_domain_info = {
337 .ops = &dmar_msi_domain_ops,
338 .chip = &dmar_msi_controller,
339 .flags = MSI_FLAG_USE_DEF_DOM_OPS,
340};
341
342static struct irq_domain *dmar_get_irq_domain(void)
343{
344 static struct irq_domain *dmar_domain;
345 static DEFINE_MUTEX(dmar_lock);
346 struct fwnode_handle *fn;
347
348 mutex_lock(&dmar_lock);
349 if (dmar_domain)
350 goto out;
351
352 fn = irq_domain_alloc_named_fwnode("DMAR-MSI");
353 if (fn) {
354 dmar_domain = msi_create_irq_domain(fn, &dmar_msi_domain_info,
355 x86_vector_domain);
356 if (!dmar_domain)
357 irq_domain_free_fwnode(fn);
358 }
359out:
360 mutex_unlock(&dmar_lock);
361 return dmar_domain;
362}
363
364int dmar_alloc_hwirq(int id, int node, void *arg)
365{
366 struct irq_domain *domain = dmar_get_irq_domain();
367 struct irq_alloc_info info;
368
369 if (!domain)
370 return -1;
371
372 init_irq_alloc_info(&info, NULL);
373 info.type = X86_IRQ_ALLOC_TYPE_DMAR;
374 info.devid = id;
375 info.hwirq = id;
376 info.data = arg;
377
378 return irq_domain_alloc_irqs(domain, 1, node, &info);
379}
380
381void dmar_free_hwirq(int irq)
382{
383 irq_domain_free_irqs(irq, 1);
384}
385#endif
386
387bool arch_restore_msi_irqs(struct pci_dev *dev)
388{
389 return xen_initdom_restore_msi(dev);
390}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Support of MSI, HPET and DMAR interrupts.
4 *
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Moved from arch/x86/kernel/apic/io_apic.c.
7 * Jiang Liu <jiang.liu@linux.intel.com>
8 * Convert to hierarchical irqdomain
9 */
10#include <linux/mm.h>
11#include <linux/interrupt.h>
12#include <linux/irq.h>
13#include <linux/pci.h>
14#include <linux/dmar.h>
15#include <linux/hpet.h>
16#include <linux/msi.h>
17#include <asm/irqdomain.h>
18#include <asm/hpet.h>
19#include <asm/hw_irq.h>
20#include <asm/apic.h>
21#include <asm/irq_remapping.h>
22
23struct irq_domain *x86_pci_msi_default_domain __ro_after_init;
24
25static void irq_msi_update_msg(struct irq_data *irqd, struct irq_cfg *cfg)
26{
27 struct msi_msg msg[2] = { [1] = { }, };
28
29 __irq_msi_compose_msg(cfg, msg, false);
30 irq_data_get_irq_chip(irqd)->irq_write_msi_msg(irqd, msg);
31}
32
33static int
34msi_set_affinity(struct irq_data *irqd, const struct cpumask *mask, bool force)
35{
36 struct irq_cfg old_cfg, *cfg = irqd_cfg(irqd);
37 struct irq_data *parent = irqd->parent_data;
38 unsigned int cpu;
39 int ret;
40
41 /* Save the current configuration */
42 cpu = cpumask_first(irq_data_get_effective_affinity_mask(irqd));
43 old_cfg = *cfg;
44
45 /* Allocate a new target vector */
46 ret = parent->chip->irq_set_affinity(parent, mask, force);
47 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
48 return ret;
49
50 /*
51 * For non-maskable and non-remapped MSI interrupts the migration
52 * to a different destination CPU and a different vector has to be
53 * done careful to handle the possible stray interrupt which can be
54 * caused by the non-atomic update of the address/data pair.
55 *
56 * Direct update is possible when:
57 * - The MSI is maskable (remapped MSI does not use this code path)).
58 * The quirk bit is not set in this case.
59 * - The new vector is the same as the old vector
60 * - The old vector is MANAGED_IRQ_SHUTDOWN_VECTOR (interrupt starts up)
61 * - The interrupt is not yet started up
62 * - The new destination CPU is the same as the old destination CPU
63 */
64 if (!irqd_msi_nomask_quirk(irqd) ||
65 cfg->vector == old_cfg.vector ||
66 old_cfg.vector == MANAGED_IRQ_SHUTDOWN_VECTOR ||
67 !irqd_is_started(irqd) ||
68 cfg->dest_apicid == old_cfg.dest_apicid) {
69 irq_msi_update_msg(irqd, cfg);
70 return ret;
71 }
72
73 /*
74 * Paranoia: Validate that the interrupt target is the local
75 * CPU.
76 */
77 if (WARN_ON_ONCE(cpu != smp_processor_id())) {
78 irq_msi_update_msg(irqd, cfg);
79 return ret;
80 }
81
82 /*
83 * Redirect the interrupt to the new vector on the current CPU
84 * first. This might cause a spurious interrupt on this vector if
85 * the device raises an interrupt right between this update and the
86 * update to the final destination CPU.
87 *
88 * If the vector is in use then the installed device handler will
89 * denote it as spurious which is no harm as this is a rare event
90 * and interrupt handlers have to cope with spurious interrupts
91 * anyway. If the vector is unused, then it is marked so it won't
92 * trigger the 'No irq handler for vector' warning in
93 * common_interrupt().
94 *
95 * This requires to hold vector lock to prevent concurrent updates to
96 * the affected vector.
97 */
98 lock_vector_lock();
99
100 /*
101 * Mark the new target vector on the local CPU if it is currently
102 * unused. Reuse the VECTOR_RETRIGGERED state which is also used in
103 * the CPU hotplug path for a similar purpose. This cannot be
104 * undone here as the current CPU has interrupts disabled and
105 * cannot handle the interrupt before the whole set_affinity()
106 * section is done. In the CPU unplug case, the current CPU is
107 * about to vanish and will not handle any interrupts anymore. The
108 * vector is cleaned up when the CPU comes online again.
109 */
110 if (IS_ERR_OR_NULL(this_cpu_read(vector_irq[cfg->vector])))
111 this_cpu_write(vector_irq[cfg->vector], VECTOR_RETRIGGERED);
112
113 /* Redirect it to the new vector on the local CPU temporarily */
114 old_cfg.vector = cfg->vector;
115 irq_msi_update_msg(irqd, &old_cfg);
116
117 /* Now transition it to the target CPU */
118 irq_msi_update_msg(irqd, cfg);
119
120 /*
121 * All interrupts after this point are now targeted at the new
122 * vector/CPU.
123 *
124 * Drop vector lock before testing whether the temporary assignment
125 * to the local CPU was hit by an interrupt raised in the device,
126 * because the retrigger function acquires vector lock again.
127 */
128 unlock_vector_lock();
129
130 /*
131 * Check whether the transition raced with a device interrupt and
132 * is pending in the local APICs IRR. It is safe to do this outside
133 * of vector lock as the irq_desc::lock of this interrupt is still
134 * held and interrupts are disabled: The check is not accessing the
135 * underlying vector store. It's just checking the local APIC's
136 * IRR.
137 */
138 if (lapic_vector_set_in_irr(cfg->vector))
139 irq_data_get_irq_chip(irqd)->irq_retrigger(irqd);
140
141 return ret;
142}
143
144/*
145 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
146 * which implement the MSI or MSI-X Capability Structure.
147 */
148static struct irq_chip pci_msi_controller = {
149 .name = "PCI-MSI",
150 .irq_unmask = pci_msi_unmask_irq,
151 .irq_mask = pci_msi_mask_irq,
152 .irq_ack = irq_chip_ack_parent,
153 .irq_retrigger = irq_chip_retrigger_hierarchy,
154 .irq_set_affinity = msi_set_affinity,
155 .flags = IRQCHIP_SKIP_SET_WAKE |
156 IRQCHIP_AFFINITY_PRE_STARTUP,
157};
158
159int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,
160 msi_alloc_info_t *arg)
161{
162 struct pci_dev *pdev = to_pci_dev(dev);
163 struct msi_desc *desc = first_pci_msi_entry(pdev);
164
165 init_irq_alloc_info(arg, NULL);
166 if (desc->msi_attrib.is_msix) {
167 arg->type = X86_IRQ_ALLOC_TYPE_PCI_MSIX;
168 } else {
169 arg->type = X86_IRQ_ALLOC_TYPE_PCI_MSI;
170 arg->flags |= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
171 }
172
173 return 0;
174}
175EXPORT_SYMBOL_GPL(pci_msi_prepare);
176
177static struct msi_domain_ops pci_msi_domain_ops = {
178 .msi_prepare = pci_msi_prepare,
179};
180
181static struct msi_domain_info pci_msi_domain_info = {
182 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
183 MSI_FLAG_PCI_MSIX,
184 .ops = &pci_msi_domain_ops,
185 .chip = &pci_msi_controller,
186 .handler = handle_edge_irq,
187 .handler_name = "edge",
188};
189
190struct irq_domain * __init native_create_pci_msi_domain(void)
191{
192 struct fwnode_handle *fn;
193 struct irq_domain *d;
194
195 if (disable_apic)
196 return NULL;
197
198 fn = irq_domain_alloc_named_fwnode("PCI-MSI");
199 if (!fn)
200 return NULL;
201
202 d = pci_msi_create_irq_domain(fn, &pci_msi_domain_info,
203 x86_vector_domain);
204 if (!d) {
205 irq_domain_free_fwnode(fn);
206 pr_warn("Failed to initialize PCI-MSI irqdomain.\n");
207 } else {
208 d->flags |= IRQ_DOMAIN_MSI_NOMASK_QUIRK;
209 }
210 return d;
211}
212
213void __init x86_create_pci_msi_domain(void)
214{
215 x86_pci_msi_default_domain = x86_init.irqs.create_pci_msi_domain();
216}
217
218#ifdef CONFIG_IRQ_REMAP
219static struct irq_chip pci_msi_ir_controller = {
220 .name = "IR-PCI-MSI",
221 .irq_unmask = pci_msi_unmask_irq,
222 .irq_mask = pci_msi_mask_irq,
223 .irq_ack = irq_chip_ack_parent,
224 .irq_retrigger = irq_chip_retrigger_hierarchy,
225 .flags = IRQCHIP_SKIP_SET_WAKE |
226 IRQCHIP_AFFINITY_PRE_STARTUP,
227};
228
229static struct msi_domain_info pci_msi_ir_domain_info = {
230 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
231 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
232 .ops = &pci_msi_domain_ops,
233 .chip = &pci_msi_ir_controller,
234 .handler = handle_edge_irq,
235 .handler_name = "edge",
236};
237
238struct irq_domain *arch_create_remap_msi_irq_domain(struct irq_domain *parent,
239 const char *name, int id)
240{
241 struct fwnode_handle *fn;
242 struct irq_domain *d;
243
244 fn = irq_domain_alloc_named_id_fwnode(name, id);
245 if (!fn)
246 return NULL;
247 d = pci_msi_create_irq_domain(fn, &pci_msi_ir_domain_info, parent);
248 if (!d)
249 irq_domain_free_fwnode(fn);
250 return d;
251}
252#endif
253
254#ifdef CONFIG_DMAR_TABLE
255/*
256 * The Intel IOMMU (ab)uses the high bits of the MSI address to contain the
257 * high bits of the destination APIC ID. This can't be done in the general
258 * case for MSIs as it would be targeting real memory above 4GiB not the
259 * APIC.
260 */
261static void dmar_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
262{
263 __irq_msi_compose_msg(irqd_cfg(data), msg, true);
264}
265
266static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
267{
268 dmar_msi_write(data->irq, msg);
269}
270
271static struct irq_chip dmar_msi_controller = {
272 .name = "DMAR-MSI",
273 .irq_unmask = dmar_msi_unmask,
274 .irq_mask = dmar_msi_mask,
275 .irq_ack = irq_chip_ack_parent,
276 .irq_set_affinity = msi_domain_set_affinity,
277 .irq_retrigger = irq_chip_retrigger_hierarchy,
278 .irq_compose_msi_msg = dmar_msi_compose_msg,
279 .irq_write_msi_msg = dmar_msi_write_msg,
280 .flags = IRQCHIP_SKIP_SET_WAKE |
281 IRQCHIP_AFFINITY_PRE_STARTUP,
282};
283
284static int dmar_msi_init(struct irq_domain *domain,
285 struct msi_domain_info *info, unsigned int virq,
286 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
287{
288 irq_domain_set_info(domain, virq, arg->devid, info->chip, NULL,
289 handle_edge_irq, arg->data, "edge");
290
291 return 0;
292}
293
294static struct msi_domain_ops dmar_msi_domain_ops = {
295 .msi_init = dmar_msi_init,
296};
297
298static struct msi_domain_info dmar_msi_domain_info = {
299 .ops = &dmar_msi_domain_ops,
300 .chip = &dmar_msi_controller,
301 .flags = MSI_FLAG_USE_DEF_DOM_OPS,
302};
303
304static struct irq_domain *dmar_get_irq_domain(void)
305{
306 static struct irq_domain *dmar_domain;
307 static DEFINE_MUTEX(dmar_lock);
308 struct fwnode_handle *fn;
309
310 mutex_lock(&dmar_lock);
311 if (dmar_domain)
312 goto out;
313
314 fn = irq_domain_alloc_named_fwnode("DMAR-MSI");
315 if (fn) {
316 dmar_domain = msi_create_irq_domain(fn, &dmar_msi_domain_info,
317 x86_vector_domain);
318 if (!dmar_domain)
319 irq_domain_free_fwnode(fn);
320 }
321out:
322 mutex_unlock(&dmar_lock);
323 return dmar_domain;
324}
325
326int dmar_alloc_hwirq(int id, int node, void *arg)
327{
328 struct irq_domain *domain = dmar_get_irq_domain();
329 struct irq_alloc_info info;
330
331 if (!domain)
332 return -1;
333
334 init_irq_alloc_info(&info, NULL);
335 info.type = X86_IRQ_ALLOC_TYPE_DMAR;
336 info.devid = id;
337 info.hwirq = id;
338 info.data = arg;
339
340 return irq_domain_alloc_irqs(domain, 1, node, &info);
341}
342
343void dmar_free_hwirq(int irq)
344{
345 irq_domain_free_irqs(irq, 1);
346}
347#endif