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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Support of MSI, HPET and DMAR interrupts.
4 *
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Moved from arch/x86/kernel/apic/io_apic.c.
7 * Jiang Liu <jiang.liu@linux.intel.com>
8 * Convert to hierarchical irqdomain
9 */
10#include <linux/mm.h>
11#include <linux/interrupt.h>
12#include <linux/irq.h>
13#include <linux/pci.h>
14#include <linux/dmar.h>
15#include <linux/hpet.h>
16#include <linux/msi.h>
17#include <asm/irqdomain.h>
18#include <asm/hpet.h>
19#include <asm/hw_irq.h>
20#include <asm/apic.h>
21#include <asm/irq_remapping.h>
22#include <asm/xen/hypervisor.h>
23
24struct irq_domain *x86_pci_msi_default_domain __ro_after_init;
25
26static void irq_msi_update_msg(struct irq_data *irqd, struct irq_cfg *cfg)
27{
28 struct msi_msg msg[2] = { [1] = { }, };
29
30 __irq_msi_compose_msg(cfg, msg, false);
31 irq_data_get_irq_chip(irqd)->irq_write_msi_msg(irqd, msg);
32}
33
34static int
35msi_set_affinity(struct irq_data *irqd, const struct cpumask *mask, bool force)
36{
37 struct irq_cfg old_cfg, *cfg = irqd_cfg(irqd);
38 struct irq_data *parent = irqd->parent_data;
39 unsigned int cpu;
40 int ret;
41
42 /* Save the current configuration */
43 cpu = cpumask_first(irq_data_get_effective_affinity_mask(irqd));
44 old_cfg = *cfg;
45
46 /* Allocate a new target vector */
47 ret = parent->chip->irq_set_affinity(parent, mask, force);
48 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
49 return ret;
50
51 /*
52 * For non-maskable and non-remapped MSI interrupts the migration
53 * to a different destination CPU and a different vector has to be
54 * done careful to handle the possible stray interrupt which can be
55 * caused by the non-atomic update of the address/data pair.
56 *
57 * Direct update is possible when:
58 * - The MSI is maskable (remapped MSI does not use this code path).
59 * The reservation mode bit is set in this case.
60 * - The new vector is the same as the old vector
61 * - The old vector is MANAGED_IRQ_SHUTDOWN_VECTOR (interrupt starts up)
62 * - The interrupt is not yet started up
63 * - The new destination CPU is the same as the old destination CPU
64 */
65 if (!irqd_can_reserve(irqd) ||
66 cfg->vector == old_cfg.vector ||
67 old_cfg.vector == MANAGED_IRQ_SHUTDOWN_VECTOR ||
68 !irqd_is_started(irqd) ||
69 cfg->dest_apicid == old_cfg.dest_apicid) {
70 irq_msi_update_msg(irqd, cfg);
71 return ret;
72 }
73
74 /*
75 * Paranoia: Validate that the interrupt target is the local
76 * CPU.
77 */
78 if (WARN_ON_ONCE(cpu != smp_processor_id())) {
79 irq_msi_update_msg(irqd, cfg);
80 return ret;
81 }
82
83 /*
84 * Redirect the interrupt to the new vector on the current CPU
85 * first. This might cause a spurious interrupt on this vector if
86 * the device raises an interrupt right between this update and the
87 * update to the final destination CPU.
88 *
89 * If the vector is in use then the installed device handler will
90 * denote it as spurious which is no harm as this is a rare event
91 * and interrupt handlers have to cope with spurious interrupts
92 * anyway. If the vector is unused, then it is marked so it won't
93 * trigger the 'No irq handler for vector' warning in
94 * common_interrupt().
95 *
96 * This requires to hold vector lock to prevent concurrent updates to
97 * the affected vector.
98 */
99 lock_vector_lock();
100
101 /*
102 * Mark the new target vector on the local CPU if it is currently
103 * unused. Reuse the VECTOR_RETRIGGERED state which is also used in
104 * the CPU hotplug path for a similar purpose. This cannot be
105 * undone here as the current CPU has interrupts disabled and
106 * cannot handle the interrupt before the whole set_affinity()
107 * section is done. In the CPU unplug case, the current CPU is
108 * about to vanish and will not handle any interrupts anymore. The
109 * vector is cleaned up when the CPU comes online again.
110 */
111 if (IS_ERR_OR_NULL(this_cpu_read(vector_irq[cfg->vector])))
112 this_cpu_write(vector_irq[cfg->vector], VECTOR_RETRIGGERED);
113
114 /* Redirect it to the new vector on the local CPU temporarily */
115 old_cfg.vector = cfg->vector;
116 irq_msi_update_msg(irqd, &old_cfg);
117
118 /* Now transition it to the target CPU */
119 irq_msi_update_msg(irqd, cfg);
120
121 /*
122 * All interrupts after this point are now targeted at the new
123 * vector/CPU.
124 *
125 * Drop vector lock before testing whether the temporary assignment
126 * to the local CPU was hit by an interrupt raised in the device,
127 * because the retrigger function acquires vector lock again.
128 */
129 unlock_vector_lock();
130
131 /*
132 * Check whether the transition raced with a device interrupt and
133 * is pending in the local APICs IRR. It is safe to do this outside
134 * of vector lock as the irq_desc::lock of this interrupt is still
135 * held and interrupts are disabled: The check is not accessing the
136 * underlying vector store. It's just checking the local APIC's
137 * IRR.
138 */
139 if (lapic_vector_set_in_irr(cfg->vector))
140 irq_data_get_irq_chip(irqd)->irq_retrigger(irqd);
141
142 return ret;
143}
144
145/**
146 * pci_dev_has_default_msi_parent_domain - Check whether the device has the default
147 * MSI parent domain associated
148 * @dev: Pointer to the PCI device
149 */
150bool pci_dev_has_default_msi_parent_domain(struct pci_dev *dev)
151{
152 struct irq_domain *domain = dev_get_msi_domain(&dev->dev);
153
154 if (!domain)
155 domain = dev_get_msi_domain(&dev->bus->dev);
156 if (!domain)
157 return false;
158
159 return domain == x86_vector_domain;
160}
161
162/**
163 * x86_msi_prepare - Setup of msi_alloc_info_t for allocations
164 * @domain: The domain for which this setup happens
165 * @dev: The device for which interrupts are allocated
166 * @nvec: The number of vectors to allocate
167 * @alloc: The allocation info structure to initialize
168 *
169 * This function is to be used for all types of MSI domains above the x86
170 * vector domain and any intermediates. It is always invoked from the
171 * top level interrupt domain. The domain specific allocation
172 * functionality is determined via the @domain's bus token which allows to
173 * map the X86 specific allocation type.
174 */
175static int x86_msi_prepare(struct irq_domain *domain, struct device *dev,
176 int nvec, msi_alloc_info_t *alloc)
177{
178 struct msi_domain_info *info = domain->host_data;
179
180 init_irq_alloc_info(alloc, NULL);
181
182 switch (info->bus_token) {
183 case DOMAIN_BUS_PCI_DEVICE_MSI:
184 alloc->type = X86_IRQ_ALLOC_TYPE_PCI_MSI;
185 return 0;
186 case DOMAIN_BUS_PCI_DEVICE_MSIX:
187 alloc->type = X86_IRQ_ALLOC_TYPE_PCI_MSIX;
188 return 0;
189 default:
190 return -EINVAL;
191 }
192}
193
194/**
195 * x86_init_dev_msi_info - Domain info setup for MSI domains
196 * @dev: The device for which the domain should be created
197 * @domain: The (root) domain providing this callback
198 * @real_parent: The real parent domain of the to initialize domain
199 * @info: The domain info for the to initialize domain
200 *
201 * This function is to be used for all types of MSI domains above the x86
202 * vector domain and any intermediates. The domain specific functionality
203 * is determined via the @real_parent.
204 */
205static bool x86_init_dev_msi_info(struct device *dev, struct irq_domain *domain,
206 struct irq_domain *real_parent, struct msi_domain_info *info)
207{
208 const struct msi_parent_ops *pops = real_parent->msi_parent_ops;
209
210 /* MSI parent domain specific settings */
211 switch (real_parent->bus_token) {
212 case DOMAIN_BUS_ANY:
213 /* Only the vector domain can have the ANY token */
214 if (WARN_ON_ONCE(domain != real_parent))
215 return false;
216 info->chip->irq_set_affinity = msi_set_affinity;
217 break;
218 case DOMAIN_BUS_DMAR:
219 case DOMAIN_BUS_AMDVI:
220 break;
221 default:
222 WARN_ON_ONCE(1);
223 return false;
224 }
225
226 /* Is the target supported? */
227 switch(info->bus_token) {
228 case DOMAIN_BUS_PCI_DEVICE_MSI:
229 case DOMAIN_BUS_PCI_DEVICE_MSIX:
230 break;
231 default:
232 WARN_ON_ONCE(1);
233 return false;
234 }
235
236 /*
237 * Mask out the domain specific MSI feature flags which are not
238 * supported by the real parent.
239 */
240 info->flags &= pops->supported_flags;
241 /* Enforce the required flags */
242 info->flags |= X86_VECTOR_MSI_FLAGS_REQUIRED;
243
244 /* This is always invoked from the top level MSI domain! */
245 info->ops->msi_prepare = x86_msi_prepare;
246
247 info->chip->irq_ack = irq_chip_ack_parent;
248 info->chip->irq_retrigger = irq_chip_retrigger_hierarchy;
249 info->chip->flags |= IRQCHIP_SKIP_SET_WAKE |
250 IRQCHIP_AFFINITY_PRE_STARTUP;
251
252 info->handler = handle_edge_irq;
253 info->handler_name = "edge";
254
255 return true;
256}
257
258static const struct msi_parent_ops x86_vector_msi_parent_ops = {
259 .supported_flags = X86_VECTOR_MSI_FLAGS_SUPPORTED,
260 .init_dev_msi_info = x86_init_dev_msi_info,
261};
262
263struct irq_domain * __init native_create_pci_msi_domain(void)
264{
265 if (apic_is_disabled)
266 return NULL;
267
268 x86_vector_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT;
269 x86_vector_domain->msi_parent_ops = &x86_vector_msi_parent_ops;
270 return x86_vector_domain;
271}
272
273void __init x86_create_pci_msi_domain(void)
274{
275 x86_pci_msi_default_domain = x86_init.irqs.create_pci_msi_domain();
276}
277
278/* Keep around for hyperV */
279int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,
280 msi_alloc_info_t *arg)
281{
282 init_irq_alloc_info(arg, NULL);
283
284 if (to_pci_dev(dev)->msix_enabled)
285 arg->type = X86_IRQ_ALLOC_TYPE_PCI_MSIX;
286 else
287 arg->type = X86_IRQ_ALLOC_TYPE_PCI_MSI;
288 return 0;
289}
290EXPORT_SYMBOL_GPL(pci_msi_prepare);
291
292#ifdef CONFIG_DMAR_TABLE
293/*
294 * The Intel IOMMU (ab)uses the high bits of the MSI address to contain the
295 * high bits of the destination APIC ID. This can't be done in the general
296 * case for MSIs as it would be targeting real memory above 4GiB not the
297 * APIC.
298 */
299static void dmar_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
300{
301 __irq_msi_compose_msg(irqd_cfg(data), msg, true);
302}
303
304static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
305{
306 dmar_msi_write(data->irq, msg);
307}
308
309static struct irq_chip dmar_msi_controller = {
310 .name = "DMAR-MSI",
311 .irq_unmask = dmar_msi_unmask,
312 .irq_mask = dmar_msi_mask,
313 .irq_ack = irq_chip_ack_parent,
314 .irq_set_affinity = msi_domain_set_affinity,
315 .irq_retrigger = irq_chip_retrigger_hierarchy,
316 .irq_compose_msi_msg = dmar_msi_compose_msg,
317 .irq_write_msi_msg = dmar_msi_write_msg,
318 .flags = IRQCHIP_SKIP_SET_WAKE |
319 IRQCHIP_AFFINITY_PRE_STARTUP,
320};
321
322static int dmar_msi_init(struct irq_domain *domain,
323 struct msi_domain_info *info, unsigned int virq,
324 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
325{
326 irq_domain_set_info(domain, virq, arg->devid, info->chip, NULL,
327 handle_edge_irq, arg->data, "edge");
328
329 return 0;
330}
331
332static struct msi_domain_ops dmar_msi_domain_ops = {
333 .msi_init = dmar_msi_init,
334};
335
336static struct msi_domain_info dmar_msi_domain_info = {
337 .ops = &dmar_msi_domain_ops,
338 .chip = &dmar_msi_controller,
339 .flags = MSI_FLAG_USE_DEF_DOM_OPS,
340};
341
342static struct irq_domain *dmar_get_irq_domain(void)
343{
344 static struct irq_domain *dmar_domain;
345 static DEFINE_MUTEX(dmar_lock);
346 struct fwnode_handle *fn;
347
348 mutex_lock(&dmar_lock);
349 if (dmar_domain)
350 goto out;
351
352 fn = irq_domain_alloc_named_fwnode("DMAR-MSI");
353 if (fn) {
354 dmar_domain = msi_create_irq_domain(fn, &dmar_msi_domain_info,
355 x86_vector_domain);
356 if (!dmar_domain)
357 irq_domain_free_fwnode(fn);
358 }
359out:
360 mutex_unlock(&dmar_lock);
361 return dmar_domain;
362}
363
364int dmar_alloc_hwirq(int id, int node, void *arg)
365{
366 struct irq_domain *domain = dmar_get_irq_domain();
367 struct irq_alloc_info info;
368
369 if (!domain)
370 return -1;
371
372 init_irq_alloc_info(&info, NULL);
373 info.type = X86_IRQ_ALLOC_TYPE_DMAR;
374 info.devid = id;
375 info.hwirq = id;
376 info.data = arg;
377
378 return irq_domain_alloc_irqs(domain, 1, node, &info);
379}
380
381void dmar_free_hwirq(int irq)
382{
383 irq_domain_free_irqs(irq, 1);
384}
385#endif
386
387bool arch_restore_msi_irqs(struct pci_dev *dev)
388{
389 return xen_initdom_restore_msi(dev);
390}
1/*
2 * Support of MSI, HPET and DMAR interrupts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 * Moved from arch/x86/kernel/apic/io_apic.c.
6 * Jiang Liu <jiang.liu@linux.intel.com>
7 * Convert to hierarchical irqdomain
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/mm.h>
14#include <linux/interrupt.h>
15#include <linux/pci.h>
16#include <linux/dmar.h>
17#include <linux/hpet.h>
18#include <linux/msi.h>
19#include <asm/irqdomain.h>
20#include <asm/msidef.h>
21#include <asm/hpet.h>
22#include <asm/hw_irq.h>
23#include <asm/apic.h>
24#include <asm/irq_remapping.h>
25
26static struct irq_domain *msi_default_domain;
27
28static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
29{
30 struct irq_cfg *cfg = irqd_cfg(data);
31
32 msg->address_hi = MSI_ADDR_BASE_HI;
33
34 if (x2apic_enabled())
35 msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
36
37 msg->address_lo =
38 MSI_ADDR_BASE_LO |
39 ((apic->irq_dest_mode == 0) ?
40 MSI_ADDR_DEST_MODE_PHYSICAL :
41 MSI_ADDR_DEST_MODE_LOGICAL) |
42 MSI_ADDR_REDIRECTION_CPU |
43 MSI_ADDR_DEST_ID(cfg->dest_apicid);
44
45 msg->data =
46 MSI_DATA_TRIGGER_EDGE |
47 MSI_DATA_LEVEL_ASSERT |
48 MSI_DATA_DELIVERY_FIXED |
49 MSI_DATA_VECTOR(cfg->vector);
50}
51
52/*
53 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
54 * which implement the MSI or MSI-X Capability Structure.
55 */
56static struct irq_chip pci_msi_controller = {
57 .name = "PCI-MSI",
58 .irq_unmask = pci_msi_unmask_irq,
59 .irq_mask = pci_msi_mask_irq,
60 .irq_ack = irq_chip_ack_parent,
61 .irq_retrigger = irq_chip_retrigger_hierarchy,
62 .irq_compose_msi_msg = irq_msi_compose_msg,
63 .flags = IRQCHIP_SKIP_SET_WAKE,
64};
65
66int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
67{
68 struct irq_domain *domain;
69 struct irq_alloc_info info;
70
71 init_irq_alloc_info(&info, NULL);
72 info.type = X86_IRQ_ALLOC_TYPE_MSI;
73 info.msi_dev = dev;
74
75 domain = irq_remapping_get_irq_domain(&info);
76 if (domain == NULL)
77 domain = msi_default_domain;
78 if (domain == NULL)
79 return -ENOSYS;
80
81 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
82}
83
84void native_teardown_msi_irq(unsigned int irq)
85{
86 irq_domain_free_irqs(irq, 1);
87}
88
89static irq_hw_number_t pci_msi_get_hwirq(struct msi_domain_info *info,
90 msi_alloc_info_t *arg)
91{
92 return arg->msi_hwirq;
93}
94
95int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,
96 msi_alloc_info_t *arg)
97{
98 struct pci_dev *pdev = to_pci_dev(dev);
99 struct msi_desc *desc = first_pci_msi_entry(pdev);
100
101 init_irq_alloc_info(arg, NULL);
102 arg->msi_dev = pdev;
103 if (desc->msi_attrib.is_msix) {
104 arg->type = X86_IRQ_ALLOC_TYPE_MSIX;
105 } else {
106 arg->type = X86_IRQ_ALLOC_TYPE_MSI;
107 arg->flags |= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
108 }
109
110 return 0;
111}
112EXPORT_SYMBOL_GPL(pci_msi_prepare);
113
114void pci_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
115{
116 arg->msi_hwirq = pci_msi_domain_calc_hwirq(arg->msi_dev, desc);
117}
118EXPORT_SYMBOL_GPL(pci_msi_set_desc);
119
120static struct msi_domain_ops pci_msi_domain_ops = {
121 .get_hwirq = pci_msi_get_hwirq,
122 .msi_prepare = pci_msi_prepare,
123 .set_desc = pci_msi_set_desc,
124};
125
126static struct msi_domain_info pci_msi_domain_info = {
127 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
128 MSI_FLAG_PCI_MSIX,
129 .ops = &pci_msi_domain_ops,
130 .chip = &pci_msi_controller,
131 .handler = handle_edge_irq,
132 .handler_name = "edge",
133};
134
135void __init arch_init_msi_domain(struct irq_domain *parent)
136{
137 struct fwnode_handle *fn;
138
139 if (disable_apic)
140 return;
141
142 fn = irq_domain_alloc_named_fwnode("PCI-MSI");
143 if (fn) {
144 msi_default_domain =
145 pci_msi_create_irq_domain(fn, &pci_msi_domain_info,
146 parent);
147 irq_domain_free_fwnode(fn);
148 }
149 if (!msi_default_domain)
150 pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n");
151}
152
153#ifdef CONFIG_IRQ_REMAP
154static struct irq_chip pci_msi_ir_controller = {
155 .name = "IR-PCI-MSI",
156 .irq_unmask = pci_msi_unmask_irq,
157 .irq_mask = pci_msi_mask_irq,
158 .irq_ack = irq_chip_ack_parent,
159 .irq_retrigger = irq_chip_retrigger_hierarchy,
160 .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
161 .flags = IRQCHIP_SKIP_SET_WAKE,
162};
163
164static struct msi_domain_info pci_msi_ir_domain_info = {
165 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
166 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
167 .ops = &pci_msi_domain_ops,
168 .chip = &pci_msi_ir_controller,
169 .handler = handle_edge_irq,
170 .handler_name = "edge",
171};
172
173struct irq_domain *arch_create_remap_msi_irq_domain(struct irq_domain *parent,
174 const char *name, int id)
175{
176 struct fwnode_handle *fn;
177 struct irq_domain *d;
178
179 fn = irq_domain_alloc_named_id_fwnode(name, id);
180 if (!fn)
181 return NULL;
182 d = pci_msi_create_irq_domain(fn, &pci_msi_ir_domain_info, parent);
183 irq_domain_free_fwnode(fn);
184 return d;
185}
186#endif
187
188#ifdef CONFIG_DMAR_TABLE
189static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
190{
191 dmar_msi_write(data->irq, msg);
192}
193
194static struct irq_chip dmar_msi_controller = {
195 .name = "DMAR-MSI",
196 .irq_unmask = dmar_msi_unmask,
197 .irq_mask = dmar_msi_mask,
198 .irq_ack = irq_chip_ack_parent,
199 .irq_set_affinity = msi_domain_set_affinity,
200 .irq_retrigger = irq_chip_retrigger_hierarchy,
201 .irq_compose_msi_msg = irq_msi_compose_msg,
202 .irq_write_msi_msg = dmar_msi_write_msg,
203 .flags = IRQCHIP_SKIP_SET_WAKE,
204};
205
206static irq_hw_number_t dmar_msi_get_hwirq(struct msi_domain_info *info,
207 msi_alloc_info_t *arg)
208{
209 return arg->dmar_id;
210}
211
212static int dmar_msi_init(struct irq_domain *domain,
213 struct msi_domain_info *info, unsigned int virq,
214 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
215{
216 irq_domain_set_info(domain, virq, arg->dmar_id, info->chip, NULL,
217 handle_edge_irq, arg->dmar_data, "edge");
218
219 return 0;
220}
221
222static struct msi_domain_ops dmar_msi_domain_ops = {
223 .get_hwirq = dmar_msi_get_hwirq,
224 .msi_init = dmar_msi_init,
225};
226
227static struct msi_domain_info dmar_msi_domain_info = {
228 .ops = &dmar_msi_domain_ops,
229 .chip = &dmar_msi_controller,
230};
231
232static struct irq_domain *dmar_get_irq_domain(void)
233{
234 static struct irq_domain *dmar_domain;
235 static DEFINE_MUTEX(dmar_lock);
236 struct fwnode_handle *fn;
237
238 mutex_lock(&dmar_lock);
239 if (dmar_domain)
240 goto out;
241
242 fn = irq_domain_alloc_named_fwnode("DMAR-MSI");
243 if (fn) {
244 dmar_domain = msi_create_irq_domain(fn, &dmar_msi_domain_info,
245 x86_vector_domain);
246 irq_domain_free_fwnode(fn);
247 }
248out:
249 mutex_unlock(&dmar_lock);
250 return dmar_domain;
251}
252
253int dmar_alloc_hwirq(int id, int node, void *arg)
254{
255 struct irq_domain *domain = dmar_get_irq_domain();
256 struct irq_alloc_info info;
257
258 if (!domain)
259 return -1;
260
261 init_irq_alloc_info(&info, NULL);
262 info.type = X86_IRQ_ALLOC_TYPE_DMAR;
263 info.dmar_id = id;
264 info.dmar_data = arg;
265
266 return irq_domain_alloc_irqs(domain, 1, node, &info);
267}
268
269void dmar_free_hwirq(int irq)
270{
271 irq_domain_free_irqs(irq, 1);
272}
273#endif
274
275/*
276 * MSI message composition
277 */
278#ifdef CONFIG_HPET_TIMER
279static inline int hpet_dev_id(struct irq_domain *domain)
280{
281 struct msi_domain_info *info = msi_get_domain_info(domain);
282
283 return (int)(long)info->data;
284}
285
286static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
287{
288 hpet_msi_write(irq_data_get_irq_handler_data(data), msg);
289}
290
291static struct irq_chip hpet_msi_controller __ro_after_init = {
292 .name = "HPET-MSI",
293 .irq_unmask = hpet_msi_unmask,
294 .irq_mask = hpet_msi_mask,
295 .irq_ack = irq_chip_ack_parent,
296 .irq_set_affinity = msi_domain_set_affinity,
297 .irq_retrigger = irq_chip_retrigger_hierarchy,
298 .irq_compose_msi_msg = irq_msi_compose_msg,
299 .irq_write_msi_msg = hpet_msi_write_msg,
300 .flags = IRQCHIP_SKIP_SET_WAKE,
301};
302
303static irq_hw_number_t hpet_msi_get_hwirq(struct msi_domain_info *info,
304 msi_alloc_info_t *arg)
305{
306 return arg->hpet_index;
307}
308
309static int hpet_msi_init(struct irq_domain *domain,
310 struct msi_domain_info *info, unsigned int virq,
311 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
312{
313 irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
314 irq_domain_set_info(domain, virq, arg->hpet_index, info->chip, NULL,
315 handle_edge_irq, arg->hpet_data, "edge");
316
317 return 0;
318}
319
320static void hpet_msi_free(struct irq_domain *domain,
321 struct msi_domain_info *info, unsigned int virq)
322{
323 irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
324}
325
326static struct msi_domain_ops hpet_msi_domain_ops = {
327 .get_hwirq = hpet_msi_get_hwirq,
328 .msi_init = hpet_msi_init,
329 .msi_free = hpet_msi_free,
330};
331
332static struct msi_domain_info hpet_msi_domain_info = {
333 .ops = &hpet_msi_domain_ops,
334 .chip = &hpet_msi_controller,
335};
336
337struct irq_domain *hpet_create_irq_domain(int hpet_id)
338{
339 struct msi_domain_info *domain_info;
340 struct irq_domain *parent, *d;
341 struct irq_alloc_info info;
342 struct fwnode_handle *fn;
343
344 if (x86_vector_domain == NULL)
345 return NULL;
346
347 domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL);
348 if (!domain_info)
349 return NULL;
350
351 *domain_info = hpet_msi_domain_info;
352 domain_info->data = (void *)(long)hpet_id;
353
354 init_irq_alloc_info(&info, NULL);
355 info.type = X86_IRQ_ALLOC_TYPE_HPET;
356 info.hpet_id = hpet_id;
357 parent = irq_remapping_get_ir_irq_domain(&info);
358 if (parent == NULL)
359 parent = x86_vector_domain;
360 else
361 hpet_msi_controller.name = "IR-HPET-MSI";
362
363 fn = irq_domain_alloc_named_id_fwnode(hpet_msi_controller.name,
364 hpet_id);
365 if (!fn) {
366 kfree(domain_info);
367 return NULL;
368 }
369
370 d = msi_create_irq_domain(fn, domain_info, parent);
371 irq_domain_free_fwnode(fn);
372 return d;
373}
374
375int hpet_assign_irq(struct irq_domain *domain, struct hpet_dev *dev,
376 int dev_num)
377{
378 struct irq_alloc_info info;
379
380 init_irq_alloc_info(&info, NULL);
381 info.type = X86_IRQ_ALLOC_TYPE_HPET;
382 info.hpet_data = dev;
383 info.hpet_id = hpet_dev_id(domain);
384 info.hpet_index = dev_num;
385
386 return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info);
387}
388#endif