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1// SPDX-License-Identifier: GPL-2.0-only
2#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3
4#include <linux/kernel.h>
5#include <linux/sched.h>
6#include <linux/sched/clock.h>
7#include <linux/init.h>
8#include <linux/export.h>
9#include <linux/timer.h>
10#include <linux/acpi_pmtmr.h>
11#include <linux/cpufreq.h>
12#include <linux/delay.h>
13#include <linux/clocksource.h>
14#include <linux/percpu.h>
15#include <linux/timex.h>
16#include <linux/static_key.h>
17#include <linux/static_call.h>
18
19#include <asm/hpet.h>
20#include <asm/timer.h>
21#include <asm/vgtod.h>
22#include <asm/time.h>
23#include <asm/delay.h>
24#include <asm/hypervisor.h>
25#include <asm/nmi.h>
26#include <asm/x86_init.h>
27#include <asm/geode.h>
28#include <asm/apic.h>
29#include <asm/cpu_device_id.h>
30#include <asm/i8259.h>
31#include <asm/topology.h>
32#include <asm/uv/uv.h>
33
34unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
35EXPORT_SYMBOL(cpu_khz);
36
37unsigned int __read_mostly tsc_khz;
38EXPORT_SYMBOL(tsc_khz);
39
40#define KHZ 1000
41
42/*
43 * TSC can be unstable due to cpufreq or due to unsynced TSCs
44 */
45static int __read_mostly tsc_unstable;
46static unsigned int __initdata tsc_early_khz;
47
48static DEFINE_STATIC_KEY_FALSE_RO(__use_tsc);
49
50int tsc_clocksource_reliable;
51
52static int __read_mostly tsc_force_recalibrate;
53
54static struct clocksource_base art_base_clk = {
55 .id = CSID_X86_ART,
56};
57static bool have_art;
58
59struct cyc2ns {
60 struct cyc2ns_data data[2]; /* 0 + 2*16 = 32 */
61 seqcount_latch_t seq; /* 32 + 4 = 36 */
62
63}; /* fits one cacheline */
64
65static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns);
66
67static int __init tsc_early_khz_setup(char *buf)
68{
69 return kstrtouint(buf, 0, &tsc_early_khz);
70}
71early_param("tsc_early_khz", tsc_early_khz_setup);
72
73__always_inline void __cyc2ns_read(struct cyc2ns_data *data)
74{
75 int seq, idx;
76
77 do {
78 seq = this_cpu_read(cyc2ns.seq.seqcount.sequence);
79 idx = seq & 1;
80
81 data->cyc2ns_offset = this_cpu_read(cyc2ns.data[idx].cyc2ns_offset);
82 data->cyc2ns_mul = this_cpu_read(cyc2ns.data[idx].cyc2ns_mul);
83 data->cyc2ns_shift = this_cpu_read(cyc2ns.data[idx].cyc2ns_shift);
84
85 } while (unlikely(seq != this_cpu_read(cyc2ns.seq.seqcount.sequence)));
86}
87
88__always_inline void cyc2ns_read_begin(struct cyc2ns_data *data)
89{
90 preempt_disable_notrace();
91 __cyc2ns_read(data);
92}
93
94__always_inline void cyc2ns_read_end(void)
95{
96 preempt_enable_notrace();
97}
98
99/*
100 * Accelerators for sched_clock()
101 * convert from cycles(64bits) => nanoseconds (64bits)
102 * basic equation:
103 * ns = cycles / (freq / ns_per_sec)
104 * ns = cycles * (ns_per_sec / freq)
105 * ns = cycles * (10^9 / (cpu_khz * 10^3))
106 * ns = cycles * (10^6 / cpu_khz)
107 *
108 * Then we use scaling math (suggested by george@mvista.com) to get:
109 * ns = cycles * (10^6 * SC / cpu_khz) / SC
110 * ns = cycles * cyc2ns_scale / SC
111 *
112 * And since SC is a constant power of two, we can convert the div
113 * into a shift. The larger SC is, the more accurate the conversion, but
114 * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication
115 * (64-bit result) can be used.
116 *
117 * We can use khz divisor instead of mhz to keep a better precision.
118 * (mathieu.desnoyers@polymtl.ca)
119 *
120 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
121 */
122
123static __always_inline unsigned long long __cycles_2_ns(unsigned long long cyc)
124{
125 struct cyc2ns_data data;
126 unsigned long long ns;
127
128 __cyc2ns_read(&data);
129
130 ns = data.cyc2ns_offset;
131 ns += mul_u64_u32_shr(cyc, data.cyc2ns_mul, data.cyc2ns_shift);
132
133 return ns;
134}
135
136static __always_inline unsigned long long cycles_2_ns(unsigned long long cyc)
137{
138 unsigned long long ns;
139 preempt_disable_notrace();
140 ns = __cycles_2_ns(cyc);
141 preempt_enable_notrace();
142 return ns;
143}
144
145static void __set_cyc2ns_scale(unsigned long khz, int cpu, unsigned long long tsc_now)
146{
147 unsigned long long ns_now;
148 struct cyc2ns_data data;
149 struct cyc2ns *c2n;
150
151 ns_now = cycles_2_ns(tsc_now);
152
153 /*
154 * Compute a new multiplier as per the above comment and ensure our
155 * time function is continuous; see the comment near struct
156 * cyc2ns_data.
157 */
158 clocks_calc_mult_shift(&data.cyc2ns_mul, &data.cyc2ns_shift, khz,
159 NSEC_PER_MSEC, 0);
160
161 /*
162 * cyc2ns_shift is exported via arch_perf_update_userpage() where it is
163 * not expected to be greater than 31 due to the original published
164 * conversion algorithm shifting a 32-bit value (now specifies a 64-bit
165 * value) - refer perf_event_mmap_page documentation in perf_event.h.
166 */
167 if (data.cyc2ns_shift == 32) {
168 data.cyc2ns_shift = 31;
169 data.cyc2ns_mul >>= 1;
170 }
171
172 data.cyc2ns_offset = ns_now -
173 mul_u64_u32_shr(tsc_now, data.cyc2ns_mul, data.cyc2ns_shift);
174
175 c2n = per_cpu_ptr(&cyc2ns, cpu);
176
177 write_seqcount_latch_begin(&c2n->seq);
178 c2n->data[0] = data;
179 write_seqcount_latch(&c2n->seq);
180 c2n->data[1] = data;
181 write_seqcount_latch_end(&c2n->seq);
182}
183
184static void set_cyc2ns_scale(unsigned long khz, int cpu, unsigned long long tsc_now)
185{
186 unsigned long flags;
187
188 local_irq_save(flags);
189 sched_clock_idle_sleep_event();
190
191 if (khz)
192 __set_cyc2ns_scale(khz, cpu, tsc_now);
193
194 sched_clock_idle_wakeup_event();
195 local_irq_restore(flags);
196}
197
198/*
199 * Initialize cyc2ns for boot cpu
200 */
201static void __init cyc2ns_init_boot_cpu(void)
202{
203 struct cyc2ns *c2n = this_cpu_ptr(&cyc2ns);
204
205 seqcount_latch_init(&c2n->seq);
206 __set_cyc2ns_scale(tsc_khz, smp_processor_id(), rdtsc());
207}
208
209/*
210 * Secondary CPUs do not run through tsc_init(), so set up
211 * all the scale factors for all CPUs, assuming the same
212 * speed as the bootup CPU.
213 */
214static void __init cyc2ns_init_secondary_cpus(void)
215{
216 unsigned int cpu, this_cpu = smp_processor_id();
217 struct cyc2ns *c2n = this_cpu_ptr(&cyc2ns);
218 struct cyc2ns_data *data = c2n->data;
219
220 for_each_possible_cpu(cpu) {
221 if (cpu != this_cpu) {
222 seqcount_latch_init(&c2n->seq);
223 c2n = per_cpu_ptr(&cyc2ns, cpu);
224 c2n->data[0] = data[0];
225 c2n->data[1] = data[1];
226 }
227 }
228}
229
230/*
231 * Scheduler clock - returns current time in nanosec units.
232 */
233noinstr u64 native_sched_clock(void)
234{
235 if (static_branch_likely(&__use_tsc)) {
236 u64 tsc_now = rdtsc();
237
238 /* return the value in ns */
239 return __cycles_2_ns(tsc_now);
240 }
241
242 /*
243 * Fall back to jiffies if there's no TSC available:
244 * ( But note that we still use it if the TSC is marked
245 * unstable. We do this because unlike Time Of Day,
246 * the scheduler clock tolerates small errors and it's
247 * very important for it to be as fast as the platform
248 * can achieve it. )
249 */
250
251 /* No locking but a rare wrong value is not a big deal: */
252 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
253}
254
255/*
256 * Generate a sched_clock if you already have a TSC value.
257 */
258u64 native_sched_clock_from_tsc(u64 tsc)
259{
260 return cycles_2_ns(tsc);
261}
262
263/* We need to define a real function for sched_clock, to override the
264 weak default version */
265#ifdef CONFIG_PARAVIRT
266noinstr u64 sched_clock_noinstr(void)
267{
268 return paravirt_sched_clock();
269}
270
271bool using_native_sched_clock(void)
272{
273 return static_call_query(pv_sched_clock) == native_sched_clock;
274}
275#else
276u64 sched_clock_noinstr(void) __attribute__((alias("native_sched_clock")));
277
278bool using_native_sched_clock(void) { return true; }
279#endif
280
281notrace u64 sched_clock(void)
282{
283 u64 now;
284 preempt_disable_notrace();
285 now = sched_clock_noinstr();
286 preempt_enable_notrace();
287 return now;
288}
289
290int check_tsc_unstable(void)
291{
292 return tsc_unstable;
293}
294EXPORT_SYMBOL_GPL(check_tsc_unstable);
295
296#ifdef CONFIG_X86_TSC
297int __init notsc_setup(char *str)
298{
299 mark_tsc_unstable("boot parameter notsc");
300 return 1;
301}
302#else
303/*
304 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
305 * in cpu/common.c
306 */
307int __init notsc_setup(char *str)
308{
309 setup_clear_cpu_cap(X86_FEATURE_TSC);
310 return 1;
311}
312#endif
313
314__setup("notsc", notsc_setup);
315
316static int no_sched_irq_time;
317static int no_tsc_watchdog;
318static int tsc_as_watchdog;
319
320static int __init tsc_setup(char *str)
321{
322 if (!strcmp(str, "reliable"))
323 tsc_clocksource_reliable = 1;
324 if (!strncmp(str, "noirqtime", 9))
325 no_sched_irq_time = 1;
326 if (!strcmp(str, "unstable"))
327 mark_tsc_unstable("boot parameter");
328 if (!strcmp(str, "nowatchdog")) {
329 no_tsc_watchdog = 1;
330 if (tsc_as_watchdog)
331 pr_alert("%s: Overriding earlier tsc=watchdog with tsc=nowatchdog\n",
332 __func__);
333 tsc_as_watchdog = 0;
334 }
335 if (!strcmp(str, "recalibrate"))
336 tsc_force_recalibrate = 1;
337 if (!strcmp(str, "watchdog")) {
338 if (no_tsc_watchdog)
339 pr_alert("%s: tsc=watchdog overridden by earlier tsc=nowatchdog\n",
340 __func__);
341 else
342 tsc_as_watchdog = 1;
343 }
344 return 1;
345}
346
347__setup("tsc=", tsc_setup);
348
349#define MAX_RETRIES 5
350#define TSC_DEFAULT_THRESHOLD 0x20000
351
352/*
353 * Read TSC and the reference counters. Take care of any disturbances
354 */
355static u64 tsc_read_refs(u64 *p, int hpet)
356{
357 u64 t1, t2;
358 u64 thresh = tsc_khz ? tsc_khz >> 5 : TSC_DEFAULT_THRESHOLD;
359 int i;
360
361 for (i = 0; i < MAX_RETRIES; i++) {
362 t1 = get_cycles();
363 if (hpet)
364 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
365 else
366 *p = acpi_pm_read_early();
367 t2 = get_cycles();
368 if ((t2 - t1) < thresh)
369 return t2;
370 }
371 return ULLONG_MAX;
372}
373
374/*
375 * Calculate the TSC frequency from HPET reference
376 */
377static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
378{
379 u64 tmp;
380
381 if (hpet2 < hpet1)
382 hpet2 += 0x100000000ULL;
383 hpet2 -= hpet1;
384 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
385 do_div(tmp, 1000000);
386 deltatsc = div64_u64(deltatsc, tmp);
387
388 return (unsigned long) deltatsc;
389}
390
391/*
392 * Calculate the TSC frequency from PMTimer reference
393 */
394static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
395{
396 u64 tmp;
397
398 if (!pm1 && !pm2)
399 return ULONG_MAX;
400
401 if (pm2 < pm1)
402 pm2 += (u64)ACPI_PM_OVRRUN;
403 pm2 -= pm1;
404 tmp = pm2 * 1000000000LL;
405 do_div(tmp, PMTMR_TICKS_PER_SEC);
406 do_div(deltatsc, tmp);
407
408 return (unsigned long) deltatsc;
409}
410
411#define CAL_MS 10
412#define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
413#define CAL_PIT_LOOPS 1000
414
415#define CAL2_MS 50
416#define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
417#define CAL2_PIT_LOOPS 5000
418
419
420/*
421 * Try to calibrate the TSC against the Programmable
422 * Interrupt Timer and return the frequency of the TSC
423 * in kHz.
424 *
425 * Return ULONG_MAX on failure to calibrate.
426 */
427static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
428{
429 u64 tsc, t1, t2, delta;
430 unsigned long tscmin, tscmax;
431 int pitcnt;
432
433 if (!has_legacy_pic()) {
434 /*
435 * Relies on tsc_early_delay_calibrate() to have given us semi
436 * usable udelay(), wait for the same 50ms we would have with
437 * the PIT loop below.
438 */
439 udelay(10 * USEC_PER_MSEC);
440 udelay(10 * USEC_PER_MSEC);
441 udelay(10 * USEC_PER_MSEC);
442 udelay(10 * USEC_PER_MSEC);
443 udelay(10 * USEC_PER_MSEC);
444 return ULONG_MAX;
445 }
446
447 /* Set the Gate high, disable speaker */
448 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
449
450 /*
451 * Setup CTC channel 2* for mode 0, (interrupt on terminal
452 * count mode), binary count. Set the latch register to 50ms
453 * (LSB then MSB) to begin countdown.
454 */
455 outb(0xb0, 0x43);
456 outb(latch & 0xff, 0x42);
457 outb(latch >> 8, 0x42);
458
459 tsc = t1 = t2 = get_cycles();
460
461 pitcnt = 0;
462 tscmax = 0;
463 tscmin = ULONG_MAX;
464 while ((inb(0x61) & 0x20) == 0) {
465 t2 = get_cycles();
466 delta = t2 - tsc;
467 tsc = t2;
468 if ((unsigned long) delta < tscmin)
469 tscmin = (unsigned int) delta;
470 if ((unsigned long) delta > tscmax)
471 tscmax = (unsigned int) delta;
472 pitcnt++;
473 }
474
475 /*
476 * Sanity checks:
477 *
478 * If we were not able to read the PIT more than loopmin
479 * times, then we have been hit by a massive SMI
480 *
481 * If the maximum is 10 times larger than the minimum,
482 * then we got hit by an SMI as well.
483 */
484 if (pitcnt < loopmin || tscmax > 10 * tscmin)
485 return ULONG_MAX;
486
487 /* Calculate the PIT value */
488 delta = t2 - t1;
489 do_div(delta, ms);
490 return delta;
491}
492
493/*
494 * This reads the current MSB of the PIT counter, and
495 * checks if we are running on sufficiently fast and
496 * non-virtualized hardware.
497 *
498 * Our expectations are:
499 *
500 * - the PIT is running at roughly 1.19MHz
501 *
502 * - each IO is going to take about 1us on real hardware,
503 * but we allow it to be much faster (by a factor of 10) or
504 * _slightly_ slower (ie we allow up to a 2us read+counter
505 * update - anything else implies a unacceptably slow CPU
506 * or PIT for the fast calibration to work.
507 *
508 * - with 256 PIT ticks to read the value, we have 214us to
509 * see the same MSB (and overhead like doing a single TSC
510 * read per MSB value etc).
511 *
512 * - We're doing 2 reads per loop (LSB, MSB), and we expect
513 * them each to take about a microsecond on real hardware.
514 * So we expect a count value of around 100. But we'll be
515 * generous, and accept anything over 50.
516 *
517 * - if the PIT is stuck, and we see *many* more reads, we
518 * return early (and the next caller of pit_expect_msb()
519 * then consider it a failure when they don't see the
520 * next expected value).
521 *
522 * These expectations mean that we know that we have seen the
523 * transition from one expected value to another with a fairly
524 * high accuracy, and we didn't miss any events. We can thus
525 * use the TSC value at the transitions to calculate a pretty
526 * good value for the TSC frequency.
527 */
528static inline int pit_verify_msb(unsigned char val)
529{
530 /* Ignore LSB */
531 inb(0x42);
532 return inb(0x42) == val;
533}
534
535static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
536{
537 int count;
538 u64 tsc = 0, prev_tsc = 0;
539
540 for (count = 0; count < 50000; count++) {
541 if (!pit_verify_msb(val))
542 break;
543 prev_tsc = tsc;
544 tsc = get_cycles();
545 }
546 *deltap = get_cycles() - prev_tsc;
547 *tscp = tsc;
548
549 /*
550 * We require _some_ success, but the quality control
551 * will be based on the error terms on the TSC values.
552 */
553 return count > 5;
554}
555
556/*
557 * How many MSB values do we want to see? We aim for
558 * a maximum error rate of 500ppm (in practice the
559 * real error is much smaller), but refuse to spend
560 * more than 50ms on it.
561 */
562#define MAX_QUICK_PIT_MS 50
563#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
564
565static unsigned long quick_pit_calibrate(void)
566{
567 int i;
568 u64 tsc, delta;
569 unsigned long d1, d2;
570
571 if (!has_legacy_pic())
572 return 0;
573
574 /* Set the Gate high, disable speaker */
575 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
576
577 /*
578 * Counter 2, mode 0 (one-shot), binary count
579 *
580 * NOTE! Mode 2 decrements by two (and then the
581 * output is flipped each time, giving the same
582 * final output frequency as a decrement-by-one),
583 * so mode 0 is much better when looking at the
584 * individual counts.
585 */
586 outb(0xb0, 0x43);
587
588 /* Start at 0xffff */
589 outb(0xff, 0x42);
590 outb(0xff, 0x42);
591
592 /*
593 * The PIT starts counting at the next edge, so we
594 * need to delay for a microsecond. The easiest way
595 * to do that is to just read back the 16-bit counter
596 * once from the PIT.
597 */
598 pit_verify_msb(0);
599
600 if (pit_expect_msb(0xff, &tsc, &d1)) {
601 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
602 if (!pit_expect_msb(0xff-i, &delta, &d2))
603 break;
604
605 delta -= tsc;
606
607 /*
608 * Extrapolate the error and fail fast if the error will
609 * never be below 500 ppm.
610 */
611 if (i == 1 &&
612 d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11)
613 return 0;
614
615 /*
616 * Iterate until the error is less than 500 ppm
617 */
618 if (d1+d2 >= delta >> 11)
619 continue;
620
621 /*
622 * Check the PIT one more time to verify that
623 * all TSC reads were stable wrt the PIT.
624 *
625 * This also guarantees serialization of the
626 * last cycle read ('d2') in pit_expect_msb.
627 */
628 if (!pit_verify_msb(0xfe - i))
629 break;
630 goto success;
631 }
632 }
633 pr_info("Fast TSC calibration failed\n");
634 return 0;
635
636success:
637 /*
638 * Ok, if we get here, then we've seen the
639 * MSB of the PIT decrement 'i' times, and the
640 * error has shrunk to less than 500 ppm.
641 *
642 * As a result, we can depend on there not being
643 * any odd delays anywhere, and the TSC reads are
644 * reliable (within the error).
645 *
646 * kHz = ticks / time-in-seconds / 1000;
647 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
648 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
649 */
650 delta *= PIT_TICK_RATE;
651 do_div(delta, i*256*1000);
652 pr_info("Fast TSC calibration using PIT\n");
653 return delta;
654}
655
656/**
657 * native_calibrate_tsc - determine TSC frequency
658 * Determine TSC frequency via CPUID, else return 0.
659 */
660unsigned long native_calibrate_tsc(void)
661{
662 unsigned int eax_denominator, ebx_numerator, ecx_hz, edx;
663 unsigned int crystal_khz;
664
665 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
666 return 0;
667
668 if (boot_cpu_data.cpuid_level < 0x15)
669 return 0;
670
671 eax_denominator = ebx_numerator = ecx_hz = edx = 0;
672
673 /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */
674 cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx);
675
676 if (ebx_numerator == 0 || eax_denominator == 0)
677 return 0;
678
679 crystal_khz = ecx_hz / 1000;
680
681 /*
682 * Denverton SoCs don't report crystal clock, and also don't support
683 * CPUID.0x16 for the calculation below, so hardcode the 25MHz crystal
684 * clock.
685 */
686 if (crystal_khz == 0 &&
687 boot_cpu_data.x86_vfm == INTEL_ATOM_GOLDMONT_D)
688 crystal_khz = 25000;
689
690 /*
691 * TSC frequency reported directly by CPUID is a "hardware reported"
692 * frequency and is the most accurate one so far we have. This
693 * is considered a known frequency.
694 */
695 if (crystal_khz != 0)
696 setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
697
698 /*
699 * Some Intel SoCs like Skylake and Kabylake don't report the crystal
700 * clock, but we can easily calculate it to a high degree of accuracy
701 * by considering the crystal ratio and the CPU speed.
702 */
703 if (crystal_khz == 0 && boot_cpu_data.cpuid_level >= 0x16) {
704 unsigned int eax_base_mhz, ebx, ecx, edx;
705
706 cpuid(0x16, &eax_base_mhz, &ebx, &ecx, &edx);
707 crystal_khz = eax_base_mhz * 1000 *
708 eax_denominator / ebx_numerator;
709 }
710
711 if (crystal_khz == 0)
712 return 0;
713
714 /*
715 * For Atom SoCs TSC is the only reliable clocksource.
716 * Mark TSC reliable so no watchdog on it.
717 */
718 if (boot_cpu_data.x86_vfm == INTEL_ATOM_GOLDMONT)
719 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
720
721#ifdef CONFIG_X86_LOCAL_APIC
722 /*
723 * The local APIC appears to be fed by the core crystal clock
724 * (which sounds entirely sensible). We can set the global
725 * lapic_timer_period here to avoid having to calibrate the APIC
726 * timer later.
727 */
728 lapic_timer_period = crystal_khz * 1000 / HZ;
729#endif
730
731 return crystal_khz * ebx_numerator / eax_denominator;
732}
733
734static unsigned long cpu_khz_from_cpuid(void)
735{
736 unsigned int eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx;
737
738 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
739 return 0;
740
741 if (boot_cpu_data.cpuid_level < 0x16)
742 return 0;
743
744 eax_base_mhz = ebx_max_mhz = ecx_bus_mhz = edx = 0;
745
746 cpuid(0x16, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx);
747
748 return eax_base_mhz * 1000;
749}
750
751/*
752 * calibrate cpu using pit, hpet, and ptimer methods. They are available
753 * later in boot after acpi is initialized.
754 */
755static unsigned long pit_hpet_ptimer_calibrate_cpu(void)
756{
757 u64 tsc1, tsc2, delta, ref1, ref2;
758 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
759 unsigned long flags, latch, ms;
760 int hpet = is_hpet_enabled(), i, loopmin;
761
762 /*
763 * Run 5 calibration loops to get the lowest frequency value
764 * (the best estimate). We use two different calibration modes
765 * here:
766 *
767 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
768 * load a timeout of 50ms. We read the time right after we
769 * started the timer and wait until the PIT count down reaches
770 * zero. In each wait loop iteration we read the TSC and check
771 * the delta to the previous read. We keep track of the min
772 * and max values of that delta. The delta is mostly defined
773 * by the IO time of the PIT access, so we can detect when
774 * any disturbance happened between the two reads. If the
775 * maximum time is significantly larger than the minimum time,
776 * then we discard the result and have another try.
777 *
778 * 2) Reference counter. If available we use the HPET or the
779 * PMTIMER as a reference to check the sanity of that value.
780 * We use separate TSC readouts and check inside of the
781 * reference read for any possible disturbance. We discard
782 * disturbed values here as well. We do that around the PIT
783 * calibration delay loop as we have to wait for a certain
784 * amount of time anyway.
785 */
786
787 /* Preset PIT loop values */
788 latch = CAL_LATCH;
789 ms = CAL_MS;
790 loopmin = CAL_PIT_LOOPS;
791
792 for (i = 0; i < 3; i++) {
793 unsigned long tsc_pit_khz;
794
795 /*
796 * Read the start value and the reference count of
797 * hpet/pmtimer when available. Then do the PIT
798 * calibration, which will take at least 50ms, and
799 * read the end value.
800 */
801 local_irq_save(flags);
802 tsc1 = tsc_read_refs(&ref1, hpet);
803 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
804 tsc2 = tsc_read_refs(&ref2, hpet);
805 local_irq_restore(flags);
806
807 /* Pick the lowest PIT TSC calibration so far */
808 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
809
810 /* hpet or pmtimer available ? */
811 if (ref1 == ref2)
812 continue;
813
814 /* Check, whether the sampling was disturbed */
815 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
816 continue;
817
818 tsc2 = (tsc2 - tsc1) * 1000000LL;
819 if (hpet)
820 tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
821 else
822 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
823
824 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
825
826 /* Check the reference deviation */
827 delta = ((u64) tsc_pit_min) * 100;
828 do_div(delta, tsc_ref_min);
829
830 /*
831 * If both calibration results are inside a 10% window
832 * then we can be sure, that the calibration
833 * succeeded. We break out of the loop right away. We
834 * use the reference value, as it is more precise.
835 */
836 if (delta >= 90 && delta <= 110) {
837 pr_info("PIT calibration matches %s. %d loops\n",
838 hpet ? "HPET" : "PMTIMER", i + 1);
839 return tsc_ref_min;
840 }
841
842 /*
843 * Check whether PIT failed more than once. This
844 * happens in virtualized environments. We need to
845 * give the virtual PC a slightly longer timeframe for
846 * the HPET/PMTIMER to make the result precise.
847 */
848 if (i == 1 && tsc_pit_min == ULONG_MAX) {
849 latch = CAL2_LATCH;
850 ms = CAL2_MS;
851 loopmin = CAL2_PIT_LOOPS;
852 }
853 }
854
855 /*
856 * Now check the results.
857 */
858 if (tsc_pit_min == ULONG_MAX) {
859 /* PIT gave no useful value */
860 pr_warn("Unable to calibrate against PIT\n");
861
862 /* We don't have an alternative source, disable TSC */
863 if (!hpet && !ref1 && !ref2) {
864 pr_notice("No reference (HPET/PMTIMER) available\n");
865 return 0;
866 }
867
868 /* The alternative source failed as well, disable TSC */
869 if (tsc_ref_min == ULONG_MAX) {
870 pr_warn("HPET/PMTIMER calibration failed\n");
871 return 0;
872 }
873
874 /* Use the alternative source */
875 pr_info("using %s reference calibration\n",
876 hpet ? "HPET" : "PMTIMER");
877
878 return tsc_ref_min;
879 }
880
881 /* We don't have an alternative source, use the PIT calibration value */
882 if (!hpet && !ref1 && !ref2) {
883 pr_info("Using PIT calibration value\n");
884 return tsc_pit_min;
885 }
886
887 /* The alternative source failed, use the PIT calibration value */
888 if (tsc_ref_min == ULONG_MAX) {
889 pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n");
890 return tsc_pit_min;
891 }
892
893 /*
894 * The calibration values differ too much. In doubt, we use
895 * the PIT value as we know that there are PMTIMERs around
896 * running at double speed. At least we let the user know:
897 */
898 pr_warn("PIT calibration deviates from %s: %lu %lu\n",
899 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
900 pr_info("Using PIT calibration value\n");
901 return tsc_pit_min;
902}
903
904/**
905 * native_calibrate_cpu_early - can calibrate the cpu early in boot
906 */
907unsigned long native_calibrate_cpu_early(void)
908{
909 unsigned long flags, fast_calibrate = cpu_khz_from_cpuid();
910
911 if (!fast_calibrate)
912 fast_calibrate = cpu_khz_from_msr();
913 if (!fast_calibrate) {
914 local_irq_save(flags);
915 fast_calibrate = quick_pit_calibrate();
916 local_irq_restore(flags);
917 }
918 return fast_calibrate;
919}
920
921
922/**
923 * native_calibrate_cpu - calibrate the cpu
924 */
925static unsigned long native_calibrate_cpu(void)
926{
927 unsigned long tsc_freq = native_calibrate_cpu_early();
928
929 if (!tsc_freq)
930 tsc_freq = pit_hpet_ptimer_calibrate_cpu();
931
932 return tsc_freq;
933}
934
935void recalibrate_cpu_khz(void)
936{
937#ifndef CONFIG_SMP
938 unsigned long cpu_khz_old = cpu_khz;
939
940 if (!boot_cpu_has(X86_FEATURE_TSC))
941 return;
942
943 cpu_khz = x86_platform.calibrate_cpu();
944 tsc_khz = x86_platform.calibrate_tsc();
945 if (tsc_khz == 0)
946 tsc_khz = cpu_khz;
947 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
948 cpu_khz = tsc_khz;
949 cpu_data(0).loops_per_jiffy = cpufreq_scale(cpu_data(0).loops_per_jiffy,
950 cpu_khz_old, cpu_khz);
951#endif
952}
953EXPORT_SYMBOL_GPL(recalibrate_cpu_khz);
954
955
956static unsigned long long cyc2ns_suspend;
957
958void tsc_save_sched_clock_state(void)
959{
960 if (!sched_clock_stable())
961 return;
962
963 cyc2ns_suspend = sched_clock();
964}
965
966/*
967 * Even on processors with invariant TSC, TSC gets reset in some the
968 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
969 * arbitrary value (still sync'd across cpu's) during resume from such sleep
970 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
971 * that sched_clock() continues from the point where it was left off during
972 * suspend.
973 */
974void tsc_restore_sched_clock_state(void)
975{
976 unsigned long long offset;
977 unsigned long flags;
978 int cpu;
979
980 if (!sched_clock_stable())
981 return;
982
983 local_irq_save(flags);
984
985 /*
986 * We're coming out of suspend, there's no concurrency yet; don't
987 * bother being nice about the RCU stuff, just write to both
988 * data fields.
989 */
990
991 this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0);
992 this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0);
993
994 offset = cyc2ns_suspend - sched_clock();
995
996 for_each_possible_cpu(cpu) {
997 per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset;
998 per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset;
999 }
1000
1001 local_irq_restore(flags);
1002}
1003
1004#ifdef CONFIG_CPU_FREQ
1005/*
1006 * Frequency scaling support. Adjust the TSC based timer when the CPU frequency
1007 * changes.
1008 *
1009 * NOTE: On SMP the situation is not fixable in general, so simply mark the TSC
1010 * as unstable and give up in those cases.
1011 *
1012 * Should fix up last_tsc too. Currently gettimeofday in the
1013 * first tick after the change will be slightly wrong.
1014 */
1015
1016static unsigned int ref_freq;
1017static unsigned long loops_per_jiffy_ref;
1018static unsigned long tsc_khz_ref;
1019
1020static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
1021 void *data)
1022{
1023 struct cpufreq_freqs *freq = data;
1024
1025 if (num_online_cpus() > 1) {
1026 mark_tsc_unstable("cpufreq changes on SMP");
1027 return 0;
1028 }
1029
1030 if (!ref_freq) {
1031 ref_freq = freq->old;
1032 loops_per_jiffy_ref = boot_cpu_data.loops_per_jiffy;
1033 tsc_khz_ref = tsc_khz;
1034 }
1035
1036 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
1037 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
1038 boot_cpu_data.loops_per_jiffy =
1039 cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
1040
1041 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
1042 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
1043 mark_tsc_unstable("cpufreq changes");
1044
1045 set_cyc2ns_scale(tsc_khz, freq->policy->cpu, rdtsc());
1046 }
1047
1048 return 0;
1049}
1050
1051static struct notifier_block time_cpufreq_notifier_block = {
1052 .notifier_call = time_cpufreq_notifier
1053};
1054
1055static int __init cpufreq_register_tsc_scaling(void)
1056{
1057 if (!boot_cpu_has(X86_FEATURE_TSC))
1058 return 0;
1059 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1060 return 0;
1061 cpufreq_register_notifier(&time_cpufreq_notifier_block,
1062 CPUFREQ_TRANSITION_NOTIFIER);
1063 return 0;
1064}
1065
1066core_initcall(cpufreq_register_tsc_scaling);
1067
1068#endif /* CONFIG_CPU_FREQ */
1069
1070#define ART_CPUID_LEAF (0x15)
1071#define ART_MIN_DENOMINATOR (1)
1072
1073
1074/*
1075 * If ART is present detect the numerator:denominator to convert to TSC
1076 */
1077static void __init detect_art(void)
1078{
1079 unsigned int unused;
1080
1081 if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF)
1082 return;
1083
1084 /*
1085 * Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required,
1086 * and the TSC counter resets must not occur asynchronously.
1087 */
1088 if (boot_cpu_has(X86_FEATURE_HYPERVISOR) ||
1089 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) ||
1090 !boot_cpu_has(X86_FEATURE_TSC_ADJUST) ||
1091 tsc_async_resets)
1092 return;
1093
1094 cpuid(ART_CPUID_LEAF, &art_base_clk.denominator,
1095 &art_base_clk.numerator, &art_base_clk.freq_khz, &unused);
1096
1097 art_base_clk.freq_khz /= KHZ;
1098 if (art_base_clk.denominator < ART_MIN_DENOMINATOR)
1099 return;
1100
1101 rdmsrl(MSR_IA32_TSC_ADJUST, art_base_clk.offset);
1102
1103 /* Make this sticky over multiple CPU init calls */
1104 setup_force_cpu_cap(X86_FEATURE_ART);
1105}
1106
1107
1108/* clocksource code */
1109
1110static void tsc_resume(struct clocksource *cs)
1111{
1112 tsc_verify_tsc_adjust(true);
1113}
1114
1115/*
1116 * We used to compare the TSC to the cycle_last value in the clocksource
1117 * structure to avoid a nasty time-warp. This can be observed in a
1118 * very small window right after one CPU updated cycle_last under
1119 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
1120 * is smaller than the cycle_last reference value due to a TSC which
1121 * is slightly behind. This delta is nowhere else observable, but in
1122 * that case it results in a forward time jump in the range of hours
1123 * due to the unsigned delta calculation of the time keeping core
1124 * code, which is necessary to support wrapping clocksources like pm
1125 * timer.
1126 *
1127 * This sanity check is now done in the core timekeeping code.
1128 * checking the result of read_tsc() - cycle_last for being negative.
1129 * That works because CLOCKSOURCE_MASK(64) does not mask out any bit.
1130 */
1131static u64 read_tsc(struct clocksource *cs)
1132{
1133 return (u64)rdtsc_ordered();
1134}
1135
1136static void tsc_cs_mark_unstable(struct clocksource *cs)
1137{
1138 if (tsc_unstable)
1139 return;
1140
1141 tsc_unstable = 1;
1142 if (using_native_sched_clock())
1143 clear_sched_clock_stable();
1144 disable_sched_clock_irqtime();
1145 pr_info("Marking TSC unstable due to clocksource watchdog\n");
1146}
1147
1148static void tsc_cs_tick_stable(struct clocksource *cs)
1149{
1150 if (tsc_unstable)
1151 return;
1152
1153 if (using_native_sched_clock())
1154 sched_clock_tick_stable();
1155}
1156
1157static int tsc_cs_enable(struct clocksource *cs)
1158{
1159 vclocks_set_used(VDSO_CLOCKMODE_TSC);
1160 return 0;
1161}
1162
1163/*
1164 * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc()
1165 */
1166static struct clocksource clocksource_tsc_early = {
1167 .name = "tsc-early",
1168 .rating = 299,
1169 .uncertainty_margin = 32 * NSEC_PER_MSEC,
1170 .read = read_tsc,
1171 .mask = CLOCKSOURCE_MASK(64),
1172 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
1173 CLOCK_SOURCE_MUST_VERIFY,
1174 .id = CSID_X86_TSC_EARLY,
1175 .vdso_clock_mode = VDSO_CLOCKMODE_TSC,
1176 .enable = tsc_cs_enable,
1177 .resume = tsc_resume,
1178 .mark_unstable = tsc_cs_mark_unstable,
1179 .tick_stable = tsc_cs_tick_stable,
1180 .list = LIST_HEAD_INIT(clocksource_tsc_early.list),
1181};
1182
1183/*
1184 * Must mark VALID_FOR_HRES early such that when we unregister tsc_early
1185 * this one will immediately take over. We will only register if TSC has
1186 * been found good.
1187 */
1188static struct clocksource clocksource_tsc = {
1189 .name = "tsc",
1190 .rating = 300,
1191 .read = read_tsc,
1192 .mask = CLOCKSOURCE_MASK(64),
1193 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
1194 CLOCK_SOURCE_VALID_FOR_HRES |
1195 CLOCK_SOURCE_MUST_VERIFY |
1196 CLOCK_SOURCE_VERIFY_PERCPU,
1197 .id = CSID_X86_TSC,
1198 .vdso_clock_mode = VDSO_CLOCKMODE_TSC,
1199 .enable = tsc_cs_enable,
1200 .resume = tsc_resume,
1201 .mark_unstable = tsc_cs_mark_unstable,
1202 .tick_stable = tsc_cs_tick_stable,
1203 .list = LIST_HEAD_INIT(clocksource_tsc.list),
1204};
1205
1206void mark_tsc_unstable(char *reason)
1207{
1208 if (tsc_unstable)
1209 return;
1210
1211 tsc_unstable = 1;
1212 if (using_native_sched_clock())
1213 clear_sched_clock_stable();
1214 disable_sched_clock_irqtime();
1215 pr_info("Marking TSC unstable due to %s\n", reason);
1216
1217 clocksource_mark_unstable(&clocksource_tsc_early);
1218 clocksource_mark_unstable(&clocksource_tsc);
1219}
1220
1221EXPORT_SYMBOL_GPL(mark_tsc_unstable);
1222
1223static void __init tsc_disable_clocksource_watchdog(void)
1224{
1225 clocksource_tsc_early.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
1226 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
1227}
1228
1229bool tsc_clocksource_watchdog_disabled(void)
1230{
1231 return !(clocksource_tsc.flags & CLOCK_SOURCE_MUST_VERIFY) &&
1232 tsc_as_watchdog && !no_tsc_watchdog;
1233}
1234
1235static void __init check_system_tsc_reliable(void)
1236{
1237#if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC)
1238 if (is_geode_lx()) {
1239 /* RTSC counts during suspend */
1240#define RTSC_SUSP 0x100
1241 unsigned long res_low, res_high;
1242
1243 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
1244 /* Geode_LX - the OLPC CPU has a very reliable TSC */
1245 if (res_low & RTSC_SUSP)
1246 tsc_clocksource_reliable = 1;
1247 }
1248#endif
1249 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
1250 tsc_clocksource_reliable = 1;
1251
1252 /*
1253 * Disable the clocksource watchdog when the system has:
1254 * - TSC running at constant frequency
1255 * - TSC which does not stop in C-States
1256 * - the TSC_ADJUST register which allows to detect even minimal
1257 * modifications
1258 * - not more than four packages
1259 */
1260 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
1261 boot_cpu_has(X86_FEATURE_NONSTOP_TSC) &&
1262 boot_cpu_has(X86_FEATURE_TSC_ADJUST) &&
1263 topology_max_packages() <= 4)
1264 tsc_disable_clocksource_watchdog();
1265}
1266
1267/*
1268 * Make an educated guess if the TSC is trustworthy and synchronized
1269 * over all CPUs.
1270 */
1271int unsynchronized_tsc(void)
1272{
1273 if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_unstable)
1274 return 1;
1275
1276#ifdef CONFIG_SMP
1277 if (apic_is_clustered_box())
1278 return 1;
1279#endif
1280
1281 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1282 return 0;
1283
1284 if (tsc_clocksource_reliable)
1285 return 0;
1286 /*
1287 * Intel systems are normally all synchronized.
1288 * Exceptions must mark TSC as unstable:
1289 */
1290 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1291 /* assume multi socket systems are not synchronized: */
1292 if (topology_max_packages() > 1)
1293 return 1;
1294 }
1295
1296 return 0;
1297}
1298
1299static void tsc_refine_calibration_work(struct work_struct *work);
1300static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
1301/**
1302 * tsc_refine_calibration_work - Further refine tsc freq calibration
1303 * @work: ignored.
1304 *
1305 * This functions uses delayed work over a period of a
1306 * second to further refine the TSC freq value. Since this is
1307 * timer based, instead of loop based, we don't block the boot
1308 * process while this longer calibration is done.
1309 *
1310 * If there are any calibration anomalies (too many SMIs, etc),
1311 * or the refined calibration is off by 1% of the fast early
1312 * calibration, we throw out the new calibration and use the
1313 * early calibration.
1314 */
1315static void tsc_refine_calibration_work(struct work_struct *work)
1316{
1317 static u64 tsc_start = ULLONG_MAX, ref_start;
1318 static int hpet;
1319 u64 tsc_stop, ref_stop, delta;
1320 unsigned long freq;
1321 int cpu;
1322
1323 /* Don't bother refining TSC on unstable systems */
1324 if (tsc_unstable)
1325 goto unreg;
1326
1327 /*
1328 * Since the work is started early in boot, we may be
1329 * delayed the first time we expire. So set the workqueue
1330 * again once we know timers are working.
1331 */
1332 if (tsc_start == ULLONG_MAX) {
1333restart:
1334 /*
1335 * Only set hpet once, to avoid mixing hardware
1336 * if the hpet becomes enabled later.
1337 */
1338 hpet = is_hpet_enabled();
1339 tsc_start = tsc_read_refs(&ref_start, hpet);
1340 schedule_delayed_work(&tsc_irqwork, HZ);
1341 return;
1342 }
1343
1344 tsc_stop = tsc_read_refs(&ref_stop, hpet);
1345
1346 /* hpet or pmtimer available ? */
1347 if (ref_start == ref_stop)
1348 goto out;
1349
1350 /* Check, whether the sampling was disturbed */
1351 if (tsc_stop == ULLONG_MAX)
1352 goto restart;
1353
1354 delta = tsc_stop - tsc_start;
1355 delta *= 1000000LL;
1356 if (hpet)
1357 freq = calc_hpet_ref(delta, ref_start, ref_stop);
1358 else
1359 freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
1360
1361 /* Will hit this only if tsc_force_recalibrate has been set */
1362 if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) {
1363
1364 /* Warn if the deviation exceeds 500 ppm */
1365 if (abs(tsc_khz - freq) > (tsc_khz >> 11)) {
1366 pr_warn("Warning: TSC freq calibrated by CPUID/MSR differs from what is calibrated by HW timer, please check with vendor!!\n");
1367 pr_info("Previous calibrated TSC freq:\t %lu.%03lu MHz\n",
1368 (unsigned long)tsc_khz / 1000,
1369 (unsigned long)tsc_khz % 1000);
1370 }
1371
1372 pr_info("TSC freq recalibrated by [%s]:\t %lu.%03lu MHz\n",
1373 hpet ? "HPET" : "PM_TIMER",
1374 (unsigned long)freq / 1000,
1375 (unsigned long)freq % 1000);
1376
1377 return;
1378 }
1379
1380 /* Make sure we're within 1% */
1381 if (abs(tsc_khz - freq) > tsc_khz/100)
1382 goto out;
1383
1384 tsc_khz = freq;
1385 pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",
1386 (unsigned long)tsc_khz / 1000,
1387 (unsigned long)tsc_khz % 1000);
1388
1389 /* Inform the TSC deadline clockevent devices about the recalibration */
1390 lapic_update_tsc_freq();
1391
1392 /* Update the sched_clock() rate to match the clocksource one */
1393 for_each_possible_cpu(cpu)
1394 set_cyc2ns_scale(tsc_khz, cpu, tsc_stop);
1395
1396out:
1397 if (tsc_unstable)
1398 goto unreg;
1399
1400 if (boot_cpu_has(X86_FEATURE_ART)) {
1401 have_art = true;
1402 clocksource_tsc.base = &art_base_clk;
1403 }
1404 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1405unreg:
1406 clocksource_unregister(&clocksource_tsc_early);
1407}
1408
1409
1410static int __init init_tsc_clocksource(void)
1411{
1412 if (!boot_cpu_has(X86_FEATURE_TSC) || !tsc_khz)
1413 return 0;
1414
1415 if (tsc_unstable) {
1416 clocksource_unregister(&clocksource_tsc_early);
1417 return 0;
1418 }
1419
1420 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3))
1421 clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1422
1423 /*
1424 * When TSC frequency is known (retrieved via MSR or CPUID), we skip
1425 * the refined calibration and directly register it as a clocksource.
1426 */
1427 if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) {
1428 if (boot_cpu_has(X86_FEATURE_ART)) {
1429 have_art = true;
1430 clocksource_tsc.base = &art_base_clk;
1431 }
1432 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1433 clocksource_unregister(&clocksource_tsc_early);
1434
1435 if (!tsc_force_recalibrate)
1436 return 0;
1437 }
1438
1439 schedule_delayed_work(&tsc_irqwork, 0);
1440 return 0;
1441}
1442/*
1443 * We use device_initcall here, to ensure we run after the hpet
1444 * is fully initialized, which may occur at fs_initcall time.
1445 */
1446device_initcall(init_tsc_clocksource);
1447
1448static bool __init determine_cpu_tsc_frequencies(bool early)
1449{
1450 /* Make sure that cpu and tsc are not already calibrated */
1451 WARN_ON(cpu_khz || tsc_khz);
1452
1453 if (early) {
1454 cpu_khz = x86_platform.calibrate_cpu();
1455 if (tsc_early_khz) {
1456 tsc_khz = tsc_early_khz;
1457 } else {
1458 tsc_khz = x86_platform.calibrate_tsc();
1459 clocksource_tsc.freq_khz = tsc_khz;
1460 }
1461 } else {
1462 /* We should not be here with non-native cpu calibration */
1463 WARN_ON(x86_platform.calibrate_cpu != native_calibrate_cpu);
1464 cpu_khz = pit_hpet_ptimer_calibrate_cpu();
1465 }
1466
1467 /*
1468 * Trust non-zero tsc_khz as authoritative,
1469 * and use it to sanity check cpu_khz,
1470 * which will be off if system timer is off.
1471 */
1472 if (tsc_khz == 0)
1473 tsc_khz = cpu_khz;
1474 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
1475 cpu_khz = tsc_khz;
1476
1477 if (tsc_khz == 0)
1478 return false;
1479
1480 pr_info("Detected %lu.%03lu MHz processor\n",
1481 (unsigned long)cpu_khz / KHZ,
1482 (unsigned long)cpu_khz % KHZ);
1483
1484 if (cpu_khz != tsc_khz) {
1485 pr_info("Detected %lu.%03lu MHz TSC",
1486 (unsigned long)tsc_khz / KHZ,
1487 (unsigned long)tsc_khz % KHZ);
1488 }
1489 return true;
1490}
1491
1492static unsigned long __init get_loops_per_jiffy(void)
1493{
1494 u64 lpj = (u64)tsc_khz * KHZ;
1495
1496 do_div(lpj, HZ);
1497 return lpj;
1498}
1499
1500static void __init tsc_enable_sched_clock(void)
1501{
1502 loops_per_jiffy = get_loops_per_jiffy();
1503 use_tsc_delay();
1504
1505 /* Sanitize TSC ADJUST before cyc2ns gets initialized */
1506 tsc_store_and_check_tsc_adjust(true);
1507 cyc2ns_init_boot_cpu();
1508 static_branch_enable(&__use_tsc);
1509}
1510
1511void __init tsc_early_init(void)
1512{
1513 if (!boot_cpu_has(X86_FEATURE_TSC))
1514 return;
1515 /* Don't change UV TSC multi-chassis synchronization */
1516 if (is_early_uv_system())
1517 return;
1518 if (!determine_cpu_tsc_frequencies(true))
1519 return;
1520 tsc_enable_sched_clock();
1521}
1522
1523void __init tsc_init(void)
1524{
1525 if (!cpu_feature_enabled(X86_FEATURE_TSC)) {
1526 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1527 return;
1528 }
1529
1530 /*
1531 * native_calibrate_cpu_early can only calibrate using methods that are
1532 * available early in boot.
1533 */
1534 if (x86_platform.calibrate_cpu == native_calibrate_cpu_early)
1535 x86_platform.calibrate_cpu = native_calibrate_cpu;
1536
1537 if (!tsc_khz) {
1538 /* We failed to determine frequencies earlier, try again */
1539 if (!determine_cpu_tsc_frequencies(false)) {
1540 mark_tsc_unstable("could not calculate TSC khz");
1541 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1542 return;
1543 }
1544 tsc_enable_sched_clock();
1545 }
1546
1547 cyc2ns_init_secondary_cpus();
1548
1549 if (!no_sched_irq_time)
1550 enable_sched_clock_irqtime();
1551
1552 lpj_fine = get_loops_per_jiffy();
1553
1554 check_system_tsc_reliable();
1555
1556 if (unsynchronized_tsc()) {
1557 mark_tsc_unstable("TSCs unsynchronized");
1558 return;
1559 }
1560
1561 if (tsc_clocksource_reliable || no_tsc_watchdog)
1562 tsc_disable_clocksource_watchdog();
1563
1564 clocksource_register_khz(&clocksource_tsc_early, tsc_khz);
1565 detect_art();
1566}
1567
1568#ifdef CONFIG_SMP
1569/*
1570 * Check whether existing calibration data can be reused.
1571 */
1572unsigned long calibrate_delay_is_known(void)
1573{
1574 int sibling, cpu = smp_processor_id();
1575 int constant_tsc = cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC);
1576 const struct cpumask *mask = topology_core_cpumask(cpu);
1577
1578 /*
1579 * If TSC has constant frequency and TSC is synchronized across
1580 * sockets then reuse CPU0 calibration.
1581 */
1582 if (constant_tsc && !tsc_unstable)
1583 return cpu_data(0).loops_per_jiffy;
1584
1585 /*
1586 * If TSC has constant frequency and TSC is not synchronized across
1587 * sockets and this is not the first CPU in the socket, then reuse
1588 * the calibration value of an already online CPU on that socket.
1589 *
1590 * This assumes that CONSTANT_TSC is consistent for all CPUs in a
1591 * socket.
1592 */
1593 if (!constant_tsc || !mask)
1594 return 0;
1595
1596 sibling = cpumask_any_but(mask, cpu);
1597 if (sibling < nr_cpu_ids)
1598 return cpu_data(sibling).loops_per_jiffy;
1599 return 0;
1600}
1601#endif
1#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
2
3#include <linux/kernel.h>
4#include <linux/sched.h>
5#include <linux/init.h>
6#include <linux/module.h>
7#include <linux/timer.h>
8#include <linux/acpi_pmtmr.h>
9#include <linux/cpufreq.h>
10#include <linux/delay.h>
11#include <linux/clocksource.h>
12#include <linux/percpu.h>
13#include <linux/timex.h>
14#include <linux/static_key.h>
15
16#include <asm/hpet.h>
17#include <asm/timer.h>
18#include <asm/vgtod.h>
19#include <asm/time.h>
20#include <asm/delay.h>
21#include <asm/hypervisor.h>
22#include <asm/nmi.h>
23#include <asm/x86_init.h>
24#include <asm/geode.h>
25
26unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
27EXPORT_SYMBOL(cpu_khz);
28
29unsigned int __read_mostly tsc_khz;
30EXPORT_SYMBOL(tsc_khz);
31
32/*
33 * TSC can be unstable due to cpufreq or due to unsynced TSCs
34 */
35static int __read_mostly tsc_unstable;
36
37/* native_sched_clock() is called before tsc_init(), so
38 we must start with the TSC soft disabled to prevent
39 erroneous rdtsc usage on !cpu_has_tsc processors */
40static int __read_mostly tsc_disabled = -1;
41
42static DEFINE_STATIC_KEY_FALSE(__use_tsc);
43
44int tsc_clocksource_reliable;
45
46static u32 art_to_tsc_numerator;
47static u32 art_to_tsc_denominator;
48static u64 art_to_tsc_offset;
49struct clocksource *art_related_clocksource;
50
51/*
52 * Use a ring-buffer like data structure, where a writer advances the head by
53 * writing a new data entry and a reader advances the tail when it observes a
54 * new entry.
55 *
56 * Writers are made to wait on readers until there's space to write a new
57 * entry.
58 *
59 * This means that we can always use an {offset, mul} pair to compute a ns
60 * value that is 'roughly' in the right direction, even if we're writing a new
61 * {offset, mul} pair during the clock read.
62 *
63 * The down-side is that we can no longer guarantee strict monotonicity anymore
64 * (assuming the TSC was that to begin with), because while we compute the
65 * intersection point of the two clock slopes and make sure the time is
66 * continuous at the point of switching; we can no longer guarantee a reader is
67 * strictly before or after the switch point.
68 *
69 * It does mean a reader no longer needs to disable IRQs in order to avoid
70 * CPU-Freq updates messing with his times, and similarly an NMI reader will
71 * no longer run the risk of hitting half-written state.
72 */
73
74struct cyc2ns {
75 struct cyc2ns_data data[2]; /* 0 + 2*24 = 48 */
76 struct cyc2ns_data *head; /* 48 + 8 = 56 */
77 struct cyc2ns_data *tail; /* 56 + 8 = 64 */
78}; /* exactly fits one cacheline */
79
80static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns);
81
82struct cyc2ns_data *cyc2ns_read_begin(void)
83{
84 struct cyc2ns_data *head;
85
86 preempt_disable();
87
88 head = this_cpu_read(cyc2ns.head);
89 /*
90 * Ensure we observe the entry when we observe the pointer to it.
91 * matches the wmb from cyc2ns_write_end().
92 */
93 smp_read_barrier_depends();
94 head->__count++;
95 barrier();
96
97 return head;
98}
99
100void cyc2ns_read_end(struct cyc2ns_data *head)
101{
102 barrier();
103 /*
104 * If we're the outer most nested read; update the tail pointer
105 * when we're done. This notifies possible pending writers
106 * that we've observed the head pointer and that the other
107 * entry is now free.
108 */
109 if (!--head->__count) {
110 /*
111 * x86-TSO does not reorder writes with older reads;
112 * therefore once this write becomes visible to another
113 * cpu, we must be finished reading the cyc2ns_data.
114 *
115 * matches with cyc2ns_write_begin().
116 */
117 this_cpu_write(cyc2ns.tail, head);
118 }
119 preempt_enable();
120}
121
122/*
123 * Begin writing a new @data entry for @cpu.
124 *
125 * Assumes some sort of write side lock; currently 'provided' by the assumption
126 * that cpufreq will call its notifiers sequentially.
127 */
128static struct cyc2ns_data *cyc2ns_write_begin(int cpu)
129{
130 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
131 struct cyc2ns_data *data = c2n->data;
132
133 if (data == c2n->head)
134 data++;
135
136 /* XXX send an IPI to @cpu in order to guarantee a read? */
137
138 /*
139 * When we observe the tail write from cyc2ns_read_end(),
140 * the cpu must be done with that entry and its safe
141 * to start writing to it.
142 */
143 while (c2n->tail == data)
144 cpu_relax();
145
146 return data;
147}
148
149static void cyc2ns_write_end(int cpu, struct cyc2ns_data *data)
150{
151 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
152
153 /*
154 * Ensure the @data writes are visible before we publish the
155 * entry. Matches the data-depencency in cyc2ns_read_begin().
156 */
157 smp_wmb();
158
159 ACCESS_ONCE(c2n->head) = data;
160}
161
162/*
163 * Accelerators for sched_clock()
164 * convert from cycles(64bits) => nanoseconds (64bits)
165 * basic equation:
166 * ns = cycles / (freq / ns_per_sec)
167 * ns = cycles * (ns_per_sec / freq)
168 * ns = cycles * (10^9 / (cpu_khz * 10^3))
169 * ns = cycles * (10^6 / cpu_khz)
170 *
171 * Then we use scaling math (suggested by george@mvista.com) to get:
172 * ns = cycles * (10^6 * SC / cpu_khz) / SC
173 * ns = cycles * cyc2ns_scale / SC
174 *
175 * And since SC is a constant power of two, we can convert the div
176 * into a shift. The larger SC is, the more accurate the conversion, but
177 * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication
178 * (64-bit result) can be used.
179 *
180 * We can use khz divisor instead of mhz to keep a better precision.
181 * (mathieu.desnoyers@polymtl.ca)
182 *
183 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
184 */
185
186static void cyc2ns_data_init(struct cyc2ns_data *data)
187{
188 data->cyc2ns_mul = 0;
189 data->cyc2ns_shift = 0;
190 data->cyc2ns_offset = 0;
191 data->__count = 0;
192}
193
194static void cyc2ns_init(int cpu)
195{
196 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
197
198 cyc2ns_data_init(&c2n->data[0]);
199 cyc2ns_data_init(&c2n->data[1]);
200
201 c2n->head = c2n->data;
202 c2n->tail = c2n->data;
203}
204
205static inline unsigned long long cycles_2_ns(unsigned long long cyc)
206{
207 struct cyc2ns_data *data, *tail;
208 unsigned long long ns;
209
210 /*
211 * See cyc2ns_read_*() for details; replicated in order to avoid
212 * an extra few instructions that came with the abstraction.
213 * Notable, it allows us to only do the __count and tail update
214 * dance when its actually needed.
215 */
216
217 preempt_disable_notrace();
218 data = this_cpu_read(cyc2ns.head);
219 tail = this_cpu_read(cyc2ns.tail);
220
221 if (likely(data == tail)) {
222 ns = data->cyc2ns_offset;
223 ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift);
224 } else {
225 data->__count++;
226
227 barrier();
228
229 ns = data->cyc2ns_offset;
230 ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift);
231
232 barrier();
233
234 if (!--data->__count)
235 this_cpu_write(cyc2ns.tail, data);
236 }
237 preempt_enable_notrace();
238
239 return ns;
240}
241
242static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
243{
244 unsigned long long tsc_now, ns_now;
245 struct cyc2ns_data *data;
246 unsigned long flags;
247
248 local_irq_save(flags);
249 sched_clock_idle_sleep_event();
250
251 if (!cpu_khz)
252 goto done;
253
254 data = cyc2ns_write_begin(cpu);
255
256 tsc_now = rdtsc();
257 ns_now = cycles_2_ns(tsc_now);
258
259 /*
260 * Compute a new multiplier as per the above comment and ensure our
261 * time function is continuous; see the comment near struct
262 * cyc2ns_data.
263 */
264 clocks_calc_mult_shift(&data->cyc2ns_mul, &data->cyc2ns_shift, cpu_khz,
265 NSEC_PER_MSEC, 0);
266
267 /*
268 * cyc2ns_shift is exported via arch_perf_update_userpage() where it is
269 * not expected to be greater than 31 due to the original published
270 * conversion algorithm shifting a 32-bit value (now specifies a 64-bit
271 * value) - refer perf_event_mmap_page documentation in perf_event.h.
272 */
273 if (data->cyc2ns_shift == 32) {
274 data->cyc2ns_shift = 31;
275 data->cyc2ns_mul >>= 1;
276 }
277
278 data->cyc2ns_offset = ns_now -
279 mul_u64_u32_shr(tsc_now, data->cyc2ns_mul, data->cyc2ns_shift);
280
281 cyc2ns_write_end(cpu, data);
282
283done:
284 sched_clock_idle_wakeup_event(0);
285 local_irq_restore(flags);
286}
287/*
288 * Scheduler clock - returns current time in nanosec units.
289 */
290u64 native_sched_clock(void)
291{
292 if (static_branch_likely(&__use_tsc)) {
293 u64 tsc_now = rdtsc();
294
295 /* return the value in ns */
296 return cycles_2_ns(tsc_now);
297 }
298
299 /*
300 * Fall back to jiffies if there's no TSC available:
301 * ( But note that we still use it if the TSC is marked
302 * unstable. We do this because unlike Time Of Day,
303 * the scheduler clock tolerates small errors and it's
304 * very important for it to be as fast as the platform
305 * can achieve it. )
306 */
307
308 /* No locking but a rare wrong value is not a big deal: */
309 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
310}
311
312/*
313 * Generate a sched_clock if you already have a TSC value.
314 */
315u64 native_sched_clock_from_tsc(u64 tsc)
316{
317 return cycles_2_ns(tsc);
318}
319
320/* We need to define a real function for sched_clock, to override the
321 weak default version */
322#ifdef CONFIG_PARAVIRT
323unsigned long long sched_clock(void)
324{
325 return paravirt_sched_clock();
326}
327#else
328unsigned long long
329sched_clock(void) __attribute__((alias("native_sched_clock")));
330#endif
331
332int check_tsc_unstable(void)
333{
334 return tsc_unstable;
335}
336EXPORT_SYMBOL_GPL(check_tsc_unstable);
337
338int check_tsc_disabled(void)
339{
340 return tsc_disabled;
341}
342EXPORT_SYMBOL_GPL(check_tsc_disabled);
343
344#ifdef CONFIG_X86_TSC
345int __init notsc_setup(char *str)
346{
347 pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n");
348 tsc_disabled = 1;
349 return 1;
350}
351#else
352/*
353 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
354 * in cpu/common.c
355 */
356int __init notsc_setup(char *str)
357{
358 setup_clear_cpu_cap(X86_FEATURE_TSC);
359 return 1;
360}
361#endif
362
363__setup("notsc", notsc_setup);
364
365static int no_sched_irq_time;
366
367static int __init tsc_setup(char *str)
368{
369 if (!strcmp(str, "reliable"))
370 tsc_clocksource_reliable = 1;
371 if (!strncmp(str, "noirqtime", 9))
372 no_sched_irq_time = 1;
373 return 1;
374}
375
376__setup("tsc=", tsc_setup);
377
378#define MAX_RETRIES 5
379#define SMI_TRESHOLD 50000
380
381/*
382 * Read TSC and the reference counters. Take care of SMI disturbance
383 */
384static u64 tsc_read_refs(u64 *p, int hpet)
385{
386 u64 t1, t2;
387 int i;
388
389 for (i = 0; i < MAX_RETRIES; i++) {
390 t1 = get_cycles();
391 if (hpet)
392 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
393 else
394 *p = acpi_pm_read_early();
395 t2 = get_cycles();
396 if ((t2 - t1) < SMI_TRESHOLD)
397 return t2;
398 }
399 return ULLONG_MAX;
400}
401
402/*
403 * Calculate the TSC frequency from HPET reference
404 */
405static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
406{
407 u64 tmp;
408
409 if (hpet2 < hpet1)
410 hpet2 += 0x100000000ULL;
411 hpet2 -= hpet1;
412 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
413 do_div(tmp, 1000000);
414 do_div(deltatsc, tmp);
415
416 return (unsigned long) deltatsc;
417}
418
419/*
420 * Calculate the TSC frequency from PMTimer reference
421 */
422static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
423{
424 u64 tmp;
425
426 if (!pm1 && !pm2)
427 return ULONG_MAX;
428
429 if (pm2 < pm1)
430 pm2 += (u64)ACPI_PM_OVRRUN;
431 pm2 -= pm1;
432 tmp = pm2 * 1000000000LL;
433 do_div(tmp, PMTMR_TICKS_PER_SEC);
434 do_div(deltatsc, tmp);
435
436 return (unsigned long) deltatsc;
437}
438
439#define CAL_MS 10
440#define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
441#define CAL_PIT_LOOPS 1000
442
443#define CAL2_MS 50
444#define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
445#define CAL2_PIT_LOOPS 5000
446
447
448/*
449 * Try to calibrate the TSC against the Programmable
450 * Interrupt Timer and return the frequency of the TSC
451 * in kHz.
452 *
453 * Return ULONG_MAX on failure to calibrate.
454 */
455static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
456{
457 u64 tsc, t1, t2, delta;
458 unsigned long tscmin, tscmax;
459 int pitcnt;
460
461 /* Set the Gate high, disable speaker */
462 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
463
464 /*
465 * Setup CTC channel 2* for mode 0, (interrupt on terminal
466 * count mode), binary count. Set the latch register to 50ms
467 * (LSB then MSB) to begin countdown.
468 */
469 outb(0xb0, 0x43);
470 outb(latch & 0xff, 0x42);
471 outb(latch >> 8, 0x42);
472
473 tsc = t1 = t2 = get_cycles();
474
475 pitcnt = 0;
476 tscmax = 0;
477 tscmin = ULONG_MAX;
478 while ((inb(0x61) & 0x20) == 0) {
479 t2 = get_cycles();
480 delta = t2 - tsc;
481 tsc = t2;
482 if ((unsigned long) delta < tscmin)
483 tscmin = (unsigned int) delta;
484 if ((unsigned long) delta > tscmax)
485 tscmax = (unsigned int) delta;
486 pitcnt++;
487 }
488
489 /*
490 * Sanity checks:
491 *
492 * If we were not able to read the PIT more than loopmin
493 * times, then we have been hit by a massive SMI
494 *
495 * If the maximum is 10 times larger than the minimum,
496 * then we got hit by an SMI as well.
497 */
498 if (pitcnt < loopmin || tscmax > 10 * tscmin)
499 return ULONG_MAX;
500
501 /* Calculate the PIT value */
502 delta = t2 - t1;
503 do_div(delta, ms);
504 return delta;
505}
506
507/*
508 * This reads the current MSB of the PIT counter, and
509 * checks if we are running on sufficiently fast and
510 * non-virtualized hardware.
511 *
512 * Our expectations are:
513 *
514 * - the PIT is running at roughly 1.19MHz
515 *
516 * - each IO is going to take about 1us on real hardware,
517 * but we allow it to be much faster (by a factor of 10) or
518 * _slightly_ slower (ie we allow up to a 2us read+counter
519 * update - anything else implies a unacceptably slow CPU
520 * or PIT for the fast calibration to work.
521 *
522 * - with 256 PIT ticks to read the value, we have 214us to
523 * see the same MSB (and overhead like doing a single TSC
524 * read per MSB value etc).
525 *
526 * - We're doing 2 reads per loop (LSB, MSB), and we expect
527 * them each to take about a microsecond on real hardware.
528 * So we expect a count value of around 100. But we'll be
529 * generous, and accept anything over 50.
530 *
531 * - if the PIT is stuck, and we see *many* more reads, we
532 * return early (and the next caller of pit_expect_msb()
533 * then consider it a failure when they don't see the
534 * next expected value).
535 *
536 * These expectations mean that we know that we have seen the
537 * transition from one expected value to another with a fairly
538 * high accuracy, and we didn't miss any events. We can thus
539 * use the TSC value at the transitions to calculate a pretty
540 * good value for the TSC frequencty.
541 */
542static inline int pit_verify_msb(unsigned char val)
543{
544 /* Ignore LSB */
545 inb(0x42);
546 return inb(0x42) == val;
547}
548
549static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
550{
551 int count;
552 u64 tsc = 0, prev_tsc = 0;
553
554 for (count = 0; count < 50000; count++) {
555 if (!pit_verify_msb(val))
556 break;
557 prev_tsc = tsc;
558 tsc = get_cycles();
559 }
560 *deltap = get_cycles() - prev_tsc;
561 *tscp = tsc;
562
563 /*
564 * We require _some_ success, but the quality control
565 * will be based on the error terms on the TSC values.
566 */
567 return count > 5;
568}
569
570/*
571 * How many MSB values do we want to see? We aim for
572 * a maximum error rate of 500ppm (in practice the
573 * real error is much smaller), but refuse to spend
574 * more than 50ms on it.
575 */
576#define MAX_QUICK_PIT_MS 50
577#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
578
579static unsigned long quick_pit_calibrate(void)
580{
581 int i;
582 u64 tsc, delta;
583 unsigned long d1, d2;
584
585 /* Set the Gate high, disable speaker */
586 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
587
588 /*
589 * Counter 2, mode 0 (one-shot), binary count
590 *
591 * NOTE! Mode 2 decrements by two (and then the
592 * output is flipped each time, giving the same
593 * final output frequency as a decrement-by-one),
594 * so mode 0 is much better when looking at the
595 * individual counts.
596 */
597 outb(0xb0, 0x43);
598
599 /* Start at 0xffff */
600 outb(0xff, 0x42);
601 outb(0xff, 0x42);
602
603 /*
604 * The PIT starts counting at the next edge, so we
605 * need to delay for a microsecond. The easiest way
606 * to do that is to just read back the 16-bit counter
607 * once from the PIT.
608 */
609 pit_verify_msb(0);
610
611 if (pit_expect_msb(0xff, &tsc, &d1)) {
612 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
613 if (!pit_expect_msb(0xff-i, &delta, &d2))
614 break;
615
616 delta -= tsc;
617
618 /*
619 * Extrapolate the error and fail fast if the error will
620 * never be below 500 ppm.
621 */
622 if (i == 1 &&
623 d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11)
624 return 0;
625
626 /*
627 * Iterate until the error is less than 500 ppm
628 */
629 if (d1+d2 >= delta >> 11)
630 continue;
631
632 /*
633 * Check the PIT one more time to verify that
634 * all TSC reads were stable wrt the PIT.
635 *
636 * This also guarantees serialization of the
637 * last cycle read ('d2') in pit_expect_msb.
638 */
639 if (!pit_verify_msb(0xfe - i))
640 break;
641 goto success;
642 }
643 }
644 pr_info("Fast TSC calibration failed\n");
645 return 0;
646
647success:
648 /*
649 * Ok, if we get here, then we've seen the
650 * MSB of the PIT decrement 'i' times, and the
651 * error has shrunk to less than 500 ppm.
652 *
653 * As a result, we can depend on there not being
654 * any odd delays anywhere, and the TSC reads are
655 * reliable (within the error).
656 *
657 * kHz = ticks / time-in-seconds / 1000;
658 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
659 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
660 */
661 delta *= PIT_TICK_RATE;
662 do_div(delta, i*256*1000);
663 pr_info("Fast TSC calibration using PIT\n");
664 return delta;
665}
666
667/**
668 * native_calibrate_tsc - calibrate the tsc on boot
669 */
670unsigned long native_calibrate_tsc(void)
671{
672 u64 tsc1, tsc2, delta, ref1, ref2;
673 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
674 unsigned long flags, latch, ms, fast_calibrate;
675 int hpet = is_hpet_enabled(), i, loopmin;
676
677 /* Calibrate TSC using MSR for Intel Atom SoCs */
678 local_irq_save(flags);
679 fast_calibrate = try_msr_calibrate_tsc();
680 local_irq_restore(flags);
681 if (fast_calibrate)
682 return fast_calibrate;
683
684 local_irq_save(flags);
685 fast_calibrate = quick_pit_calibrate();
686 local_irq_restore(flags);
687 if (fast_calibrate)
688 return fast_calibrate;
689
690 /*
691 * Run 5 calibration loops to get the lowest frequency value
692 * (the best estimate). We use two different calibration modes
693 * here:
694 *
695 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
696 * load a timeout of 50ms. We read the time right after we
697 * started the timer and wait until the PIT count down reaches
698 * zero. In each wait loop iteration we read the TSC and check
699 * the delta to the previous read. We keep track of the min
700 * and max values of that delta. The delta is mostly defined
701 * by the IO time of the PIT access, so we can detect when a
702 * SMI/SMM disturbance happened between the two reads. If the
703 * maximum time is significantly larger than the minimum time,
704 * then we discard the result and have another try.
705 *
706 * 2) Reference counter. If available we use the HPET or the
707 * PMTIMER as a reference to check the sanity of that value.
708 * We use separate TSC readouts and check inside of the
709 * reference read for a SMI/SMM disturbance. We dicard
710 * disturbed values here as well. We do that around the PIT
711 * calibration delay loop as we have to wait for a certain
712 * amount of time anyway.
713 */
714
715 /* Preset PIT loop values */
716 latch = CAL_LATCH;
717 ms = CAL_MS;
718 loopmin = CAL_PIT_LOOPS;
719
720 for (i = 0; i < 3; i++) {
721 unsigned long tsc_pit_khz;
722
723 /*
724 * Read the start value and the reference count of
725 * hpet/pmtimer when available. Then do the PIT
726 * calibration, which will take at least 50ms, and
727 * read the end value.
728 */
729 local_irq_save(flags);
730 tsc1 = tsc_read_refs(&ref1, hpet);
731 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
732 tsc2 = tsc_read_refs(&ref2, hpet);
733 local_irq_restore(flags);
734
735 /* Pick the lowest PIT TSC calibration so far */
736 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
737
738 /* hpet or pmtimer available ? */
739 if (ref1 == ref2)
740 continue;
741
742 /* Check, whether the sampling was disturbed by an SMI */
743 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
744 continue;
745
746 tsc2 = (tsc2 - tsc1) * 1000000LL;
747 if (hpet)
748 tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
749 else
750 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
751
752 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
753
754 /* Check the reference deviation */
755 delta = ((u64) tsc_pit_min) * 100;
756 do_div(delta, tsc_ref_min);
757
758 /*
759 * If both calibration results are inside a 10% window
760 * then we can be sure, that the calibration
761 * succeeded. We break out of the loop right away. We
762 * use the reference value, as it is more precise.
763 */
764 if (delta >= 90 && delta <= 110) {
765 pr_info("PIT calibration matches %s. %d loops\n",
766 hpet ? "HPET" : "PMTIMER", i + 1);
767 return tsc_ref_min;
768 }
769
770 /*
771 * Check whether PIT failed more than once. This
772 * happens in virtualized environments. We need to
773 * give the virtual PC a slightly longer timeframe for
774 * the HPET/PMTIMER to make the result precise.
775 */
776 if (i == 1 && tsc_pit_min == ULONG_MAX) {
777 latch = CAL2_LATCH;
778 ms = CAL2_MS;
779 loopmin = CAL2_PIT_LOOPS;
780 }
781 }
782
783 /*
784 * Now check the results.
785 */
786 if (tsc_pit_min == ULONG_MAX) {
787 /* PIT gave no useful value */
788 pr_warn("Unable to calibrate against PIT\n");
789
790 /* We don't have an alternative source, disable TSC */
791 if (!hpet && !ref1 && !ref2) {
792 pr_notice("No reference (HPET/PMTIMER) available\n");
793 return 0;
794 }
795
796 /* The alternative source failed as well, disable TSC */
797 if (tsc_ref_min == ULONG_MAX) {
798 pr_warn("HPET/PMTIMER calibration failed\n");
799 return 0;
800 }
801
802 /* Use the alternative source */
803 pr_info("using %s reference calibration\n",
804 hpet ? "HPET" : "PMTIMER");
805
806 return tsc_ref_min;
807 }
808
809 /* We don't have an alternative source, use the PIT calibration value */
810 if (!hpet && !ref1 && !ref2) {
811 pr_info("Using PIT calibration value\n");
812 return tsc_pit_min;
813 }
814
815 /* The alternative source failed, use the PIT calibration value */
816 if (tsc_ref_min == ULONG_MAX) {
817 pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n");
818 return tsc_pit_min;
819 }
820
821 /*
822 * The calibration values differ too much. In doubt, we use
823 * the PIT value as we know that there are PMTIMERs around
824 * running at double speed. At least we let the user know:
825 */
826 pr_warn("PIT calibration deviates from %s: %lu %lu\n",
827 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
828 pr_info("Using PIT calibration value\n");
829 return tsc_pit_min;
830}
831
832int recalibrate_cpu_khz(void)
833{
834#ifndef CONFIG_SMP
835 unsigned long cpu_khz_old = cpu_khz;
836
837 if (cpu_has_tsc) {
838 tsc_khz = x86_platform.calibrate_tsc();
839 cpu_khz = tsc_khz;
840 cpu_data(0).loops_per_jiffy =
841 cpufreq_scale(cpu_data(0).loops_per_jiffy,
842 cpu_khz_old, cpu_khz);
843 return 0;
844 } else
845 return -ENODEV;
846#else
847 return -ENODEV;
848#endif
849}
850
851EXPORT_SYMBOL(recalibrate_cpu_khz);
852
853
854static unsigned long long cyc2ns_suspend;
855
856void tsc_save_sched_clock_state(void)
857{
858 if (!sched_clock_stable())
859 return;
860
861 cyc2ns_suspend = sched_clock();
862}
863
864/*
865 * Even on processors with invariant TSC, TSC gets reset in some the
866 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
867 * arbitrary value (still sync'd across cpu's) during resume from such sleep
868 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
869 * that sched_clock() continues from the point where it was left off during
870 * suspend.
871 */
872void tsc_restore_sched_clock_state(void)
873{
874 unsigned long long offset;
875 unsigned long flags;
876 int cpu;
877
878 if (!sched_clock_stable())
879 return;
880
881 local_irq_save(flags);
882
883 /*
884 * We're coming out of suspend, there's no concurrency yet; don't
885 * bother being nice about the RCU stuff, just write to both
886 * data fields.
887 */
888
889 this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0);
890 this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0);
891
892 offset = cyc2ns_suspend - sched_clock();
893
894 for_each_possible_cpu(cpu) {
895 per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset;
896 per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset;
897 }
898
899 local_irq_restore(flags);
900}
901
902#ifdef CONFIG_CPU_FREQ
903
904/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
905 * changes.
906 *
907 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
908 * not that important because current Opteron setups do not support
909 * scaling on SMP anyroads.
910 *
911 * Should fix up last_tsc too. Currently gettimeofday in the
912 * first tick after the change will be slightly wrong.
913 */
914
915static unsigned int ref_freq;
916static unsigned long loops_per_jiffy_ref;
917static unsigned long tsc_khz_ref;
918
919static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
920 void *data)
921{
922 struct cpufreq_freqs *freq = data;
923 unsigned long *lpj;
924
925 if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
926 return 0;
927
928 lpj = &boot_cpu_data.loops_per_jiffy;
929#ifdef CONFIG_SMP
930 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
931 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
932#endif
933
934 if (!ref_freq) {
935 ref_freq = freq->old;
936 loops_per_jiffy_ref = *lpj;
937 tsc_khz_ref = tsc_khz;
938 }
939 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
940 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
941 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
942
943 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
944 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
945 mark_tsc_unstable("cpufreq changes");
946
947 set_cyc2ns_scale(tsc_khz, freq->cpu);
948 }
949
950 return 0;
951}
952
953static struct notifier_block time_cpufreq_notifier_block = {
954 .notifier_call = time_cpufreq_notifier
955};
956
957static int __init cpufreq_tsc(void)
958{
959 if (!cpu_has_tsc)
960 return 0;
961 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
962 return 0;
963 cpufreq_register_notifier(&time_cpufreq_notifier_block,
964 CPUFREQ_TRANSITION_NOTIFIER);
965 return 0;
966}
967
968core_initcall(cpufreq_tsc);
969
970#endif /* CONFIG_CPU_FREQ */
971
972#define ART_CPUID_LEAF (0x15)
973#define ART_MIN_DENOMINATOR (1)
974
975
976/*
977 * If ART is present detect the numerator:denominator to convert to TSC
978 */
979static void detect_art(void)
980{
981 unsigned int unused[2];
982
983 if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF)
984 return;
985
986 cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator,
987 &art_to_tsc_numerator, unused, unused+1);
988
989 /* Don't enable ART in a VM, non-stop TSC required */
990 if (boot_cpu_has(X86_FEATURE_HYPERVISOR) ||
991 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) ||
992 art_to_tsc_denominator < ART_MIN_DENOMINATOR)
993 return;
994
995 if (rdmsrl_safe(MSR_IA32_TSC_ADJUST, &art_to_tsc_offset))
996 return;
997
998 /* Make this sticky over multiple CPU init calls */
999 setup_force_cpu_cap(X86_FEATURE_ART);
1000}
1001
1002
1003/* clocksource code */
1004
1005static struct clocksource clocksource_tsc;
1006
1007/*
1008 * We used to compare the TSC to the cycle_last value in the clocksource
1009 * structure to avoid a nasty time-warp. This can be observed in a
1010 * very small window right after one CPU updated cycle_last under
1011 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
1012 * is smaller than the cycle_last reference value due to a TSC which
1013 * is slighty behind. This delta is nowhere else observable, but in
1014 * that case it results in a forward time jump in the range of hours
1015 * due to the unsigned delta calculation of the time keeping core
1016 * code, which is necessary to support wrapping clocksources like pm
1017 * timer.
1018 *
1019 * This sanity check is now done in the core timekeeping code.
1020 * checking the result of read_tsc() - cycle_last for being negative.
1021 * That works because CLOCKSOURCE_MASK(64) does not mask out any bit.
1022 */
1023static cycle_t read_tsc(struct clocksource *cs)
1024{
1025 return (cycle_t)rdtsc_ordered();
1026}
1027
1028/*
1029 * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc()
1030 */
1031static struct clocksource clocksource_tsc = {
1032 .name = "tsc",
1033 .rating = 300,
1034 .read = read_tsc,
1035 .mask = CLOCKSOURCE_MASK(64),
1036 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
1037 CLOCK_SOURCE_MUST_VERIFY,
1038 .archdata = { .vclock_mode = VCLOCK_TSC },
1039};
1040
1041void mark_tsc_unstable(char *reason)
1042{
1043 if (!tsc_unstable) {
1044 tsc_unstable = 1;
1045 clear_sched_clock_stable();
1046 disable_sched_clock_irqtime();
1047 pr_info("Marking TSC unstable due to %s\n", reason);
1048 /* Change only the rating, when not registered */
1049 if (clocksource_tsc.mult)
1050 clocksource_mark_unstable(&clocksource_tsc);
1051 else {
1052 clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
1053 clocksource_tsc.rating = 0;
1054 }
1055 }
1056}
1057
1058EXPORT_SYMBOL_GPL(mark_tsc_unstable);
1059
1060static void __init check_system_tsc_reliable(void)
1061{
1062#if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC)
1063 if (is_geode_lx()) {
1064 /* RTSC counts during suspend */
1065#define RTSC_SUSP 0x100
1066 unsigned long res_low, res_high;
1067
1068 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
1069 /* Geode_LX - the OLPC CPU has a very reliable TSC */
1070 if (res_low & RTSC_SUSP)
1071 tsc_clocksource_reliable = 1;
1072 }
1073#endif
1074 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
1075 tsc_clocksource_reliable = 1;
1076}
1077
1078/*
1079 * Make an educated guess if the TSC is trustworthy and synchronized
1080 * over all CPUs.
1081 */
1082int unsynchronized_tsc(void)
1083{
1084 if (!cpu_has_tsc || tsc_unstable)
1085 return 1;
1086
1087#ifdef CONFIG_SMP
1088 if (apic_is_clustered_box())
1089 return 1;
1090#endif
1091
1092 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1093 return 0;
1094
1095 if (tsc_clocksource_reliable)
1096 return 0;
1097 /*
1098 * Intel systems are normally all synchronized.
1099 * Exceptions must mark TSC as unstable:
1100 */
1101 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1102 /* assume multi socket systems are not synchronized: */
1103 if (num_possible_cpus() > 1)
1104 return 1;
1105 }
1106
1107 return 0;
1108}
1109
1110/*
1111 * Convert ART to TSC given numerator/denominator found in detect_art()
1112 */
1113struct system_counterval_t convert_art_to_tsc(cycle_t art)
1114{
1115 u64 tmp, res, rem;
1116
1117 rem = do_div(art, art_to_tsc_denominator);
1118
1119 res = art * art_to_tsc_numerator;
1120 tmp = rem * art_to_tsc_numerator;
1121
1122 do_div(tmp, art_to_tsc_denominator);
1123 res += tmp + art_to_tsc_offset;
1124
1125 return (struct system_counterval_t) {.cs = art_related_clocksource,
1126 .cycles = res};
1127}
1128EXPORT_SYMBOL(convert_art_to_tsc);
1129
1130static void tsc_refine_calibration_work(struct work_struct *work);
1131static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
1132/**
1133 * tsc_refine_calibration_work - Further refine tsc freq calibration
1134 * @work - ignored.
1135 *
1136 * This functions uses delayed work over a period of a
1137 * second to further refine the TSC freq value. Since this is
1138 * timer based, instead of loop based, we don't block the boot
1139 * process while this longer calibration is done.
1140 *
1141 * If there are any calibration anomalies (too many SMIs, etc),
1142 * or the refined calibration is off by 1% of the fast early
1143 * calibration, we throw out the new calibration and use the
1144 * early calibration.
1145 */
1146static void tsc_refine_calibration_work(struct work_struct *work)
1147{
1148 static u64 tsc_start = -1, ref_start;
1149 static int hpet;
1150 u64 tsc_stop, ref_stop, delta;
1151 unsigned long freq;
1152
1153 /* Don't bother refining TSC on unstable systems */
1154 if (check_tsc_unstable())
1155 goto out;
1156
1157 /*
1158 * Since the work is started early in boot, we may be
1159 * delayed the first time we expire. So set the workqueue
1160 * again once we know timers are working.
1161 */
1162 if (tsc_start == -1) {
1163 /*
1164 * Only set hpet once, to avoid mixing hardware
1165 * if the hpet becomes enabled later.
1166 */
1167 hpet = is_hpet_enabled();
1168 schedule_delayed_work(&tsc_irqwork, HZ);
1169 tsc_start = tsc_read_refs(&ref_start, hpet);
1170 return;
1171 }
1172
1173 tsc_stop = tsc_read_refs(&ref_stop, hpet);
1174
1175 /* hpet or pmtimer available ? */
1176 if (ref_start == ref_stop)
1177 goto out;
1178
1179 /* Check, whether the sampling was disturbed by an SMI */
1180 if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
1181 goto out;
1182
1183 delta = tsc_stop - tsc_start;
1184 delta *= 1000000LL;
1185 if (hpet)
1186 freq = calc_hpet_ref(delta, ref_start, ref_stop);
1187 else
1188 freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
1189
1190 /* Make sure we're within 1% */
1191 if (abs(tsc_khz - freq) > tsc_khz/100)
1192 goto out;
1193
1194 tsc_khz = freq;
1195 pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",
1196 (unsigned long)tsc_khz / 1000,
1197 (unsigned long)tsc_khz % 1000);
1198
1199out:
1200 if (boot_cpu_has(X86_FEATURE_ART))
1201 art_related_clocksource = &clocksource_tsc;
1202 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1203}
1204
1205
1206static int __init init_tsc_clocksource(void)
1207{
1208 if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz)
1209 return 0;
1210
1211 if (tsc_clocksource_reliable)
1212 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
1213 /* lower the rating if we already know its unstable: */
1214 if (check_tsc_unstable()) {
1215 clocksource_tsc.rating = 0;
1216 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
1217 }
1218
1219 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3))
1220 clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1221
1222 /*
1223 * Trust the results of the earlier calibration on systems
1224 * exporting a reliable TSC.
1225 */
1226 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) {
1227 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1228 return 0;
1229 }
1230
1231 schedule_delayed_work(&tsc_irqwork, 0);
1232 return 0;
1233}
1234/*
1235 * We use device_initcall here, to ensure we run after the hpet
1236 * is fully initialized, which may occur at fs_initcall time.
1237 */
1238device_initcall(init_tsc_clocksource);
1239
1240void __init tsc_init(void)
1241{
1242 u64 lpj;
1243 int cpu;
1244
1245 if (!cpu_has_tsc) {
1246 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1247 return;
1248 }
1249
1250 tsc_khz = x86_platform.calibrate_tsc();
1251 cpu_khz = tsc_khz;
1252
1253 if (!tsc_khz) {
1254 mark_tsc_unstable("could not calculate TSC khz");
1255 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1256 return;
1257 }
1258
1259 pr_info("Detected %lu.%03lu MHz processor\n",
1260 (unsigned long)cpu_khz / 1000,
1261 (unsigned long)cpu_khz % 1000);
1262
1263 /*
1264 * Secondary CPUs do not run through tsc_init(), so set up
1265 * all the scale factors for all CPUs, assuming the same
1266 * speed as the bootup CPU. (cpufreq notifiers will fix this
1267 * up if their speed diverges)
1268 */
1269 for_each_possible_cpu(cpu) {
1270 cyc2ns_init(cpu);
1271 set_cyc2ns_scale(cpu_khz, cpu);
1272 }
1273
1274 if (tsc_disabled > 0)
1275 return;
1276
1277 /* now allow native_sched_clock() to use rdtsc */
1278
1279 tsc_disabled = 0;
1280 static_branch_enable(&__use_tsc);
1281
1282 if (!no_sched_irq_time)
1283 enable_sched_clock_irqtime();
1284
1285 lpj = ((u64)tsc_khz * 1000);
1286 do_div(lpj, HZ);
1287 lpj_fine = lpj;
1288
1289 use_tsc_delay();
1290
1291 if (unsynchronized_tsc())
1292 mark_tsc_unstable("TSCs unsynchronized");
1293
1294 check_system_tsc_reliable();
1295
1296 detect_art();
1297}
1298
1299#ifdef CONFIG_SMP
1300/*
1301 * If we have a constant TSC and are using the TSC for the delay loop,
1302 * we can skip clock calibration if another cpu in the same socket has already
1303 * been calibrated. This assumes that CONSTANT_TSC applies to all
1304 * cpus in the socket - this should be a safe assumption.
1305 */
1306unsigned long calibrate_delay_is_known(void)
1307{
1308 int sibling, cpu = smp_processor_id();
1309 struct cpumask *mask = topology_core_cpumask(cpu);
1310
1311 if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC))
1312 return 0;
1313
1314 if (!mask)
1315 return 0;
1316
1317 sibling = cpumask_any_but(mask, cpu);
1318 if (sibling < nr_cpu_ids)
1319 return cpu_data(sibling).loops_per_jiffy;
1320 return 0;
1321}
1322#endif