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1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27#include <linux/pci.h>
28
29#include <drm/drm_device.h>
30#include <drm/drm_edid.h>
31#include <drm/radeon_drm.h>
32
33#include "radeon.h"
34
35#include "atom.h"
36#include "atom-bits.h"
37#include "radeon_asic.h"
38#include "radeon_atombios.h"
39#include "radeon_legacy_encoders.h"
40
41union atom_supported_devices {
42 struct _ATOM_SUPPORTED_DEVICES_INFO info;
43 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
44 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
45};
46
47static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
48 ATOM_GPIO_I2C_ASSIGMENT *gpio,
49 u8 index)
50{
51 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
52 if ((rdev->family == CHIP_R420) ||
53 (rdev->family == CHIP_R423) ||
54 (rdev->family == CHIP_RV410)) {
55 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
56 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
57 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
58 gpio->ucClkMaskShift = 0x19;
59 gpio->ucDataMaskShift = 0x18;
60 }
61 }
62
63 /* some evergreen boards have bad data for this entry */
64 if (ASIC_IS_DCE4(rdev)) {
65 if ((index == 7) &&
66 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
67 (gpio->sucI2cId.ucAccess == 0)) {
68 gpio->sucI2cId.ucAccess = 0x97;
69 gpio->ucDataMaskShift = 8;
70 gpio->ucDataEnShift = 8;
71 gpio->ucDataY_Shift = 8;
72 gpio->ucDataA_Shift = 8;
73 }
74 }
75
76 /* some DCE3 boards have bad data for this entry */
77 if (ASIC_IS_DCE3(rdev)) {
78 if ((index == 4) &&
79 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
80 (gpio->sucI2cId.ucAccess == 0x94))
81 gpio->sucI2cId.ucAccess = 0x14;
82 }
83}
84
85static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
86{
87 struct radeon_i2c_bus_rec i2c;
88
89 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
90
91 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
92 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
93 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
94 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
95 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
96 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
97 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
98 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
99 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
100 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
101 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
102 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
103 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
104 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
105 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
106 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
107
108 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
109 i2c.hw_capable = true;
110 else
111 i2c.hw_capable = false;
112
113 if (gpio->sucI2cId.ucAccess == 0xa0)
114 i2c.mm_i2c = true;
115 else
116 i2c.mm_i2c = false;
117
118 i2c.i2c_id = gpio->sucI2cId.ucAccess;
119
120 if (i2c.mask_clk_reg)
121 i2c.valid = true;
122 else
123 i2c.valid = false;
124
125 return i2c;
126}
127
128static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
129 uint8_t id)
130{
131 struct atom_context *ctx = rdev->mode_info.atom_context;
132 ATOM_GPIO_I2C_ASSIGMENT *gpio;
133 struct radeon_i2c_bus_rec i2c;
134 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
135 struct _ATOM_GPIO_I2C_INFO *i2c_info;
136 uint16_t data_offset, size;
137 int i, num_indices;
138
139 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
140 i2c.valid = false;
141
142 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
143 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
144
145 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
146 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
147
148 gpio = &i2c_info->asGPIO_Info[0];
149 for (i = 0; i < num_indices; i++) {
150
151 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
152
153 if (gpio->sucI2cId.ucAccess == id) {
154 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
155 break;
156 }
157 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
158 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
159 }
160 }
161
162 return i2c;
163}
164
165void radeon_atombios_i2c_init(struct radeon_device *rdev)
166{
167 struct atom_context *ctx = rdev->mode_info.atom_context;
168 ATOM_GPIO_I2C_ASSIGMENT *gpio;
169 struct radeon_i2c_bus_rec i2c;
170 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
171 struct _ATOM_GPIO_I2C_INFO *i2c_info;
172 uint16_t data_offset, size;
173 int i, num_indices;
174 char stmp[32];
175
176 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
177 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
178
179 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
180 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
181
182 gpio = &i2c_info->asGPIO_Info[0];
183 for (i = 0; i < num_indices; i++) {
184 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
185
186 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
187
188 if (i2c.valid) {
189 sprintf(stmp, "0x%x", i2c.i2c_id);
190 rdev->i2c_bus[i] = radeon_i2c_create(rdev_to_drm(rdev), &i2c, stmp);
191 }
192 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
193 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
194 }
195 }
196}
197
198struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
199 u8 id)
200{
201 struct atom_context *ctx = rdev->mode_info.atom_context;
202 struct radeon_gpio_rec gpio;
203 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
204 struct _ATOM_GPIO_PIN_LUT *gpio_info;
205 ATOM_GPIO_PIN_ASSIGNMENT *pin;
206 u16 data_offset, size;
207 int i, num_indices;
208
209 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
210 gpio.valid = false;
211
212 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
213 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
214
215 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
216 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
217
218 pin = gpio_info->asGPIO_Pin;
219 for (i = 0; i < num_indices; i++) {
220 if (id == pin->ucGPIO_ID) {
221 gpio.id = pin->ucGPIO_ID;
222 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
223 gpio.shift = pin->ucGpioPinBitShift;
224 gpio.mask = (1 << pin->ucGpioPinBitShift);
225 gpio.valid = true;
226 break;
227 }
228 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
229 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
230 }
231 }
232
233 return gpio;
234}
235
236static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
237 struct radeon_gpio_rec *gpio)
238{
239 struct radeon_hpd hpd;
240 u32 reg;
241
242 memset(&hpd, 0, sizeof(struct radeon_hpd));
243
244 if (ASIC_IS_DCE6(rdev))
245 reg = SI_DC_GPIO_HPD_A;
246 else if (ASIC_IS_DCE4(rdev))
247 reg = EVERGREEN_DC_GPIO_HPD_A;
248 else
249 reg = AVIVO_DC_GPIO_HPD_A;
250
251 hpd.gpio = *gpio;
252 if (gpio->reg == reg) {
253 switch(gpio->mask) {
254 case (1 << 0):
255 hpd.hpd = RADEON_HPD_1;
256 break;
257 case (1 << 8):
258 hpd.hpd = RADEON_HPD_2;
259 break;
260 case (1 << 16):
261 hpd.hpd = RADEON_HPD_3;
262 break;
263 case (1 << 24):
264 hpd.hpd = RADEON_HPD_4;
265 break;
266 case (1 << 26):
267 hpd.hpd = RADEON_HPD_5;
268 break;
269 case (1 << 28):
270 hpd.hpd = RADEON_HPD_6;
271 break;
272 default:
273 hpd.hpd = RADEON_HPD_NONE;
274 break;
275 }
276 } else
277 hpd.hpd = RADEON_HPD_NONE;
278 return hpd;
279}
280
281static bool radeon_atom_apply_quirks(struct drm_device *dev,
282 uint32_t supported_device,
283 int *connector_type,
284 struct radeon_i2c_bus_rec *i2c_bus,
285 uint16_t *line_mux,
286 struct radeon_hpd *hpd)
287{
288 struct pci_dev *pdev = to_pci_dev(dev->dev);
289
290 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
291 if ((pdev->device == 0x791e) &&
292 (pdev->subsystem_vendor == 0x1043) &&
293 (pdev->subsystem_device == 0x826d)) {
294 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
295 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
296 *connector_type = DRM_MODE_CONNECTOR_DVID;
297 }
298
299 /* Asrock RS600 board lists the DVI port as HDMI */
300 if ((pdev->device == 0x7941) &&
301 (pdev->subsystem_vendor == 0x1849) &&
302 (pdev->subsystem_device == 0x7941)) {
303 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
304 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
305 *connector_type = DRM_MODE_CONNECTOR_DVID;
306 }
307
308 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
309 if ((pdev->device == 0x796e) &&
310 (pdev->subsystem_vendor == 0x1462) &&
311 (pdev->subsystem_device == 0x7302)) {
312 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
313 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
314 return false;
315 }
316
317 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
318 if ((pdev->device == 0x7941) &&
319 (pdev->subsystem_vendor == 0x147b) &&
320 (pdev->subsystem_device == 0x2412)) {
321 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
322 return false;
323 }
324
325 /* Falcon NW laptop lists vga ddc line for LVDS */
326 if ((pdev->device == 0x5653) &&
327 (pdev->subsystem_vendor == 0x1462) &&
328 (pdev->subsystem_device == 0x0291)) {
329 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
330 i2c_bus->valid = false;
331 *line_mux = 53;
332 }
333 }
334
335 /* HIS X1300 is DVI+VGA, not DVI+DVI */
336 if ((pdev->device == 0x7146) &&
337 (pdev->subsystem_vendor == 0x17af) &&
338 (pdev->subsystem_device == 0x2058)) {
339 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
340 return false;
341 }
342
343 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
344 if ((pdev->device == 0x7142) &&
345 (pdev->subsystem_vendor == 0x1458) &&
346 (pdev->subsystem_device == 0x2134)) {
347 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
348 return false;
349 }
350
351
352 /* Funky macbooks */
353 if ((pdev->device == 0x71C5) &&
354 (pdev->subsystem_vendor == 0x106b) &&
355 (pdev->subsystem_device == 0x0080)) {
356 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
357 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
358 return false;
359 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
360 *line_mux = 0x90;
361 }
362
363 /* mac rv630, rv730, others */
364 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
365 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
366 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
367 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
368 }
369
370 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
371 if ((pdev->device == 0x9598) &&
372 (pdev->subsystem_vendor == 0x1043) &&
373 (pdev->subsystem_device == 0x01da)) {
374 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
375 *connector_type = DRM_MODE_CONNECTOR_DVII;
376 }
377 }
378
379 /* ASUS HD 3600 board lists the DVI port as HDMI */
380 if ((pdev->device == 0x9598) &&
381 (pdev->subsystem_vendor == 0x1043) &&
382 (pdev->subsystem_device == 0x01e4)) {
383 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
384 *connector_type = DRM_MODE_CONNECTOR_DVII;
385 }
386 }
387
388 /* ASUS HD 3450 board lists the DVI port as HDMI */
389 if ((pdev->device == 0x95C5) &&
390 (pdev->subsystem_vendor == 0x1043) &&
391 (pdev->subsystem_device == 0x01e2)) {
392 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
393 *connector_type = DRM_MODE_CONNECTOR_DVII;
394 }
395 }
396
397 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
398 * HDMI + VGA reporting as HDMI
399 */
400 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
401 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
402 *connector_type = DRM_MODE_CONNECTOR_VGA;
403 *line_mux = 0;
404 }
405 }
406
407 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
408 * on the laptop and a DVI port on the docking station and
409 * both share the same encoder, hpd pin, and ddc line.
410 * So while the bios table is technically correct,
411 * we drop the DVI port here since xrandr has no concept of
412 * encoders and will try and drive both connectors
413 * with different crtcs which isn't possible on the hardware
414 * side and leaves no crtcs for LVDS or VGA.
415 */
416 if (((pdev->device == 0x95c4) || (pdev->device == 0x9591)) &&
417 (pdev->subsystem_vendor == 0x1025) &&
418 (pdev->subsystem_device == 0x013c)) {
419 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
420 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
421 /* actually it's a DVI-D port not DVI-I */
422 *connector_type = DRM_MODE_CONNECTOR_DVID;
423 return false;
424 }
425 }
426
427 /* XFX Pine Group device rv730 reports no VGA DDC lines
428 * even though they are wired up to record 0x93
429 */
430 if ((pdev->device == 0x9498) &&
431 (pdev->subsystem_vendor == 0x1682) &&
432 (pdev->subsystem_device == 0x2452) &&
433 (i2c_bus->valid == false) &&
434 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
435 struct radeon_device *rdev = dev->dev_private;
436 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
437 }
438
439 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
440 if (((pdev->device == 0x9802) ||
441 (pdev->device == 0x9805) ||
442 (pdev->device == 0x9806)) &&
443 (pdev->subsystem_vendor == 0x1734) &&
444 (pdev->subsystem_device == 0x11bd)) {
445 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
446 *connector_type = DRM_MODE_CONNECTOR_DVII;
447 *line_mux = 0x3103;
448 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
449 *connector_type = DRM_MODE_CONNECTOR_DVII;
450 }
451 }
452
453 return true;
454}
455
456static const int supported_devices_connector_convert[] = {
457 DRM_MODE_CONNECTOR_Unknown,
458 DRM_MODE_CONNECTOR_VGA,
459 DRM_MODE_CONNECTOR_DVII,
460 DRM_MODE_CONNECTOR_DVID,
461 DRM_MODE_CONNECTOR_DVIA,
462 DRM_MODE_CONNECTOR_SVIDEO,
463 DRM_MODE_CONNECTOR_Composite,
464 DRM_MODE_CONNECTOR_LVDS,
465 DRM_MODE_CONNECTOR_Unknown,
466 DRM_MODE_CONNECTOR_Unknown,
467 DRM_MODE_CONNECTOR_HDMIA,
468 DRM_MODE_CONNECTOR_HDMIB,
469 DRM_MODE_CONNECTOR_Unknown,
470 DRM_MODE_CONNECTOR_Unknown,
471 DRM_MODE_CONNECTOR_9PinDIN,
472 DRM_MODE_CONNECTOR_DisplayPort
473};
474
475static const uint16_t supported_devices_connector_object_id_convert[] = {
476 CONNECTOR_OBJECT_ID_NONE,
477 CONNECTOR_OBJECT_ID_VGA,
478 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
479 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
480 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
481 CONNECTOR_OBJECT_ID_COMPOSITE,
482 CONNECTOR_OBJECT_ID_SVIDEO,
483 CONNECTOR_OBJECT_ID_LVDS,
484 CONNECTOR_OBJECT_ID_9PIN_DIN,
485 CONNECTOR_OBJECT_ID_9PIN_DIN,
486 CONNECTOR_OBJECT_ID_DISPLAYPORT,
487 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
488 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
489 CONNECTOR_OBJECT_ID_SVIDEO
490};
491
492static const int object_connector_convert[] = {
493 DRM_MODE_CONNECTOR_Unknown,
494 DRM_MODE_CONNECTOR_DVII,
495 DRM_MODE_CONNECTOR_DVII,
496 DRM_MODE_CONNECTOR_DVID,
497 DRM_MODE_CONNECTOR_DVID,
498 DRM_MODE_CONNECTOR_VGA,
499 DRM_MODE_CONNECTOR_Composite,
500 DRM_MODE_CONNECTOR_SVIDEO,
501 DRM_MODE_CONNECTOR_Unknown,
502 DRM_MODE_CONNECTOR_Unknown,
503 DRM_MODE_CONNECTOR_9PinDIN,
504 DRM_MODE_CONNECTOR_Unknown,
505 DRM_MODE_CONNECTOR_HDMIA,
506 DRM_MODE_CONNECTOR_HDMIB,
507 DRM_MODE_CONNECTOR_LVDS,
508 DRM_MODE_CONNECTOR_9PinDIN,
509 DRM_MODE_CONNECTOR_Unknown,
510 DRM_MODE_CONNECTOR_Unknown,
511 DRM_MODE_CONNECTOR_Unknown,
512 DRM_MODE_CONNECTOR_DisplayPort,
513 DRM_MODE_CONNECTOR_eDP,
514 DRM_MODE_CONNECTOR_Unknown
515};
516
517bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
518{
519 struct radeon_device *rdev = dev->dev_private;
520 struct radeon_mode_info *mode_info = &rdev->mode_info;
521 struct atom_context *ctx = mode_info->atom_context;
522 int index = GetIndexIntoMasterTable(DATA, Object_Header);
523 u16 size, data_offset;
524 u8 frev, crev;
525 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
526 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
527 ATOM_OBJECT_TABLE *router_obj;
528 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
529 ATOM_OBJECT_HEADER *obj_header;
530 int i, j, k, path_size, device_support;
531 int connector_type;
532 u16 igp_lane_info, conn_id, connector_object_id;
533 struct radeon_i2c_bus_rec ddc_bus;
534 struct radeon_router router;
535 struct radeon_gpio_rec gpio;
536 struct radeon_hpd hpd;
537
538 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
539 return false;
540
541 if (crev < 2)
542 return false;
543
544 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
545 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
546 (ctx->bios + data_offset +
547 le16_to_cpu(obj_header->usDisplayPathTableOffset));
548 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
549 (ctx->bios + data_offset +
550 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
551 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
552 (ctx->bios + data_offset +
553 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
554 router_obj = (ATOM_OBJECT_TABLE *)
555 (ctx->bios + data_offset +
556 le16_to_cpu(obj_header->usRouterObjectTableOffset));
557 device_support = le16_to_cpu(obj_header->usDeviceSupport);
558
559 path_size = 0;
560 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
561 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
562 ATOM_DISPLAY_OBJECT_PATH *path;
563 addr += path_size;
564 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
565 path_size += le16_to_cpu(path->usSize);
566
567 if (device_support & le16_to_cpu(path->usDeviceTag)) {
568 uint8_t con_obj_id, con_obj_num;
569
570 con_obj_id =
571 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
572 >> OBJECT_ID_SHIFT;
573 con_obj_num =
574 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
575 >> ENUM_ID_SHIFT;
576
577 /* TODO CV support */
578 if (le16_to_cpu(path->usDeviceTag) ==
579 ATOM_DEVICE_CV_SUPPORT)
580 continue;
581
582 /* IGP chips */
583 if ((rdev->flags & RADEON_IS_IGP) &&
584 (con_obj_id ==
585 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
586 uint16_t igp_offset = 0;
587 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
588
589 index =
590 GetIndexIntoMasterTable(DATA,
591 IntegratedSystemInfo);
592
593 if (atom_parse_data_header(ctx, index, &size, &frev,
594 &crev, &igp_offset)) {
595
596 if (crev >= 2) {
597 igp_obj =
598 (ATOM_INTEGRATED_SYSTEM_INFO_V2
599 *) (ctx->bios + igp_offset);
600
601 if (igp_obj) {
602 uint32_t slot_config, ct;
603
604 if (con_obj_num == 1)
605 slot_config =
606 igp_obj->
607 ulDDISlot1Config;
608 else
609 slot_config =
610 igp_obj->
611 ulDDISlot2Config;
612
613 ct = (slot_config >> 16) & 0xff;
614 connector_type =
615 object_connector_convert
616 [ct];
617 connector_object_id = ct;
618 igp_lane_info =
619 slot_config & 0xffff;
620 } else
621 continue;
622 } else
623 continue;
624 } else {
625 igp_lane_info = 0;
626 connector_type =
627 object_connector_convert[con_obj_id];
628 connector_object_id = con_obj_id;
629 }
630 } else {
631 igp_lane_info = 0;
632 connector_type =
633 object_connector_convert[con_obj_id];
634 connector_object_id = con_obj_id;
635 }
636
637 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
638 continue;
639
640 router.ddc_valid = false;
641 router.cd_valid = false;
642 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
643 uint8_t grph_obj_type =
644 (le16_to_cpu(path->usGraphicObjIds[j]) &
645 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
646
647 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
648 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
649 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
650 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
651 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
652 (ctx->bios + data_offset +
653 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
654 ATOM_ENCODER_CAP_RECORD *cap_record;
655 u16 caps = 0;
656
657 while (record->ucRecordSize > 0 &&
658 record->ucRecordType > 0 &&
659 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
660 switch (record->ucRecordType) {
661 case ATOM_ENCODER_CAP_RECORD_TYPE:
662 cap_record =(ATOM_ENCODER_CAP_RECORD *)
663 record;
664 caps = le16_to_cpu(cap_record->usEncoderCap);
665 break;
666 }
667 record = (ATOM_COMMON_RECORD_HEADER *)
668 ((char *)record + record->ucRecordSize);
669 }
670 radeon_add_atom_encoder(dev,
671 encoder_obj,
672 le16_to_cpu
673 (path->
674 usDeviceTag),
675 caps);
676 }
677 }
678 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
679 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
680 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
681 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
682 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
683 (ctx->bios + data_offset +
684 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
685 ATOM_I2C_RECORD *i2c_record;
686 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
687 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
688 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
689 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
690 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
691 (ctx->bios + data_offset +
692 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
693 u8 *num_dst_objs = (u8 *)
694 ((u8 *)router_src_dst_table + 1 +
695 (router_src_dst_table->ucNumberOfSrc * 2));
696 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
697 int enum_id;
698
699 router.router_id = router_obj_id;
700 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
701 if (le16_to_cpu(path->usConnObjectId) ==
702 le16_to_cpu(dst_objs[enum_id]))
703 break;
704 }
705
706 while (record->ucRecordSize > 0 &&
707 record->ucRecordType > 0 &&
708 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
709 switch (record->ucRecordType) {
710 case ATOM_I2C_RECORD_TYPE:
711 i2c_record =
712 (ATOM_I2C_RECORD *)
713 record;
714 i2c_config =
715 (ATOM_I2C_ID_CONFIG_ACCESS *)
716 &i2c_record->sucI2cId;
717 router.i2c_info =
718 radeon_lookup_i2c_gpio(rdev,
719 i2c_config->
720 ucAccess);
721 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
722 break;
723 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
724 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
725 record;
726 router.ddc_valid = true;
727 router.ddc_mux_type = ddc_path->ucMuxType;
728 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
729 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
730 break;
731 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
732 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
733 record;
734 router.cd_valid = true;
735 router.cd_mux_type = cd_path->ucMuxType;
736 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
737 router.cd_mux_state = cd_path->ucMuxState[enum_id];
738 break;
739 }
740 record = (ATOM_COMMON_RECORD_HEADER *)
741 ((char *)record + record->ucRecordSize);
742 }
743 }
744 }
745 }
746 }
747
748 /* look up gpio for ddc, hpd */
749 ddc_bus.valid = false;
750 hpd.hpd = RADEON_HPD_NONE;
751 if ((le16_to_cpu(path->usDeviceTag) &
752 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
753 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
754 if (le16_to_cpu(path->usConnObjectId) ==
755 le16_to_cpu(con_obj->asObjects[j].
756 usObjectID)) {
757 ATOM_COMMON_RECORD_HEADER
758 *record =
759 (ATOM_COMMON_RECORD_HEADER
760 *)
761 (ctx->bios + data_offset +
762 le16_to_cpu(con_obj->
763 asObjects[j].
764 usRecordOffset));
765 ATOM_I2C_RECORD *i2c_record;
766 ATOM_HPD_INT_RECORD *hpd_record;
767 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
768
769 while (record->ucRecordSize > 0 &&
770 record->ucRecordType > 0 &&
771 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
772 switch (record->ucRecordType) {
773 case ATOM_I2C_RECORD_TYPE:
774 i2c_record =
775 (ATOM_I2C_RECORD *)
776 record;
777 i2c_config =
778 (ATOM_I2C_ID_CONFIG_ACCESS *)
779 &i2c_record->sucI2cId;
780 ddc_bus = radeon_lookup_i2c_gpio(rdev,
781 i2c_config->
782 ucAccess);
783 break;
784 case ATOM_HPD_INT_RECORD_TYPE:
785 hpd_record =
786 (ATOM_HPD_INT_RECORD *)
787 record;
788 gpio = radeon_atombios_lookup_gpio(rdev,
789 hpd_record->ucHPDIntGPIOID);
790 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
791 hpd.plugged_state = hpd_record->ucPlugged_PinState;
792 break;
793 }
794 record =
795 (ATOM_COMMON_RECORD_HEADER
796 *) ((char *)record
797 +
798 record->
799 ucRecordSize);
800 }
801 break;
802 }
803 }
804 }
805
806 /* needed for aux chan transactions */
807 ddc_bus.hpd = hpd.hpd;
808
809 conn_id = le16_to_cpu(path->usConnObjectId);
810
811 if (!radeon_atom_apply_quirks
812 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
813 &ddc_bus, &conn_id, &hpd))
814 continue;
815
816 radeon_add_atom_connector(dev,
817 conn_id,
818 le16_to_cpu(path->
819 usDeviceTag),
820 connector_type, &ddc_bus,
821 igp_lane_info,
822 connector_object_id,
823 &hpd,
824 &router);
825
826 }
827 }
828
829 radeon_link_encoder_connector(dev);
830 return true;
831}
832
833static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
834 int connector_type,
835 uint16_t devices)
836{
837 struct radeon_device *rdev = dev->dev_private;
838
839 if (rdev->flags & RADEON_IS_IGP) {
840 return supported_devices_connector_object_id_convert
841 [connector_type];
842 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
843 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
844 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
845 struct radeon_mode_info *mode_info = &rdev->mode_info;
846 struct atom_context *ctx = mode_info->atom_context;
847 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
848 uint16_t size, data_offset;
849 uint8_t frev, crev;
850 ATOM_XTMDS_INFO *xtmds;
851
852 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
853 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
854
855 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
856 if (connector_type == DRM_MODE_CONNECTOR_DVII)
857 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
858 else
859 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
860 } else {
861 if (connector_type == DRM_MODE_CONNECTOR_DVII)
862 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
863 else
864 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
865 }
866 } else
867 return supported_devices_connector_object_id_convert
868 [connector_type];
869 } else {
870 return supported_devices_connector_object_id_convert
871 [connector_type];
872 }
873}
874
875struct bios_connector {
876 bool valid;
877 uint16_t line_mux;
878 uint16_t devices;
879 int connector_type;
880 struct radeon_i2c_bus_rec ddc_bus;
881 struct radeon_hpd hpd;
882};
883
884bool radeon_get_atom_connector_info_from_supported_devices_table(struct
885 drm_device
886 *dev)
887{
888 struct radeon_device *rdev = dev->dev_private;
889 struct radeon_mode_info *mode_info = &rdev->mode_info;
890 struct atom_context *ctx = mode_info->atom_context;
891 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
892 uint16_t size, data_offset;
893 uint8_t frev, crev;
894 uint16_t device_support;
895 uint8_t dac;
896 union atom_supported_devices *supported_devices;
897 int i, j, max_device;
898 struct bios_connector *bios_connectors;
899 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
900 struct radeon_router router;
901
902 router.ddc_valid = false;
903 router.cd_valid = false;
904
905 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
906 if (!bios_connectors)
907 return false;
908
909 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
910 &data_offset)) {
911 kfree(bios_connectors);
912 return false;
913 }
914
915 supported_devices =
916 (union atom_supported_devices *)(ctx->bios + data_offset);
917
918 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
919
920 if (frev > 1)
921 max_device = ATOM_MAX_SUPPORTED_DEVICE;
922 else
923 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
924
925 for (i = 0; i < max_device; i++) {
926 ATOM_CONNECTOR_INFO_I2C ci;
927
928 if (frev > 1)
929 ci = supported_devices->info_2d1.asConnInfo[i];
930 else
931 ci = supported_devices->info.asConnInfo[i];
932
933 bios_connectors[i].valid = false;
934
935 if (!(device_support & (1 << i))) {
936 continue;
937 }
938
939 if (i == ATOM_DEVICE_CV_INDEX) {
940 DRM_DEBUG_KMS("Skipping Component Video\n");
941 continue;
942 }
943
944 bios_connectors[i].connector_type =
945 supported_devices_connector_convert[ci.sucConnectorInfo.
946 sbfAccess.
947 bfConnectorType];
948
949 if (bios_connectors[i].connector_type ==
950 DRM_MODE_CONNECTOR_Unknown)
951 continue;
952
953 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
954
955 bios_connectors[i].line_mux =
956 ci.sucI2cId.ucAccess;
957
958 /* give tv unique connector ids */
959 if (i == ATOM_DEVICE_TV1_INDEX) {
960 bios_connectors[i].ddc_bus.valid = false;
961 bios_connectors[i].line_mux = 50;
962 } else if (i == ATOM_DEVICE_TV2_INDEX) {
963 bios_connectors[i].ddc_bus.valid = false;
964 bios_connectors[i].line_mux = 51;
965 } else if (i == ATOM_DEVICE_CV_INDEX) {
966 bios_connectors[i].ddc_bus.valid = false;
967 bios_connectors[i].line_mux = 52;
968 } else
969 bios_connectors[i].ddc_bus =
970 radeon_lookup_i2c_gpio(rdev,
971 bios_connectors[i].line_mux);
972
973 if ((crev > 1) && (frev > 1)) {
974 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
975 switch (isb) {
976 case 0x4:
977 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
978 break;
979 case 0xa:
980 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
981 break;
982 default:
983 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
984 break;
985 }
986 } else {
987 if (i == ATOM_DEVICE_DFP1_INDEX)
988 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
989 else if (i == ATOM_DEVICE_DFP2_INDEX)
990 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
991 else
992 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
993 }
994
995 /* Always set the connector type to VGA for CRT1/CRT2. if they are
996 * shared with a DVI port, we'll pick up the DVI connector when we
997 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
998 */
999 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1000 bios_connectors[i].connector_type =
1001 DRM_MODE_CONNECTOR_VGA;
1002
1003 if (!radeon_atom_apply_quirks
1004 (dev, (1 << i), &bios_connectors[i].connector_type,
1005 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1006 &bios_connectors[i].hpd))
1007 continue;
1008
1009 bios_connectors[i].valid = true;
1010 bios_connectors[i].devices = (1 << i);
1011
1012 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1013 radeon_add_atom_encoder(dev,
1014 radeon_get_encoder_enum(dev,
1015 (1 << i),
1016 dac),
1017 (1 << i),
1018 0);
1019 else
1020 radeon_add_legacy_encoder(dev,
1021 radeon_get_encoder_enum(dev,
1022 (1 << i),
1023 dac),
1024 (1 << i));
1025 }
1026
1027 /* combine shared connectors */
1028 for (i = 0; i < max_device; i++) {
1029 if (bios_connectors[i].valid) {
1030 for (j = 0; j < max_device; j++) {
1031 if (bios_connectors[j].valid && (i != j)) {
1032 if (bios_connectors[i].line_mux ==
1033 bios_connectors[j].line_mux) {
1034 /* make sure not to combine LVDS */
1035 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1036 bios_connectors[i].line_mux = 53;
1037 bios_connectors[i].ddc_bus.valid = false;
1038 continue;
1039 }
1040 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1041 bios_connectors[j].line_mux = 53;
1042 bios_connectors[j].ddc_bus.valid = false;
1043 continue;
1044 }
1045 /* combine analog and digital for DVI-I */
1046 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1047 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1048 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1049 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1050 bios_connectors[i].devices |=
1051 bios_connectors[j].devices;
1052 bios_connectors[i].connector_type =
1053 DRM_MODE_CONNECTOR_DVII;
1054 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1055 bios_connectors[i].hpd =
1056 bios_connectors[j].hpd;
1057 bios_connectors[j].valid = false;
1058 }
1059 }
1060 }
1061 }
1062 }
1063 }
1064
1065 /* add the connectors */
1066 for (i = 0; i < max_device; i++) {
1067 if (bios_connectors[i].valid) {
1068 uint16_t connector_object_id =
1069 atombios_get_connector_object_id(dev,
1070 bios_connectors[i].connector_type,
1071 bios_connectors[i].devices);
1072 radeon_add_atom_connector(dev,
1073 bios_connectors[i].line_mux,
1074 bios_connectors[i].devices,
1075 bios_connectors[i].
1076 connector_type,
1077 &bios_connectors[i].ddc_bus,
1078 0,
1079 connector_object_id,
1080 &bios_connectors[i].hpd,
1081 &router);
1082 }
1083 }
1084
1085 radeon_link_encoder_connector(dev);
1086
1087 kfree(bios_connectors);
1088 return true;
1089}
1090
1091union firmware_info {
1092 ATOM_FIRMWARE_INFO info;
1093 ATOM_FIRMWARE_INFO_V1_2 info_12;
1094 ATOM_FIRMWARE_INFO_V1_3 info_13;
1095 ATOM_FIRMWARE_INFO_V1_4 info_14;
1096 ATOM_FIRMWARE_INFO_V2_1 info_21;
1097 ATOM_FIRMWARE_INFO_V2_2 info_22;
1098};
1099
1100union igp_info {
1101 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1102 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1103 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1104 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1105 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1106};
1107
1108static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev)
1109{
1110 struct radeon_mode_info *mode_info = &rdev->mode_info;
1111 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1112 union igp_info *igp_info;
1113 u8 frev, crev;
1114 u16 data_offset;
1115
1116 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1117 &frev, &crev, &data_offset)) {
1118 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1119 data_offset);
1120 rdev->clock.vco_freq =
1121 le32_to_cpu(igp_info->info_6.ulDentistVCOFreq);
1122 }
1123}
1124
1125bool radeon_atom_get_clock_info(struct drm_device *dev)
1126{
1127 struct radeon_device *rdev = dev->dev_private;
1128 struct radeon_mode_info *mode_info = &rdev->mode_info;
1129 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1130 union firmware_info *firmware_info;
1131 uint8_t frev, crev;
1132 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1133 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1134 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1135 struct radeon_pll *spll = &rdev->clock.spll;
1136 struct radeon_pll *mpll = &rdev->clock.mpll;
1137 uint16_t data_offset;
1138
1139 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1140 &frev, &crev, &data_offset)) {
1141 firmware_info =
1142 (union firmware_info *)(mode_info->atom_context->bios +
1143 data_offset);
1144 /* pixel clocks */
1145 p1pll->reference_freq =
1146 le16_to_cpu(firmware_info->info.usReferenceClock);
1147 p1pll->reference_div = 0;
1148
1149 if ((frev < 2) && (crev < 2))
1150 p1pll->pll_out_min =
1151 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1152 else
1153 p1pll->pll_out_min =
1154 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1155 p1pll->pll_out_max =
1156 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1157
1158 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) {
1159 p1pll->lcd_pll_out_min =
1160 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1161 if (p1pll->lcd_pll_out_min == 0)
1162 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1163 p1pll->lcd_pll_out_max =
1164 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1165 if (p1pll->lcd_pll_out_max == 0)
1166 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1167 } else {
1168 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1169 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1170 }
1171
1172 if (p1pll->pll_out_min == 0) {
1173 if (ASIC_IS_AVIVO(rdev))
1174 p1pll->pll_out_min = 64800;
1175 else
1176 p1pll->pll_out_min = 20000;
1177 }
1178
1179 p1pll->pll_in_min =
1180 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1181 p1pll->pll_in_max =
1182 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1183
1184 *p2pll = *p1pll;
1185
1186 /* system clock */
1187 if (ASIC_IS_DCE4(rdev))
1188 spll->reference_freq =
1189 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1190 else
1191 spll->reference_freq =
1192 le16_to_cpu(firmware_info->info.usReferenceClock);
1193 spll->reference_div = 0;
1194
1195 spll->pll_out_min =
1196 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1197 spll->pll_out_max =
1198 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1199
1200 /* ??? */
1201 if (spll->pll_out_min == 0) {
1202 if (ASIC_IS_AVIVO(rdev))
1203 spll->pll_out_min = 64800;
1204 else
1205 spll->pll_out_min = 20000;
1206 }
1207
1208 spll->pll_in_min =
1209 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1210 spll->pll_in_max =
1211 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1212
1213 /* memory clock */
1214 if (ASIC_IS_DCE4(rdev))
1215 mpll->reference_freq =
1216 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1217 else
1218 mpll->reference_freq =
1219 le16_to_cpu(firmware_info->info.usReferenceClock);
1220 mpll->reference_div = 0;
1221
1222 mpll->pll_out_min =
1223 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1224 mpll->pll_out_max =
1225 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1226
1227 /* ??? */
1228 if (mpll->pll_out_min == 0) {
1229 if (ASIC_IS_AVIVO(rdev))
1230 mpll->pll_out_min = 64800;
1231 else
1232 mpll->pll_out_min = 20000;
1233 }
1234
1235 mpll->pll_in_min =
1236 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1237 mpll->pll_in_max =
1238 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1239
1240 rdev->clock.default_sclk =
1241 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1242 rdev->clock.default_mclk =
1243 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1244
1245 if (ASIC_IS_DCE4(rdev)) {
1246 rdev->clock.default_dispclk =
1247 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1248 if (rdev->clock.default_dispclk == 0) {
1249 if (ASIC_IS_DCE6(rdev))
1250 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1251 else if (ASIC_IS_DCE5(rdev))
1252 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1253 else
1254 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1255 }
1256 /* set a reasonable default for DP */
1257 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1258 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1259 rdev->clock.default_dispclk / 100);
1260 rdev->clock.default_dispclk = 60000;
1261 }
1262 rdev->clock.dp_extclk =
1263 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1264 rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1265 }
1266 *dcpll = *p1pll;
1267
1268 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1269 if (rdev->clock.max_pixel_clock == 0)
1270 rdev->clock.max_pixel_clock = 40000;
1271
1272 /* not technically a clock, but... */
1273 rdev->mode_info.firmware_flags =
1274 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1275
1276 if (ASIC_IS_DCE8(rdev))
1277 rdev->clock.vco_freq =
1278 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq);
1279 else if (ASIC_IS_DCE5(rdev))
1280 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1281 else if (ASIC_IS_DCE41(rdev))
1282 radeon_atombios_get_dentist_vco_freq(rdev);
1283 else
1284 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1285
1286 if (rdev->clock.vco_freq == 0)
1287 rdev->clock.vco_freq = 360000; /* 3.6 GHz */
1288
1289 return true;
1290 }
1291
1292 return false;
1293}
1294
1295bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1296{
1297 struct radeon_mode_info *mode_info = &rdev->mode_info;
1298 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1299 union igp_info *igp_info;
1300 u8 frev, crev;
1301 u16 data_offset;
1302
1303 /* sideport is AMD only */
1304 if (rdev->family == CHIP_RS600)
1305 return false;
1306
1307 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1308 &frev, &crev, &data_offset)) {
1309 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1310 data_offset);
1311 switch (crev) {
1312 case 1:
1313 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1314 return true;
1315 break;
1316 case 2:
1317 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1318 return true;
1319 break;
1320 default:
1321 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1322 break;
1323 }
1324 }
1325 return false;
1326}
1327
1328bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1329 struct radeon_encoder_int_tmds *tmds)
1330{
1331 struct drm_device *dev = encoder->base.dev;
1332 struct radeon_device *rdev = dev->dev_private;
1333 struct radeon_mode_info *mode_info = &rdev->mode_info;
1334 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1335 uint16_t data_offset;
1336 struct _ATOM_TMDS_INFO *tmds_info;
1337 uint8_t frev, crev;
1338 uint16_t maxfreq;
1339 int i;
1340
1341 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1342 &frev, &crev, &data_offset)) {
1343 tmds_info =
1344 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1345 data_offset);
1346
1347 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1348 for (i = 0; i < 4; i++) {
1349 tmds->tmds_pll[i].freq =
1350 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1351 tmds->tmds_pll[i].value =
1352 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1353 tmds->tmds_pll[i].value |=
1354 (tmds_info->asMiscInfo[i].
1355 ucPLL_VCO_Gain & 0x3f) << 6;
1356 tmds->tmds_pll[i].value |=
1357 (tmds_info->asMiscInfo[i].
1358 ucPLL_DutyCycle & 0xf) << 12;
1359 tmds->tmds_pll[i].value |=
1360 (tmds_info->asMiscInfo[i].
1361 ucPLL_VoltageSwing & 0xf) << 16;
1362
1363 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1364 tmds->tmds_pll[i].freq,
1365 tmds->tmds_pll[i].value);
1366
1367 if (maxfreq == tmds->tmds_pll[i].freq) {
1368 tmds->tmds_pll[i].freq = 0xffffffff;
1369 break;
1370 }
1371 }
1372 return true;
1373 }
1374 return false;
1375}
1376
1377bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1378 struct radeon_atom_ss *ss,
1379 int id)
1380{
1381 struct radeon_mode_info *mode_info = &rdev->mode_info;
1382 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1383 uint16_t data_offset, size;
1384 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1385 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1386 uint8_t frev, crev;
1387 int i, num_indices;
1388
1389 memset(ss, 0, sizeof(struct radeon_atom_ss));
1390 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1391 &frev, &crev, &data_offset)) {
1392 ss_info =
1393 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1394
1395 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1396 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1397 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *)
1398 ((u8 *)&ss_info->asSS_Info[0]);
1399 for (i = 0; i < num_indices; i++) {
1400 if (ss_assign->ucSS_Id == id) {
1401 ss->percentage =
1402 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
1403 ss->type = ss_assign->ucSpreadSpectrumType;
1404 ss->step = ss_assign->ucSS_Step;
1405 ss->delay = ss_assign->ucSS_Delay;
1406 ss->range = ss_assign->ucSS_Range;
1407 ss->refdiv = ss_assign->ucRecommendedRef_Div;
1408 return true;
1409 }
1410 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *)
1411 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1412 }
1413 }
1414 return false;
1415}
1416
1417static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1418 struct radeon_atom_ss *ss,
1419 int id)
1420{
1421 struct radeon_mode_info *mode_info = &rdev->mode_info;
1422 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1423 u16 data_offset, size;
1424 union igp_info *igp_info;
1425 u8 frev, crev;
1426 u16 percentage = 0, rate = 0;
1427
1428 /* get any igp specific overrides */
1429 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1430 &frev, &crev, &data_offset)) {
1431 igp_info = (union igp_info *)
1432 (mode_info->atom_context->bios + data_offset);
1433 switch (crev) {
1434 case 6:
1435 switch (id) {
1436 case ASIC_INTERNAL_SS_ON_TMDS:
1437 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1438 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1439 break;
1440 case ASIC_INTERNAL_SS_ON_HDMI:
1441 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1442 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1443 break;
1444 case ASIC_INTERNAL_SS_ON_LVDS:
1445 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1446 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1447 break;
1448 }
1449 break;
1450 case 7:
1451 switch (id) {
1452 case ASIC_INTERNAL_SS_ON_TMDS:
1453 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1454 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1455 break;
1456 case ASIC_INTERNAL_SS_ON_HDMI:
1457 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1458 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1459 break;
1460 case ASIC_INTERNAL_SS_ON_LVDS:
1461 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1462 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1463 break;
1464 }
1465 break;
1466 case 8:
1467 switch (id) {
1468 case ASIC_INTERNAL_SS_ON_TMDS:
1469 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1470 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1471 break;
1472 case ASIC_INTERNAL_SS_ON_HDMI:
1473 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1474 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1475 break;
1476 case ASIC_INTERNAL_SS_ON_LVDS:
1477 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1478 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1479 break;
1480 }
1481 break;
1482 default:
1483 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1484 break;
1485 }
1486 if (percentage)
1487 ss->percentage = percentage;
1488 if (rate)
1489 ss->rate = rate;
1490 }
1491}
1492
1493union asic_ss_info {
1494 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1495 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1496 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1497};
1498
1499union asic_ss_assignment {
1500 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
1501 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
1502 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
1503};
1504
1505bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1506 struct radeon_atom_ss *ss,
1507 int id, u32 clock)
1508{
1509 struct radeon_mode_info *mode_info = &rdev->mode_info;
1510 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1511 uint16_t data_offset, size;
1512 union asic_ss_info *ss_info;
1513 union asic_ss_assignment *ss_assign;
1514 uint8_t frev, crev;
1515 int i, num_indices;
1516
1517 if (id == ASIC_INTERNAL_MEMORY_SS) {
1518 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1519 return false;
1520 }
1521 if (id == ASIC_INTERNAL_ENGINE_SS) {
1522 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1523 return false;
1524 }
1525
1526 memset(ss, 0, sizeof(struct radeon_atom_ss));
1527 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1528 &frev, &crev, &data_offset)) {
1529
1530 ss_info =
1531 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1532
1533 switch (frev) {
1534 case 1:
1535 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1536 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1537
1538 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
1539 for (i = 0; i < num_indices; i++) {
1540 if ((ss_assign->v1.ucClockIndication == id) &&
1541 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1542 ss->percentage =
1543 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1544 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1545 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1546 ss->percentage_divider = 100;
1547 return true;
1548 }
1549 ss_assign = (union asic_ss_assignment *)
1550 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1551 }
1552 break;
1553 case 2:
1554 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1555 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1556 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
1557 for (i = 0; i < num_indices; i++) {
1558 if ((ss_assign->v2.ucClockIndication == id) &&
1559 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1560 ss->percentage =
1561 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1562 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1563 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1564 ss->percentage_divider = 100;
1565 if ((crev == 2) &&
1566 ((id == ASIC_INTERNAL_ENGINE_SS) ||
1567 (id == ASIC_INTERNAL_MEMORY_SS)))
1568 ss->rate /= 100;
1569 return true;
1570 }
1571 ss_assign = (union asic_ss_assignment *)
1572 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1573 }
1574 break;
1575 case 3:
1576 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1577 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1578 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
1579 for (i = 0; i < num_indices; i++) {
1580 if ((ss_assign->v3.ucClockIndication == id) &&
1581 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1582 ss->percentage =
1583 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1584 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1585 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1586 if (ss_assign->v3.ucSpreadSpectrumMode &
1587 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
1588 ss->percentage_divider = 1000;
1589 else
1590 ss->percentage_divider = 100;
1591 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1592 (id == ASIC_INTERNAL_MEMORY_SS))
1593 ss->rate /= 100;
1594 if (rdev->flags & RADEON_IS_IGP)
1595 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1596 return true;
1597 }
1598 ss_assign = (union asic_ss_assignment *)
1599 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1600 }
1601 break;
1602 default:
1603 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1604 break;
1605 }
1606
1607 }
1608 return false;
1609}
1610
1611union lvds_info {
1612 struct _ATOM_LVDS_INFO info;
1613 struct _ATOM_LVDS_INFO_V12 info_12;
1614};
1615
1616struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1617 radeon_encoder
1618 *encoder)
1619{
1620 struct drm_device *dev = encoder->base.dev;
1621 struct radeon_device *rdev = dev->dev_private;
1622 struct radeon_mode_info *mode_info = &rdev->mode_info;
1623 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1624 uint16_t data_offset, misc;
1625 union lvds_info *lvds_info;
1626 uint8_t frev, crev;
1627 struct radeon_encoder_atom_dig *lvds = NULL;
1628 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1629
1630 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1631 &frev, &crev, &data_offset)) {
1632 lvds_info =
1633 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1634 lvds =
1635 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1636
1637 if (!lvds)
1638 return NULL;
1639
1640 lvds->native_mode.clock =
1641 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1642 lvds->native_mode.hdisplay =
1643 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1644 lvds->native_mode.vdisplay =
1645 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1646 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1647 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1648 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1649 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1650 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1651 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1652 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1653 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1654 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1655 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1656 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1657 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1658 lvds->panel_pwr_delay =
1659 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1660 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1661
1662 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1663 if (misc & ATOM_VSYNC_POLARITY)
1664 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1665 if (misc & ATOM_HSYNC_POLARITY)
1666 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1667 if (misc & ATOM_COMPOSITESYNC)
1668 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1669 if (misc & ATOM_INTERLACE)
1670 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1671 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1672 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1673
1674 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1675 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1676
1677 /* set crtc values */
1678 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1679
1680 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1681
1682 encoder->native_mode = lvds->native_mode;
1683
1684 if (encoder_enum == 2)
1685 lvds->linkb = true;
1686 else
1687 lvds->linkb = false;
1688
1689 /* parse the lcd record table */
1690 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1691 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1692 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1693 bool bad_record = false;
1694 u8 *record;
1695
1696 if ((frev == 1) && (crev < 2))
1697 /* absolute */
1698 record = (u8 *)(mode_info->atom_context->bios +
1699 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1700 else
1701 /* relative */
1702 record = (u8 *)(mode_info->atom_context->bios +
1703 data_offset +
1704 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1705 while (*record != ATOM_RECORD_END_TYPE) {
1706 switch (*record) {
1707 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1708 record += sizeof(ATOM_PATCH_RECORD_MODE);
1709 break;
1710 case LCD_RTS_RECORD_TYPE:
1711 record += sizeof(ATOM_LCD_RTS_RECORD);
1712 break;
1713 case LCD_CAP_RECORD_TYPE:
1714 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1715 break;
1716 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1717 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1718 if (fake_edid_record->ucFakeEDIDLength) {
1719 const struct drm_edid *edid;
1720 int edid_size;
1721
1722 if (fake_edid_record->ucFakeEDIDLength == 128)
1723 edid_size = fake_edid_record->ucFakeEDIDLength;
1724 else
1725 edid_size = fake_edid_record->ucFakeEDIDLength * 128;
1726 edid = drm_edid_alloc(fake_edid_record->ucFakeEDIDString, edid_size);
1727 if (drm_edid_valid(edid))
1728 rdev->mode_info.bios_hardcoded_edid = edid;
1729 else
1730 drm_edid_free(edid);
1731 record += struct_size(fake_edid_record,
1732 ucFakeEDIDString,
1733 edid_size);
1734 } else {
1735 /* empty fake edid record must be 3 bytes long */
1736 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1;
1737 }
1738 break;
1739 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1740 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1741 lvds->native_mode.width_mm = panel_res_record->usHSize;
1742 lvds->native_mode.height_mm = panel_res_record->usVSize;
1743 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1744 break;
1745 default:
1746 DRM_ERROR("Bad LCD record %d\n", *record);
1747 bad_record = true;
1748 break;
1749 }
1750 if (bad_record)
1751 break;
1752 }
1753 }
1754 }
1755 return lvds;
1756}
1757
1758struct radeon_encoder_primary_dac *
1759radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1760{
1761 struct drm_device *dev = encoder->base.dev;
1762 struct radeon_device *rdev = dev->dev_private;
1763 struct radeon_mode_info *mode_info = &rdev->mode_info;
1764 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1765 uint16_t data_offset;
1766 struct _COMPASSIONATE_DATA *dac_info;
1767 uint8_t frev, crev;
1768 uint8_t bg, dac;
1769 struct radeon_encoder_primary_dac *p_dac = NULL;
1770
1771 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1772 &frev, &crev, &data_offset)) {
1773 dac_info = (struct _COMPASSIONATE_DATA *)
1774 (mode_info->atom_context->bios + data_offset);
1775
1776 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1777
1778 if (!p_dac)
1779 return NULL;
1780
1781 bg = dac_info->ucDAC1_BG_Adjustment;
1782 dac = dac_info->ucDAC1_DAC_Adjustment;
1783 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1784
1785 }
1786 return p_dac;
1787}
1788
1789bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1790 struct drm_display_mode *mode)
1791{
1792 struct radeon_mode_info *mode_info = &rdev->mode_info;
1793 ATOM_ANALOG_TV_INFO *tv_info;
1794 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1795 ATOM_DTD_FORMAT *dtd_timings;
1796 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1797 u8 frev, crev;
1798 u16 data_offset, misc;
1799
1800 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1801 &frev, &crev, &data_offset))
1802 return false;
1803
1804 switch (crev) {
1805 case 1:
1806 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1807 if (index >= MAX_SUPPORTED_TV_TIMING)
1808 return false;
1809
1810 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1811 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1812 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1813 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1814 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1815
1816 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1817 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1818 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1819 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1820 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1821
1822 mode->flags = 0;
1823 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1824 if (misc & ATOM_VSYNC_POLARITY)
1825 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1826 if (misc & ATOM_HSYNC_POLARITY)
1827 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1828 if (misc & ATOM_COMPOSITESYNC)
1829 mode->flags |= DRM_MODE_FLAG_CSYNC;
1830 if (misc & ATOM_INTERLACE)
1831 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1832 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1833 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1834
1835 mode->crtc_clock = mode->clock =
1836 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1837
1838 if (index == 1) {
1839 /* PAL timings appear to have wrong values for totals */
1840 mode->crtc_htotal -= 1;
1841 mode->crtc_vtotal -= 1;
1842 }
1843 break;
1844 case 2:
1845 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1846 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1847 return false;
1848
1849 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1850 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1851 le16_to_cpu(dtd_timings->usHBlanking_Time);
1852 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1853 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1854 le16_to_cpu(dtd_timings->usHSyncOffset);
1855 mode->crtc_hsync_end = mode->crtc_hsync_start +
1856 le16_to_cpu(dtd_timings->usHSyncWidth);
1857
1858 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1859 le16_to_cpu(dtd_timings->usVBlanking_Time);
1860 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1861 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1862 le16_to_cpu(dtd_timings->usVSyncOffset);
1863 mode->crtc_vsync_end = mode->crtc_vsync_start +
1864 le16_to_cpu(dtd_timings->usVSyncWidth);
1865
1866 mode->flags = 0;
1867 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1868 if (misc & ATOM_VSYNC_POLARITY)
1869 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1870 if (misc & ATOM_HSYNC_POLARITY)
1871 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1872 if (misc & ATOM_COMPOSITESYNC)
1873 mode->flags |= DRM_MODE_FLAG_CSYNC;
1874 if (misc & ATOM_INTERLACE)
1875 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1876 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1877 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1878
1879 mode->crtc_clock = mode->clock =
1880 le16_to_cpu(dtd_timings->usPixClk) * 10;
1881 break;
1882 }
1883 return true;
1884}
1885
1886enum radeon_tv_std
1887radeon_atombios_get_tv_info(struct radeon_device *rdev)
1888{
1889 struct radeon_mode_info *mode_info = &rdev->mode_info;
1890 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1891 uint16_t data_offset;
1892 uint8_t frev, crev;
1893 struct _ATOM_ANALOG_TV_INFO *tv_info;
1894 enum radeon_tv_std tv_std = TV_STD_NTSC;
1895
1896 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1897 &frev, &crev, &data_offset)) {
1898
1899 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1900 (mode_info->atom_context->bios + data_offset);
1901
1902 switch (tv_info->ucTV_BootUpDefaultStandard) {
1903 case ATOM_TV_NTSC:
1904 tv_std = TV_STD_NTSC;
1905 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1906 break;
1907 case ATOM_TV_NTSCJ:
1908 tv_std = TV_STD_NTSC_J;
1909 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1910 break;
1911 case ATOM_TV_PAL:
1912 tv_std = TV_STD_PAL;
1913 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1914 break;
1915 case ATOM_TV_PALM:
1916 tv_std = TV_STD_PAL_M;
1917 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1918 break;
1919 case ATOM_TV_PALN:
1920 tv_std = TV_STD_PAL_N;
1921 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1922 break;
1923 case ATOM_TV_PALCN:
1924 tv_std = TV_STD_PAL_CN;
1925 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1926 break;
1927 case ATOM_TV_PAL60:
1928 tv_std = TV_STD_PAL_60;
1929 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1930 break;
1931 case ATOM_TV_SECAM:
1932 tv_std = TV_STD_SECAM;
1933 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1934 break;
1935 default:
1936 tv_std = TV_STD_NTSC;
1937 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1938 break;
1939 }
1940 }
1941 return tv_std;
1942}
1943
1944struct radeon_encoder_tv_dac *
1945radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1946{
1947 struct drm_device *dev = encoder->base.dev;
1948 struct radeon_device *rdev = dev->dev_private;
1949 struct radeon_mode_info *mode_info = &rdev->mode_info;
1950 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1951 uint16_t data_offset;
1952 struct _COMPASSIONATE_DATA *dac_info;
1953 uint8_t frev, crev;
1954 uint8_t bg, dac;
1955 struct radeon_encoder_tv_dac *tv_dac = NULL;
1956
1957 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1958 &frev, &crev, &data_offset)) {
1959
1960 dac_info = (struct _COMPASSIONATE_DATA *)
1961 (mode_info->atom_context->bios + data_offset);
1962
1963 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1964
1965 if (!tv_dac)
1966 return NULL;
1967
1968 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1969 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1970 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1971
1972 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1973 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1974 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1975
1976 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1977 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1978 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1979
1980 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1981 }
1982 return tv_dac;
1983}
1984
1985static const char *thermal_controller_names[] = {
1986 "NONE",
1987 "lm63",
1988 "adm1032",
1989 "adm1030",
1990 "max6649",
1991 "lm63", /* lm64 */
1992 "f75375",
1993 "asc7xxx",
1994};
1995
1996static const char *pp_lib_thermal_controller_names[] = {
1997 "NONE",
1998 "lm63",
1999 "adm1032",
2000 "adm1030",
2001 "max6649",
2002 "lm63", /* lm64 */
2003 "f75375",
2004 "RV6xx",
2005 "RV770",
2006 "adt7473",
2007 "NONE",
2008 "External GPIO",
2009 "Evergreen",
2010 "emc2103",
2011 "Sumo",
2012 "Northern Islands",
2013 "Southern Islands",
2014 "lm96163",
2015 "Sea Islands",
2016};
2017
2018union power_info {
2019 struct _ATOM_POWERPLAY_INFO info;
2020 struct _ATOM_POWERPLAY_INFO_V2 info_2;
2021 struct _ATOM_POWERPLAY_INFO_V3 info_3;
2022 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2023 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2024 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2025};
2026
2027union pplib_clock_info {
2028 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2029 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2030 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2031 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2032 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
2033 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
2034};
2035
2036union pplib_power_state {
2037 struct _ATOM_PPLIB_STATE v1;
2038 struct _ATOM_PPLIB_STATE_V2 v2;
2039};
2040
2041static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2042 int state_index,
2043 u32 misc, u32 misc2)
2044{
2045 rdev->pm.power_state[state_index].misc = misc;
2046 rdev->pm.power_state[state_index].misc2 = misc2;
2047 /* order matters! */
2048 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2049 rdev->pm.power_state[state_index].type =
2050 POWER_STATE_TYPE_POWERSAVE;
2051 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2052 rdev->pm.power_state[state_index].type =
2053 POWER_STATE_TYPE_BATTERY;
2054 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2055 rdev->pm.power_state[state_index].type =
2056 POWER_STATE_TYPE_BATTERY;
2057 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2058 rdev->pm.power_state[state_index].type =
2059 POWER_STATE_TYPE_BALANCED;
2060 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2061 rdev->pm.power_state[state_index].type =
2062 POWER_STATE_TYPE_PERFORMANCE;
2063 rdev->pm.power_state[state_index].flags &=
2064 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2065 }
2066 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2067 rdev->pm.power_state[state_index].type =
2068 POWER_STATE_TYPE_BALANCED;
2069 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2070 rdev->pm.power_state[state_index].type =
2071 POWER_STATE_TYPE_DEFAULT;
2072 rdev->pm.default_power_state_index = state_index;
2073 rdev->pm.power_state[state_index].default_clock_mode =
2074 &rdev->pm.power_state[state_index].clock_info[0];
2075 } else if (state_index == 0) {
2076 rdev->pm.power_state[state_index].clock_info[0].flags |=
2077 RADEON_PM_MODE_NO_DISPLAY;
2078 }
2079}
2080
2081static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2082{
2083 struct radeon_mode_info *mode_info = &rdev->mode_info;
2084 u32 misc, misc2 = 0;
2085 int num_modes = 0, i;
2086 int state_index = 0;
2087 struct radeon_i2c_bus_rec i2c_bus;
2088 union power_info *power_info;
2089 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2090 u16 data_offset;
2091 u8 frev, crev;
2092
2093 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2094 &frev, &crev, &data_offset))
2095 return state_index;
2096 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2097
2098 /* add the i2c bus for thermal/fan chip */
2099 if ((power_info->info.ucOverdriveThermalController > 0) &&
2100 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2101 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2102 thermal_controller_names[power_info->info.ucOverdriveThermalController],
2103 power_info->info.ucOverdriveControllerAddress >> 1);
2104 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2105 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2106 if (rdev->pm.i2c_bus) {
2107 struct i2c_board_info info = { };
2108 const char *name = thermal_controller_names[power_info->info.
2109 ucOverdriveThermalController];
2110 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2111 strscpy(info.type, name, sizeof(info.type));
2112 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2113 }
2114 }
2115 num_modes = power_info->info.ucNumOfPowerModeEntries;
2116 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2117 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2118 if (num_modes == 0)
2119 return state_index;
2120 rdev->pm.power_state = kcalloc(num_modes,
2121 sizeof(struct radeon_power_state),
2122 GFP_KERNEL);
2123 if (!rdev->pm.power_state)
2124 return state_index;
2125 /* last mode is usually default, array is low to high */
2126 for (i = 0; i < num_modes; i++) {
2127 /* avoid memory leaks from invalid modes or unknown frev. */
2128 if (!rdev->pm.power_state[state_index].clock_info) {
2129 rdev->pm.power_state[state_index].clock_info =
2130 kzalloc(sizeof(struct radeon_pm_clock_info),
2131 GFP_KERNEL);
2132 }
2133 if (!rdev->pm.power_state[state_index].clock_info)
2134 goto out;
2135 rdev->pm.power_state[state_index].num_clock_modes = 1;
2136 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2137 switch (frev) {
2138 case 1:
2139 rdev->pm.power_state[state_index].clock_info[0].mclk =
2140 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2141 rdev->pm.power_state[state_index].clock_info[0].sclk =
2142 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2143 /* skip invalid modes */
2144 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2145 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2146 continue;
2147 rdev->pm.power_state[state_index].pcie_lanes =
2148 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2149 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2150 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2151 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2152 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2153 VOLTAGE_GPIO;
2154 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2155 radeon_atombios_lookup_gpio(rdev,
2156 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2157 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2158 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2159 true;
2160 else
2161 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2162 false;
2163 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2164 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2165 VOLTAGE_VDDC;
2166 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2167 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2168 }
2169 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2170 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2171 state_index++;
2172 break;
2173 case 2:
2174 rdev->pm.power_state[state_index].clock_info[0].mclk =
2175 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2176 rdev->pm.power_state[state_index].clock_info[0].sclk =
2177 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2178 /* skip invalid modes */
2179 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2180 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2181 continue;
2182 rdev->pm.power_state[state_index].pcie_lanes =
2183 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2184 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2185 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2186 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2187 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2188 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2189 VOLTAGE_GPIO;
2190 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2191 radeon_atombios_lookup_gpio(rdev,
2192 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2193 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2194 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2195 true;
2196 else
2197 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2198 false;
2199 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2200 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2201 VOLTAGE_VDDC;
2202 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2203 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2204 }
2205 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2206 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2207 state_index++;
2208 break;
2209 case 3:
2210 rdev->pm.power_state[state_index].clock_info[0].mclk =
2211 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2212 rdev->pm.power_state[state_index].clock_info[0].sclk =
2213 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2214 /* skip invalid modes */
2215 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2216 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2217 continue;
2218 rdev->pm.power_state[state_index].pcie_lanes =
2219 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2220 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2221 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2222 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2223 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2224 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2225 VOLTAGE_GPIO;
2226 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2227 radeon_atombios_lookup_gpio(rdev,
2228 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2229 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2230 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2231 true;
2232 else
2233 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2234 false;
2235 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2236 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2237 VOLTAGE_VDDC;
2238 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2239 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2240 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2241 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2242 true;
2243 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2244 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2245 }
2246 }
2247 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2248 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2249 state_index++;
2250 break;
2251 }
2252 }
2253out:
2254 /* free any unused clock_info allocation. */
2255 if (state_index && state_index < num_modes) {
2256 kfree(rdev->pm.power_state[state_index].clock_info);
2257 rdev->pm.power_state[state_index].clock_info = NULL;
2258 }
2259
2260 /* last mode is usually default */
2261 if (state_index && rdev->pm.default_power_state_index == -1) {
2262 rdev->pm.power_state[state_index - 1].type =
2263 POWER_STATE_TYPE_DEFAULT;
2264 rdev->pm.default_power_state_index = state_index - 1;
2265 rdev->pm.power_state[state_index - 1].default_clock_mode =
2266 &rdev->pm.power_state[state_index - 1].clock_info[0];
2267 rdev->pm.power_state[state_index - 1].flags &=
2268 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2269 rdev->pm.power_state[state_index - 1].misc = 0;
2270 rdev->pm.power_state[state_index - 1].misc2 = 0;
2271 }
2272 return state_index;
2273}
2274
2275static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2276 ATOM_PPLIB_THERMALCONTROLLER *controller)
2277{
2278 struct radeon_i2c_bus_rec i2c_bus;
2279
2280 /* add the i2c bus for thermal/fan chip */
2281 if (controller->ucType > 0) {
2282 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN)
2283 rdev->pm.no_fan = true;
2284 rdev->pm.fan_pulses_per_revolution =
2285 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
2286 if (rdev->pm.fan_pulses_per_revolution) {
2287 rdev->pm.fan_min_rpm = controller->ucFanMinRPM;
2288 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM;
2289 }
2290 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2291 DRM_INFO("Internal thermal controller %s fan control\n",
2292 (controller->ucFanParameters &
2293 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2294 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2295 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2296 DRM_INFO("Internal thermal controller %s fan control\n",
2297 (controller->ucFanParameters &
2298 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2299 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2300 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2301 DRM_INFO("Internal thermal controller %s fan control\n",
2302 (controller->ucFanParameters &
2303 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2304 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2305 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2306 DRM_INFO("Internal thermal controller %s fan control\n",
2307 (controller->ucFanParameters &
2308 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2309 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2310 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2311 DRM_INFO("Internal thermal controller %s fan control\n",
2312 (controller->ucFanParameters &
2313 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2314 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2315 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2316 DRM_INFO("Internal thermal controller %s fan control\n",
2317 (controller->ucFanParameters &
2318 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2319 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2320 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2321 DRM_INFO("Internal thermal controller %s fan control\n",
2322 (controller->ucFanParameters &
2323 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2324 rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2325 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
2326 DRM_INFO("Internal thermal controller %s fan control\n",
2327 (controller->ucFanParameters &
2328 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2329 rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2330 } else if (controller->ucType ==
2331 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
2332 DRM_INFO("External GPIO thermal controller %s fan control\n",
2333 (controller->ucFanParameters &
2334 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2335 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
2336 } else if (controller->ucType ==
2337 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
2338 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
2339 (controller->ucFanParameters &
2340 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2341 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
2342 } else if (controller->ucType ==
2343 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
2344 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
2345 (controller->ucFanParameters &
2346 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2347 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2348 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2349 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2350 pp_lib_thermal_controller_names[controller->ucType],
2351 controller->ucI2cAddress >> 1,
2352 (controller->ucFanParameters &
2353 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2354 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
2355 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2356 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2357 if (rdev->pm.i2c_bus) {
2358 struct i2c_board_info info = { };
2359 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2360 info.addr = controller->ucI2cAddress >> 1;
2361 strscpy(info.type, name, sizeof(info.type));
2362 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2363 }
2364 } else {
2365 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2366 controller->ucType,
2367 controller->ucI2cAddress >> 1,
2368 (controller->ucFanParameters &
2369 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2370 }
2371 }
2372}
2373
2374void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2375 u16 *vddc, u16 *vddci, u16 *mvdd)
2376{
2377 struct radeon_mode_info *mode_info = &rdev->mode_info;
2378 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2379 u8 frev, crev;
2380 u16 data_offset;
2381 union firmware_info *firmware_info;
2382
2383 *vddc = 0;
2384 *vddci = 0;
2385 *mvdd = 0;
2386
2387 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2388 &frev, &crev, &data_offset)) {
2389 firmware_info =
2390 (union firmware_info *)(mode_info->atom_context->bios +
2391 data_offset);
2392 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2393 if ((frev == 2) && (crev >= 2)) {
2394 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2395 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2396 }
2397 }
2398}
2399
2400static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2401 int state_index, int mode_index,
2402 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2403{
2404 int j;
2405 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2406 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2407 u16 vddc, vddci, mvdd;
2408
2409 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2410
2411 rdev->pm.power_state[state_index].misc = misc;
2412 rdev->pm.power_state[state_index].misc2 = misc2;
2413 rdev->pm.power_state[state_index].pcie_lanes =
2414 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2415 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2416 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2417 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2418 rdev->pm.power_state[state_index].type =
2419 POWER_STATE_TYPE_BATTERY;
2420 break;
2421 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2422 rdev->pm.power_state[state_index].type =
2423 POWER_STATE_TYPE_BALANCED;
2424 break;
2425 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2426 rdev->pm.power_state[state_index].type =
2427 POWER_STATE_TYPE_PERFORMANCE;
2428 break;
2429 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2430 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2431 rdev->pm.power_state[state_index].type =
2432 POWER_STATE_TYPE_PERFORMANCE;
2433 break;
2434 }
2435 rdev->pm.power_state[state_index].flags = 0;
2436 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2437 rdev->pm.power_state[state_index].flags |=
2438 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2439 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2440 rdev->pm.power_state[state_index].type =
2441 POWER_STATE_TYPE_DEFAULT;
2442 rdev->pm.default_power_state_index = state_index;
2443 rdev->pm.power_state[state_index].default_clock_mode =
2444 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2445 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2446 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2447 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2448 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2449 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2450 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2451 } else {
2452 u16 max_vddci = 0;
2453
2454 if (ASIC_IS_DCE4(rdev))
2455 radeon_atom_get_max_voltage(rdev,
2456 SET_VOLTAGE_TYPE_ASIC_VDDCI,
2457 &max_vddci);
2458 /* patch the table values with the default sclk/mclk from firmware info */
2459 for (j = 0; j < mode_index; j++) {
2460 rdev->pm.power_state[state_index].clock_info[j].mclk =
2461 rdev->clock.default_mclk;
2462 rdev->pm.power_state[state_index].clock_info[j].sclk =
2463 rdev->clock.default_sclk;
2464 if (vddc)
2465 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2466 vddc;
2467 if (max_vddci)
2468 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2469 max_vddci;
2470 }
2471 }
2472 }
2473}
2474
2475static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2476 int state_index, int mode_index,
2477 union pplib_clock_info *clock_info)
2478{
2479 u32 sclk, mclk;
2480 u16 vddc;
2481
2482 if (rdev->flags & RADEON_IS_IGP) {
2483 if (rdev->family >= CHIP_PALM) {
2484 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2485 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2486 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2487 } else {
2488 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2489 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2490 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2491 }
2492 } else if (rdev->family >= CHIP_BONAIRE) {
2493 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2494 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2495 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2496 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2497 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2498 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2499 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2500 VOLTAGE_NONE;
2501 } else if (rdev->family >= CHIP_TAHITI) {
2502 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2503 sclk |= clock_info->si.ucEngineClockHigh << 16;
2504 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2505 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2506 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2507 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2508 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2509 VOLTAGE_SW;
2510 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2511 le16_to_cpu(clock_info->si.usVDDC);
2512 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2513 le16_to_cpu(clock_info->si.usVDDCI);
2514 } else if (rdev->family >= CHIP_CEDAR) {
2515 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2516 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2517 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2518 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2519 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2520 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2521 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2522 VOLTAGE_SW;
2523 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2524 le16_to_cpu(clock_info->evergreen.usVDDC);
2525 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2526 le16_to_cpu(clock_info->evergreen.usVDDCI);
2527 } else {
2528 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2529 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2530 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2531 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2532 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2533 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2534 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2535 VOLTAGE_SW;
2536 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2537 le16_to_cpu(clock_info->r600.usVDDC);
2538 }
2539
2540 /* patch up vddc if necessary */
2541 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2542 case ATOM_VIRTUAL_VOLTAGE_ID0:
2543 case ATOM_VIRTUAL_VOLTAGE_ID1:
2544 case ATOM_VIRTUAL_VOLTAGE_ID2:
2545 case ATOM_VIRTUAL_VOLTAGE_ID3:
2546 case ATOM_VIRTUAL_VOLTAGE_ID4:
2547 case ATOM_VIRTUAL_VOLTAGE_ID5:
2548 case ATOM_VIRTUAL_VOLTAGE_ID6:
2549 case ATOM_VIRTUAL_VOLTAGE_ID7:
2550 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2551 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2552 &vddc) == 0)
2553 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2554 break;
2555 default:
2556 break;
2557 }
2558
2559 if (rdev->flags & RADEON_IS_IGP) {
2560 /* skip invalid modes */
2561 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2562 return false;
2563 } else {
2564 /* skip invalid modes */
2565 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2566 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2567 return false;
2568 }
2569 return true;
2570}
2571
2572static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2573{
2574 struct radeon_mode_info *mode_info = &rdev->mode_info;
2575 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2576 union pplib_power_state *power_state;
2577 int i, j;
2578 int state_index = 0, mode_index = 0;
2579 union pplib_clock_info *clock_info;
2580 bool valid;
2581 union power_info *power_info;
2582 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2583 u16 data_offset;
2584 u8 frev, crev;
2585
2586 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2587 &frev, &crev, &data_offset))
2588 return state_index;
2589 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2590
2591 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2592 if (power_info->pplib.ucNumStates == 0)
2593 return state_index;
2594 rdev->pm.power_state = kcalloc(power_info->pplib.ucNumStates,
2595 sizeof(struct radeon_power_state),
2596 GFP_KERNEL);
2597 if (!rdev->pm.power_state)
2598 return state_index;
2599 /* first mode is usually default, followed by low to high */
2600 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2601 mode_index = 0;
2602 power_state = (union pplib_power_state *)
2603 (mode_info->atom_context->bios + data_offset +
2604 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2605 i * power_info->pplib.ucStateEntrySize);
2606 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2607 (mode_info->atom_context->bios + data_offset +
2608 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2609 (power_state->v1.ucNonClockStateIndex *
2610 power_info->pplib.ucNonClockSize));
2611 rdev->pm.power_state[i].clock_info =
2612 kcalloc((power_info->pplib.ucStateEntrySize - 1) ?
2613 (power_info->pplib.ucStateEntrySize - 1) : 1,
2614 sizeof(struct radeon_pm_clock_info),
2615 GFP_KERNEL);
2616 if (!rdev->pm.power_state[i].clock_info)
2617 return state_index;
2618 if (power_info->pplib.ucStateEntrySize - 1) {
2619 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2620 clock_info = (union pplib_clock_info *)
2621 (mode_info->atom_context->bios + data_offset +
2622 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2623 (power_state->v1.ucClockStateIndices[j] *
2624 power_info->pplib.ucClockInfoSize));
2625 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2626 state_index, mode_index,
2627 clock_info);
2628 if (valid)
2629 mode_index++;
2630 }
2631 } else {
2632 rdev->pm.power_state[state_index].clock_info[0].mclk =
2633 rdev->clock.default_mclk;
2634 rdev->pm.power_state[state_index].clock_info[0].sclk =
2635 rdev->clock.default_sclk;
2636 mode_index++;
2637 }
2638 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2639 if (mode_index) {
2640 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2641 non_clock_info);
2642 state_index++;
2643 }
2644 }
2645 /* if multiple clock modes, mark the lowest as no display */
2646 for (i = 0; i < state_index; i++) {
2647 if (rdev->pm.power_state[i].num_clock_modes > 1)
2648 rdev->pm.power_state[i].clock_info[0].flags |=
2649 RADEON_PM_MODE_NO_DISPLAY;
2650 }
2651 /* first mode is usually default */
2652 if (rdev->pm.default_power_state_index == -1) {
2653 rdev->pm.power_state[0].type =
2654 POWER_STATE_TYPE_DEFAULT;
2655 rdev->pm.default_power_state_index = 0;
2656 rdev->pm.power_state[0].default_clock_mode =
2657 &rdev->pm.power_state[0].clock_info[0];
2658 }
2659 return state_index;
2660}
2661
2662static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2663{
2664 struct radeon_mode_info *mode_info = &rdev->mode_info;
2665 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2666 union pplib_power_state *power_state;
2667 int i, j, non_clock_array_index, clock_array_index;
2668 int state_index = 0, mode_index = 0;
2669 union pplib_clock_info *clock_info;
2670 struct _StateArray *state_array;
2671 struct _ClockInfoArray *clock_info_array;
2672 struct _NonClockInfoArray *non_clock_info_array;
2673 bool valid;
2674 union power_info *power_info;
2675 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2676 u16 data_offset;
2677 u8 frev, crev;
2678 u8 *power_state_offset;
2679
2680 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2681 &frev, &crev, &data_offset))
2682 return state_index;
2683 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2684
2685 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2686 state_array = (struct _StateArray *)
2687 (mode_info->atom_context->bios + data_offset +
2688 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2689 clock_info_array = (struct _ClockInfoArray *)
2690 (mode_info->atom_context->bios + data_offset +
2691 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2692 non_clock_info_array = (struct _NonClockInfoArray *)
2693 (mode_info->atom_context->bios + data_offset +
2694 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2695 if (state_array->ucNumEntries == 0)
2696 return state_index;
2697 rdev->pm.power_state = kcalloc(state_array->ucNumEntries,
2698 sizeof(struct radeon_power_state),
2699 GFP_KERNEL);
2700 if (!rdev->pm.power_state)
2701 return state_index;
2702 power_state_offset = (u8 *)state_array->states;
2703 for (i = 0; i < state_array->ucNumEntries; i++) {
2704 mode_index = 0;
2705 power_state = (union pplib_power_state *)power_state_offset;
2706 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2707 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2708 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2709 rdev->pm.power_state[i].clock_info =
2710 kcalloc(power_state->v2.ucNumDPMLevels ?
2711 power_state->v2.ucNumDPMLevels : 1,
2712 sizeof(struct radeon_pm_clock_info),
2713 GFP_KERNEL);
2714 if (!rdev->pm.power_state[i].clock_info)
2715 return state_index;
2716 if (power_state->v2.ucNumDPMLevels) {
2717 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2718 clock_array_index = power_state->v2.clockInfoIndex[j];
2719 clock_info = (union pplib_clock_info *)
2720 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2721 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2722 state_index, mode_index,
2723 clock_info);
2724 if (valid)
2725 mode_index++;
2726 }
2727 } else {
2728 rdev->pm.power_state[state_index].clock_info[0].mclk =
2729 rdev->clock.default_mclk;
2730 rdev->pm.power_state[state_index].clock_info[0].sclk =
2731 rdev->clock.default_sclk;
2732 mode_index++;
2733 }
2734 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2735 if (mode_index) {
2736 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2737 non_clock_info);
2738 state_index++;
2739 }
2740 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2741 }
2742 /* if multiple clock modes, mark the lowest as no display */
2743 for (i = 0; i < state_index; i++) {
2744 if (rdev->pm.power_state[i].num_clock_modes > 1)
2745 rdev->pm.power_state[i].clock_info[0].flags |=
2746 RADEON_PM_MODE_NO_DISPLAY;
2747 }
2748 /* first mode is usually default */
2749 if (rdev->pm.default_power_state_index == -1) {
2750 rdev->pm.power_state[0].type =
2751 POWER_STATE_TYPE_DEFAULT;
2752 rdev->pm.default_power_state_index = 0;
2753 rdev->pm.power_state[0].default_clock_mode =
2754 &rdev->pm.power_state[0].clock_info[0];
2755 }
2756 return state_index;
2757}
2758
2759void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2760{
2761 struct radeon_mode_info *mode_info = &rdev->mode_info;
2762 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2763 u16 data_offset;
2764 u8 frev, crev;
2765 int state_index = 0;
2766
2767 rdev->pm.default_power_state_index = -1;
2768
2769 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2770 &frev, &crev, &data_offset)) {
2771 switch (frev) {
2772 case 1:
2773 case 2:
2774 case 3:
2775 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2776 break;
2777 case 4:
2778 case 5:
2779 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2780 break;
2781 case 6:
2782 state_index = radeon_atombios_parse_power_table_6(rdev);
2783 break;
2784 default:
2785 break;
2786 }
2787 }
2788
2789 if (state_index == 0) {
2790 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2791 if (rdev->pm.power_state) {
2792 rdev->pm.power_state[0].clock_info =
2793 kcalloc(1,
2794 sizeof(struct radeon_pm_clock_info),
2795 GFP_KERNEL);
2796 if (rdev->pm.power_state[0].clock_info) {
2797 /* add the default mode */
2798 rdev->pm.power_state[state_index].type =
2799 POWER_STATE_TYPE_DEFAULT;
2800 rdev->pm.power_state[state_index].num_clock_modes = 1;
2801 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2802 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2803 rdev->pm.power_state[state_index].default_clock_mode =
2804 &rdev->pm.power_state[state_index].clock_info[0];
2805 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2806 rdev->pm.power_state[state_index].pcie_lanes = 16;
2807 rdev->pm.default_power_state_index = state_index;
2808 rdev->pm.power_state[state_index].flags = 0;
2809 state_index++;
2810 }
2811 }
2812 }
2813
2814 rdev->pm.num_power_states = state_index;
2815
2816 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2817 rdev->pm.current_clock_mode_index = 0;
2818 if (rdev->pm.default_power_state_index >= 0)
2819 rdev->pm.current_vddc =
2820 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2821 else
2822 rdev->pm.current_vddc = 0;
2823}
2824
2825union get_clock_dividers {
2826 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2827 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2828 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2829 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2830 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2831 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2832 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2833};
2834
2835int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2836 u8 clock_type,
2837 u32 clock,
2838 bool strobe_mode,
2839 struct atom_clock_dividers *dividers)
2840{
2841 union get_clock_dividers args;
2842 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2843 u8 frev, crev;
2844
2845 memset(&args, 0, sizeof(args));
2846 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2847
2848 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2849 return -EINVAL;
2850
2851 switch (crev) {
2852 case 1:
2853 /* r4xx, r5xx */
2854 args.v1.ucAction = clock_type;
2855 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
2856
2857 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2858
2859 dividers->post_div = args.v1.ucPostDiv;
2860 dividers->fb_div = args.v1.ucFbDiv;
2861 dividers->enable_post_div = true;
2862 break;
2863 case 2:
2864 case 3:
2865 case 5:
2866 /* r6xx, r7xx, evergreen, ni, si */
2867 if (rdev->family <= CHIP_RV770) {
2868 args.v2.ucAction = clock_type;
2869 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
2870
2871 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2872
2873 dividers->post_div = args.v2.ucPostDiv;
2874 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2875 dividers->ref_div = args.v2.ucAction;
2876 if (rdev->family == CHIP_RV770) {
2877 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2878 true : false;
2879 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2880 } else
2881 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2882 } else {
2883 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2884 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2885
2886 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2887
2888 dividers->post_div = args.v3.ucPostDiv;
2889 dividers->enable_post_div = (args.v3.ucCntlFlag &
2890 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2891 dividers->enable_dithen = (args.v3.ucCntlFlag &
2892 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2893 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2894 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2895 dividers->ref_div = args.v3.ucRefDiv;
2896 dividers->vco_mode = (args.v3.ucCntlFlag &
2897 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2898 } else {
2899 /* for SI we use ComputeMemoryClockParam for memory plls */
2900 if (rdev->family >= CHIP_TAHITI)
2901 return -EINVAL;
2902 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2903 if (strobe_mode)
2904 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2905
2906 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2907
2908 dividers->post_div = args.v5.ucPostDiv;
2909 dividers->enable_post_div = (args.v5.ucCntlFlag &
2910 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2911 dividers->enable_dithen = (args.v5.ucCntlFlag &
2912 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2913 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2914 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2915 dividers->ref_div = args.v5.ucRefDiv;
2916 dividers->vco_mode = (args.v5.ucCntlFlag &
2917 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2918 }
2919 }
2920 break;
2921 case 4:
2922 /* fusion */
2923 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
2924
2925 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2926
2927 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2928 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2929 break;
2930 case 6:
2931 /* CI */
2932 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2933 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2934 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2935
2936 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2937
2938 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2939 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2940 dividers->ref_div = args.v6_out.ucPllRefDiv;
2941 dividers->post_div = args.v6_out.ucPllPostDiv;
2942 dividers->flags = args.v6_out.ucPllCntlFlag;
2943 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2944 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2945 break;
2946 default:
2947 return -EINVAL;
2948 }
2949 return 0;
2950}
2951
2952int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2953 u32 clock,
2954 bool strobe_mode,
2955 struct atom_mpll_param *mpll_param)
2956{
2957 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2958 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2959 u8 frev, crev;
2960
2961 memset(&args, 0, sizeof(args));
2962 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2963
2964 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2965 return -EINVAL;
2966
2967 switch (frev) {
2968 case 2:
2969 switch (crev) {
2970 case 1:
2971 /* SI */
2972 args.ulClock = cpu_to_le32(clock); /* 10 khz */
2973 args.ucInputFlag = 0;
2974 if (strobe_mode)
2975 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2976
2977 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2978
2979 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2980 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2981 mpll_param->post_div = args.ucPostDiv;
2982 mpll_param->dll_speed = args.ucDllSpeed;
2983 mpll_param->bwcntl = args.ucBWCntl;
2984 mpll_param->vco_mode =
2985 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
2986 mpll_param->yclk_sel =
2987 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2988 mpll_param->qdr =
2989 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2990 mpll_param->half_rate =
2991 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
2992 break;
2993 default:
2994 return -EINVAL;
2995 }
2996 break;
2997 default:
2998 return -EINVAL;
2999 }
3000 return 0;
3001}
3002
3003void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
3004{
3005 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
3006 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
3007
3008 args.ucEnable = enable;
3009
3010 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3011}
3012
3013uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
3014{
3015 GET_ENGINE_CLOCK_PS_ALLOCATION args;
3016 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
3017
3018 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3019 return le32_to_cpu(args.ulReturnEngineClock);
3020}
3021
3022uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
3023{
3024 GET_MEMORY_CLOCK_PS_ALLOCATION args;
3025 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
3026
3027 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3028 return le32_to_cpu(args.ulReturnMemoryClock);
3029}
3030
3031void radeon_atom_set_engine_clock(struct radeon_device *rdev,
3032 uint32_t eng_clock)
3033{
3034 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3035 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
3036
3037 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
3038
3039 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3040}
3041
3042void radeon_atom_set_memory_clock(struct radeon_device *rdev,
3043 uint32_t mem_clock)
3044{
3045 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3046 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
3047
3048 if (rdev->flags & RADEON_IS_IGP)
3049 return;
3050
3051 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
3052
3053 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3054}
3055
3056void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
3057 u32 eng_clock, u32 mem_clock)
3058{
3059 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3060 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3061 u32 tmp;
3062
3063 memset(&args, 0, sizeof(args));
3064
3065 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
3066 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
3067
3068 args.ulTargetEngineClock = cpu_to_le32(tmp);
3069 if (mem_clock)
3070 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
3071
3072 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3073}
3074
3075void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3076 u32 mem_clock)
3077{
3078 u32 args;
3079 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3080
3081 args = cpu_to_le32(mem_clock); /* 10 khz */
3082
3083 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3084}
3085
3086void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3087 u32 mem_clock)
3088{
3089 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3090 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3091 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
3092
3093 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */
3094
3095 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3096}
3097
3098union set_voltage {
3099 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
3100 struct _SET_VOLTAGE_PARAMETERS v1;
3101 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
3102 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
3103};
3104
3105void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3106{
3107 union set_voltage args;
3108 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3109 u8 frev, crev, volt_index = voltage_level;
3110
3111 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3112 return;
3113
3114 /* 0xff01 is a flag rather then an actual voltage */
3115 if (voltage_level == 0xff01)
3116 return;
3117
3118 switch (crev) {
3119 case 1:
3120 args.v1.ucVoltageType = voltage_type;
3121 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3122 args.v1.ucVoltageIndex = volt_index;
3123 break;
3124 case 2:
3125 args.v2.ucVoltageType = voltage_type;
3126 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3127 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3128 break;
3129 case 3:
3130 args.v3.ucVoltageType = voltage_type;
3131 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3132 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3133 break;
3134 default:
3135 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3136 return;
3137 }
3138
3139 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3140}
3141
3142int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3143 u16 voltage_id, u16 *voltage)
3144{
3145 union set_voltage args;
3146 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3147 u8 frev, crev;
3148
3149 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3150 return -EINVAL;
3151
3152 switch (crev) {
3153 case 1:
3154 return -EINVAL;
3155 case 2:
3156 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3157 args.v2.ucVoltageMode = 0;
3158 args.v2.usVoltageLevel = 0;
3159
3160 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3161
3162 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3163 break;
3164 case 3:
3165 args.v3.ucVoltageType = voltage_type;
3166 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3167 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3168
3169 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3170
3171 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3172 break;
3173 default:
3174 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3175 return -EINVAL;
3176 }
3177
3178 return 0;
3179}
3180
3181int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3182 u16 *voltage,
3183 u16 leakage_idx)
3184{
3185 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3186}
3187
3188int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3189 u16 *leakage_id)
3190{
3191 union set_voltage args;
3192 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3193 u8 frev, crev;
3194
3195 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3196 return -EINVAL;
3197
3198 switch (crev) {
3199 case 3:
3200 case 4:
3201 args.v3.ucVoltageType = 0;
3202 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
3203 args.v3.usVoltageLevel = 0;
3204
3205 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3206
3207 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
3208 break;
3209 default:
3210 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3211 return -EINVAL;
3212 }
3213
3214 return 0;
3215}
3216
3217int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3218 u16 *vddc, u16 *vddci,
3219 u16 virtual_voltage_id,
3220 u16 vbios_voltage_id)
3221{
3222 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
3223 u8 frev, crev;
3224 u16 data_offset, size;
3225 int i, j;
3226 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
3227 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
3228
3229 *vddc = 0;
3230 *vddci = 0;
3231
3232 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3233 &frev, &crev, &data_offset))
3234 return -EINVAL;
3235
3236 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
3237 (rdev->mode_info.atom_context->bios + data_offset);
3238
3239 switch (frev) {
3240 case 1:
3241 return -EINVAL;
3242 case 2:
3243 switch (crev) {
3244 case 1:
3245 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
3246 return -EINVAL;
3247 leakage_bin = (u16 *)
3248 (rdev->mode_info.atom_context->bios + data_offset +
3249 le16_to_cpu(profile->usLeakageBinArrayOffset));
3250 vddc_id_buf = (u16 *)
3251 (rdev->mode_info.atom_context->bios + data_offset +
3252 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
3253 vddc_buf = (u16 *)
3254 (rdev->mode_info.atom_context->bios + data_offset +
3255 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
3256 vddci_id_buf = (u16 *)
3257 (rdev->mode_info.atom_context->bios + data_offset +
3258 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
3259 vddci_buf = (u16 *)
3260 (rdev->mode_info.atom_context->bios + data_offset +
3261 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
3262
3263 if (profile->ucElbVDDC_Num > 0) {
3264 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
3265 if (vddc_id_buf[i] == virtual_voltage_id) {
3266 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3267 if (vbios_voltage_id <= leakage_bin[j]) {
3268 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
3269 break;
3270 }
3271 }
3272 break;
3273 }
3274 }
3275 }
3276 if (profile->ucElbVDDCI_Num > 0) {
3277 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
3278 if (vddci_id_buf[i] == virtual_voltage_id) {
3279 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3280 if (vbios_voltage_id <= leakage_bin[j]) {
3281 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
3282 break;
3283 }
3284 }
3285 break;
3286 }
3287 }
3288 }
3289 break;
3290 default:
3291 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3292 return -EINVAL;
3293 }
3294 break;
3295 default:
3296 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3297 return -EINVAL;
3298 }
3299
3300 return 0;
3301}
3302
3303union get_voltage_info {
3304 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
3305 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
3306};
3307
3308int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
3309 u16 virtual_voltage_id,
3310 u16 *voltage)
3311{
3312 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
3313 u32 entry_id;
3314 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
3315 union get_voltage_info args;
3316
3317 for (entry_id = 0; entry_id < count; entry_id++) {
3318 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
3319 virtual_voltage_id)
3320 break;
3321 }
3322
3323 if (entry_id >= count)
3324 return -EINVAL;
3325
3326 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
3327 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
3328 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
3329 args.in.ulSCLKFreq =
3330 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
3331
3332 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3333
3334 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
3335
3336 return 0;
3337}
3338
3339int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3340 u16 voltage_level, u8 voltage_type,
3341 u32 *gpio_value, u32 *gpio_mask)
3342{
3343 union set_voltage args;
3344 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3345 u8 frev, crev;
3346
3347 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3348 return -EINVAL;
3349
3350 switch (crev) {
3351 case 1:
3352 return -EINVAL;
3353 case 2:
3354 args.v2.ucVoltageType = voltage_type;
3355 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3356 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3357
3358 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3359
3360 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3361
3362 args.v2.ucVoltageType = voltage_type;
3363 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3364 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3365
3366 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3367
3368 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3369 break;
3370 default:
3371 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3372 return -EINVAL;
3373 }
3374
3375 return 0;
3376}
3377
3378union voltage_object_info {
3379 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3380 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3381 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3382};
3383
3384union voltage_object {
3385 struct _ATOM_VOLTAGE_OBJECT v1;
3386 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3387 union _ATOM_VOLTAGE_OBJECT_V3 v3;
3388};
3389
3390static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3391 u8 voltage_type)
3392{
3393 u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3394 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3395 u8 *start = (u8 *)v1;
3396
3397 while (offset < size) {
3398 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3399 if (vo->ucVoltageType == voltage_type)
3400 return vo;
3401 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3402 vo->asFormula.ucNumOfVoltageEntries;
3403 }
3404 return NULL;
3405}
3406
3407static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3408 u8 voltage_type)
3409{
3410 u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3411 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3412 u8 *start = (u8 *)v2;
3413
3414 while (offset < size) {
3415 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3416 if (vo->ucVoltageType == voltage_type)
3417 return vo;
3418 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3419 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3420 }
3421 return NULL;
3422}
3423
3424static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3425 u8 voltage_type, u8 voltage_mode)
3426{
3427 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3428 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3429 u8 *start = (u8 *)v3;
3430
3431 while (offset < size) {
3432 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3433 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3434 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3435 return vo;
3436 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3437 }
3438 return NULL;
3439}
3440
3441bool
3442radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3443 u8 voltage_type, u8 voltage_mode)
3444{
3445 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3446 u8 frev, crev;
3447 u16 data_offset, size;
3448 union voltage_object_info *voltage_info;
3449 union voltage_object *voltage_object = NULL;
3450
3451 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3452 &frev, &crev, &data_offset)) {
3453 voltage_info = (union voltage_object_info *)
3454 (rdev->mode_info.atom_context->bios + data_offset);
3455
3456 switch (frev) {
3457 case 1:
3458 case 2:
3459 switch (crev) {
3460 case 1:
3461 voltage_object = (union voltage_object *)
3462 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3463 if (voltage_object &&
3464 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3465 return true;
3466 break;
3467 case 2:
3468 voltage_object = (union voltage_object *)
3469 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3470 if (voltage_object &&
3471 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3472 return true;
3473 break;
3474 default:
3475 DRM_ERROR("unknown voltage object table\n");
3476 return false;
3477 }
3478 break;
3479 case 3:
3480 switch (crev) {
3481 case 1:
3482 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3483 voltage_type, voltage_mode))
3484 return true;
3485 break;
3486 default:
3487 DRM_ERROR("unknown voltage object table\n");
3488 return false;
3489 }
3490 break;
3491 default:
3492 DRM_ERROR("unknown voltage object table\n");
3493 return false;
3494 }
3495
3496 }
3497 return false;
3498}
3499
3500int radeon_atom_get_svi2_info(struct radeon_device *rdev,
3501 u8 voltage_type,
3502 u8 *svd_gpio_id, u8 *svc_gpio_id)
3503{
3504 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3505 u8 frev, crev;
3506 u16 data_offset, size;
3507 union voltage_object_info *voltage_info;
3508 union voltage_object *voltage_object = NULL;
3509
3510 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3511 &frev, &crev, &data_offset)) {
3512 voltage_info = (union voltage_object_info *)
3513 (rdev->mode_info.atom_context->bios + data_offset);
3514
3515 switch (frev) {
3516 case 3:
3517 switch (crev) {
3518 case 1:
3519 voltage_object = (union voltage_object *)
3520 atom_lookup_voltage_object_v3(&voltage_info->v3,
3521 voltage_type,
3522 VOLTAGE_OBJ_SVID2);
3523 if (voltage_object) {
3524 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
3525 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
3526 } else {
3527 return -EINVAL;
3528 }
3529 break;
3530 default:
3531 DRM_ERROR("unknown voltage object table\n");
3532 return -EINVAL;
3533 }
3534 break;
3535 default:
3536 DRM_ERROR("unknown voltage object table\n");
3537 return -EINVAL;
3538 }
3539
3540 }
3541 return 0;
3542}
3543
3544int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3545 u8 voltage_type, u16 *max_voltage)
3546{
3547 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3548 u8 frev, crev;
3549 u16 data_offset, size;
3550 union voltage_object_info *voltage_info;
3551 union voltage_object *voltage_object = NULL;
3552
3553 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3554 &frev, &crev, &data_offset)) {
3555 voltage_info = (union voltage_object_info *)
3556 (rdev->mode_info.atom_context->bios + data_offset);
3557
3558 switch (crev) {
3559 case 1:
3560 voltage_object = (union voltage_object *)
3561 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3562 if (voltage_object) {
3563 ATOM_VOLTAGE_FORMULA *formula =
3564 &voltage_object->v1.asFormula;
3565 if (formula->ucFlag & 1)
3566 *max_voltage =
3567 le16_to_cpu(formula->usVoltageBaseLevel) +
3568 formula->ucNumOfVoltageEntries / 2 *
3569 le16_to_cpu(formula->usVoltageStep);
3570 else
3571 *max_voltage =
3572 le16_to_cpu(formula->usVoltageBaseLevel) +
3573 (formula->ucNumOfVoltageEntries - 1) *
3574 le16_to_cpu(formula->usVoltageStep);
3575 return 0;
3576 }
3577 break;
3578 case 2:
3579 voltage_object = (union voltage_object *)
3580 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3581 if (voltage_object) {
3582 ATOM_VOLTAGE_FORMULA_V2 *formula =
3583 &voltage_object->v2.asFormula;
3584 if (formula->ucNumOfVoltageEntries) {
3585 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *)
3586 ((u8 *)&formula->asVIDAdjustEntries[0] +
3587 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
3588 *max_voltage =
3589 le16_to_cpu(lut->usVoltageValue);
3590 return 0;
3591 }
3592 }
3593 break;
3594 default:
3595 DRM_ERROR("unknown voltage object table\n");
3596 return -EINVAL;
3597 }
3598
3599 }
3600 return -EINVAL;
3601}
3602
3603int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3604 u8 voltage_type, u16 *min_voltage)
3605{
3606 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3607 u8 frev, crev;
3608 u16 data_offset, size;
3609 union voltage_object_info *voltage_info;
3610 union voltage_object *voltage_object = NULL;
3611
3612 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3613 &frev, &crev, &data_offset)) {
3614 voltage_info = (union voltage_object_info *)
3615 (rdev->mode_info.atom_context->bios + data_offset);
3616
3617 switch (crev) {
3618 case 1:
3619 voltage_object = (union voltage_object *)
3620 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3621 if (voltage_object) {
3622 ATOM_VOLTAGE_FORMULA *formula =
3623 &voltage_object->v1.asFormula;
3624 *min_voltage =
3625 le16_to_cpu(formula->usVoltageBaseLevel);
3626 return 0;
3627 }
3628 break;
3629 case 2:
3630 voltage_object = (union voltage_object *)
3631 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3632 if (voltage_object) {
3633 ATOM_VOLTAGE_FORMULA_V2 *formula =
3634 &voltage_object->v2.asFormula;
3635 if (formula->ucNumOfVoltageEntries) {
3636 *min_voltage =
3637 le16_to_cpu(formula->asVIDAdjustEntries[
3638 0
3639 ].usVoltageValue);
3640 return 0;
3641 }
3642 }
3643 break;
3644 default:
3645 DRM_ERROR("unknown voltage object table\n");
3646 return -EINVAL;
3647 }
3648
3649 }
3650 return -EINVAL;
3651}
3652
3653int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3654 u8 voltage_type, u16 *voltage_step)
3655{
3656 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3657 u8 frev, crev;
3658 u16 data_offset, size;
3659 union voltage_object_info *voltage_info;
3660 union voltage_object *voltage_object = NULL;
3661
3662 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3663 &frev, &crev, &data_offset)) {
3664 voltage_info = (union voltage_object_info *)
3665 (rdev->mode_info.atom_context->bios + data_offset);
3666
3667 switch (crev) {
3668 case 1:
3669 voltage_object = (union voltage_object *)
3670 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3671 if (voltage_object) {
3672 ATOM_VOLTAGE_FORMULA *formula =
3673 &voltage_object->v1.asFormula;
3674 if (formula->ucFlag & 1)
3675 *voltage_step =
3676 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3677 else
3678 *voltage_step =
3679 le16_to_cpu(formula->usVoltageStep);
3680 return 0;
3681 }
3682 break;
3683 case 2:
3684 return -EINVAL;
3685 default:
3686 DRM_ERROR("unknown voltage object table\n");
3687 return -EINVAL;
3688 }
3689
3690 }
3691 return -EINVAL;
3692}
3693
3694int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3695 u8 voltage_type,
3696 u16 nominal_voltage,
3697 u16 *true_voltage)
3698{
3699 u16 min_voltage, max_voltage, voltage_step;
3700
3701 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3702 return -EINVAL;
3703 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3704 return -EINVAL;
3705 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3706 return -EINVAL;
3707
3708 if (nominal_voltage <= min_voltage)
3709 *true_voltage = min_voltage;
3710 else if (nominal_voltage >= max_voltage)
3711 *true_voltage = max_voltage;
3712 else
3713 *true_voltage = min_voltage +
3714 ((nominal_voltage - min_voltage) / voltage_step) *
3715 voltage_step;
3716
3717 return 0;
3718}
3719
3720int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3721 u8 voltage_type, u8 voltage_mode,
3722 struct atom_voltage_table *voltage_table)
3723{
3724 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3725 u8 frev, crev;
3726 u16 data_offset, size;
3727 int i, ret;
3728 union voltage_object_info *voltage_info;
3729 union voltage_object *voltage_object = NULL;
3730
3731 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3732 &frev, &crev, &data_offset)) {
3733 voltage_info = (union voltage_object_info *)
3734 (rdev->mode_info.atom_context->bios + data_offset);
3735
3736 switch (frev) {
3737 case 1:
3738 case 2:
3739 switch (crev) {
3740 case 1:
3741 DRM_ERROR("old table version %d, %d\n", frev, crev);
3742 return -EINVAL;
3743 case 2:
3744 voltage_object = (union voltage_object *)
3745 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3746 if (voltage_object) {
3747 ATOM_VOLTAGE_FORMULA_V2 *formula =
3748 &voltage_object->v2.asFormula;
3749 VOLTAGE_LUT_ENTRY *lut;
3750 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3751 return -EINVAL;
3752 lut = &formula->asVIDAdjustEntries[0];
3753 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3754 voltage_table->entries[i].value =
3755 le16_to_cpu(lut->usVoltageValue);
3756 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3757 voltage_table->entries[i].value,
3758 voltage_type,
3759 &voltage_table->entries[i].smio_low,
3760 &voltage_table->mask_low);
3761 if (ret)
3762 return ret;
3763 lut = (VOLTAGE_LUT_ENTRY *)
3764 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
3765 }
3766 voltage_table->count = formula->ucNumOfVoltageEntries;
3767 return 0;
3768 }
3769 break;
3770 default:
3771 DRM_ERROR("unknown voltage object table\n");
3772 return -EINVAL;
3773 }
3774 break;
3775 case 3:
3776 switch (crev) {
3777 case 1:
3778 voltage_object = (union voltage_object *)
3779 atom_lookup_voltage_object_v3(&voltage_info->v3,
3780 voltage_type, voltage_mode);
3781 if (voltage_object) {
3782 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3783 &voltage_object->v3.asGpioVoltageObj;
3784 VOLTAGE_LUT_ENTRY_V2 *lut;
3785 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3786 return -EINVAL;
3787 lut = &gpio->asVolGpioLut[0];
3788 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3789 voltage_table->entries[i].value =
3790 le16_to_cpu(lut->usVoltageValue);
3791 voltage_table->entries[i].smio_low =
3792 le32_to_cpu(lut->ulVoltageId);
3793 lut = (VOLTAGE_LUT_ENTRY_V2 *)
3794 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
3795 }
3796 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3797 voltage_table->count = gpio->ucGpioEntryNum;
3798 voltage_table->phase_delay = gpio->ucPhaseDelay;
3799 return 0;
3800 }
3801 break;
3802 default:
3803 DRM_ERROR("unknown voltage object table\n");
3804 return -EINVAL;
3805 }
3806 break;
3807 default:
3808 DRM_ERROR("unknown voltage object table\n");
3809 return -EINVAL;
3810 }
3811 }
3812 return -EINVAL;
3813}
3814
3815union vram_info {
3816 struct _ATOM_VRAM_INFO_V3 v1_3;
3817 struct _ATOM_VRAM_INFO_V4 v1_4;
3818 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3819};
3820
3821int radeon_atom_get_memory_info(struct radeon_device *rdev,
3822 u8 module_index, struct atom_memory_info *mem_info)
3823{
3824 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3825 u8 frev, crev, i;
3826 u16 data_offset, size;
3827 union vram_info *vram_info;
3828
3829 memset(mem_info, 0, sizeof(struct atom_memory_info));
3830
3831 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3832 &frev, &crev, &data_offset)) {
3833 vram_info = (union vram_info *)
3834 (rdev->mode_info.atom_context->bios + data_offset);
3835 switch (frev) {
3836 case 1:
3837 switch (crev) {
3838 case 3:
3839 /* r6xx */
3840 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3841 ATOM_VRAM_MODULE_V3 *vram_module =
3842 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3843
3844 for (i = 0; i < module_index; i++) {
3845 if (le16_to_cpu(vram_module->usSize) == 0)
3846 return -EINVAL;
3847 vram_module = (ATOM_VRAM_MODULE_V3 *)
3848 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3849 }
3850 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3851 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3852 } else
3853 return -EINVAL;
3854 break;
3855 case 4:
3856 /* r7xx, evergreen */
3857 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3858 ATOM_VRAM_MODULE_V4 *vram_module =
3859 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3860
3861 for (i = 0; i < module_index; i++) {
3862 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3863 return -EINVAL;
3864 vram_module = (ATOM_VRAM_MODULE_V4 *)
3865 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3866 }
3867 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3868 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3869 } else
3870 return -EINVAL;
3871 break;
3872 default:
3873 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3874 return -EINVAL;
3875 }
3876 break;
3877 case 2:
3878 switch (crev) {
3879 case 1:
3880 /* ni */
3881 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3882 ATOM_VRAM_MODULE_V7 *vram_module =
3883 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3884
3885 for (i = 0; i < module_index; i++) {
3886 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3887 return -EINVAL;
3888 vram_module = (ATOM_VRAM_MODULE_V7 *)
3889 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3890 }
3891 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3892 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3893 } else
3894 return -EINVAL;
3895 break;
3896 default:
3897 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3898 return -EINVAL;
3899 }
3900 break;
3901 default:
3902 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3903 return -EINVAL;
3904 }
3905 return 0;
3906 }
3907 return -EINVAL;
3908}
3909
3910int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3911 bool gddr5, u8 module_index,
3912 struct atom_memory_clock_range_table *mclk_range_table)
3913{
3914 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3915 u8 frev, crev, i;
3916 u16 data_offset, size;
3917 union vram_info *vram_info;
3918 u32 mem_timing_size = gddr5 ?
3919 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3920
3921 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3922
3923 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3924 &frev, &crev, &data_offset)) {
3925 vram_info = (union vram_info *)
3926 (rdev->mode_info.atom_context->bios + data_offset);
3927 switch (frev) {
3928 case 1:
3929 switch (crev) {
3930 case 3:
3931 DRM_ERROR("old table version %d, %d\n", frev, crev);
3932 return -EINVAL;
3933 case 4:
3934 /* r7xx, evergreen */
3935 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3936 ATOM_VRAM_MODULE_V4 *vram_module =
3937 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3938 ATOM_MEMORY_TIMING_FORMAT *format;
3939
3940 for (i = 0; i < module_index; i++) {
3941 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3942 return -EINVAL;
3943 vram_module = (ATOM_VRAM_MODULE_V4 *)
3944 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3945 }
3946 mclk_range_table->num_entries = (u8)
3947 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3948 mem_timing_size);
3949 format = &vram_module->asMemTiming[0];
3950 for (i = 0; i < mclk_range_table->num_entries; i++) {
3951 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3952 format = (ATOM_MEMORY_TIMING_FORMAT *)
3953 ((u8 *)format + mem_timing_size);
3954 }
3955 } else
3956 return -EINVAL;
3957 break;
3958 default:
3959 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3960 return -EINVAL;
3961 }
3962 break;
3963 case 2:
3964 DRM_ERROR("new table version %d, %d\n", frev, crev);
3965 return -EINVAL;
3966 default:
3967 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3968 return -EINVAL;
3969 }
3970 return 0;
3971 }
3972 return -EINVAL;
3973}
3974
3975#define MEM_ID_MASK 0xff000000
3976#define MEM_ID_SHIFT 24
3977#define CLOCK_RANGE_MASK 0x00ffffff
3978#define CLOCK_RANGE_SHIFT 0
3979#define LOW_NIBBLE_MASK 0xf
3980#define DATA_EQU_PREV 0
3981#define DATA_FROM_TABLE 4
3982
3983int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3984 u8 module_index,
3985 struct atom_mc_reg_table *reg_table)
3986{
3987 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3988 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3989 u32 i = 0, j;
3990 u16 data_offset, size;
3991 union vram_info *vram_info;
3992
3993 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
3994
3995 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3996 &frev, &crev, &data_offset)) {
3997 vram_info = (union vram_info *)
3998 (rdev->mode_info.atom_context->bios + data_offset);
3999 switch (frev) {
4000 case 1:
4001 DRM_ERROR("old table version %d, %d\n", frev, crev);
4002 return -EINVAL;
4003 case 2:
4004 switch (crev) {
4005 case 1:
4006 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
4007 ATOM_INIT_REG_BLOCK *reg_block =
4008 (ATOM_INIT_REG_BLOCK *)
4009 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
4010 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
4011 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4012 ((u8 *)reg_block + (2 * sizeof(u16)) +
4013 le16_to_cpu(reg_block->usRegIndexTblSize));
4014 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
4015 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
4016 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
4017 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
4018 return -EINVAL;
4019 while (i < num_entries) {
4020 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
4021 break;
4022 reg_table->mc_reg_address[i].s1 =
4023 (u16)(le16_to_cpu(format->usRegIndex));
4024 reg_table->mc_reg_address[i].pre_reg_data =
4025 (u8)(format->ucPreRegDataLength);
4026 i++;
4027 format = (ATOM_INIT_REG_INDEX_FORMAT *)
4028 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
4029 }
4030 reg_table->last = i;
4031 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
4032 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
4033 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
4034 >> MEM_ID_SHIFT);
4035 if (module_index == t_mem_id) {
4036 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
4037 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
4038 >> CLOCK_RANGE_SHIFT);
4039 for (i = 0, j = 1; i < reg_table->last; i++) {
4040 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
4041 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4042 (u32)le32_to_cpu(*((u32 *)reg_data + j));
4043 j++;
4044 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
4045 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4046 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
4047 }
4048 }
4049 num_ranges++;
4050 }
4051 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4052 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
4053 }
4054 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
4055 return -EINVAL;
4056 reg_table->num_entries = num_ranges;
4057 } else
4058 return -EINVAL;
4059 break;
4060 default:
4061 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4062 return -EINVAL;
4063 }
4064 break;
4065 default:
4066 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4067 return -EINVAL;
4068 }
4069 return 0;
4070 }
4071 return -EINVAL;
4072}
4073
4074void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
4075{
4076 struct radeon_device *rdev = dev->dev_private;
4077 uint32_t bios_2_scratch, bios_6_scratch;
4078
4079 if (rdev->family >= CHIP_R600) {
4080 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4081 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4082 } else {
4083 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4084 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4085 }
4086
4087 /* let the bios control the backlight */
4088 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
4089
4090 /* tell the bios not to handle mode switching */
4091 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
4092
4093 /* clear the vbios dpms state */
4094 if (ASIC_IS_DCE4(rdev))
4095 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
4096
4097 if (rdev->family >= CHIP_R600) {
4098 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4099 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4100 } else {
4101 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4102 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4103 }
4104
4105}
4106
4107void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
4108{
4109 uint32_t scratch_reg;
4110 int i;
4111
4112 if (rdev->family >= CHIP_R600)
4113 scratch_reg = R600_BIOS_0_SCRATCH;
4114 else
4115 scratch_reg = RADEON_BIOS_0_SCRATCH;
4116
4117 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4118 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
4119}
4120
4121void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
4122{
4123 uint32_t scratch_reg;
4124 int i;
4125
4126 if (rdev->family >= CHIP_R600)
4127 scratch_reg = R600_BIOS_0_SCRATCH;
4128 else
4129 scratch_reg = RADEON_BIOS_0_SCRATCH;
4130
4131 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4132 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
4133}
4134
4135void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
4136{
4137 struct drm_device *dev = encoder->dev;
4138 struct radeon_device *rdev = dev->dev_private;
4139 uint32_t bios_6_scratch;
4140
4141 if (rdev->family >= CHIP_R600)
4142 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4143 else
4144 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4145
4146 if (lock) {
4147 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
4148 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
4149 } else {
4150 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
4151 bios_6_scratch |= ATOM_S6_ACC_MODE;
4152 }
4153
4154 if (rdev->family >= CHIP_R600)
4155 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4156 else
4157 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4158}
4159
4160/* at some point we may want to break this out into individual functions */
4161void
4162radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
4163 struct drm_encoder *encoder,
4164 bool connected)
4165{
4166 struct drm_device *dev = connector->dev;
4167 struct radeon_device *rdev = dev->dev_private;
4168 struct radeon_connector *radeon_connector =
4169 to_radeon_connector(connector);
4170 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4171 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
4172
4173 if (rdev->family >= CHIP_R600) {
4174 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
4175 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4176 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4177 } else {
4178 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
4179 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4180 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4181 }
4182
4183 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
4184 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
4185 if (connected) {
4186 DRM_DEBUG_KMS("TV1 connected\n");
4187 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
4188 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
4189 } else {
4190 DRM_DEBUG_KMS("TV1 disconnected\n");
4191 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
4192 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
4193 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
4194 }
4195 }
4196 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
4197 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
4198 if (connected) {
4199 DRM_DEBUG_KMS("CV connected\n");
4200 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
4201 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
4202 } else {
4203 DRM_DEBUG_KMS("CV disconnected\n");
4204 bios_0_scratch &= ~ATOM_S0_CV_MASK;
4205 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
4206 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
4207 }
4208 }
4209 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
4210 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
4211 if (connected) {
4212 DRM_DEBUG_KMS("LCD1 connected\n");
4213 bios_0_scratch |= ATOM_S0_LCD1;
4214 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
4215 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
4216 } else {
4217 DRM_DEBUG_KMS("LCD1 disconnected\n");
4218 bios_0_scratch &= ~ATOM_S0_LCD1;
4219 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
4220 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
4221 }
4222 }
4223 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
4224 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
4225 if (connected) {
4226 DRM_DEBUG_KMS("CRT1 connected\n");
4227 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
4228 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
4229 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
4230 } else {
4231 DRM_DEBUG_KMS("CRT1 disconnected\n");
4232 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
4233 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
4234 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
4235 }
4236 }
4237 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
4238 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
4239 if (connected) {
4240 DRM_DEBUG_KMS("CRT2 connected\n");
4241 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
4242 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
4243 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
4244 } else {
4245 DRM_DEBUG_KMS("CRT2 disconnected\n");
4246 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
4247 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
4248 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
4249 }
4250 }
4251 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
4252 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
4253 if (connected) {
4254 DRM_DEBUG_KMS("DFP1 connected\n");
4255 bios_0_scratch |= ATOM_S0_DFP1;
4256 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
4257 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
4258 } else {
4259 DRM_DEBUG_KMS("DFP1 disconnected\n");
4260 bios_0_scratch &= ~ATOM_S0_DFP1;
4261 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
4262 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
4263 }
4264 }
4265 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
4266 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
4267 if (connected) {
4268 DRM_DEBUG_KMS("DFP2 connected\n");
4269 bios_0_scratch |= ATOM_S0_DFP2;
4270 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
4271 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
4272 } else {
4273 DRM_DEBUG_KMS("DFP2 disconnected\n");
4274 bios_0_scratch &= ~ATOM_S0_DFP2;
4275 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
4276 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
4277 }
4278 }
4279 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
4280 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
4281 if (connected) {
4282 DRM_DEBUG_KMS("DFP3 connected\n");
4283 bios_0_scratch |= ATOM_S0_DFP3;
4284 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
4285 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
4286 } else {
4287 DRM_DEBUG_KMS("DFP3 disconnected\n");
4288 bios_0_scratch &= ~ATOM_S0_DFP3;
4289 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
4290 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
4291 }
4292 }
4293 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
4294 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
4295 if (connected) {
4296 DRM_DEBUG_KMS("DFP4 connected\n");
4297 bios_0_scratch |= ATOM_S0_DFP4;
4298 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
4299 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
4300 } else {
4301 DRM_DEBUG_KMS("DFP4 disconnected\n");
4302 bios_0_scratch &= ~ATOM_S0_DFP4;
4303 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
4304 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
4305 }
4306 }
4307 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
4308 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
4309 if (connected) {
4310 DRM_DEBUG_KMS("DFP5 connected\n");
4311 bios_0_scratch |= ATOM_S0_DFP5;
4312 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
4313 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
4314 } else {
4315 DRM_DEBUG_KMS("DFP5 disconnected\n");
4316 bios_0_scratch &= ~ATOM_S0_DFP5;
4317 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
4318 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
4319 }
4320 }
4321 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4322 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4323 if (connected) {
4324 DRM_DEBUG_KMS("DFP6 connected\n");
4325 bios_0_scratch |= ATOM_S0_DFP6;
4326 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4327 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4328 } else {
4329 DRM_DEBUG_KMS("DFP6 disconnected\n");
4330 bios_0_scratch &= ~ATOM_S0_DFP6;
4331 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4332 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4333 }
4334 }
4335
4336 if (rdev->family >= CHIP_R600) {
4337 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4338 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4339 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4340 } else {
4341 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4342 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4343 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4344 }
4345}
4346
4347void
4348radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4349{
4350 struct drm_device *dev = encoder->dev;
4351 struct radeon_device *rdev = dev->dev_private;
4352 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4353 uint32_t bios_3_scratch;
4354
4355 if (ASIC_IS_DCE4(rdev))
4356 return;
4357
4358 if (rdev->family >= CHIP_R600)
4359 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4360 else
4361 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4362
4363 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4364 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4365 bios_3_scratch |= (crtc << 18);
4366 }
4367 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4368 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4369 bios_3_scratch |= (crtc << 24);
4370 }
4371 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4372 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4373 bios_3_scratch |= (crtc << 16);
4374 }
4375 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4376 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4377 bios_3_scratch |= (crtc << 20);
4378 }
4379 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4380 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4381 bios_3_scratch |= (crtc << 17);
4382 }
4383 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4384 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4385 bios_3_scratch |= (crtc << 19);
4386 }
4387 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4388 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4389 bios_3_scratch |= (crtc << 23);
4390 }
4391 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4392 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4393 bios_3_scratch |= (crtc << 25);
4394 }
4395
4396 if (rdev->family >= CHIP_R600)
4397 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4398 else
4399 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4400}
4401
4402void
4403radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4404{
4405 struct drm_device *dev = encoder->dev;
4406 struct radeon_device *rdev = dev->dev_private;
4407 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4408 uint32_t bios_2_scratch;
4409
4410 if (ASIC_IS_DCE4(rdev))
4411 return;
4412
4413 if (rdev->family >= CHIP_R600)
4414 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4415 else
4416 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4417
4418 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4419 if (on)
4420 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4421 else
4422 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4423 }
4424 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4425 if (on)
4426 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4427 else
4428 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4429 }
4430 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4431 if (on)
4432 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4433 else
4434 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4435 }
4436 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4437 if (on)
4438 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4439 else
4440 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4441 }
4442 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4443 if (on)
4444 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4445 else
4446 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4447 }
4448 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4449 if (on)
4450 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4451 else
4452 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4453 }
4454 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4455 if (on)
4456 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4457 else
4458 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4459 }
4460 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4461 if (on)
4462 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4463 else
4464 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4465 }
4466 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4467 if (on)
4468 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4469 else
4470 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4471 }
4472 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4473 if (on)
4474 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4475 else
4476 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4477 }
4478
4479 if (rdev->family >= CHIP_R600)
4480 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4481 else
4482 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4483}
1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/radeon_drm.h>
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33extern void
34radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
35 uint32_t supported_device, u16 caps);
36
37/* from radeon_legacy_encoder.c */
38extern void
39radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device);
41
42union atom_supported_devices {
43 struct _ATOM_SUPPORTED_DEVICES_INFO info;
44 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
45 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
46};
47
48static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
49 ATOM_GPIO_I2C_ASSIGMENT *gpio,
50 u8 index)
51{
52 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
53 if ((rdev->family == CHIP_R420) ||
54 (rdev->family == CHIP_R423) ||
55 (rdev->family == CHIP_RV410)) {
56 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
57 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
58 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
59 gpio->ucClkMaskShift = 0x19;
60 gpio->ucDataMaskShift = 0x18;
61 }
62 }
63
64 /* some evergreen boards have bad data for this entry */
65 if (ASIC_IS_DCE4(rdev)) {
66 if ((index == 7) &&
67 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
68 (gpio->sucI2cId.ucAccess == 0)) {
69 gpio->sucI2cId.ucAccess = 0x97;
70 gpio->ucDataMaskShift = 8;
71 gpio->ucDataEnShift = 8;
72 gpio->ucDataY_Shift = 8;
73 gpio->ucDataA_Shift = 8;
74 }
75 }
76
77 /* some DCE3 boards have bad data for this entry */
78 if (ASIC_IS_DCE3(rdev)) {
79 if ((index == 4) &&
80 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
81 (gpio->sucI2cId.ucAccess == 0x94))
82 gpio->sucI2cId.ucAccess = 0x14;
83 }
84}
85
86static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
87{
88 struct radeon_i2c_bus_rec i2c;
89
90 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
91
92 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
93 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
94 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
95 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
96 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
97 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
98 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
99 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
100 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
101 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
102 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
103 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
104 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
105 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
106 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
107 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
108
109 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
110 i2c.hw_capable = true;
111 else
112 i2c.hw_capable = false;
113
114 if (gpio->sucI2cId.ucAccess == 0xa0)
115 i2c.mm_i2c = true;
116 else
117 i2c.mm_i2c = false;
118
119 i2c.i2c_id = gpio->sucI2cId.ucAccess;
120
121 if (i2c.mask_clk_reg)
122 i2c.valid = true;
123 else
124 i2c.valid = false;
125
126 return i2c;
127}
128
129static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
130 uint8_t id)
131{
132 struct atom_context *ctx = rdev->mode_info.atom_context;
133 ATOM_GPIO_I2C_ASSIGMENT *gpio;
134 struct radeon_i2c_bus_rec i2c;
135 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
136 struct _ATOM_GPIO_I2C_INFO *i2c_info;
137 uint16_t data_offset, size;
138 int i, num_indices;
139
140 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
141 i2c.valid = false;
142
143 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
144 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
145
146 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
147 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
148
149 gpio = &i2c_info->asGPIO_Info[0];
150 for (i = 0; i < num_indices; i++) {
151
152 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
153
154 if (gpio->sucI2cId.ucAccess == id) {
155 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
156 break;
157 }
158 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
159 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
160 }
161 }
162
163 return i2c;
164}
165
166void radeon_atombios_i2c_init(struct radeon_device *rdev)
167{
168 struct atom_context *ctx = rdev->mode_info.atom_context;
169 ATOM_GPIO_I2C_ASSIGMENT *gpio;
170 struct radeon_i2c_bus_rec i2c;
171 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
172 struct _ATOM_GPIO_I2C_INFO *i2c_info;
173 uint16_t data_offset, size;
174 int i, num_indices;
175 char stmp[32];
176
177 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
178 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
179
180 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
181 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
182
183 gpio = &i2c_info->asGPIO_Info[0];
184 for (i = 0; i < num_indices; i++) {
185 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
186
187 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
188
189 if (i2c.valid) {
190 sprintf(stmp, "0x%x", i2c.i2c_id);
191 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
192 }
193 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
194 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
195 }
196 }
197}
198
199struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
200 u8 id)
201{
202 struct atom_context *ctx = rdev->mode_info.atom_context;
203 struct radeon_gpio_rec gpio;
204 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
205 struct _ATOM_GPIO_PIN_LUT *gpio_info;
206 ATOM_GPIO_PIN_ASSIGNMENT *pin;
207 u16 data_offset, size;
208 int i, num_indices;
209
210 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
211 gpio.valid = false;
212
213 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
214 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
215
216 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
217 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
218
219 pin = gpio_info->asGPIO_Pin;
220 for (i = 0; i < num_indices; i++) {
221 if (id == pin->ucGPIO_ID) {
222 gpio.id = pin->ucGPIO_ID;
223 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
224 gpio.shift = pin->ucGpioPinBitShift;
225 gpio.mask = (1 << pin->ucGpioPinBitShift);
226 gpio.valid = true;
227 break;
228 }
229 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
230 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
231 }
232 }
233
234 return gpio;
235}
236
237static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
238 struct radeon_gpio_rec *gpio)
239{
240 struct radeon_hpd hpd;
241 u32 reg;
242
243 memset(&hpd, 0, sizeof(struct radeon_hpd));
244
245 if (ASIC_IS_DCE6(rdev))
246 reg = SI_DC_GPIO_HPD_A;
247 else if (ASIC_IS_DCE4(rdev))
248 reg = EVERGREEN_DC_GPIO_HPD_A;
249 else
250 reg = AVIVO_DC_GPIO_HPD_A;
251
252 hpd.gpio = *gpio;
253 if (gpio->reg == reg) {
254 switch(gpio->mask) {
255 case (1 << 0):
256 hpd.hpd = RADEON_HPD_1;
257 break;
258 case (1 << 8):
259 hpd.hpd = RADEON_HPD_2;
260 break;
261 case (1 << 16):
262 hpd.hpd = RADEON_HPD_3;
263 break;
264 case (1 << 24):
265 hpd.hpd = RADEON_HPD_4;
266 break;
267 case (1 << 26):
268 hpd.hpd = RADEON_HPD_5;
269 break;
270 case (1 << 28):
271 hpd.hpd = RADEON_HPD_6;
272 break;
273 default:
274 hpd.hpd = RADEON_HPD_NONE;
275 break;
276 }
277 } else
278 hpd.hpd = RADEON_HPD_NONE;
279 return hpd;
280}
281
282static bool radeon_atom_apply_quirks(struct drm_device *dev,
283 uint32_t supported_device,
284 int *connector_type,
285 struct radeon_i2c_bus_rec *i2c_bus,
286 uint16_t *line_mux,
287 struct radeon_hpd *hpd)
288{
289
290 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
291 if ((dev->pdev->device == 0x791e) &&
292 (dev->pdev->subsystem_vendor == 0x1043) &&
293 (dev->pdev->subsystem_device == 0x826d)) {
294 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
295 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
296 *connector_type = DRM_MODE_CONNECTOR_DVID;
297 }
298
299 /* Asrock RS600 board lists the DVI port as HDMI */
300 if ((dev->pdev->device == 0x7941) &&
301 (dev->pdev->subsystem_vendor == 0x1849) &&
302 (dev->pdev->subsystem_device == 0x7941)) {
303 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
304 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
305 *connector_type = DRM_MODE_CONNECTOR_DVID;
306 }
307
308 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
309 if ((dev->pdev->device == 0x796e) &&
310 (dev->pdev->subsystem_vendor == 0x1462) &&
311 (dev->pdev->subsystem_device == 0x7302)) {
312 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
313 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
314 return false;
315 }
316
317 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
318 if ((dev->pdev->device == 0x7941) &&
319 (dev->pdev->subsystem_vendor == 0x147b) &&
320 (dev->pdev->subsystem_device == 0x2412)) {
321 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
322 return false;
323 }
324
325 /* Falcon NW laptop lists vga ddc line for LVDS */
326 if ((dev->pdev->device == 0x5653) &&
327 (dev->pdev->subsystem_vendor == 0x1462) &&
328 (dev->pdev->subsystem_device == 0x0291)) {
329 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
330 i2c_bus->valid = false;
331 *line_mux = 53;
332 }
333 }
334
335 /* HIS X1300 is DVI+VGA, not DVI+DVI */
336 if ((dev->pdev->device == 0x7146) &&
337 (dev->pdev->subsystem_vendor == 0x17af) &&
338 (dev->pdev->subsystem_device == 0x2058)) {
339 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
340 return false;
341 }
342
343 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
344 if ((dev->pdev->device == 0x7142) &&
345 (dev->pdev->subsystem_vendor == 0x1458) &&
346 (dev->pdev->subsystem_device == 0x2134)) {
347 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
348 return false;
349 }
350
351
352 /* Funky macbooks */
353 if ((dev->pdev->device == 0x71C5) &&
354 (dev->pdev->subsystem_vendor == 0x106b) &&
355 (dev->pdev->subsystem_device == 0x0080)) {
356 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
357 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
358 return false;
359 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
360 *line_mux = 0x90;
361 }
362
363 /* mac rv630, rv730, others */
364 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
365 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
366 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
367 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
368 }
369
370 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
371 if ((dev->pdev->device == 0x9598) &&
372 (dev->pdev->subsystem_vendor == 0x1043) &&
373 (dev->pdev->subsystem_device == 0x01da)) {
374 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
375 *connector_type = DRM_MODE_CONNECTOR_DVII;
376 }
377 }
378
379 /* ASUS HD 3600 board lists the DVI port as HDMI */
380 if ((dev->pdev->device == 0x9598) &&
381 (dev->pdev->subsystem_vendor == 0x1043) &&
382 (dev->pdev->subsystem_device == 0x01e4)) {
383 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
384 *connector_type = DRM_MODE_CONNECTOR_DVII;
385 }
386 }
387
388 /* ASUS HD 3450 board lists the DVI port as HDMI */
389 if ((dev->pdev->device == 0x95C5) &&
390 (dev->pdev->subsystem_vendor == 0x1043) &&
391 (dev->pdev->subsystem_device == 0x01e2)) {
392 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
393 *connector_type = DRM_MODE_CONNECTOR_DVII;
394 }
395 }
396
397 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
398 * HDMI + VGA reporting as HDMI
399 */
400 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
401 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
402 *connector_type = DRM_MODE_CONNECTOR_VGA;
403 *line_mux = 0;
404 }
405 }
406
407 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
408 * on the laptop and a DVI port on the docking station and
409 * both share the same encoder, hpd pin, and ddc line.
410 * So while the bios table is technically correct,
411 * we drop the DVI port here since xrandr has no concept of
412 * encoders and will try and drive both connectors
413 * with different crtcs which isn't possible on the hardware
414 * side and leaves no crtcs for LVDS or VGA.
415 */
416 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
417 (dev->pdev->subsystem_vendor == 0x1025) &&
418 (dev->pdev->subsystem_device == 0x013c)) {
419 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
420 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
421 /* actually it's a DVI-D port not DVI-I */
422 *connector_type = DRM_MODE_CONNECTOR_DVID;
423 return false;
424 }
425 }
426
427 /* XFX Pine Group device rv730 reports no VGA DDC lines
428 * even though they are wired up to record 0x93
429 */
430 if ((dev->pdev->device == 0x9498) &&
431 (dev->pdev->subsystem_vendor == 0x1682) &&
432 (dev->pdev->subsystem_device == 0x2452) &&
433 (i2c_bus->valid == false) &&
434 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
435 struct radeon_device *rdev = dev->dev_private;
436 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
437 }
438
439 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
440 if (((dev->pdev->device == 0x9802) ||
441 (dev->pdev->device == 0x9805) ||
442 (dev->pdev->device == 0x9806)) &&
443 (dev->pdev->subsystem_vendor == 0x1734) &&
444 (dev->pdev->subsystem_device == 0x11bd)) {
445 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
446 *connector_type = DRM_MODE_CONNECTOR_DVII;
447 *line_mux = 0x3103;
448 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
449 *connector_type = DRM_MODE_CONNECTOR_DVII;
450 }
451 }
452
453 return true;
454}
455
456static const int supported_devices_connector_convert[] = {
457 DRM_MODE_CONNECTOR_Unknown,
458 DRM_MODE_CONNECTOR_VGA,
459 DRM_MODE_CONNECTOR_DVII,
460 DRM_MODE_CONNECTOR_DVID,
461 DRM_MODE_CONNECTOR_DVIA,
462 DRM_MODE_CONNECTOR_SVIDEO,
463 DRM_MODE_CONNECTOR_Composite,
464 DRM_MODE_CONNECTOR_LVDS,
465 DRM_MODE_CONNECTOR_Unknown,
466 DRM_MODE_CONNECTOR_Unknown,
467 DRM_MODE_CONNECTOR_HDMIA,
468 DRM_MODE_CONNECTOR_HDMIB,
469 DRM_MODE_CONNECTOR_Unknown,
470 DRM_MODE_CONNECTOR_Unknown,
471 DRM_MODE_CONNECTOR_9PinDIN,
472 DRM_MODE_CONNECTOR_DisplayPort
473};
474
475static const uint16_t supported_devices_connector_object_id_convert[] = {
476 CONNECTOR_OBJECT_ID_NONE,
477 CONNECTOR_OBJECT_ID_VGA,
478 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
479 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
480 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
481 CONNECTOR_OBJECT_ID_COMPOSITE,
482 CONNECTOR_OBJECT_ID_SVIDEO,
483 CONNECTOR_OBJECT_ID_LVDS,
484 CONNECTOR_OBJECT_ID_9PIN_DIN,
485 CONNECTOR_OBJECT_ID_9PIN_DIN,
486 CONNECTOR_OBJECT_ID_DISPLAYPORT,
487 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
488 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
489 CONNECTOR_OBJECT_ID_SVIDEO
490};
491
492static const int object_connector_convert[] = {
493 DRM_MODE_CONNECTOR_Unknown,
494 DRM_MODE_CONNECTOR_DVII,
495 DRM_MODE_CONNECTOR_DVII,
496 DRM_MODE_CONNECTOR_DVID,
497 DRM_MODE_CONNECTOR_DVID,
498 DRM_MODE_CONNECTOR_VGA,
499 DRM_MODE_CONNECTOR_Composite,
500 DRM_MODE_CONNECTOR_SVIDEO,
501 DRM_MODE_CONNECTOR_Unknown,
502 DRM_MODE_CONNECTOR_Unknown,
503 DRM_MODE_CONNECTOR_9PinDIN,
504 DRM_MODE_CONNECTOR_Unknown,
505 DRM_MODE_CONNECTOR_HDMIA,
506 DRM_MODE_CONNECTOR_HDMIB,
507 DRM_MODE_CONNECTOR_LVDS,
508 DRM_MODE_CONNECTOR_9PinDIN,
509 DRM_MODE_CONNECTOR_Unknown,
510 DRM_MODE_CONNECTOR_Unknown,
511 DRM_MODE_CONNECTOR_Unknown,
512 DRM_MODE_CONNECTOR_DisplayPort,
513 DRM_MODE_CONNECTOR_eDP,
514 DRM_MODE_CONNECTOR_Unknown
515};
516
517bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
518{
519 struct radeon_device *rdev = dev->dev_private;
520 struct radeon_mode_info *mode_info = &rdev->mode_info;
521 struct atom_context *ctx = mode_info->atom_context;
522 int index = GetIndexIntoMasterTable(DATA, Object_Header);
523 u16 size, data_offset;
524 u8 frev, crev;
525 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
526 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
527 ATOM_OBJECT_TABLE *router_obj;
528 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
529 ATOM_OBJECT_HEADER *obj_header;
530 int i, j, k, path_size, device_support;
531 int connector_type;
532 u16 igp_lane_info, conn_id, connector_object_id;
533 struct radeon_i2c_bus_rec ddc_bus;
534 struct radeon_router router;
535 struct radeon_gpio_rec gpio;
536 struct radeon_hpd hpd;
537
538 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
539 return false;
540
541 if (crev < 2)
542 return false;
543
544 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
545 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
546 (ctx->bios + data_offset +
547 le16_to_cpu(obj_header->usDisplayPathTableOffset));
548 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
549 (ctx->bios + data_offset +
550 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
551 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
552 (ctx->bios + data_offset +
553 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
554 router_obj = (ATOM_OBJECT_TABLE *)
555 (ctx->bios + data_offset +
556 le16_to_cpu(obj_header->usRouterObjectTableOffset));
557 device_support = le16_to_cpu(obj_header->usDeviceSupport);
558
559 path_size = 0;
560 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
561 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
562 ATOM_DISPLAY_OBJECT_PATH *path;
563 addr += path_size;
564 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
565 path_size += le16_to_cpu(path->usSize);
566
567 if (device_support & le16_to_cpu(path->usDeviceTag)) {
568 uint8_t con_obj_id, con_obj_num, con_obj_type;
569
570 con_obj_id =
571 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
572 >> OBJECT_ID_SHIFT;
573 con_obj_num =
574 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
575 >> ENUM_ID_SHIFT;
576 con_obj_type =
577 (le16_to_cpu(path->usConnObjectId) &
578 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
579
580 /* TODO CV support */
581 if (le16_to_cpu(path->usDeviceTag) ==
582 ATOM_DEVICE_CV_SUPPORT)
583 continue;
584
585 /* IGP chips */
586 if ((rdev->flags & RADEON_IS_IGP) &&
587 (con_obj_id ==
588 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
589 uint16_t igp_offset = 0;
590 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
591
592 index =
593 GetIndexIntoMasterTable(DATA,
594 IntegratedSystemInfo);
595
596 if (atom_parse_data_header(ctx, index, &size, &frev,
597 &crev, &igp_offset)) {
598
599 if (crev >= 2) {
600 igp_obj =
601 (ATOM_INTEGRATED_SYSTEM_INFO_V2
602 *) (ctx->bios + igp_offset);
603
604 if (igp_obj) {
605 uint32_t slot_config, ct;
606
607 if (con_obj_num == 1)
608 slot_config =
609 igp_obj->
610 ulDDISlot1Config;
611 else
612 slot_config =
613 igp_obj->
614 ulDDISlot2Config;
615
616 ct = (slot_config >> 16) & 0xff;
617 connector_type =
618 object_connector_convert
619 [ct];
620 connector_object_id = ct;
621 igp_lane_info =
622 slot_config & 0xffff;
623 } else
624 continue;
625 } else
626 continue;
627 } else {
628 igp_lane_info = 0;
629 connector_type =
630 object_connector_convert[con_obj_id];
631 connector_object_id = con_obj_id;
632 }
633 } else {
634 igp_lane_info = 0;
635 connector_type =
636 object_connector_convert[con_obj_id];
637 connector_object_id = con_obj_id;
638 }
639
640 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
641 continue;
642
643 router.ddc_valid = false;
644 router.cd_valid = false;
645 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
646 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
647
648 grph_obj_id =
649 (le16_to_cpu(path->usGraphicObjIds[j]) &
650 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
651 grph_obj_num =
652 (le16_to_cpu(path->usGraphicObjIds[j]) &
653 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
654 grph_obj_type =
655 (le16_to_cpu(path->usGraphicObjIds[j]) &
656 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
657
658 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
659 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
660 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
661 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
662 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
663 (ctx->bios + data_offset +
664 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
665 ATOM_ENCODER_CAP_RECORD *cap_record;
666 u16 caps = 0;
667
668 while (record->ucRecordSize > 0 &&
669 record->ucRecordType > 0 &&
670 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
671 switch (record->ucRecordType) {
672 case ATOM_ENCODER_CAP_RECORD_TYPE:
673 cap_record =(ATOM_ENCODER_CAP_RECORD *)
674 record;
675 caps = le16_to_cpu(cap_record->usEncoderCap);
676 break;
677 }
678 record = (ATOM_COMMON_RECORD_HEADER *)
679 ((char *)record + record->ucRecordSize);
680 }
681 radeon_add_atom_encoder(dev,
682 encoder_obj,
683 le16_to_cpu
684 (path->
685 usDeviceTag),
686 caps);
687 }
688 }
689 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
690 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
691 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
692 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
693 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
694 (ctx->bios + data_offset +
695 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
696 ATOM_I2C_RECORD *i2c_record;
697 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
698 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
699 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
700 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
701 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
702 (ctx->bios + data_offset +
703 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
704 u8 *num_dst_objs = (u8 *)
705 ((u8 *)router_src_dst_table + 1 +
706 (router_src_dst_table->ucNumberOfSrc * 2));
707 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
708 int enum_id;
709
710 router.router_id = router_obj_id;
711 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
712 if (le16_to_cpu(path->usConnObjectId) ==
713 le16_to_cpu(dst_objs[enum_id]))
714 break;
715 }
716
717 while (record->ucRecordSize > 0 &&
718 record->ucRecordType > 0 &&
719 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
720 switch (record->ucRecordType) {
721 case ATOM_I2C_RECORD_TYPE:
722 i2c_record =
723 (ATOM_I2C_RECORD *)
724 record;
725 i2c_config =
726 (ATOM_I2C_ID_CONFIG_ACCESS *)
727 &i2c_record->sucI2cId;
728 router.i2c_info =
729 radeon_lookup_i2c_gpio(rdev,
730 i2c_config->
731 ucAccess);
732 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
733 break;
734 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
735 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
736 record;
737 router.ddc_valid = true;
738 router.ddc_mux_type = ddc_path->ucMuxType;
739 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
740 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
741 break;
742 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
743 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
744 record;
745 router.cd_valid = true;
746 router.cd_mux_type = cd_path->ucMuxType;
747 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
748 router.cd_mux_state = cd_path->ucMuxState[enum_id];
749 break;
750 }
751 record = (ATOM_COMMON_RECORD_HEADER *)
752 ((char *)record + record->ucRecordSize);
753 }
754 }
755 }
756 }
757 }
758
759 /* look up gpio for ddc, hpd */
760 ddc_bus.valid = false;
761 hpd.hpd = RADEON_HPD_NONE;
762 if ((le16_to_cpu(path->usDeviceTag) &
763 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
764 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
765 if (le16_to_cpu(path->usConnObjectId) ==
766 le16_to_cpu(con_obj->asObjects[j].
767 usObjectID)) {
768 ATOM_COMMON_RECORD_HEADER
769 *record =
770 (ATOM_COMMON_RECORD_HEADER
771 *)
772 (ctx->bios + data_offset +
773 le16_to_cpu(con_obj->
774 asObjects[j].
775 usRecordOffset));
776 ATOM_I2C_RECORD *i2c_record;
777 ATOM_HPD_INT_RECORD *hpd_record;
778 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
779
780 while (record->ucRecordSize > 0 &&
781 record->ucRecordType > 0 &&
782 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
783 switch (record->ucRecordType) {
784 case ATOM_I2C_RECORD_TYPE:
785 i2c_record =
786 (ATOM_I2C_RECORD *)
787 record;
788 i2c_config =
789 (ATOM_I2C_ID_CONFIG_ACCESS *)
790 &i2c_record->sucI2cId;
791 ddc_bus = radeon_lookup_i2c_gpio(rdev,
792 i2c_config->
793 ucAccess);
794 break;
795 case ATOM_HPD_INT_RECORD_TYPE:
796 hpd_record =
797 (ATOM_HPD_INT_RECORD *)
798 record;
799 gpio = radeon_atombios_lookup_gpio(rdev,
800 hpd_record->ucHPDIntGPIOID);
801 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
802 hpd.plugged_state = hpd_record->ucPlugged_PinState;
803 break;
804 }
805 record =
806 (ATOM_COMMON_RECORD_HEADER
807 *) ((char *)record
808 +
809 record->
810 ucRecordSize);
811 }
812 break;
813 }
814 }
815 }
816
817 /* needed for aux chan transactions */
818 ddc_bus.hpd = hpd.hpd;
819
820 conn_id = le16_to_cpu(path->usConnObjectId);
821
822 if (!radeon_atom_apply_quirks
823 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
824 &ddc_bus, &conn_id, &hpd))
825 continue;
826
827 radeon_add_atom_connector(dev,
828 conn_id,
829 le16_to_cpu(path->
830 usDeviceTag),
831 connector_type, &ddc_bus,
832 igp_lane_info,
833 connector_object_id,
834 &hpd,
835 &router);
836
837 }
838 }
839
840 radeon_link_encoder_connector(dev);
841
842 radeon_setup_mst_connector(dev);
843 return true;
844}
845
846static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
847 int connector_type,
848 uint16_t devices)
849{
850 struct radeon_device *rdev = dev->dev_private;
851
852 if (rdev->flags & RADEON_IS_IGP) {
853 return supported_devices_connector_object_id_convert
854 [connector_type];
855 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
856 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
857 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
858 struct radeon_mode_info *mode_info = &rdev->mode_info;
859 struct atom_context *ctx = mode_info->atom_context;
860 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
861 uint16_t size, data_offset;
862 uint8_t frev, crev;
863 ATOM_XTMDS_INFO *xtmds;
864
865 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
866 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
867
868 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
869 if (connector_type == DRM_MODE_CONNECTOR_DVII)
870 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
871 else
872 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
873 } else {
874 if (connector_type == DRM_MODE_CONNECTOR_DVII)
875 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
876 else
877 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
878 }
879 } else
880 return supported_devices_connector_object_id_convert
881 [connector_type];
882 } else {
883 return supported_devices_connector_object_id_convert
884 [connector_type];
885 }
886}
887
888struct bios_connector {
889 bool valid;
890 uint16_t line_mux;
891 uint16_t devices;
892 int connector_type;
893 struct radeon_i2c_bus_rec ddc_bus;
894 struct radeon_hpd hpd;
895};
896
897bool radeon_get_atom_connector_info_from_supported_devices_table(struct
898 drm_device
899 *dev)
900{
901 struct radeon_device *rdev = dev->dev_private;
902 struct radeon_mode_info *mode_info = &rdev->mode_info;
903 struct atom_context *ctx = mode_info->atom_context;
904 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
905 uint16_t size, data_offset;
906 uint8_t frev, crev;
907 uint16_t device_support;
908 uint8_t dac;
909 union atom_supported_devices *supported_devices;
910 int i, j, max_device;
911 struct bios_connector *bios_connectors;
912 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
913 struct radeon_router router;
914
915 router.ddc_valid = false;
916 router.cd_valid = false;
917
918 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
919 if (!bios_connectors)
920 return false;
921
922 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
923 &data_offset)) {
924 kfree(bios_connectors);
925 return false;
926 }
927
928 supported_devices =
929 (union atom_supported_devices *)(ctx->bios + data_offset);
930
931 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
932
933 if (frev > 1)
934 max_device = ATOM_MAX_SUPPORTED_DEVICE;
935 else
936 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
937
938 for (i = 0; i < max_device; i++) {
939 ATOM_CONNECTOR_INFO_I2C ci =
940 supported_devices->info.asConnInfo[i];
941
942 bios_connectors[i].valid = false;
943
944 if (!(device_support & (1 << i))) {
945 continue;
946 }
947
948 if (i == ATOM_DEVICE_CV_INDEX) {
949 DRM_DEBUG_KMS("Skipping Component Video\n");
950 continue;
951 }
952
953 bios_connectors[i].connector_type =
954 supported_devices_connector_convert[ci.sucConnectorInfo.
955 sbfAccess.
956 bfConnectorType];
957
958 if (bios_connectors[i].connector_type ==
959 DRM_MODE_CONNECTOR_Unknown)
960 continue;
961
962 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
963
964 bios_connectors[i].line_mux =
965 ci.sucI2cId.ucAccess;
966
967 /* give tv unique connector ids */
968 if (i == ATOM_DEVICE_TV1_INDEX) {
969 bios_connectors[i].ddc_bus.valid = false;
970 bios_connectors[i].line_mux = 50;
971 } else if (i == ATOM_DEVICE_TV2_INDEX) {
972 bios_connectors[i].ddc_bus.valid = false;
973 bios_connectors[i].line_mux = 51;
974 } else if (i == ATOM_DEVICE_CV_INDEX) {
975 bios_connectors[i].ddc_bus.valid = false;
976 bios_connectors[i].line_mux = 52;
977 } else
978 bios_connectors[i].ddc_bus =
979 radeon_lookup_i2c_gpio(rdev,
980 bios_connectors[i].line_mux);
981
982 if ((crev > 1) && (frev > 1)) {
983 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
984 switch (isb) {
985 case 0x4:
986 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
987 break;
988 case 0xa:
989 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
990 break;
991 default:
992 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
993 break;
994 }
995 } else {
996 if (i == ATOM_DEVICE_DFP1_INDEX)
997 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
998 else if (i == ATOM_DEVICE_DFP2_INDEX)
999 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1000 else
1001 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1002 }
1003
1004 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1005 * shared with a DVI port, we'll pick up the DVI connector when we
1006 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1007 */
1008 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1009 bios_connectors[i].connector_type =
1010 DRM_MODE_CONNECTOR_VGA;
1011
1012 if (!radeon_atom_apply_quirks
1013 (dev, (1 << i), &bios_connectors[i].connector_type,
1014 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1015 &bios_connectors[i].hpd))
1016 continue;
1017
1018 bios_connectors[i].valid = true;
1019 bios_connectors[i].devices = (1 << i);
1020
1021 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1022 radeon_add_atom_encoder(dev,
1023 radeon_get_encoder_enum(dev,
1024 (1 << i),
1025 dac),
1026 (1 << i),
1027 0);
1028 else
1029 radeon_add_legacy_encoder(dev,
1030 radeon_get_encoder_enum(dev,
1031 (1 << i),
1032 dac),
1033 (1 << i));
1034 }
1035
1036 /* combine shared connectors */
1037 for (i = 0; i < max_device; i++) {
1038 if (bios_connectors[i].valid) {
1039 for (j = 0; j < max_device; j++) {
1040 if (bios_connectors[j].valid && (i != j)) {
1041 if (bios_connectors[i].line_mux ==
1042 bios_connectors[j].line_mux) {
1043 /* make sure not to combine LVDS */
1044 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1045 bios_connectors[i].line_mux = 53;
1046 bios_connectors[i].ddc_bus.valid = false;
1047 continue;
1048 }
1049 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1050 bios_connectors[j].line_mux = 53;
1051 bios_connectors[j].ddc_bus.valid = false;
1052 continue;
1053 }
1054 /* combine analog and digital for DVI-I */
1055 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1056 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1057 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1058 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1059 bios_connectors[i].devices |=
1060 bios_connectors[j].devices;
1061 bios_connectors[i].connector_type =
1062 DRM_MODE_CONNECTOR_DVII;
1063 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1064 bios_connectors[i].hpd =
1065 bios_connectors[j].hpd;
1066 bios_connectors[j].valid = false;
1067 }
1068 }
1069 }
1070 }
1071 }
1072 }
1073
1074 /* add the connectors */
1075 for (i = 0; i < max_device; i++) {
1076 if (bios_connectors[i].valid) {
1077 uint16_t connector_object_id =
1078 atombios_get_connector_object_id(dev,
1079 bios_connectors[i].connector_type,
1080 bios_connectors[i].devices);
1081 radeon_add_atom_connector(dev,
1082 bios_connectors[i].line_mux,
1083 bios_connectors[i].devices,
1084 bios_connectors[i].
1085 connector_type,
1086 &bios_connectors[i].ddc_bus,
1087 0,
1088 connector_object_id,
1089 &bios_connectors[i].hpd,
1090 &router);
1091 }
1092 }
1093
1094 radeon_link_encoder_connector(dev);
1095
1096 kfree(bios_connectors);
1097 return true;
1098}
1099
1100union firmware_info {
1101 ATOM_FIRMWARE_INFO info;
1102 ATOM_FIRMWARE_INFO_V1_2 info_12;
1103 ATOM_FIRMWARE_INFO_V1_3 info_13;
1104 ATOM_FIRMWARE_INFO_V1_4 info_14;
1105 ATOM_FIRMWARE_INFO_V2_1 info_21;
1106 ATOM_FIRMWARE_INFO_V2_2 info_22;
1107};
1108
1109union igp_info {
1110 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1111 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1112 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1113 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1114 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1115};
1116
1117static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev)
1118{
1119 struct radeon_mode_info *mode_info = &rdev->mode_info;
1120 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1121 union igp_info *igp_info;
1122 u8 frev, crev;
1123 u16 data_offset;
1124
1125 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1126 &frev, &crev, &data_offset)) {
1127 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1128 data_offset);
1129 rdev->clock.vco_freq =
1130 le32_to_cpu(igp_info->info_6.ulDentistVCOFreq);
1131 }
1132}
1133
1134bool radeon_atom_get_clock_info(struct drm_device *dev)
1135{
1136 struct radeon_device *rdev = dev->dev_private;
1137 struct radeon_mode_info *mode_info = &rdev->mode_info;
1138 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1139 union firmware_info *firmware_info;
1140 uint8_t frev, crev;
1141 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1142 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1143 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1144 struct radeon_pll *spll = &rdev->clock.spll;
1145 struct radeon_pll *mpll = &rdev->clock.mpll;
1146 uint16_t data_offset;
1147
1148 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1149 &frev, &crev, &data_offset)) {
1150 firmware_info =
1151 (union firmware_info *)(mode_info->atom_context->bios +
1152 data_offset);
1153 /* pixel clocks */
1154 p1pll->reference_freq =
1155 le16_to_cpu(firmware_info->info.usReferenceClock);
1156 p1pll->reference_div = 0;
1157
1158 if (crev < 2)
1159 p1pll->pll_out_min =
1160 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1161 else
1162 p1pll->pll_out_min =
1163 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1164 p1pll->pll_out_max =
1165 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1166
1167 if (crev >= 4) {
1168 p1pll->lcd_pll_out_min =
1169 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1170 if (p1pll->lcd_pll_out_min == 0)
1171 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1172 p1pll->lcd_pll_out_max =
1173 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1174 if (p1pll->lcd_pll_out_max == 0)
1175 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1176 } else {
1177 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1178 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1179 }
1180
1181 if (p1pll->pll_out_min == 0) {
1182 if (ASIC_IS_AVIVO(rdev))
1183 p1pll->pll_out_min = 64800;
1184 else
1185 p1pll->pll_out_min = 20000;
1186 }
1187
1188 p1pll->pll_in_min =
1189 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1190 p1pll->pll_in_max =
1191 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1192
1193 *p2pll = *p1pll;
1194
1195 /* system clock */
1196 if (ASIC_IS_DCE4(rdev))
1197 spll->reference_freq =
1198 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1199 else
1200 spll->reference_freq =
1201 le16_to_cpu(firmware_info->info.usReferenceClock);
1202 spll->reference_div = 0;
1203
1204 spll->pll_out_min =
1205 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1206 spll->pll_out_max =
1207 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1208
1209 /* ??? */
1210 if (spll->pll_out_min == 0) {
1211 if (ASIC_IS_AVIVO(rdev))
1212 spll->pll_out_min = 64800;
1213 else
1214 spll->pll_out_min = 20000;
1215 }
1216
1217 spll->pll_in_min =
1218 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1219 spll->pll_in_max =
1220 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1221
1222 /* memory clock */
1223 if (ASIC_IS_DCE4(rdev))
1224 mpll->reference_freq =
1225 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1226 else
1227 mpll->reference_freq =
1228 le16_to_cpu(firmware_info->info.usReferenceClock);
1229 mpll->reference_div = 0;
1230
1231 mpll->pll_out_min =
1232 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1233 mpll->pll_out_max =
1234 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1235
1236 /* ??? */
1237 if (mpll->pll_out_min == 0) {
1238 if (ASIC_IS_AVIVO(rdev))
1239 mpll->pll_out_min = 64800;
1240 else
1241 mpll->pll_out_min = 20000;
1242 }
1243
1244 mpll->pll_in_min =
1245 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1246 mpll->pll_in_max =
1247 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1248
1249 rdev->clock.default_sclk =
1250 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1251 rdev->clock.default_mclk =
1252 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1253
1254 if (ASIC_IS_DCE4(rdev)) {
1255 rdev->clock.default_dispclk =
1256 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1257 if (rdev->clock.default_dispclk == 0) {
1258 if (ASIC_IS_DCE6(rdev))
1259 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1260 else if (ASIC_IS_DCE5(rdev))
1261 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1262 else
1263 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1264 }
1265 /* set a reasonable default for DP */
1266 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1267 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1268 rdev->clock.default_dispclk / 100);
1269 rdev->clock.default_dispclk = 60000;
1270 }
1271 rdev->clock.dp_extclk =
1272 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1273 rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1274 }
1275 *dcpll = *p1pll;
1276
1277 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1278 if (rdev->clock.max_pixel_clock == 0)
1279 rdev->clock.max_pixel_clock = 40000;
1280
1281 /* not technically a clock, but... */
1282 rdev->mode_info.firmware_flags =
1283 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1284
1285 if (ASIC_IS_DCE8(rdev))
1286 rdev->clock.vco_freq =
1287 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq);
1288 else if (ASIC_IS_DCE5(rdev))
1289 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1290 else if (ASIC_IS_DCE41(rdev))
1291 radeon_atombios_get_dentist_vco_freq(rdev);
1292 else
1293 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1294
1295 if (rdev->clock.vco_freq == 0)
1296 rdev->clock.vco_freq = 360000; /* 3.6 GHz */
1297
1298 return true;
1299 }
1300
1301 return false;
1302}
1303
1304bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1305{
1306 struct radeon_mode_info *mode_info = &rdev->mode_info;
1307 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1308 union igp_info *igp_info;
1309 u8 frev, crev;
1310 u16 data_offset;
1311
1312 /* sideport is AMD only */
1313 if (rdev->family == CHIP_RS600)
1314 return false;
1315
1316 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1317 &frev, &crev, &data_offset)) {
1318 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1319 data_offset);
1320 switch (crev) {
1321 case 1:
1322 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1323 return true;
1324 break;
1325 case 2:
1326 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1327 return true;
1328 break;
1329 default:
1330 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1331 break;
1332 }
1333 }
1334 return false;
1335}
1336
1337bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1338 struct radeon_encoder_int_tmds *tmds)
1339{
1340 struct drm_device *dev = encoder->base.dev;
1341 struct radeon_device *rdev = dev->dev_private;
1342 struct radeon_mode_info *mode_info = &rdev->mode_info;
1343 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1344 uint16_t data_offset;
1345 struct _ATOM_TMDS_INFO *tmds_info;
1346 uint8_t frev, crev;
1347 uint16_t maxfreq;
1348 int i;
1349
1350 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1351 &frev, &crev, &data_offset)) {
1352 tmds_info =
1353 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1354 data_offset);
1355
1356 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1357 for (i = 0; i < 4; i++) {
1358 tmds->tmds_pll[i].freq =
1359 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1360 tmds->tmds_pll[i].value =
1361 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1362 tmds->tmds_pll[i].value |=
1363 (tmds_info->asMiscInfo[i].
1364 ucPLL_VCO_Gain & 0x3f) << 6;
1365 tmds->tmds_pll[i].value |=
1366 (tmds_info->asMiscInfo[i].
1367 ucPLL_DutyCycle & 0xf) << 12;
1368 tmds->tmds_pll[i].value |=
1369 (tmds_info->asMiscInfo[i].
1370 ucPLL_VoltageSwing & 0xf) << 16;
1371
1372 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1373 tmds->tmds_pll[i].freq,
1374 tmds->tmds_pll[i].value);
1375
1376 if (maxfreq == tmds->tmds_pll[i].freq) {
1377 tmds->tmds_pll[i].freq = 0xffffffff;
1378 break;
1379 }
1380 }
1381 return true;
1382 }
1383 return false;
1384}
1385
1386bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1387 struct radeon_atom_ss *ss,
1388 int id)
1389{
1390 struct radeon_mode_info *mode_info = &rdev->mode_info;
1391 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1392 uint16_t data_offset, size;
1393 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1394 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1395 uint8_t frev, crev;
1396 int i, num_indices;
1397
1398 memset(ss, 0, sizeof(struct radeon_atom_ss));
1399 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1400 &frev, &crev, &data_offset)) {
1401 ss_info =
1402 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1403
1404 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1405 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1406 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1407 ((u8 *)&ss_info->asSS_Info[0]);
1408 for (i = 0; i < num_indices; i++) {
1409 if (ss_assign->ucSS_Id == id) {
1410 ss->percentage =
1411 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
1412 ss->type = ss_assign->ucSpreadSpectrumType;
1413 ss->step = ss_assign->ucSS_Step;
1414 ss->delay = ss_assign->ucSS_Delay;
1415 ss->range = ss_assign->ucSS_Range;
1416 ss->refdiv = ss_assign->ucRecommendedRef_Div;
1417 return true;
1418 }
1419 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1420 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1421 }
1422 }
1423 return false;
1424}
1425
1426static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1427 struct radeon_atom_ss *ss,
1428 int id)
1429{
1430 struct radeon_mode_info *mode_info = &rdev->mode_info;
1431 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1432 u16 data_offset, size;
1433 union igp_info *igp_info;
1434 u8 frev, crev;
1435 u16 percentage = 0, rate = 0;
1436
1437 /* get any igp specific overrides */
1438 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1439 &frev, &crev, &data_offset)) {
1440 igp_info = (union igp_info *)
1441 (mode_info->atom_context->bios + data_offset);
1442 switch (crev) {
1443 case 6:
1444 switch (id) {
1445 case ASIC_INTERNAL_SS_ON_TMDS:
1446 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1447 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1448 break;
1449 case ASIC_INTERNAL_SS_ON_HDMI:
1450 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1451 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1452 break;
1453 case ASIC_INTERNAL_SS_ON_LVDS:
1454 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1455 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1456 break;
1457 }
1458 break;
1459 case 7:
1460 switch (id) {
1461 case ASIC_INTERNAL_SS_ON_TMDS:
1462 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1463 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1464 break;
1465 case ASIC_INTERNAL_SS_ON_HDMI:
1466 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1467 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1468 break;
1469 case ASIC_INTERNAL_SS_ON_LVDS:
1470 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1471 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1472 break;
1473 }
1474 break;
1475 case 8:
1476 switch (id) {
1477 case ASIC_INTERNAL_SS_ON_TMDS:
1478 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1479 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1480 break;
1481 case ASIC_INTERNAL_SS_ON_HDMI:
1482 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1483 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1484 break;
1485 case ASIC_INTERNAL_SS_ON_LVDS:
1486 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1487 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1488 break;
1489 }
1490 break;
1491 default:
1492 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1493 break;
1494 }
1495 if (percentage)
1496 ss->percentage = percentage;
1497 if (rate)
1498 ss->rate = rate;
1499 }
1500}
1501
1502union asic_ss_info {
1503 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1504 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1505 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1506};
1507
1508union asic_ss_assignment {
1509 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
1510 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
1511 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
1512};
1513
1514bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1515 struct radeon_atom_ss *ss,
1516 int id, u32 clock)
1517{
1518 struct radeon_mode_info *mode_info = &rdev->mode_info;
1519 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1520 uint16_t data_offset, size;
1521 union asic_ss_info *ss_info;
1522 union asic_ss_assignment *ss_assign;
1523 uint8_t frev, crev;
1524 int i, num_indices;
1525
1526 if (id == ASIC_INTERNAL_MEMORY_SS) {
1527 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1528 return false;
1529 }
1530 if (id == ASIC_INTERNAL_ENGINE_SS) {
1531 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1532 return false;
1533 }
1534
1535 memset(ss, 0, sizeof(struct radeon_atom_ss));
1536 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1537 &frev, &crev, &data_offset)) {
1538
1539 ss_info =
1540 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1541
1542 switch (frev) {
1543 case 1:
1544 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1545 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1546
1547 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
1548 for (i = 0; i < num_indices; i++) {
1549 if ((ss_assign->v1.ucClockIndication == id) &&
1550 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1551 ss->percentage =
1552 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1553 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1554 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1555 ss->percentage_divider = 100;
1556 return true;
1557 }
1558 ss_assign = (union asic_ss_assignment *)
1559 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1560 }
1561 break;
1562 case 2:
1563 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1564 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1565 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
1566 for (i = 0; i < num_indices; i++) {
1567 if ((ss_assign->v2.ucClockIndication == id) &&
1568 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1569 ss->percentage =
1570 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1571 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1572 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1573 ss->percentage_divider = 100;
1574 if ((crev == 2) &&
1575 ((id == ASIC_INTERNAL_ENGINE_SS) ||
1576 (id == ASIC_INTERNAL_MEMORY_SS)))
1577 ss->rate /= 100;
1578 return true;
1579 }
1580 ss_assign = (union asic_ss_assignment *)
1581 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1582 }
1583 break;
1584 case 3:
1585 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1586 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1587 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
1588 for (i = 0; i < num_indices; i++) {
1589 if ((ss_assign->v3.ucClockIndication == id) &&
1590 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1591 ss->percentage =
1592 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1593 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1594 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1595 if (ss_assign->v3.ucSpreadSpectrumMode &
1596 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
1597 ss->percentage_divider = 1000;
1598 else
1599 ss->percentage_divider = 100;
1600 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1601 (id == ASIC_INTERNAL_MEMORY_SS))
1602 ss->rate /= 100;
1603 if (rdev->flags & RADEON_IS_IGP)
1604 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1605 return true;
1606 }
1607 ss_assign = (union asic_ss_assignment *)
1608 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1609 }
1610 break;
1611 default:
1612 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1613 break;
1614 }
1615
1616 }
1617 return false;
1618}
1619
1620union lvds_info {
1621 struct _ATOM_LVDS_INFO info;
1622 struct _ATOM_LVDS_INFO_V12 info_12;
1623};
1624
1625struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1626 radeon_encoder
1627 *encoder)
1628{
1629 struct drm_device *dev = encoder->base.dev;
1630 struct radeon_device *rdev = dev->dev_private;
1631 struct radeon_mode_info *mode_info = &rdev->mode_info;
1632 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1633 uint16_t data_offset, misc;
1634 union lvds_info *lvds_info;
1635 uint8_t frev, crev;
1636 struct radeon_encoder_atom_dig *lvds = NULL;
1637 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1638
1639 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1640 &frev, &crev, &data_offset)) {
1641 lvds_info =
1642 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1643 lvds =
1644 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1645
1646 if (!lvds)
1647 return NULL;
1648
1649 lvds->native_mode.clock =
1650 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1651 lvds->native_mode.hdisplay =
1652 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1653 lvds->native_mode.vdisplay =
1654 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1655 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1656 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1657 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1658 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1659 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1660 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1661 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1662 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1663 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1664 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1665 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1666 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1667 lvds->panel_pwr_delay =
1668 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1669 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1670
1671 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1672 if (misc & ATOM_VSYNC_POLARITY)
1673 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1674 if (misc & ATOM_HSYNC_POLARITY)
1675 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1676 if (misc & ATOM_COMPOSITESYNC)
1677 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1678 if (misc & ATOM_INTERLACE)
1679 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1680 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1681 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1682
1683 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1684 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1685
1686 /* set crtc values */
1687 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1688
1689 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1690
1691 encoder->native_mode = lvds->native_mode;
1692
1693 if (encoder_enum == 2)
1694 lvds->linkb = true;
1695 else
1696 lvds->linkb = false;
1697
1698 /* parse the lcd record table */
1699 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1700 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1701 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1702 bool bad_record = false;
1703 u8 *record;
1704
1705 if ((frev == 1) && (crev < 2))
1706 /* absolute */
1707 record = (u8 *)(mode_info->atom_context->bios +
1708 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1709 else
1710 /* relative */
1711 record = (u8 *)(mode_info->atom_context->bios +
1712 data_offset +
1713 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1714 while (*record != ATOM_RECORD_END_TYPE) {
1715 switch (*record) {
1716 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1717 record += sizeof(ATOM_PATCH_RECORD_MODE);
1718 break;
1719 case LCD_RTS_RECORD_TYPE:
1720 record += sizeof(ATOM_LCD_RTS_RECORD);
1721 break;
1722 case LCD_CAP_RECORD_TYPE:
1723 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1724 break;
1725 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1726 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1727 if (fake_edid_record->ucFakeEDIDLength) {
1728 struct edid *edid;
1729 int edid_size =
1730 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1731 edid = kmalloc(edid_size, GFP_KERNEL);
1732 if (edid) {
1733 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1734 fake_edid_record->ucFakeEDIDLength);
1735
1736 if (drm_edid_is_valid(edid)) {
1737 rdev->mode_info.bios_hardcoded_edid = edid;
1738 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1739 } else
1740 kfree(edid);
1741 }
1742 }
1743 record += fake_edid_record->ucFakeEDIDLength ?
1744 fake_edid_record->ucFakeEDIDLength + 2 :
1745 sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1746 break;
1747 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1748 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1749 lvds->native_mode.width_mm = panel_res_record->usHSize;
1750 lvds->native_mode.height_mm = panel_res_record->usVSize;
1751 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1752 break;
1753 default:
1754 DRM_ERROR("Bad LCD record %d\n", *record);
1755 bad_record = true;
1756 break;
1757 }
1758 if (bad_record)
1759 break;
1760 }
1761 }
1762 }
1763 return lvds;
1764}
1765
1766struct radeon_encoder_primary_dac *
1767radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1768{
1769 struct drm_device *dev = encoder->base.dev;
1770 struct radeon_device *rdev = dev->dev_private;
1771 struct radeon_mode_info *mode_info = &rdev->mode_info;
1772 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1773 uint16_t data_offset;
1774 struct _COMPASSIONATE_DATA *dac_info;
1775 uint8_t frev, crev;
1776 uint8_t bg, dac;
1777 struct radeon_encoder_primary_dac *p_dac = NULL;
1778
1779 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1780 &frev, &crev, &data_offset)) {
1781 dac_info = (struct _COMPASSIONATE_DATA *)
1782 (mode_info->atom_context->bios + data_offset);
1783
1784 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1785
1786 if (!p_dac)
1787 return NULL;
1788
1789 bg = dac_info->ucDAC1_BG_Adjustment;
1790 dac = dac_info->ucDAC1_DAC_Adjustment;
1791 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1792
1793 }
1794 return p_dac;
1795}
1796
1797bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1798 struct drm_display_mode *mode)
1799{
1800 struct radeon_mode_info *mode_info = &rdev->mode_info;
1801 ATOM_ANALOG_TV_INFO *tv_info;
1802 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1803 ATOM_DTD_FORMAT *dtd_timings;
1804 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1805 u8 frev, crev;
1806 u16 data_offset, misc;
1807
1808 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1809 &frev, &crev, &data_offset))
1810 return false;
1811
1812 switch (crev) {
1813 case 1:
1814 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1815 if (index >= MAX_SUPPORTED_TV_TIMING)
1816 return false;
1817
1818 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1819 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1820 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1821 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1822 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1823
1824 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1825 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1826 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1827 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1828 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1829
1830 mode->flags = 0;
1831 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1832 if (misc & ATOM_VSYNC_POLARITY)
1833 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1834 if (misc & ATOM_HSYNC_POLARITY)
1835 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1836 if (misc & ATOM_COMPOSITESYNC)
1837 mode->flags |= DRM_MODE_FLAG_CSYNC;
1838 if (misc & ATOM_INTERLACE)
1839 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1840 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1841 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1842
1843 mode->crtc_clock = mode->clock =
1844 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1845
1846 if (index == 1) {
1847 /* PAL timings appear to have wrong values for totals */
1848 mode->crtc_htotal -= 1;
1849 mode->crtc_vtotal -= 1;
1850 }
1851 break;
1852 case 2:
1853 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1854 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1855 return false;
1856
1857 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1858 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1859 le16_to_cpu(dtd_timings->usHBlanking_Time);
1860 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1861 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1862 le16_to_cpu(dtd_timings->usHSyncOffset);
1863 mode->crtc_hsync_end = mode->crtc_hsync_start +
1864 le16_to_cpu(dtd_timings->usHSyncWidth);
1865
1866 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1867 le16_to_cpu(dtd_timings->usVBlanking_Time);
1868 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1869 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1870 le16_to_cpu(dtd_timings->usVSyncOffset);
1871 mode->crtc_vsync_end = mode->crtc_vsync_start +
1872 le16_to_cpu(dtd_timings->usVSyncWidth);
1873
1874 mode->flags = 0;
1875 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1876 if (misc & ATOM_VSYNC_POLARITY)
1877 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1878 if (misc & ATOM_HSYNC_POLARITY)
1879 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1880 if (misc & ATOM_COMPOSITESYNC)
1881 mode->flags |= DRM_MODE_FLAG_CSYNC;
1882 if (misc & ATOM_INTERLACE)
1883 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1884 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1885 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1886
1887 mode->crtc_clock = mode->clock =
1888 le16_to_cpu(dtd_timings->usPixClk) * 10;
1889 break;
1890 }
1891 return true;
1892}
1893
1894enum radeon_tv_std
1895radeon_atombios_get_tv_info(struct radeon_device *rdev)
1896{
1897 struct radeon_mode_info *mode_info = &rdev->mode_info;
1898 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1899 uint16_t data_offset;
1900 uint8_t frev, crev;
1901 struct _ATOM_ANALOG_TV_INFO *tv_info;
1902 enum radeon_tv_std tv_std = TV_STD_NTSC;
1903
1904 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1905 &frev, &crev, &data_offset)) {
1906
1907 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1908 (mode_info->atom_context->bios + data_offset);
1909
1910 switch (tv_info->ucTV_BootUpDefaultStandard) {
1911 case ATOM_TV_NTSC:
1912 tv_std = TV_STD_NTSC;
1913 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1914 break;
1915 case ATOM_TV_NTSCJ:
1916 tv_std = TV_STD_NTSC_J;
1917 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1918 break;
1919 case ATOM_TV_PAL:
1920 tv_std = TV_STD_PAL;
1921 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1922 break;
1923 case ATOM_TV_PALM:
1924 tv_std = TV_STD_PAL_M;
1925 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1926 break;
1927 case ATOM_TV_PALN:
1928 tv_std = TV_STD_PAL_N;
1929 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1930 break;
1931 case ATOM_TV_PALCN:
1932 tv_std = TV_STD_PAL_CN;
1933 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1934 break;
1935 case ATOM_TV_PAL60:
1936 tv_std = TV_STD_PAL_60;
1937 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1938 break;
1939 case ATOM_TV_SECAM:
1940 tv_std = TV_STD_SECAM;
1941 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1942 break;
1943 default:
1944 tv_std = TV_STD_NTSC;
1945 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1946 break;
1947 }
1948 }
1949 return tv_std;
1950}
1951
1952struct radeon_encoder_tv_dac *
1953radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1954{
1955 struct drm_device *dev = encoder->base.dev;
1956 struct radeon_device *rdev = dev->dev_private;
1957 struct radeon_mode_info *mode_info = &rdev->mode_info;
1958 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1959 uint16_t data_offset;
1960 struct _COMPASSIONATE_DATA *dac_info;
1961 uint8_t frev, crev;
1962 uint8_t bg, dac;
1963 struct radeon_encoder_tv_dac *tv_dac = NULL;
1964
1965 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1966 &frev, &crev, &data_offset)) {
1967
1968 dac_info = (struct _COMPASSIONATE_DATA *)
1969 (mode_info->atom_context->bios + data_offset);
1970
1971 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1972
1973 if (!tv_dac)
1974 return NULL;
1975
1976 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1977 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1978 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1979
1980 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1981 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1982 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1983
1984 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1985 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1986 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1987
1988 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1989 }
1990 return tv_dac;
1991}
1992
1993static const char *thermal_controller_names[] = {
1994 "NONE",
1995 "lm63",
1996 "adm1032",
1997 "adm1030",
1998 "max6649",
1999 "lm63", /* lm64 */
2000 "f75375",
2001 "asc7xxx",
2002};
2003
2004static const char *pp_lib_thermal_controller_names[] = {
2005 "NONE",
2006 "lm63",
2007 "adm1032",
2008 "adm1030",
2009 "max6649",
2010 "lm63", /* lm64 */
2011 "f75375",
2012 "RV6xx",
2013 "RV770",
2014 "adt7473",
2015 "NONE",
2016 "External GPIO",
2017 "Evergreen",
2018 "emc2103",
2019 "Sumo",
2020 "Northern Islands",
2021 "Southern Islands",
2022 "lm96163",
2023 "Sea Islands",
2024};
2025
2026union power_info {
2027 struct _ATOM_POWERPLAY_INFO info;
2028 struct _ATOM_POWERPLAY_INFO_V2 info_2;
2029 struct _ATOM_POWERPLAY_INFO_V3 info_3;
2030 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2031 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2032 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2033};
2034
2035union pplib_clock_info {
2036 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2037 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2038 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2039 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2040 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
2041 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
2042};
2043
2044union pplib_power_state {
2045 struct _ATOM_PPLIB_STATE v1;
2046 struct _ATOM_PPLIB_STATE_V2 v2;
2047};
2048
2049static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2050 int state_index,
2051 u32 misc, u32 misc2)
2052{
2053 rdev->pm.power_state[state_index].misc = misc;
2054 rdev->pm.power_state[state_index].misc2 = misc2;
2055 /* order matters! */
2056 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2057 rdev->pm.power_state[state_index].type =
2058 POWER_STATE_TYPE_POWERSAVE;
2059 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2060 rdev->pm.power_state[state_index].type =
2061 POWER_STATE_TYPE_BATTERY;
2062 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2063 rdev->pm.power_state[state_index].type =
2064 POWER_STATE_TYPE_BATTERY;
2065 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2066 rdev->pm.power_state[state_index].type =
2067 POWER_STATE_TYPE_BALANCED;
2068 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2069 rdev->pm.power_state[state_index].type =
2070 POWER_STATE_TYPE_PERFORMANCE;
2071 rdev->pm.power_state[state_index].flags &=
2072 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2073 }
2074 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2075 rdev->pm.power_state[state_index].type =
2076 POWER_STATE_TYPE_BALANCED;
2077 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2078 rdev->pm.power_state[state_index].type =
2079 POWER_STATE_TYPE_DEFAULT;
2080 rdev->pm.default_power_state_index = state_index;
2081 rdev->pm.power_state[state_index].default_clock_mode =
2082 &rdev->pm.power_state[state_index].clock_info[0];
2083 } else if (state_index == 0) {
2084 rdev->pm.power_state[state_index].clock_info[0].flags |=
2085 RADEON_PM_MODE_NO_DISPLAY;
2086 }
2087}
2088
2089static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2090{
2091 struct radeon_mode_info *mode_info = &rdev->mode_info;
2092 u32 misc, misc2 = 0;
2093 int num_modes = 0, i;
2094 int state_index = 0;
2095 struct radeon_i2c_bus_rec i2c_bus;
2096 union power_info *power_info;
2097 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2098 u16 data_offset;
2099 u8 frev, crev;
2100
2101 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2102 &frev, &crev, &data_offset))
2103 return state_index;
2104 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2105
2106 /* add the i2c bus for thermal/fan chip */
2107 if ((power_info->info.ucOverdriveThermalController > 0) &&
2108 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2109 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2110 thermal_controller_names[power_info->info.ucOverdriveThermalController],
2111 power_info->info.ucOverdriveControllerAddress >> 1);
2112 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2113 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2114 if (rdev->pm.i2c_bus) {
2115 struct i2c_board_info info = { };
2116 const char *name = thermal_controller_names[power_info->info.
2117 ucOverdriveThermalController];
2118 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2119 strlcpy(info.type, name, sizeof(info.type));
2120 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2121 }
2122 }
2123 num_modes = power_info->info.ucNumOfPowerModeEntries;
2124 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2125 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2126 if (num_modes == 0)
2127 return state_index;
2128 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2129 if (!rdev->pm.power_state)
2130 return state_index;
2131 /* last mode is usually default, array is low to high */
2132 for (i = 0; i < num_modes; i++) {
2133 rdev->pm.power_state[state_index].clock_info =
2134 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2135 if (!rdev->pm.power_state[state_index].clock_info)
2136 return state_index;
2137 rdev->pm.power_state[state_index].num_clock_modes = 1;
2138 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2139 switch (frev) {
2140 case 1:
2141 rdev->pm.power_state[state_index].clock_info[0].mclk =
2142 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2143 rdev->pm.power_state[state_index].clock_info[0].sclk =
2144 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2145 /* skip invalid modes */
2146 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2147 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2148 continue;
2149 rdev->pm.power_state[state_index].pcie_lanes =
2150 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2151 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2152 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2153 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2154 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2155 VOLTAGE_GPIO;
2156 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2157 radeon_atombios_lookup_gpio(rdev,
2158 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2159 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2160 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2161 true;
2162 else
2163 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2164 false;
2165 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2166 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2167 VOLTAGE_VDDC;
2168 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2169 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2170 }
2171 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2172 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2173 state_index++;
2174 break;
2175 case 2:
2176 rdev->pm.power_state[state_index].clock_info[0].mclk =
2177 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2178 rdev->pm.power_state[state_index].clock_info[0].sclk =
2179 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2180 /* skip invalid modes */
2181 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2182 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2183 continue;
2184 rdev->pm.power_state[state_index].pcie_lanes =
2185 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2186 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2187 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2188 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2189 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2190 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2191 VOLTAGE_GPIO;
2192 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2193 radeon_atombios_lookup_gpio(rdev,
2194 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2195 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2196 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2197 true;
2198 else
2199 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2200 false;
2201 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2202 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2203 VOLTAGE_VDDC;
2204 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2205 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2206 }
2207 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2208 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2209 state_index++;
2210 break;
2211 case 3:
2212 rdev->pm.power_state[state_index].clock_info[0].mclk =
2213 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2214 rdev->pm.power_state[state_index].clock_info[0].sclk =
2215 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2216 /* skip invalid modes */
2217 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2218 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2219 continue;
2220 rdev->pm.power_state[state_index].pcie_lanes =
2221 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2222 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2223 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2224 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2225 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2226 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2227 VOLTAGE_GPIO;
2228 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2229 radeon_atombios_lookup_gpio(rdev,
2230 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2231 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2232 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2233 true;
2234 else
2235 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2236 false;
2237 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2238 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2239 VOLTAGE_VDDC;
2240 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2241 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2242 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2243 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2244 true;
2245 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2246 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2247 }
2248 }
2249 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2250 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2251 state_index++;
2252 break;
2253 }
2254 }
2255 /* last mode is usually default */
2256 if (rdev->pm.default_power_state_index == -1) {
2257 rdev->pm.power_state[state_index - 1].type =
2258 POWER_STATE_TYPE_DEFAULT;
2259 rdev->pm.default_power_state_index = state_index - 1;
2260 rdev->pm.power_state[state_index - 1].default_clock_mode =
2261 &rdev->pm.power_state[state_index - 1].clock_info[0];
2262 rdev->pm.power_state[state_index].flags &=
2263 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2264 rdev->pm.power_state[state_index].misc = 0;
2265 rdev->pm.power_state[state_index].misc2 = 0;
2266 }
2267 return state_index;
2268}
2269
2270static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2271 ATOM_PPLIB_THERMALCONTROLLER *controller)
2272{
2273 struct radeon_i2c_bus_rec i2c_bus;
2274
2275 /* add the i2c bus for thermal/fan chip */
2276 if (controller->ucType > 0) {
2277 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN)
2278 rdev->pm.no_fan = true;
2279 rdev->pm.fan_pulses_per_revolution =
2280 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
2281 if (rdev->pm.fan_pulses_per_revolution) {
2282 rdev->pm.fan_min_rpm = controller->ucFanMinRPM;
2283 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM;
2284 }
2285 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2286 DRM_INFO("Internal thermal controller %s fan control\n",
2287 (controller->ucFanParameters &
2288 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2289 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2290 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2291 DRM_INFO("Internal thermal controller %s fan control\n",
2292 (controller->ucFanParameters &
2293 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2294 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2295 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2296 DRM_INFO("Internal thermal controller %s fan control\n",
2297 (controller->ucFanParameters &
2298 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2299 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2300 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2301 DRM_INFO("Internal thermal controller %s fan control\n",
2302 (controller->ucFanParameters &
2303 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2304 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2305 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2306 DRM_INFO("Internal thermal controller %s fan control\n",
2307 (controller->ucFanParameters &
2308 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2309 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2310 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2311 DRM_INFO("Internal thermal controller %s fan control\n",
2312 (controller->ucFanParameters &
2313 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2314 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2315 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2316 DRM_INFO("Internal thermal controller %s fan control\n",
2317 (controller->ucFanParameters &
2318 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2319 rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2320 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
2321 DRM_INFO("Internal thermal controller %s fan control\n",
2322 (controller->ucFanParameters &
2323 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2324 rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2325 } else if (controller->ucType ==
2326 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
2327 DRM_INFO("External GPIO thermal controller %s fan control\n",
2328 (controller->ucFanParameters &
2329 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2330 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
2331 } else if (controller->ucType ==
2332 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
2333 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
2334 (controller->ucFanParameters &
2335 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2336 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
2337 } else if (controller->ucType ==
2338 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
2339 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
2340 (controller->ucFanParameters &
2341 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2342 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2343 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2344 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2345 pp_lib_thermal_controller_names[controller->ucType],
2346 controller->ucI2cAddress >> 1,
2347 (controller->ucFanParameters &
2348 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2349 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
2350 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2351 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2352 if (rdev->pm.i2c_bus) {
2353 struct i2c_board_info info = { };
2354 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2355 info.addr = controller->ucI2cAddress >> 1;
2356 strlcpy(info.type, name, sizeof(info.type));
2357 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2358 }
2359 } else {
2360 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2361 controller->ucType,
2362 controller->ucI2cAddress >> 1,
2363 (controller->ucFanParameters &
2364 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2365 }
2366 }
2367}
2368
2369void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2370 u16 *vddc, u16 *vddci, u16 *mvdd)
2371{
2372 struct radeon_mode_info *mode_info = &rdev->mode_info;
2373 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2374 u8 frev, crev;
2375 u16 data_offset;
2376 union firmware_info *firmware_info;
2377
2378 *vddc = 0;
2379 *vddci = 0;
2380 *mvdd = 0;
2381
2382 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2383 &frev, &crev, &data_offset)) {
2384 firmware_info =
2385 (union firmware_info *)(mode_info->atom_context->bios +
2386 data_offset);
2387 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2388 if ((frev == 2) && (crev >= 2)) {
2389 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2390 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2391 }
2392 }
2393}
2394
2395static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2396 int state_index, int mode_index,
2397 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2398{
2399 int j;
2400 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2401 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2402 u16 vddc, vddci, mvdd;
2403
2404 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2405
2406 rdev->pm.power_state[state_index].misc = misc;
2407 rdev->pm.power_state[state_index].misc2 = misc2;
2408 rdev->pm.power_state[state_index].pcie_lanes =
2409 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2410 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2411 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2412 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2413 rdev->pm.power_state[state_index].type =
2414 POWER_STATE_TYPE_BATTERY;
2415 break;
2416 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2417 rdev->pm.power_state[state_index].type =
2418 POWER_STATE_TYPE_BALANCED;
2419 break;
2420 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2421 rdev->pm.power_state[state_index].type =
2422 POWER_STATE_TYPE_PERFORMANCE;
2423 break;
2424 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2425 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2426 rdev->pm.power_state[state_index].type =
2427 POWER_STATE_TYPE_PERFORMANCE;
2428 break;
2429 }
2430 rdev->pm.power_state[state_index].flags = 0;
2431 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2432 rdev->pm.power_state[state_index].flags |=
2433 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2434 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2435 rdev->pm.power_state[state_index].type =
2436 POWER_STATE_TYPE_DEFAULT;
2437 rdev->pm.default_power_state_index = state_index;
2438 rdev->pm.power_state[state_index].default_clock_mode =
2439 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2440 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2441 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2442 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2443 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2444 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2445 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2446 } else {
2447 u16 max_vddci = 0;
2448
2449 if (ASIC_IS_DCE4(rdev))
2450 radeon_atom_get_max_voltage(rdev,
2451 SET_VOLTAGE_TYPE_ASIC_VDDCI,
2452 &max_vddci);
2453 /* patch the table values with the default sclk/mclk from firmware info */
2454 for (j = 0; j < mode_index; j++) {
2455 rdev->pm.power_state[state_index].clock_info[j].mclk =
2456 rdev->clock.default_mclk;
2457 rdev->pm.power_state[state_index].clock_info[j].sclk =
2458 rdev->clock.default_sclk;
2459 if (vddc)
2460 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2461 vddc;
2462 if (max_vddci)
2463 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2464 max_vddci;
2465 }
2466 }
2467 }
2468}
2469
2470static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2471 int state_index, int mode_index,
2472 union pplib_clock_info *clock_info)
2473{
2474 u32 sclk, mclk;
2475 u16 vddc;
2476
2477 if (rdev->flags & RADEON_IS_IGP) {
2478 if (rdev->family >= CHIP_PALM) {
2479 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2480 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2481 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2482 } else {
2483 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2484 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2485 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2486 }
2487 } else if (rdev->family >= CHIP_BONAIRE) {
2488 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2489 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2490 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2491 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2492 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2493 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2494 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2495 VOLTAGE_NONE;
2496 } else if (rdev->family >= CHIP_TAHITI) {
2497 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2498 sclk |= clock_info->si.ucEngineClockHigh << 16;
2499 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2500 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2501 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2502 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2503 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2504 VOLTAGE_SW;
2505 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2506 le16_to_cpu(clock_info->si.usVDDC);
2507 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2508 le16_to_cpu(clock_info->si.usVDDCI);
2509 } else if (rdev->family >= CHIP_CEDAR) {
2510 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2511 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2512 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2513 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2514 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2515 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2516 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2517 VOLTAGE_SW;
2518 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2519 le16_to_cpu(clock_info->evergreen.usVDDC);
2520 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2521 le16_to_cpu(clock_info->evergreen.usVDDCI);
2522 } else {
2523 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2524 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2525 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2526 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2527 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2528 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2529 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2530 VOLTAGE_SW;
2531 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2532 le16_to_cpu(clock_info->r600.usVDDC);
2533 }
2534
2535 /* patch up vddc if necessary */
2536 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2537 case ATOM_VIRTUAL_VOLTAGE_ID0:
2538 case ATOM_VIRTUAL_VOLTAGE_ID1:
2539 case ATOM_VIRTUAL_VOLTAGE_ID2:
2540 case ATOM_VIRTUAL_VOLTAGE_ID3:
2541 case ATOM_VIRTUAL_VOLTAGE_ID4:
2542 case ATOM_VIRTUAL_VOLTAGE_ID5:
2543 case ATOM_VIRTUAL_VOLTAGE_ID6:
2544 case ATOM_VIRTUAL_VOLTAGE_ID7:
2545 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2546 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2547 &vddc) == 0)
2548 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2549 break;
2550 default:
2551 break;
2552 }
2553
2554 if (rdev->flags & RADEON_IS_IGP) {
2555 /* skip invalid modes */
2556 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2557 return false;
2558 } else {
2559 /* skip invalid modes */
2560 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2561 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2562 return false;
2563 }
2564 return true;
2565}
2566
2567static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2568{
2569 struct radeon_mode_info *mode_info = &rdev->mode_info;
2570 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2571 union pplib_power_state *power_state;
2572 int i, j;
2573 int state_index = 0, mode_index = 0;
2574 union pplib_clock_info *clock_info;
2575 bool valid;
2576 union power_info *power_info;
2577 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2578 u16 data_offset;
2579 u8 frev, crev;
2580
2581 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2582 &frev, &crev, &data_offset))
2583 return state_index;
2584 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2585
2586 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2587 if (power_info->pplib.ucNumStates == 0)
2588 return state_index;
2589 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2590 power_info->pplib.ucNumStates, GFP_KERNEL);
2591 if (!rdev->pm.power_state)
2592 return state_index;
2593 /* first mode is usually default, followed by low to high */
2594 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2595 mode_index = 0;
2596 power_state = (union pplib_power_state *)
2597 (mode_info->atom_context->bios + data_offset +
2598 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2599 i * power_info->pplib.ucStateEntrySize);
2600 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2601 (mode_info->atom_context->bios + data_offset +
2602 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2603 (power_state->v1.ucNonClockStateIndex *
2604 power_info->pplib.ucNonClockSize));
2605 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2606 ((power_info->pplib.ucStateEntrySize - 1) ?
2607 (power_info->pplib.ucStateEntrySize - 1) : 1),
2608 GFP_KERNEL);
2609 if (!rdev->pm.power_state[i].clock_info)
2610 return state_index;
2611 if (power_info->pplib.ucStateEntrySize - 1) {
2612 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2613 clock_info = (union pplib_clock_info *)
2614 (mode_info->atom_context->bios + data_offset +
2615 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2616 (power_state->v1.ucClockStateIndices[j] *
2617 power_info->pplib.ucClockInfoSize));
2618 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2619 state_index, mode_index,
2620 clock_info);
2621 if (valid)
2622 mode_index++;
2623 }
2624 } else {
2625 rdev->pm.power_state[state_index].clock_info[0].mclk =
2626 rdev->clock.default_mclk;
2627 rdev->pm.power_state[state_index].clock_info[0].sclk =
2628 rdev->clock.default_sclk;
2629 mode_index++;
2630 }
2631 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2632 if (mode_index) {
2633 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2634 non_clock_info);
2635 state_index++;
2636 }
2637 }
2638 /* if multiple clock modes, mark the lowest as no display */
2639 for (i = 0; i < state_index; i++) {
2640 if (rdev->pm.power_state[i].num_clock_modes > 1)
2641 rdev->pm.power_state[i].clock_info[0].flags |=
2642 RADEON_PM_MODE_NO_DISPLAY;
2643 }
2644 /* first mode is usually default */
2645 if (rdev->pm.default_power_state_index == -1) {
2646 rdev->pm.power_state[0].type =
2647 POWER_STATE_TYPE_DEFAULT;
2648 rdev->pm.default_power_state_index = 0;
2649 rdev->pm.power_state[0].default_clock_mode =
2650 &rdev->pm.power_state[0].clock_info[0];
2651 }
2652 return state_index;
2653}
2654
2655static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2656{
2657 struct radeon_mode_info *mode_info = &rdev->mode_info;
2658 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2659 union pplib_power_state *power_state;
2660 int i, j, non_clock_array_index, clock_array_index;
2661 int state_index = 0, mode_index = 0;
2662 union pplib_clock_info *clock_info;
2663 struct _StateArray *state_array;
2664 struct _ClockInfoArray *clock_info_array;
2665 struct _NonClockInfoArray *non_clock_info_array;
2666 bool valid;
2667 union power_info *power_info;
2668 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2669 u16 data_offset;
2670 u8 frev, crev;
2671 u8 *power_state_offset;
2672
2673 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2674 &frev, &crev, &data_offset))
2675 return state_index;
2676 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2677
2678 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2679 state_array = (struct _StateArray *)
2680 (mode_info->atom_context->bios + data_offset +
2681 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2682 clock_info_array = (struct _ClockInfoArray *)
2683 (mode_info->atom_context->bios + data_offset +
2684 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2685 non_clock_info_array = (struct _NonClockInfoArray *)
2686 (mode_info->atom_context->bios + data_offset +
2687 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2688 if (state_array->ucNumEntries == 0)
2689 return state_index;
2690 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2691 state_array->ucNumEntries, GFP_KERNEL);
2692 if (!rdev->pm.power_state)
2693 return state_index;
2694 power_state_offset = (u8 *)state_array->states;
2695 for (i = 0; i < state_array->ucNumEntries; i++) {
2696 mode_index = 0;
2697 power_state = (union pplib_power_state *)power_state_offset;
2698 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2699 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2700 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2701 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2702 (power_state->v2.ucNumDPMLevels ?
2703 power_state->v2.ucNumDPMLevels : 1),
2704 GFP_KERNEL);
2705 if (!rdev->pm.power_state[i].clock_info)
2706 return state_index;
2707 if (power_state->v2.ucNumDPMLevels) {
2708 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2709 clock_array_index = power_state->v2.clockInfoIndex[j];
2710 clock_info = (union pplib_clock_info *)
2711 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2712 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2713 state_index, mode_index,
2714 clock_info);
2715 if (valid)
2716 mode_index++;
2717 }
2718 } else {
2719 rdev->pm.power_state[state_index].clock_info[0].mclk =
2720 rdev->clock.default_mclk;
2721 rdev->pm.power_state[state_index].clock_info[0].sclk =
2722 rdev->clock.default_sclk;
2723 mode_index++;
2724 }
2725 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2726 if (mode_index) {
2727 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2728 non_clock_info);
2729 state_index++;
2730 }
2731 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2732 }
2733 /* if multiple clock modes, mark the lowest as no display */
2734 for (i = 0; i < state_index; i++) {
2735 if (rdev->pm.power_state[i].num_clock_modes > 1)
2736 rdev->pm.power_state[i].clock_info[0].flags |=
2737 RADEON_PM_MODE_NO_DISPLAY;
2738 }
2739 /* first mode is usually default */
2740 if (rdev->pm.default_power_state_index == -1) {
2741 rdev->pm.power_state[0].type =
2742 POWER_STATE_TYPE_DEFAULT;
2743 rdev->pm.default_power_state_index = 0;
2744 rdev->pm.power_state[0].default_clock_mode =
2745 &rdev->pm.power_state[0].clock_info[0];
2746 }
2747 return state_index;
2748}
2749
2750void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2751{
2752 struct radeon_mode_info *mode_info = &rdev->mode_info;
2753 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2754 u16 data_offset;
2755 u8 frev, crev;
2756 int state_index = 0;
2757
2758 rdev->pm.default_power_state_index = -1;
2759
2760 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2761 &frev, &crev, &data_offset)) {
2762 switch (frev) {
2763 case 1:
2764 case 2:
2765 case 3:
2766 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2767 break;
2768 case 4:
2769 case 5:
2770 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2771 break;
2772 case 6:
2773 state_index = radeon_atombios_parse_power_table_6(rdev);
2774 break;
2775 default:
2776 break;
2777 }
2778 }
2779
2780 if (state_index == 0) {
2781 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2782 if (rdev->pm.power_state) {
2783 rdev->pm.power_state[0].clock_info =
2784 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2785 if (rdev->pm.power_state[0].clock_info) {
2786 /* add the default mode */
2787 rdev->pm.power_state[state_index].type =
2788 POWER_STATE_TYPE_DEFAULT;
2789 rdev->pm.power_state[state_index].num_clock_modes = 1;
2790 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2791 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2792 rdev->pm.power_state[state_index].default_clock_mode =
2793 &rdev->pm.power_state[state_index].clock_info[0];
2794 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2795 rdev->pm.power_state[state_index].pcie_lanes = 16;
2796 rdev->pm.default_power_state_index = state_index;
2797 rdev->pm.power_state[state_index].flags = 0;
2798 state_index++;
2799 }
2800 }
2801 }
2802
2803 rdev->pm.num_power_states = state_index;
2804
2805 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2806 rdev->pm.current_clock_mode_index = 0;
2807 if (rdev->pm.default_power_state_index >= 0)
2808 rdev->pm.current_vddc =
2809 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2810 else
2811 rdev->pm.current_vddc = 0;
2812}
2813
2814union get_clock_dividers {
2815 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2816 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2817 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2818 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2819 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2820 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2821 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2822};
2823
2824int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2825 u8 clock_type,
2826 u32 clock,
2827 bool strobe_mode,
2828 struct atom_clock_dividers *dividers)
2829{
2830 union get_clock_dividers args;
2831 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2832 u8 frev, crev;
2833
2834 memset(&args, 0, sizeof(args));
2835 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2836
2837 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2838 return -EINVAL;
2839
2840 switch (crev) {
2841 case 1:
2842 /* r4xx, r5xx */
2843 args.v1.ucAction = clock_type;
2844 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
2845
2846 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2847
2848 dividers->post_div = args.v1.ucPostDiv;
2849 dividers->fb_div = args.v1.ucFbDiv;
2850 dividers->enable_post_div = true;
2851 break;
2852 case 2:
2853 case 3:
2854 case 5:
2855 /* r6xx, r7xx, evergreen, ni, si */
2856 if (rdev->family <= CHIP_RV770) {
2857 args.v2.ucAction = clock_type;
2858 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
2859
2860 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2861
2862 dividers->post_div = args.v2.ucPostDiv;
2863 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2864 dividers->ref_div = args.v2.ucAction;
2865 if (rdev->family == CHIP_RV770) {
2866 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2867 true : false;
2868 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2869 } else
2870 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2871 } else {
2872 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2873 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2874
2875 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2876
2877 dividers->post_div = args.v3.ucPostDiv;
2878 dividers->enable_post_div = (args.v3.ucCntlFlag &
2879 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2880 dividers->enable_dithen = (args.v3.ucCntlFlag &
2881 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2882 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2883 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2884 dividers->ref_div = args.v3.ucRefDiv;
2885 dividers->vco_mode = (args.v3.ucCntlFlag &
2886 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2887 } else {
2888 /* for SI we use ComputeMemoryClockParam for memory plls */
2889 if (rdev->family >= CHIP_TAHITI)
2890 return -EINVAL;
2891 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2892 if (strobe_mode)
2893 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2894
2895 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2896
2897 dividers->post_div = args.v5.ucPostDiv;
2898 dividers->enable_post_div = (args.v5.ucCntlFlag &
2899 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2900 dividers->enable_dithen = (args.v5.ucCntlFlag &
2901 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2902 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2903 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2904 dividers->ref_div = args.v5.ucRefDiv;
2905 dividers->vco_mode = (args.v5.ucCntlFlag &
2906 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2907 }
2908 }
2909 break;
2910 case 4:
2911 /* fusion */
2912 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
2913
2914 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2915
2916 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2917 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2918 break;
2919 case 6:
2920 /* CI */
2921 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2922 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2923 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2924
2925 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2926
2927 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2928 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2929 dividers->ref_div = args.v6_out.ucPllRefDiv;
2930 dividers->post_div = args.v6_out.ucPllPostDiv;
2931 dividers->flags = args.v6_out.ucPllCntlFlag;
2932 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2933 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2934 break;
2935 default:
2936 return -EINVAL;
2937 }
2938 return 0;
2939}
2940
2941int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2942 u32 clock,
2943 bool strobe_mode,
2944 struct atom_mpll_param *mpll_param)
2945{
2946 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2947 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2948 u8 frev, crev;
2949
2950 memset(&args, 0, sizeof(args));
2951 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2952
2953 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2954 return -EINVAL;
2955
2956 switch (frev) {
2957 case 2:
2958 switch (crev) {
2959 case 1:
2960 /* SI */
2961 args.ulClock = cpu_to_le32(clock); /* 10 khz */
2962 args.ucInputFlag = 0;
2963 if (strobe_mode)
2964 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2965
2966 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2967
2968 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2969 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2970 mpll_param->post_div = args.ucPostDiv;
2971 mpll_param->dll_speed = args.ucDllSpeed;
2972 mpll_param->bwcntl = args.ucBWCntl;
2973 mpll_param->vco_mode =
2974 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
2975 mpll_param->yclk_sel =
2976 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2977 mpll_param->qdr =
2978 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2979 mpll_param->half_rate =
2980 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
2981 break;
2982 default:
2983 return -EINVAL;
2984 }
2985 break;
2986 default:
2987 return -EINVAL;
2988 }
2989 return 0;
2990}
2991
2992void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2993{
2994 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2995 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2996
2997 args.ucEnable = enable;
2998
2999 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3000}
3001
3002uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
3003{
3004 GET_ENGINE_CLOCK_PS_ALLOCATION args;
3005 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
3006
3007 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3008 return le32_to_cpu(args.ulReturnEngineClock);
3009}
3010
3011uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
3012{
3013 GET_MEMORY_CLOCK_PS_ALLOCATION args;
3014 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
3015
3016 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3017 return le32_to_cpu(args.ulReturnMemoryClock);
3018}
3019
3020void radeon_atom_set_engine_clock(struct radeon_device *rdev,
3021 uint32_t eng_clock)
3022{
3023 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3024 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
3025
3026 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
3027
3028 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3029}
3030
3031void radeon_atom_set_memory_clock(struct radeon_device *rdev,
3032 uint32_t mem_clock)
3033{
3034 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3035 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
3036
3037 if (rdev->flags & RADEON_IS_IGP)
3038 return;
3039
3040 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
3041
3042 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3043}
3044
3045void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
3046 u32 eng_clock, u32 mem_clock)
3047{
3048 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3049 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3050 u32 tmp;
3051
3052 memset(&args, 0, sizeof(args));
3053
3054 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
3055 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
3056
3057 args.ulTargetEngineClock = cpu_to_le32(tmp);
3058 if (mem_clock)
3059 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
3060
3061 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3062}
3063
3064void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3065 u32 mem_clock)
3066{
3067 u32 args;
3068 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3069
3070 args = cpu_to_le32(mem_clock); /* 10 khz */
3071
3072 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3073}
3074
3075void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3076 u32 mem_clock)
3077{
3078 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3079 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3080 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
3081
3082 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */
3083
3084 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3085}
3086
3087union set_voltage {
3088 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
3089 struct _SET_VOLTAGE_PARAMETERS v1;
3090 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
3091 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
3092};
3093
3094void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3095{
3096 union set_voltage args;
3097 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3098 u8 frev, crev, volt_index = voltage_level;
3099
3100 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3101 return;
3102
3103 /* 0xff01 is a flag rather then an actual voltage */
3104 if (voltage_level == 0xff01)
3105 return;
3106
3107 switch (crev) {
3108 case 1:
3109 args.v1.ucVoltageType = voltage_type;
3110 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3111 args.v1.ucVoltageIndex = volt_index;
3112 break;
3113 case 2:
3114 args.v2.ucVoltageType = voltage_type;
3115 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3116 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3117 break;
3118 case 3:
3119 args.v3.ucVoltageType = voltage_type;
3120 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3121 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3122 break;
3123 default:
3124 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3125 return;
3126 }
3127
3128 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3129}
3130
3131int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3132 u16 voltage_id, u16 *voltage)
3133{
3134 union set_voltage args;
3135 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3136 u8 frev, crev;
3137
3138 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3139 return -EINVAL;
3140
3141 switch (crev) {
3142 case 1:
3143 return -EINVAL;
3144 case 2:
3145 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3146 args.v2.ucVoltageMode = 0;
3147 args.v2.usVoltageLevel = 0;
3148
3149 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3150
3151 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3152 break;
3153 case 3:
3154 args.v3.ucVoltageType = voltage_type;
3155 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3156 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3157
3158 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3159
3160 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3161 break;
3162 default:
3163 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3164 return -EINVAL;
3165 }
3166
3167 return 0;
3168}
3169
3170int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3171 u16 *voltage,
3172 u16 leakage_idx)
3173{
3174 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3175}
3176
3177int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3178 u16 *leakage_id)
3179{
3180 union set_voltage args;
3181 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3182 u8 frev, crev;
3183
3184 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3185 return -EINVAL;
3186
3187 switch (crev) {
3188 case 3:
3189 case 4:
3190 args.v3.ucVoltageType = 0;
3191 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
3192 args.v3.usVoltageLevel = 0;
3193
3194 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3195
3196 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
3197 break;
3198 default:
3199 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3200 return -EINVAL;
3201 }
3202
3203 return 0;
3204}
3205
3206int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3207 u16 *vddc, u16 *vddci,
3208 u16 virtual_voltage_id,
3209 u16 vbios_voltage_id)
3210{
3211 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
3212 u8 frev, crev;
3213 u16 data_offset, size;
3214 int i, j;
3215 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
3216 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
3217
3218 *vddc = 0;
3219 *vddci = 0;
3220
3221 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3222 &frev, &crev, &data_offset))
3223 return -EINVAL;
3224
3225 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
3226 (rdev->mode_info.atom_context->bios + data_offset);
3227
3228 switch (frev) {
3229 case 1:
3230 return -EINVAL;
3231 case 2:
3232 switch (crev) {
3233 case 1:
3234 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
3235 return -EINVAL;
3236 leakage_bin = (u16 *)
3237 (rdev->mode_info.atom_context->bios + data_offset +
3238 le16_to_cpu(profile->usLeakageBinArrayOffset));
3239 vddc_id_buf = (u16 *)
3240 (rdev->mode_info.atom_context->bios + data_offset +
3241 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
3242 vddc_buf = (u16 *)
3243 (rdev->mode_info.atom_context->bios + data_offset +
3244 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
3245 vddci_id_buf = (u16 *)
3246 (rdev->mode_info.atom_context->bios + data_offset +
3247 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
3248 vddci_buf = (u16 *)
3249 (rdev->mode_info.atom_context->bios + data_offset +
3250 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
3251
3252 if (profile->ucElbVDDC_Num > 0) {
3253 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
3254 if (vddc_id_buf[i] == virtual_voltage_id) {
3255 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3256 if (vbios_voltage_id <= leakage_bin[j]) {
3257 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
3258 break;
3259 }
3260 }
3261 break;
3262 }
3263 }
3264 }
3265 if (profile->ucElbVDDCI_Num > 0) {
3266 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
3267 if (vddci_id_buf[i] == virtual_voltage_id) {
3268 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3269 if (vbios_voltage_id <= leakage_bin[j]) {
3270 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
3271 break;
3272 }
3273 }
3274 break;
3275 }
3276 }
3277 }
3278 break;
3279 default:
3280 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3281 return -EINVAL;
3282 }
3283 break;
3284 default:
3285 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3286 return -EINVAL;
3287 }
3288
3289 return 0;
3290}
3291
3292union get_voltage_info {
3293 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
3294 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
3295};
3296
3297int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
3298 u16 virtual_voltage_id,
3299 u16 *voltage)
3300{
3301 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
3302 u32 entry_id;
3303 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
3304 union get_voltage_info args;
3305
3306 for (entry_id = 0; entry_id < count; entry_id++) {
3307 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
3308 virtual_voltage_id)
3309 break;
3310 }
3311
3312 if (entry_id >= count)
3313 return -EINVAL;
3314
3315 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
3316 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
3317 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
3318 args.in.ulSCLKFreq =
3319 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
3320
3321 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3322
3323 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
3324
3325 return 0;
3326}
3327
3328int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3329 u16 voltage_level, u8 voltage_type,
3330 u32 *gpio_value, u32 *gpio_mask)
3331{
3332 union set_voltage args;
3333 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3334 u8 frev, crev;
3335
3336 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3337 return -EINVAL;
3338
3339 switch (crev) {
3340 case 1:
3341 return -EINVAL;
3342 case 2:
3343 args.v2.ucVoltageType = voltage_type;
3344 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3345 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3346
3347 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3348
3349 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3350
3351 args.v2.ucVoltageType = voltage_type;
3352 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3353 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3354
3355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3356
3357 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3358 break;
3359 default:
3360 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3361 return -EINVAL;
3362 }
3363
3364 return 0;
3365}
3366
3367union voltage_object_info {
3368 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3369 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3370 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3371};
3372
3373union voltage_object {
3374 struct _ATOM_VOLTAGE_OBJECT v1;
3375 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3376 union _ATOM_VOLTAGE_OBJECT_V3 v3;
3377};
3378
3379static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3380 u8 voltage_type)
3381{
3382 u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3383 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3384 u8 *start = (u8 *)v1;
3385
3386 while (offset < size) {
3387 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3388 if (vo->ucVoltageType == voltage_type)
3389 return vo;
3390 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3391 vo->asFormula.ucNumOfVoltageEntries;
3392 }
3393 return NULL;
3394}
3395
3396static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3397 u8 voltage_type)
3398{
3399 u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3400 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3401 u8 *start = (u8*)v2;
3402
3403 while (offset < size) {
3404 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3405 if (vo->ucVoltageType == voltage_type)
3406 return vo;
3407 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3408 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3409 }
3410 return NULL;
3411}
3412
3413static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3414 u8 voltage_type, u8 voltage_mode)
3415{
3416 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3417 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3418 u8 *start = (u8*)v3;
3419
3420 while (offset < size) {
3421 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3422 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3423 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3424 return vo;
3425 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3426 }
3427 return NULL;
3428}
3429
3430bool
3431radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3432 u8 voltage_type, u8 voltage_mode)
3433{
3434 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3435 u8 frev, crev;
3436 u16 data_offset, size;
3437 union voltage_object_info *voltage_info;
3438 union voltage_object *voltage_object = NULL;
3439
3440 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3441 &frev, &crev, &data_offset)) {
3442 voltage_info = (union voltage_object_info *)
3443 (rdev->mode_info.atom_context->bios + data_offset);
3444
3445 switch (frev) {
3446 case 1:
3447 case 2:
3448 switch (crev) {
3449 case 1:
3450 voltage_object = (union voltage_object *)
3451 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3452 if (voltage_object &&
3453 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3454 return true;
3455 break;
3456 case 2:
3457 voltage_object = (union voltage_object *)
3458 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3459 if (voltage_object &&
3460 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3461 return true;
3462 break;
3463 default:
3464 DRM_ERROR("unknown voltage object table\n");
3465 return false;
3466 }
3467 break;
3468 case 3:
3469 switch (crev) {
3470 case 1:
3471 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3472 voltage_type, voltage_mode))
3473 return true;
3474 break;
3475 default:
3476 DRM_ERROR("unknown voltage object table\n");
3477 return false;
3478 }
3479 break;
3480 default:
3481 DRM_ERROR("unknown voltage object table\n");
3482 return false;
3483 }
3484
3485 }
3486 return false;
3487}
3488
3489int radeon_atom_get_svi2_info(struct radeon_device *rdev,
3490 u8 voltage_type,
3491 u8 *svd_gpio_id, u8 *svc_gpio_id)
3492{
3493 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3494 u8 frev, crev;
3495 u16 data_offset, size;
3496 union voltage_object_info *voltage_info;
3497 union voltage_object *voltage_object = NULL;
3498
3499 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3500 &frev, &crev, &data_offset)) {
3501 voltage_info = (union voltage_object_info *)
3502 (rdev->mode_info.atom_context->bios + data_offset);
3503
3504 switch (frev) {
3505 case 3:
3506 switch (crev) {
3507 case 1:
3508 voltage_object = (union voltage_object *)
3509 atom_lookup_voltage_object_v3(&voltage_info->v3,
3510 voltage_type,
3511 VOLTAGE_OBJ_SVID2);
3512 if (voltage_object) {
3513 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
3514 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
3515 } else {
3516 return -EINVAL;
3517 }
3518 break;
3519 default:
3520 DRM_ERROR("unknown voltage object table\n");
3521 return -EINVAL;
3522 }
3523 break;
3524 default:
3525 DRM_ERROR("unknown voltage object table\n");
3526 return -EINVAL;
3527 }
3528
3529 }
3530 return 0;
3531}
3532
3533int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3534 u8 voltage_type, u16 *max_voltage)
3535{
3536 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3537 u8 frev, crev;
3538 u16 data_offset, size;
3539 union voltage_object_info *voltage_info;
3540 union voltage_object *voltage_object = NULL;
3541
3542 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3543 &frev, &crev, &data_offset)) {
3544 voltage_info = (union voltage_object_info *)
3545 (rdev->mode_info.atom_context->bios + data_offset);
3546
3547 switch (crev) {
3548 case 1:
3549 voltage_object = (union voltage_object *)
3550 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3551 if (voltage_object) {
3552 ATOM_VOLTAGE_FORMULA *formula =
3553 &voltage_object->v1.asFormula;
3554 if (formula->ucFlag & 1)
3555 *max_voltage =
3556 le16_to_cpu(formula->usVoltageBaseLevel) +
3557 formula->ucNumOfVoltageEntries / 2 *
3558 le16_to_cpu(formula->usVoltageStep);
3559 else
3560 *max_voltage =
3561 le16_to_cpu(formula->usVoltageBaseLevel) +
3562 (formula->ucNumOfVoltageEntries - 1) *
3563 le16_to_cpu(formula->usVoltageStep);
3564 return 0;
3565 }
3566 break;
3567 case 2:
3568 voltage_object = (union voltage_object *)
3569 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3570 if (voltage_object) {
3571 ATOM_VOLTAGE_FORMULA_V2 *formula =
3572 &voltage_object->v2.asFormula;
3573 if (formula->ucNumOfVoltageEntries) {
3574 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *)
3575 ((u8 *)&formula->asVIDAdjustEntries[0] +
3576 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
3577 *max_voltage =
3578 le16_to_cpu(lut->usVoltageValue);
3579 return 0;
3580 }
3581 }
3582 break;
3583 default:
3584 DRM_ERROR("unknown voltage object table\n");
3585 return -EINVAL;
3586 }
3587
3588 }
3589 return -EINVAL;
3590}
3591
3592int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3593 u8 voltage_type, u16 *min_voltage)
3594{
3595 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3596 u8 frev, crev;
3597 u16 data_offset, size;
3598 union voltage_object_info *voltage_info;
3599 union voltage_object *voltage_object = NULL;
3600
3601 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3602 &frev, &crev, &data_offset)) {
3603 voltage_info = (union voltage_object_info *)
3604 (rdev->mode_info.atom_context->bios + data_offset);
3605
3606 switch (crev) {
3607 case 1:
3608 voltage_object = (union voltage_object *)
3609 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3610 if (voltage_object) {
3611 ATOM_VOLTAGE_FORMULA *formula =
3612 &voltage_object->v1.asFormula;
3613 *min_voltage =
3614 le16_to_cpu(formula->usVoltageBaseLevel);
3615 return 0;
3616 }
3617 break;
3618 case 2:
3619 voltage_object = (union voltage_object *)
3620 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3621 if (voltage_object) {
3622 ATOM_VOLTAGE_FORMULA_V2 *formula =
3623 &voltage_object->v2.asFormula;
3624 if (formula->ucNumOfVoltageEntries) {
3625 *min_voltage =
3626 le16_to_cpu(formula->asVIDAdjustEntries[
3627 0
3628 ].usVoltageValue);
3629 return 0;
3630 }
3631 }
3632 break;
3633 default:
3634 DRM_ERROR("unknown voltage object table\n");
3635 return -EINVAL;
3636 }
3637
3638 }
3639 return -EINVAL;
3640}
3641
3642int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3643 u8 voltage_type, u16 *voltage_step)
3644{
3645 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3646 u8 frev, crev;
3647 u16 data_offset, size;
3648 union voltage_object_info *voltage_info;
3649 union voltage_object *voltage_object = NULL;
3650
3651 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3652 &frev, &crev, &data_offset)) {
3653 voltage_info = (union voltage_object_info *)
3654 (rdev->mode_info.atom_context->bios + data_offset);
3655
3656 switch (crev) {
3657 case 1:
3658 voltage_object = (union voltage_object *)
3659 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3660 if (voltage_object) {
3661 ATOM_VOLTAGE_FORMULA *formula =
3662 &voltage_object->v1.asFormula;
3663 if (formula->ucFlag & 1)
3664 *voltage_step =
3665 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3666 else
3667 *voltage_step =
3668 le16_to_cpu(formula->usVoltageStep);
3669 return 0;
3670 }
3671 break;
3672 case 2:
3673 return -EINVAL;
3674 default:
3675 DRM_ERROR("unknown voltage object table\n");
3676 return -EINVAL;
3677 }
3678
3679 }
3680 return -EINVAL;
3681}
3682
3683int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3684 u8 voltage_type,
3685 u16 nominal_voltage,
3686 u16 *true_voltage)
3687{
3688 u16 min_voltage, max_voltage, voltage_step;
3689
3690 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3691 return -EINVAL;
3692 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3693 return -EINVAL;
3694 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3695 return -EINVAL;
3696
3697 if (nominal_voltage <= min_voltage)
3698 *true_voltage = min_voltage;
3699 else if (nominal_voltage >= max_voltage)
3700 *true_voltage = max_voltage;
3701 else
3702 *true_voltage = min_voltage +
3703 ((nominal_voltage - min_voltage) / voltage_step) *
3704 voltage_step;
3705
3706 return 0;
3707}
3708
3709int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3710 u8 voltage_type, u8 voltage_mode,
3711 struct atom_voltage_table *voltage_table)
3712{
3713 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3714 u8 frev, crev;
3715 u16 data_offset, size;
3716 int i, ret;
3717 union voltage_object_info *voltage_info;
3718 union voltage_object *voltage_object = NULL;
3719
3720 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3721 &frev, &crev, &data_offset)) {
3722 voltage_info = (union voltage_object_info *)
3723 (rdev->mode_info.atom_context->bios + data_offset);
3724
3725 switch (frev) {
3726 case 1:
3727 case 2:
3728 switch (crev) {
3729 case 1:
3730 DRM_ERROR("old table version %d, %d\n", frev, crev);
3731 return -EINVAL;
3732 case 2:
3733 voltage_object = (union voltage_object *)
3734 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3735 if (voltage_object) {
3736 ATOM_VOLTAGE_FORMULA_V2 *formula =
3737 &voltage_object->v2.asFormula;
3738 VOLTAGE_LUT_ENTRY *lut;
3739 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3740 return -EINVAL;
3741 lut = &formula->asVIDAdjustEntries[0];
3742 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3743 voltage_table->entries[i].value =
3744 le16_to_cpu(lut->usVoltageValue);
3745 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3746 voltage_table->entries[i].value,
3747 voltage_type,
3748 &voltage_table->entries[i].smio_low,
3749 &voltage_table->mask_low);
3750 if (ret)
3751 return ret;
3752 lut = (VOLTAGE_LUT_ENTRY *)
3753 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
3754 }
3755 voltage_table->count = formula->ucNumOfVoltageEntries;
3756 return 0;
3757 }
3758 break;
3759 default:
3760 DRM_ERROR("unknown voltage object table\n");
3761 return -EINVAL;
3762 }
3763 break;
3764 case 3:
3765 switch (crev) {
3766 case 1:
3767 voltage_object = (union voltage_object *)
3768 atom_lookup_voltage_object_v3(&voltage_info->v3,
3769 voltage_type, voltage_mode);
3770 if (voltage_object) {
3771 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3772 &voltage_object->v3.asGpioVoltageObj;
3773 VOLTAGE_LUT_ENTRY_V2 *lut;
3774 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3775 return -EINVAL;
3776 lut = &gpio->asVolGpioLut[0];
3777 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3778 voltage_table->entries[i].value =
3779 le16_to_cpu(lut->usVoltageValue);
3780 voltage_table->entries[i].smio_low =
3781 le32_to_cpu(lut->ulVoltageId);
3782 lut = (VOLTAGE_LUT_ENTRY_V2 *)
3783 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
3784 }
3785 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3786 voltage_table->count = gpio->ucGpioEntryNum;
3787 voltage_table->phase_delay = gpio->ucPhaseDelay;
3788 return 0;
3789 }
3790 break;
3791 default:
3792 DRM_ERROR("unknown voltage object table\n");
3793 return -EINVAL;
3794 }
3795 break;
3796 default:
3797 DRM_ERROR("unknown voltage object table\n");
3798 return -EINVAL;
3799 }
3800 }
3801 return -EINVAL;
3802}
3803
3804union vram_info {
3805 struct _ATOM_VRAM_INFO_V3 v1_3;
3806 struct _ATOM_VRAM_INFO_V4 v1_4;
3807 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3808};
3809
3810int radeon_atom_get_memory_info(struct radeon_device *rdev,
3811 u8 module_index, struct atom_memory_info *mem_info)
3812{
3813 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3814 u8 frev, crev, i;
3815 u16 data_offset, size;
3816 union vram_info *vram_info;
3817
3818 memset(mem_info, 0, sizeof(struct atom_memory_info));
3819
3820 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3821 &frev, &crev, &data_offset)) {
3822 vram_info = (union vram_info *)
3823 (rdev->mode_info.atom_context->bios + data_offset);
3824 switch (frev) {
3825 case 1:
3826 switch (crev) {
3827 case 3:
3828 /* r6xx */
3829 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3830 ATOM_VRAM_MODULE_V3 *vram_module =
3831 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3832
3833 for (i = 0; i < module_index; i++) {
3834 if (le16_to_cpu(vram_module->usSize) == 0)
3835 return -EINVAL;
3836 vram_module = (ATOM_VRAM_MODULE_V3 *)
3837 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3838 }
3839 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3840 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3841 } else
3842 return -EINVAL;
3843 break;
3844 case 4:
3845 /* r7xx, evergreen */
3846 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3847 ATOM_VRAM_MODULE_V4 *vram_module =
3848 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3849
3850 for (i = 0; i < module_index; i++) {
3851 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3852 return -EINVAL;
3853 vram_module = (ATOM_VRAM_MODULE_V4 *)
3854 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3855 }
3856 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3857 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3858 } else
3859 return -EINVAL;
3860 break;
3861 default:
3862 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3863 return -EINVAL;
3864 }
3865 break;
3866 case 2:
3867 switch (crev) {
3868 case 1:
3869 /* ni */
3870 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3871 ATOM_VRAM_MODULE_V7 *vram_module =
3872 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3873
3874 for (i = 0; i < module_index; i++) {
3875 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3876 return -EINVAL;
3877 vram_module = (ATOM_VRAM_MODULE_V7 *)
3878 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3879 }
3880 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3881 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3882 } else
3883 return -EINVAL;
3884 break;
3885 default:
3886 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3887 return -EINVAL;
3888 }
3889 break;
3890 default:
3891 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3892 return -EINVAL;
3893 }
3894 return 0;
3895 }
3896 return -EINVAL;
3897}
3898
3899int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3900 bool gddr5, u8 module_index,
3901 struct atom_memory_clock_range_table *mclk_range_table)
3902{
3903 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3904 u8 frev, crev, i;
3905 u16 data_offset, size;
3906 union vram_info *vram_info;
3907 u32 mem_timing_size = gddr5 ?
3908 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3909
3910 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3911
3912 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3913 &frev, &crev, &data_offset)) {
3914 vram_info = (union vram_info *)
3915 (rdev->mode_info.atom_context->bios + data_offset);
3916 switch (frev) {
3917 case 1:
3918 switch (crev) {
3919 case 3:
3920 DRM_ERROR("old table version %d, %d\n", frev, crev);
3921 return -EINVAL;
3922 case 4:
3923 /* r7xx, evergreen */
3924 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3925 ATOM_VRAM_MODULE_V4 *vram_module =
3926 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3927 ATOM_MEMORY_TIMING_FORMAT *format;
3928
3929 for (i = 0; i < module_index; i++) {
3930 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3931 return -EINVAL;
3932 vram_module = (ATOM_VRAM_MODULE_V4 *)
3933 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3934 }
3935 mclk_range_table->num_entries = (u8)
3936 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3937 mem_timing_size);
3938 format = &vram_module->asMemTiming[0];
3939 for (i = 0; i < mclk_range_table->num_entries; i++) {
3940 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3941 format = (ATOM_MEMORY_TIMING_FORMAT *)
3942 ((u8 *)format + mem_timing_size);
3943 }
3944 } else
3945 return -EINVAL;
3946 break;
3947 default:
3948 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3949 return -EINVAL;
3950 }
3951 break;
3952 case 2:
3953 DRM_ERROR("new table version %d, %d\n", frev, crev);
3954 return -EINVAL;
3955 default:
3956 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3957 return -EINVAL;
3958 }
3959 return 0;
3960 }
3961 return -EINVAL;
3962}
3963
3964#define MEM_ID_MASK 0xff000000
3965#define MEM_ID_SHIFT 24
3966#define CLOCK_RANGE_MASK 0x00ffffff
3967#define CLOCK_RANGE_SHIFT 0
3968#define LOW_NIBBLE_MASK 0xf
3969#define DATA_EQU_PREV 0
3970#define DATA_FROM_TABLE 4
3971
3972int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3973 u8 module_index,
3974 struct atom_mc_reg_table *reg_table)
3975{
3976 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3977 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3978 u32 i = 0, j;
3979 u16 data_offset, size;
3980 union vram_info *vram_info;
3981
3982 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
3983
3984 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3985 &frev, &crev, &data_offset)) {
3986 vram_info = (union vram_info *)
3987 (rdev->mode_info.atom_context->bios + data_offset);
3988 switch (frev) {
3989 case 1:
3990 DRM_ERROR("old table version %d, %d\n", frev, crev);
3991 return -EINVAL;
3992 case 2:
3993 switch (crev) {
3994 case 1:
3995 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3996 ATOM_INIT_REG_BLOCK *reg_block =
3997 (ATOM_INIT_REG_BLOCK *)
3998 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
3999 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
4000 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4001 ((u8 *)reg_block + (2 * sizeof(u16)) +
4002 le16_to_cpu(reg_block->usRegIndexTblSize));
4003 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
4004 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
4005 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
4006 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
4007 return -EINVAL;
4008 while (i < num_entries) {
4009 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
4010 break;
4011 reg_table->mc_reg_address[i].s1 =
4012 (u16)(le16_to_cpu(format->usRegIndex));
4013 reg_table->mc_reg_address[i].pre_reg_data =
4014 (u8)(format->ucPreRegDataLength);
4015 i++;
4016 format = (ATOM_INIT_REG_INDEX_FORMAT *)
4017 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
4018 }
4019 reg_table->last = i;
4020 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
4021 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
4022 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
4023 >> MEM_ID_SHIFT);
4024 if (module_index == t_mem_id) {
4025 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
4026 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
4027 >> CLOCK_RANGE_SHIFT);
4028 for (i = 0, j = 1; i < reg_table->last; i++) {
4029 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
4030 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4031 (u32)le32_to_cpu(*((u32 *)reg_data + j));
4032 j++;
4033 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
4034 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4035 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
4036 }
4037 }
4038 num_ranges++;
4039 }
4040 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4041 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
4042 }
4043 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
4044 return -EINVAL;
4045 reg_table->num_entries = num_ranges;
4046 } else
4047 return -EINVAL;
4048 break;
4049 default:
4050 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4051 return -EINVAL;
4052 }
4053 break;
4054 default:
4055 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4056 return -EINVAL;
4057 }
4058 return 0;
4059 }
4060 return -EINVAL;
4061}
4062
4063void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
4064{
4065 struct radeon_device *rdev = dev->dev_private;
4066 uint32_t bios_2_scratch, bios_6_scratch;
4067
4068 if (rdev->family >= CHIP_R600) {
4069 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4070 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4071 } else {
4072 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4073 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4074 }
4075
4076 /* let the bios control the backlight */
4077 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
4078
4079 /* tell the bios not to handle mode switching */
4080 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
4081
4082 /* clear the vbios dpms state */
4083 if (ASIC_IS_DCE4(rdev))
4084 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
4085
4086 if (rdev->family >= CHIP_R600) {
4087 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4088 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4089 } else {
4090 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4091 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4092 }
4093
4094}
4095
4096void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
4097{
4098 uint32_t scratch_reg;
4099 int i;
4100
4101 if (rdev->family >= CHIP_R600)
4102 scratch_reg = R600_BIOS_0_SCRATCH;
4103 else
4104 scratch_reg = RADEON_BIOS_0_SCRATCH;
4105
4106 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4107 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
4108}
4109
4110void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
4111{
4112 uint32_t scratch_reg;
4113 int i;
4114
4115 if (rdev->family >= CHIP_R600)
4116 scratch_reg = R600_BIOS_0_SCRATCH;
4117 else
4118 scratch_reg = RADEON_BIOS_0_SCRATCH;
4119
4120 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4121 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
4122}
4123
4124void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
4125{
4126 struct drm_device *dev = encoder->dev;
4127 struct radeon_device *rdev = dev->dev_private;
4128 uint32_t bios_6_scratch;
4129
4130 if (rdev->family >= CHIP_R600)
4131 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4132 else
4133 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4134
4135 if (lock) {
4136 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
4137 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
4138 } else {
4139 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
4140 bios_6_scratch |= ATOM_S6_ACC_MODE;
4141 }
4142
4143 if (rdev->family >= CHIP_R600)
4144 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4145 else
4146 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4147}
4148
4149/* at some point we may want to break this out into individual functions */
4150void
4151radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
4152 struct drm_encoder *encoder,
4153 bool connected)
4154{
4155 struct drm_device *dev = connector->dev;
4156 struct radeon_device *rdev = dev->dev_private;
4157 struct radeon_connector *radeon_connector =
4158 to_radeon_connector(connector);
4159 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4160 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
4161
4162 if (rdev->family >= CHIP_R600) {
4163 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
4164 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4165 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4166 } else {
4167 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
4168 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4169 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4170 }
4171
4172 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
4173 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
4174 if (connected) {
4175 DRM_DEBUG_KMS("TV1 connected\n");
4176 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
4177 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
4178 } else {
4179 DRM_DEBUG_KMS("TV1 disconnected\n");
4180 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
4181 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
4182 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
4183 }
4184 }
4185 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
4186 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
4187 if (connected) {
4188 DRM_DEBUG_KMS("CV connected\n");
4189 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
4190 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
4191 } else {
4192 DRM_DEBUG_KMS("CV disconnected\n");
4193 bios_0_scratch &= ~ATOM_S0_CV_MASK;
4194 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
4195 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
4196 }
4197 }
4198 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
4199 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
4200 if (connected) {
4201 DRM_DEBUG_KMS("LCD1 connected\n");
4202 bios_0_scratch |= ATOM_S0_LCD1;
4203 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
4204 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
4205 } else {
4206 DRM_DEBUG_KMS("LCD1 disconnected\n");
4207 bios_0_scratch &= ~ATOM_S0_LCD1;
4208 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
4209 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
4210 }
4211 }
4212 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
4213 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
4214 if (connected) {
4215 DRM_DEBUG_KMS("CRT1 connected\n");
4216 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
4217 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
4218 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
4219 } else {
4220 DRM_DEBUG_KMS("CRT1 disconnected\n");
4221 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
4222 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
4223 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
4224 }
4225 }
4226 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
4227 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
4228 if (connected) {
4229 DRM_DEBUG_KMS("CRT2 connected\n");
4230 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
4231 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
4232 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
4233 } else {
4234 DRM_DEBUG_KMS("CRT2 disconnected\n");
4235 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
4236 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
4237 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
4238 }
4239 }
4240 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
4241 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
4242 if (connected) {
4243 DRM_DEBUG_KMS("DFP1 connected\n");
4244 bios_0_scratch |= ATOM_S0_DFP1;
4245 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
4246 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
4247 } else {
4248 DRM_DEBUG_KMS("DFP1 disconnected\n");
4249 bios_0_scratch &= ~ATOM_S0_DFP1;
4250 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
4251 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
4252 }
4253 }
4254 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
4255 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
4256 if (connected) {
4257 DRM_DEBUG_KMS("DFP2 connected\n");
4258 bios_0_scratch |= ATOM_S0_DFP2;
4259 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
4260 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
4261 } else {
4262 DRM_DEBUG_KMS("DFP2 disconnected\n");
4263 bios_0_scratch &= ~ATOM_S0_DFP2;
4264 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
4265 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
4266 }
4267 }
4268 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
4269 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
4270 if (connected) {
4271 DRM_DEBUG_KMS("DFP3 connected\n");
4272 bios_0_scratch |= ATOM_S0_DFP3;
4273 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
4274 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
4275 } else {
4276 DRM_DEBUG_KMS("DFP3 disconnected\n");
4277 bios_0_scratch &= ~ATOM_S0_DFP3;
4278 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
4279 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
4280 }
4281 }
4282 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
4283 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
4284 if (connected) {
4285 DRM_DEBUG_KMS("DFP4 connected\n");
4286 bios_0_scratch |= ATOM_S0_DFP4;
4287 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
4288 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
4289 } else {
4290 DRM_DEBUG_KMS("DFP4 disconnected\n");
4291 bios_0_scratch &= ~ATOM_S0_DFP4;
4292 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
4293 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
4294 }
4295 }
4296 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
4297 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
4298 if (connected) {
4299 DRM_DEBUG_KMS("DFP5 connected\n");
4300 bios_0_scratch |= ATOM_S0_DFP5;
4301 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
4302 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
4303 } else {
4304 DRM_DEBUG_KMS("DFP5 disconnected\n");
4305 bios_0_scratch &= ~ATOM_S0_DFP5;
4306 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
4307 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
4308 }
4309 }
4310 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4311 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4312 if (connected) {
4313 DRM_DEBUG_KMS("DFP6 connected\n");
4314 bios_0_scratch |= ATOM_S0_DFP6;
4315 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4316 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4317 } else {
4318 DRM_DEBUG_KMS("DFP6 disconnected\n");
4319 bios_0_scratch &= ~ATOM_S0_DFP6;
4320 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4321 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4322 }
4323 }
4324
4325 if (rdev->family >= CHIP_R600) {
4326 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4327 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4328 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4329 } else {
4330 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4331 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4332 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4333 }
4334}
4335
4336void
4337radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4338{
4339 struct drm_device *dev = encoder->dev;
4340 struct radeon_device *rdev = dev->dev_private;
4341 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4342 uint32_t bios_3_scratch;
4343
4344 if (ASIC_IS_DCE4(rdev))
4345 return;
4346
4347 if (rdev->family >= CHIP_R600)
4348 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4349 else
4350 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4351
4352 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4353 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4354 bios_3_scratch |= (crtc << 18);
4355 }
4356 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4357 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4358 bios_3_scratch |= (crtc << 24);
4359 }
4360 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4361 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4362 bios_3_scratch |= (crtc << 16);
4363 }
4364 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4365 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4366 bios_3_scratch |= (crtc << 20);
4367 }
4368 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4369 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4370 bios_3_scratch |= (crtc << 17);
4371 }
4372 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4373 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4374 bios_3_scratch |= (crtc << 19);
4375 }
4376 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4377 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4378 bios_3_scratch |= (crtc << 23);
4379 }
4380 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4381 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4382 bios_3_scratch |= (crtc << 25);
4383 }
4384
4385 if (rdev->family >= CHIP_R600)
4386 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4387 else
4388 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4389}
4390
4391void
4392radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4393{
4394 struct drm_device *dev = encoder->dev;
4395 struct radeon_device *rdev = dev->dev_private;
4396 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4397 uint32_t bios_2_scratch;
4398
4399 if (ASIC_IS_DCE4(rdev))
4400 return;
4401
4402 if (rdev->family >= CHIP_R600)
4403 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4404 else
4405 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4406
4407 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4408 if (on)
4409 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4410 else
4411 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4412 }
4413 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4414 if (on)
4415 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4416 else
4417 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4418 }
4419 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4420 if (on)
4421 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4422 else
4423 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4424 }
4425 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4426 if (on)
4427 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4428 else
4429 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4430 }
4431 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4432 if (on)
4433 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4434 else
4435 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4436 }
4437 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4438 if (on)
4439 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4440 else
4441 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4442 }
4443 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4444 if (on)
4445 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4446 else
4447 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4448 }
4449 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4450 if (on)
4451 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4452 else
4453 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4454 }
4455 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4456 if (on)
4457 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4458 else
4459 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4460 }
4461 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4462 if (on)
4463 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4464 else
4465 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4466 }
4467
4468 if (rdev->family >= CHIP_R600)
4469 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4470 else
4471 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4472}