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1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27#include <linux/pci.h>
28
29#include <drm/drm_device.h>
30#include <drm/drm_edid.h>
31#include <drm/radeon_drm.h>
32
33#include "radeon.h"
34
35#include "atom.h"
36#include "atom-bits.h"
37#include "radeon_asic.h"
38#include "radeon_atombios.h"
39#include "radeon_legacy_encoders.h"
40
41union atom_supported_devices {
42 struct _ATOM_SUPPORTED_DEVICES_INFO info;
43 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
44 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
45};
46
47static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
48 ATOM_GPIO_I2C_ASSIGMENT *gpio,
49 u8 index)
50{
51 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
52 if ((rdev->family == CHIP_R420) ||
53 (rdev->family == CHIP_R423) ||
54 (rdev->family == CHIP_RV410)) {
55 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
56 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
57 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
58 gpio->ucClkMaskShift = 0x19;
59 gpio->ucDataMaskShift = 0x18;
60 }
61 }
62
63 /* some evergreen boards have bad data for this entry */
64 if (ASIC_IS_DCE4(rdev)) {
65 if ((index == 7) &&
66 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
67 (gpio->sucI2cId.ucAccess == 0)) {
68 gpio->sucI2cId.ucAccess = 0x97;
69 gpio->ucDataMaskShift = 8;
70 gpio->ucDataEnShift = 8;
71 gpio->ucDataY_Shift = 8;
72 gpio->ucDataA_Shift = 8;
73 }
74 }
75
76 /* some DCE3 boards have bad data for this entry */
77 if (ASIC_IS_DCE3(rdev)) {
78 if ((index == 4) &&
79 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
80 (gpio->sucI2cId.ucAccess == 0x94))
81 gpio->sucI2cId.ucAccess = 0x14;
82 }
83}
84
85static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
86{
87 struct radeon_i2c_bus_rec i2c;
88
89 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
90
91 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
92 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
93 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
94 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
95 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
96 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
97 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
98 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
99 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
100 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
101 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
102 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
103 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
104 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
105 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
106 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
107
108 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
109 i2c.hw_capable = true;
110 else
111 i2c.hw_capable = false;
112
113 if (gpio->sucI2cId.ucAccess == 0xa0)
114 i2c.mm_i2c = true;
115 else
116 i2c.mm_i2c = false;
117
118 i2c.i2c_id = gpio->sucI2cId.ucAccess;
119
120 if (i2c.mask_clk_reg)
121 i2c.valid = true;
122 else
123 i2c.valid = false;
124
125 return i2c;
126}
127
128static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
129 uint8_t id)
130{
131 struct atom_context *ctx = rdev->mode_info.atom_context;
132 ATOM_GPIO_I2C_ASSIGMENT *gpio;
133 struct radeon_i2c_bus_rec i2c;
134 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
135 struct _ATOM_GPIO_I2C_INFO *i2c_info;
136 uint16_t data_offset, size;
137 int i, num_indices;
138
139 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
140 i2c.valid = false;
141
142 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
143 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
144
145 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
146 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
147
148 gpio = &i2c_info->asGPIO_Info[0];
149 for (i = 0; i < num_indices; i++) {
150
151 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
152
153 if (gpio->sucI2cId.ucAccess == id) {
154 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
155 break;
156 }
157 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
158 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
159 }
160 }
161
162 return i2c;
163}
164
165void radeon_atombios_i2c_init(struct radeon_device *rdev)
166{
167 struct atom_context *ctx = rdev->mode_info.atom_context;
168 ATOM_GPIO_I2C_ASSIGMENT *gpio;
169 struct radeon_i2c_bus_rec i2c;
170 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
171 struct _ATOM_GPIO_I2C_INFO *i2c_info;
172 uint16_t data_offset, size;
173 int i, num_indices;
174 char stmp[32];
175
176 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
177 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
178
179 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
180 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
181
182 gpio = &i2c_info->asGPIO_Info[0];
183 for (i = 0; i < num_indices; i++) {
184 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
185
186 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
187
188 if (i2c.valid) {
189 sprintf(stmp, "0x%x", i2c.i2c_id);
190 rdev->i2c_bus[i] = radeon_i2c_create(rdev_to_drm(rdev), &i2c, stmp);
191 }
192 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
193 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
194 }
195 }
196}
197
198struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
199 u8 id)
200{
201 struct atom_context *ctx = rdev->mode_info.atom_context;
202 struct radeon_gpio_rec gpio;
203 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
204 struct _ATOM_GPIO_PIN_LUT *gpio_info;
205 ATOM_GPIO_PIN_ASSIGNMENT *pin;
206 u16 data_offset, size;
207 int i, num_indices;
208
209 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
210 gpio.valid = false;
211
212 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
213 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
214
215 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
216 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
217
218 pin = gpio_info->asGPIO_Pin;
219 for (i = 0; i < num_indices; i++) {
220 if (id == pin->ucGPIO_ID) {
221 gpio.id = pin->ucGPIO_ID;
222 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
223 gpio.shift = pin->ucGpioPinBitShift;
224 gpio.mask = (1 << pin->ucGpioPinBitShift);
225 gpio.valid = true;
226 break;
227 }
228 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
229 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
230 }
231 }
232
233 return gpio;
234}
235
236static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
237 struct radeon_gpio_rec *gpio)
238{
239 struct radeon_hpd hpd;
240 u32 reg;
241
242 memset(&hpd, 0, sizeof(struct radeon_hpd));
243
244 if (ASIC_IS_DCE6(rdev))
245 reg = SI_DC_GPIO_HPD_A;
246 else if (ASIC_IS_DCE4(rdev))
247 reg = EVERGREEN_DC_GPIO_HPD_A;
248 else
249 reg = AVIVO_DC_GPIO_HPD_A;
250
251 hpd.gpio = *gpio;
252 if (gpio->reg == reg) {
253 switch(gpio->mask) {
254 case (1 << 0):
255 hpd.hpd = RADEON_HPD_1;
256 break;
257 case (1 << 8):
258 hpd.hpd = RADEON_HPD_2;
259 break;
260 case (1 << 16):
261 hpd.hpd = RADEON_HPD_3;
262 break;
263 case (1 << 24):
264 hpd.hpd = RADEON_HPD_4;
265 break;
266 case (1 << 26):
267 hpd.hpd = RADEON_HPD_5;
268 break;
269 case (1 << 28):
270 hpd.hpd = RADEON_HPD_6;
271 break;
272 default:
273 hpd.hpd = RADEON_HPD_NONE;
274 break;
275 }
276 } else
277 hpd.hpd = RADEON_HPD_NONE;
278 return hpd;
279}
280
281static bool radeon_atom_apply_quirks(struct drm_device *dev,
282 uint32_t supported_device,
283 int *connector_type,
284 struct radeon_i2c_bus_rec *i2c_bus,
285 uint16_t *line_mux,
286 struct radeon_hpd *hpd)
287{
288 struct pci_dev *pdev = to_pci_dev(dev->dev);
289
290 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
291 if ((pdev->device == 0x791e) &&
292 (pdev->subsystem_vendor == 0x1043) &&
293 (pdev->subsystem_device == 0x826d)) {
294 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
295 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
296 *connector_type = DRM_MODE_CONNECTOR_DVID;
297 }
298
299 /* Asrock RS600 board lists the DVI port as HDMI */
300 if ((pdev->device == 0x7941) &&
301 (pdev->subsystem_vendor == 0x1849) &&
302 (pdev->subsystem_device == 0x7941)) {
303 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
304 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
305 *connector_type = DRM_MODE_CONNECTOR_DVID;
306 }
307
308 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
309 if ((pdev->device == 0x796e) &&
310 (pdev->subsystem_vendor == 0x1462) &&
311 (pdev->subsystem_device == 0x7302)) {
312 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
313 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
314 return false;
315 }
316
317 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
318 if ((pdev->device == 0x7941) &&
319 (pdev->subsystem_vendor == 0x147b) &&
320 (pdev->subsystem_device == 0x2412)) {
321 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
322 return false;
323 }
324
325 /* Falcon NW laptop lists vga ddc line for LVDS */
326 if ((pdev->device == 0x5653) &&
327 (pdev->subsystem_vendor == 0x1462) &&
328 (pdev->subsystem_device == 0x0291)) {
329 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
330 i2c_bus->valid = false;
331 *line_mux = 53;
332 }
333 }
334
335 /* HIS X1300 is DVI+VGA, not DVI+DVI */
336 if ((pdev->device == 0x7146) &&
337 (pdev->subsystem_vendor == 0x17af) &&
338 (pdev->subsystem_device == 0x2058)) {
339 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
340 return false;
341 }
342
343 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
344 if ((pdev->device == 0x7142) &&
345 (pdev->subsystem_vendor == 0x1458) &&
346 (pdev->subsystem_device == 0x2134)) {
347 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
348 return false;
349 }
350
351
352 /* Funky macbooks */
353 if ((pdev->device == 0x71C5) &&
354 (pdev->subsystem_vendor == 0x106b) &&
355 (pdev->subsystem_device == 0x0080)) {
356 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
357 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
358 return false;
359 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
360 *line_mux = 0x90;
361 }
362
363 /* mac rv630, rv730, others */
364 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
365 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
366 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
367 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
368 }
369
370 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
371 if ((pdev->device == 0x9598) &&
372 (pdev->subsystem_vendor == 0x1043) &&
373 (pdev->subsystem_device == 0x01da)) {
374 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
375 *connector_type = DRM_MODE_CONNECTOR_DVII;
376 }
377 }
378
379 /* ASUS HD 3600 board lists the DVI port as HDMI */
380 if ((pdev->device == 0x9598) &&
381 (pdev->subsystem_vendor == 0x1043) &&
382 (pdev->subsystem_device == 0x01e4)) {
383 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
384 *connector_type = DRM_MODE_CONNECTOR_DVII;
385 }
386 }
387
388 /* ASUS HD 3450 board lists the DVI port as HDMI */
389 if ((pdev->device == 0x95C5) &&
390 (pdev->subsystem_vendor == 0x1043) &&
391 (pdev->subsystem_device == 0x01e2)) {
392 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
393 *connector_type = DRM_MODE_CONNECTOR_DVII;
394 }
395 }
396
397 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
398 * HDMI + VGA reporting as HDMI
399 */
400 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
401 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
402 *connector_type = DRM_MODE_CONNECTOR_VGA;
403 *line_mux = 0;
404 }
405 }
406
407 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
408 * on the laptop and a DVI port on the docking station and
409 * both share the same encoder, hpd pin, and ddc line.
410 * So while the bios table is technically correct,
411 * we drop the DVI port here since xrandr has no concept of
412 * encoders and will try and drive both connectors
413 * with different crtcs which isn't possible on the hardware
414 * side and leaves no crtcs for LVDS or VGA.
415 */
416 if (((pdev->device == 0x95c4) || (pdev->device == 0x9591)) &&
417 (pdev->subsystem_vendor == 0x1025) &&
418 (pdev->subsystem_device == 0x013c)) {
419 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
420 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
421 /* actually it's a DVI-D port not DVI-I */
422 *connector_type = DRM_MODE_CONNECTOR_DVID;
423 return false;
424 }
425 }
426
427 /* XFX Pine Group device rv730 reports no VGA DDC lines
428 * even though they are wired up to record 0x93
429 */
430 if ((pdev->device == 0x9498) &&
431 (pdev->subsystem_vendor == 0x1682) &&
432 (pdev->subsystem_device == 0x2452) &&
433 (i2c_bus->valid == false) &&
434 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
435 struct radeon_device *rdev = dev->dev_private;
436 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
437 }
438
439 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
440 if (((pdev->device == 0x9802) ||
441 (pdev->device == 0x9805) ||
442 (pdev->device == 0x9806)) &&
443 (pdev->subsystem_vendor == 0x1734) &&
444 (pdev->subsystem_device == 0x11bd)) {
445 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
446 *connector_type = DRM_MODE_CONNECTOR_DVII;
447 *line_mux = 0x3103;
448 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
449 *connector_type = DRM_MODE_CONNECTOR_DVII;
450 }
451 }
452
453 return true;
454}
455
456static const int supported_devices_connector_convert[] = {
457 DRM_MODE_CONNECTOR_Unknown,
458 DRM_MODE_CONNECTOR_VGA,
459 DRM_MODE_CONNECTOR_DVII,
460 DRM_MODE_CONNECTOR_DVID,
461 DRM_MODE_CONNECTOR_DVIA,
462 DRM_MODE_CONNECTOR_SVIDEO,
463 DRM_MODE_CONNECTOR_Composite,
464 DRM_MODE_CONNECTOR_LVDS,
465 DRM_MODE_CONNECTOR_Unknown,
466 DRM_MODE_CONNECTOR_Unknown,
467 DRM_MODE_CONNECTOR_HDMIA,
468 DRM_MODE_CONNECTOR_HDMIB,
469 DRM_MODE_CONNECTOR_Unknown,
470 DRM_MODE_CONNECTOR_Unknown,
471 DRM_MODE_CONNECTOR_9PinDIN,
472 DRM_MODE_CONNECTOR_DisplayPort
473};
474
475static const uint16_t supported_devices_connector_object_id_convert[] = {
476 CONNECTOR_OBJECT_ID_NONE,
477 CONNECTOR_OBJECT_ID_VGA,
478 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
479 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
480 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
481 CONNECTOR_OBJECT_ID_COMPOSITE,
482 CONNECTOR_OBJECT_ID_SVIDEO,
483 CONNECTOR_OBJECT_ID_LVDS,
484 CONNECTOR_OBJECT_ID_9PIN_DIN,
485 CONNECTOR_OBJECT_ID_9PIN_DIN,
486 CONNECTOR_OBJECT_ID_DISPLAYPORT,
487 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
488 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
489 CONNECTOR_OBJECT_ID_SVIDEO
490};
491
492static const int object_connector_convert[] = {
493 DRM_MODE_CONNECTOR_Unknown,
494 DRM_MODE_CONNECTOR_DVII,
495 DRM_MODE_CONNECTOR_DVII,
496 DRM_MODE_CONNECTOR_DVID,
497 DRM_MODE_CONNECTOR_DVID,
498 DRM_MODE_CONNECTOR_VGA,
499 DRM_MODE_CONNECTOR_Composite,
500 DRM_MODE_CONNECTOR_SVIDEO,
501 DRM_MODE_CONNECTOR_Unknown,
502 DRM_MODE_CONNECTOR_Unknown,
503 DRM_MODE_CONNECTOR_9PinDIN,
504 DRM_MODE_CONNECTOR_Unknown,
505 DRM_MODE_CONNECTOR_HDMIA,
506 DRM_MODE_CONNECTOR_HDMIB,
507 DRM_MODE_CONNECTOR_LVDS,
508 DRM_MODE_CONNECTOR_9PinDIN,
509 DRM_MODE_CONNECTOR_Unknown,
510 DRM_MODE_CONNECTOR_Unknown,
511 DRM_MODE_CONNECTOR_Unknown,
512 DRM_MODE_CONNECTOR_DisplayPort,
513 DRM_MODE_CONNECTOR_eDP,
514 DRM_MODE_CONNECTOR_Unknown
515};
516
517bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
518{
519 struct radeon_device *rdev = dev->dev_private;
520 struct radeon_mode_info *mode_info = &rdev->mode_info;
521 struct atom_context *ctx = mode_info->atom_context;
522 int index = GetIndexIntoMasterTable(DATA, Object_Header);
523 u16 size, data_offset;
524 u8 frev, crev;
525 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
526 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
527 ATOM_OBJECT_TABLE *router_obj;
528 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
529 ATOM_OBJECT_HEADER *obj_header;
530 int i, j, k, path_size, device_support;
531 int connector_type;
532 u16 igp_lane_info, conn_id, connector_object_id;
533 struct radeon_i2c_bus_rec ddc_bus;
534 struct radeon_router router;
535 struct radeon_gpio_rec gpio;
536 struct radeon_hpd hpd;
537
538 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
539 return false;
540
541 if (crev < 2)
542 return false;
543
544 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
545 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
546 (ctx->bios + data_offset +
547 le16_to_cpu(obj_header->usDisplayPathTableOffset));
548 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
549 (ctx->bios + data_offset +
550 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
551 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
552 (ctx->bios + data_offset +
553 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
554 router_obj = (ATOM_OBJECT_TABLE *)
555 (ctx->bios + data_offset +
556 le16_to_cpu(obj_header->usRouterObjectTableOffset));
557 device_support = le16_to_cpu(obj_header->usDeviceSupport);
558
559 path_size = 0;
560 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
561 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
562 ATOM_DISPLAY_OBJECT_PATH *path;
563 addr += path_size;
564 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
565 path_size += le16_to_cpu(path->usSize);
566
567 if (device_support & le16_to_cpu(path->usDeviceTag)) {
568 uint8_t con_obj_id, con_obj_num;
569
570 con_obj_id =
571 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
572 >> OBJECT_ID_SHIFT;
573 con_obj_num =
574 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
575 >> ENUM_ID_SHIFT;
576
577 /* TODO CV support */
578 if (le16_to_cpu(path->usDeviceTag) ==
579 ATOM_DEVICE_CV_SUPPORT)
580 continue;
581
582 /* IGP chips */
583 if ((rdev->flags & RADEON_IS_IGP) &&
584 (con_obj_id ==
585 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
586 uint16_t igp_offset = 0;
587 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
588
589 index =
590 GetIndexIntoMasterTable(DATA,
591 IntegratedSystemInfo);
592
593 if (atom_parse_data_header(ctx, index, &size, &frev,
594 &crev, &igp_offset)) {
595
596 if (crev >= 2) {
597 igp_obj =
598 (ATOM_INTEGRATED_SYSTEM_INFO_V2
599 *) (ctx->bios + igp_offset);
600
601 if (igp_obj) {
602 uint32_t slot_config, ct;
603
604 if (con_obj_num == 1)
605 slot_config =
606 igp_obj->
607 ulDDISlot1Config;
608 else
609 slot_config =
610 igp_obj->
611 ulDDISlot2Config;
612
613 ct = (slot_config >> 16) & 0xff;
614 connector_type =
615 object_connector_convert
616 [ct];
617 connector_object_id = ct;
618 igp_lane_info =
619 slot_config & 0xffff;
620 } else
621 continue;
622 } else
623 continue;
624 } else {
625 igp_lane_info = 0;
626 connector_type =
627 object_connector_convert[con_obj_id];
628 connector_object_id = con_obj_id;
629 }
630 } else {
631 igp_lane_info = 0;
632 connector_type =
633 object_connector_convert[con_obj_id];
634 connector_object_id = con_obj_id;
635 }
636
637 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
638 continue;
639
640 router.ddc_valid = false;
641 router.cd_valid = false;
642 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
643 uint8_t grph_obj_type =
644 (le16_to_cpu(path->usGraphicObjIds[j]) &
645 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
646
647 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
648 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
649 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
650 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
651 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
652 (ctx->bios + data_offset +
653 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
654 ATOM_ENCODER_CAP_RECORD *cap_record;
655 u16 caps = 0;
656
657 while (record->ucRecordSize > 0 &&
658 record->ucRecordType > 0 &&
659 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
660 switch (record->ucRecordType) {
661 case ATOM_ENCODER_CAP_RECORD_TYPE:
662 cap_record =(ATOM_ENCODER_CAP_RECORD *)
663 record;
664 caps = le16_to_cpu(cap_record->usEncoderCap);
665 break;
666 }
667 record = (ATOM_COMMON_RECORD_HEADER *)
668 ((char *)record + record->ucRecordSize);
669 }
670 radeon_add_atom_encoder(dev,
671 encoder_obj,
672 le16_to_cpu
673 (path->
674 usDeviceTag),
675 caps);
676 }
677 }
678 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
679 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
680 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
681 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
682 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
683 (ctx->bios + data_offset +
684 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
685 ATOM_I2C_RECORD *i2c_record;
686 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
687 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
688 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
689 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
690 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
691 (ctx->bios + data_offset +
692 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
693 u8 *num_dst_objs = (u8 *)
694 ((u8 *)router_src_dst_table + 1 +
695 (router_src_dst_table->ucNumberOfSrc * 2));
696 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
697 int enum_id;
698
699 router.router_id = router_obj_id;
700 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
701 if (le16_to_cpu(path->usConnObjectId) ==
702 le16_to_cpu(dst_objs[enum_id]))
703 break;
704 }
705
706 while (record->ucRecordSize > 0 &&
707 record->ucRecordType > 0 &&
708 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
709 switch (record->ucRecordType) {
710 case ATOM_I2C_RECORD_TYPE:
711 i2c_record =
712 (ATOM_I2C_RECORD *)
713 record;
714 i2c_config =
715 (ATOM_I2C_ID_CONFIG_ACCESS *)
716 &i2c_record->sucI2cId;
717 router.i2c_info =
718 radeon_lookup_i2c_gpio(rdev,
719 i2c_config->
720 ucAccess);
721 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
722 break;
723 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
724 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
725 record;
726 router.ddc_valid = true;
727 router.ddc_mux_type = ddc_path->ucMuxType;
728 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
729 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
730 break;
731 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
732 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
733 record;
734 router.cd_valid = true;
735 router.cd_mux_type = cd_path->ucMuxType;
736 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
737 router.cd_mux_state = cd_path->ucMuxState[enum_id];
738 break;
739 }
740 record = (ATOM_COMMON_RECORD_HEADER *)
741 ((char *)record + record->ucRecordSize);
742 }
743 }
744 }
745 }
746 }
747
748 /* look up gpio for ddc, hpd */
749 ddc_bus.valid = false;
750 hpd.hpd = RADEON_HPD_NONE;
751 if ((le16_to_cpu(path->usDeviceTag) &
752 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
753 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
754 if (le16_to_cpu(path->usConnObjectId) ==
755 le16_to_cpu(con_obj->asObjects[j].
756 usObjectID)) {
757 ATOM_COMMON_RECORD_HEADER
758 *record =
759 (ATOM_COMMON_RECORD_HEADER
760 *)
761 (ctx->bios + data_offset +
762 le16_to_cpu(con_obj->
763 asObjects[j].
764 usRecordOffset));
765 ATOM_I2C_RECORD *i2c_record;
766 ATOM_HPD_INT_RECORD *hpd_record;
767 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
768
769 while (record->ucRecordSize > 0 &&
770 record->ucRecordType > 0 &&
771 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
772 switch (record->ucRecordType) {
773 case ATOM_I2C_RECORD_TYPE:
774 i2c_record =
775 (ATOM_I2C_RECORD *)
776 record;
777 i2c_config =
778 (ATOM_I2C_ID_CONFIG_ACCESS *)
779 &i2c_record->sucI2cId;
780 ddc_bus = radeon_lookup_i2c_gpio(rdev,
781 i2c_config->
782 ucAccess);
783 break;
784 case ATOM_HPD_INT_RECORD_TYPE:
785 hpd_record =
786 (ATOM_HPD_INT_RECORD *)
787 record;
788 gpio = radeon_atombios_lookup_gpio(rdev,
789 hpd_record->ucHPDIntGPIOID);
790 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
791 hpd.plugged_state = hpd_record->ucPlugged_PinState;
792 break;
793 }
794 record =
795 (ATOM_COMMON_RECORD_HEADER
796 *) ((char *)record
797 +
798 record->
799 ucRecordSize);
800 }
801 break;
802 }
803 }
804 }
805
806 /* needed for aux chan transactions */
807 ddc_bus.hpd = hpd.hpd;
808
809 conn_id = le16_to_cpu(path->usConnObjectId);
810
811 if (!radeon_atom_apply_quirks
812 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
813 &ddc_bus, &conn_id, &hpd))
814 continue;
815
816 radeon_add_atom_connector(dev,
817 conn_id,
818 le16_to_cpu(path->
819 usDeviceTag),
820 connector_type, &ddc_bus,
821 igp_lane_info,
822 connector_object_id,
823 &hpd,
824 &router);
825
826 }
827 }
828
829 radeon_link_encoder_connector(dev);
830 return true;
831}
832
833static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
834 int connector_type,
835 uint16_t devices)
836{
837 struct radeon_device *rdev = dev->dev_private;
838
839 if (rdev->flags & RADEON_IS_IGP) {
840 return supported_devices_connector_object_id_convert
841 [connector_type];
842 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
843 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
844 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
845 struct radeon_mode_info *mode_info = &rdev->mode_info;
846 struct atom_context *ctx = mode_info->atom_context;
847 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
848 uint16_t size, data_offset;
849 uint8_t frev, crev;
850 ATOM_XTMDS_INFO *xtmds;
851
852 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
853 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
854
855 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
856 if (connector_type == DRM_MODE_CONNECTOR_DVII)
857 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
858 else
859 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
860 } else {
861 if (connector_type == DRM_MODE_CONNECTOR_DVII)
862 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
863 else
864 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
865 }
866 } else
867 return supported_devices_connector_object_id_convert
868 [connector_type];
869 } else {
870 return supported_devices_connector_object_id_convert
871 [connector_type];
872 }
873}
874
875struct bios_connector {
876 bool valid;
877 uint16_t line_mux;
878 uint16_t devices;
879 int connector_type;
880 struct radeon_i2c_bus_rec ddc_bus;
881 struct radeon_hpd hpd;
882};
883
884bool radeon_get_atom_connector_info_from_supported_devices_table(struct
885 drm_device
886 *dev)
887{
888 struct radeon_device *rdev = dev->dev_private;
889 struct radeon_mode_info *mode_info = &rdev->mode_info;
890 struct atom_context *ctx = mode_info->atom_context;
891 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
892 uint16_t size, data_offset;
893 uint8_t frev, crev;
894 uint16_t device_support;
895 uint8_t dac;
896 union atom_supported_devices *supported_devices;
897 int i, j, max_device;
898 struct bios_connector *bios_connectors;
899 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
900 struct radeon_router router;
901
902 router.ddc_valid = false;
903 router.cd_valid = false;
904
905 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
906 if (!bios_connectors)
907 return false;
908
909 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
910 &data_offset)) {
911 kfree(bios_connectors);
912 return false;
913 }
914
915 supported_devices =
916 (union atom_supported_devices *)(ctx->bios + data_offset);
917
918 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
919
920 if (frev > 1)
921 max_device = ATOM_MAX_SUPPORTED_DEVICE;
922 else
923 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
924
925 for (i = 0; i < max_device; i++) {
926 ATOM_CONNECTOR_INFO_I2C ci;
927
928 if (frev > 1)
929 ci = supported_devices->info_2d1.asConnInfo[i];
930 else
931 ci = supported_devices->info.asConnInfo[i];
932
933 bios_connectors[i].valid = false;
934
935 if (!(device_support & (1 << i))) {
936 continue;
937 }
938
939 if (i == ATOM_DEVICE_CV_INDEX) {
940 DRM_DEBUG_KMS("Skipping Component Video\n");
941 continue;
942 }
943
944 bios_connectors[i].connector_type =
945 supported_devices_connector_convert[ci.sucConnectorInfo.
946 sbfAccess.
947 bfConnectorType];
948
949 if (bios_connectors[i].connector_type ==
950 DRM_MODE_CONNECTOR_Unknown)
951 continue;
952
953 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
954
955 bios_connectors[i].line_mux =
956 ci.sucI2cId.ucAccess;
957
958 /* give tv unique connector ids */
959 if (i == ATOM_DEVICE_TV1_INDEX) {
960 bios_connectors[i].ddc_bus.valid = false;
961 bios_connectors[i].line_mux = 50;
962 } else if (i == ATOM_DEVICE_TV2_INDEX) {
963 bios_connectors[i].ddc_bus.valid = false;
964 bios_connectors[i].line_mux = 51;
965 } else if (i == ATOM_DEVICE_CV_INDEX) {
966 bios_connectors[i].ddc_bus.valid = false;
967 bios_connectors[i].line_mux = 52;
968 } else
969 bios_connectors[i].ddc_bus =
970 radeon_lookup_i2c_gpio(rdev,
971 bios_connectors[i].line_mux);
972
973 if ((crev > 1) && (frev > 1)) {
974 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
975 switch (isb) {
976 case 0x4:
977 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
978 break;
979 case 0xa:
980 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
981 break;
982 default:
983 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
984 break;
985 }
986 } else {
987 if (i == ATOM_DEVICE_DFP1_INDEX)
988 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
989 else if (i == ATOM_DEVICE_DFP2_INDEX)
990 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
991 else
992 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
993 }
994
995 /* Always set the connector type to VGA for CRT1/CRT2. if they are
996 * shared with a DVI port, we'll pick up the DVI connector when we
997 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
998 */
999 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1000 bios_connectors[i].connector_type =
1001 DRM_MODE_CONNECTOR_VGA;
1002
1003 if (!radeon_atom_apply_quirks
1004 (dev, (1 << i), &bios_connectors[i].connector_type,
1005 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1006 &bios_connectors[i].hpd))
1007 continue;
1008
1009 bios_connectors[i].valid = true;
1010 bios_connectors[i].devices = (1 << i);
1011
1012 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1013 radeon_add_atom_encoder(dev,
1014 radeon_get_encoder_enum(dev,
1015 (1 << i),
1016 dac),
1017 (1 << i),
1018 0);
1019 else
1020 radeon_add_legacy_encoder(dev,
1021 radeon_get_encoder_enum(dev,
1022 (1 << i),
1023 dac),
1024 (1 << i));
1025 }
1026
1027 /* combine shared connectors */
1028 for (i = 0; i < max_device; i++) {
1029 if (bios_connectors[i].valid) {
1030 for (j = 0; j < max_device; j++) {
1031 if (bios_connectors[j].valid && (i != j)) {
1032 if (bios_connectors[i].line_mux ==
1033 bios_connectors[j].line_mux) {
1034 /* make sure not to combine LVDS */
1035 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1036 bios_connectors[i].line_mux = 53;
1037 bios_connectors[i].ddc_bus.valid = false;
1038 continue;
1039 }
1040 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1041 bios_connectors[j].line_mux = 53;
1042 bios_connectors[j].ddc_bus.valid = false;
1043 continue;
1044 }
1045 /* combine analog and digital for DVI-I */
1046 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1047 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1048 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1049 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1050 bios_connectors[i].devices |=
1051 bios_connectors[j].devices;
1052 bios_connectors[i].connector_type =
1053 DRM_MODE_CONNECTOR_DVII;
1054 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1055 bios_connectors[i].hpd =
1056 bios_connectors[j].hpd;
1057 bios_connectors[j].valid = false;
1058 }
1059 }
1060 }
1061 }
1062 }
1063 }
1064
1065 /* add the connectors */
1066 for (i = 0; i < max_device; i++) {
1067 if (bios_connectors[i].valid) {
1068 uint16_t connector_object_id =
1069 atombios_get_connector_object_id(dev,
1070 bios_connectors[i].connector_type,
1071 bios_connectors[i].devices);
1072 radeon_add_atom_connector(dev,
1073 bios_connectors[i].line_mux,
1074 bios_connectors[i].devices,
1075 bios_connectors[i].
1076 connector_type,
1077 &bios_connectors[i].ddc_bus,
1078 0,
1079 connector_object_id,
1080 &bios_connectors[i].hpd,
1081 &router);
1082 }
1083 }
1084
1085 radeon_link_encoder_connector(dev);
1086
1087 kfree(bios_connectors);
1088 return true;
1089}
1090
1091union firmware_info {
1092 ATOM_FIRMWARE_INFO info;
1093 ATOM_FIRMWARE_INFO_V1_2 info_12;
1094 ATOM_FIRMWARE_INFO_V1_3 info_13;
1095 ATOM_FIRMWARE_INFO_V1_4 info_14;
1096 ATOM_FIRMWARE_INFO_V2_1 info_21;
1097 ATOM_FIRMWARE_INFO_V2_2 info_22;
1098};
1099
1100union igp_info {
1101 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1102 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1103 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1104 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1105 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1106};
1107
1108static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev)
1109{
1110 struct radeon_mode_info *mode_info = &rdev->mode_info;
1111 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1112 union igp_info *igp_info;
1113 u8 frev, crev;
1114 u16 data_offset;
1115
1116 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1117 &frev, &crev, &data_offset)) {
1118 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1119 data_offset);
1120 rdev->clock.vco_freq =
1121 le32_to_cpu(igp_info->info_6.ulDentistVCOFreq);
1122 }
1123}
1124
1125bool radeon_atom_get_clock_info(struct drm_device *dev)
1126{
1127 struct radeon_device *rdev = dev->dev_private;
1128 struct radeon_mode_info *mode_info = &rdev->mode_info;
1129 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1130 union firmware_info *firmware_info;
1131 uint8_t frev, crev;
1132 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1133 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1134 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1135 struct radeon_pll *spll = &rdev->clock.spll;
1136 struct radeon_pll *mpll = &rdev->clock.mpll;
1137 uint16_t data_offset;
1138
1139 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1140 &frev, &crev, &data_offset)) {
1141 firmware_info =
1142 (union firmware_info *)(mode_info->atom_context->bios +
1143 data_offset);
1144 /* pixel clocks */
1145 p1pll->reference_freq =
1146 le16_to_cpu(firmware_info->info.usReferenceClock);
1147 p1pll->reference_div = 0;
1148
1149 if ((frev < 2) && (crev < 2))
1150 p1pll->pll_out_min =
1151 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1152 else
1153 p1pll->pll_out_min =
1154 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1155 p1pll->pll_out_max =
1156 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1157
1158 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) {
1159 p1pll->lcd_pll_out_min =
1160 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1161 if (p1pll->lcd_pll_out_min == 0)
1162 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1163 p1pll->lcd_pll_out_max =
1164 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1165 if (p1pll->lcd_pll_out_max == 0)
1166 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1167 } else {
1168 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1169 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1170 }
1171
1172 if (p1pll->pll_out_min == 0) {
1173 if (ASIC_IS_AVIVO(rdev))
1174 p1pll->pll_out_min = 64800;
1175 else
1176 p1pll->pll_out_min = 20000;
1177 }
1178
1179 p1pll->pll_in_min =
1180 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1181 p1pll->pll_in_max =
1182 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1183
1184 *p2pll = *p1pll;
1185
1186 /* system clock */
1187 if (ASIC_IS_DCE4(rdev))
1188 spll->reference_freq =
1189 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1190 else
1191 spll->reference_freq =
1192 le16_to_cpu(firmware_info->info.usReferenceClock);
1193 spll->reference_div = 0;
1194
1195 spll->pll_out_min =
1196 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1197 spll->pll_out_max =
1198 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1199
1200 /* ??? */
1201 if (spll->pll_out_min == 0) {
1202 if (ASIC_IS_AVIVO(rdev))
1203 spll->pll_out_min = 64800;
1204 else
1205 spll->pll_out_min = 20000;
1206 }
1207
1208 spll->pll_in_min =
1209 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1210 spll->pll_in_max =
1211 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1212
1213 /* memory clock */
1214 if (ASIC_IS_DCE4(rdev))
1215 mpll->reference_freq =
1216 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1217 else
1218 mpll->reference_freq =
1219 le16_to_cpu(firmware_info->info.usReferenceClock);
1220 mpll->reference_div = 0;
1221
1222 mpll->pll_out_min =
1223 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1224 mpll->pll_out_max =
1225 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1226
1227 /* ??? */
1228 if (mpll->pll_out_min == 0) {
1229 if (ASIC_IS_AVIVO(rdev))
1230 mpll->pll_out_min = 64800;
1231 else
1232 mpll->pll_out_min = 20000;
1233 }
1234
1235 mpll->pll_in_min =
1236 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1237 mpll->pll_in_max =
1238 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1239
1240 rdev->clock.default_sclk =
1241 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1242 rdev->clock.default_mclk =
1243 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1244
1245 if (ASIC_IS_DCE4(rdev)) {
1246 rdev->clock.default_dispclk =
1247 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1248 if (rdev->clock.default_dispclk == 0) {
1249 if (ASIC_IS_DCE6(rdev))
1250 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1251 else if (ASIC_IS_DCE5(rdev))
1252 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1253 else
1254 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1255 }
1256 /* set a reasonable default for DP */
1257 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1258 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1259 rdev->clock.default_dispclk / 100);
1260 rdev->clock.default_dispclk = 60000;
1261 }
1262 rdev->clock.dp_extclk =
1263 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1264 rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1265 }
1266 *dcpll = *p1pll;
1267
1268 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1269 if (rdev->clock.max_pixel_clock == 0)
1270 rdev->clock.max_pixel_clock = 40000;
1271
1272 /* not technically a clock, but... */
1273 rdev->mode_info.firmware_flags =
1274 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1275
1276 if (ASIC_IS_DCE8(rdev))
1277 rdev->clock.vco_freq =
1278 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq);
1279 else if (ASIC_IS_DCE5(rdev))
1280 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1281 else if (ASIC_IS_DCE41(rdev))
1282 radeon_atombios_get_dentist_vco_freq(rdev);
1283 else
1284 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1285
1286 if (rdev->clock.vco_freq == 0)
1287 rdev->clock.vco_freq = 360000; /* 3.6 GHz */
1288
1289 return true;
1290 }
1291
1292 return false;
1293}
1294
1295bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1296{
1297 struct radeon_mode_info *mode_info = &rdev->mode_info;
1298 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1299 union igp_info *igp_info;
1300 u8 frev, crev;
1301 u16 data_offset;
1302
1303 /* sideport is AMD only */
1304 if (rdev->family == CHIP_RS600)
1305 return false;
1306
1307 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1308 &frev, &crev, &data_offset)) {
1309 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1310 data_offset);
1311 switch (crev) {
1312 case 1:
1313 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1314 return true;
1315 break;
1316 case 2:
1317 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1318 return true;
1319 break;
1320 default:
1321 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1322 break;
1323 }
1324 }
1325 return false;
1326}
1327
1328bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1329 struct radeon_encoder_int_tmds *tmds)
1330{
1331 struct drm_device *dev = encoder->base.dev;
1332 struct radeon_device *rdev = dev->dev_private;
1333 struct radeon_mode_info *mode_info = &rdev->mode_info;
1334 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1335 uint16_t data_offset;
1336 struct _ATOM_TMDS_INFO *tmds_info;
1337 uint8_t frev, crev;
1338 uint16_t maxfreq;
1339 int i;
1340
1341 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1342 &frev, &crev, &data_offset)) {
1343 tmds_info =
1344 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1345 data_offset);
1346
1347 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1348 for (i = 0; i < 4; i++) {
1349 tmds->tmds_pll[i].freq =
1350 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1351 tmds->tmds_pll[i].value =
1352 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1353 tmds->tmds_pll[i].value |=
1354 (tmds_info->asMiscInfo[i].
1355 ucPLL_VCO_Gain & 0x3f) << 6;
1356 tmds->tmds_pll[i].value |=
1357 (tmds_info->asMiscInfo[i].
1358 ucPLL_DutyCycle & 0xf) << 12;
1359 tmds->tmds_pll[i].value |=
1360 (tmds_info->asMiscInfo[i].
1361 ucPLL_VoltageSwing & 0xf) << 16;
1362
1363 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1364 tmds->tmds_pll[i].freq,
1365 tmds->tmds_pll[i].value);
1366
1367 if (maxfreq == tmds->tmds_pll[i].freq) {
1368 tmds->tmds_pll[i].freq = 0xffffffff;
1369 break;
1370 }
1371 }
1372 return true;
1373 }
1374 return false;
1375}
1376
1377bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1378 struct radeon_atom_ss *ss,
1379 int id)
1380{
1381 struct radeon_mode_info *mode_info = &rdev->mode_info;
1382 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1383 uint16_t data_offset, size;
1384 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1385 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1386 uint8_t frev, crev;
1387 int i, num_indices;
1388
1389 memset(ss, 0, sizeof(struct radeon_atom_ss));
1390 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1391 &frev, &crev, &data_offset)) {
1392 ss_info =
1393 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1394
1395 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1396 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1397 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *)
1398 ((u8 *)&ss_info->asSS_Info[0]);
1399 for (i = 0; i < num_indices; i++) {
1400 if (ss_assign->ucSS_Id == id) {
1401 ss->percentage =
1402 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
1403 ss->type = ss_assign->ucSpreadSpectrumType;
1404 ss->step = ss_assign->ucSS_Step;
1405 ss->delay = ss_assign->ucSS_Delay;
1406 ss->range = ss_assign->ucSS_Range;
1407 ss->refdiv = ss_assign->ucRecommendedRef_Div;
1408 return true;
1409 }
1410 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *)
1411 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1412 }
1413 }
1414 return false;
1415}
1416
1417static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1418 struct radeon_atom_ss *ss,
1419 int id)
1420{
1421 struct radeon_mode_info *mode_info = &rdev->mode_info;
1422 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1423 u16 data_offset, size;
1424 union igp_info *igp_info;
1425 u8 frev, crev;
1426 u16 percentage = 0, rate = 0;
1427
1428 /* get any igp specific overrides */
1429 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1430 &frev, &crev, &data_offset)) {
1431 igp_info = (union igp_info *)
1432 (mode_info->atom_context->bios + data_offset);
1433 switch (crev) {
1434 case 6:
1435 switch (id) {
1436 case ASIC_INTERNAL_SS_ON_TMDS:
1437 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1438 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1439 break;
1440 case ASIC_INTERNAL_SS_ON_HDMI:
1441 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1442 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1443 break;
1444 case ASIC_INTERNAL_SS_ON_LVDS:
1445 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1446 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1447 break;
1448 }
1449 break;
1450 case 7:
1451 switch (id) {
1452 case ASIC_INTERNAL_SS_ON_TMDS:
1453 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1454 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1455 break;
1456 case ASIC_INTERNAL_SS_ON_HDMI:
1457 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1458 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1459 break;
1460 case ASIC_INTERNAL_SS_ON_LVDS:
1461 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1462 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1463 break;
1464 }
1465 break;
1466 case 8:
1467 switch (id) {
1468 case ASIC_INTERNAL_SS_ON_TMDS:
1469 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1470 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1471 break;
1472 case ASIC_INTERNAL_SS_ON_HDMI:
1473 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1474 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1475 break;
1476 case ASIC_INTERNAL_SS_ON_LVDS:
1477 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1478 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1479 break;
1480 }
1481 break;
1482 default:
1483 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1484 break;
1485 }
1486 if (percentage)
1487 ss->percentage = percentage;
1488 if (rate)
1489 ss->rate = rate;
1490 }
1491}
1492
1493union asic_ss_info {
1494 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1495 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1496 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1497};
1498
1499union asic_ss_assignment {
1500 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
1501 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
1502 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
1503};
1504
1505bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1506 struct radeon_atom_ss *ss,
1507 int id, u32 clock)
1508{
1509 struct radeon_mode_info *mode_info = &rdev->mode_info;
1510 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1511 uint16_t data_offset, size;
1512 union asic_ss_info *ss_info;
1513 union asic_ss_assignment *ss_assign;
1514 uint8_t frev, crev;
1515 int i, num_indices;
1516
1517 if (id == ASIC_INTERNAL_MEMORY_SS) {
1518 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1519 return false;
1520 }
1521 if (id == ASIC_INTERNAL_ENGINE_SS) {
1522 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1523 return false;
1524 }
1525
1526 memset(ss, 0, sizeof(struct radeon_atom_ss));
1527 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1528 &frev, &crev, &data_offset)) {
1529
1530 ss_info =
1531 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1532
1533 switch (frev) {
1534 case 1:
1535 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1536 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1537
1538 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
1539 for (i = 0; i < num_indices; i++) {
1540 if ((ss_assign->v1.ucClockIndication == id) &&
1541 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1542 ss->percentage =
1543 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1544 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1545 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1546 ss->percentage_divider = 100;
1547 return true;
1548 }
1549 ss_assign = (union asic_ss_assignment *)
1550 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1551 }
1552 break;
1553 case 2:
1554 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1555 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1556 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
1557 for (i = 0; i < num_indices; i++) {
1558 if ((ss_assign->v2.ucClockIndication == id) &&
1559 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1560 ss->percentage =
1561 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1562 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1563 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1564 ss->percentage_divider = 100;
1565 if ((crev == 2) &&
1566 ((id == ASIC_INTERNAL_ENGINE_SS) ||
1567 (id == ASIC_INTERNAL_MEMORY_SS)))
1568 ss->rate /= 100;
1569 return true;
1570 }
1571 ss_assign = (union asic_ss_assignment *)
1572 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1573 }
1574 break;
1575 case 3:
1576 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1577 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1578 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
1579 for (i = 0; i < num_indices; i++) {
1580 if ((ss_assign->v3.ucClockIndication == id) &&
1581 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1582 ss->percentage =
1583 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1584 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1585 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1586 if (ss_assign->v3.ucSpreadSpectrumMode &
1587 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
1588 ss->percentage_divider = 1000;
1589 else
1590 ss->percentage_divider = 100;
1591 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1592 (id == ASIC_INTERNAL_MEMORY_SS))
1593 ss->rate /= 100;
1594 if (rdev->flags & RADEON_IS_IGP)
1595 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1596 return true;
1597 }
1598 ss_assign = (union asic_ss_assignment *)
1599 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1600 }
1601 break;
1602 default:
1603 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1604 break;
1605 }
1606
1607 }
1608 return false;
1609}
1610
1611union lvds_info {
1612 struct _ATOM_LVDS_INFO info;
1613 struct _ATOM_LVDS_INFO_V12 info_12;
1614};
1615
1616struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1617 radeon_encoder
1618 *encoder)
1619{
1620 struct drm_device *dev = encoder->base.dev;
1621 struct radeon_device *rdev = dev->dev_private;
1622 struct radeon_mode_info *mode_info = &rdev->mode_info;
1623 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1624 uint16_t data_offset, misc;
1625 union lvds_info *lvds_info;
1626 uint8_t frev, crev;
1627 struct radeon_encoder_atom_dig *lvds = NULL;
1628 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1629
1630 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1631 &frev, &crev, &data_offset)) {
1632 lvds_info =
1633 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1634 lvds =
1635 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1636
1637 if (!lvds)
1638 return NULL;
1639
1640 lvds->native_mode.clock =
1641 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1642 lvds->native_mode.hdisplay =
1643 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1644 lvds->native_mode.vdisplay =
1645 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1646 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1647 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1648 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1649 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1650 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1651 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1652 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1653 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1654 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1655 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1656 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1657 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1658 lvds->panel_pwr_delay =
1659 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1660 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1661
1662 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1663 if (misc & ATOM_VSYNC_POLARITY)
1664 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1665 if (misc & ATOM_HSYNC_POLARITY)
1666 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1667 if (misc & ATOM_COMPOSITESYNC)
1668 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1669 if (misc & ATOM_INTERLACE)
1670 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1671 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1672 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1673
1674 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1675 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1676
1677 /* set crtc values */
1678 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1679
1680 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1681
1682 encoder->native_mode = lvds->native_mode;
1683
1684 if (encoder_enum == 2)
1685 lvds->linkb = true;
1686 else
1687 lvds->linkb = false;
1688
1689 /* parse the lcd record table */
1690 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1691 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1692 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1693 bool bad_record = false;
1694 u8 *record;
1695
1696 if ((frev == 1) && (crev < 2))
1697 /* absolute */
1698 record = (u8 *)(mode_info->atom_context->bios +
1699 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1700 else
1701 /* relative */
1702 record = (u8 *)(mode_info->atom_context->bios +
1703 data_offset +
1704 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1705 while (*record != ATOM_RECORD_END_TYPE) {
1706 switch (*record) {
1707 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1708 record += sizeof(ATOM_PATCH_RECORD_MODE);
1709 break;
1710 case LCD_RTS_RECORD_TYPE:
1711 record += sizeof(ATOM_LCD_RTS_RECORD);
1712 break;
1713 case LCD_CAP_RECORD_TYPE:
1714 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1715 break;
1716 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1717 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1718 if (fake_edid_record->ucFakeEDIDLength) {
1719 const struct drm_edid *edid;
1720 int edid_size;
1721
1722 if (fake_edid_record->ucFakeEDIDLength == 128)
1723 edid_size = fake_edid_record->ucFakeEDIDLength;
1724 else
1725 edid_size = fake_edid_record->ucFakeEDIDLength * 128;
1726 edid = drm_edid_alloc(fake_edid_record->ucFakeEDIDString, edid_size);
1727 if (drm_edid_valid(edid))
1728 rdev->mode_info.bios_hardcoded_edid = edid;
1729 else
1730 drm_edid_free(edid);
1731 record += struct_size(fake_edid_record,
1732 ucFakeEDIDString,
1733 edid_size);
1734 } else {
1735 /* empty fake edid record must be 3 bytes long */
1736 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1;
1737 }
1738 break;
1739 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1740 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1741 lvds->native_mode.width_mm = panel_res_record->usHSize;
1742 lvds->native_mode.height_mm = panel_res_record->usVSize;
1743 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1744 break;
1745 default:
1746 DRM_ERROR("Bad LCD record %d\n", *record);
1747 bad_record = true;
1748 break;
1749 }
1750 if (bad_record)
1751 break;
1752 }
1753 }
1754 }
1755 return lvds;
1756}
1757
1758struct radeon_encoder_primary_dac *
1759radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1760{
1761 struct drm_device *dev = encoder->base.dev;
1762 struct radeon_device *rdev = dev->dev_private;
1763 struct radeon_mode_info *mode_info = &rdev->mode_info;
1764 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1765 uint16_t data_offset;
1766 struct _COMPASSIONATE_DATA *dac_info;
1767 uint8_t frev, crev;
1768 uint8_t bg, dac;
1769 struct radeon_encoder_primary_dac *p_dac = NULL;
1770
1771 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1772 &frev, &crev, &data_offset)) {
1773 dac_info = (struct _COMPASSIONATE_DATA *)
1774 (mode_info->atom_context->bios + data_offset);
1775
1776 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1777
1778 if (!p_dac)
1779 return NULL;
1780
1781 bg = dac_info->ucDAC1_BG_Adjustment;
1782 dac = dac_info->ucDAC1_DAC_Adjustment;
1783 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1784
1785 }
1786 return p_dac;
1787}
1788
1789bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1790 struct drm_display_mode *mode)
1791{
1792 struct radeon_mode_info *mode_info = &rdev->mode_info;
1793 ATOM_ANALOG_TV_INFO *tv_info;
1794 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1795 ATOM_DTD_FORMAT *dtd_timings;
1796 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1797 u8 frev, crev;
1798 u16 data_offset, misc;
1799
1800 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1801 &frev, &crev, &data_offset))
1802 return false;
1803
1804 switch (crev) {
1805 case 1:
1806 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1807 if (index >= MAX_SUPPORTED_TV_TIMING)
1808 return false;
1809
1810 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1811 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1812 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1813 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1814 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1815
1816 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1817 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1818 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1819 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1820 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1821
1822 mode->flags = 0;
1823 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1824 if (misc & ATOM_VSYNC_POLARITY)
1825 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1826 if (misc & ATOM_HSYNC_POLARITY)
1827 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1828 if (misc & ATOM_COMPOSITESYNC)
1829 mode->flags |= DRM_MODE_FLAG_CSYNC;
1830 if (misc & ATOM_INTERLACE)
1831 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1832 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1833 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1834
1835 mode->crtc_clock = mode->clock =
1836 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1837
1838 if (index == 1) {
1839 /* PAL timings appear to have wrong values for totals */
1840 mode->crtc_htotal -= 1;
1841 mode->crtc_vtotal -= 1;
1842 }
1843 break;
1844 case 2:
1845 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1846 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1847 return false;
1848
1849 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1850 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1851 le16_to_cpu(dtd_timings->usHBlanking_Time);
1852 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1853 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1854 le16_to_cpu(dtd_timings->usHSyncOffset);
1855 mode->crtc_hsync_end = mode->crtc_hsync_start +
1856 le16_to_cpu(dtd_timings->usHSyncWidth);
1857
1858 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1859 le16_to_cpu(dtd_timings->usVBlanking_Time);
1860 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1861 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1862 le16_to_cpu(dtd_timings->usVSyncOffset);
1863 mode->crtc_vsync_end = mode->crtc_vsync_start +
1864 le16_to_cpu(dtd_timings->usVSyncWidth);
1865
1866 mode->flags = 0;
1867 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1868 if (misc & ATOM_VSYNC_POLARITY)
1869 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1870 if (misc & ATOM_HSYNC_POLARITY)
1871 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1872 if (misc & ATOM_COMPOSITESYNC)
1873 mode->flags |= DRM_MODE_FLAG_CSYNC;
1874 if (misc & ATOM_INTERLACE)
1875 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1876 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1877 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1878
1879 mode->crtc_clock = mode->clock =
1880 le16_to_cpu(dtd_timings->usPixClk) * 10;
1881 break;
1882 }
1883 return true;
1884}
1885
1886enum radeon_tv_std
1887radeon_atombios_get_tv_info(struct radeon_device *rdev)
1888{
1889 struct radeon_mode_info *mode_info = &rdev->mode_info;
1890 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1891 uint16_t data_offset;
1892 uint8_t frev, crev;
1893 struct _ATOM_ANALOG_TV_INFO *tv_info;
1894 enum radeon_tv_std tv_std = TV_STD_NTSC;
1895
1896 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1897 &frev, &crev, &data_offset)) {
1898
1899 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1900 (mode_info->atom_context->bios + data_offset);
1901
1902 switch (tv_info->ucTV_BootUpDefaultStandard) {
1903 case ATOM_TV_NTSC:
1904 tv_std = TV_STD_NTSC;
1905 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1906 break;
1907 case ATOM_TV_NTSCJ:
1908 tv_std = TV_STD_NTSC_J;
1909 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1910 break;
1911 case ATOM_TV_PAL:
1912 tv_std = TV_STD_PAL;
1913 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1914 break;
1915 case ATOM_TV_PALM:
1916 tv_std = TV_STD_PAL_M;
1917 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1918 break;
1919 case ATOM_TV_PALN:
1920 tv_std = TV_STD_PAL_N;
1921 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1922 break;
1923 case ATOM_TV_PALCN:
1924 tv_std = TV_STD_PAL_CN;
1925 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1926 break;
1927 case ATOM_TV_PAL60:
1928 tv_std = TV_STD_PAL_60;
1929 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1930 break;
1931 case ATOM_TV_SECAM:
1932 tv_std = TV_STD_SECAM;
1933 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1934 break;
1935 default:
1936 tv_std = TV_STD_NTSC;
1937 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1938 break;
1939 }
1940 }
1941 return tv_std;
1942}
1943
1944struct radeon_encoder_tv_dac *
1945radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1946{
1947 struct drm_device *dev = encoder->base.dev;
1948 struct radeon_device *rdev = dev->dev_private;
1949 struct radeon_mode_info *mode_info = &rdev->mode_info;
1950 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1951 uint16_t data_offset;
1952 struct _COMPASSIONATE_DATA *dac_info;
1953 uint8_t frev, crev;
1954 uint8_t bg, dac;
1955 struct radeon_encoder_tv_dac *tv_dac = NULL;
1956
1957 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1958 &frev, &crev, &data_offset)) {
1959
1960 dac_info = (struct _COMPASSIONATE_DATA *)
1961 (mode_info->atom_context->bios + data_offset);
1962
1963 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1964
1965 if (!tv_dac)
1966 return NULL;
1967
1968 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1969 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1970 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1971
1972 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1973 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1974 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1975
1976 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1977 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1978 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1979
1980 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1981 }
1982 return tv_dac;
1983}
1984
1985static const char *thermal_controller_names[] = {
1986 "NONE",
1987 "lm63",
1988 "adm1032",
1989 "adm1030",
1990 "max6649",
1991 "lm63", /* lm64 */
1992 "f75375",
1993 "asc7xxx",
1994};
1995
1996static const char *pp_lib_thermal_controller_names[] = {
1997 "NONE",
1998 "lm63",
1999 "adm1032",
2000 "adm1030",
2001 "max6649",
2002 "lm63", /* lm64 */
2003 "f75375",
2004 "RV6xx",
2005 "RV770",
2006 "adt7473",
2007 "NONE",
2008 "External GPIO",
2009 "Evergreen",
2010 "emc2103",
2011 "Sumo",
2012 "Northern Islands",
2013 "Southern Islands",
2014 "lm96163",
2015 "Sea Islands",
2016};
2017
2018union power_info {
2019 struct _ATOM_POWERPLAY_INFO info;
2020 struct _ATOM_POWERPLAY_INFO_V2 info_2;
2021 struct _ATOM_POWERPLAY_INFO_V3 info_3;
2022 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2023 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2024 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2025};
2026
2027union pplib_clock_info {
2028 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2029 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2030 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2031 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2032 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
2033 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
2034};
2035
2036union pplib_power_state {
2037 struct _ATOM_PPLIB_STATE v1;
2038 struct _ATOM_PPLIB_STATE_V2 v2;
2039};
2040
2041static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2042 int state_index,
2043 u32 misc, u32 misc2)
2044{
2045 rdev->pm.power_state[state_index].misc = misc;
2046 rdev->pm.power_state[state_index].misc2 = misc2;
2047 /* order matters! */
2048 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2049 rdev->pm.power_state[state_index].type =
2050 POWER_STATE_TYPE_POWERSAVE;
2051 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2052 rdev->pm.power_state[state_index].type =
2053 POWER_STATE_TYPE_BATTERY;
2054 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2055 rdev->pm.power_state[state_index].type =
2056 POWER_STATE_TYPE_BATTERY;
2057 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2058 rdev->pm.power_state[state_index].type =
2059 POWER_STATE_TYPE_BALANCED;
2060 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2061 rdev->pm.power_state[state_index].type =
2062 POWER_STATE_TYPE_PERFORMANCE;
2063 rdev->pm.power_state[state_index].flags &=
2064 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2065 }
2066 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2067 rdev->pm.power_state[state_index].type =
2068 POWER_STATE_TYPE_BALANCED;
2069 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2070 rdev->pm.power_state[state_index].type =
2071 POWER_STATE_TYPE_DEFAULT;
2072 rdev->pm.default_power_state_index = state_index;
2073 rdev->pm.power_state[state_index].default_clock_mode =
2074 &rdev->pm.power_state[state_index].clock_info[0];
2075 } else if (state_index == 0) {
2076 rdev->pm.power_state[state_index].clock_info[0].flags |=
2077 RADEON_PM_MODE_NO_DISPLAY;
2078 }
2079}
2080
2081static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2082{
2083 struct radeon_mode_info *mode_info = &rdev->mode_info;
2084 u32 misc, misc2 = 0;
2085 int num_modes = 0, i;
2086 int state_index = 0;
2087 struct radeon_i2c_bus_rec i2c_bus;
2088 union power_info *power_info;
2089 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2090 u16 data_offset;
2091 u8 frev, crev;
2092
2093 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2094 &frev, &crev, &data_offset))
2095 return state_index;
2096 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2097
2098 /* add the i2c bus for thermal/fan chip */
2099 if ((power_info->info.ucOverdriveThermalController > 0) &&
2100 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2101 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2102 thermal_controller_names[power_info->info.ucOverdriveThermalController],
2103 power_info->info.ucOverdriveControllerAddress >> 1);
2104 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2105 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2106 if (rdev->pm.i2c_bus) {
2107 struct i2c_board_info info = { };
2108 const char *name = thermal_controller_names[power_info->info.
2109 ucOverdriveThermalController];
2110 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2111 strscpy(info.type, name, sizeof(info.type));
2112 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2113 }
2114 }
2115 num_modes = power_info->info.ucNumOfPowerModeEntries;
2116 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2117 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2118 if (num_modes == 0)
2119 return state_index;
2120 rdev->pm.power_state = kcalloc(num_modes,
2121 sizeof(struct radeon_power_state),
2122 GFP_KERNEL);
2123 if (!rdev->pm.power_state)
2124 return state_index;
2125 /* last mode is usually default, array is low to high */
2126 for (i = 0; i < num_modes; i++) {
2127 /* avoid memory leaks from invalid modes or unknown frev. */
2128 if (!rdev->pm.power_state[state_index].clock_info) {
2129 rdev->pm.power_state[state_index].clock_info =
2130 kzalloc(sizeof(struct radeon_pm_clock_info),
2131 GFP_KERNEL);
2132 }
2133 if (!rdev->pm.power_state[state_index].clock_info)
2134 goto out;
2135 rdev->pm.power_state[state_index].num_clock_modes = 1;
2136 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2137 switch (frev) {
2138 case 1:
2139 rdev->pm.power_state[state_index].clock_info[0].mclk =
2140 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2141 rdev->pm.power_state[state_index].clock_info[0].sclk =
2142 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2143 /* skip invalid modes */
2144 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2145 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2146 continue;
2147 rdev->pm.power_state[state_index].pcie_lanes =
2148 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2149 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2150 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2151 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2152 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2153 VOLTAGE_GPIO;
2154 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2155 radeon_atombios_lookup_gpio(rdev,
2156 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2157 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2158 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2159 true;
2160 else
2161 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2162 false;
2163 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2164 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2165 VOLTAGE_VDDC;
2166 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2167 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2168 }
2169 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2170 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2171 state_index++;
2172 break;
2173 case 2:
2174 rdev->pm.power_state[state_index].clock_info[0].mclk =
2175 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2176 rdev->pm.power_state[state_index].clock_info[0].sclk =
2177 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2178 /* skip invalid modes */
2179 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2180 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2181 continue;
2182 rdev->pm.power_state[state_index].pcie_lanes =
2183 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2184 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2185 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2186 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2187 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2188 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2189 VOLTAGE_GPIO;
2190 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2191 radeon_atombios_lookup_gpio(rdev,
2192 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2193 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2194 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2195 true;
2196 else
2197 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2198 false;
2199 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2200 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2201 VOLTAGE_VDDC;
2202 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2203 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2204 }
2205 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2206 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2207 state_index++;
2208 break;
2209 case 3:
2210 rdev->pm.power_state[state_index].clock_info[0].mclk =
2211 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2212 rdev->pm.power_state[state_index].clock_info[0].sclk =
2213 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2214 /* skip invalid modes */
2215 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2216 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2217 continue;
2218 rdev->pm.power_state[state_index].pcie_lanes =
2219 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2220 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2221 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2222 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2223 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2224 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2225 VOLTAGE_GPIO;
2226 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2227 radeon_atombios_lookup_gpio(rdev,
2228 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2229 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2230 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2231 true;
2232 else
2233 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2234 false;
2235 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2236 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2237 VOLTAGE_VDDC;
2238 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2239 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2240 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2241 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2242 true;
2243 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2244 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2245 }
2246 }
2247 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2248 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2249 state_index++;
2250 break;
2251 }
2252 }
2253out:
2254 /* free any unused clock_info allocation. */
2255 if (state_index && state_index < num_modes) {
2256 kfree(rdev->pm.power_state[state_index].clock_info);
2257 rdev->pm.power_state[state_index].clock_info = NULL;
2258 }
2259
2260 /* last mode is usually default */
2261 if (state_index && rdev->pm.default_power_state_index == -1) {
2262 rdev->pm.power_state[state_index - 1].type =
2263 POWER_STATE_TYPE_DEFAULT;
2264 rdev->pm.default_power_state_index = state_index - 1;
2265 rdev->pm.power_state[state_index - 1].default_clock_mode =
2266 &rdev->pm.power_state[state_index - 1].clock_info[0];
2267 rdev->pm.power_state[state_index - 1].flags &=
2268 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2269 rdev->pm.power_state[state_index - 1].misc = 0;
2270 rdev->pm.power_state[state_index - 1].misc2 = 0;
2271 }
2272 return state_index;
2273}
2274
2275static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2276 ATOM_PPLIB_THERMALCONTROLLER *controller)
2277{
2278 struct radeon_i2c_bus_rec i2c_bus;
2279
2280 /* add the i2c bus for thermal/fan chip */
2281 if (controller->ucType > 0) {
2282 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN)
2283 rdev->pm.no_fan = true;
2284 rdev->pm.fan_pulses_per_revolution =
2285 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
2286 if (rdev->pm.fan_pulses_per_revolution) {
2287 rdev->pm.fan_min_rpm = controller->ucFanMinRPM;
2288 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM;
2289 }
2290 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2291 DRM_INFO("Internal thermal controller %s fan control\n",
2292 (controller->ucFanParameters &
2293 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2294 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2295 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2296 DRM_INFO("Internal thermal controller %s fan control\n",
2297 (controller->ucFanParameters &
2298 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2299 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2300 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2301 DRM_INFO("Internal thermal controller %s fan control\n",
2302 (controller->ucFanParameters &
2303 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2304 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2305 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2306 DRM_INFO("Internal thermal controller %s fan control\n",
2307 (controller->ucFanParameters &
2308 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2309 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2310 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2311 DRM_INFO("Internal thermal controller %s fan control\n",
2312 (controller->ucFanParameters &
2313 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2314 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2315 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2316 DRM_INFO("Internal thermal controller %s fan control\n",
2317 (controller->ucFanParameters &
2318 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2319 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2320 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2321 DRM_INFO("Internal thermal controller %s fan control\n",
2322 (controller->ucFanParameters &
2323 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2324 rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2325 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
2326 DRM_INFO("Internal thermal controller %s fan control\n",
2327 (controller->ucFanParameters &
2328 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2329 rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2330 } else if (controller->ucType ==
2331 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
2332 DRM_INFO("External GPIO thermal controller %s fan control\n",
2333 (controller->ucFanParameters &
2334 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2335 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
2336 } else if (controller->ucType ==
2337 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
2338 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
2339 (controller->ucFanParameters &
2340 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2341 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
2342 } else if (controller->ucType ==
2343 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
2344 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
2345 (controller->ucFanParameters &
2346 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2347 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2348 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2349 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2350 pp_lib_thermal_controller_names[controller->ucType],
2351 controller->ucI2cAddress >> 1,
2352 (controller->ucFanParameters &
2353 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2354 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
2355 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2356 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2357 if (rdev->pm.i2c_bus) {
2358 struct i2c_board_info info = { };
2359 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2360 info.addr = controller->ucI2cAddress >> 1;
2361 strscpy(info.type, name, sizeof(info.type));
2362 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2363 }
2364 } else {
2365 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2366 controller->ucType,
2367 controller->ucI2cAddress >> 1,
2368 (controller->ucFanParameters &
2369 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2370 }
2371 }
2372}
2373
2374void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2375 u16 *vddc, u16 *vddci, u16 *mvdd)
2376{
2377 struct radeon_mode_info *mode_info = &rdev->mode_info;
2378 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2379 u8 frev, crev;
2380 u16 data_offset;
2381 union firmware_info *firmware_info;
2382
2383 *vddc = 0;
2384 *vddci = 0;
2385 *mvdd = 0;
2386
2387 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2388 &frev, &crev, &data_offset)) {
2389 firmware_info =
2390 (union firmware_info *)(mode_info->atom_context->bios +
2391 data_offset);
2392 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2393 if ((frev == 2) && (crev >= 2)) {
2394 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2395 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2396 }
2397 }
2398}
2399
2400static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2401 int state_index, int mode_index,
2402 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2403{
2404 int j;
2405 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2406 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2407 u16 vddc, vddci, mvdd;
2408
2409 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2410
2411 rdev->pm.power_state[state_index].misc = misc;
2412 rdev->pm.power_state[state_index].misc2 = misc2;
2413 rdev->pm.power_state[state_index].pcie_lanes =
2414 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2415 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2416 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2417 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2418 rdev->pm.power_state[state_index].type =
2419 POWER_STATE_TYPE_BATTERY;
2420 break;
2421 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2422 rdev->pm.power_state[state_index].type =
2423 POWER_STATE_TYPE_BALANCED;
2424 break;
2425 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2426 rdev->pm.power_state[state_index].type =
2427 POWER_STATE_TYPE_PERFORMANCE;
2428 break;
2429 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2430 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2431 rdev->pm.power_state[state_index].type =
2432 POWER_STATE_TYPE_PERFORMANCE;
2433 break;
2434 }
2435 rdev->pm.power_state[state_index].flags = 0;
2436 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2437 rdev->pm.power_state[state_index].flags |=
2438 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2439 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2440 rdev->pm.power_state[state_index].type =
2441 POWER_STATE_TYPE_DEFAULT;
2442 rdev->pm.default_power_state_index = state_index;
2443 rdev->pm.power_state[state_index].default_clock_mode =
2444 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2445 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2446 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2447 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2448 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2449 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2450 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2451 } else {
2452 u16 max_vddci = 0;
2453
2454 if (ASIC_IS_DCE4(rdev))
2455 radeon_atom_get_max_voltage(rdev,
2456 SET_VOLTAGE_TYPE_ASIC_VDDCI,
2457 &max_vddci);
2458 /* patch the table values with the default sclk/mclk from firmware info */
2459 for (j = 0; j < mode_index; j++) {
2460 rdev->pm.power_state[state_index].clock_info[j].mclk =
2461 rdev->clock.default_mclk;
2462 rdev->pm.power_state[state_index].clock_info[j].sclk =
2463 rdev->clock.default_sclk;
2464 if (vddc)
2465 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2466 vddc;
2467 if (max_vddci)
2468 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2469 max_vddci;
2470 }
2471 }
2472 }
2473}
2474
2475static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2476 int state_index, int mode_index,
2477 union pplib_clock_info *clock_info)
2478{
2479 u32 sclk, mclk;
2480 u16 vddc;
2481
2482 if (rdev->flags & RADEON_IS_IGP) {
2483 if (rdev->family >= CHIP_PALM) {
2484 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2485 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2486 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2487 } else {
2488 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2489 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2490 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2491 }
2492 } else if (rdev->family >= CHIP_BONAIRE) {
2493 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2494 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2495 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2496 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2497 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2498 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2499 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2500 VOLTAGE_NONE;
2501 } else if (rdev->family >= CHIP_TAHITI) {
2502 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2503 sclk |= clock_info->si.ucEngineClockHigh << 16;
2504 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2505 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2506 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2507 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2508 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2509 VOLTAGE_SW;
2510 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2511 le16_to_cpu(clock_info->si.usVDDC);
2512 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2513 le16_to_cpu(clock_info->si.usVDDCI);
2514 } else if (rdev->family >= CHIP_CEDAR) {
2515 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2516 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2517 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2518 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2519 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2520 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2521 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2522 VOLTAGE_SW;
2523 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2524 le16_to_cpu(clock_info->evergreen.usVDDC);
2525 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2526 le16_to_cpu(clock_info->evergreen.usVDDCI);
2527 } else {
2528 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2529 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2530 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2531 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2532 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2533 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2534 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2535 VOLTAGE_SW;
2536 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2537 le16_to_cpu(clock_info->r600.usVDDC);
2538 }
2539
2540 /* patch up vddc if necessary */
2541 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2542 case ATOM_VIRTUAL_VOLTAGE_ID0:
2543 case ATOM_VIRTUAL_VOLTAGE_ID1:
2544 case ATOM_VIRTUAL_VOLTAGE_ID2:
2545 case ATOM_VIRTUAL_VOLTAGE_ID3:
2546 case ATOM_VIRTUAL_VOLTAGE_ID4:
2547 case ATOM_VIRTUAL_VOLTAGE_ID5:
2548 case ATOM_VIRTUAL_VOLTAGE_ID6:
2549 case ATOM_VIRTUAL_VOLTAGE_ID7:
2550 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2551 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2552 &vddc) == 0)
2553 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2554 break;
2555 default:
2556 break;
2557 }
2558
2559 if (rdev->flags & RADEON_IS_IGP) {
2560 /* skip invalid modes */
2561 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2562 return false;
2563 } else {
2564 /* skip invalid modes */
2565 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2566 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2567 return false;
2568 }
2569 return true;
2570}
2571
2572static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2573{
2574 struct radeon_mode_info *mode_info = &rdev->mode_info;
2575 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2576 union pplib_power_state *power_state;
2577 int i, j;
2578 int state_index = 0, mode_index = 0;
2579 union pplib_clock_info *clock_info;
2580 bool valid;
2581 union power_info *power_info;
2582 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2583 u16 data_offset;
2584 u8 frev, crev;
2585
2586 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2587 &frev, &crev, &data_offset))
2588 return state_index;
2589 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2590
2591 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2592 if (power_info->pplib.ucNumStates == 0)
2593 return state_index;
2594 rdev->pm.power_state = kcalloc(power_info->pplib.ucNumStates,
2595 sizeof(struct radeon_power_state),
2596 GFP_KERNEL);
2597 if (!rdev->pm.power_state)
2598 return state_index;
2599 /* first mode is usually default, followed by low to high */
2600 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2601 mode_index = 0;
2602 power_state = (union pplib_power_state *)
2603 (mode_info->atom_context->bios + data_offset +
2604 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2605 i * power_info->pplib.ucStateEntrySize);
2606 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2607 (mode_info->atom_context->bios + data_offset +
2608 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2609 (power_state->v1.ucNonClockStateIndex *
2610 power_info->pplib.ucNonClockSize));
2611 rdev->pm.power_state[i].clock_info =
2612 kcalloc((power_info->pplib.ucStateEntrySize - 1) ?
2613 (power_info->pplib.ucStateEntrySize - 1) : 1,
2614 sizeof(struct radeon_pm_clock_info),
2615 GFP_KERNEL);
2616 if (!rdev->pm.power_state[i].clock_info)
2617 return state_index;
2618 if (power_info->pplib.ucStateEntrySize - 1) {
2619 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2620 clock_info = (union pplib_clock_info *)
2621 (mode_info->atom_context->bios + data_offset +
2622 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2623 (power_state->v1.ucClockStateIndices[j] *
2624 power_info->pplib.ucClockInfoSize));
2625 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2626 state_index, mode_index,
2627 clock_info);
2628 if (valid)
2629 mode_index++;
2630 }
2631 } else {
2632 rdev->pm.power_state[state_index].clock_info[0].mclk =
2633 rdev->clock.default_mclk;
2634 rdev->pm.power_state[state_index].clock_info[0].sclk =
2635 rdev->clock.default_sclk;
2636 mode_index++;
2637 }
2638 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2639 if (mode_index) {
2640 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2641 non_clock_info);
2642 state_index++;
2643 }
2644 }
2645 /* if multiple clock modes, mark the lowest as no display */
2646 for (i = 0; i < state_index; i++) {
2647 if (rdev->pm.power_state[i].num_clock_modes > 1)
2648 rdev->pm.power_state[i].clock_info[0].flags |=
2649 RADEON_PM_MODE_NO_DISPLAY;
2650 }
2651 /* first mode is usually default */
2652 if (rdev->pm.default_power_state_index == -1) {
2653 rdev->pm.power_state[0].type =
2654 POWER_STATE_TYPE_DEFAULT;
2655 rdev->pm.default_power_state_index = 0;
2656 rdev->pm.power_state[0].default_clock_mode =
2657 &rdev->pm.power_state[0].clock_info[0];
2658 }
2659 return state_index;
2660}
2661
2662static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2663{
2664 struct radeon_mode_info *mode_info = &rdev->mode_info;
2665 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2666 union pplib_power_state *power_state;
2667 int i, j, non_clock_array_index, clock_array_index;
2668 int state_index = 0, mode_index = 0;
2669 union pplib_clock_info *clock_info;
2670 struct _StateArray *state_array;
2671 struct _ClockInfoArray *clock_info_array;
2672 struct _NonClockInfoArray *non_clock_info_array;
2673 bool valid;
2674 union power_info *power_info;
2675 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2676 u16 data_offset;
2677 u8 frev, crev;
2678 u8 *power_state_offset;
2679
2680 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2681 &frev, &crev, &data_offset))
2682 return state_index;
2683 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2684
2685 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2686 state_array = (struct _StateArray *)
2687 (mode_info->atom_context->bios + data_offset +
2688 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2689 clock_info_array = (struct _ClockInfoArray *)
2690 (mode_info->atom_context->bios + data_offset +
2691 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2692 non_clock_info_array = (struct _NonClockInfoArray *)
2693 (mode_info->atom_context->bios + data_offset +
2694 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2695 if (state_array->ucNumEntries == 0)
2696 return state_index;
2697 rdev->pm.power_state = kcalloc(state_array->ucNumEntries,
2698 sizeof(struct radeon_power_state),
2699 GFP_KERNEL);
2700 if (!rdev->pm.power_state)
2701 return state_index;
2702 power_state_offset = (u8 *)state_array->states;
2703 for (i = 0; i < state_array->ucNumEntries; i++) {
2704 mode_index = 0;
2705 power_state = (union pplib_power_state *)power_state_offset;
2706 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2707 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2708 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2709 rdev->pm.power_state[i].clock_info =
2710 kcalloc(power_state->v2.ucNumDPMLevels ?
2711 power_state->v2.ucNumDPMLevels : 1,
2712 sizeof(struct radeon_pm_clock_info),
2713 GFP_KERNEL);
2714 if (!rdev->pm.power_state[i].clock_info)
2715 return state_index;
2716 if (power_state->v2.ucNumDPMLevels) {
2717 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2718 clock_array_index = power_state->v2.clockInfoIndex[j];
2719 clock_info = (union pplib_clock_info *)
2720 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2721 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2722 state_index, mode_index,
2723 clock_info);
2724 if (valid)
2725 mode_index++;
2726 }
2727 } else {
2728 rdev->pm.power_state[state_index].clock_info[0].mclk =
2729 rdev->clock.default_mclk;
2730 rdev->pm.power_state[state_index].clock_info[0].sclk =
2731 rdev->clock.default_sclk;
2732 mode_index++;
2733 }
2734 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2735 if (mode_index) {
2736 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2737 non_clock_info);
2738 state_index++;
2739 }
2740 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2741 }
2742 /* if multiple clock modes, mark the lowest as no display */
2743 for (i = 0; i < state_index; i++) {
2744 if (rdev->pm.power_state[i].num_clock_modes > 1)
2745 rdev->pm.power_state[i].clock_info[0].flags |=
2746 RADEON_PM_MODE_NO_DISPLAY;
2747 }
2748 /* first mode is usually default */
2749 if (rdev->pm.default_power_state_index == -1) {
2750 rdev->pm.power_state[0].type =
2751 POWER_STATE_TYPE_DEFAULT;
2752 rdev->pm.default_power_state_index = 0;
2753 rdev->pm.power_state[0].default_clock_mode =
2754 &rdev->pm.power_state[0].clock_info[0];
2755 }
2756 return state_index;
2757}
2758
2759void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2760{
2761 struct radeon_mode_info *mode_info = &rdev->mode_info;
2762 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2763 u16 data_offset;
2764 u8 frev, crev;
2765 int state_index = 0;
2766
2767 rdev->pm.default_power_state_index = -1;
2768
2769 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2770 &frev, &crev, &data_offset)) {
2771 switch (frev) {
2772 case 1:
2773 case 2:
2774 case 3:
2775 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2776 break;
2777 case 4:
2778 case 5:
2779 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2780 break;
2781 case 6:
2782 state_index = radeon_atombios_parse_power_table_6(rdev);
2783 break;
2784 default:
2785 break;
2786 }
2787 }
2788
2789 if (state_index == 0) {
2790 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2791 if (rdev->pm.power_state) {
2792 rdev->pm.power_state[0].clock_info =
2793 kcalloc(1,
2794 sizeof(struct radeon_pm_clock_info),
2795 GFP_KERNEL);
2796 if (rdev->pm.power_state[0].clock_info) {
2797 /* add the default mode */
2798 rdev->pm.power_state[state_index].type =
2799 POWER_STATE_TYPE_DEFAULT;
2800 rdev->pm.power_state[state_index].num_clock_modes = 1;
2801 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2802 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2803 rdev->pm.power_state[state_index].default_clock_mode =
2804 &rdev->pm.power_state[state_index].clock_info[0];
2805 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2806 rdev->pm.power_state[state_index].pcie_lanes = 16;
2807 rdev->pm.default_power_state_index = state_index;
2808 rdev->pm.power_state[state_index].flags = 0;
2809 state_index++;
2810 }
2811 }
2812 }
2813
2814 rdev->pm.num_power_states = state_index;
2815
2816 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2817 rdev->pm.current_clock_mode_index = 0;
2818 if (rdev->pm.default_power_state_index >= 0)
2819 rdev->pm.current_vddc =
2820 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2821 else
2822 rdev->pm.current_vddc = 0;
2823}
2824
2825union get_clock_dividers {
2826 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2827 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2828 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2829 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2830 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2831 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2832 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2833};
2834
2835int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2836 u8 clock_type,
2837 u32 clock,
2838 bool strobe_mode,
2839 struct atom_clock_dividers *dividers)
2840{
2841 union get_clock_dividers args;
2842 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2843 u8 frev, crev;
2844
2845 memset(&args, 0, sizeof(args));
2846 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2847
2848 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2849 return -EINVAL;
2850
2851 switch (crev) {
2852 case 1:
2853 /* r4xx, r5xx */
2854 args.v1.ucAction = clock_type;
2855 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
2856
2857 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2858
2859 dividers->post_div = args.v1.ucPostDiv;
2860 dividers->fb_div = args.v1.ucFbDiv;
2861 dividers->enable_post_div = true;
2862 break;
2863 case 2:
2864 case 3:
2865 case 5:
2866 /* r6xx, r7xx, evergreen, ni, si */
2867 if (rdev->family <= CHIP_RV770) {
2868 args.v2.ucAction = clock_type;
2869 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
2870
2871 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2872
2873 dividers->post_div = args.v2.ucPostDiv;
2874 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2875 dividers->ref_div = args.v2.ucAction;
2876 if (rdev->family == CHIP_RV770) {
2877 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2878 true : false;
2879 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2880 } else
2881 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2882 } else {
2883 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2884 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2885
2886 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2887
2888 dividers->post_div = args.v3.ucPostDiv;
2889 dividers->enable_post_div = (args.v3.ucCntlFlag &
2890 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2891 dividers->enable_dithen = (args.v3.ucCntlFlag &
2892 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2893 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2894 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2895 dividers->ref_div = args.v3.ucRefDiv;
2896 dividers->vco_mode = (args.v3.ucCntlFlag &
2897 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2898 } else {
2899 /* for SI we use ComputeMemoryClockParam for memory plls */
2900 if (rdev->family >= CHIP_TAHITI)
2901 return -EINVAL;
2902 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2903 if (strobe_mode)
2904 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2905
2906 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2907
2908 dividers->post_div = args.v5.ucPostDiv;
2909 dividers->enable_post_div = (args.v5.ucCntlFlag &
2910 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2911 dividers->enable_dithen = (args.v5.ucCntlFlag &
2912 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2913 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2914 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2915 dividers->ref_div = args.v5.ucRefDiv;
2916 dividers->vco_mode = (args.v5.ucCntlFlag &
2917 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2918 }
2919 }
2920 break;
2921 case 4:
2922 /* fusion */
2923 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
2924
2925 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2926
2927 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2928 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2929 break;
2930 case 6:
2931 /* CI */
2932 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2933 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2934 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2935
2936 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2937
2938 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2939 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2940 dividers->ref_div = args.v6_out.ucPllRefDiv;
2941 dividers->post_div = args.v6_out.ucPllPostDiv;
2942 dividers->flags = args.v6_out.ucPllCntlFlag;
2943 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2944 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2945 break;
2946 default:
2947 return -EINVAL;
2948 }
2949 return 0;
2950}
2951
2952int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2953 u32 clock,
2954 bool strobe_mode,
2955 struct atom_mpll_param *mpll_param)
2956{
2957 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2958 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2959 u8 frev, crev;
2960
2961 memset(&args, 0, sizeof(args));
2962 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2963
2964 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2965 return -EINVAL;
2966
2967 switch (frev) {
2968 case 2:
2969 switch (crev) {
2970 case 1:
2971 /* SI */
2972 args.ulClock = cpu_to_le32(clock); /* 10 khz */
2973 args.ucInputFlag = 0;
2974 if (strobe_mode)
2975 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2976
2977 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2978
2979 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2980 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2981 mpll_param->post_div = args.ucPostDiv;
2982 mpll_param->dll_speed = args.ucDllSpeed;
2983 mpll_param->bwcntl = args.ucBWCntl;
2984 mpll_param->vco_mode =
2985 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
2986 mpll_param->yclk_sel =
2987 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2988 mpll_param->qdr =
2989 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2990 mpll_param->half_rate =
2991 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
2992 break;
2993 default:
2994 return -EINVAL;
2995 }
2996 break;
2997 default:
2998 return -EINVAL;
2999 }
3000 return 0;
3001}
3002
3003void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
3004{
3005 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
3006 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
3007
3008 args.ucEnable = enable;
3009
3010 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3011}
3012
3013uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
3014{
3015 GET_ENGINE_CLOCK_PS_ALLOCATION args;
3016 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
3017
3018 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3019 return le32_to_cpu(args.ulReturnEngineClock);
3020}
3021
3022uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
3023{
3024 GET_MEMORY_CLOCK_PS_ALLOCATION args;
3025 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
3026
3027 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3028 return le32_to_cpu(args.ulReturnMemoryClock);
3029}
3030
3031void radeon_atom_set_engine_clock(struct radeon_device *rdev,
3032 uint32_t eng_clock)
3033{
3034 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3035 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
3036
3037 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
3038
3039 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3040}
3041
3042void radeon_atom_set_memory_clock(struct radeon_device *rdev,
3043 uint32_t mem_clock)
3044{
3045 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3046 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
3047
3048 if (rdev->flags & RADEON_IS_IGP)
3049 return;
3050
3051 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
3052
3053 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3054}
3055
3056void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
3057 u32 eng_clock, u32 mem_clock)
3058{
3059 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3060 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3061 u32 tmp;
3062
3063 memset(&args, 0, sizeof(args));
3064
3065 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
3066 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
3067
3068 args.ulTargetEngineClock = cpu_to_le32(tmp);
3069 if (mem_clock)
3070 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
3071
3072 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3073}
3074
3075void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3076 u32 mem_clock)
3077{
3078 u32 args;
3079 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3080
3081 args = cpu_to_le32(mem_clock); /* 10 khz */
3082
3083 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3084}
3085
3086void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3087 u32 mem_clock)
3088{
3089 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3090 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3091 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
3092
3093 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */
3094
3095 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3096}
3097
3098union set_voltage {
3099 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
3100 struct _SET_VOLTAGE_PARAMETERS v1;
3101 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
3102 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
3103};
3104
3105void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3106{
3107 union set_voltage args;
3108 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3109 u8 frev, crev, volt_index = voltage_level;
3110
3111 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3112 return;
3113
3114 /* 0xff01 is a flag rather then an actual voltage */
3115 if (voltage_level == 0xff01)
3116 return;
3117
3118 switch (crev) {
3119 case 1:
3120 args.v1.ucVoltageType = voltage_type;
3121 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3122 args.v1.ucVoltageIndex = volt_index;
3123 break;
3124 case 2:
3125 args.v2.ucVoltageType = voltage_type;
3126 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3127 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3128 break;
3129 case 3:
3130 args.v3.ucVoltageType = voltage_type;
3131 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3132 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3133 break;
3134 default:
3135 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3136 return;
3137 }
3138
3139 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3140}
3141
3142int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3143 u16 voltage_id, u16 *voltage)
3144{
3145 union set_voltage args;
3146 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3147 u8 frev, crev;
3148
3149 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3150 return -EINVAL;
3151
3152 switch (crev) {
3153 case 1:
3154 return -EINVAL;
3155 case 2:
3156 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3157 args.v2.ucVoltageMode = 0;
3158 args.v2.usVoltageLevel = 0;
3159
3160 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3161
3162 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3163 break;
3164 case 3:
3165 args.v3.ucVoltageType = voltage_type;
3166 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3167 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3168
3169 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3170
3171 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3172 break;
3173 default:
3174 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3175 return -EINVAL;
3176 }
3177
3178 return 0;
3179}
3180
3181int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3182 u16 *voltage,
3183 u16 leakage_idx)
3184{
3185 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3186}
3187
3188int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3189 u16 *leakage_id)
3190{
3191 union set_voltage args;
3192 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3193 u8 frev, crev;
3194
3195 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3196 return -EINVAL;
3197
3198 switch (crev) {
3199 case 3:
3200 case 4:
3201 args.v3.ucVoltageType = 0;
3202 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
3203 args.v3.usVoltageLevel = 0;
3204
3205 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3206
3207 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
3208 break;
3209 default:
3210 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3211 return -EINVAL;
3212 }
3213
3214 return 0;
3215}
3216
3217int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3218 u16 *vddc, u16 *vddci,
3219 u16 virtual_voltage_id,
3220 u16 vbios_voltage_id)
3221{
3222 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
3223 u8 frev, crev;
3224 u16 data_offset, size;
3225 int i, j;
3226 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
3227 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
3228
3229 *vddc = 0;
3230 *vddci = 0;
3231
3232 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3233 &frev, &crev, &data_offset))
3234 return -EINVAL;
3235
3236 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
3237 (rdev->mode_info.atom_context->bios + data_offset);
3238
3239 switch (frev) {
3240 case 1:
3241 return -EINVAL;
3242 case 2:
3243 switch (crev) {
3244 case 1:
3245 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
3246 return -EINVAL;
3247 leakage_bin = (u16 *)
3248 (rdev->mode_info.atom_context->bios + data_offset +
3249 le16_to_cpu(profile->usLeakageBinArrayOffset));
3250 vddc_id_buf = (u16 *)
3251 (rdev->mode_info.atom_context->bios + data_offset +
3252 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
3253 vddc_buf = (u16 *)
3254 (rdev->mode_info.atom_context->bios + data_offset +
3255 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
3256 vddci_id_buf = (u16 *)
3257 (rdev->mode_info.atom_context->bios + data_offset +
3258 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
3259 vddci_buf = (u16 *)
3260 (rdev->mode_info.atom_context->bios + data_offset +
3261 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
3262
3263 if (profile->ucElbVDDC_Num > 0) {
3264 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
3265 if (vddc_id_buf[i] == virtual_voltage_id) {
3266 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3267 if (vbios_voltage_id <= leakage_bin[j]) {
3268 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
3269 break;
3270 }
3271 }
3272 break;
3273 }
3274 }
3275 }
3276 if (profile->ucElbVDDCI_Num > 0) {
3277 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
3278 if (vddci_id_buf[i] == virtual_voltage_id) {
3279 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3280 if (vbios_voltage_id <= leakage_bin[j]) {
3281 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
3282 break;
3283 }
3284 }
3285 break;
3286 }
3287 }
3288 }
3289 break;
3290 default:
3291 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3292 return -EINVAL;
3293 }
3294 break;
3295 default:
3296 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3297 return -EINVAL;
3298 }
3299
3300 return 0;
3301}
3302
3303union get_voltage_info {
3304 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
3305 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
3306};
3307
3308int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
3309 u16 virtual_voltage_id,
3310 u16 *voltage)
3311{
3312 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
3313 u32 entry_id;
3314 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
3315 union get_voltage_info args;
3316
3317 for (entry_id = 0; entry_id < count; entry_id++) {
3318 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
3319 virtual_voltage_id)
3320 break;
3321 }
3322
3323 if (entry_id >= count)
3324 return -EINVAL;
3325
3326 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
3327 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
3328 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
3329 args.in.ulSCLKFreq =
3330 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
3331
3332 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3333
3334 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
3335
3336 return 0;
3337}
3338
3339int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3340 u16 voltage_level, u8 voltage_type,
3341 u32 *gpio_value, u32 *gpio_mask)
3342{
3343 union set_voltage args;
3344 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3345 u8 frev, crev;
3346
3347 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3348 return -EINVAL;
3349
3350 switch (crev) {
3351 case 1:
3352 return -EINVAL;
3353 case 2:
3354 args.v2.ucVoltageType = voltage_type;
3355 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3356 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3357
3358 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3359
3360 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3361
3362 args.v2.ucVoltageType = voltage_type;
3363 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3364 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3365
3366 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3367
3368 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3369 break;
3370 default:
3371 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3372 return -EINVAL;
3373 }
3374
3375 return 0;
3376}
3377
3378union voltage_object_info {
3379 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3380 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3381 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3382};
3383
3384union voltage_object {
3385 struct _ATOM_VOLTAGE_OBJECT v1;
3386 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3387 union _ATOM_VOLTAGE_OBJECT_V3 v3;
3388};
3389
3390static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3391 u8 voltage_type)
3392{
3393 u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3394 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3395 u8 *start = (u8 *)v1;
3396
3397 while (offset < size) {
3398 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3399 if (vo->ucVoltageType == voltage_type)
3400 return vo;
3401 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3402 vo->asFormula.ucNumOfVoltageEntries;
3403 }
3404 return NULL;
3405}
3406
3407static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3408 u8 voltage_type)
3409{
3410 u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3411 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3412 u8 *start = (u8 *)v2;
3413
3414 while (offset < size) {
3415 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3416 if (vo->ucVoltageType == voltage_type)
3417 return vo;
3418 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3419 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3420 }
3421 return NULL;
3422}
3423
3424static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3425 u8 voltage_type, u8 voltage_mode)
3426{
3427 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3428 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3429 u8 *start = (u8 *)v3;
3430
3431 while (offset < size) {
3432 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3433 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3434 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3435 return vo;
3436 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3437 }
3438 return NULL;
3439}
3440
3441bool
3442radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3443 u8 voltage_type, u8 voltage_mode)
3444{
3445 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3446 u8 frev, crev;
3447 u16 data_offset, size;
3448 union voltage_object_info *voltage_info;
3449 union voltage_object *voltage_object = NULL;
3450
3451 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3452 &frev, &crev, &data_offset)) {
3453 voltage_info = (union voltage_object_info *)
3454 (rdev->mode_info.atom_context->bios + data_offset);
3455
3456 switch (frev) {
3457 case 1:
3458 case 2:
3459 switch (crev) {
3460 case 1:
3461 voltage_object = (union voltage_object *)
3462 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3463 if (voltage_object &&
3464 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3465 return true;
3466 break;
3467 case 2:
3468 voltage_object = (union voltage_object *)
3469 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3470 if (voltage_object &&
3471 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3472 return true;
3473 break;
3474 default:
3475 DRM_ERROR("unknown voltage object table\n");
3476 return false;
3477 }
3478 break;
3479 case 3:
3480 switch (crev) {
3481 case 1:
3482 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3483 voltage_type, voltage_mode))
3484 return true;
3485 break;
3486 default:
3487 DRM_ERROR("unknown voltage object table\n");
3488 return false;
3489 }
3490 break;
3491 default:
3492 DRM_ERROR("unknown voltage object table\n");
3493 return false;
3494 }
3495
3496 }
3497 return false;
3498}
3499
3500int radeon_atom_get_svi2_info(struct radeon_device *rdev,
3501 u8 voltage_type,
3502 u8 *svd_gpio_id, u8 *svc_gpio_id)
3503{
3504 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3505 u8 frev, crev;
3506 u16 data_offset, size;
3507 union voltage_object_info *voltage_info;
3508 union voltage_object *voltage_object = NULL;
3509
3510 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3511 &frev, &crev, &data_offset)) {
3512 voltage_info = (union voltage_object_info *)
3513 (rdev->mode_info.atom_context->bios + data_offset);
3514
3515 switch (frev) {
3516 case 3:
3517 switch (crev) {
3518 case 1:
3519 voltage_object = (union voltage_object *)
3520 atom_lookup_voltage_object_v3(&voltage_info->v3,
3521 voltage_type,
3522 VOLTAGE_OBJ_SVID2);
3523 if (voltage_object) {
3524 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
3525 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
3526 } else {
3527 return -EINVAL;
3528 }
3529 break;
3530 default:
3531 DRM_ERROR("unknown voltage object table\n");
3532 return -EINVAL;
3533 }
3534 break;
3535 default:
3536 DRM_ERROR("unknown voltage object table\n");
3537 return -EINVAL;
3538 }
3539
3540 }
3541 return 0;
3542}
3543
3544int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3545 u8 voltage_type, u16 *max_voltage)
3546{
3547 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3548 u8 frev, crev;
3549 u16 data_offset, size;
3550 union voltage_object_info *voltage_info;
3551 union voltage_object *voltage_object = NULL;
3552
3553 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3554 &frev, &crev, &data_offset)) {
3555 voltage_info = (union voltage_object_info *)
3556 (rdev->mode_info.atom_context->bios + data_offset);
3557
3558 switch (crev) {
3559 case 1:
3560 voltage_object = (union voltage_object *)
3561 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3562 if (voltage_object) {
3563 ATOM_VOLTAGE_FORMULA *formula =
3564 &voltage_object->v1.asFormula;
3565 if (formula->ucFlag & 1)
3566 *max_voltage =
3567 le16_to_cpu(formula->usVoltageBaseLevel) +
3568 formula->ucNumOfVoltageEntries / 2 *
3569 le16_to_cpu(formula->usVoltageStep);
3570 else
3571 *max_voltage =
3572 le16_to_cpu(formula->usVoltageBaseLevel) +
3573 (formula->ucNumOfVoltageEntries - 1) *
3574 le16_to_cpu(formula->usVoltageStep);
3575 return 0;
3576 }
3577 break;
3578 case 2:
3579 voltage_object = (union voltage_object *)
3580 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3581 if (voltage_object) {
3582 ATOM_VOLTAGE_FORMULA_V2 *formula =
3583 &voltage_object->v2.asFormula;
3584 if (formula->ucNumOfVoltageEntries) {
3585 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *)
3586 ((u8 *)&formula->asVIDAdjustEntries[0] +
3587 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
3588 *max_voltage =
3589 le16_to_cpu(lut->usVoltageValue);
3590 return 0;
3591 }
3592 }
3593 break;
3594 default:
3595 DRM_ERROR("unknown voltage object table\n");
3596 return -EINVAL;
3597 }
3598
3599 }
3600 return -EINVAL;
3601}
3602
3603int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3604 u8 voltage_type, u16 *min_voltage)
3605{
3606 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3607 u8 frev, crev;
3608 u16 data_offset, size;
3609 union voltage_object_info *voltage_info;
3610 union voltage_object *voltage_object = NULL;
3611
3612 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3613 &frev, &crev, &data_offset)) {
3614 voltage_info = (union voltage_object_info *)
3615 (rdev->mode_info.atom_context->bios + data_offset);
3616
3617 switch (crev) {
3618 case 1:
3619 voltage_object = (union voltage_object *)
3620 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3621 if (voltage_object) {
3622 ATOM_VOLTAGE_FORMULA *formula =
3623 &voltage_object->v1.asFormula;
3624 *min_voltage =
3625 le16_to_cpu(formula->usVoltageBaseLevel);
3626 return 0;
3627 }
3628 break;
3629 case 2:
3630 voltage_object = (union voltage_object *)
3631 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3632 if (voltage_object) {
3633 ATOM_VOLTAGE_FORMULA_V2 *formula =
3634 &voltage_object->v2.asFormula;
3635 if (formula->ucNumOfVoltageEntries) {
3636 *min_voltage =
3637 le16_to_cpu(formula->asVIDAdjustEntries[
3638 0
3639 ].usVoltageValue);
3640 return 0;
3641 }
3642 }
3643 break;
3644 default:
3645 DRM_ERROR("unknown voltage object table\n");
3646 return -EINVAL;
3647 }
3648
3649 }
3650 return -EINVAL;
3651}
3652
3653int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3654 u8 voltage_type, u16 *voltage_step)
3655{
3656 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3657 u8 frev, crev;
3658 u16 data_offset, size;
3659 union voltage_object_info *voltage_info;
3660 union voltage_object *voltage_object = NULL;
3661
3662 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3663 &frev, &crev, &data_offset)) {
3664 voltage_info = (union voltage_object_info *)
3665 (rdev->mode_info.atom_context->bios + data_offset);
3666
3667 switch (crev) {
3668 case 1:
3669 voltage_object = (union voltage_object *)
3670 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3671 if (voltage_object) {
3672 ATOM_VOLTAGE_FORMULA *formula =
3673 &voltage_object->v1.asFormula;
3674 if (formula->ucFlag & 1)
3675 *voltage_step =
3676 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3677 else
3678 *voltage_step =
3679 le16_to_cpu(formula->usVoltageStep);
3680 return 0;
3681 }
3682 break;
3683 case 2:
3684 return -EINVAL;
3685 default:
3686 DRM_ERROR("unknown voltage object table\n");
3687 return -EINVAL;
3688 }
3689
3690 }
3691 return -EINVAL;
3692}
3693
3694int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3695 u8 voltage_type,
3696 u16 nominal_voltage,
3697 u16 *true_voltage)
3698{
3699 u16 min_voltage, max_voltage, voltage_step;
3700
3701 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3702 return -EINVAL;
3703 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3704 return -EINVAL;
3705 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3706 return -EINVAL;
3707
3708 if (nominal_voltage <= min_voltage)
3709 *true_voltage = min_voltage;
3710 else if (nominal_voltage >= max_voltage)
3711 *true_voltage = max_voltage;
3712 else
3713 *true_voltage = min_voltage +
3714 ((nominal_voltage - min_voltage) / voltage_step) *
3715 voltage_step;
3716
3717 return 0;
3718}
3719
3720int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3721 u8 voltage_type, u8 voltage_mode,
3722 struct atom_voltage_table *voltage_table)
3723{
3724 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3725 u8 frev, crev;
3726 u16 data_offset, size;
3727 int i, ret;
3728 union voltage_object_info *voltage_info;
3729 union voltage_object *voltage_object = NULL;
3730
3731 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3732 &frev, &crev, &data_offset)) {
3733 voltage_info = (union voltage_object_info *)
3734 (rdev->mode_info.atom_context->bios + data_offset);
3735
3736 switch (frev) {
3737 case 1:
3738 case 2:
3739 switch (crev) {
3740 case 1:
3741 DRM_ERROR("old table version %d, %d\n", frev, crev);
3742 return -EINVAL;
3743 case 2:
3744 voltage_object = (union voltage_object *)
3745 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3746 if (voltage_object) {
3747 ATOM_VOLTAGE_FORMULA_V2 *formula =
3748 &voltage_object->v2.asFormula;
3749 VOLTAGE_LUT_ENTRY *lut;
3750 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3751 return -EINVAL;
3752 lut = &formula->asVIDAdjustEntries[0];
3753 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3754 voltage_table->entries[i].value =
3755 le16_to_cpu(lut->usVoltageValue);
3756 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3757 voltage_table->entries[i].value,
3758 voltage_type,
3759 &voltage_table->entries[i].smio_low,
3760 &voltage_table->mask_low);
3761 if (ret)
3762 return ret;
3763 lut = (VOLTAGE_LUT_ENTRY *)
3764 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
3765 }
3766 voltage_table->count = formula->ucNumOfVoltageEntries;
3767 return 0;
3768 }
3769 break;
3770 default:
3771 DRM_ERROR("unknown voltage object table\n");
3772 return -EINVAL;
3773 }
3774 break;
3775 case 3:
3776 switch (crev) {
3777 case 1:
3778 voltage_object = (union voltage_object *)
3779 atom_lookup_voltage_object_v3(&voltage_info->v3,
3780 voltage_type, voltage_mode);
3781 if (voltage_object) {
3782 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3783 &voltage_object->v3.asGpioVoltageObj;
3784 VOLTAGE_LUT_ENTRY_V2 *lut;
3785 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3786 return -EINVAL;
3787 lut = &gpio->asVolGpioLut[0];
3788 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3789 voltage_table->entries[i].value =
3790 le16_to_cpu(lut->usVoltageValue);
3791 voltage_table->entries[i].smio_low =
3792 le32_to_cpu(lut->ulVoltageId);
3793 lut = (VOLTAGE_LUT_ENTRY_V2 *)
3794 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
3795 }
3796 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3797 voltage_table->count = gpio->ucGpioEntryNum;
3798 voltage_table->phase_delay = gpio->ucPhaseDelay;
3799 return 0;
3800 }
3801 break;
3802 default:
3803 DRM_ERROR("unknown voltage object table\n");
3804 return -EINVAL;
3805 }
3806 break;
3807 default:
3808 DRM_ERROR("unknown voltage object table\n");
3809 return -EINVAL;
3810 }
3811 }
3812 return -EINVAL;
3813}
3814
3815union vram_info {
3816 struct _ATOM_VRAM_INFO_V3 v1_3;
3817 struct _ATOM_VRAM_INFO_V4 v1_4;
3818 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3819};
3820
3821int radeon_atom_get_memory_info(struct radeon_device *rdev,
3822 u8 module_index, struct atom_memory_info *mem_info)
3823{
3824 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3825 u8 frev, crev, i;
3826 u16 data_offset, size;
3827 union vram_info *vram_info;
3828
3829 memset(mem_info, 0, sizeof(struct atom_memory_info));
3830
3831 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3832 &frev, &crev, &data_offset)) {
3833 vram_info = (union vram_info *)
3834 (rdev->mode_info.atom_context->bios + data_offset);
3835 switch (frev) {
3836 case 1:
3837 switch (crev) {
3838 case 3:
3839 /* r6xx */
3840 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3841 ATOM_VRAM_MODULE_V3 *vram_module =
3842 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3843
3844 for (i = 0; i < module_index; i++) {
3845 if (le16_to_cpu(vram_module->usSize) == 0)
3846 return -EINVAL;
3847 vram_module = (ATOM_VRAM_MODULE_V3 *)
3848 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3849 }
3850 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3851 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3852 } else
3853 return -EINVAL;
3854 break;
3855 case 4:
3856 /* r7xx, evergreen */
3857 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3858 ATOM_VRAM_MODULE_V4 *vram_module =
3859 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3860
3861 for (i = 0; i < module_index; i++) {
3862 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3863 return -EINVAL;
3864 vram_module = (ATOM_VRAM_MODULE_V4 *)
3865 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3866 }
3867 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3868 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3869 } else
3870 return -EINVAL;
3871 break;
3872 default:
3873 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3874 return -EINVAL;
3875 }
3876 break;
3877 case 2:
3878 switch (crev) {
3879 case 1:
3880 /* ni */
3881 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3882 ATOM_VRAM_MODULE_V7 *vram_module =
3883 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3884
3885 for (i = 0; i < module_index; i++) {
3886 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3887 return -EINVAL;
3888 vram_module = (ATOM_VRAM_MODULE_V7 *)
3889 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3890 }
3891 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3892 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3893 } else
3894 return -EINVAL;
3895 break;
3896 default:
3897 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3898 return -EINVAL;
3899 }
3900 break;
3901 default:
3902 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3903 return -EINVAL;
3904 }
3905 return 0;
3906 }
3907 return -EINVAL;
3908}
3909
3910int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3911 bool gddr5, u8 module_index,
3912 struct atom_memory_clock_range_table *mclk_range_table)
3913{
3914 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3915 u8 frev, crev, i;
3916 u16 data_offset, size;
3917 union vram_info *vram_info;
3918 u32 mem_timing_size = gddr5 ?
3919 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3920
3921 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3922
3923 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3924 &frev, &crev, &data_offset)) {
3925 vram_info = (union vram_info *)
3926 (rdev->mode_info.atom_context->bios + data_offset);
3927 switch (frev) {
3928 case 1:
3929 switch (crev) {
3930 case 3:
3931 DRM_ERROR("old table version %d, %d\n", frev, crev);
3932 return -EINVAL;
3933 case 4:
3934 /* r7xx, evergreen */
3935 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3936 ATOM_VRAM_MODULE_V4 *vram_module =
3937 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3938 ATOM_MEMORY_TIMING_FORMAT *format;
3939
3940 for (i = 0; i < module_index; i++) {
3941 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3942 return -EINVAL;
3943 vram_module = (ATOM_VRAM_MODULE_V4 *)
3944 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3945 }
3946 mclk_range_table->num_entries = (u8)
3947 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3948 mem_timing_size);
3949 format = &vram_module->asMemTiming[0];
3950 for (i = 0; i < mclk_range_table->num_entries; i++) {
3951 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3952 format = (ATOM_MEMORY_TIMING_FORMAT *)
3953 ((u8 *)format + mem_timing_size);
3954 }
3955 } else
3956 return -EINVAL;
3957 break;
3958 default:
3959 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3960 return -EINVAL;
3961 }
3962 break;
3963 case 2:
3964 DRM_ERROR("new table version %d, %d\n", frev, crev);
3965 return -EINVAL;
3966 default:
3967 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3968 return -EINVAL;
3969 }
3970 return 0;
3971 }
3972 return -EINVAL;
3973}
3974
3975#define MEM_ID_MASK 0xff000000
3976#define MEM_ID_SHIFT 24
3977#define CLOCK_RANGE_MASK 0x00ffffff
3978#define CLOCK_RANGE_SHIFT 0
3979#define LOW_NIBBLE_MASK 0xf
3980#define DATA_EQU_PREV 0
3981#define DATA_FROM_TABLE 4
3982
3983int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3984 u8 module_index,
3985 struct atom_mc_reg_table *reg_table)
3986{
3987 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3988 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3989 u32 i = 0, j;
3990 u16 data_offset, size;
3991 union vram_info *vram_info;
3992
3993 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
3994
3995 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3996 &frev, &crev, &data_offset)) {
3997 vram_info = (union vram_info *)
3998 (rdev->mode_info.atom_context->bios + data_offset);
3999 switch (frev) {
4000 case 1:
4001 DRM_ERROR("old table version %d, %d\n", frev, crev);
4002 return -EINVAL;
4003 case 2:
4004 switch (crev) {
4005 case 1:
4006 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
4007 ATOM_INIT_REG_BLOCK *reg_block =
4008 (ATOM_INIT_REG_BLOCK *)
4009 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
4010 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
4011 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4012 ((u8 *)reg_block + (2 * sizeof(u16)) +
4013 le16_to_cpu(reg_block->usRegIndexTblSize));
4014 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
4015 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
4016 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
4017 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
4018 return -EINVAL;
4019 while (i < num_entries) {
4020 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
4021 break;
4022 reg_table->mc_reg_address[i].s1 =
4023 (u16)(le16_to_cpu(format->usRegIndex));
4024 reg_table->mc_reg_address[i].pre_reg_data =
4025 (u8)(format->ucPreRegDataLength);
4026 i++;
4027 format = (ATOM_INIT_REG_INDEX_FORMAT *)
4028 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
4029 }
4030 reg_table->last = i;
4031 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
4032 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
4033 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
4034 >> MEM_ID_SHIFT);
4035 if (module_index == t_mem_id) {
4036 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
4037 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
4038 >> CLOCK_RANGE_SHIFT);
4039 for (i = 0, j = 1; i < reg_table->last; i++) {
4040 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
4041 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4042 (u32)le32_to_cpu(*((u32 *)reg_data + j));
4043 j++;
4044 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
4045 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4046 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
4047 }
4048 }
4049 num_ranges++;
4050 }
4051 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4052 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
4053 }
4054 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
4055 return -EINVAL;
4056 reg_table->num_entries = num_ranges;
4057 } else
4058 return -EINVAL;
4059 break;
4060 default:
4061 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4062 return -EINVAL;
4063 }
4064 break;
4065 default:
4066 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4067 return -EINVAL;
4068 }
4069 return 0;
4070 }
4071 return -EINVAL;
4072}
4073
4074void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
4075{
4076 struct radeon_device *rdev = dev->dev_private;
4077 uint32_t bios_2_scratch, bios_6_scratch;
4078
4079 if (rdev->family >= CHIP_R600) {
4080 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4081 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4082 } else {
4083 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4084 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4085 }
4086
4087 /* let the bios control the backlight */
4088 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
4089
4090 /* tell the bios not to handle mode switching */
4091 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
4092
4093 /* clear the vbios dpms state */
4094 if (ASIC_IS_DCE4(rdev))
4095 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
4096
4097 if (rdev->family >= CHIP_R600) {
4098 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4099 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4100 } else {
4101 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4102 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4103 }
4104
4105}
4106
4107void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
4108{
4109 uint32_t scratch_reg;
4110 int i;
4111
4112 if (rdev->family >= CHIP_R600)
4113 scratch_reg = R600_BIOS_0_SCRATCH;
4114 else
4115 scratch_reg = RADEON_BIOS_0_SCRATCH;
4116
4117 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4118 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
4119}
4120
4121void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
4122{
4123 uint32_t scratch_reg;
4124 int i;
4125
4126 if (rdev->family >= CHIP_R600)
4127 scratch_reg = R600_BIOS_0_SCRATCH;
4128 else
4129 scratch_reg = RADEON_BIOS_0_SCRATCH;
4130
4131 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4132 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
4133}
4134
4135void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
4136{
4137 struct drm_device *dev = encoder->dev;
4138 struct radeon_device *rdev = dev->dev_private;
4139 uint32_t bios_6_scratch;
4140
4141 if (rdev->family >= CHIP_R600)
4142 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4143 else
4144 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4145
4146 if (lock) {
4147 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
4148 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
4149 } else {
4150 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
4151 bios_6_scratch |= ATOM_S6_ACC_MODE;
4152 }
4153
4154 if (rdev->family >= CHIP_R600)
4155 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4156 else
4157 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4158}
4159
4160/* at some point we may want to break this out into individual functions */
4161void
4162radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
4163 struct drm_encoder *encoder,
4164 bool connected)
4165{
4166 struct drm_device *dev = connector->dev;
4167 struct radeon_device *rdev = dev->dev_private;
4168 struct radeon_connector *radeon_connector =
4169 to_radeon_connector(connector);
4170 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4171 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
4172
4173 if (rdev->family >= CHIP_R600) {
4174 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
4175 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4176 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4177 } else {
4178 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
4179 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4180 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4181 }
4182
4183 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
4184 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
4185 if (connected) {
4186 DRM_DEBUG_KMS("TV1 connected\n");
4187 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
4188 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
4189 } else {
4190 DRM_DEBUG_KMS("TV1 disconnected\n");
4191 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
4192 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
4193 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
4194 }
4195 }
4196 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
4197 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
4198 if (connected) {
4199 DRM_DEBUG_KMS("CV connected\n");
4200 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
4201 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
4202 } else {
4203 DRM_DEBUG_KMS("CV disconnected\n");
4204 bios_0_scratch &= ~ATOM_S0_CV_MASK;
4205 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
4206 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
4207 }
4208 }
4209 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
4210 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
4211 if (connected) {
4212 DRM_DEBUG_KMS("LCD1 connected\n");
4213 bios_0_scratch |= ATOM_S0_LCD1;
4214 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
4215 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
4216 } else {
4217 DRM_DEBUG_KMS("LCD1 disconnected\n");
4218 bios_0_scratch &= ~ATOM_S0_LCD1;
4219 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
4220 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
4221 }
4222 }
4223 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
4224 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
4225 if (connected) {
4226 DRM_DEBUG_KMS("CRT1 connected\n");
4227 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
4228 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
4229 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
4230 } else {
4231 DRM_DEBUG_KMS("CRT1 disconnected\n");
4232 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
4233 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
4234 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
4235 }
4236 }
4237 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
4238 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
4239 if (connected) {
4240 DRM_DEBUG_KMS("CRT2 connected\n");
4241 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
4242 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
4243 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
4244 } else {
4245 DRM_DEBUG_KMS("CRT2 disconnected\n");
4246 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
4247 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
4248 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
4249 }
4250 }
4251 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
4252 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
4253 if (connected) {
4254 DRM_DEBUG_KMS("DFP1 connected\n");
4255 bios_0_scratch |= ATOM_S0_DFP1;
4256 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
4257 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
4258 } else {
4259 DRM_DEBUG_KMS("DFP1 disconnected\n");
4260 bios_0_scratch &= ~ATOM_S0_DFP1;
4261 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
4262 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
4263 }
4264 }
4265 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
4266 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
4267 if (connected) {
4268 DRM_DEBUG_KMS("DFP2 connected\n");
4269 bios_0_scratch |= ATOM_S0_DFP2;
4270 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
4271 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
4272 } else {
4273 DRM_DEBUG_KMS("DFP2 disconnected\n");
4274 bios_0_scratch &= ~ATOM_S0_DFP2;
4275 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
4276 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
4277 }
4278 }
4279 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
4280 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
4281 if (connected) {
4282 DRM_DEBUG_KMS("DFP3 connected\n");
4283 bios_0_scratch |= ATOM_S0_DFP3;
4284 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
4285 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
4286 } else {
4287 DRM_DEBUG_KMS("DFP3 disconnected\n");
4288 bios_0_scratch &= ~ATOM_S0_DFP3;
4289 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
4290 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
4291 }
4292 }
4293 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
4294 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
4295 if (connected) {
4296 DRM_DEBUG_KMS("DFP4 connected\n");
4297 bios_0_scratch |= ATOM_S0_DFP4;
4298 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
4299 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
4300 } else {
4301 DRM_DEBUG_KMS("DFP4 disconnected\n");
4302 bios_0_scratch &= ~ATOM_S0_DFP4;
4303 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
4304 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
4305 }
4306 }
4307 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
4308 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
4309 if (connected) {
4310 DRM_DEBUG_KMS("DFP5 connected\n");
4311 bios_0_scratch |= ATOM_S0_DFP5;
4312 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
4313 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
4314 } else {
4315 DRM_DEBUG_KMS("DFP5 disconnected\n");
4316 bios_0_scratch &= ~ATOM_S0_DFP5;
4317 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
4318 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
4319 }
4320 }
4321 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4322 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4323 if (connected) {
4324 DRM_DEBUG_KMS("DFP6 connected\n");
4325 bios_0_scratch |= ATOM_S0_DFP6;
4326 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4327 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4328 } else {
4329 DRM_DEBUG_KMS("DFP6 disconnected\n");
4330 bios_0_scratch &= ~ATOM_S0_DFP6;
4331 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4332 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4333 }
4334 }
4335
4336 if (rdev->family >= CHIP_R600) {
4337 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4338 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4339 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4340 } else {
4341 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4342 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4343 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4344 }
4345}
4346
4347void
4348radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4349{
4350 struct drm_device *dev = encoder->dev;
4351 struct radeon_device *rdev = dev->dev_private;
4352 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4353 uint32_t bios_3_scratch;
4354
4355 if (ASIC_IS_DCE4(rdev))
4356 return;
4357
4358 if (rdev->family >= CHIP_R600)
4359 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4360 else
4361 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4362
4363 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4364 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4365 bios_3_scratch |= (crtc << 18);
4366 }
4367 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4368 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4369 bios_3_scratch |= (crtc << 24);
4370 }
4371 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4372 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4373 bios_3_scratch |= (crtc << 16);
4374 }
4375 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4376 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4377 bios_3_scratch |= (crtc << 20);
4378 }
4379 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4380 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4381 bios_3_scratch |= (crtc << 17);
4382 }
4383 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4384 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4385 bios_3_scratch |= (crtc << 19);
4386 }
4387 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4388 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4389 bios_3_scratch |= (crtc << 23);
4390 }
4391 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4392 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4393 bios_3_scratch |= (crtc << 25);
4394 }
4395
4396 if (rdev->family >= CHIP_R600)
4397 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4398 else
4399 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4400}
4401
4402void
4403radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4404{
4405 struct drm_device *dev = encoder->dev;
4406 struct radeon_device *rdev = dev->dev_private;
4407 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4408 uint32_t bios_2_scratch;
4409
4410 if (ASIC_IS_DCE4(rdev))
4411 return;
4412
4413 if (rdev->family >= CHIP_R600)
4414 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4415 else
4416 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4417
4418 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4419 if (on)
4420 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4421 else
4422 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4423 }
4424 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4425 if (on)
4426 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4427 else
4428 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4429 }
4430 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4431 if (on)
4432 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4433 else
4434 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4435 }
4436 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4437 if (on)
4438 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4439 else
4440 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4441 }
4442 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4443 if (on)
4444 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4445 else
4446 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4447 }
4448 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4449 if (on)
4450 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4451 else
4452 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4453 }
4454 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4455 if (on)
4456 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4457 else
4458 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4459 }
4460 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4461 if (on)
4462 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4463 else
4464 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4465 }
4466 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4467 if (on)
4468 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4469 else
4470 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4471 }
4472 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4473 if (on)
4474 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4475 else
4476 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4477 }
4478
4479 if (rdev->family >= CHIP_R600)
4480 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4481 else
4482 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4483}
1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/radeon_drm.h>
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32#include "radeon_asic.h"
33
34extern void
35radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
36 uint32_t supported_device, u16 caps);
37
38/* from radeon_legacy_encoder.c */
39extern void
40radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
41 uint32_t supported_device);
42
43union atom_supported_devices {
44 struct _ATOM_SUPPORTED_DEVICES_INFO info;
45 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
46 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
47};
48
49static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
50 ATOM_GPIO_I2C_ASSIGMENT *gpio,
51 u8 index)
52{
53 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
54 if ((rdev->family == CHIP_R420) ||
55 (rdev->family == CHIP_R423) ||
56 (rdev->family == CHIP_RV410)) {
57 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
58 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
59 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
60 gpio->ucClkMaskShift = 0x19;
61 gpio->ucDataMaskShift = 0x18;
62 }
63 }
64
65 /* some evergreen boards have bad data for this entry */
66 if (ASIC_IS_DCE4(rdev)) {
67 if ((index == 7) &&
68 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
69 (gpio->sucI2cId.ucAccess == 0)) {
70 gpio->sucI2cId.ucAccess = 0x97;
71 gpio->ucDataMaskShift = 8;
72 gpio->ucDataEnShift = 8;
73 gpio->ucDataY_Shift = 8;
74 gpio->ucDataA_Shift = 8;
75 }
76 }
77
78 /* some DCE3 boards have bad data for this entry */
79 if (ASIC_IS_DCE3(rdev)) {
80 if ((index == 4) &&
81 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
82 (gpio->sucI2cId.ucAccess == 0x94))
83 gpio->sucI2cId.ucAccess = 0x14;
84 }
85}
86
87static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
88{
89 struct radeon_i2c_bus_rec i2c;
90
91 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
92
93 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
94 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
95 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
96 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
97 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
98 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
99 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
100 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
101 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
102 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
103 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
104 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
105 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
106 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
107 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
108 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
109
110 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
111 i2c.hw_capable = true;
112 else
113 i2c.hw_capable = false;
114
115 if (gpio->sucI2cId.ucAccess == 0xa0)
116 i2c.mm_i2c = true;
117 else
118 i2c.mm_i2c = false;
119
120 i2c.i2c_id = gpio->sucI2cId.ucAccess;
121
122 if (i2c.mask_clk_reg)
123 i2c.valid = true;
124 else
125 i2c.valid = false;
126
127 return i2c;
128}
129
130static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
131 uint8_t id)
132{
133 struct atom_context *ctx = rdev->mode_info.atom_context;
134 ATOM_GPIO_I2C_ASSIGMENT *gpio;
135 struct radeon_i2c_bus_rec i2c;
136 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
137 struct _ATOM_GPIO_I2C_INFO *i2c_info;
138 uint16_t data_offset, size;
139 int i, num_indices;
140
141 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
142 i2c.valid = false;
143
144 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
145 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
146
147 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
148 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
149
150 gpio = &i2c_info->asGPIO_Info[0];
151 for (i = 0; i < num_indices; i++) {
152
153 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
154
155 if (gpio->sucI2cId.ucAccess == id) {
156 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
157 break;
158 }
159 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
160 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
161 }
162 }
163
164 return i2c;
165}
166
167void radeon_atombios_i2c_init(struct radeon_device *rdev)
168{
169 struct atom_context *ctx = rdev->mode_info.atom_context;
170 ATOM_GPIO_I2C_ASSIGMENT *gpio;
171 struct radeon_i2c_bus_rec i2c;
172 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
173 struct _ATOM_GPIO_I2C_INFO *i2c_info;
174 uint16_t data_offset, size;
175 int i, num_indices;
176 char stmp[32];
177
178 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
179 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
180
181 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
182 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
183
184 gpio = &i2c_info->asGPIO_Info[0];
185 for (i = 0; i < num_indices; i++) {
186 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
187
188 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
189
190 if (i2c.valid) {
191 sprintf(stmp, "0x%x", i2c.i2c_id);
192 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
193 }
194 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
195 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
196 }
197 }
198}
199
200struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
201 u8 id)
202{
203 struct atom_context *ctx = rdev->mode_info.atom_context;
204 struct radeon_gpio_rec gpio;
205 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
206 struct _ATOM_GPIO_PIN_LUT *gpio_info;
207 ATOM_GPIO_PIN_ASSIGNMENT *pin;
208 u16 data_offset, size;
209 int i, num_indices;
210
211 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
212 gpio.valid = false;
213
214 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
215 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
216
217 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
218 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
219
220 pin = gpio_info->asGPIO_Pin;
221 for (i = 0; i < num_indices; i++) {
222 if (id == pin->ucGPIO_ID) {
223 gpio.id = pin->ucGPIO_ID;
224 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
225 gpio.shift = pin->ucGpioPinBitShift;
226 gpio.mask = (1 << pin->ucGpioPinBitShift);
227 gpio.valid = true;
228 break;
229 }
230 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
231 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
232 }
233 }
234
235 return gpio;
236}
237
238static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
239 struct radeon_gpio_rec *gpio)
240{
241 struct radeon_hpd hpd;
242 u32 reg;
243
244 memset(&hpd, 0, sizeof(struct radeon_hpd));
245
246 if (ASIC_IS_DCE6(rdev))
247 reg = SI_DC_GPIO_HPD_A;
248 else if (ASIC_IS_DCE4(rdev))
249 reg = EVERGREEN_DC_GPIO_HPD_A;
250 else
251 reg = AVIVO_DC_GPIO_HPD_A;
252
253 hpd.gpio = *gpio;
254 if (gpio->reg == reg) {
255 switch(gpio->mask) {
256 case (1 << 0):
257 hpd.hpd = RADEON_HPD_1;
258 break;
259 case (1 << 8):
260 hpd.hpd = RADEON_HPD_2;
261 break;
262 case (1 << 16):
263 hpd.hpd = RADEON_HPD_3;
264 break;
265 case (1 << 24):
266 hpd.hpd = RADEON_HPD_4;
267 break;
268 case (1 << 26):
269 hpd.hpd = RADEON_HPD_5;
270 break;
271 case (1 << 28):
272 hpd.hpd = RADEON_HPD_6;
273 break;
274 default:
275 hpd.hpd = RADEON_HPD_NONE;
276 break;
277 }
278 } else
279 hpd.hpd = RADEON_HPD_NONE;
280 return hpd;
281}
282
283static bool radeon_atom_apply_quirks(struct drm_device *dev,
284 uint32_t supported_device,
285 int *connector_type,
286 struct radeon_i2c_bus_rec *i2c_bus,
287 uint16_t *line_mux,
288 struct radeon_hpd *hpd)
289{
290
291 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
292 if ((dev->pdev->device == 0x791e) &&
293 (dev->pdev->subsystem_vendor == 0x1043) &&
294 (dev->pdev->subsystem_device == 0x826d)) {
295 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
296 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
297 *connector_type = DRM_MODE_CONNECTOR_DVID;
298 }
299
300 /* Asrock RS600 board lists the DVI port as HDMI */
301 if ((dev->pdev->device == 0x7941) &&
302 (dev->pdev->subsystem_vendor == 0x1849) &&
303 (dev->pdev->subsystem_device == 0x7941)) {
304 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
305 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
306 *connector_type = DRM_MODE_CONNECTOR_DVID;
307 }
308
309 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
310 if ((dev->pdev->device == 0x796e) &&
311 (dev->pdev->subsystem_vendor == 0x1462) &&
312 (dev->pdev->subsystem_device == 0x7302)) {
313 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
314 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
315 return false;
316 }
317
318 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
319 if ((dev->pdev->device == 0x7941) &&
320 (dev->pdev->subsystem_vendor == 0x147b) &&
321 (dev->pdev->subsystem_device == 0x2412)) {
322 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
323 return false;
324 }
325
326 /* Falcon NW laptop lists vga ddc line for LVDS */
327 if ((dev->pdev->device == 0x5653) &&
328 (dev->pdev->subsystem_vendor == 0x1462) &&
329 (dev->pdev->subsystem_device == 0x0291)) {
330 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
331 i2c_bus->valid = false;
332 *line_mux = 53;
333 }
334 }
335
336 /* HIS X1300 is DVI+VGA, not DVI+DVI */
337 if ((dev->pdev->device == 0x7146) &&
338 (dev->pdev->subsystem_vendor == 0x17af) &&
339 (dev->pdev->subsystem_device == 0x2058)) {
340 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
341 return false;
342 }
343
344 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
345 if ((dev->pdev->device == 0x7142) &&
346 (dev->pdev->subsystem_vendor == 0x1458) &&
347 (dev->pdev->subsystem_device == 0x2134)) {
348 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
349 return false;
350 }
351
352
353 /* Funky macbooks */
354 if ((dev->pdev->device == 0x71C5) &&
355 (dev->pdev->subsystem_vendor == 0x106b) &&
356 (dev->pdev->subsystem_device == 0x0080)) {
357 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
358 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
359 return false;
360 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
361 *line_mux = 0x90;
362 }
363
364 /* mac rv630, rv730, others */
365 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
366 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
367 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
368 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
369 }
370
371 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
372 if ((dev->pdev->device == 0x9598) &&
373 (dev->pdev->subsystem_vendor == 0x1043) &&
374 (dev->pdev->subsystem_device == 0x01da)) {
375 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
376 *connector_type = DRM_MODE_CONNECTOR_DVII;
377 }
378 }
379
380 /* ASUS HD 3600 board lists the DVI port as HDMI */
381 if ((dev->pdev->device == 0x9598) &&
382 (dev->pdev->subsystem_vendor == 0x1043) &&
383 (dev->pdev->subsystem_device == 0x01e4)) {
384 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
385 *connector_type = DRM_MODE_CONNECTOR_DVII;
386 }
387 }
388
389 /* ASUS HD 3450 board lists the DVI port as HDMI */
390 if ((dev->pdev->device == 0x95C5) &&
391 (dev->pdev->subsystem_vendor == 0x1043) &&
392 (dev->pdev->subsystem_device == 0x01e2)) {
393 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
394 *connector_type = DRM_MODE_CONNECTOR_DVII;
395 }
396 }
397
398 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
399 * HDMI + VGA reporting as HDMI
400 */
401 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
402 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
403 *connector_type = DRM_MODE_CONNECTOR_VGA;
404 *line_mux = 0;
405 }
406 }
407
408 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
409 * on the laptop and a DVI port on the docking station and
410 * both share the same encoder, hpd pin, and ddc line.
411 * So while the bios table is technically correct,
412 * we drop the DVI port here since xrandr has no concept of
413 * encoders and will try and drive both connectors
414 * with different crtcs which isn't possible on the hardware
415 * side and leaves no crtcs for LVDS or VGA.
416 */
417 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
418 (dev->pdev->subsystem_vendor == 0x1025) &&
419 (dev->pdev->subsystem_device == 0x013c)) {
420 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
421 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
422 /* actually it's a DVI-D port not DVI-I */
423 *connector_type = DRM_MODE_CONNECTOR_DVID;
424 return false;
425 }
426 }
427
428 /* XFX Pine Group device rv730 reports no VGA DDC lines
429 * even though they are wired up to record 0x93
430 */
431 if ((dev->pdev->device == 0x9498) &&
432 (dev->pdev->subsystem_vendor == 0x1682) &&
433 (dev->pdev->subsystem_device == 0x2452) &&
434 (i2c_bus->valid == false) &&
435 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
436 struct radeon_device *rdev = dev->dev_private;
437 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
438 }
439
440 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
441 if (((dev->pdev->device == 0x9802) ||
442 (dev->pdev->device == 0x9805) ||
443 (dev->pdev->device == 0x9806)) &&
444 (dev->pdev->subsystem_vendor == 0x1734) &&
445 (dev->pdev->subsystem_device == 0x11bd)) {
446 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
447 *connector_type = DRM_MODE_CONNECTOR_DVII;
448 *line_mux = 0x3103;
449 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
450 *connector_type = DRM_MODE_CONNECTOR_DVII;
451 }
452 }
453
454 return true;
455}
456
457static const int supported_devices_connector_convert[] = {
458 DRM_MODE_CONNECTOR_Unknown,
459 DRM_MODE_CONNECTOR_VGA,
460 DRM_MODE_CONNECTOR_DVII,
461 DRM_MODE_CONNECTOR_DVID,
462 DRM_MODE_CONNECTOR_DVIA,
463 DRM_MODE_CONNECTOR_SVIDEO,
464 DRM_MODE_CONNECTOR_Composite,
465 DRM_MODE_CONNECTOR_LVDS,
466 DRM_MODE_CONNECTOR_Unknown,
467 DRM_MODE_CONNECTOR_Unknown,
468 DRM_MODE_CONNECTOR_HDMIA,
469 DRM_MODE_CONNECTOR_HDMIB,
470 DRM_MODE_CONNECTOR_Unknown,
471 DRM_MODE_CONNECTOR_Unknown,
472 DRM_MODE_CONNECTOR_9PinDIN,
473 DRM_MODE_CONNECTOR_DisplayPort
474};
475
476static const uint16_t supported_devices_connector_object_id_convert[] = {
477 CONNECTOR_OBJECT_ID_NONE,
478 CONNECTOR_OBJECT_ID_VGA,
479 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
480 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
481 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
482 CONNECTOR_OBJECT_ID_COMPOSITE,
483 CONNECTOR_OBJECT_ID_SVIDEO,
484 CONNECTOR_OBJECT_ID_LVDS,
485 CONNECTOR_OBJECT_ID_9PIN_DIN,
486 CONNECTOR_OBJECT_ID_9PIN_DIN,
487 CONNECTOR_OBJECT_ID_DISPLAYPORT,
488 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
489 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
490 CONNECTOR_OBJECT_ID_SVIDEO
491};
492
493static const int object_connector_convert[] = {
494 DRM_MODE_CONNECTOR_Unknown,
495 DRM_MODE_CONNECTOR_DVII,
496 DRM_MODE_CONNECTOR_DVII,
497 DRM_MODE_CONNECTOR_DVID,
498 DRM_MODE_CONNECTOR_DVID,
499 DRM_MODE_CONNECTOR_VGA,
500 DRM_MODE_CONNECTOR_Composite,
501 DRM_MODE_CONNECTOR_SVIDEO,
502 DRM_MODE_CONNECTOR_Unknown,
503 DRM_MODE_CONNECTOR_Unknown,
504 DRM_MODE_CONNECTOR_9PinDIN,
505 DRM_MODE_CONNECTOR_Unknown,
506 DRM_MODE_CONNECTOR_HDMIA,
507 DRM_MODE_CONNECTOR_HDMIB,
508 DRM_MODE_CONNECTOR_LVDS,
509 DRM_MODE_CONNECTOR_9PinDIN,
510 DRM_MODE_CONNECTOR_Unknown,
511 DRM_MODE_CONNECTOR_Unknown,
512 DRM_MODE_CONNECTOR_Unknown,
513 DRM_MODE_CONNECTOR_DisplayPort,
514 DRM_MODE_CONNECTOR_eDP,
515 DRM_MODE_CONNECTOR_Unknown
516};
517
518bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
519{
520 struct radeon_device *rdev = dev->dev_private;
521 struct radeon_mode_info *mode_info = &rdev->mode_info;
522 struct atom_context *ctx = mode_info->atom_context;
523 int index = GetIndexIntoMasterTable(DATA, Object_Header);
524 u16 size, data_offset;
525 u8 frev, crev;
526 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
527 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
528 ATOM_OBJECT_TABLE *router_obj;
529 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
530 ATOM_OBJECT_HEADER *obj_header;
531 int i, j, k, path_size, device_support;
532 int connector_type;
533 u16 igp_lane_info, conn_id, connector_object_id;
534 struct radeon_i2c_bus_rec ddc_bus;
535 struct radeon_router router;
536 struct radeon_gpio_rec gpio;
537 struct radeon_hpd hpd;
538
539 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
540 return false;
541
542 if (crev < 2)
543 return false;
544
545 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
546 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
547 (ctx->bios + data_offset +
548 le16_to_cpu(obj_header->usDisplayPathTableOffset));
549 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
550 (ctx->bios + data_offset +
551 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
552 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
553 (ctx->bios + data_offset +
554 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
555 router_obj = (ATOM_OBJECT_TABLE *)
556 (ctx->bios + data_offset +
557 le16_to_cpu(obj_header->usRouterObjectTableOffset));
558 device_support = le16_to_cpu(obj_header->usDeviceSupport);
559
560 path_size = 0;
561 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
562 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
563 ATOM_DISPLAY_OBJECT_PATH *path;
564 addr += path_size;
565 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
566 path_size += le16_to_cpu(path->usSize);
567
568 if (device_support & le16_to_cpu(path->usDeviceTag)) {
569 uint8_t con_obj_id, con_obj_num, con_obj_type;
570
571 con_obj_id =
572 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
573 >> OBJECT_ID_SHIFT;
574 con_obj_num =
575 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
576 >> ENUM_ID_SHIFT;
577 con_obj_type =
578 (le16_to_cpu(path->usConnObjectId) &
579 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
580
581 /* TODO CV support */
582 if (le16_to_cpu(path->usDeviceTag) ==
583 ATOM_DEVICE_CV_SUPPORT)
584 continue;
585
586 /* IGP chips */
587 if ((rdev->flags & RADEON_IS_IGP) &&
588 (con_obj_id ==
589 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
590 uint16_t igp_offset = 0;
591 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
592
593 index =
594 GetIndexIntoMasterTable(DATA,
595 IntegratedSystemInfo);
596
597 if (atom_parse_data_header(ctx, index, &size, &frev,
598 &crev, &igp_offset)) {
599
600 if (crev >= 2) {
601 igp_obj =
602 (ATOM_INTEGRATED_SYSTEM_INFO_V2
603 *) (ctx->bios + igp_offset);
604
605 if (igp_obj) {
606 uint32_t slot_config, ct;
607
608 if (con_obj_num == 1)
609 slot_config =
610 igp_obj->
611 ulDDISlot1Config;
612 else
613 slot_config =
614 igp_obj->
615 ulDDISlot2Config;
616
617 ct = (slot_config >> 16) & 0xff;
618 connector_type =
619 object_connector_convert
620 [ct];
621 connector_object_id = ct;
622 igp_lane_info =
623 slot_config & 0xffff;
624 } else
625 continue;
626 } else
627 continue;
628 } else {
629 igp_lane_info = 0;
630 connector_type =
631 object_connector_convert[con_obj_id];
632 connector_object_id = con_obj_id;
633 }
634 } else {
635 igp_lane_info = 0;
636 connector_type =
637 object_connector_convert[con_obj_id];
638 connector_object_id = con_obj_id;
639 }
640
641 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
642 continue;
643
644 router.ddc_valid = false;
645 router.cd_valid = false;
646 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
647 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
648
649 grph_obj_id =
650 (le16_to_cpu(path->usGraphicObjIds[j]) &
651 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
652 grph_obj_num =
653 (le16_to_cpu(path->usGraphicObjIds[j]) &
654 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
655 grph_obj_type =
656 (le16_to_cpu(path->usGraphicObjIds[j]) &
657 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
658
659 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
660 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
661 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
662 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
663 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
664 (ctx->bios + data_offset +
665 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
666 ATOM_ENCODER_CAP_RECORD *cap_record;
667 u16 caps = 0;
668
669 while (record->ucRecordSize > 0 &&
670 record->ucRecordType > 0 &&
671 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
672 switch (record->ucRecordType) {
673 case ATOM_ENCODER_CAP_RECORD_TYPE:
674 cap_record =(ATOM_ENCODER_CAP_RECORD *)
675 record;
676 caps = le16_to_cpu(cap_record->usEncoderCap);
677 break;
678 }
679 record = (ATOM_COMMON_RECORD_HEADER *)
680 ((char *)record + record->ucRecordSize);
681 }
682 radeon_add_atom_encoder(dev,
683 encoder_obj,
684 le16_to_cpu
685 (path->
686 usDeviceTag),
687 caps);
688 }
689 }
690 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
691 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
692 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
693 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
694 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
695 (ctx->bios + data_offset +
696 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
697 ATOM_I2C_RECORD *i2c_record;
698 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
699 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
700 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
701 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
702 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
703 (ctx->bios + data_offset +
704 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
705 u8 *num_dst_objs = (u8 *)
706 ((u8 *)router_src_dst_table + 1 +
707 (router_src_dst_table->ucNumberOfSrc * 2));
708 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
709 int enum_id;
710
711 router.router_id = router_obj_id;
712 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
713 if (le16_to_cpu(path->usConnObjectId) ==
714 le16_to_cpu(dst_objs[enum_id]))
715 break;
716 }
717
718 while (record->ucRecordSize > 0 &&
719 record->ucRecordType > 0 &&
720 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
721 switch (record->ucRecordType) {
722 case ATOM_I2C_RECORD_TYPE:
723 i2c_record =
724 (ATOM_I2C_RECORD *)
725 record;
726 i2c_config =
727 (ATOM_I2C_ID_CONFIG_ACCESS *)
728 &i2c_record->sucI2cId;
729 router.i2c_info =
730 radeon_lookup_i2c_gpio(rdev,
731 i2c_config->
732 ucAccess);
733 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
734 break;
735 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
736 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
737 record;
738 router.ddc_valid = true;
739 router.ddc_mux_type = ddc_path->ucMuxType;
740 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
741 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
742 break;
743 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
744 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
745 record;
746 router.cd_valid = true;
747 router.cd_mux_type = cd_path->ucMuxType;
748 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
749 router.cd_mux_state = cd_path->ucMuxState[enum_id];
750 break;
751 }
752 record = (ATOM_COMMON_RECORD_HEADER *)
753 ((char *)record + record->ucRecordSize);
754 }
755 }
756 }
757 }
758 }
759
760 /* look up gpio for ddc, hpd */
761 ddc_bus.valid = false;
762 hpd.hpd = RADEON_HPD_NONE;
763 if ((le16_to_cpu(path->usDeviceTag) &
764 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
765 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
766 if (le16_to_cpu(path->usConnObjectId) ==
767 le16_to_cpu(con_obj->asObjects[j].
768 usObjectID)) {
769 ATOM_COMMON_RECORD_HEADER
770 *record =
771 (ATOM_COMMON_RECORD_HEADER
772 *)
773 (ctx->bios + data_offset +
774 le16_to_cpu(con_obj->
775 asObjects[j].
776 usRecordOffset));
777 ATOM_I2C_RECORD *i2c_record;
778 ATOM_HPD_INT_RECORD *hpd_record;
779 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
780
781 while (record->ucRecordSize > 0 &&
782 record->ucRecordType > 0 &&
783 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
784 switch (record->ucRecordType) {
785 case ATOM_I2C_RECORD_TYPE:
786 i2c_record =
787 (ATOM_I2C_RECORD *)
788 record;
789 i2c_config =
790 (ATOM_I2C_ID_CONFIG_ACCESS *)
791 &i2c_record->sucI2cId;
792 ddc_bus = radeon_lookup_i2c_gpio(rdev,
793 i2c_config->
794 ucAccess);
795 break;
796 case ATOM_HPD_INT_RECORD_TYPE:
797 hpd_record =
798 (ATOM_HPD_INT_RECORD *)
799 record;
800 gpio = radeon_atombios_lookup_gpio(rdev,
801 hpd_record->ucHPDIntGPIOID);
802 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
803 hpd.plugged_state = hpd_record->ucPlugged_PinState;
804 break;
805 }
806 record =
807 (ATOM_COMMON_RECORD_HEADER
808 *) ((char *)record
809 +
810 record->
811 ucRecordSize);
812 }
813 break;
814 }
815 }
816 }
817
818 /* needed for aux chan transactions */
819 ddc_bus.hpd = hpd.hpd;
820
821 conn_id = le16_to_cpu(path->usConnObjectId);
822
823 if (!radeon_atom_apply_quirks
824 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
825 &ddc_bus, &conn_id, &hpd))
826 continue;
827
828 radeon_add_atom_connector(dev,
829 conn_id,
830 le16_to_cpu(path->
831 usDeviceTag),
832 connector_type, &ddc_bus,
833 igp_lane_info,
834 connector_object_id,
835 &hpd,
836 &router);
837
838 }
839 }
840
841 radeon_link_encoder_connector(dev);
842
843 radeon_setup_mst_connector(dev);
844 return true;
845}
846
847static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
848 int connector_type,
849 uint16_t devices)
850{
851 struct radeon_device *rdev = dev->dev_private;
852
853 if (rdev->flags & RADEON_IS_IGP) {
854 return supported_devices_connector_object_id_convert
855 [connector_type];
856 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
857 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
858 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
859 struct radeon_mode_info *mode_info = &rdev->mode_info;
860 struct atom_context *ctx = mode_info->atom_context;
861 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
862 uint16_t size, data_offset;
863 uint8_t frev, crev;
864 ATOM_XTMDS_INFO *xtmds;
865
866 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
867 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
868
869 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
870 if (connector_type == DRM_MODE_CONNECTOR_DVII)
871 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
872 else
873 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
874 } else {
875 if (connector_type == DRM_MODE_CONNECTOR_DVII)
876 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
877 else
878 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
879 }
880 } else
881 return supported_devices_connector_object_id_convert
882 [connector_type];
883 } else {
884 return supported_devices_connector_object_id_convert
885 [connector_type];
886 }
887}
888
889struct bios_connector {
890 bool valid;
891 uint16_t line_mux;
892 uint16_t devices;
893 int connector_type;
894 struct radeon_i2c_bus_rec ddc_bus;
895 struct radeon_hpd hpd;
896};
897
898bool radeon_get_atom_connector_info_from_supported_devices_table(struct
899 drm_device
900 *dev)
901{
902 struct radeon_device *rdev = dev->dev_private;
903 struct radeon_mode_info *mode_info = &rdev->mode_info;
904 struct atom_context *ctx = mode_info->atom_context;
905 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
906 uint16_t size, data_offset;
907 uint8_t frev, crev;
908 uint16_t device_support;
909 uint8_t dac;
910 union atom_supported_devices *supported_devices;
911 int i, j, max_device;
912 struct bios_connector *bios_connectors;
913 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
914 struct radeon_router router;
915
916 router.ddc_valid = false;
917 router.cd_valid = false;
918
919 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
920 if (!bios_connectors)
921 return false;
922
923 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
924 &data_offset)) {
925 kfree(bios_connectors);
926 return false;
927 }
928
929 supported_devices =
930 (union atom_supported_devices *)(ctx->bios + data_offset);
931
932 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
933
934 if (frev > 1)
935 max_device = ATOM_MAX_SUPPORTED_DEVICE;
936 else
937 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
938
939 for (i = 0; i < max_device; i++) {
940 ATOM_CONNECTOR_INFO_I2C ci =
941 supported_devices->info.asConnInfo[i];
942
943 bios_connectors[i].valid = false;
944
945 if (!(device_support & (1 << i))) {
946 continue;
947 }
948
949 if (i == ATOM_DEVICE_CV_INDEX) {
950 DRM_DEBUG_KMS("Skipping Component Video\n");
951 continue;
952 }
953
954 bios_connectors[i].connector_type =
955 supported_devices_connector_convert[ci.sucConnectorInfo.
956 sbfAccess.
957 bfConnectorType];
958
959 if (bios_connectors[i].connector_type ==
960 DRM_MODE_CONNECTOR_Unknown)
961 continue;
962
963 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
964
965 bios_connectors[i].line_mux =
966 ci.sucI2cId.ucAccess;
967
968 /* give tv unique connector ids */
969 if (i == ATOM_DEVICE_TV1_INDEX) {
970 bios_connectors[i].ddc_bus.valid = false;
971 bios_connectors[i].line_mux = 50;
972 } else if (i == ATOM_DEVICE_TV2_INDEX) {
973 bios_connectors[i].ddc_bus.valid = false;
974 bios_connectors[i].line_mux = 51;
975 } else if (i == ATOM_DEVICE_CV_INDEX) {
976 bios_connectors[i].ddc_bus.valid = false;
977 bios_connectors[i].line_mux = 52;
978 } else
979 bios_connectors[i].ddc_bus =
980 radeon_lookup_i2c_gpio(rdev,
981 bios_connectors[i].line_mux);
982
983 if ((crev > 1) && (frev > 1)) {
984 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
985 switch (isb) {
986 case 0x4:
987 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
988 break;
989 case 0xa:
990 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
991 break;
992 default:
993 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
994 break;
995 }
996 } else {
997 if (i == ATOM_DEVICE_DFP1_INDEX)
998 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
999 else if (i == ATOM_DEVICE_DFP2_INDEX)
1000 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1001 else
1002 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1003 }
1004
1005 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1006 * shared with a DVI port, we'll pick up the DVI connector when we
1007 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1008 */
1009 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1010 bios_connectors[i].connector_type =
1011 DRM_MODE_CONNECTOR_VGA;
1012
1013 if (!radeon_atom_apply_quirks
1014 (dev, (1 << i), &bios_connectors[i].connector_type,
1015 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1016 &bios_connectors[i].hpd))
1017 continue;
1018
1019 bios_connectors[i].valid = true;
1020 bios_connectors[i].devices = (1 << i);
1021
1022 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1023 radeon_add_atom_encoder(dev,
1024 radeon_get_encoder_enum(dev,
1025 (1 << i),
1026 dac),
1027 (1 << i),
1028 0);
1029 else
1030 radeon_add_legacy_encoder(dev,
1031 radeon_get_encoder_enum(dev,
1032 (1 << i),
1033 dac),
1034 (1 << i));
1035 }
1036
1037 /* combine shared connectors */
1038 for (i = 0; i < max_device; i++) {
1039 if (bios_connectors[i].valid) {
1040 for (j = 0; j < max_device; j++) {
1041 if (bios_connectors[j].valid && (i != j)) {
1042 if (bios_connectors[i].line_mux ==
1043 bios_connectors[j].line_mux) {
1044 /* make sure not to combine LVDS */
1045 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1046 bios_connectors[i].line_mux = 53;
1047 bios_connectors[i].ddc_bus.valid = false;
1048 continue;
1049 }
1050 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1051 bios_connectors[j].line_mux = 53;
1052 bios_connectors[j].ddc_bus.valid = false;
1053 continue;
1054 }
1055 /* combine analog and digital for DVI-I */
1056 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1057 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1058 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1059 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1060 bios_connectors[i].devices |=
1061 bios_connectors[j].devices;
1062 bios_connectors[i].connector_type =
1063 DRM_MODE_CONNECTOR_DVII;
1064 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1065 bios_connectors[i].hpd =
1066 bios_connectors[j].hpd;
1067 bios_connectors[j].valid = false;
1068 }
1069 }
1070 }
1071 }
1072 }
1073 }
1074
1075 /* add the connectors */
1076 for (i = 0; i < max_device; i++) {
1077 if (bios_connectors[i].valid) {
1078 uint16_t connector_object_id =
1079 atombios_get_connector_object_id(dev,
1080 bios_connectors[i].connector_type,
1081 bios_connectors[i].devices);
1082 radeon_add_atom_connector(dev,
1083 bios_connectors[i].line_mux,
1084 bios_connectors[i].devices,
1085 bios_connectors[i].
1086 connector_type,
1087 &bios_connectors[i].ddc_bus,
1088 0,
1089 connector_object_id,
1090 &bios_connectors[i].hpd,
1091 &router);
1092 }
1093 }
1094
1095 radeon_link_encoder_connector(dev);
1096
1097 kfree(bios_connectors);
1098 return true;
1099}
1100
1101union firmware_info {
1102 ATOM_FIRMWARE_INFO info;
1103 ATOM_FIRMWARE_INFO_V1_2 info_12;
1104 ATOM_FIRMWARE_INFO_V1_3 info_13;
1105 ATOM_FIRMWARE_INFO_V1_4 info_14;
1106 ATOM_FIRMWARE_INFO_V2_1 info_21;
1107 ATOM_FIRMWARE_INFO_V2_2 info_22;
1108};
1109
1110union igp_info {
1111 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1112 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1113 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1114 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1115 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1116};
1117
1118static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev)
1119{
1120 struct radeon_mode_info *mode_info = &rdev->mode_info;
1121 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1122 union igp_info *igp_info;
1123 u8 frev, crev;
1124 u16 data_offset;
1125
1126 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1127 &frev, &crev, &data_offset)) {
1128 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1129 data_offset);
1130 rdev->clock.vco_freq =
1131 le32_to_cpu(igp_info->info_6.ulDentistVCOFreq);
1132 }
1133}
1134
1135bool radeon_atom_get_clock_info(struct drm_device *dev)
1136{
1137 struct radeon_device *rdev = dev->dev_private;
1138 struct radeon_mode_info *mode_info = &rdev->mode_info;
1139 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1140 union firmware_info *firmware_info;
1141 uint8_t frev, crev;
1142 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1143 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1144 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1145 struct radeon_pll *spll = &rdev->clock.spll;
1146 struct radeon_pll *mpll = &rdev->clock.mpll;
1147 uint16_t data_offset;
1148
1149 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1150 &frev, &crev, &data_offset)) {
1151 firmware_info =
1152 (union firmware_info *)(mode_info->atom_context->bios +
1153 data_offset);
1154 /* pixel clocks */
1155 p1pll->reference_freq =
1156 le16_to_cpu(firmware_info->info.usReferenceClock);
1157 p1pll->reference_div = 0;
1158
1159 if ((frev < 2) && (crev < 2))
1160 p1pll->pll_out_min =
1161 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1162 else
1163 p1pll->pll_out_min =
1164 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1165 p1pll->pll_out_max =
1166 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1167
1168 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) {
1169 p1pll->lcd_pll_out_min =
1170 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1171 if (p1pll->lcd_pll_out_min == 0)
1172 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1173 p1pll->lcd_pll_out_max =
1174 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1175 if (p1pll->lcd_pll_out_max == 0)
1176 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1177 } else {
1178 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1179 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1180 }
1181
1182 if (p1pll->pll_out_min == 0) {
1183 if (ASIC_IS_AVIVO(rdev))
1184 p1pll->pll_out_min = 64800;
1185 else
1186 p1pll->pll_out_min = 20000;
1187 }
1188
1189 p1pll->pll_in_min =
1190 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1191 p1pll->pll_in_max =
1192 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1193
1194 *p2pll = *p1pll;
1195
1196 /* system clock */
1197 if (ASIC_IS_DCE4(rdev))
1198 spll->reference_freq =
1199 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1200 else
1201 spll->reference_freq =
1202 le16_to_cpu(firmware_info->info.usReferenceClock);
1203 spll->reference_div = 0;
1204
1205 spll->pll_out_min =
1206 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1207 spll->pll_out_max =
1208 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1209
1210 /* ??? */
1211 if (spll->pll_out_min == 0) {
1212 if (ASIC_IS_AVIVO(rdev))
1213 spll->pll_out_min = 64800;
1214 else
1215 spll->pll_out_min = 20000;
1216 }
1217
1218 spll->pll_in_min =
1219 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1220 spll->pll_in_max =
1221 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1222
1223 /* memory clock */
1224 if (ASIC_IS_DCE4(rdev))
1225 mpll->reference_freq =
1226 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1227 else
1228 mpll->reference_freq =
1229 le16_to_cpu(firmware_info->info.usReferenceClock);
1230 mpll->reference_div = 0;
1231
1232 mpll->pll_out_min =
1233 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1234 mpll->pll_out_max =
1235 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1236
1237 /* ??? */
1238 if (mpll->pll_out_min == 0) {
1239 if (ASIC_IS_AVIVO(rdev))
1240 mpll->pll_out_min = 64800;
1241 else
1242 mpll->pll_out_min = 20000;
1243 }
1244
1245 mpll->pll_in_min =
1246 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1247 mpll->pll_in_max =
1248 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1249
1250 rdev->clock.default_sclk =
1251 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1252 rdev->clock.default_mclk =
1253 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1254
1255 if (ASIC_IS_DCE4(rdev)) {
1256 rdev->clock.default_dispclk =
1257 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1258 if (rdev->clock.default_dispclk == 0) {
1259 if (ASIC_IS_DCE6(rdev))
1260 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1261 else if (ASIC_IS_DCE5(rdev))
1262 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1263 else
1264 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1265 }
1266 /* set a reasonable default for DP */
1267 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1268 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1269 rdev->clock.default_dispclk / 100);
1270 rdev->clock.default_dispclk = 60000;
1271 }
1272 rdev->clock.dp_extclk =
1273 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1274 rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1275 }
1276 *dcpll = *p1pll;
1277
1278 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1279 if (rdev->clock.max_pixel_clock == 0)
1280 rdev->clock.max_pixel_clock = 40000;
1281
1282 /* not technically a clock, but... */
1283 rdev->mode_info.firmware_flags =
1284 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1285
1286 if (ASIC_IS_DCE8(rdev))
1287 rdev->clock.vco_freq =
1288 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq);
1289 else if (ASIC_IS_DCE5(rdev))
1290 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1291 else if (ASIC_IS_DCE41(rdev))
1292 radeon_atombios_get_dentist_vco_freq(rdev);
1293 else
1294 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1295
1296 if (rdev->clock.vco_freq == 0)
1297 rdev->clock.vco_freq = 360000; /* 3.6 GHz */
1298
1299 return true;
1300 }
1301
1302 return false;
1303}
1304
1305bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1306{
1307 struct radeon_mode_info *mode_info = &rdev->mode_info;
1308 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1309 union igp_info *igp_info;
1310 u8 frev, crev;
1311 u16 data_offset;
1312
1313 /* sideport is AMD only */
1314 if (rdev->family == CHIP_RS600)
1315 return false;
1316
1317 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1318 &frev, &crev, &data_offset)) {
1319 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1320 data_offset);
1321 switch (crev) {
1322 case 1:
1323 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1324 return true;
1325 break;
1326 case 2:
1327 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1328 return true;
1329 break;
1330 default:
1331 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1332 break;
1333 }
1334 }
1335 return false;
1336}
1337
1338bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1339 struct radeon_encoder_int_tmds *tmds)
1340{
1341 struct drm_device *dev = encoder->base.dev;
1342 struct radeon_device *rdev = dev->dev_private;
1343 struct radeon_mode_info *mode_info = &rdev->mode_info;
1344 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1345 uint16_t data_offset;
1346 struct _ATOM_TMDS_INFO *tmds_info;
1347 uint8_t frev, crev;
1348 uint16_t maxfreq;
1349 int i;
1350
1351 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1352 &frev, &crev, &data_offset)) {
1353 tmds_info =
1354 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1355 data_offset);
1356
1357 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1358 for (i = 0; i < 4; i++) {
1359 tmds->tmds_pll[i].freq =
1360 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1361 tmds->tmds_pll[i].value =
1362 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1363 tmds->tmds_pll[i].value |=
1364 (tmds_info->asMiscInfo[i].
1365 ucPLL_VCO_Gain & 0x3f) << 6;
1366 tmds->tmds_pll[i].value |=
1367 (tmds_info->asMiscInfo[i].
1368 ucPLL_DutyCycle & 0xf) << 12;
1369 tmds->tmds_pll[i].value |=
1370 (tmds_info->asMiscInfo[i].
1371 ucPLL_VoltageSwing & 0xf) << 16;
1372
1373 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1374 tmds->tmds_pll[i].freq,
1375 tmds->tmds_pll[i].value);
1376
1377 if (maxfreq == tmds->tmds_pll[i].freq) {
1378 tmds->tmds_pll[i].freq = 0xffffffff;
1379 break;
1380 }
1381 }
1382 return true;
1383 }
1384 return false;
1385}
1386
1387bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1388 struct radeon_atom_ss *ss,
1389 int id)
1390{
1391 struct radeon_mode_info *mode_info = &rdev->mode_info;
1392 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1393 uint16_t data_offset, size;
1394 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1395 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1396 uint8_t frev, crev;
1397 int i, num_indices;
1398
1399 memset(ss, 0, sizeof(struct radeon_atom_ss));
1400 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1401 &frev, &crev, &data_offset)) {
1402 ss_info =
1403 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1404
1405 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1406 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1407 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1408 ((u8 *)&ss_info->asSS_Info[0]);
1409 for (i = 0; i < num_indices; i++) {
1410 if (ss_assign->ucSS_Id == id) {
1411 ss->percentage =
1412 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
1413 ss->type = ss_assign->ucSpreadSpectrumType;
1414 ss->step = ss_assign->ucSS_Step;
1415 ss->delay = ss_assign->ucSS_Delay;
1416 ss->range = ss_assign->ucSS_Range;
1417 ss->refdiv = ss_assign->ucRecommendedRef_Div;
1418 return true;
1419 }
1420 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1421 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1422 }
1423 }
1424 return false;
1425}
1426
1427static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1428 struct radeon_atom_ss *ss,
1429 int id)
1430{
1431 struct radeon_mode_info *mode_info = &rdev->mode_info;
1432 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1433 u16 data_offset, size;
1434 union igp_info *igp_info;
1435 u8 frev, crev;
1436 u16 percentage = 0, rate = 0;
1437
1438 /* get any igp specific overrides */
1439 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1440 &frev, &crev, &data_offset)) {
1441 igp_info = (union igp_info *)
1442 (mode_info->atom_context->bios + data_offset);
1443 switch (crev) {
1444 case 6:
1445 switch (id) {
1446 case ASIC_INTERNAL_SS_ON_TMDS:
1447 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1448 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1449 break;
1450 case ASIC_INTERNAL_SS_ON_HDMI:
1451 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1452 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1453 break;
1454 case ASIC_INTERNAL_SS_ON_LVDS:
1455 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1456 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1457 break;
1458 }
1459 break;
1460 case 7:
1461 switch (id) {
1462 case ASIC_INTERNAL_SS_ON_TMDS:
1463 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1464 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1465 break;
1466 case ASIC_INTERNAL_SS_ON_HDMI:
1467 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1468 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1469 break;
1470 case ASIC_INTERNAL_SS_ON_LVDS:
1471 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1472 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1473 break;
1474 }
1475 break;
1476 case 8:
1477 switch (id) {
1478 case ASIC_INTERNAL_SS_ON_TMDS:
1479 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1480 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1481 break;
1482 case ASIC_INTERNAL_SS_ON_HDMI:
1483 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1484 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1485 break;
1486 case ASIC_INTERNAL_SS_ON_LVDS:
1487 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1488 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1489 break;
1490 }
1491 break;
1492 default:
1493 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1494 break;
1495 }
1496 if (percentage)
1497 ss->percentage = percentage;
1498 if (rate)
1499 ss->rate = rate;
1500 }
1501}
1502
1503union asic_ss_info {
1504 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1505 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1506 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1507};
1508
1509union asic_ss_assignment {
1510 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
1511 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
1512 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
1513};
1514
1515bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1516 struct radeon_atom_ss *ss,
1517 int id, u32 clock)
1518{
1519 struct radeon_mode_info *mode_info = &rdev->mode_info;
1520 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1521 uint16_t data_offset, size;
1522 union asic_ss_info *ss_info;
1523 union asic_ss_assignment *ss_assign;
1524 uint8_t frev, crev;
1525 int i, num_indices;
1526
1527 if (id == ASIC_INTERNAL_MEMORY_SS) {
1528 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1529 return false;
1530 }
1531 if (id == ASIC_INTERNAL_ENGINE_SS) {
1532 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1533 return false;
1534 }
1535
1536 memset(ss, 0, sizeof(struct radeon_atom_ss));
1537 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1538 &frev, &crev, &data_offset)) {
1539
1540 ss_info =
1541 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1542
1543 switch (frev) {
1544 case 1:
1545 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1546 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1547
1548 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
1549 for (i = 0; i < num_indices; i++) {
1550 if ((ss_assign->v1.ucClockIndication == id) &&
1551 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1552 ss->percentage =
1553 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1554 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1555 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1556 ss->percentage_divider = 100;
1557 return true;
1558 }
1559 ss_assign = (union asic_ss_assignment *)
1560 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1561 }
1562 break;
1563 case 2:
1564 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1565 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1566 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
1567 for (i = 0; i < num_indices; i++) {
1568 if ((ss_assign->v2.ucClockIndication == id) &&
1569 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1570 ss->percentage =
1571 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1572 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1573 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1574 ss->percentage_divider = 100;
1575 if ((crev == 2) &&
1576 ((id == ASIC_INTERNAL_ENGINE_SS) ||
1577 (id == ASIC_INTERNAL_MEMORY_SS)))
1578 ss->rate /= 100;
1579 return true;
1580 }
1581 ss_assign = (union asic_ss_assignment *)
1582 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1583 }
1584 break;
1585 case 3:
1586 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1587 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1588 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
1589 for (i = 0; i < num_indices; i++) {
1590 if ((ss_assign->v3.ucClockIndication == id) &&
1591 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1592 ss->percentage =
1593 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1594 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1595 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1596 if (ss_assign->v3.ucSpreadSpectrumMode &
1597 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
1598 ss->percentage_divider = 1000;
1599 else
1600 ss->percentage_divider = 100;
1601 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1602 (id == ASIC_INTERNAL_MEMORY_SS))
1603 ss->rate /= 100;
1604 if (rdev->flags & RADEON_IS_IGP)
1605 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1606 return true;
1607 }
1608 ss_assign = (union asic_ss_assignment *)
1609 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1610 }
1611 break;
1612 default:
1613 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1614 break;
1615 }
1616
1617 }
1618 return false;
1619}
1620
1621union lvds_info {
1622 struct _ATOM_LVDS_INFO info;
1623 struct _ATOM_LVDS_INFO_V12 info_12;
1624};
1625
1626struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1627 radeon_encoder
1628 *encoder)
1629{
1630 struct drm_device *dev = encoder->base.dev;
1631 struct radeon_device *rdev = dev->dev_private;
1632 struct radeon_mode_info *mode_info = &rdev->mode_info;
1633 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1634 uint16_t data_offset, misc;
1635 union lvds_info *lvds_info;
1636 uint8_t frev, crev;
1637 struct radeon_encoder_atom_dig *lvds = NULL;
1638 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1639
1640 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1641 &frev, &crev, &data_offset)) {
1642 lvds_info =
1643 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1644 lvds =
1645 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1646
1647 if (!lvds)
1648 return NULL;
1649
1650 lvds->native_mode.clock =
1651 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1652 lvds->native_mode.hdisplay =
1653 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1654 lvds->native_mode.vdisplay =
1655 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1656 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1657 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1658 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1659 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1660 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1661 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1662 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1663 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1664 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1665 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1666 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1667 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1668 lvds->panel_pwr_delay =
1669 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1670 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1671
1672 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1673 if (misc & ATOM_VSYNC_POLARITY)
1674 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1675 if (misc & ATOM_HSYNC_POLARITY)
1676 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1677 if (misc & ATOM_COMPOSITESYNC)
1678 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1679 if (misc & ATOM_INTERLACE)
1680 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1681 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1682 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1683
1684 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1685 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1686
1687 /* set crtc values */
1688 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1689
1690 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1691
1692 encoder->native_mode = lvds->native_mode;
1693
1694 if (encoder_enum == 2)
1695 lvds->linkb = true;
1696 else
1697 lvds->linkb = false;
1698
1699 /* parse the lcd record table */
1700 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1701 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1702 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1703 bool bad_record = false;
1704 u8 *record;
1705
1706 if ((frev == 1) && (crev < 2))
1707 /* absolute */
1708 record = (u8 *)(mode_info->atom_context->bios +
1709 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1710 else
1711 /* relative */
1712 record = (u8 *)(mode_info->atom_context->bios +
1713 data_offset +
1714 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1715 while (*record != ATOM_RECORD_END_TYPE) {
1716 switch (*record) {
1717 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1718 record += sizeof(ATOM_PATCH_RECORD_MODE);
1719 break;
1720 case LCD_RTS_RECORD_TYPE:
1721 record += sizeof(ATOM_LCD_RTS_RECORD);
1722 break;
1723 case LCD_CAP_RECORD_TYPE:
1724 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1725 break;
1726 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1727 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1728 if (fake_edid_record->ucFakeEDIDLength) {
1729 struct edid *edid;
1730 int edid_size =
1731 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1732 edid = kmalloc(edid_size, GFP_KERNEL);
1733 if (edid) {
1734 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1735 fake_edid_record->ucFakeEDIDLength);
1736
1737 if (drm_edid_is_valid(edid)) {
1738 rdev->mode_info.bios_hardcoded_edid = edid;
1739 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1740 } else
1741 kfree(edid);
1742 }
1743 }
1744 record += fake_edid_record->ucFakeEDIDLength ?
1745 fake_edid_record->ucFakeEDIDLength + 2 :
1746 sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1747 break;
1748 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1749 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1750 lvds->native_mode.width_mm = panel_res_record->usHSize;
1751 lvds->native_mode.height_mm = panel_res_record->usVSize;
1752 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1753 break;
1754 default:
1755 DRM_ERROR("Bad LCD record %d\n", *record);
1756 bad_record = true;
1757 break;
1758 }
1759 if (bad_record)
1760 break;
1761 }
1762 }
1763 }
1764 return lvds;
1765}
1766
1767struct radeon_encoder_primary_dac *
1768radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1769{
1770 struct drm_device *dev = encoder->base.dev;
1771 struct radeon_device *rdev = dev->dev_private;
1772 struct radeon_mode_info *mode_info = &rdev->mode_info;
1773 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1774 uint16_t data_offset;
1775 struct _COMPASSIONATE_DATA *dac_info;
1776 uint8_t frev, crev;
1777 uint8_t bg, dac;
1778 struct radeon_encoder_primary_dac *p_dac = NULL;
1779
1780 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1781 &frev, &crev, &data_offset)) {
1782 dac_info = (struct _COMPASSIONATE_DATA *)
1783 (mode_info->atom_context->bios + data_offset);
1784
1785 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1786
1787 if (!p_dac)
1788 return NULL;
1789
1790 bg = dac_info->ucDAC1_BG_Adjustment;
1791 dac = dac_info->ucDAC1_DAC_Adjustment;
1792 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1793
1794 }
1795 return p_dac;
1796}
1797
1798bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1799 struct drm_display_mode *mode)
1800{
1801 struct radeon_mode_info *mode_info = &rdev->mode_info;
1802 ATOM_ANALOG_TV_INFO *tv_info;
1803 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1804 ATOM_DTD_FORMAT *dtd_timings;
1805 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1806 u8 frev, crev;
1807 u16 data_offset, misc;
1808
1809 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1810 &frev, &crev, &data_offset))
1811 return false;
1812
1813 switch (crev) {
1814 case 1:
1815 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1816 if (index >= MAX_SUPPORTED_TV_TIMING)
1817 return false;
1818
1819 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1820 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1821 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1822 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1823 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1824
1825 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1826 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1827 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1828 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1829 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1830
1831 mode->flags = 0;
1832 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1833 if (misc & ATOM_VSYNC_POLARITY)
1834 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1835 if (misc & ATOM_HSYNC_POLARITY)
1836 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1837 if (misc & ATOM_COMPOSITESYNC)
1838 mode->flags |= DRM_MODE_FLAG_CSYNC;
1839 if (misc & ATOM_INTERLACE)
1840 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1841 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1842 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1843
1844 mode->crtc_clock = mode->clock =
1845 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1846
1847 if (index == 1) {
1848 /* PAL timings appear to have wrong values for totals */
1849 mode->crtc_htotal -= 1;
1850 mode->crtc_vtotal -= 1;
1851 }
1852 break;
1853 case 2:
1854 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1855 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1856 return false;
1857
1858 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1859 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1860 le16_to_cpu(dtd_timings->usHBlanking_Time);
1861 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1862 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1863 le16_to_cpu(dtd_timings->usHSyncOffset);
1864 mode->crtc_hsync_end = mode->crtc_hsync_start +
1865 le16_to_cpu(dtd_timings->usHSyncWidth);
1866
1867 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1868 le16_to_cpu(dtd_timings->usVBlanking_Time);
1869 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1870 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1871 le16_to_cpu(dtd_timings->usVSyncOffset);
1872 mode->crtc_vsync_end = mode->crtc_vsync_start +
1873 le16_to_cpu(dtd_timings->usVSyncWidth);
1874
1875 mode->flags = 0;
1876 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1877 if (misc & ATOM_VSYNC_POLARITY)
1878 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1879 if (misc & ATOM_HSYNC_POLARITY)
1880 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1881 if (misc & ATOM_COMPOSITESYNC)
1882 mode->flags |= DRM_MODE_FLAG_CSYNC;
1883 if (misc & ATOM_INTERLACE)
1884 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1885 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1886 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1887
1888 mode->crtc_clock = mode->clock =
1889 le16_to_cpu(dtd_timings->usPixClk) * 10;
1890 break;
1891 }
1892 return true;
1893}
1894
1895enum radeon_tv_std
1896radeon_atombios_get_tv_info(struct radeon_device *rdev)
1897{
1898 struct radeon_mode_info *mode_info = &rdev->mode_info;
1899 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1900 uint16_t data_offset;
1901 uint8_t frev, crev;
1902 struct _ATOM_ANALOG_TV_INFO *tv_info;
1903 enum radeon_tv_std tv_std = TV_STD_NTSC;
1904
1905 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1906 &frev, &crev, &data_offset)) {
1907
1908 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1909 (mode_info->atom_context->bios + data_offset);
1910
1911 switch (tv_info->ucTV_BootUpDefaultStandard) {
1912 case ATOM_TV_NTSC:
1913 tv_std = TV_STD_NTSC;
1914 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1915 break;
1916 case ATOM_TV_NTSCJ:
1917 tv_std = TV_STD_NTSC_J;
1918 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1919 break;
1920 case ATOM_TV_PAL:
1921 tv_std = TV_STD_PAL;
1922 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1923 break;
1924 case ATOM_TV_PALM:
1925 tv_std = TV_STD_PAL_M;
1926 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1927 break;
1928 case ATOM_TV_PALN:
1929 tv_std = TV_STD_PAL_N;
1930 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1931 break;
1932 case ATOM_TV_PALCN:
1933 tv_std = TV_STD_PAL_CN;
1934 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1935 break;
1936 case ATOM_TV_PAL60:
1937 tv_std = TV_STD_PAL_60;
1938 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1939 break;
1940 case ATOM_TV_SECAM:
1941 tv_std = TV_STD_SECAM;
1942 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1943 break;
1944 default:
1945 tv_std = TV_STD_NTSC;
1946 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1947 break;
1948 }
1949 }
1950 return tv_std;
1951}
1952
1953struct radeon_encoder_tv_dac *
1954radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1955{
1956 struct drm_device *dev = encoder->base.dev;
1957 struct radeon_device *rdev = dev->dev_private;
1958 struct radeon_mode_info *mode_info = &rdev->mode_info;
1959 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1960 uint16_t data_offset;
1961 struct _COMPASSIONATE_DATA *dac_info;
1962 uint8_t frev, crev;
1963 uint8_t bg, dac;
1964 struct radeon_encoder_tv_dac *tv_dac = NULL;
1965
1966 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1967 &frev, &crev, &data_offset)) {
1968
1969 dac_info = (struct _COMPASSIONATE_DATA *)
1970 (mode_info->atom_context->bios + data_offset);
1971
1972 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1973
1974 if (!tv_dac)
1975 return NULL;
1976
1977 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1978 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1979 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1980
1981 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1982 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1983 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1984
1985 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1986 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1987 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1988
1989 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1990 }
1991 return tv_dac;
1992}
1993
1994static const char *thermal_controller_names[] = {
1995 "NONE",
1996 "lm63",
1997 "adm1032",
1998 "adm1030",
1999 "max6649",
2000 "lm63", /* lm64 */
2001 "f75375",
2002 "asc7xxx",
2003};
2004
2005static const char *pp_lib_thermal_controller_names[] = {
2006 "NONE",
2007 "lm63",
2008 "adm1032",
2009 "adm1030",
2010 "max6649",
2011 "lm63", /* lm64 */
2012 "f75375",
2013 "RV6xx",
2014 "RV770",
2015 "adt7473",
2016 "NONE",
2017 "External GPIO",
2018 "Evergreen",
2019 "emc2103",
2020 "Sumo",
2021 "Northern Islands",
2022 "Southern Islands",
2023 "lm96163",
2024 "Sea Islands",
2025};
2026
2027union power_info {
2028 struct _ATOM_POWERPLAY_INFO info;
2029 struct _ATOM_POWERPLAY_INFO_V2 info_2;
2030 struct _ATOM_POWERPLAY_INFO_V3 info_3;
2031 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2032 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2033 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2034};
2035
2036union pplib_clock_info {
2037 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2038 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2039 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2040 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2041 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
2042 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
2043};
2044
2045union pplib_power_state {
2046 struct _ATOM_PPLIB_STATE v1;
2047 struct _ATOM_PPLIB_STATE_V2 v2;
2048};
2049
2050static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2051 int state_index,
2052 u32 misc, u32 misc2)
2053{
2054 rdev->pm.power_state[state_index].misc = misc;
2055 rdev->pm.power_state[state_index].misc2 = misc2;
2056 /* order matters! */
2057 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2058 rdev->pm.power_state[state_index].type =
2059 POWER_STATE_TYPE_POWERSAVE;
2060 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2061 rdev->pm.power_state[state_index].type =
2062 POWER_STATE_TYPE_BATTERY;
2063 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2064 rdev->pm.power_state[state_index].type =
2065 POWER_STATE_TYPE_BATTERY;
2066 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2067 rdev->pm.power_state[state_index].type =
2068 POWER_STATE_TYPE_BALANCED;
2069 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2070 rdev->pm.power_state[state_index].type =
2071 POWER_STATE_TYPE_PERFORMANCE;
2072 rdev->pm.power_state[state_index].flags &=
2073 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2074 }
2075 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2076 rdev->pm.power_state[state_index].type =
2077 POWER_STATE_TYPE_BALANCED;
2078 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2079 rdev->pm.power_state[state_index].type =
2080 POWER_STATE_TYPE_DEFAULT;
2081 rdev->pm.default_power_state_index = state_index;
2082 rdev->pm.power_state[state_index].default_clock_mode =
2083 &rdev->pm.power_state[state_index].clock_info[0];
2084 } else if (state_index == 0) {
2085 rdev->pm.power_state[state_index].clock_info[0].flags |=
2086 RADEON_PM_MODE_NO_DISPLAY;
2087 }
2088}
2089
2090static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2091{
2092 struct radeon_mode_info *mode_info = &rdev->mode_info;
2093 u32 misc, misc2 = 0;
2094 int num_modes = 0, i;
2095 int state_index = 0;
2096 struct radeon_i2c_bus_rec i2c_bus;
2097 union power_info *power_info;
2098 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2099 u16 data_offset;
2100 u8 frev, crev;
2101
2102 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2103 &frev, &crev, &data_offset))
2104 return state_index;
2105 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2106
2107 /* add the i2c bus for thermal/fan chip */
2108 if ((power_info->info.ucOverdriveThermalController > 0) &&
2109 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2110 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2111 thermal_controller_names[power_info->info.ucOverdriveThermalController],
2112 power_info->info.ucOverdriveControllerAddress >> 1);
2113 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2114 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2115 if (rdev->pm.i2c_bus) {
2116 struct i2c_board_info info = { };
2117 const char *name = thermal_controller_names[power_info->info.
2118 ucOverdriveThermalController];
2119 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2120 strlcpy(info.type, name, sizeof(info.type));
2121 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2122 }
2123 }
2124 num_modes = power_info->info.ucNumOfPowerModeEntries;
2125 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2126 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2127 if (num_modes == 0)
2128 return state_index;
2129 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2130 if (!rdev->pm.power_state)
2131 return state_index;
2132 /* last mode is usually default, array is low to high */
2133 for (i = 0; i < num_modes; i++) {
2134 rdev->pm.power_state[state_index].clock_info =
2135 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2136 if (!rdev->pm.power_state[state_index].clock_info)
2137 return state_index;
2138 rdev->pm.power_state[state_index].num_clock_modes = 1;
2139 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2140 switch (frev) {
2141 case 1:
2142 rdev->pm.power_state[state_index].clock_info[0].mclk =
2143 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2144 rdev->pm.power_state[state_index].clock_info[0].sclk =
2145 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2146 /* skip invalid modes */
2147 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2148 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2149 continue;
2150 rdev->pm.power_state[state_index].pcie_lanes =
2151 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2152 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2153 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2154 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2155 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2156 VOLTAGE_GPIO;
2157 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2158 radeon_atombios_lookup_gpio(rdev,
2159 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2160 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2161 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2162 true;
2163 else
2164 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2165 false;
2166 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2167 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2168 VOLTAGE_VDDC;
2169 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2170 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2171 }
2172 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2173 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2174 state_index++;
2175 break;
2176 case 2:
2177 rdev->pm.power_state[state_index].clock_info[0].mclk =
2178 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2179 rdev->pm.power_state[state_index].clock_info[0].sclk =
2180 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2181 /* skip invalid modes */
2182 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2183 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2184 continue;
2185 rdev->pm.power_state[state_index].pcie_lanes =
2186 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2187 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2188 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2189 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2190 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2191 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2192 VOLTAGE_GPIO;
2193 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2194 radeon_atombios_lookup_gpio(rdev,
2195 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2196 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2197 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2198 true;
2199 else
2200 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2201 false;
2202 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2203 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2204 VOLTAGE_VDDC;
2205 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2206 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2207 }
2208 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2209 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2210 state_index++;
2211 break;
2212 case 3:
2213 rdev->pm.power_state[state_index].clock_info[0].mclk =
2214 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2215 rdev->pm.power_state[state_index].clock_info[0].sclk =
2216 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2217 /* skip invalid modes */
2218 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2219 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2220 continue;
2221 rdev->pm.power_state[state_index].pcie_lanes =
2222 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2223 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2224 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2225 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2226 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2227 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2228 VOLTAGE_GPIO;
2229 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2230 radeon_atombios_lookup_gpio(rdev,
2231 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2232 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2233 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2234 true;
2235 else
2236 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2237 false;
2238 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2239 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2240 VOLTAGE_VDDC;
2241 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2242 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2243 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2244 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2245 true;
2246 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2247 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2248 }
2249 }
2250 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2251 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2252 state_index++;
2253 break;
2254 }
2255 }
2256 /* last mode is usually default */
2257 if (rdev->pm.default_power_state_index == -1) {
2258 rdev->pm.power_state[state_index - 1].type =
2259 POWER_STATE_TYPE_DEFAULT;
2260 rdev->pm.default_power_state_index = state_index - 1;
2261 rdev->pm.power_state[state_index - 1].default_clock_mode =
2262 &rdev->pm.power_state[state_index - 1].clock_info[0];
2263 rdev->pm.power_state[state_index].flags &=
2264 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2265 rdev->pm.power_state[state_index].misc = 0;
2266 rdev->pm.power_state[state_index].misc2 = 0;
2267 }
2268 return state_index;
2269}
2270
2271static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2272 ATOM_PPLIB_THERMALCONTROLLER *controller)
2273{
2274 struct radeon_i2c_bus_rec i2c_bus;
2275
2276 /* add the i2c bus for thermal/fan chip */
2277 if (controller->ucType > 0) {
2278 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN)
2279 rdev->pm.no_fan = true;
2280 rdev->pm.fan_pulses_per_revolution =
2281 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
2282 if (rdev->pm.fan_pulses_per_revolution) {
2283 rdev->pm.fan_min_rpm = controller->ucFanMinRPM;
2284 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM;
2285 }
2286 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2287 DRM_INFO("Internal thermal controller %s fan control\n",
2288 (controller->ucFanParameters &
2289 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2290 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2291 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2292 DRM_INFO("Internal thermal controller %s fan control\n",
2293 (controller->ucFanParameters &
2294 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2295 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2296 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2297 DRM_INFO("Internal thermal controller %s fan control\n",
2298 (controller->ucFanParameters &
2299 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2300 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2301 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2302 DRM_INFO("Internal thermal controller %s fan control\n",
2303 (controller->ucFanParameters &
2304 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2305 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2306 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2307 DRM_INFO("Internal thermal controller %s fan control\n",
2308 (controller->ucFanParameters &
2309 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2310 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2311 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2312 DRM_INFO("Internal thermal controller %s fan control\n",
2313 (controller->ucFanParameters &
2314 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2315 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2316 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2317 DRM_INFO("Internal thermal controller %s fan control\n",
2318 (controller->ucFanParameters &
2319 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2320 rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2321 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
2322 DRM_INFO("Internal thermal controller %s fan control\n",
2323 (controller->ucFanParameters &
2324 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2325 rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2326 } else if (controller->ucType ==
2327 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
2328 DRM_INFO("External GPIO thermal controller %s fan control\n",
2329 (controller->ucFanParameters &
2330 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2331 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
2332 } else if (controller->ucType ==
2333 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
2334 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
2335 (controller->ucFanParameters &
2336 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2337 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
2338 } else if (controller->ucType ==
2339 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
2340 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
2341 (controller->ucFanParameters &
2342 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2343 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2344 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2345 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2346 pp_lib_thermal_controller_names[controller->ucType],
2347 controller->ucI2cAddress >> 1,
2348 (controller->ucFanParameters &
2349 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2350 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
2351 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2352 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2353 if (rdev->pm.i2c_bus) {
2354 struct i2c_board_info info = { };
2355 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2356 info.addr = controller->ucI2cAddress >> 1;
2357 strlcpy(info.type, name, sizeof(info.type));
2358 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2359 }
2360 } else {
2361 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2362 controller->ucType,
2363 controller->ucI2cAddress >> 1,
2364 (controller->ucFanParameters &
2365 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2366 }
2367 }
2368}
2369
2370void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2371 u16 *vddc, u16 *vddci, u16 *mvdd)
2372{
2373 struct radeon_mode_info *mode_info = &rdev->mode_info;
2374 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2375 u8 frev, crev;
2376 u16 data_offset;
2377 union firmware_info *firmware_info;
2378
2379 *vddc = 0;
2380 *vddci = 0;
2381 *mvdd = 0;
2382
2383 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2384 &frev, &crev, &data_offset)) {
2385 firmware_info =
2386 (union firmware_info *)(mode_info->atom_context->bios +
2387 data_offset);
2388 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2389 if ((frev == 2) && (crev >= 2)) {
2390 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2391 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2392 }
2393 }
2394}
2395
2396static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2397 int state_index, int mode_index,
2398 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2399{
2400 int j;
2401 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2402 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2403 u16 vddc, vddci, mvdd;
2404
2405 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2406
2407 rdev->pm.power_state[state_index].misc = misc;
2408 rdev->pm.power_state[state_index].misc2 = misc2;
2409 rdev->pm.power_state[state_index].pcie_lanes =
2410 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2411 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2412 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2413 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2414 rdev->pm.power_state[state_index].type =
2415 POWER_STATE_TYPE_BATTERY;
2416 break;
2417 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2418 rdev->pm.power_state[state_index].type =
2419 POWER_STATE_TYPE_BALANCED;
2420 break;
2421 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2422 rdev->pm.power_state[state_index].type =
2423 POWER_STATE_TYPE_PERFORMANCE;
2424 break;
2425 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2426 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2427 rdev->pm.power_state[state_index].type =
2428 POWER_STATE_TYPE_PERFORMANCE;
2429 break;
2430 }
2431 rdev->pm.power_state[state_index].flags = 0;
2432 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2433 rdev->pm.power_state[state_index].flags |=
2434 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2435 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2436 rdev->pm.power_state[state_index].type =
2437 POWER_STATE_TYPE_DEFAULT;
2438 rdev->pm.default_power_state_index = state_index;
2439 rdev->pm.power_state[state_index].default_clock_mode =
2440 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2441 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2442 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2443 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2444 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2445 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2446 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2447 } else {
2448 u16 max_vddci = 0;
2449
2450 if (ASIC_IS_DCE4(rdev))
2451 radeon_atom_get_max_voltage(rdev,
2452 SET_VOLTAGE_TYPE_ASIC_VDDCI,
2453 &max_vddci);
2454 /* patch the table values with the default sclk/mclk from firmware info */
2455 for (j = 0; j < mode_index; j++) {
2456 rdev->pm.power_state[state_index].clock_info[j].mclk =
2457 rdev->clock.default_mclk;
2458 rdev->pm.power_state[state_index].clock_info[j].sclk =
2459 rdev->clock.default_sclk;
2460 if (vddc)
2461 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2462 vddc;
2463 if (max_vddci)
2464 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2465 max_vddci;
2466 }
2467 }
2468 }
2469}
2470
2471static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2472 int state_index, int mode_index,
2473 union pplib_clock_info *clock_info)
2474{
2475 u32 sclk, mclk;
2476 u16 vddc;
2477
2478 if (rdev->flags & RADEON_IS_IGP) {
2479 if (rdev->family >= CHIP_PALM) {
2480 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2481 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2482 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2483 } else {
2484 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2485 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2486 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2487 }
2488 } else if (rdev->family >= CHIP_BONAIRE) {
2489 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2490 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2491 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2492 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2493 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2494 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2495 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2496 VOLTAGE_NONE;
2497 } else if (rdev->family >= CHIP_TAHITI) {
2498 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2499 sclk |= clock_info->si.ucEngineClockHigh << 16;
2500 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2501 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2502 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2503 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2504 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2505 VOLTAGE_SW;
2506 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2507 le16_to_cpu(clock_info->si.usVDDC);
2508 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2509 le16_to_cpu(clock_info->si.usVDDCI);
2510 } else if (rdev->family >= CHIP_CEDAR) {
2511 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2512 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2513 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2514 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2515 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2516 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2517 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2518 VOLTAGE_SW;
2519 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2520 le16_to_cpu(clock_info->evergreen.usVDDC);
2521 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2522 le16_to_cpu(clock_info->evergreen.usVDDCI);
2523 } else {
2524 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2525 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2526 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2527 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2528 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2529 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2530 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2531 VOLTAGE_SW;
2532 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2533 le16_to_cpu(clock_info->r600.usVDDC);
2534 }
2535
2536 /* patch up vddc if necessary */
2537 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2538 case ATOM_VIRTUAL_VOLTAGE_ID0:
2539 case ATOM_VIRTUAL_VOLTAGE_ID1:
2540 case ATOM_VIRTUAL_VOLTAGE_ID2:
2541 case ATOM_VIRTUAL_VOLTAGE_ID3:
2542 case ATOM_VIRTUAL_VOLTAGE_ID4:
2543 case ATOM_VIRTUAL_VOLTAGE_ID5:
2544 case ATOM_VIRTUAL_VOLTAGE_ID6:
2545 case ATOM_VIRTUAL_VOLTAGE_ID7:
2546 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2547 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2548 &vddc) == 0)
2549 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2550 break;
2551 default:
2552 break;
2553 }
2554
2555 if (rdev->flags & RADEON_IS_IGP) {
2556 /* skip invalid modes */
2557 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2558 return false;
2559 } else {
2560 /* skip invalid modes */
2561 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2562 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2563 return false;
2564 }
2565 return true;
2566}
2567
2568static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2569{
2570 struct radeon_mode_info *mode_info = &rdev->mode_info;
2571 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2572 union pplib_power_state *power_state;
2573 int i, j;
2574 int state_index = 0, mode_index = 0;
2575 union pplib_clock_info *clock_info;
2576 bool valid;
2577 union power_info *power_info;
2578 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2579 u16 data_offset;
2580 u8 frev, crev;
2581
2582 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2583 &frev, &crev, &data_offset))
2584 return state_index;
2585 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2586
2587 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2588 if (power_info->pplib.ucNumStates == 0)
2589 return state_index;
2590 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2591 power_info->pplib.ucNumStates, GFP_KERNEL);
2592 if (!rdev->pm.power_state)
2593 return state_index;
2594 /* first mode is usually default, followed by low to high */
2595 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2596 mode_index = 0;
2597 power_state = (union pplib_power_state *)
2598 (mode_info->atom_context->bios + data_offset +
2599 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2600 i * power_info->pplib.ucStateEntrySize);
2601 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2602 (mode_info->atom_context->bios + data_offset +
2603 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2604 (power_state->v1.ucNonClockStateIndex *
2605 power_info->pplib.ucNonClockSize));
2606 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2607 ((power_info->pplib.ucStateEntrySize - 1) ?
2608 (power_info->pplib.ucStateEntrySize - 1) : 1),
2609 GFP_KERNEL);
2610 if (!rdev->pm.power_state[i].clock_info)
2611 return state_index;
2612 if (power_info->pplib.ucStateEntrySize - 1) {
2613 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2614 clock_info = (union pplib_clock_info *)
2615 (mode_info->atom_context->bios + data_offset +
2616 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2617 (power_state->v1.ucClockStateIndices[j] *
2618 power_info->pplib.ucClockInfoSize));
2619 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2620 state_index, mode_index,
2621 clock_info);
2622 if (valid)
2623 mode_index++;
2624 }
2625 } else {
2626 rdev->pm.power_state[state_index].clock_info[0].mclk =
2627 rdev->clock.default_mclk;
2628 rdev->pm.power_state[state_index].clock_info[0].sclk =
2629 rdev->clock.default_sclk;
2630 mode_index++;
2631 }
2632 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2633 if (mode_index) {
2634 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2635 non_clock_info);
2636 state_index++;
2637 }
2638 }
2639 /* if multiple clock modes, mark the lowest as no display */
2640 for (i = 0; i < state_index; i++) {
2641 if (rdev->pm.power_state[i].num_clock_modes > 1)
2642 rdev->pm.power_state[i].clock_info[0].flags |=
2643 RADEON_PM_MODE_NO_DISPLAY;
2644 }
2645 /* first mode is usually default */
2646 if (rdev->pm.default_power_state_index == -1) {
2647 rdev->pm.power_state[0].type =
2648 POWER_STATE_TYPE_DEFAULT;
2649 rdev->pm.default_power_state_index = 0;
2650 rdev->pm.power_state[0].default_clock_mode =
2651 &rdev->pm.power_state[0].clock_info[0];
2652 }
2653 return state_index;
2654}
2655
2656static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2657{
2658 struct radeon_mode_info *mode_info = &rdev->mode_info;
2659 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2660 union pplib_power_state *power_state;
2661 int i, j, non_clock_array_index, clock_array_index;
2662 int state_index = 0, mode_index = 0;
2663 union pplib_clock_info *clock_info;
2664 struct _StateArray *state_array;
2665 struct _ClockInfoArray *clock_info_array;
2666 struct _NonClockInfoArray *non_clock_info_array;
2667 bool valid;
2668 union power_info *power_info;
2669 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2670 u16 data_offset;
2671 u8 frev, crev;
2672 u8 *power_state_offset;
2673
2674 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2675 &frev, &crev, &data_offset))
2676 return state_index;
2677 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2678
2679 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2680 state_array = (struct _StateArray *)
2681 (mode_info->atom_context->bios + data_offset +
2682 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2683 clock_info_array = (struct _ClockInfoArray *)
2684 (mode_info->atom_context->bios + data_offset +
2685 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2686 non_clock_info_array = (struct _NonClockInfoArray *)
2687 (mode_info->atom_context->bios + data_offset +
2688 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2689 if (state_array->ucNumEntries == 0)
2690 return state_index;
2691 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2692 state_array->ucNumEntries, GFP_KERNEL);
2693 if (!rdev->pm.power_state)
2694 return state_index;
2695 power_state_offset = (u8 *)state_array->states;
2696 for (i = 0; i < state_array->ucNumEntries; i++) {
2697 mode_index = 0;
2698 power_state = (union pplib_power_state *)power_state_offset;
2699 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2700 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2701 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2702 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2703 (power_state->v2.ucNumDPMLevels ?
2704 power_state->v2.ucNumDPMLevels : 1),
2705 GFP_KERNEL);
2706 if (!rdev->pm.power_state[i].clock_info)
2707 return state_index;
2708 if (power_state->v2.ucNumDPMLevels) {
2709 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2710 clock_array_index = power_state->v2.clockInfoIndex[j];
2711 clock_info = (union pplib_clock_info *)
2712 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2713 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2714 state_index, mode_index,
2715 clock_info);
2716 if (valid)
2717 mode_index++;
2718 }
2719 } else {
2720 rdev->pm.power_state[state_index].clock_info[0].mclk =
2721 rdev->clock.default_mclk;
2722 rdev->pm.power_state[state_index].clock_info[0].sclk =
2723 rdev->clock.default_sclk;
2724 mode_index++;
2725 }
2726 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2727 if (mode_index) {
2728 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2729 non_clock_info);
2730 state_index++;
2731 }
2732 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2733 }
2734 /* if multiple clock modes, mark the lowest as no display */
2735 for (i = 0; i < state_index; i++) {
2736 if (rdev->pm.power_state[i].num_clock_modes > 1)
2737 rdev->pm.power_state[i].clock_info[0].flags |=
2738 RADEON_PM_MODE_NO_DISPLAY;
2739 }
2740 /* first mode is usually default */
2741 if (rdev->pm.default_power_state_index == -1) {
2742 rdev->pm.power_state[0].type =
2743 POWER_STATE_TYPE_DEFAULT;
2744 rdev->pm.default_power_state_index = 0;
2745 rdev->pm.power_state[0].default_clock_mode =
2746 &rdev->pm.power_state[0].clock_info[0];
2747 }
2748 return state_index;
2749}
2750
2751void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2752{
2753 struct radeon_mode_info *mode_info = &rdev->mode_info;
2754 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2755 u16 data_offset;
2756 u8 frev, crev;
2757 int state_index = 0;
2758
2759 rdev->pm.default_power_state_index = -1;
2760
2761 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2762 &frev, &crev, &data_offset)) {
2763 switch (frev) {
2764 case 1:
2765 case 2:
2766 case 3:
2767 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2768 break;
2769 case 4:
2770 case 5:
2771 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2772 break;
2773 case 6:
2774 state_index = radeon_atombios_parse_power_table_6(rdev);
2775 break;
2776 default:
2777 break;
2778 }
2779 }
2780
2781 if (state_index == 0) {
2782 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2783 if (rdev->pm.power_state) {
2784 rdev->pm.power_state[0].clock_info =
2785 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2786 if (rdev->pm.power_state[0].clock_info) {
2787 /* add the default mode */
2788 rdev->pm.power_state[state_index].type =
2789 POWER_STATE_TYPE_DEFAULT;
2790 rdev->pm.power_state[state_index].num_clock_modes = 1;
2791 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2792 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2793 rdev->pm.power_state[state_index].default_clock_mode =
2794 &rdev->pm.power_state[state_index].clock_info[0];
2795 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2796 rdev->pm.power_state[state_index].pcie_lanes = 16;
2797 rdev->pm.default_power_state_index = state_index;
2798 rdev->pm.power_state[state_index].flags = 0;
2799 state_index++;
2800 }
2801 }
2802 }
2803
2804 rdev->pm.num_power_states = state_index;
2805
2806 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2807 rdev->pm.current_clock_mode_index = 0;
2808 if (rdev->pm.default_power_state_index >= 0)
2809 rdev->pm.current_vddc =
2810 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2811 else
2812 rdev->pm.current_vddc = 0;
2813}
2814
2815union get_clock_dividers {
2816 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2817 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2818 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2819 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2820 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2821 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2822 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2823};
2824
2825int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2826 u8 clock_type,
2827 u32 clock,
2828 bool strobe_mode,
2829 struct atom_clock_dividers *dividers)
2830{
2831 union get_clock_dividers args;
2832 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2833 u8 frev, crev;
2834
2835 memset(&args, 0, sizeof(args));
2836 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2837
2838 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2839 return -EINVAL;
2840
2841 switch (crev) {
2842 case 1:
2843 /* r4xx, r5xx */
2844 args.v1.ucAction = clock_type;
2845 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
2846
2847 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2848
2849 dividers->post_div = args.v1.ucPostDiv;
2850 dividers->fb_div = args.v1.ucFbDiv;
2851 dividers->enable_post_div = true;
2852 break;
2853 case 2:
2854 case 3:
2855 case 5:
2856 /* r6xx, r7xx, evergreen, ni, si */
2857 if (rdev->family <= CHIP_RV770) {
2858 args.v2.ucAction = clock_type;
2859 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
2860
2861 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2862
2863 dividers->post_div = args.v2.ucPostDiv;
2864 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2865 dividers->ref_div = args.v2.ucAction;
2866 if (rdev->family == CHIP_RV770) {
2867 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2868 true : false;
2869 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2870 } else
2871 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2872 } else {
2873 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2874 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2875
2876 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2877
2878 dividers->post_div = args.v3.ucPostDiv;
2879 dividers->enable_post_div = (args.v3.ucCntlFlag &
2880 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2881 dividers->enable_dithen = (args.v3.ucCntlFlag &
2882 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2883 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2884 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2885 dividers->ref_div = args.v3.ucRefDiv;
2886 dividers->vco_mode = (args.v3.ucCntlFlag &
2887 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2888 } else {
2889 /* for SI we use ComputeMemoryClockParam for memory plls */
2890 if (rdev->family >= CHIP_TAHITI)
2891 return -EINVAL;
2892 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2893 if (strobe_mode)
2894 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2895
2896 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2897
2898 dividers->post_div = args.v5.ucPostDiv;
2899 dividers->enable_post_div = (args.v5.ucCntlFlag &
2900 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2901 dividers->enable_dithen = (args.v5.ucCntlFlag &
2902 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2903 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2904 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2905 dividers->ref_div = args.v5.ucRefDiv;
2906 dividers->vco_mode = (args.v5.ucCntlFlag &
2907 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2908 }
2909 }
2910 break;
2911 case 4:
2912 /* fusion */
2913 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
2914
2915 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2916
2917 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2918 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2919 break;
2920 case 6:
2921 /* CI */
2922 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2923 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2924 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2925
2926 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2927
2928 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2929 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2930 dividers->ref_div = args.v6_out.ucPllRefDiv;
2931 dividers->post_div = args.v6_out.ucPllPostDiv;
2932 dividers->flags = args.v6_out.ucPllCntlFlag;
2933 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2934 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2935 break;
2936 default:
2937 return -EINVAL;
2938 }
2939 return 0;
2940}
2941
2942int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2943 u32 clock,
2944 bool strobe_mode,
2945 struct atom_mpll_param *mpll_param)
2946{
2947 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2948 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2949 u8 frev, crev;
2950
2951 memset(&args, 0, sizeof(args));
2952 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2953
2954 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2955 return -EINVAL;
2956
2957 switch (frev) {
2958 case 2:
2959 switch (crev) {
2960 case 1:
2961 /* SI */
2962 args.ulClock = cpu_to_le32(clock); /* 10 khz */
2963 args.ucInputFlag = 0;
2964 if (strobe_mode)
2965 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2966
2967 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2968
2969 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2970 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2971 mpll_param->post_div = args.ucPostDiv;
2972 mpll_param->dll_speed = args.ucDllSpeed;
2973 mpll_param->bwcntl = args.ucBWCntl;
2974 mpll_param->vco_mode =
2975 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
2976 mpll_param->yclk_sel =
2977 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2978 mpll_param->qdr =
2979 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2980 mpll_param->half_rate =
2981 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
2982 break;
2983 default:
2984 return -EINVAL;
2985 }
2986 break;
2987 default:
2988 return -EINVAL;
2989 }
2990 return 0;
2991}
2992
2993void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2994{
2995 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2996 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2997
2998 args.ucEnable = enable;
2999
3000 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3001}
3002
3003uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
3004{
3005 GET_ENGINE_CLOCK_PS_ALLOCATION args;
3006 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
3007
3008 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3009 return le32_to_cpu(args.ulReturnEngineClock);
3010}
3011
3012uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
3013{
3014 GET_MEMORY_CLOCK_PS_ALLOCATION args;
3015 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
3016
3017 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3018 return le32_to_cpu(args.ulReturnMemoryClock);
3019}
3020
3021void radeon_atom_set_engine_clock(struct radeon_device *rdev,
3022 uint32_t eng_clock)
3023{
3024 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3025 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
3026
3027 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
3028
3029 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3030}
3031
3032void radeon_atom_set_memory_clock(struct radeon_device *rdev,
3033 uint32_t mem_clock)
3034{
3035 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3036 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
3037
3038 if (rdev->flags & RADEON_IS_IGP)
3039 return;
3040
3041 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
3042
3043 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3044}
3045
3046void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
3047 u32 eng_clock, u32 mem_clock)
3048{
3049 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3050 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3051 u32 tmp;
3052
3053 memset(&args, 0, sizeof(args));
3054
3055 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
3056 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
3057
3058 args.ulTargetEngineClock = cpu_to_le32(tmp);
3059 if (mem_clock)
3060 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
3061
3062 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3063}
3064
3065void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3066 u32 mem_clock)
3067{
3068 u32 args;
3069 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3070
3071 args = cpu_to_le32(mem_clock); /* 10 khz */
3072
3073 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3074}
3075
3076void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3077 u32 mem_clock)
3078{
3079 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3080 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3081 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
3082
3083 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */
3084
3085 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3086}
3087
3088union set_voltage {
3089 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
3090 struct _SET_VOLTAGE_PARAMETERS v1;
3091 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
3092 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
3093};
3094
3095void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3096{
3097 union set_voltage args;
3098 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3099 u8 frev, crev, volt_index = voltage_level;
3100
3101 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3102 return;
3103
3104 /* 0xff01 is a flag rather then an actual voltage */
3105 if (voltage_level == 0xff01)
3106 return;
3107
3108 switch (crev) {
3109 case 1:
3110 args.v1.ucVoltageType = voltage_type;
3111 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3112 args.v1.ucVoltageIndex = volt_index;
3113 break;
3114 case 2:
3115 args.v2.ucVoltageType = voltage_type;
3116 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3117 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3118 break;
3119 case 3:
3120 args.v3.ucVoltageType = voltage_type;
3121 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3122 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3123 break;
3124 default:
3125 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3126 return;
3127 }
3128
3129 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3130}
3131
3132int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3133 u16 voltage_id, u16 *voltage)
3134{
3135 union set_voltage args;
3136 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3137 u8 frev, crev;
3138
3139 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3140 return -EINVAL;
3141
3142 switch (crev) {
3143 case 1:
3144 return -EINVAL;
3145 case 2:
3146 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3147 args.v2.ucVoltageMode = 0;
3148 args.v2.usVoltageLevel = 0;
3149
3150 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3151
3152 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3153 break;
3154 case 3:
3155 args.v3.ucVoltageType = voltage_type;
3156 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3157 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3158
3159 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3160
3161 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3162 break;
3163 default:
3164 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3165 return -EINVAL;
3166 }
3167
3168 return 0;
3169}
3170
3171int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3172 u16 *voltage,
3173 u16 leakage_idx)
3174{
3175 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3176}
3177
3178int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3179 u16 *leakage_id)
3180{
3181 union set_voltage args;
3182 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3183 u8 frev, crev;
3184
3185 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3186 return -EINVAL;
3187
3188 switch (crev) {
3189 case 3:
3190 case 4:
3191 args.v3.ucVoltageType = 0;
3192 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
3193 args.v3.usVoltageLevel = 0;
3194
3195 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3196
3197 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
3198 break;
3199 default:
3200 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3201 return -EINVAL;
3202 }
3203
3204 return 0;
3205}
3206
3207int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3208 u16 *vddc, u16 *vddci,
3209 u16 virtual_voltage_id,
3210 u16 vbios_voltage_id)
3211{
3212 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
3213 u8 frev, crev;
3214 u16 data_offset, size;
3215 int i, j;
3216 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
3217 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
3218
3219 *vddc = 0;
3220 *vddci = 0;
3221
3222 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3223 &frev, &crev, &data_offset))
3224 return -EINVAL;
3225
3226 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
3227 (rdev->mode_info.atom_context->bios + data_offset);
3228
3229 switch (frev) {
3230 case 1:
3231 return -EINVAL;
3232 case 2:
3233 switch (crev) {
3234 case 1:
3235 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
3236 return -EINVAL;
3237 leakage_bin = (u16 *)
3238 (rdev->mode_info.atom_context->bios + data_offset +
3239 le16_to_cpu(profile->usLeakageBinArrayOffset));
3240 vddc_id_buf = (u16 *)
3241 (rdev->mode_info.atom_context->bios + data_offset +
3242 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
3243 vddc_buf = (u16 *)
3244 (rdev->mode_info.atom_context->bios + data_offset +
3245 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
3246 vddci_id_buf = (u16 *)
3247 (rdev->mode_info.atom_context->bios + data_offset +
3248 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
3249 vddci_buf = (u16 *)
3250 (rdev->mode_info.atom_context->bios + data_offset +
3251 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
3252
3253 if (profile->ucElbVDDC_Num > 0) {
3254 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
3255 if (vddc_id_buf[i] == virtual_voltage_id) {
3256 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3257 if (vbios_voltage_id <= leakage_bin[j]) {
3258 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
3259 break;
3260 }
3261 }
3262 break;
3263 }
3264 }
3265 }
3266 if (profile->ucElbVDDCI_Num > 0) {
3267 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
3268 if (vddci_id_buf[i] == virtual_voltage_id) {
3269 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3270 if (vbios_voltage_id <= leakage_bin[j]) {
3271 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
3272 break;
3273 }
3274 }
3275 break;
3276 }
3277 }
3278 }
3279 break;
3280 default:
3281 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3282 return -EINVAL;
3283 }
3284 break;
3285 default:
3286 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3287 return -EINVAL;
3288 }
3289
3290 return 0;
3291}
3292
3293union get_voltage_info {
3294 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
3295 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
3296};
3297
3298int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
3299 u16 virtual_voltage_id,
3300 u16 *voltage)
3301{
3302 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
3303 u32 entry_id;
3304 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
3305 union get_voltage_info args;
3306
3307 for (entry_id = 0; entry_id < count; entry_id++) {
3308 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
3309 virtual_voltage_id)
3310 break;
3311 }
3312
3313 if (entry_id >= count)
3314 return -EINVAL;
3315
3316 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
3317 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
3318 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
3319 args.in.ulSCLKFreq =
3320 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
3321
3322 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3323
3324 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
3325
3326 return 0;
3327}
3328
3329int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3330 u16 voltage_level, u8 voltage_type,
3331 u32 *gpio_value, u32 *gpio_mask)
3332{
3333 union set_voltage args;
3334 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3335 u8 frev, crev;
3336
3337 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3338 return -EINVAL;
3339
3340 switch (crev) {
3341 case 1:
3342 return -EINVAL;
3343 case 2:
3344 args.v2.ucVoltageType = voltage_type;
3345 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3346 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3347
3348 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3349
3350 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3351
3352 args.v2.ucVoltageType = voltage_type;
3353 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3354 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3355
3356 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3357
3358 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3359 break;
3360 default:
3361 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3362 return -EINVAL;
3363 }
3364
3365 return 0;
3366}
3367
3368union voltage_object_info {
3369 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3370 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3371 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3372};
3373
3374union voltage_object {
3375 struct _ATOM_VOLTAGE_OBJECT v1;
3376 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3377 union _ATOM_VOLTAGE_OBJECT_V3 v3;
3378};
3379
3380static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3381 u8 voltage_type)
3382{
3383 u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3384 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3385 u8 *start = (u8 *)v1;
3386
3387 while (offset < size) {
3388 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3389 if (vo->ucVoltageType == voltage_type)
3390 return vo;
3391 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3392 vo->asFormula.ucNumOfVoltageEntries;
3393 }
3394 return NULL;
3395}
3396
3397static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3398 u8 voltage_type)
3399{
3400 u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3401 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3402 u8 *start = (u8*)v2;
3403
3404 while (offset < size) {
3405 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3406 if (vo->ucVoltageType == voltage_type)
3407 return vo;
3408 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3409 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3410 }
3411 return NULL;
3412}
3413
3414static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3415 u8 voltage_type, u8 voltage_mode)
3416{
3417 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3418 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3419 u8 *start = (u8*)v3;
3420
3421 while (offset < size) {
3422 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3423 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3424 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3425 return vo;
3426 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3427 }
3428 return NULL;
3429}
3430
3431bool
3432radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3433 u8 voltage_type, u8 voltage_mode)
3434{
3435 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3436 u8 frev, crev;
3437 u16 data_offset, size;
3438 union voltage_object_info *voltage_info;
3439 union voltage_object *voltage_object = NULL;
3440
3441 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3442 &frev, &crev, &data_offset)) {
3443 voltage_info = (union voltage_object_info *)
3444 (rdev->mode_info.atom_context->bios + data_offset);
3445
3446 switch (frev) {
3447 case 1:
3448 case 2:
3449 switch (crev) {
3450 case 1:
3451 voltage_object = (union voltage_object *)
3452 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3453 if (voltage_object &&
3454 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3455 return true;
3456 break;
3457 case 2:
3458 voltage_object = (union voltage_object *)
3459 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3460 if (voltage_object &&
3461 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3462 return true;
3463 break;
3464 default:
3465 DRM_ERROR("unknown voltage object table\n");
3466 return false;
3467 }
3468 break;
3469 case 3:
3470 switch (crev) {
3471 case 1:
3472 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3473 voltage_type, voltage_mode))
3474 return true;
3475 break;
3476 default:
3477 DRM_ERROR("unknown voltage object table\n");
3478 return false;
3479 }
3480 break;
3481 default:
3482 DRM_ERROR("unknown voltage object table\n");
3483 return false;
3484 }
3485
3486 }
3487 return false;
3488}
3489
3490int radeon_atom_get_svi2_info(struct radeon_device *rdev,
3491 u8 voltage_type,
3492 u8 *svd_gpio_id, u8 *svc_gpio_id)
3493{
3494 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3495 u8 frev, crev;
3496 u16 data_offset, size;
3497 union voltage_object_info *voltage_info;
3498 union voltage_object *voltage_object = NULL;
3499
3500 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3501 &frev, &crev, &data_offset)) {
3502 voltage_info = (union voltage_object_info *)
3503 (rdev->mode_info.atom_context->bios + data_offset);
3504
3505 switch (frev) {
3506 case 3:
3507 switch (crev) {
3508 case 1:
3509 voltage_object = (union voltage_object *)
3510 atom_lookup_voltage_object_v3(&voltage_info->v3,
3511 voltage_type,
3512 VOLTAGE_OBJ_SVID2);
3513 if (voltage_object) {
3514 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
3515 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
3516 } else {
3517 return -EINVAL;
3518 }
3519 break;
3520 default:
3521 DRM_ERROR("unknown voltage object table\n");
3522 return -EINVAL;
3523 }
3524 break;
3525 default:
3526 DRM_ERROR("unknown voltage object table\n");
3527 return -EINVAL;
3528 }
3529
3530 }
3531 return 0;
3532}
3533
3534int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3535 u8 voltage_type, u16 *max_voltage)
3536{
3537 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3538 u8 frev, crev;
3539 u16 data_offset, size;
3540 union voltage_object_info *voltage_info;
3541 union voltage_object *voltage_object = NULL;
3542
3543 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3544 &frev, &crev, &data_offset)) {
3545 voltage_info = (union voltage_object_info *)
3546 (rdev->mode_info.atom_context->bios + data_offset);
3547
3548 switch (crev) {
3549 case 1:
3550 voltage_object = (union voltage_object *)
3551 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3552 if (voltage_object) {
3553 ATOM_VOLTAGE_FORMULA *formula =
3554 &voltage_object->v1.asFormula;
3555 if (formula->ucFlag & 1)
3556 *max_voltage =
3557 le16_to_cpu(formula->usVoltageBaseLevel) +
3558 formula->ucNumOfVoltageEntries / 2 *
3559 le16_to_cpu(formula->usVoltageStep);
3560 else
3561 *max_voltage =
3562 le16_to_cpu(formula->usVoltageBaseLevel) +
3563 (formula->ucNumOfVoltageEntries - 1) *
3564 le16_to_cpu(formula->usVoltageStep);
3565 return 0;
3566 }
3567 break;
3568 case 2:
3569 voltage_object = (union voltage_object *)
3570 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3571 if (voltage_object) {
3572 ATOM_VOLTAGE_FORMULA_V2 *formula =
3573 &voltage_object->v2.asFormula;
3574 if (formula->ucNumOfVoltageEntries) {
3575 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *)
3576 ((u8 *)&formula->asVIDAdjustEntries[0] +
3577 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
3578 *max_voltage =
3579 le16_to_cpu(lut->usVoltageValue);
3580 return 0;
3581 }
3582 }
3583 break;
3584 default:
3585 DRM_ERROR("unknown voltage object table\n");
3586 return -EINVAL;
3587 }
3588
3589 }
3590 return -EINVAL;
3591}
3592
3593int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3594 u8 voltage_type, u16 *min_voltage)
3595{
3596 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3597 u8 frev, crev;
3598 u16 data_offset, size;
3599 union voltage_object_info *voltage_info;
3600 union voltage_object *voltage_object = NULL;
3601
3602 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3603 &frev, &crev, &data_offset)) {
3604 voltage_info = (union voltage_object_info *)
3605 (rdev->mode_info.atom_context->bios + data_offset);
3606
3607 switch (crev) {
3608 case 1:
3609 voltage_object = (union voltage_object *)
3610 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3611 if (voltage_object) {
3612 ATOM_VOLTAGE_FORMULA *formula =
3613 &voltage_object->v1.asFormula;
3614 *min_voltage =
3615 le16_to_cpu(formula->usVoltageBaseLevel);
3616 return 0;
3617 }
3618 break;
3619 case 2:
3620 voltage_object = (union voltage_object *)
3621 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3622 if (voltage_object) {
3623 ATOM_VOLTAGE_FORMULA_V2 *formula =
3624 &voltage_object->v2.asFormula;
3625 if (formula->ucNumOfVoltageEntries) {
3626 *min_voltage =
3627 le16_to_cpu(formula->asVIDAdjustEntries[
3628 0
3629 ].usVoltageValue);
3630 return 0;
3631 }
3632 }
3633 break;
3634 default:
3635 DRM_ERROR("unknown voltage object table\n");
3636 return -EINVAL;
3637 }
3638
3639 }
3640 return -EINVAL;
3641}
3642
3643int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3644 u8 voltage_type, u16 *voltage_step)
3645{
3646 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3647 u8 frev, crev;
3648 u16 data_offset, size;
3649 union voltage_object_info *voltage_info;
3650 union voltage_object *voltage_object = NULL;
3651
3652 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3653 &frev, &crev, &data_offset)) {
3654 voltage_info = (union voltage_object_info *)
3655 (rdev->mode_info.atom_context->bios + data_offset);
3656
3657 switch (crev) {
3658 case 1:
3659 voltage_object = (union voltage_object *)
3660 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3661 if (voltage_object) {
3662 ATOM_VOLTAGE_FORMULA *formula =
3663 &voltage_object->v1.asFormula;
3664 if (formula->ucFlag & 1)
3665 *voltage_step =
3666 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3667 else
3668 *voltage_step =
3669 le16_to_cpu(formula->usVoltageStep);
3670 return 0;
3671 }
3672 break;
3673 case 2:
3674 return -EINVAL;
3675 default:
3676 DRM_ERROR("unknown voltage object table\n");
3677 return -EINVAL;
3678 }
3679
3680 }
3681 return -EINVAL;
3682}
3683
3684int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3685 u8 voltage_type,
3686 u16 nominal_voltage,
3687 u16 *true_voltage)
3688{
3689 u16 min_voltage, max_voltage, voltage_step;
3690
3691 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3692 return -EINVAL;
3693 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3694 return -EINVAL;
3695 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3696 return -EINVAL;
3697
3698 if (nominal_voltage <= min_voltage)
3699 *true_voltage = min_voltage;
3700 else if (nominal_voltage >= max_voltage)
3701 *true_voltage = max_voltage;
3702 else
3703 *true_voltage = min_voltage +
3704 ((nominal_voltage - min_voltage) / voltage_step) *
3705 voltage_step;
3706
3707 return 0;
3708}
3709
3710int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3711 u8 voltage_type, u8 voltage_mode,
3712 struct atom_voltage_table *voltage_table)
3713{
3714 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3715 u8 frev, crev;
3716 u16 data_offset, size;
3717 int i, ret;
3718 union voltage_object_info *voltage_info;
3719 union voltage_object *voltage_object = NULL;
3720
3721 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3722 &frev, &crev, &data_offset)) {
3723 voltage_info = (union voltage_object_info *)
3724 (rdev->mode_info.atom_context->bios + data_offset);
3725
3726 switch (frev) {
3727 case 1:
3728 case 2:
3729 switch (crev) {
3730 case 1:
3731 DRM_ERROR("old table version %d, %d\n", frev, crev);
3732 return -EINVAL;
3733 case 2:
3734 voltage_object = (union voltage_object *)
3735 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3736 if (voltage_object) {
3737 ATOM_VOLTAGE_FORMULA_V2 *formula =
3738 &voltage_object->v2.asFormula;
3739 VOLTAGE_LUT_ENTRY *lut;
3740 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3741 return -EINVAL;
3742 lut = &formula->asVIDAdjustEntries[0];
3743 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3744 voltage_table->entries[i].value =
3745 le16_to_cpu(lut->usVoltageValue);
3746 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3747 voltage_table->entries[i].value,
3748 voltage_type,
3749 &voltage_table->entries[i].smio_low,
3750 &voltage_table->mask_low);
3751 if (ret)
3752 return ret;
3753 lut = (VOLTAGE_LUT_ENTRY *)
3754 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
3755 }
3756 voltage_table->count = formula->ucNumOfVoltageEntries;
3757 return 0;
3758 }
3759 break;
3760 default:
3761 DRM_ERROR("unknown voltage object table\n");
3762 return -EINVAL;
3763 }
3764 break;
3765 case 3:
3766 switch (crev) {
3767 case 1:
3768 voltage_object = (union voltage_object *)
3769 atom_lookup_voltage_object_v3(&voltage_info->v3,
3770 voltage_type, voltage_mode);
3771 if (voltage_object) {
3772 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3773 &voltage_object->v3.asGpioVoltageObj;
3774 VOLTAGE_LUT_ENTRY_V2 *lut;
3775 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3776 return -EINVAL;
3777 lut = &gpio->asVolGpioLut[0];
3778 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3779 voltage_table->entries[i].value =
3780 le16_to_cpu(lut->usVoltageValue);
3781 voltage_table->entries[i].smio_low =
3782 le32_to_cpu(lut->ulVoltageId);
3783 lut = (VOLTAGE_LUT_ENTRY_V2 *)
3784 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
3785 }
3786 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3787 voltage_table->count = gpio->ucGpioEntryNum;
3788 voltage_table->phase_delay = gpio->ucPhaseDelay;
3789 return 0;
3790 }
3791 break;
3792 default:
3793 DRM_ERROR("unknown voltage object table\n");
3794 return -EINVAL;
3795 }
3796 break;
3797 default:
3798 DRM_ERROR("unknown voltage object table\n");
3799 return -EINVAL;
3800 }
3801 }
3802 return -EINVAL;
3803}
3804
3805union vram_info {
3806 struct _ATOM_VRAM_INFO_V3 v1_3;
3807 struct _ATOM_VRAM_INFO_V4 v1_4;
3808 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3809};
3810
3811int radeon_atom_get_memory_info(struct radeon_device *rdev,
3812 u8 module_index, struct atom_memory_info *mem_info)
3813{
3814 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3815 u8 frev, crev, i;
3816 u16 data_offset, size;
3817 union vram_info *vram_info;
3818
3819 memset(mem_info, 0, sizeof(struct atom_memory_info));
3820
3821 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3822 &frev, &crev, &data_offset)) {
3823 vram_info = (union vram_info *)
3824 (rdev->mode_info.atom_context->bios + data_offset);
3825 switch (frev) {
3826 case 1:
3827 switch (crev) {
3828 case 3:
3829 /* r6xx */
3830 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3831 ATOM_VRAM_MODULE_V3 *vram_module =
3832 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3833
3834 for (i = 0; i < module_index; i++) {
3835 if (le16_to_cpu(vram_module->usSize) == 0)
3836 return -EINVAL;
3837 vram_module = (ATOM_VRAM_MODULE_V3 *)
3838 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3839 }
3840 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3841 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3842 } else
3843 return -EINVAL;
3844 break;
3845 case 4:
3846 /* r7xx, evergreen */
3847 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3848 ATOM_VRAM_MODULE_V4 *vram_module =
3849 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3850
3851 for (i = 0; i < module_index; i++) {
3852 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3853 return -EINVAL;
3854 vram_module = (ATOM_VRAM_MODULE_V4 *)
3855 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3856 }
3857 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3858 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3859 } else
3860 return -EINVAL;
3861 break;
3862 default:
3863 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3864 return -EINVAL;
3865 }
3866 break;
3867 case 2:
3868 switch (crev) {
3869 case 1:
3870 /* ni */
3871 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3872 ATOM_VRAM_MODULE_V7 *vram_module =
3873 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3874
3875 for (i = 0; i < module_index; i++) {
3876 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3877 return -EINVAL;
3878 vram_module = (ATOM_VRAM_MODULE_V7 *)
3879 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3880 }
3881 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3882 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3883 } else
3884 return -EINVAL;
3885 break;
3886 default:
3887 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3888 return -EINVAL;
3889 }
3890 break;
3891 default:
3892 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3893 return -EINVAL;
3894 }
3895 return 0;
3896 }
3897 return -EINVAL;
3898}
3899
3900int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3901 bool gddr5, u8 module_index,
3902 struct atom_memory_clock_range_table *mclk_range_table)
3903{
3904 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3905 u8 frev, crev, i;
3906 u16 data_offset, size;
3907 union vram_info *vram_info;
3908 u32 mem_timing_size = gddr5 ?
3909 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3910
3911 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3912
3913 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3914 &frev, &crev, &data_offset)) {
3915 vram_info = (union vram_info *)
3916 (rdev->mode_info.atom_context->bios + data_offset);
3917 switch (frev) {
3918 case 1:
3919 switch (crev) {
3920 case 3:
3921 DRM_ERROR("old table version %d, %d\n", frev, crev);
3922 return -EINVAL;
3923 case 4:
3924 /* r7xx, evergreen */
3925 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3926 ATOM_VRAM_MODULE_V4 *vram_module =
3927 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3928 ATOM_MEMORY_TIMING_FORMAT *format;
3929
3930 for (i = 0; i < module_index; i++) {
3931 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3932 return -EINVAL;
3933 vram_module = (ATOM_VRAM_MODULE_V4 *)
3934 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3935 }
3936 mclk_range_table->num_entries = (u8)
3937 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3938 mem_timing_size);
3939 format = &vram_module->asMemTiming[0];
3940 for (i = 0; i < mclk_range_table->num_entries; i++) {
3941 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3942 format = (ATOM_MEMORY_TIMING_FORMAT *)
3943 ((u8 *)format + mem_timing_size);
3944 }
3945 } else
3946 return -EINVAL;
3947 break;
3948 default:
3949 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3950 return -EINVAL;
3951 }
3952 break;
3953 case 2:
3954 DRM_ERROR("new table version %d, %d\n", frev, crev);
3955 return -EINVAL;
3956 default:
3957 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3958 return -EINVAL;
3959 }
3960 return 0;
3961 }
3962 return -EINVAL;
3963}
3964
3965#define MEM_ID_MASK 0xff000000
3966#define MEM_ID_SHIFT 24
3967#define CLOCK_RANGE_MASK 0x00ffffff
3968#define CLOCK_RANGE_SHIFT 0
3969#define LOW_NIBBLE_MASK 0xf
3970#define DATA_EQU_PREV 0
3971#define DATA_FROM_TABLE 4
3972
3973int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3974 u8 module_index,
3975 struct atom_mc_reg_table *reg_table)
3976{
3977 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3978 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3979 u32 i = 0, j;
3980 u16 data_offset, size;
3981 union vram_info *vram_info;
3982
3983 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
3984
3985 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3986 &frev, &crev, &data_offset)) {
3987 vram_info = (union vram_info *)
3988 (rdev->mode_info.atom_context->bios + data_offset);
3989 switch (frev) {
3990 case 1:
3991 DRM_ERROR("old table version %d, %d\n", frev, crev);
3992 return -EINVAL;
3993 case 2:
3994 switch (crev) {
3995 case 1:
3996 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3997 ATOM_INIT_REG_BLOCK *reg_block =
3998 (ATOM_INIT_REG_BLOCK *)
3999 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
4000 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
4001 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4002 ((u8 *)reg_block + (2 * sizeof(u16)) +
4003 le16_to_cpu(reg_block->usRegIndexTblSize));
4004 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
4005 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
4006 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
4007 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
4008 return -EINVAL;
4009 while (i < num_entries) {
4010 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
4011 break;
4012 reg_table->mc_reg_address[i].s1 =
4013 (u16)(le16_to_cpu(format->usRegIndex));
4014 reg_table->mc_reg_address[i].pre_reg_data =
4015 (u8)(format->ucPreRegDataLength);
4016 i++;
4017 format = (ATOM_INIT_REG_INDEX_FORMAT *)
4018 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
4019 }
4020 reg_table->last = i;
4021 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
4022 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
4023 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
4024 >> MEM_ID_SHIFT);
4025 if (module_index == t_mem_id) {
4026 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
4027 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
4028 >> CLOCK_RANGE_SHIFT);
4029 for (i = 0, j = 1; i < reg_table->last; i++) {
4030 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
4031 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4032 (u32)le32_to_cpu(*((u32 *)reg_data + j));
4033 j++;
4034 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
4035 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4036 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
4037 }
4038 }
4039 num_ranges++;
4040 }
4041 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4042 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
4043 }
4044 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
4045 return -EINVAL;
4046 reg_table->num_entries = num_ranges;
4047 } else
4048 return -EINVAL;
4049 break;
4050 default:
4051 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4052 return -EINVAL;
4053 }
4054 break;
4055 default:
4056 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4057 return -EINVAL;
4058 }
4059 return 0;
4060 }
4061 return -EINVAL;
4062}
4063
4064void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
4065{
4066 struct radeon_device *rdev = dev->dev_private;
4067 uint32_t bios_2_scratch, bios_6_scratch;
4068
4069 if (rdev->family >= CHIP_R600) {
4070 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4071 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4072 } else {
4073 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4074 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4075 }
4076
4077 /* let the bios control the backlight */
4078 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
4079
4080 /* tell the bios not to handle mode switching */
4081 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
4082
4083 /* clear the vbios dpms state */
4084 if (ASIC_IS_DCE4(rdev))
4085 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
4086
4087 if (rdev->family >= CHIP_R600) {
4088 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4089 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4090 } else {
4091 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4092 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4093 }
4094
4095}
4096
4097void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
4098{
4099 uint32_t scratch_reg;
4100 int i;
4101
4102 if (rdev->family >= CHIP_R600)
4103 scratch_reg = R600_BIOS_0_SCRATCH;
4104 else
4105 scratch_reg = RADEON_BIOS_0_SCRATCH;
4106
4107 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4108 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
4109}
4110
4111void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
4112{
4113 uint32_t scratch_reg;
4114 int i;
4115
4116 if (rdev->family >= CHIP_R600)
4117 scratch_reg = R600_BIOS_0_SCRATCH;
4118 else
4119 scratch_reg = RADEON_BIOS_0_SCRATCH;
4120
4121 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4122 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
4123}
4124
4125void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
4126{
4127 struct drm_device *dev = encoder->dev;
4128 struct radeon_device *rdev = dev->dev_private;
4129 uint32_t bios_6_scratch;
4130
4131 if (rdev->family >= CHIP_R600)
4132 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4133 else
4134 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4135
4136 if (lock) {
4137 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
4138 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
4139 } else {
4140 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
4141 bios_6_scratch |= ATOM_S6_ACC_MODE;
4142 }
4143
4144 if (rdev->family >= CHIP_R600)
4145 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4146 else
4147 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4148}
4149
4150/* at some point we may want to break this out into individual functions */
4151void
4152radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
4153 struct drm_encoder *encoder,
4154 bool connected)
4155{
4156 struct drm_device *dev = connector->dev;
4157 struct radeon_device *rdev = dev->dev_private;
4158 struct radeon_connector *radeon_connector =
4159 to_radeon_connector(connector);
4160 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4161 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
4162
4163 if (rdev->family >= CHIP_R600) {
4164 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
4165 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4166 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4167 } else {
4168 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
4169 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4170 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4171 }
4172
4173 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
4174 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
4175 if (connected) {
4176 DRM_DEBUG_KMS("TV1 connected\n");
4177 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
4178 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
4179 } else {
4180 DRM_DEBUG_KMS("TV1 disconnected\n");
4181 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
4182 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
4183 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
4184 }
4185 }
4186 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
4187 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
4188 if (connected) {
4189 DRM_DEBUG_KMS("CV connected\n");
4190 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
4191 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
4192 } else {
4193 DRM_DEBUG_KMS("CV disconnected\n");
4194 bios_0_scratch &= ~ATOM_S0_CV_MASK;
4195 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
4196 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
4197 }
4198 }
4199 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
4200 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
4201 if (connected) {
4202 DRM_DEBUG_KMS("LCD1 connected\n");
4203 bios_0_scratch |= ATOM_S0_LCD1;
4204 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
4205 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
4206 } else {
4207 DRM_DEBUG_KMS("LCD1 disconnected\n");
4208 bios_0_scratch &= ~ATOM_S0_LCD1;
4209 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
4210 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
4211 }
4212 }
4213 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
4214 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
4215 if (connected) {
4216 DRM_DEBUG_KMS("CRT1 connected\n");
4217 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
4218 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
4219 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
4220 } else {
4221 DRM_DEBUG_KMS("CRT1 disconnected\n");
4222 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
4223 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
4224 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
4225 }
4226 }
4227 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
4228 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
4229 if (connected) {
4230 DRM_DEBUG_KMS("CRT2 connected\n");
4231 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
4232 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
4233 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
4234 } else {
4235 DRM_DEBUG_KMS("CRT2 disconnected\n");
4236 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
4237 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
4238 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
4239 }
4240 }
4241 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
4242 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
4243 if (connected) {
4244 DRM_DEBUG_KMS("DFP1 connected\n");
4245 bios_0_scratch |= ATOM_S0_DFP1;
4246 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
4247 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
4248 } else {
4249 DRM_DEBUG_KMS("DFP1 disconnected\n");
4250 bios_0_scratch &= ~ATOM_S0_DFP1;
4251 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
4252 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
4253 }
4254 }
4255 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
4256 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
4257 if (connected) {
4258 DRM_DEBUG_KMS("DFP2 connected\n");
4259 bios_0_scratch |= ATOM_S0_DFP2;
4260 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
4261 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
4262 } else {
4263 DRM_DEBUG_KMS("DFP2 disconnected\n");
4264 bios_0_scratch &= ~ATOM_S0_DFP2;
4265 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
4266 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
4267 }
4268 }
4269 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
4270 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
4271 if (connected) {
4272 DRM_DEBUG_KMS("DFP3 connected\n");
4273 bios_0_scratch |= ATOM_S0_DFP3;
4274 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
4275 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
4276 } else {
4277 DRM_DEBUG_KMS("DFP3 disconnected\n");
4278 bios_0_scratch &= ~ATOM_S0_DFP3;
4279 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
4280 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
4281 }
4282 }
4283 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
4284 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
4285 if (connected) {
4286 DRM_DEBUG_KMS("DFP4 connected\n");
4287 bios_0_scratch |= ATOM_S0_DFP4;
4288 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
4289 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
4290 } else {
4291 DRM_DEBUG_KMS("DFP4 disconnected\n");
4292 bios_0_scratch &= ~ATOM_S0_DFP4;
4293 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
4294 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
4295 }
4296 }
4297 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
4298 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
4299 if (connected) {
4300 DRM_DEBUG_KMS("DFP5 connected\n");
4301 bios_0_scratch |= ATOM_S0_DFP5;
4302 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
4303 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
4304 } else {
4305 DRM_DEBUG_KMS("DFP5 disconnected\n");
4306 bios_0_scratch &= ~ATOM_S0_DFP5;
4307 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
4308 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
4309 }
4310 }
4311 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4312 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4313 if (connected) {
4314 DRM_DEBUG_KMS("DFP6 connected\n");
4315 bios_0_scratch |= ATOM_S0_DFP6;
4316 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4317 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4318 } else {
4319 DRM_DEBUG_KMS("DFP6 disconnected\n");
4320 bios_0_scratch &= ~ATOM_S0_DFP6;
4321 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4322 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4323 }
4324 }
4325
4326 if (rdev->family >= CHIP_R600) {
4327 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4328 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4329 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4330 } else {
4331 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4332 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4333 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4334 }
4335}
4336
4337void
4338radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4339{
4340 struct drm_device *dev = encoder->dev;
4341 struct radeon_device *rdev = dev->dev_private;
4342 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4343 uint32_t bios_3_scratch;
4344
4345 if (ASIC_IS_DCE4(rdev))
4346 return;
4347
4348 if (rdev->family >= CHIP_R600)
4349 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4350 else
4351 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4352
4353 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4354 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4355 bios_3_scratch |= (crtc << 18);
4356 }
4357 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4358 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4359 bios_3_scratch |= (crtc << 24);
4360 }
4361 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4362 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4363 bios_3_scratch |= (crtc << 16);
4364 }
4365 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4366 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4367 bios_3_scratch |= (crtc << 20);
4368 }
4369 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4370 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4371 bios_3_scratch |= (crtc << 17);
4372 }
4373 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4374 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4375 bios_3_scratch |= (crtc << 19);
4376 }
4377 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4378 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4379 bios_3_scratch |= (crtc << 23);
4380 }
4381 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4382 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4383 bios_3_scratch |= (crtc << 25);
4384 }
4385
4386 if (rdev->family >= CHIP_R600)
4387 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4388 else
4389 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4390}
4391
4392void
4393radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4394{
4395 struct drm_device *dev = encoder->dev;
4396 struct radeon_device *rdev = dev->dev_private;
4397 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4398 uint32_t bios_2_scratch;
4399
4400 if (ASIC_IS_DCE4(rdev))
4401 return;
4402
4403 if (rdev->family >= CHIP_R600)
4404 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4405 else
4406 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4407
4408 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4409 if (on)
4410 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4411 else
4412 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4413 }
4414 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4415 if (on)
4416 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4417 else
4418 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4419 }
4420 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4421 if (on)
4422 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4423 else
4424 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4425 }
4426 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4427 if (on)
4428 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4429 else
4430 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4431 }
4432 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4433 if (on)
4434 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4435 else
4436 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4437 }
4438 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4439 if (on)
4440 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4441 else
4442 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4443 }
4444 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4445 if (on)
4446 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4447 else
4448 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4449 }
4450 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4451 if (on)
4452 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4453 else
4454 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4455 }
4456 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4457 if (on)
4458 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4459 else
4460 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4461 }
4462 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4463 if (on)
4464 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4465 else
4466 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4467 }
4468
4469 if (rdev->family >= CHIP_R600)
4470 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4471 else
4472 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4473}