1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
  4 * Copyright (C) 2013, 2021 Intel Corporation
 
 
 
 
  5 */
  6
  7#ifndef SPI_PXA2XX_H
  8#define SPI_PXA2XX_H
  9
 
 10#include <linux/dmaengine.h>
 11#include <linux/irqreturn.h>
 12#include <linux/types.h>
 13#include <linux/sizes.h>
 14
 15#include <linux/pxa2xx_ssp.h>
 16
 17struct device;
 18struct gpio_desc;
 19
 20/*
 21 * The platform data for SSP controller devices
 22 * (resides in device.platform_data).
 23 */
 24struct pxa2xx_spi_controller {
 25	u8 num_chipselect;
 26	u8 enable_dma;
 27	u8 dma_burst_size;
 28	bool is_target;
 29
 30	/* DMA engine specific config */
 31	dma_filter_fn dma_filter;
 32	void *tx_param;
 33	void *rx_param;
 34
 35	/* For non-PXA arches */
 36	struct ssp_device ssp;
 37};
 38
 39struct spi_controller;
 40struct spi_device;
 41struct spi_transfer;
 42
 43struct driver_data {
 
 
 
 44	/* SSP Info */
 45	struct ssp_device *ssp;
 46
 47	/* SPI framework hookup */
 48	enum pxa_ssp_type ssp_type;
 49	struct spi_controller *controller;
 50
 51	/* PXA hookup */
 52	struct pxa2xx_spi_controller *controller_info;
 
 
 
 
 53
 54	/* SSP masks*/
 55	u32 dma_cr1;
 56	u32 int_cr1;
 57	u32 clear_sr;
 58	u32 mask_sr;
 59
 
 
 
 60	/* DMA engine support */
 61	atomic_t dma_running;
 62
 63	/* Current transfer state info */
 
 
 64	void *tx;
 65	void *tx_end;
 66	void *rx;
 67	void *rx_end;
 68	u8 n_bytes;
 69	int (*write)(struct driver_data *drv_data);
 70	int (*read)(struct driver_data *drv_data);
 71	irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
 
 72
 73	void __iomem *lpss_base;
 74
 75	/* Optional slave FIFO ready signal */
 76	struct gpio_desc *gpiod_ready;
 77};
 78
 79static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data, u32 reg)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 80{
 81	return pxa_ssp_read_reg(drv_data->ssp, reg);
 82}
 83
 84static inline void pxa2xx_spi_write(const struct driver_data *drv_data, u32 reg, u32 val)
 
 85{
 86	pxa_ssp_write_reg(drv_data->ssp, reg, val);
 87}
 88
 
 
 
 
 
 89#define DMA_ALIGNMENT		8
 90
 91static inline int pxa25x_ssp_comp(const struct driver_data *drv_data)
 92{
 93	switch (drv_data->ssp_type) {
 94	case PXA25x_SSP:
 95	case CE4100_SSP:
 96	case QUARK_X1000_SSP:
 97		return 1;
 98	default:
 99		return 0;
100	}
101}
102
103static inline void clear_SSCR1_bits(const struct driver_data *drv_data, u32 bits)
104{
105	pxa2xx_spi_write(drv_data, SSCR1, pxa2xx_spi_read(drv_data, SSCR1) & ~bits);
106}
107
108static inline u32 read_SSSR_bits(const struct driver_data *drv_data, u32 bits)
109{
110	return pxa2xx_spi_read(drv_data, SSSR) & bits;
111}
112
113static inline void write_SSSR_CS(const struct driver_data *drv_data, u32 val)
114{
115	if (drv_data->ssp_type == CE4100_SSP ||
116	    drv_data->ssp_type == QUARK_X1000_SSP)
117		val |= read_SSSR_bits(drv_data, SSSR_ALT_FRM_MASK);
118
119	pxa2xx_spi_write(drv_data, SSSR, val);
120}
121
122extern int pxa2xx_spi_flush(struct driver_data *drv_data);
 
123
124#define MAX_DMA_LEN		SZ_64K
125#define DEFAULT_DMA_CR1		(SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
126
127extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
128extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
129				  struct spi_transfer *xfer);
130extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
131extern void pxa2xx_spi_dma_stop(struct driver_data *drv_data);
132extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
133extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
134
135int pxa2xx_spi_probe(struct device *dev, struct ssp_device *ssp,
136		     struct pxa2xx_spi_controller *platform_info);
137void pxa2xx_spi_remove(struct device *dev);
138
139extern const struct dev_pm_ops pxa2xx_spi_pm_ops;
140
141#endif /* SPI_PXA2XX_H */

 
  1/*
  2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
  3 * Copyright (C) 2013, Intel Corporation
  4 *
  5 * This program is free software; you can redistribute it and/or modify
  6 * it under the terms of the GNU General Public License version 2 as
  7 * published by the Free Software Foundation.
  8 */
  9
 10#ifndef SPI_PXA2XX_H
 11#define SPI_PXA2XX_H
 12
 13#include <linux/atomic.h>
 14#include <linux/dmaengine.h>
 15#include <linux/errno.h>
 16#include <linux/io.h>
 17#include <linux/interrupt.h>
 18#include <linux/platform_device.h>
 19#include <linux/pxa2xx_ssp.h>
 20#include <linux/scatterlist.h>
 21#include <linux/sizes.h>
 22#include <linux/spi/spi.h>
 23#include <linux/spi/pxa2xx_spi.h>
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 24
 25struct driver_data {
 26	/* Driver model hookup */
 27	struct platform_device *pdev;
 28
 29	/* SSP Info */
 30	struct ssp_device *ssp;
 31
 32	/* SPI framework hookup */
 33	enum pxa_ssp_type ssp_type;
 34	struct spi_controller *master;
 35
 36	/* PXA hookup */
 37	struct pxa2xx_spi_master *master_info;
 38
 39	/* SSP register addresses */
 40	void __iomem *ioaddr;
 41	phys_addr_t ssdr_physical;
 42
 43	/* SSP masks*/
 44	u32 dma_cr1;
 45	u32 int_cr1;
 46	u32 clear_sr;
 47	u32 mask_sr;
 48
 49	/* Message Transfer pump */
 50	struct tasklet_struct pump_transfers;
 51
 52	/* DMA engine support */
 53	atomic_t dma_running;
 54
 55	/* Current message transfer state info */
 56	struct spi_transfer *cur_transfer;
 57	size_t len;
 58	void *tx;
 59	void *tx_end;
 60	void *rx;
 61	void *rx_end;
 62	u8 n_bytes;
 63	int (*write)(struct driver_data *drv_data);
 64	int (*read)(struct driver_data *drv_data);
 65	irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
 66	void (*cs_control)(u32 command);
 67
 68	void __iomem *lpss_base;
 69
 70	/* GPIOs for chip selects */
 71	struct gpio_desc **cs_gpiods;
 72};
 73
 74struct chip_data {
 75	u32 cr1;
 76	u32 dds_rate;
 77	u32 timeout;
 78	u8 n_bytes;
 79	u32 dma_burst_size;
 80	u32 threshold;
 81	u32 dma_threshold;
 82	u16 lpss_rx_threshold;
 83	u16 lpss_tx_threshold;
 84	u8 enable_dma;
 85	union {
 86		struct gpio_desc *gpiod_cs;
 87		unsigned int frm;
 88	};
 89	int gpio_cs_inverted;
 90	int (*write)(struct driver_data *drv_data);
 91	int (*read)(struct driver_data *drv_data);
 92	void (*cs_control)(u32 command);
 93};
 94
 95static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data,
 96				  unsigned reg)
 97{
 98	return __raw_readl(drv_data->ioaddr + reg);
 99}
100
101static  inline void pxa2xx_spi_write(const struct driver_data *drv_data,
102				     unsigned reg, u32 val)
103{
104	__raw_writel(val, drv_data->ioaddr + reg);
105}
106
107#define START_STATE ((void *)0)
108#define RUNNING_STATE ((void *)1)
109#define DONE_STATE ((void *)2)
110#define ERROR_STATE ((void *)-1)
111
112#define DMA_ALIGNMENT		8
113
114static inline int pxa25x_ssp_comp(struct driver_data *drv_data)
115{
116	switch (drv_data->ssp_type) {
117	case PXA25x_SSP:
118	case CE4100_SSP:
119	case QUARK_X1000_SSP:
120		return 1;
121	default:
122		return 0;
123	}
124}
125
126static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val)
 
 
 
 
 
 
 
 
 
 
127{
128	if (drv_data->ssp_type == CE4100_SSP ||
129	    drv_data->ssp_type == QUARK_X1000_SSP)
130		val |= pxa2xx_spi_read(drv_data, SSSR) & SSSR_ALT_FRM_MASK;
131
132	pxa2xx_spi_write(drv_data, SSSR, val);
133}
134
135extern int pxa2xx_spi_flush(struct driver_data *drv_data);
136extern void *pxa2xx_spi_next_transfer(struct driver_data *drv_data);
137
138#define MAX_DMA_LEN		SZ_64K
139#define DEFAULT_DMA_CR1		(SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
140
141extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
142extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst);
 
143extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
 
144extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
145extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
146extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
147						  struct spi_device *spi,
148						  u8 bits_per_word,
149						  u32 *burst_code,
150						  u32 *threshold);
 
151
152#endif /* SPI_PXA2XX_H */