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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * Copyright (C) 2013, 2021 Intel Corporation
5 */
6
7#ifndef SPI_PXA2XX_H
8#define SPI_PXA2XX_H
9
10#include <linux/dmaengine.h>
11#include <linux/irqreturn.h>
12#include <linux/types.h>
13#include <linux/sizes.h>
14
15#include <linux/pxa2xx_ssp.h>
16
17struct device;
18struct gpio_desc;
19
20/*
21 * The platform data for SSP controller devices
22 * (resides in device.platform_data).
23 */
24struct pxa2xx_spi_controller {
25 u8 num_chipselect;
26 u8 enable_dma;
27 u8 dma_burst_size;
28 bool is_target;
29
30 /* DMA engine specific config */
31 dma_filter_fn dma_filter;
32 void *tx_param;
33 void *rx_param;
34
35 /* For non-PXA arches */
36 struct ssp_device ssp;
37};
38
39struct spi_controller;
40struct spi_device;
41struct spi_transfer;
42
43struct driver_data {
44 /* SSP Info */
45 struct ssp_device *ssp;
46
47 /* SPI framework hookup */
48 enum pxa_ssp_type ssp_type;
49 struct spi_controller *controller;
50
51 /* PXA hookup */
52 struct pxa2xx_spi_controller *controller_info;
53
54 /* SSP masks*/
55 u32 dma_cr1;
56 u32 int_cr1;
57 u32 clear_sr;
58 u32 mask_sr;
59
60 /* DMA engine support */
61 atomic_t dma_running;
62
63 /* Current transfer state info */
64 void *tx;
65 void *tx_end;
66 void *rx;
67 void *rx_end;
68 u8 n_bytes;
69 int (*write)(struct driver_data *drv_data);
70 int (*read)(struct driver_data *drv_data);
71 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
72
73 void __iomem *lpss_base;
74
75 /* Optional slave FIFO ready signal */
76 struct gpio_desc *gpiod_ready;
77};
78
79static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data, u32 reg)
80{
81 return pxa_ssp_read_reg(drv_data->ssp, reg);
82}
83
84static inline void pxa2xx_spi_write(const struct driver_data *drv_data, u32 reg, u32 val)
85{
86 pxa_ssp_write_reg(drv_data->ssp, reg, val);
87}
88
89#define DMA_ALIGNMENT 8
90
91static inline int pxa25x_ssp_comp(const struct driver_data *drv_data)
92{
93 switch (drv_data->ssp_type) {
94 case PXA25x_SSP:
95 case CE4100_SSP:
96 case QUARK_X1000_SSP:
97 return 1;
98 default:
99 return 0;
100 }
101}
102
103static inline void clear_SSCR1_bits(const struct driver_data *drv_data, u32 bits)
104{
105 pxa2xx_spi_write(drv_data, SSCR1, pxa2xx_spi_read(drv_data, SSCR1) & ~bits);
106}
107
108static inline u32 read_SSSR_bits(const struct driver_data *drv_data, u32 bits)
109{
110 return pxa2xx_spi_read(drv_data, SSSR) & bits;
111}
112
113static inline void write_SSSR_CS(const struct driver_data *drv_data, u32 val)
114{
115 if (drv_data->ssp_type == CE4100_SSP ||
116 drv_data->ssp_type == QUARK_X1000_SSP)
117 val |= read_SSSR_bits(drv_data, SSSR_ALT_FRM_MASK);
118
119 pxa2xx_spi_write(drv_data, SSSR, val);
120}
121
122extern int pxa2xx_spi_flush(struct driver_data *drv_data);
123
124#define MAX_DMA_LEN SZ_64K
125#define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
126
127extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
128extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
129 struct spi_transfer *xfer);
130extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
131extern void pxa2xx_spi_dma_stop(struct driver_data *drv_data);
132extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
133extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
134
135int pxa2xx_spi_probe(struct device *dev, struct ssp_device *ssp,
136 struct pxa2xx_spi_controller *platform_info);
137void pxa2xx_spi_remove(struct device *dev);
138
139extern const struct dev_pm_ops pxa2xx_spi_pm_ops;
140
141#endif /* SPI_PXA2XX_H */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * Copyright (C) 2013, 2021 Intel Corporation
5 */
6
7#ifndef SPI_PXA2XX_H
8#define SPI_PXA2XX_H
9
10#include <linux/interrupt.h>
11#include <linux/io.h>
12#include <linux/types.h>
13#include <linux/sizes.h>
14
15#include <linux/pxa2xx_ssp.h>
16
17struct gpio_desc;
18struct pxa2xx_spi_controller;
19struct spi_controller;
20struct spi_device;
21struct spi_transfer;
22
23struct driver_data {
24 /* SSP Info */
25 struct ssp_device *ssp;
26
27 /* SPI framework hookup */
28 enum pxa_ssp_type ssp_type;
29 struct spi_controller *controller;
30
31 /* PXA hookup */
32 struct pxa2xx_spi_controller *controller_info;
33
34 /* SSP masks*/
35 u32 dma_cr1;
36 u32 int_cr1;
37 u32 clear_sr;
38 u32 mask_sr;
39
40 /* DMA engine support */
41 atomic_t dma_running;
42
43 /* Current transfer state info */
44 void *tx;
45 void *tx_end;
46 void *rx;
47 void *rx_end;
48 u8 n_bytes;
49 int (*write)(struct driver_data *drv_data);
50 int (*read)(struct driver_data *drv_data);
51 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
52
53 void __iomem *lpss_base;
54
55 /* Optional slave FIFO ready signal */
56 struct gpio_desc *gpiod_ready;
57};
58
59struct chip_data {
60 u32 cr1;
61 u32 dds_rate;
62 u32 timeout;
63 u8 enable_dma;
64 u32 dma_burst_size;
65 u32 dma_threshold;
66 u32 threshold;
67 u16 lpss_rx_threshold;
68 u16 lpss_tx_threshold;
69};
70
71static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data, u32 reg)
72{
73 return pxa_ssp_read_reg(drv_data->ssp, reg);
74}
75
76static inline void pxa2xx_spi_write(const struct driver_data *drv_data, u32 reg, u32 val)
77{
78 pxa_ssp_write_reg(drv_data->ssp, reg, val);
79}
80
81#define DMA_ALIGNMENT 8
82
83static inline int pxa25x_ssp_comp(const struct driver_data *drv_data)
84{
85 switch (drv_data->ssp_type) {
86 case PXA25x_SSP:
87 case CE4100_SSP:
88 case QUARK_X1000_SSP:
89 return 1;
90 default:
91 return 0;
92 }
93}
94
95static inline void clear_SSCR1_bits(const struct driver_data *drv_data, u32 bits)
96{
97 pxa2xx_spi_write(drv_data, SSCR1, pxa2xx_spi_read(drv_data, SSCR1) & ~bits);
98}
99
100static inline u32 read_SSSR_bits(const struct driver_data *drv_data, u32 bits)
101{
102 return pxa2xx_spi_read(drv_data, SSSR) & bits;
103}
104
105static inline void write_SSSR_CS(const struct driver_data *drv_data, u32 val)
106{
107 if (drv_data->ssp_type == CE4100_SSP ||
108 drv_data->ssp_type == QUARK_X1000_SSP)
109 val |= read_SSSR_bits(drv_data, SSSR_ALT_FRM_MASK);
110
111 pxa2xx_spi_write(drv_data, SSSR, val);
112}
113
114extern int pxa2xx_spi_flush(struct driver_data *drv_data);
115
116#define MAX_DMA_LEN SZ_64K
117#define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
118
119extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
120extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
121 struct spi_transfer *xfer);
122extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
123extern void pxa2xx_spi_dma_stop(struct driver_data *drv_data);
124extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
125extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
126extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
127 struct spi_device *spi,
128 u8 bits_per_word,
129 u32 *burst_code,
130 u32 *threshold);
131
132#endif /* SPI_PXA2XX_H */