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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * An rtc driver for the Dallas DS1511
4 *
5 * Copyright (C) 2006 Atsushi Nemoto <anemo@mba.ocn.ne.jp>
6 * Copyright (C) 2007 Andrew Sharp <andy.sharp@lsi.com>
7 *
8 * Real time clock driver for the Dallas 1511 chip, which also
9 * contains a watchdog timer. There is a tiny amount of code that
10 * platform code could use to mess with the watchdog device a little
11 * bit, but not a full watchdog driver.
12 */
13
14#include <linux/bcd.h>
15#include <linux/init.h>
16#include <linux/kernel.h>
17#include <linux/gfp.h>
18#include <linux/delay.h>
19#include <linux/interrupt.h>
20#include <linux/rtc.h>
21#include <linux/platform_device.h>
22#include <linux/io.h>
23#include <linux/module.h>
24
25#define DS1511_SEC 0x0
26#define DS1511_MIN 0x1
27#define DS1511_HOUR 0x2
28#define DS1511_DOW 0x3
29#define DS1511_DOM 0x4
30#define DS1511_MONTH 0x5
31#define DS1511_YEAR 0x6
32#define DS1511_CENTURY 0x7
33#define DS1511_AM1_SEC 0x8
34#define DS1511_AM2_MIN 0x9
35#define DS1511_AM3_HOUR 0xa
36#define DS1511_AM4_DATE 0xb
37#define DS1511_WD_MSEC 0xc
38#define DS1511_WD_SEC 0xd
39#define DS1511_CONTROL_A 0xe
40#define DS1511_CONTROL_B 0xf
41#define DS1511_RAMADDR_LSB 0x10
42#define DS1511_RAMDATA 0x13
43
44#define DS1511_BLF1 0x80
45#define DS1511_BLF2 0x40
46#define DS1511_PRS 0x20
47#define DS1511_PAB 0x10
48#define DS1511_TDF 0x08
49#define DS1511_KSF 0x04
50#define DS1511_WDF 0x02
51#define DS1511_IRQF 0x01
52#define DS1511_TE 0x80
53#define DS1511_CS 0x40
54#define DS1511_BME 0x20
55#define DS1511_TPE 0x10
56#define DS1511_TIE 0x08
57#define DS1511_KIE 0x04
58#define DS1511_WDE 0x02
59#define DS1511_WDS 0x01
60#define DS1511_RAM_MAX 0x100
61
62struct ds1511_data {
63 struct rtc_device *rtc;
64 void __iomem *ioaddr; /* virtual base address */
65 int irq;
66 spinlock_t lock;
67};
68
69static DEFINE_SPINLOCK(ds1511_lock);
70
71static __iomem char *ds1511_base;
72static u32 reg_spacing = 1;
73
74static void rtc_write(uint8_t val, uint32_t reg)
75{
76 writeb(val, ds1511_base + (reg * reg_spacing));
77}
78
79static uint8_t rtc_read(uint32_t reg)
80{
81 return readb(ds1511_base + (reg * reg_spacing));
82}
83
84static void rtc_disable_update(void)
85{
86 rtc_write((rtc_read(DS1511_CONTROL_B) & ~DS1511_TE), DS1511_CONTROL_B);
87}
88
89static void rtc_enable_update(void)
90{
91 rtc_write((rtc_read(DS1511_CONTROL_B) | DS1511_TE), DS1511_CONTROL_B);
92}
93
94static int ds1511_rtc_set_time(struct device *dev, struct rtc_time *rtc_tm)
95{
96 u8 mon, day, dow, hrs, min, sec, yrs, cen;
97 unsigned long flags;
98
99 yrs = rtc_tm->tm_year % 100;
100 cen = 19 + rtc_tm->tm_year / 100;
101 mon = rtc_tm->tm_mon + 1; /* tm_mon starts at zero */
102 day = rtc_tm->tm_mday;
103 dow = rtc_tm->tm_wday & 0x7; /* automatic BCD */
104 hrs = rtc_tm->tm_hour;
105 min = rtc_tm->tm_min;
106 sec = rtc_tm->tm_sec;
107
108 /*
109 * each register is a different number of valid bits
110 */
111 sec = bin2bcd(sec) & 0x7f;
112 min = bin2bcd(min) & 0x7f;
113 hrs = bin2bcd(hrs) & 0x3f;
114 day = bin2bcd(day) & 0x3f;
115 mon = bin2bcd(mon) & 0x1f;
116 yrs = bin2bcd(yrs) & 0xff;
117 cen = bin2bcd(cen) & 0xff;
118
119 spin_lock_irqsave(&ds1511_lock, flags);
120 rtc_disable_update();
121 rtc_write(cen, DS1511_CENTURY);
122 rtc_write(yrs, DS1511_YEAR);
123 rtc_write((rtc_read(DS1511_MONTH) & 0xe0) | mon, DS1511_MONTH);
124 rtc_write(day, DS1511_DOM);
125 rtc_write(hrs, DS1511_HOUR);
126 rtc_write(min, DS1511_MIN);
127 rtc_write(sec, DS1511_SEC);
128 rtc_write(dow, DS1511_DOW);
129 rtc_enable_update();
130 spin_unlock_irqrestore(&ds1511_lock, flags);
131
132 return 0;
133}
134
135static int ds1511_rtc_read_time(struct device *dev, struct rtc_time *rtc_tm)
136{
137 unsigned int century;
138 unsigned long flags;
139
140 spin_lock_irqsave(&ds1511_lock, flags);
141 rtc_disable_update();
142
143 rtc_tm->tm_sec = rtc_read(DS1511_SEC) & 0x7f;
144 rtc_tm->tm_min = rtc_read(DS1511_MIN) & 0x7f;
145 rtc_tm->tm_hour = rtc_read(DS1511_HOUR) & 0x3f;
146 rtc_tm->tm_mday = rtc_read(DS1511_DOM) & 0x3f;
147 rtc_tm->tm_wday = rtc_read(DS1511_DOW) & 0x7;
148 rtc_tm->tm_mon = rtc_read(DS1511_MONTH) & 0x1f;
149 rtc_tm->tm_year = rtc_read(DS1511_YEAR) & 0x7f;
150 century = rtc_read(DS1511_CENTURY);
151
152 rtc_enable_update();
153 spin_unlock_irqrestore(&ds1511_lock, flags);
154
155 rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
156 rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
157 rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
158 rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
159 rtc_tm->tm_wday = bcd2bin(rtc_tm->tm_wday);
160 rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon);
161 rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
162 century = bcd2bin(century) * 100;
163
164 /*
165 * Account for differences between how the RTC uses the values
166 * and how they are defined in a struct rtc_time;
167 */
168 century += rtc_tm->tm_year;
169 rtc_tm->tm_year = century - 1900;
170
171 rtc_tm->tm_mon--;
172
173 return 0;
174}
175
176static void ds1511_rtc_alarm_enable(unsigned int enabled)
177{
178 rtc_write(rtc_read(DS1511_CONTROL_B) | (enabled ? DS1511_TIE : 0), DS1511_CONTROL_B);
179}
180
181static int ds1511_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
182{
183 struct ds1511_data *ds1511 = dev_get_drvdata(dev);
184 unsigned long flags;
185
186 spin_lock_irqsave(&ds1511->lock, flags);
187 rtc_write(bin2bcd(alrm->time.tm_mday) & 0x3f, DS1511_AM4_DATE);
188 rtc_write(bin2bcd(alrm->time.tm_hour) & 0x3f, DS1511_AM3_HOUR);
189 rtc_write(bin2bcd(alrm->time.tm_min) & 0x7f, DS1511_AM2_MIN);
190 rtc_write(bin2bcd(alrm->time.tm_sec) & 0x7f, DS1511_AM1_SEC);
191 ds1511_rtc_alarm_enable(alrm->enabled);
192
193 rtc_read(DS1511_CONTROL_A); /* clear interrupts */
194 spin_unlock_irqrestore(&ds1511->lock, flags);
195
196 return 0;
197}
198
199static int ds1511_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
200{
201 alrm->time.tm_mday = bcd2bin(rtc_read(DS1511_AM4_DATE) & 0x3f);
202 alrm->time.tm_hour = bcd2bin(rtc_read(DS1511_AM3_HOUR) & 0x3f);
203 alrm->time.tm_min = bcd2bin(rtc_read(DS1511_AM2_MIN) & 0x7f);
204 alrm->time.tm_sec = bcd2bin(rtc_read(DS1511_AM1_SEC) & 0x7f);
205 alrm->enabled = !!(rtc_read(DS1511_CONTROL_B) & DS1511_TIE);
206
207 return 0;
208}
209
210static irqreturn_t ds1511_interrupt(int irq, void *dev_id)
211{
212 struct platform_device *pdev = dev_id;
213 struct ds1511_data *ds1511 = platform_get_drvdata(pdev);
214 unsigned long events = 0;
215
216 spin_lock(&ds1511->lock);
217 /*
218 * read and clear interrupt
219 */
220 if (rtc_read(DS1511_CONTROL_A) & DS1511_IRQF) {
221 events = RTC_IRQF | RTC_AF;
222 rtc_update_irq(ds1511->rtc, 1, events);
223 }
224 spin_unlock(&ds1511->lock);
225 return events ? IRQ_HANDLED : IRQ_NONE;
226}
227
228static int ds1511_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
229{
230 struct ds1511_data *ds1511 = dev_get_drvdata(dev);
231 unsigned long flags;
232
233 spin_lock_irqsave(&ds1511->lock, flags);
234 ds1511_rtc_alarm_enable(enabled);
235 spin_unlock_irqrestore(&ds1511->lock, flags);
236
237 return 0;
238}
239
240static const struct rtc_class_ops ds1511_rtc_ops = {
241 .read_time = ds1511_rtc_read_time,
242 .set_time = ds1511_rtc_set_time,
243 .read_alarm = ds1511_rtc_read_alarm,
244 .set_alarm = ds1511_rtc_set_alarm,
245 .alarm_irq_enable = ds1511_rtc_alarm_irq_enable,
246};
247
248static int ds1511_nvram_read(void *priv, unsigned int pos, void *buf,
249 size_t size)
250{
251 int i;
252
253 rtc_write(pos, DS1511_RAMADDR_LSB);
254 for (i = 0; i < size; i++)
255 *(char *)buf++ = rtc_read(DS1511_RAMDATA);
256
257 return 0;
258}
259
260static int ds1511_nvram_write(void *priv, unsigned int pos, void *buf,
261 size_t size)
262{
263 int i;
264
265 rtc_write(pos, DS1511_RAMADDR_LSB);
266 for (i = 0; i < size; i++)
267 rtc_write(*(char *)buf++, DS1511_RAMDATA);
268
269 return 0;
270}
271
272static int ds1511_rtc_probe(struct platform_device *pdev)
273{
274 struct ds1511_data *ds1511;
275 int ret = 0;
276 struct nvmem_config ds1511_nvmem_cfg = {
277 .name = "ds1511_nvram",
278 .word_size = 1,
279 .stride = 1,
280 .size = DS1511_RAM_MAX,
281 .reg_read = ds1511_nvram_read,
282 .reg_write = ds1511_nvram_write,
283 .priv = &pdev->dev,
284 };
285
286 ds1511 = devm_kzalloc(&pdev->dev, sizeof(*ds1511), GFP_KERNEL);
287 if (!ds1511)
288 return -ENOMEM;
289
290 ds1511_base = devm_platform_ioremap_resource(pdev, 0);
291 if (IS_ERR(ds1511_base))
292 return PTR_ERR(ds1511_base);
293 ds1511->ioaddr = ds1511_base;
294 ds1511->irq = platform_get_irq(pdev, 0);
295
296 /*
297 * turn on the clock and the crystal, etc.
298 */
299 rtc_write(DS1511_BME, DS1511_CONTROL_B);
300 rtc_write(0, DS1511_CONTROL_A);
301 /*
302 * clear the wdog counter
303 */
304 rtc_write(0, DS1511_WD_MSEC);
305 rtc_write(0, DS1511_WD_SEC);
306 /*
307 * start the clock
308 */
309 rtc_enable_update();
310
311 /*
312 * check for a dying bat-tree
313 */
314 if (rtc_read(DS1511_CONTROL_A) & DS1511_BLF1)
315 dev_warn(&pdev->dev, "voltage-low detected.\n");
316
317 spin_lock_init(&ds1511->lock);
318 platform_set_drvdata(pdev, ds1511);
319
320 ds1511->rtc = devm_rtc_allocate_device(&pdev->dev);
321 if (IS_ERR(ds1511->rtc))
322 return PTR_ERR(ds1511->rtc);
323
324 ds1511->rtc->ops = &ds1511_rtc_ops;
325 ds1511->rtc->range_max = RTC_TIMESTAMP_END_2099;
326 ds1511->rtc->alarm_offset_max = 28 * 24 * 60 * 60 - 1;
327
328 /*
329 * if the platform has an interrupt in mind for this device,
330 * then by all means, set it
331 */
332 if (ds1511->irq > 0) {
333 rtc_read(DS1511_CONTROL_A);
334 if (devm_request_irq(&pdev->dev, ds1511->irq, ds1511_interrupt,
335 IRQF_SHARED, pdev->name, pdev) < 0) {
336
337 dev_warn(&pdev->dev, "interrupt not available.\n");
338 ds1511->irq = 0;
339 }
340 }
341
342 if (ds1511->irq == 0)
343 clear_bit(RTC_FEATURE_ALARM, ds1511->rtc->features);
344
345 ret = devm_rtc_register_device(ds1511->rtc);
346 if (ret)
347 return ret;
348
349 devm_rtc_nvmem_register(ds1511->rtc, &ds1511_nvmem_cfg);
350
351 return 0;
352}
353
354/* work with hotplug and coldplug */
355MODULE_ALIAS("platform:ds1511");
356
357static struct platform_driver ds1511_rtc_driver = {
358 .probe = ds1511_rtc_probe,
359 .driver = {
360 .name = "ds1511",
361 },
362};
363
364module_platform_driver(ds1511_rtc_driver);
365
366MODULE_AUTHOR("Andrew Sharp <andy.sharp@lsi.com>");
367MODULE_DESCRIPTION("Dallas DS1511 RTC driver");
368MODULE_LICENSE("GPL");
1/*
2 * An rtc driver for the Dallas DS1511
3 *
4 * Copyright (C) 2006 Atsushi Nemoto <anemo@mba.ocn.ne.jp>
5 * Copyright (C) 2007 Andrew Sharp <andy.sharp@lsi.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Real time clock driver for the Dallas 1511 chip, which also
12 * contains a watchdog timer. There is a tiny amount of code that
13 * platform code could use to mess with the watchdog device a little
14 * bit, but not a full watchdog driver.
15 */
16
17#include <linux/bcd.h>
18#include <linux/init.h>
19#include <linux/kernel.h>
20#include <linux/gfp.h>
21#include <linux/delay.h>
22#include <linux/interrupt.h>
23#include <linux/rtc.h>
24#include <linux/platform_device.h>
25#include <linux/io.h>
26#include <linux/module.h>
27
28enum ds1511reg {
29 DS1511_SEC = 0x0,
30 DS1511_MIN = 0x1,
31 DS1511_HOUR = 0x2,
32 DS1511_DOW = 0x3,
33 DS1511_DOM = 0x4,
34 DS1511_MONTH = 0x5,
35 DS1511_YEAR = 0x6,
36 DS1511_CENTURY = 0x7,
37 DS1511_AM1_SEC = 0x8,
38 DS1511_AM2_MIN = 0x9,
39 DS1511_AM3_HOUR = 0xa,
40 DS1511_AM4_DATE = 0xb,
41 DS1511_WD_MSEC = 0xc,
42 DS1511_WD_SEC = 0xd,
43 DS1511_CONTROL_A = 0xe,
44 DS1511_CONTROL_B = 0xf,
45 DS1511_RAMADDR_LSB = 0x10,
46 DS1511_RAMDATA = 0x13
47};
48
49#define DS1511_BLF1 0x80
50#define DS1511_BLF2 0x40
51#define DS1511_PRS 0x20
52#define DS1511_PAB 0x10
53#define DS1511_TDF 0x08
54#define DS1511_KSF 0x04
55#define DS1511_WDF 0x02
56#define DS1511_IRQF 0x01
57#define DS1511_TE 0x80
58#define DS1511_CS 0x40
59#define DS1511_BME 0x20
60#define DS1511_TPE 0x10
61#define DS1511_TIE 0x08
62#define DS1511_KIE 0x04
63#define DS1511_WDE 0x02
64#define DS1511_WDS 0x01
65#define DS1511_RAM_MAX 0x100
66
67#define RTC_CMD DS1511_CONTROL_B
68#define RTC_CMD1 DS1511_CONTROL_A
69
70#define RTC_ALARM_SEC DS1511_AM1_SEC
71#define RTC_ALARM_MIN DS1511_AM2_MIN
72#define RTC_ALARM_HOUR DS1511_AM3_HOUR
73#define RTC_ALARM_DATE DS1511_AM4_DATE
74
75#define RTC_SEC DS1511_SEC
76#define RTC_MIN DS1511_MIN
77#define RTC_HOUR DS1511_HOUR
78#define RTC_DOW DS1511_DOW
79#define RTC_DOM DS1511_DOM
80#define RTC_MON DS1511_MONTH
81#define RTC_YEAR DS1511_YEAR
82#define RTC_CENTURY DS1511_CENTURY
83
84#define RTC_TIE DS1511_TIE
85#define RTC_TE DS1511_TE
86
87struct rtc_plat_data {
88 struct rtc_device *rtc;
89 void __iomem *ioaddr; /* virtual base address */
90 int irq;
91 unsigned int irqen;
92 int alrm_sec;
93 int alrm_min;
94 int alrm_hour;
95 int alrm_mday;
96 spinlock_t lock;
97};
98
99static DEFINE_SPINLOCK(ds1511_lock);
100
101static __iomem char *ds1511_base;
102static u32 reg_spacing = 1;
103
104static noinline void
105rtc_write(uint8_t val, uint32_t reg)
106{
107 writeb(val, ds1511_base + (reg * reg_spacing));
108}
109
110static inline void
111rtc_write_alarm(uint8_t val, enum ds1511reg reg)
112{
113 rtc_write((val | 0x80), reg);
114}
115
116static noinline uint8_t
117rtc_read(enum ds1511reg reg)
118{
119 return readb(ds1511_base + (reg * reg_spacing));
120}
121
122static inline void
123rtc_disable_update(void)
124{
125 rtc_write((rtc_read(RTC_CMD) & ~RTC_TE), RTC_CMD);
126}
127
128static void
129rtc_enable_update(void)
130{
131 rtc_write((rtc_read(RTC_CMD) | RTC_TE), RTC_CMD);
132}
133
134/*
135 * #define DS1511_WDOG_RESET_SUPPORT
136 *
137 * Uncomment this if you want to use these routines in
138 * some platform code.
139 */
140#ifdef DS1511_WDOG_RESET_SUPPORT
141/*
142 * just enough code to set the watchdog timer so that it
143 * will reboot the system
144 */
145void
146ds1511_wdog_set(unsigned long deciseconds)
147{
148 /*
149 * the wdog timer can take 99.99 seconds
150 */
151 deciseconds %= 10000;
152 /*
153 * set the wdog values in the wdog registers
154 */
155 rtc_write(bin2bcd(deciseconds % 100), DS1511_WD_MSEC);
156 rtc_write(bin2bcd(deciseconds / 100), DS1511_WD_SEC);
157 /*
158 * set wdog enable and wdog 'steering' bit to issue a reset
159 */
160 rtc_write(rtc_read(RTC_CMD) | DS1511_WDE | DS1511_WDS, RTC_CMD);
161}
162
163void
164ds1511_wdog_disable(void)
165{
166 /*
167 * clear wdog enable and wdog 'steering' bits
168 */
169 rtc_write(rtc_read(RTC_CMD) & ~(DS1511_WDE | DS1511_WDS), RTC_CMD);
170 /*
171 * clear the wdog counter
172 */
173 rtc_write(0, DS1511_WD_MSEC);
174 rtc_write(0, DS1511_WD_SEC);
175}
176#endif
177
178/*
179 * set the rtc chip's idea of the time.
180 * stupidly, some callers call with year unmolested;
181 * and some call with year = year - 1900. thanks.
182 */
183static int ds1511_rtc_set_time(struct device *dev, struct rtc_time *rtc_tm)
184{
185 u8 mon, day, dow, hrs, min, sec, yrs, cen;
186 unsigned long flags;
187
188 /*
189 * won't have to change this for a while
190 */
191 if (rtc_tm->tm_year < 1900)
192 rtc_tm->tm_year += 1900;
193
194 if (rtc_tm->tm_year < 1970)
195 return -EINVAL;
196
197 yrs = rtc_tm->tm_year % 100;
198 cen = rtc_tm->tm_year / 100;
199 mon = rtc_tm->tm_mon + 1; /* tm_mon starts at zero */
200 day = rtc_tm->tm_mday;
201 dow = rtc_tm->tm_wday & 0x7; /* automatic BCD */
202 hrs = rtc_tm->tm_hour;
203 min = rtc_tm->tm_min;
204 sec = rtc_tm->tm_sec;
205
206 if ((mon > 12) || (day == 0))
207 return -EINVAL;
208
209 if (day > rtc_month_days(rtc_tm->tm_mon, rtc_tm->tm_year))
210 return -EINVAL;
211
212 if ((hrs >= 24) || (min >= 60) || (sec >= 60))
213 return -EINVAL;
214
215 /*
216 * each register is a different number of valid bits
217 */
218 sec = bin2bcd(sec) & 0x7f;
219 min = bin2bcd(min) & 0x7f;
220 hrs = bin2bcd(hrs) & 0x3f;
221 day = bin2bcd(day) & 0x3f;
222 mon = bin2bcd(mon) & 0x1f;
223 yrs = bin2bcd(yrs) & 0xff;
224 cen = bin2bcd(cen) & 0xff;
225
226 spin_lock_irqsave(&ds1511_lock, flags);
227 rtc_disable_update();
228 rtc_write(cen, RTC_CENTURY);
229 rtc_write(yrs, RTC_YEAR);
230 rtc_write((rtc_read(RTC_MON) & 0xe0) | mon, RTC_MON);
231 rtc_write(day, RTC_DOM);
232 rtc_write(hrs, RTC_HOUR);
233 rtc_write(min, RTC_MIN);
234 rtc_write(sec, RTC_SEC);
235 rtc_write(dow, RTC_DOW);
236 rtc_enable_update();
237 spin_unlock_irqrestore(&ds1511_lock, flags);
238
239 return 0;
240}
241
242static int ds1511_rtc_read_time(struct device *dev, struct rtc_time *rtc_tm)
243{
244 unsigned int century;
245 unsigned long flags;
246
247 spin_lock_irqsave(&ds1511_lock, flags);
248 rtc_disable_update();
249
250 rtc_tm->tm_sec = rtc_read(RTC_SEC) & 0x7f;
251 rtc_tm->tm_min = rtc_read(RTC_MIN) & 0x7f;
252 rtc_tm->tm_hour = rtc_read(RTC_HOUR) & 0x3f;
253 rtc_tm->tm_mday = rtc_read(RTC_DOM) & 0x3f;
254 rtc_tm->tm_wday = rtc_read(RTC_DOW) & 0x7;
255 rtc_tm->tm_mon = rtc_read(RTC_MON) & 0x1f;
256 rtc_tm->tm_year = rtc_read(RTC_YEAR) & 0x7f;
257 century = rtc_read(RTC_CENTURY);
258
259 rtc_enable_update();
260 spin_unlock_irqrestore(&ds1511_lock, flags);
261
262 rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
263 rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
264 rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
265 rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
266 rtc_tm->tm_wday = bcd2bin(rtc_tm->tm_wday);
267 rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon);
268 rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
269 century = bcd2bin(century) * 100;
270
271 /*
272 * Account for differences between how the RTC uses the values
273 * and how they are defined in a struct rtc_time;
274 */
275 century += rtc_tm->tm_year;
276 rtc_tm->tm_year = century - 1900;
277
278 rtc_tm->tm_mon--;
279
280 return 0;
281}
282
283/*
284 * write the alarm register settings
285 *
286 * we only have the use to interrupt every second, otherwise
287 * known as the update interrupt, or the interrupt if the whole
288 * date/hours/mins/secs matches. the ds1511 has many more
289 * permutations, but the kernel doesn't.
290 */
291static void
292ds1511_rtc_update_alarm(struct rtc_plat_data *pdata)
293{
294 unsigned long flags;
295
296 spin_lock_irqsave(&pdata->lock, flags);
297 rtc_write(pdata->alrm_mday < 0 || (pdata->irqen & RTC_UF) ?
298 0x80 : bin2bcd(pdata->alrm_mday) & 0x3f,
299 RTC_ALARM_DATE);
300 rtc_write(pdata->alrm_hour < 0 || (pdata->irqen & RTC_UF) ?
301 0x80 : bin2bcd(pdata->alrm_hour) & 0x3f,
302 RTC_ALARM_HOUR);
303 rtc_write(pdata->alrm_min < 0 || (pdata->irqen & RTC_UF) ?
304 0x80 : bin2bcd(pdata->alrm_min) & 0x7f,
305 RTC_ALARM_MIN);
306 rtc_write(pdata->alrm_sec < 0 || (pdata->irqen & RTC_UF) ?
307 0x80 : bin2bcd(pdata->alrm_sec) & 0x7f,
308 RTC_ALARM_SEC);
309 rtc_write(rtc_read(RTC_CMD) | (pdata->irqen ? RTC_TIE : 0), RTC_CMD);
310 rtc_read(RTC_CMD1); /* clear interrupts */
311 spin_unlock_irqrestore(&pdata->lock, flags);
312}
313
314static int
315ds1511_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
316{
317 struct platform_device *pdev = to_platform_device(dev);
318 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
319
320 if (pdata->irq <= 0)
321 return -EINVAL;
322
323 pdata->alrm_mday = alrm->time.tm_mday;
324 pdata->alrm_hour = alrm->time.tm_hour;
325 pdata->alrm_min = alrm->time.tm_min;
326 pdata->alrm_sec = alrm->time.tm_sec;
327 if (alrm->enabled)
328 pdata->irqen |= RTC_AF;
329
330 ds1511_rtc_update_alarm(pdata);
331 return 0;
332}
333
334static int
335ds1511_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
336{
337 struct platform_device *pdev = to_platform_device(dev);
338 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
339
340 if (pdata->irq <= 0)
341 return -EINVAL;
342
343 alrm->time.tm_mday = pdata->alrm_mday < 0 ? 0 : pdata->alrm_mday;
344 alrm->time.tm_hour = pdata->alrm_hour < 0 ? 0 : pdata->alrm_hour;
345 alrm->time.tm_min = pdata->alrm_min < 0 ? 0 : pdata->alrm_min;
346 alrm->time.tm_sec = pdata->alrm_sec < 0 ? 0 : pdata->alrm_sec;
347 alrm->enabled = (pdata->irqen & RTC_AF) ? 1 : 0;
348 return 0;
349}
350
351static irqreturn_t
352ds1511_interrupt(int irq, void *dev_id)
353{
354 struct platform_device *pdev = dev_id;
355 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
356 unsigned long events = 0;
357
358 spin_lock(&pdata->lock);
359 /*
360 * read and clear interrupt
361 */
362 if (rtc_read(RTC_CMD1) & DS1511_IRQF) {
363 events = RTC_IRQF;
364 if (rtc_read(RTC_ALARM_SEC) & 0x80)
365 events |= RTC_UF;
366 else
367 events |= RTC_AF;
368 rtc_update_irq(pdata->rtc, 1, events);
369 }
370 spin_unlock(&pdata->lock);
371 return events ? IRQ_HANDLED : IRQ_NONE;
372}
373
374static int ds1511_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
375{
376 struct platform_device *pdev = to_platform_device(dev);
377 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
378
379 if (pdata->irq <= 0)
380 return -EINVAL;
381 if (enabled)
382 pdata->irqen |= RTC_AF;
383 else
384 pdata->irqen &= ~RTC_AF;
385 ds1511_rtc_update_alarm(pdata);
386 return 0;
387}
388
389static const struct rtc_class_ops ds1511_rtc_ops = {
390 .read_time = ds1511_rtc_read_time,
391 .set_time = ds1511_rtc_set_time,
392 .read_alarm = ds1511_rtc_read_alarm,
393 .set_alarm = ds1511_rtc_set_alarm,
394 .alarm_irq_enable = ds1511_rtc_alarm_irq_enable,
395};
396
397static int ds1511_nvram_read(void *priv, unsigned int pos, void *buf,
398 size_t size)
399{
400 int i;
401
402 rtc_write(pos, DS1511_RAMADDR_LSB);
403 for (i = 0; i < size; i++)
404 *(char *)buf++ = rtc_read(DS1511_RAMDATA);
405
406 return 0;
407}
408
409static int ds1511_nvram_write(void *priv, unsigned int pos, void *buf,
410 size_t size)
411{
412 int i;
413
414 rtc_write(pos, DS1511_RAMADDR_LSB);
415 for (i = 0; i < size; i++)
416 rtc_write(*(char *)buf++, DS1511_RAMDATA);
417
418 return 0;
419}
420
421static int ds1511_rtc_probe(struct platform_device *pdev)
422{
423 struct resource *res;
424 struct rtc_plat_data *pdata;
425 int ret = 0;
426 struct nvmem_config ds1511_nvmem_cfg = {
427 .name = "ds1511_nvram",
428 .word_size = 1,
429 .stride = 1,
430 .size = DS1511_RAM_MAX,
431 .reg_read = ds1511_nvram_read,
432 .reg_write = ds1511_nvram_write,
433 .priv = &pdev->dev,
434 };
435
436 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
437 if (!pdata)
438 return -ENOMEM;
439
440 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
441 ds1511_base = devm_ioremap_resource(&pdev->dev, res);
442 if (IS_ERR(ds1511_base))
443 return PTR_ERR(ds1511_base);
444 pdata->ioaddr = ds1511_base;
445 pdata->irq = platform_get_irq(pdev, 0);
446
447 /*
448 * turn on the clock and the crystal, etc.
449 */
450 rtc_write(DS1511_BME, RTC_CMD);
451 rtc_write(0, RTC_CMD1);
452 /*
453 * clear the wdog counter
454 */
455 rtc_write(0, DS1511_WD_MSEC);
456 rtc_write(0, DS1511_WD_SEC);
457 /*
458 * start the clock
459 */
460 rtc_enable_update();
461
462 /*
463 * check for a dying bat-tree
464 */
465 if (rtc_read(RTC_CMD1) & DS1511_BLF1)
466 dev_warn(&pdev->dev, "voltage-low detected.\n");
467
468 spin_lock_init(&pdata->lock);
469 platform_set_drvdata(pdev, pdata);
470
471 pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
472 if (IS_ERR(pdata->rtc))
473 return PTR_ERR(pdata->rtc);
474
475 pdata->rtc->ops = &ds1511_rtc_ops;
476
477 pdata->rtc->nvram_old_abi = true;
478
479 ret = rtc_register_device(pdata->rtc);
480 if (ret)
481 return ret;
482
483 rtc_nvmem_register(pdata->rtc, &ds1511_nvmem_cfg);
484
485 /*
486 * if the platform has an interrupt in mind for this device,
487 * then by all means, set it
488 */
489 if (pdata->irq > 0) {
490 rtc_read(RTC_CMD1);
491 if (devm_request_irq(&pdev->dev, pdata->irq, ds1511_interrupt,
492 IRQF_SHARED, pdev->name, pdev) < 0) {
493
494 dev_warn(&pdev->dev, "interrupt not available.\n");
495 pdata->irq = 0;
496 }
497 }
498
499 return 0;
500}
501
502/* work with hotplug and coldplug */
503MODULE_ALIAS("platform:ds1511");
504
505static struct platform_driver ds1511_rtc_driver = {
506 .probe = ds1511_rtc_probe,
507 .driver = {
508 .name = "ds1511",
509 },
510};
511
512module_platform_driver(ds1511_rtc_driver);
513
514MODULE_AUTHOR("Andrew Sharp <andy.sharp@lsi.com>");
515MODULE_DESCRIPTION("Dallas DS1511 RTC driver");
516MODULE_LICENSE("GPL");