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1// SPDX-License-Identifier: GPL-2.0
2/*******************************************************************************
3 *
4 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
5 * Copyright(c) 2013 - 2014 Intel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#include "i40e_type.h"
29#include "i40e_adminq.h"
30#include "i40e_prototype.h"
31#include <linux/avf/virtchnl.h>
32
33/**
34 * i40e_set_mac_type - Sets MAC type
35 * @hw: pointer to the HW structure
36 *
37 * This function sets the mac type of the adapter based on the
38 * vendor ID and device ID stored in the hw structure.
39 **/
40i40e_status i40e_set_mac_type(struct i40e_hw *hw)
41{
42 i40e_status status = 0;
43
44 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
45 switch (hw->device_id) {
46 case I40E_DEV_ID_SFP_XL710:
47 case I40E_DEV_ID_QEMU:
48 case I40E_DEV_ID_KX_B:
49 case I40E_DEV_ID_KX_C:
50 case I40E_DEV_ID_QSFP_A:
51 case I40E_DEV_ID_QSFP_B:
52 case I40E_DEV_ID_QSFP_C:
53 case I40E_DEV_ID_10G_BASE_T:
54 case I40E_DEV_ID_10G_BASE_T4:
55 case I40E_DEV_ID_20G_KR2:
56 case I40E_DEV_ID_20G_KR2_A:
57 case I40E_DEV_ID_25G_B:
58 case I40E_DEV_ID_25G_SFP28:
59 hw->mac.type = I40E_MAC_XL710;
60 break;
61 case I40E_DEV_ID_SFP_X722:
62 case I40E_DEV_ID_1G_BASE_T_X722:
63 case I40E_DEV_ID_10G_BASE_T_X722:
64 case I40E_DEV_ID_SFP_I_X722:
65 hw->mac.type = I40E_MAC_X722;
66 break;
67 case I40E_DEV_ID_X722_VF:
68 hw->mac.type = I40E_MAC_X722_VF;
69 break;
70 case I40E_DEV_ID_VF:
71 case I40E_DEV_ID_VF_HV:
72 case I40E_DEV_ID_ADAPTIVE_VF:
73 hw->mac.type = I40E_MAC_VF;
74 break;
75 default:
76 hw->mac.type = I40E_MAC_GENERIC;
77 break;
78 }
79 } else {
80 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
81 }
82
83 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
84 hw->mac.type, status);
85 return status;
86}
87
88/**
89 * i40evf_aq_str - convert AQ err code to a string
90 * @hw: pointer to the HW structure
91 * @aq_err: the AQ error code to convert
92 **/
93const char *i40evf_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
94{
95 switch (aq_err) {
96 case I40E_AQ_RC_OK:
97 return "OK";
98 case I40E_AQ_RC_EPERM:
99 return "I40E_AQ_RC_EPERM";
100 case I40E_AQ_RC_ENOENT:
101 return "I40E_AQ_RC_ENOENT";
102 case I40E_AQ_RC_ESRCH:
103 return "I40E_AQ_RC_ESRCH";
104 case I40E_AQ_RC_EINTR:
105 return "I40E_AQ_RC_EINTR";
106 case I40E_AQ_RC_EIO:
107 return "I40E_AQ_RC_EIO";
108 case I40E_AQ_RC_ENXIO:
109 return "I40E_AQ_RC_ENXIO";
110 case I40E_AQ_RC_E2BIG:
111 return "I40E_AQ_RC_E2BIG";
112 case I40E_AQ_RC_EAGAIN:
113 return "I40E_AQ_RC_EAGAIN";
114 case I40E_AQ_RC_ENOMEM:
115 return "I40E_AQ_RC_ENOMEM";
116 case I40E_AQ_RC_EACCES:
117 return "I40E_AQ_RC_EACCES";
118 case I40E_AQ_RC_EFAULT:
119 return "I40E_AQ_RC_EFAULT";
120 case I40E_AQ_RC_EBUSY:
121 return "I40E_AQ_RC_EBUSY";
122 case I40E_AQ_RC_EEXIST:
123 return "I40E_AQ_RC_EEXIST";
124 case I40E_AQ_RC_EINVAL:
125 return "I40E_AQ_RC_EINVAL";
126 case I40E_AQ_RC_ENOTTY:
127 return "I40E_AQ_RC_ENOTTY";
128 case I40E_AQ_RC_ENOSPC:
129 return "I40E_AQ_RC_ENOSPC";
130 case I40E_AQ_RC_ENOSYS:
131 return "I40E_AQ_RC_ENOSYS";
132 case I40E_AQ_RC_ERANGE:
133 return "I40E_AQ_RC_ERANGE";
134 case I40E_AQ_RC_EFLUSHED:
135 return "I40E_AQ_RC_EFLUSHED";
136 case I40E_AQ_RC_BAD_ADDR:
137 return "I40E_AQ_RC_BAD_ADDR";
138 case I40E_AQ_RC_EMODE:
139 return "I40E_AQ_RC_EMODE";
140 case I40E_AQ_RC_EFBIG:
141 return "I40E_AQ_RC_EFBIG";
142 }
143
144 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
145 return hw->err_str;
146}
147
148/**
149 * i40evf_stat_str - convert status err code to a string
150 * @hw: pointer to the HW structure
151 * @stat_err: the status error code to convert
152 **/
153const char *i40evf_stat_str(struct i40e_hw *hw, i40e_status stat_err)
154{
155 switch (stat_err) {
156 case 0:
157 return "OK";
158 case I40E_ERR_NVM:
159 return "I40E_ERR_NVM";
160 case I40E_ERR_NVM_CHECKSUM:
161 return "I40E_ERR_NVM_CHECKSUM";
162 case I40E_ERR_PHY:
163 return "I40E_ERR_PHY";
164 case I40E_ERR_CONFIG:
165 return "I40E_ERR_CONFIG";
166 case I40E_ERR_PARAM:
167 return "I40E_ERR_PARAM";
168 case I40E_ERR_MAC_TYPE:
169 return "I40E_ERR_MAC_TYPE";
170 case I40E_ERR_UNKNOWN_PHY:
171 return "I40E_ERR_UNKNOWN_PHY";
172 case I40E_ERR_LINK_SETUP:
173 return "I40E_ERR_LINK_SETUP";
174 case I40E_ERR_ADAPTER_STOPPED:
175 return "I40E_ERR_ADAPTER_STOPPED";
176 case I40E_ERR_INVALID_MAC_ADDR:
177 return "I40E_ERR_INVALID_MAC_ADDR";
178 case I40E_ERR_DEVICE_NOT_SUPPORTED:
179 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
180 case I40E_ERR_MASTER_REQUESTS_PENDING:
181 return "I40E_ERR_MASTER_REQUESTS_PENDING";
182 case I40E_ERR_INVALID_LINK_SETTINGS:
183 return "I40E_ERR_INVALID_LINK_SETTINGS";
184 case I40E_ERR_AUTONEG_NOT_COMPLETE:
185 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
186 case I40E_ERR_RESET_FAILED:
187 return "I40E_ERR_RESET_FAILED";
188 case I40E_ERR_SWFW_SYNC:
189 return "I40E_ERR_SWFW_SYNC";
190 case I40E_ERR_NO_AVAILABLE_VSI:
191 return "I40E_ERR_NO_AVAILABLE_VSI";
192 case I40E_ERR_NO_MEMORY:
193 return "I40E_ERR_NO_MEMORY";
194 case I40E_ERR_BAD_PTR:
195 return "I40E_ERR_BAD_PTR";
196 case I40E_ERR_RING_FULL:
197 return "I40E_ERR_RING_FULL";
198 case I40E_ERR_INVALID_PD_ID:
199 return "I40E_ERR_INVALID_PD_ID";
200 case I40E_ERR_INVALID_QP_ID:
201 return "I40E_ERR_INVALID_QP_ID";
202 case I40E_ERR_INVALID_CQ_ID:
203 return "I40E_ERR_INVALID_CQ_ID";
204 case I40E_ERR_INVALID_CEQ_ID:
205 return "I40E_ERR_INVALID_CEQ_ID";
206 case I40E_ERR_INVALID_AEQ_ID:
207 return "I40E_ERR_INVALID_AEQ_ID";
208 case I40E_ERR_INVALID_SIZE:
209 return "I40E_ERR_INVALID_SIZE";
210 case I40E_ERR_INVALID_ARP_INDEX:
211 return "I40E_ERR_INVALID_ARP_INDEX";
212 case I40E_ERR_INVALID_FPM_FUNC_ID:
213 return "I40E_ERR_INVALID_FPM_FUNC_ID";
214 case I40E_ERR_QP_INVALID_MSG_SIZE:
215 return "I40E_ERR_QP_INVALID_MSG_SIZE";
216 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
217 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
218 case I40E_ERR_INVALID_FRAG_COUNT:
219 return "I40E_ERR_INVALID_FRAG_COUNT";
220 case I40E_ERR_QUEUE_EMPTY:
221 return "I40E_ERR_QUEUE_EMPTY";
222 case I40E_ERR_INVALID_ALIGNMENT:
223 return "I40E_ERR_INVALID_ALIGNMENT";
224 case I40E_ERR_FLUSHED_QUEUE:
225 return "I40E_ERR_FLUSHED_QUEUE";
226 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
227 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
228 case I40E_ERR_INVALID_IMM_DATA_SIZE:
229 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
230 case I40E_ERR_TIMEOUT:
231 return "I40E_ERR_TIMEOUT";
232 case I40E_ERR_OPCODE_MISMATCH:
233 return "I40E_ERR_OPCODE_MISMATCH";
234 case I40E_ERR_CQP_COMPL_ERROR:
235 return "I40E_ERR_CQP_COMPL_ERROR";
236 case I40E_ERR_INVALID_VF_ID:
237 return "I40E_ERR_INVALID_VF_ID";
238 case I40E_ERR_INVALID_HMCFN_ID:
239 return "I40E_ERR_INVALID_HMCFN_ID";
240 case I40E_ERR_BACKING_PAGE_ERROR:
241 return "I40E_ERR_BACKING_PAGE_ERROR";
242 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
243 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
244 case I40E_ERR_INVALID_PBLE_INDEX:
245 return "I40E_ERR_INVALID_PBLE_INDEX";
246 case I40E_ERR_INVALID_SD_INDEX:
247 return "I40E_ERR_INVALID_SD_INDEX";
248 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
249 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
250 case I40E_ERR_INVALID_SD_TYPE:
251 return "I40E_ERR_INVALID_SD_TYPE";
252 case I40E_ERR_MEMCPY_FAILED:
253 return "I40E_ERR_MEMCPY_FAILED";
254 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
255 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
256 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
257 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
258 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
259 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
260 case I40E_ERR_SRQ_ENABLED:
261 return "I40E_ERR_SRQ_ENABLED";
262 case I40E_ERR_ADMIN_QUEUE_ERROR:
263 return "I40E_ERR_ADMIN_QUEUE_ERROR";
264 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
265 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
266 case I40E_ERR_BUF_TOO_SHORT:
267 return "I40E_ERR_BUF_TOO_SHORT";
268 case I40E_ERR_ADMIN_QUEUE_FULL:
269 return "I40E_ERR_ADMIN_QUEUE_FULL";
270 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
271 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
272 case I40E_ERR_BAD_IWARP_CQE:
273 return "I40E_ERR_BAD_IWARP_CQE";
274 case I40E_ERR_NVM_BLANK_MODE:
275 return "I40E_ERR_NVM_BLANK_MODE";
276 case I40E_ERR_NOT_IMPLEMENTED:
277 return "I40E_ERR_NOT_IMPLEMENTED";
278 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
279 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
280 case I40E_ERR_DIAG_TEST_FAILED:
281 return "I40E_ERR_DIAG_TEST_FAILED";
282 case I40E_ERR_NOT_READY:
283 return "I40E_ERR_NOT_READY";
284 case I40E_NOT_SUPPORTED:
285 return "I40E_NOT_SUPPORTED";
286 case I40E_ERR_FIRMWARE_API_VERSION:
287 return "I40E_ERR_FIRMWARE_API_VERSION";
288 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
289 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
290 }
291
292 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
293 return hw->err_str;
294}
295
296/**
297 * i40evf_debug_aq
298 * @hw: debug mask related to admin queue
299 * @mask: debug mask
300 * @desc: pointer to admin queue descriptor
301 * @buffer: pointer to command buffer
302 * @buf_len: max length of buffer
303 *
304 * Dumps debug log about adminq command with descriptor contents.
305 **/
306void i40evf_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
307 void *buffer, u16 buf_len)
308{
309 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
310 u8 *buf = (u8 *)buffer;
311
312 if ((!(mask & hw->debug_mask)) || (desc == NULL))
313 return;
314
315 i40e_debug(hw, mask,
316 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
317 le16_to_cpu(aq_desc->opcode),
318 le16_to_cpu(aq_desc->flags),
319 le16_to_cpu(aq_desc->datalen),
320 le16_to_cpu(aq_desc->retval));
321 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
322 le32_to_cpu(aq_desc->cookie_high),
323 le32_to_cpu(aq_desc->cookie_low));
324 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
325 le32_to_cpu(aq_desc->params.internal.param0),
326 le32_to_cpu(aq_desc->params.internal.param1));
327 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
328 le32_to_cpu(aq_desc->params.external.addr_high),
329 le32_to_cpu(aq_desc->params.external.addr_low));
330
331 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
332 u16 len = le16_to_cpu(aq_desc->datalen);
333
334 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
335 if (buf_len < len)
336 len = buf_len;
337 /* write the full 16-byte chunks */
338 if (hw->debug_mask & mask) {
339 char prefix[27];
340
341 snprintf(prefix, sizeof(prefix),
342 "i40evf %02x:%02x.%x: \t0x",
343 hw->bus.bus_id,
344 hw->bus.device,
345 hw->bus.func);
346
347 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET,
348 16, 1, buf, len, false);
349 }
350 }
351}
352
353/**
354 * i40evf_check_asq_alive
355 * @hw: pointer to the hw struct
356 *
357 * Returns true if Queue is enabled else false.
358 **/
359bool i40evf_check_asq_alive(struct i40e_hw *hw)
360{
361 if (hw->aq.asq.len)
362 return !!(rd32(hw, hw->aq.asq.len) &
363 I40E_VF_ATQLEN1_ATQENABLE_MASK);
364 else
365 return false;
366}
367
368/**
369 * i40evf_aq_queue_shutdown
370 * @hw: pointer to the hw struct
371 * @unloading: is the driver unloading itself
372 *
373 * Tell the Firmware that we're shutting down the AdminQ and whether
374 * or not the driver is unloading as well.
375 **/
376i40e_status i40evf_aq_queue_shutdown(struct i40e_hw *hw,
377 bool unloading)
378{
379 struct i40e_aq_desc desc;
380 struct i40e_aqc_queue_shutdown *cmd =
381 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
382 i40e_status status;
383
384 i40evf_fill_default_direct_cmd_desc(&desc,
385 i40e_aqc_opc_queue_shutdown);
386
387 if (unloading)
388 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
389 status = i40evf_asq_send_command(hw, &desc, NULL, 0, NULL);
390
391 return status;
392}
393
394/**
395 * i40e_aq_get_set_rss_lut
396 * @hw: pointer to the hardware structure
397 * @vsi_id: vsi fw index
398 * @pf_lut: for PF table set true, for VSI table set false
399 * @lut: pointer to the lut buffer provided by the caller
400 * @lut_size: size of the lut buffer
401 * @set: set true to set the table, false to get the table
402 *
403 * Internal function to get or set RSS look up table
404 **/
405static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
406 u16 vsi_id, bool pf_lut,
407 u8 *lut, u16 lut_size,
408 bool set)
409{
410 i40e_status status;
411 struct i40e_aq_desc desc;
412 struct i40e_aqc_get_set_rss_lut *cmd_resp =
413 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
414
415 if (set)
416 i40evf_fill_default_direct_cmd_desc(&desc,
417 i40e_aqc_opc_set_rss_lut);
418 else
419 i40evf_fill_default_direct_cmd_desc(&desc,
420 i40e_aqc_opc_get_rss_lut);
421
422 /* Indirect command */
423 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
424 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
425
426 cmd_resp->vsi_id =
427 cpu_to_le16((u16)((vsi_id <<
428 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
429 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
430 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
431
432 if (pf_lut)
433 cmd_resp->flags |= cpu_to_le16((u16)
434 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
435 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
436 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
437 else
438 cmd_resp->flags |= cpu_to_le16((u16)
439 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
440 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
441 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
442
443 status = i40evf_asq_send_command(hw, &desc, lut, lut_size, NULL);
444
445 return status;
446}
447
448/**
449 * i40evf_aq_get_rss_lut
450 * @hw: pointer to the hardware structure
451 * @vsi_id: vsi fw index
452 * @pf_lut: for PF table set true, for VSI table set false
453 * @lut: pointer to the lut buffer provided by the caller
454 * @lut_size: size of the lut buffer
455 *
456 * get the RSS lookup table, PF or VSI type
457 **/
458i40e_status i40evf_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
459 bool pf_lut, u8 *lut, u16 lut_size)
460{
461 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
462 false);
463}
464
465/**
466 * i40evf_aq_set_rss_lut
467 * @hw: pointer to the hardware structure
468 * @vsi_id: vsi fw index
469 * @pf_lut: for PF table set true, for VSI table set false
470 * @lut: pointer to the lut buffer provided by the caller
471 * @lut_size: size of the lut buffer
472 *
473 * set the RSS lookup table, PF or VSI type
474 **/
475i40e_status i40evf_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
476 bool pf_lut, u8 *lut, u16 lut_size)
477{
478 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
479}
480
481/**
482 * i40e_aq_get_set_rss_key
483 * @hw: pointer to the hw struct
484 * @vsi_id: vsi fw index
485 * @key: pointer to key info struct
486 * @set: set true to set the key, false to get the key
487 *
488 * get the RSS key per VSI
489 **/
490static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
491 u16 vsi_id,
492 struct i40e_aqc_get_set_rss_key_data *key,
493 bool set)
494{
495 i40e_status status;
496 struct i40e_aq_desc desc;
497 struct i40e_aqc_get_set_rss_key *cmd_resp =
498 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
499 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
500
501 if (set)
502 i40evf_fill_default_direct_cmd_desc(&desc,
503 i40e_aqc_opc_set_rss_key);
504 else
505 i40evf_fill_default_direct_cmd_desc(&desc,
506 i40e_aqc_opc_get_rss_key);
507
508 /* Indirect command */
509 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
510 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
511
512 cmd_resp->vsi_id =
513 cpu_to_le16((u16)((vsi_id <<
514 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
515 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
516 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
517
518 status = i40evf_asq_send_command(hw, &desc, key, key_size, NULL);
519
520 return status;
521}
522
523/**
524 * i40evf_aq_get_rss_key
525 * @hw: pointer to the hw struct
526 * @vsi_id: vsi fw index
527 * @key: pointer to key info struct
528 *
529 **/
530i40e_status i40evf_aq_get_rss_key(struct i40e_hw *hw,
531 u16 vsi_id,
532 struct i40e_aqc_get_set_rss_key_data *key)
533{
534 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
535}
536
537/**
538 * i40evf_aq_set_rss_key
539 * @hw: pointer to the hw struct
540 * @vsi_id: vsi fw index
541 * @key: pointer to key info struct
542 *
543 * set the RSS key per VSI
544 **/
545i40e_status i40evf_aq_set_rss_key(struct i40e_hw *hw,
546 u16 vsi_id,
547 struct i40e_aqc_get_set_rss_key_data *key)
548{
549 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
550}
551
552
553/* The i40evf_ptype_lookup table is used to convert from the 8-bit ptype in the
554 * hardware to a bit-field that can be used by SW to more easily determine the
555 * packet type.
556 *
557 * Macros are used to shorten the table lines and make this table human
558 * readable.
559 *
560 * We store the PTYPE in the top byte of the bit field - this is just so that
561 * we can check that the table doesn't have a row missing, as the index into
562 * the table should be the PTYPE.
563 *
564 * Typical work flow:
565 *
566 * IF NOT i40evf_ptype_lookup[ptype].known
567 * THEN
568 * Packet is unknown
569 * ELSE IF i40evf_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
570 * Use the rest of the fields to look at the tunnels, inner protocols, etc
571 * ELSE
572 * Use the enum i40e_rx_l2_ptype to decode the packet type
573 * ENDIF
574 */
575
576/* macro to make the table lines short */
577#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
578 { PTYPE, \
579 1, \
580 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
581 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
582 I40E_RX_PTYPE_##OUTER_FRAG, \
583 I40E_RX_PTYPE_TUNNEL_##T, \
584 I40E_RX_PTYPE_TUNNEL_END_##TE, \
585 I40E_RX_PTYPE_##TEF, \
586 I40E_RX_PTYPE_INNER_PROT_##I, \
587 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
588
589#define I40E_PTT_UNUSED_ENTRY(PTYPE) \
590 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
591
592/* shorter macros makes the table fit but are terse */
593#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
594#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
595#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
596
597/* Lookup table mapping the HW PTYPE to the bit field for decoding */
598struct i40e_rx_ptype_decoded i40evf_ptype_lookup[] = {
599 /* L2 Packet types */
600 I40E_PTT_UNUSED_ENTRY(0),
601 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
602 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
603 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
604 I40E_PTT_UNUSED_ENTRY(4),
605 I40E_PTT_UNUSED_ENTRY(5),
606 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
607 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
608 I40E_PTT_UNUSED_ENTRY(8),
609 I40E_PTT_UNUSED_ENTRY(9),
610 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
611 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
612 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
613 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
614 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
615 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
616 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
617 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
618 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
619 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
620 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
621 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
622
623 /* Non Tunneled IPv4 */
624 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
625 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
626 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
627 I40E_PTT_UNUSED_ENTRY(25),
628 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
629 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
630 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
631
632 /* IPv4 --> IPv4 */
633 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
634 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
635 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
636 I40E_PTT_UNUSED_ENTRY(32),
637 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
638 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
639 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
640
641 /* IPv4 --> IPv6 */
642 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
643 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
644 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
645 I40E_PTT_UNUSED_ENTRY(39),
646 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
647 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
648 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
649
650 /* IPv4 --> GRE/NAT */
651 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
652
653 /* IPv4 --> GRE/NAT --> IPv4 */
654 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
655 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
656 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
657 I40E_PTT_UNUSED_ENTRY(47),
658 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
659 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
660 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
661
662 /* IPv4 --> GRE/NAT --> IPv6 */
663 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
664 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
665 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
666 I40E_PTT_UNUSED_ENTRY(54),
667 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
668 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
669 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
670
671 /* IPv4 --> GRE/NAT --> MAC */
672 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
673
674 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
675 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
676 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
677 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
678 I40E_PTT_UNUSED_ENTRY(62),
679 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
680 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
681 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
682
683 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
684 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
685 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
686 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
687 I40E_PTT_UNUSED_ENTRY(69),
688 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
689 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
690 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
691
692 /* IPv4 --> GRE/NAT --> MAC/VLAN */
693 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
694
695 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
696 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
697 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
698 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
699 I40E_PTT_UNUSED_ENTRY(77),
700 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
701 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
702 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
703
704 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
705 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
706 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
707 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
708 I40E_PTT_UNUSED_ENTRY(84),
709 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
710 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
711 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
712
713 /* Non Tunneled IPv6 */
714 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
715 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
716 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
717 I40E_PTT_UNUSED_ENTRY(91),
718 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
719 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
720 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
721
722 /* IPv6 --> IPv4 */
723 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
724 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
725 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
726 I40E_PTT_UNUSED_ENTRY(98),
727 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
728 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
729 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
730
731 /* IPv6 --> IPv6 */
732 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
733 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
734 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
735 I40E_PTT_UNUSED_ENTRY(105),
736 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
737 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
738 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
739
740 /* IPv6 --> GRE/NAT */
741 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
742
743 /* IPv6 --> GRE/NAT -> IPv4 */
744 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
745 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
746 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
747 I40E_PTT_UNUSED_ENTRY(113),
748 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
749 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
750 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
751
752 /* IPv6 --> GRE/NAT -> IPv6 */
753 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
754 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
755 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
756 I40E_PTT_UNUSED_ENTRY(120),
757 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
758 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
759 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
760
761 /* IPv6 --> GRE/NAT -> MAC */
762 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
763
764 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
765 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
766 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
767 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
768 I40E_PTT_UNUSED_ENTRY(128),
769 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
770 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
771 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
772
773 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
774 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
775 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
776 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
777 I40E_PTT_UNUSED_ENTRY(135),
778 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
779 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
780 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
781
782 /* IPv6 --> GRE/NAT -> MAC/VLAN */
783 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
784
785 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
786 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
787 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
788 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
789 I40E_PTT_UNUSED_ENTRY(143),
790 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
791 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
792 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
793
794 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
795 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
796 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
797 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
798 I40E_PTT_UNUSED_ENTRY(150),
799 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
800 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
801 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
802
803 /* unused entries */
804 I40E_PTT_UNUSED_ENTRY(154),
805 I40E_PTT_UNUSED_ENTRY(155),
806 I40E_PTT_UNUSED_ENTRY(156),
807 I40E_PTT_UNUSED_ENTRY(157),
808 I40E_PTT_UNUSED_ENTRY(158),
809 I40E_PTT_UNUSED_ENTRY(159),
810
811 I40E_PTT_UNUSED_ENTRY(160),
812 I40E_PTT_UNUSED_ENTRY(161),
813 I40E_PTT_UNUSED_ENTRY(162),
814 I40E_PTT_UNUSED_ENTRY(163),
815 I40E_PTT_UNUSED_ENTRY(164),
816 I40E_PTT_UNUSED_ENTRY(165),
817 I40E_PTT_UNUSED_ENTRY(166),
818 I40E_PTT_UNUSED_ENTRY(167),
819 I40E_PTT_UNUSED_ENTRY(168),
820 I40E_PTT_UNUSED_ENTRY(169),
821
822 I40E_PTT_UNUSED_ENTRY(170),
823 I40E_PTT_UNUSED_ENTRY(171),
824 I40E_PTT_UNUSED_ENTRY(172),
825 I40E_PTT_UNUSED_ENTRY(173),
826 I40E_PTT_UNUSED_ENTRY(174),
827 I40E_PTT_UNUSED_ENTRY(175),
828 I40E_PTT_UNUSED_ENTRY(176),
829 I40E_PTT_UNUSED_ENTRY(177),
830 I40E_PTT_UNUSED_ENTRY(178),
831 I40E_PTT_UNUSED_ENTRY(179),
832
833 I40E_PTT_UNUSED_ENTRY(180),
834 I40E_PTT_UNUSED_ENTRY(181),
835 I40E_PTT_UNUSED_ENTRY(182),
836 I40E_PTT_UNUSED_ENTRY(183),
837 I40E_PTT_UNUSED_ENTRY(184),
838 I40E_PTT_UNUSED_ENTRY(185),
839 I40E_PTT_UNUSED_ENTRY(186),
840 I40E_PTT_UNUSED_ENTRY(187),
841 I40E_PTT_UNUSED_ENTRY(188),
842 I40E_PTT_UNUSED_ENTRY(189),
843
844 I40E_PTT_UNUSED_ENTRY(190),
845 I40E_PTT_UNUSED_ENTRY(191),
846 I40E_PTT_UNUSED_ENTRY(192),
847 I40E_PTT_UNUSED_ENTRY(193),
848 I40E_PTT_UNUSED_ENTRY(194),
849 I40E_PTT_UNUSED_ENTRY(195),
850 I40E_PTT_UNUSED_ENTRY(196),
851 I40E_PTT_UNUSED_ENTRY(197),
852 I40E_PTT_UNUSED_ENTRY(198),
853 I40E_PTT_UNUSED_ENTRY(199),
854
855 I40E_PTT_UNUSED_ENTRY(200),
856 I40E_PTT_UNUSED_ENTRY(201),
857 I40E_PTT_UNUSED_ENTRY(202),
858 I40E_PTT_UNUSED_ENTRY(203),
859 I40E_PTT_UNUSED_ENTRY(204),
860 I40E_PTT_UNUSED_ENTRY(205),
861 I40E_PTT_UNUSED_ENTRY(206),
862 I40E_PTT_UNUSED_ENTRY(207),
863 I40E_PTT_UNUSED_ENTRY(208),
864 I40E_PTT_UNUSED_ENTRY(209),
865
866 I40E_PTT_UNUSED_ENTRY(210),
867 I40E_PTT_UNUSED_ENTRY(211),
868 I40E_PTT_UNUSED_ENTRY(212),
869 I40E_PTT_UNUSED_ENTRY(213),
870 I40E_PTT_UNUSED_ENTRY(214),
871 I40E_PTT_UNUSED_ENTRY(215),
872 I40E_PTT_UNUSED_ENTRY(216),
873 I40E_PTT_UNUSED_ENTRY(217),
874 I40E_PTT_UNUSED_ENTRY(218),
875 I40E_PTT_UNUSED_ENTRY(219),
876
877 I40E_PTT_UNUSED_ENTRY(220),
878 I40E_PTT_UNUSED_ENTRY(221),
879 I40E_PTT_UNUSED_ENTRY(222),
880 I40E_PTT_UNUSED_ENTRY(223),
881 I40E_PTT_UNUSED_ENTRY(224),
882 I40E_PTT_UNUSED_ENTRY(225),
883 I40E_PTT_UNUSED_ENTRY(226),
884 I40E_PTT_UNUSED_ENTRY(227),
885 I40E_PTT_UNUSED_ENTRY(228),
886 I40E_PTT_UNUSED_ENTRY(229),
887
888 I40E_PTT_UNUSED_ENTRY(230),
889 I40E_PTT_UNUSED_ENTRY(231),
890 I40E_PTT_UNUSED_ENTRY(232),
891 I40E_PTT_UNUSED_ENTRY(233),
892 I40E_PTT_UNUSED_ENTRY(234),
893 I40E_PTT_UNUSED_ENTRY(235),
894 I40E_PTT_UNUSED_ENTRY(236),
895 I40E_PTT_UNUSED_ENTRY(237),
896 I40E_PTT_UNUSED_ENTRY(238),
897 I40E_PTT_UNUSED_ENTRY(239),
898
899 I40E_PTT_UNUSED_ENTRY(240),
900 I40E_PTT_UNUSED_ENTRY(241),
901 I40E_PTT_UNUSED_ENTRY(242),
902 I40E_PTT_UNUSED_ENTRY(243),
903 I40E_PTT_UNUSED_ENTRY(244),
904 I40E_PTT_UNUSED_ENTRY(245),
905 I40E_PTT_UNUSED_ENTRY(246),
906 I40E_PTT_UNUSED_ENTRY(247),
907 I40E_PTT_UNUSED_ENTRY(248),
908 I40E_PTT_UNUSED_ENTRY(249),
909
910 I40E_PTT_UNUSED_ENTRY(250),
911 I40E_PTT_UNUSED_ENTRY(251),
912 I40E_PTT_UNUSED_ENTRY(252),
913 I40E_PTT_UNUSED_ENTRY(253),
914 I40E_PTT_UNUSED_ENTRY(254),
915 I40E_PTT_UNUSED_ENTRY(255)
916};
917
918/**
919 * i40evf_aq_rx_ctl_read_register - use FW to read from an Rx control register
920 * @hw: pointer to the hw struct
921 * @reg_addr: register address
922 * @reg_val: ptr to register value
923 * @cmd_details: pointer to command details structure or NULL
924 *
925 * Use the firmware to read the Rx control register,
926 * especially useful if the Rx unit is under heavy pressure
927 **/
928i40e_status i40evf_aq_rx_ctl_read_register(struct i40e_hw *hw,
929 u32 reg_addr, u32 *reg_val,
930 struct i40e_asq_cmd_details *cmd_details)
931{
932 struct i40e_aq_desc desc;
933 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
934 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
935 i40e_status status;
936
937 if (!reg_val)
938 return I40E_ERR_PARAM;
939
940 i40evf_fill_default_direct_cmd_desc(&desc,
941 i40e_aqc_opc_rx_ctl_reg_read);
942
943 cmd_resp->address = cpu_to_le32(reg_addr);
944
945 status = i40evf_asq_send_command(hw, &desc, NULL, 0, cmd_details);
946
947 if (status == 0)
948 *reg_val = le32_to_cpu(cmd_resp->value);
949
950 return status;
951}
952
953/**
954 * i40evf_read_rx_ctl - read from an Rx control register
955 * @hw: pointer to the hw struct
956 * @reg_addr: register address
957 **/
958u32 i40evf_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
959{
960 i40e_status status = 0;
961 bool use_register;
962 int retry = 5;
963 u32 val = 0;
964
965 use_register = (((hw->aq.api_maj_ver == 1) &&
966 (hw->aq.api_min_ver < 5)) ||
967 (hw->mac.type == I40E_MAC_X722));
968 if (!use_register) {
969do_retry:
970 status = i40evf_aq_rx_ctl_read_register(hw, reg_addr,
971 &val, NULL);
972 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
973 usleep_range(1000, 2000);
974 retry--;
975 goto do_retry;
976 }
977 }
978
979 /* if the AQ access failed, try the old-fashioned way */
980 if (status || use_register)
981 val = rd32(hw, reg_addr);
982
983 return val;
984}
985
986/**
987 * i40evf_aq_rx_ctl_write_register
988 * @hw: pointer to the hw struct
989 * @reg_addr: register address
990 * @reg_val: register value
991 * @cmd_details: pointer to command details structure or NULL
992 *
993 * Use the firmware to write to an Rx control register,
994 * especially useful if the Rx unit is under heavy pressure
995 **/
996i40e_status i40evf_aq_rx_ctl_write_register(struct i40e_hw *hw,
997 u32 reg_addr, u32 reg_val,
998 struct i40e_asq_cmd_details *cmd_details)
999{
1000 struct i40e_aq_desc desc;
1001 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
1002 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
1003 i40e_status status;
1004
1005 i40evf_fill_default_direct_cmd_desc(&desc,
1006 i40e_aqc_opc_rx_ctl_reg_write);
1007
1008 cmd->address = cpu_to_le32(reg_addr);
1009 cmd->value = cpu_to_le32(reg_val);
1010
1011 status = i40evf_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1012
1013 return status;
1014}
1015
1016/**
1017 * i40evf_write_rx_ctl - write to an Rx control register
1018 * @hw: pointer to the hw struct
1019 * @reg_addr: register address
1020 * @reg_val: register value
1021 **/
1022void i40evf_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
1023{
1024 i40e_status status = 0;
1025 bool use_register;
1026 int retry = 5;
1027
1028 use_register = (((hw->aq.api_maj_ver == 1) &&
1029 (hw->aq.api_min_ver < 5)) ||
1030 (hw->mac.type == I40E_MAC_X722));
1031 if (!use_register) {
1032do_retry:
1033 status = i40evf_aq_rx_ctl_write_register(hw, reg_addr,
1034 reg_val, NULL);
1035 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
1036 usleep_range(1000, 2000);
1037 retry--;
1038 goto do_retry;
1039 }
1040 }
1041
1042 /* if the AQ access failed, try the old-fashioned way */
1043 if (status || use_register)
1044 wr32(hw, reg_addr, reg_val);
1045}
1046
1047/**
1048 * i40evf_aq_set_phy_register
1049 * @hw: pointer to the hw struct
1050 * @phy_select: select which phy should be accessed
1051 * @dev_addr: PHY device address
1052 * @reg_addr: PHY register address
1053 * @reg_val: new register value
1054 * @cmd_details: pointer to command details structure or NULL
1055 *
1056 * Reset the external PHY.
1057 **/
1058i40e_status i40evf_aq_set_phy_register(struct i40e_hw *hw,
1059 u8 phy_select, u8 dev_addr,
1060 u32 reg_addr, u32 reg_val,
1061 struct i40e_asq_cmd_details *cmd_details)
1062{
1063 struct i40e_aq_desc desc;
1064 struct i40e_aqc_phy_register_access *cmd =
1065 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
1066 i40e_status status;
1067
1068 i40evf_fill_default_direct_cmd_desc(&desc,
1069 i40e_aqc_opc_set_phy_register);
1070
1071 cmd->phy_interface = phy_select;
1072 cmd->dev_address = dev_addr;
1073 cmd->reg_address = cpu_to_le32(reg_addr);
1074 cmd->reg_value = cpu_to_le32(reg_val);
1075
1076 status = i40evf_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1077
1078 return status;
1079}
1080
1081/**
1082 * i40evf_aq_get_phy_register
1083 * @hw: pointer to the hw struct
1084 * @phy_select: select which phy should be accessed
1085 * @dev_addr: PHY device address
1086 * @reg_addr: PHY register address
1087 * @reg_val: read register value
1088 * @cmd_details: pointer to command details structure or NULL
1089 *
1090 * Reset the external PHY.
1091 **/
1092i40e_status i40evf_aq_get_phy_register(struct i40e_hw *hw,
1093 u8 phy_select, u8 dev_addr,
1094 u32 reg_addr, u32 *reg_val,
1095 struct i40e_asq_cmd_details *cmd_details)
1096{
1097 struct i40e_aq_desc desc;
1098 struct i40e_aqc_phy_register_access *cmd =
1099 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
1100 i40e_status status;
1101
1102 i40evf_fill_default_direct_cmd_desc(&desc,
1103 i40e_aqc_opc_get_phy_register);
1104
1105 cmd->phy_interface = phy_select;
1106 cmd->dev_address = dev_addr;
1107 cmd->reg_address = cpu_to_le32(reg_addr);
1108
1109 status = i40evf_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1110 if (!status)
1111 *reg_val = le32_to_cpu(cmd->reg_value);
1112
1113 return status;
1114}
1115
1116/**
1117 * i40e_aq_send_msg_to_pf
1118 * @hw: pointer to the hardware structure
1119 * @v_opcode: opcodes for VF-PF communication
1120 * @v_retval: return error code
1121 * @msg: pointer to the msg buffer
1122 * @msglen: msg length
1123 * @cmd_details: pointer to command details
1124 *
1125 * Send message to PF driver using admin queue. By default, this message
1126 * is sent asynchronously, i.e. i40evf_asq_send_command() does not wait for
1127 * completion before returning.
1128 **/
1129i40e_status i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
1130 enum virtchnl_ops v_opcode,
1131 i40e_status v_retval,
1132 u8 *msg, u16 msglen,
1133 struct i40e_asq_cmd_details *cmd_details)
1134{
1135 struct i40e_aq_desc desc;
1136 struct i40e_asq_cmd_details details;
1137 i40e_status status;
1138
1139 i40evf_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
1140 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
1141 desc.cookie_high = cpu_to_le32(v_opcode);
1142 desc.cookie_low = cpu_to_le32(v_retval);
1143 if (msglen) {
1144 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF
1145 | I40E_AQ_FLAG_RD));
1146 if (msglen > I40E_AQ_LARGE_BUF)
1147 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1148 desc.datalen = cpu_to_le16(msglen);
1149 }
1150 if (!cmd_details) {
1151 memset(&details, 0, sizeof(details));
1152 details.async = true;
1153 cmd_details = &details;
1154 }
1155 status = i40evf_asq_send_command(hw, &desc, msg, msglen, cmd_details);
1156 return status;
1157}
1158
1159/**
1160 * i40e_vf_parse_hw_config
1161 * @hw: pointer to the hardware structure
1162 * @msg: pointer to the virtual channel VF resource structure
1163 *
1164 * Given a VF resource message from the PF, populate the hw struct
1165 * with appropriate information.
1166 **/
1167void i40e_vf_parse_hw_config(struct i40e_hw *hw,
1168 struct virtchnl_vf_resource *msg)
1169{
1170 struct virtchnl_vsi_resource *vsi_res;
1171 int i;
1172
1173 vsi_res = &msg->vsi_res[0];
1174
1175 hw->dev_caps.num_vsis = msg->num_vsis;
1176 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
1177 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
1178 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
1179 hw->dev_caps.dcb = msg->vf_cap_flags &
1180 VIRTCHNL_VF_OFFLOAD_L2;
1181 hw->dev_caps.fcoe = 0;
1182 for (i = 0; i < msg->num_vsis; i++) {
1183 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
1184 ether_addr_copy(hw->mac.perm_addr,
1185 vsi_res->default_mac_addr);
1186 ether_addr_copy(hw->mac.addr,
1187 vsi_res->default_mac_addr);
1188 }
1189 vsi_res++;
1190 }
1191}
1192
1193/**
1194 * i40e_vf_reset
1195 * @hw: pointer to the hardware structure
1196 *
1197 * Send a VF_RESET message to the PF. Does not wait for response from PF
1198 * as none will be forthcoming. Immediately after calling this function,
1199 * the admin queue should be shut down and (optionally) reinitialized.
1200 **/
1201i40e_status i40e_vf_reset(struct i40e_hw *hw)
1202{
1203 return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
1204 0, NULL, 0, NULL);
1205}
1206
1207/**
1208 * i40evf_aq_write_ddp - Write dynamic device personalization (ddp)
1209 * @hw: pointer to the hw struct
1210 * @buff: command buffer (size in bytes = buff_size)
1211 * @buff_size: buffer size in bytes
1212 * @track_id: package tracking id
1213 * @error_offset: returns error offset
1214 * @error_info: returns error information
1215 * @cmd_details: pointer to command details structure or NULL
1216 **/
1217enum
1218i40e_status_code i40evf_aq_write_ddp(struct i40e_hw *hw, void *buff,
1219 u16 buff_size, u32 track_id,
1220 u32 *error_offset, u32 *error_info,
1221 struct i40e_asq_cmd_details *cmd_details)
1222{
1223 struct i40e_aq_desc desc;
1224 struct i40e_aqc_write_personalization_profile *cmd =
1225 (struct i40e_aqc_write_personalization_profile *)
1226 &desc.params.raw;
1227 struct i40e_aqc_write_ddp_resp *resp;
1228 i40e_status status;
1229
1230 i40evf_fill_default_direct_cmd_desc(&desc,
1231 i40e_aqc_opc_write_personalization_profile);
1232
1233 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
1234 if (buff_size > I40E_AQ_LARGE_BUF)
1235 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1236
1237 desc.datalen = cpu_to_le16(buff_size);
1238
1239 cmd->profile_track_id = cpu_to_le32(track_id);
1240
1241 status = i40evf_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1242 if (!status) {
1243 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
1244 if (error_offset)
1245 *error_offset = le32_to_cpu(resp->error_offset);
1246 if (error_info)
1247 *error_info = le32_to_cpu(resp->error_info);
1248 }
1249
1250 return status;
1251}
1252
1253/**
1254 * i40evf_aq_get_ddp_list - Read dynamic device personalization (ddp)
1255 * @hw: pointer to the hw struct
1256 * @buff: command buffer (size in bytes = buff_size)
1257 * @buff_size: buffer size in bytes
1258 * @cmd_details: pointer to command details structure or NULL
1259 **/
1260enum
1261i40e_status_code i40evf_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
1262 u16 buff_size, u8 flags,
1263 struct i40e_asq_cmd_details *cmd_details)
1264{
1265 struct i40e_aq_desc desc;
1266 struct i40e_aqc_get_applied_profiles *cmd =
1267 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
1268 i40e_status status;
1269
1270 i40evf_fill_default_direct_cmd_desc(&desc,
1271 i40e_aqc_opc_get_personalization_profile_list);
1272
1273 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1274 if (buff_size > I40E_AQ_LARGE_BUF)
1275 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1276 desc.datalen = cpu_to_le16(buff_size);
1277
1278 cmd->flags = flags;
1279
1280 status = i40evf_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1281
1282 return status;
1283}
1284
1285/**
1286 * i40evf_find_segment_in_package
1287 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
1288 * @pkg_hdr: pointer to the package header to be searched
1289 *
1290 * This function searches a package file for a particular segment type. On
1291 * success it returns a pointer to the segment header, otherwise it will
1292 * return NULL.
1293 **/
1294struct i40e_generic_seg_header *
1295i40evf_find_segment_in_package(u32 segment_type,
1296 struct i40e_package_header *pkg_hdr)
1297{
1298 struct i40e_generic_seg_header *segment;
1299 u32 i;
1300
1301 /* Search all package segments for the requested segment type */
1302 for (i = 0; i < pkg_hdr->segment_count; i++) {
1303 segment =
1304 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
1305 pkg_hdr->segment_offset[i]);
1306
1307 if (segment->type == segment_type)
1308 return segment;
1309 }
1310
1311 return NULL;
1312}
1313
1314/**
1315 * i40evf_write_profile
1316 * @hw: pointer to the hardware structure
1317 * @profile: pointer to the profile segment of the package to be downloaded
1318 * @track_id: package tracking id
1319 *
1320 * Handles the download of a complete package.
1321 */
1322enum i40e_status_code
1323i40evf_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
1324 u32 track_id)
1325{
1326 i40e_status status = 0;
1327 struct i40e_section_table *sec_tbl;
1328 struct i40e_profile_section_header *sec = NULL;
1329 u32 dev_cnt;
1330 u32 vendor_dev_id;
1331 u32 *nvm;
1332 u32 section_size = 0;
1333 u32 offset = 0, info = 0;
1334 u32 i;
1335
1336 dev_cnt = profile->device_table_count;
1337
1338 for (i = 0; i < dev_cnt; i++) {
1339 vendor_dev_id = profile->device_table[i].vendor_dev_id;
1340 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL)
1341 if (hw->device_id == (vendor_dev_id & 0xFFFF))
1342 break;
1343 }
1344 if (i == dev_cnt) {
1345 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support DDP");
1346 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1347 }
1348
1349 nvm = (u32 *)&profile->device_table[dev_cnt];
1350 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1];
1351
1352 for (i = 0; i < sec_tbl->section_count; i++) {
1353 sec = (struct i40e_profile_section_header *)((u8 *)profile +
1354 sec_tbl->section_offset[i]);
1355
1356 /* Skip 'AQ', 'note' and 'name' sections */
1357 if (sec->section.type != SECTION_TYPE_MMIO)
1358 continue;
1359
1360 section_size = sec->section.size +
1361 sizeof(struct i40e_profile_section_header);
1362
1363 /* Write profile */
1364 status = i40evf_aq_write_ddp(hw, (void *)sec, (u16)section_size,
1365 track_id, &offset, &info, NULL);
1366 if (status) {
1367 i40e_debug(hw, I40E_DEBUG_PACKAGE,
1368 "Failed to write profile: offset %d, info %d",
1369 offset, info);
1370 break;
1371 }
1372 }
1373 return status;
1374}
1375
1376/**
1377 * i40evf_add_pinfo_to_list
1378 * @hw: pointer to the hardware structure
1379 * @profile: pointer to the profile segment of the package
1380 * @profile_info_sec: buffer for information section
1381 * @track_id: package tracking id
1382 *
1383 * Register a profile to the list of loaded profiles.
1384 */
1385enum i40e_status_code
1386i40evf_add_pinfo_to_list(struct i40e_hw *hw,
1387 struct i40e_profile_segment *profile,
1388 u8 *profile_info_sec, u32 track_id)
1389{
1390 i40e_status status = 0;
1391 struct i40e_profile_section_header *sec = NULL;
1392 struct i40e_profile_info *pinfo;
1393 u32 offset = 0, info = 0;
1394
1395 sec = (struct i40e_profile_section_header *)profile_info_sec;
1396 sec->tbl_size = 1;
1397 sec->data_end = sizeof(struct i40e_profile_section_header) +
1398 sizeof(struct i40e_profile_info);
1399 sec->section.type = SECTION_TYPE_INFO;
1400 sec->section.offset = sizeof(struct i40e_profile_section_header);
1401 sec->section.size = sizeof(struct i40e_profile_info);
1402 pinfo = (struct i40e_profile_info *)(profile_info_sec +
1403 sec->section.offset);
1404 pinfo->track_id = track_id;
1405 pinfo->version = profile->version;
1406 pinfo->op = I40E_DDP_ADD_TRACKID;
1407 memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
1408
1409 status = i40evf_aq_write_ddp(hw, (void *)sec, sec->data_end,
1410 track_id, &offset, &info, NULL);
1411 return status;
1412}