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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * drivers/net/ethernet/ibm/emac/core.c
4 *
5 * Driver for PowerPC 4xx on-chip ethernet controller.
6 *
7 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
8 * <benh@kernel.crashing.org>
9 *
10 * Based on the arch/ppc version of the driver:
11 *
12 * Copyright (c) 2004, 2005 Zultys Technologies.
13 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
14 *
15 * Based on original work by
16 * Matt Porter <mporter@kernel.crashing.org>
17 * (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
18 * Armin Kuster <akuster@mvista.com>
19 * Johnnie Peters <jpeters@mvista.com>
20 */
21
22#include <linux/module.h>
23#include <linux/sched.h>
24#include <linux/string.h>
25#include <linux/errno.h>
26#include <linux/delay.h>
27#include <linux/types.h>
28#include <linux/pci.h>
29#include <linux/etherdevice.h>
30#include <linux/skbuff.h>
31#include <linux/crc32.h>
32#include <linux/ethtool.h>
33#include <linux/mii.h>
34#include <linux/bitops.h>
35#include <linux/of.h>
36#include <linux/of_address.h>
37#include <linux/of_irq.h>
38#include <linux/of_net.h>
39#include <linux/of_mdio.h>
40#include <linux/of_platform.h>
41#include <linux/platform_device.h>
42#include <linux/slab.h>
43
44#include <asm/processor.h>
45#include <asm/io.h>
46#include <asm/dma.h>
47#include <linux/uaccess.h>
48#include <asm/dcr.h>
49#include <asm/dcr-regs.h>
50
51#include "core.h"
52
53/*
54 * Lack of dma_unmap_???? calls is intentional.
55 *
56 * API-correct usage requires additional support state information to be
57 * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to
58 * EMAC design (e.g. TX buffer passed from network stack can be split into
59 * several BDs, dma_map_single/dma_map_page can be used to map particular BD),
60 * maintaining such information will add additional overhead.
61 * Current DMA API implementation for 4xx processors only ensures cache coherency
62 * and dma_unmap_???? routines are empty and are likely to stay this way.
63 * I decided to omit dma_unmap_??? calls because I don't want to add additional
64 * complexity just for the sake of following some abstract API, when it doesn't
65 * add any real benefit to the driver. I understand that this decision maybe
66 * controversial, but I really tried to make code API-correct and efficient
67 * at the same time and didn't come up with code I liked :(. --ebs
68 */
69
70#define DRV_NAME "emac"
71#define DRV_VERSION "3.54"
72#define DRV_DESC "PPC 4xx OCP EMAC driver"
73
74MODULE_DESCRIPTION(DRV_DESC);
75MODULE_AUTHOR
76 ("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>");
77MODULE_LICENSE("GPL");
78
79/* minimum number of free TX descriptors required to wake up TX process */
80#define EMAC_TX_WAKEUP_THRESH (NUM_TX_BUFF / 4)
81
82/* If packet size is less than this number, we allocate small skb and copy packet
83 * contents into it instead of just sending original big skb up
84 */
85#define EMAC_RX_COPY_THRESH CONFIG_IBM_EMAC_RX_COPY_THRESHOLD
86
87/* Since multiple EMACs share MDIO lines in various ways, we need
88 * to avoid re-using the same PHY ID in cases where the arch didn't
89 * setup precise phy_map entries
90 *
91 * XXX This is something that needs to be reworked as we can have multiple
92 * EMAC "sets" (multiple ASICs containing several EMACs) though we can
93 * probably require in that case to have explicit PHY IDs in the device-tree
94 */
95static u32 busy_phy_map;
96static DEFINE_MUTEX(emac_phy_map_lock);
97
98/* Having stable interface names is a doomed idea. However, it would be nice
99 * if we didn't have completely random interface names at boot too :-) It's
100 * just a matter of making everybody's life easier. Since we are doing
101 * threaded probing, it's a bit harder though. The base idea here is that
102 * we make up a list of all emacs in the device-tree before we register the
103 * driver. Every emac will then wait for the previous one in the list to
104 * initialize before itself. We should also keep that list ordered by
105 * cell_index.
106 * That list is only 4 entries long, meaning that additional EMACs don't
107 * get ordering guarantees unless EMAC_BOOT_LIST_SIZE is increased.
108 */
109
110#define EMAC_BOOT_LIST_SIZE 4
111static struct device_node *emac_boot_list[EMAC_BOOT_LIST_SIZE];
112
113/* I don't want to litter system log with timeout errors
114 * when we have brain-damaged PHY.
115 */
116static inline void emac_report_timeout_error(struct emac_instance *dev,
117 const char *error)
118{
119 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX |
120 EMAC_FTR_460EX_PHY_CLK_FIX |
121 EMAC_FTR_440EP_PHY_CLK_FIX))
122 DBG(dev, "%s" NL, error);
123 else if (net_ratelimit())
124 printk(KERN_ERR "%pOF: %s\n", dev->ofdev->dev.of_node, error);
125}
126
127/* EMAC PHY clock workaround:
128 * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX,
129 * which allows controlling each EMAC clock
130 */
131static inline void emac_rx_clk_tx(struct emac_instance *dev)
132{
133#ifdef CONFIG_PPC_DCR_NATIVE
134 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
135 dcri_clrset(SDR0, SDR0_MFR,
136 0, SDR0_MFR_ECS >> dev->cell_index);
137#endif
138}
139
140static inline void emac_rx_clk_default(struct emac_instance *dev)
141{
142#ifdef CONFIG_PPC_DCR_NATIVE
143 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
144 dcri_clrset(SDR0, SDR0_MFR,
145 SDR0_MFR_ECS >> dev->cell_index, 0);
146#endif
147}
148
149/* PHY polling intervals */
150#define PHY_POLL_LINK_ON HZ
151#define PHY_POLL_LINK_OFF (HZ / 5)
152
153/* Graceful stop timeouts in us.
154 * We should allow up to 1 frame time (full-duplex, ignoring collisions)
155 */
156#define STOP_TIMEOUT_10 1230
157#define STOP_TIMEOUT_100 124
158#define STOP_TIMEOUT_1000 13
159#define STOP_TIMEOUT_1000_JUMBO 73
160
161static unsigned char default_mcast_addr[] = {
162 0x01, 0x80, 0xC2, 0x00, 0x00, 0x01
163};
164
165/* Please, keep in sync with struct ibm_emac_stats/ibm_emac_error_stats */
166static const char emac_stats_keys[EMAC_ETHTOOL_STATS_COUNT][ETH_GSTRING_LEN] = {
167 "rx_packets", "rx_bytes", "tx_packets", "tx_bytes", "rx_packets_csum",
168 "tx_packets_csum", "tx_undo", "rx_dropped_stack", "rx_dropped_oom",
169 "rx_dropped_error", "rx_dropped_resize", "rx_dropped_mtu",
170 "rx_stopped", "rx_bd_errors", "rx_bd_overrun", "rx_bd_bad_packet",
171 "rx_bd_runt_packet", "rx_bd_short_event", "rx_bd_alignment_error",
172 "rx_bd_bad_fcs", "rx_bd_packet_too_long", "rx_bd_out_of_range",
173 "rx_bd_in_range", "rx_parity", "rx_fifo_overrun", "rx_overrun",
174 "rx_bad_packet", "rx_runt_packet", "rx_short_event",
175 "rx_alignment_error", "rx_bad_fcs", "rx_packet_too_long",
176 "rx_out_of_range", "rx_in_range", "tx_dropped", "tx_bd_errors",
177 "tx_bd_bad_fcs", "tx_bd_carrier_loss", "tx_bd_excessive_deferral",
178 "tx_bd_excessive_collisions", "tx_bd_late_collision",
179 "tx_bd_multple_collisions", "tx_bd_single_collision",
180 "tx_bd_underrun", "tx_bd_sqe", "tx_parity", "tx_underrun", "tx_sqe",
181 "tx_errors"
182};
183
184static irqreturn_t emac_irq(int irq, void *dev_instance);
185static void emac_clean_tx_ring(struct emac_instance *dev);
186static void __emac_set_multicast_list(struct emac_instance *dev);
187
188static inline int emac_phy_supports_gige(int phy_mode)
189{
190 return phy_interface_mode_is_rgmii(phy_mode) ||
191 phy_mode == PHY_INTERFACE_MODE_GMII ||
192 phy_mode == PHY_INTERFACE_MODE_SGMII ||
193 phy_mode == PHY_INTERFACE_MODE_TBI ||
194 phy_mode == PHY_INTERFACE_MODE_RTBI;
195}
196
197static inline int emac_phy_gpcs(int phy_mode)
198{
199 return phy_mode == PHY_INTERFACE_MODE_SGMII ||
200 phy_mode == PHY_INTERFACE_MODE_TBI ||
201 phy_mode == PHY_INTERFACE_MODE_RTBI;
202}
203
204static inline void emac_tx_enable(struct emac_instance *dev)
205{
206 struct emac_regs __iomem *p = dev->emacp;
207 u32 r;
208
209 DBG(dev, "tx_enable" NL);
210
211 r = in_be32(&p->mr0);
212 if (!(r & EMAC_MR0_TXE))
213 out_be32(&p->mr0, r | EMAC_MR0_TXE);
214}
215
216static void emac_tx_disable(struct emac_instance *dev)
217{
218 struct emac_regs __iomem *p = dev->emacp;
219 u32 r;
220
221 DBG(dev, "tx_disable" NL);
222
223 r = in_be32(&p->mr0);
224 if (r & EMAC_MR0_TXE) {
225 int n = dev->stop_timeout;
226 out_be32(&p->mr0, r & ~EMAC_MR0_TXE);
227 while (!(in_be32(&p->mr0) & EMAC_MR0_TXI) && n) {
228 udelay(1);
229 --n;
230 }
231 if (unlikely(!n))
232 emac_report_timeout_error(dev, "TX disable timeout");
233 }
234}
235
236static void emac_rx_enable(struct emac_instance *dev)
237{
238 struct emac_regs __iomem *p = dev->emacp;
239 u32 r;
240
241 if (unlikely(test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags)))
242 goto out;
243
244 DBG(dev, "rx_enable" NL);
245
246 r = in_be32(&p->mr0);
247 if (!(r & EMAC_MR0_RXE)) {
248 if (unlikely(!(r & EMAC_MR0_RXI))) {
249 /* Wait if previous async disable is still in progress */
250 int n = dev->stop_timeout;
251 while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
252 udelay(1);
253 --n;
254 }
255 if (unlikely(!n))
256 emac_report_timeout_error(dev,
257 "RX disable timeout");
258 }
259 out_be32(&p->mr0, r | EMAC_MR0_RXE);
260 }
261 out:
262 ;
263}
264
265static void emac_rx_disable(struct emac_instance *dev)
266{
267 struct emac_regs __iomem *p = dev->emacp;
268 u32 r;
269
270 DBG(dev, "rx_disable" NL);
271
272 r = in_be32(&p->mr0);
273 if (r & EMAC_MR0_RXE) {
274 int n = dev->stop_timeout;
275 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
276 while (!(in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
277 udelay(1);
278 --n;
279 }
280 if (unlikely(!n))
281 emac_report_timeout_error(dev, "RX disable timeout");
282 }
283}
284
285static inline void emac_netif_stop(struct emac_instance *dev)
286{
287 netif_tx_lock_bh(dev->ndev);
288 netif_addr_lock(dev->ndev);
289 dev->no_mcast = 1;
290 netif_addr_unlock(dev->ndev);
291 netif_tx_unlock_bh(dev->ndev);
292 netif_trans_update(dev->ndev); /* prevent tx timeout */
293 mal_poll_disable(dev->mal, &dev->commac);
294 netif_tx_disable(dev->ndev);
295}
296
297static inline void emac_netif_start(struct emac_instance *dev)
298{
299 netif_tx_lock_bh(dev->ndev);
300 netif_addr_lock(dev->ndev);
301 dev->no_mcast = 0;
302 if (dev->mcast_pending && netif_running(dev->ndev))
303 __emac_set_multicast_list(dev);
304 netif_addr_unlock(dev->ndev);
305 netif_tx_unlock_bh(dev->ndev);
306
307 netif_wake_queue(dev->ndev);
308
309 /* NOTE: unconditional netif_wake_queue is only appropriate
310 * so long as all callers are assured to have free tx slots
311 * (taken from tg3... though the case where that is wrong is
312 * not terribly harmful)
313 */
314 mal_poll_enable(dev->mal, &dev->commac);
315}
316
317static inline void emac_rx_disable_async(struct emac_instance *dev)
318{
319 struct emac_regs __iomem *p = dev->emacp;
320 u32 r;
321
322 DBG(dev, "rx_disable_async" NL);
323
324 r = in_be32(&p->mr0);
325 if (r & EMAC_MR0_RXE)
326 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
327}
328
329static int emac_reset(struct emac_instance *dev)
330{
331 struct emac_regs __iomem *p = dev->emacp;
332 int n = 20;
333 bool __maybe_unused try_internal_clock = false;
334
335 DBG(dev, "reset" NL);
336
337 if (!dev->reset_failed) {
338 /* 40x erratum suggests stopping RX channel before reset,
339 * we stop TX as well
340 */
341 emac_rx_disable(dev);
342 emac_tx_disable(dev);
343 }
344
345#ifdef CONFIG_PPC_DCR_NATIVE
346do_retry:
347 /*
348 * PPC460EX/GT Embedded Processor Advanced User's Manual
349 * section 28.10.1 Mode Register 0 (EMACx_MR0) states:
350 * Note: The PHY must provide a TX Clk in order to perform a soft reset
351 * of the EMAC. If none is present, select the internal clock
352 * (SDR0_ETH_CFG[EMACx_PHY_CLK] = 1).
353 * After a soft reset, select the external clock.
354 *
355 * The AR8035-A PHY Meraki MR24 does not provide a TX Clk if the
356 * ethernet cable is not attached. This causes the reset to timeout
357 * and the PHY detection code in emac_init_phy() is unable to
358 * communicate and detect the AR8035-A PHY. As a result, the emac
359 * driver bails out early and the user has no ethernet.
360 * In order to stay compatible with existing configurations, the
361 * driver will temporarily switch to the internal clock, after
362 * the first reset fails.
363 */
364 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
365 if (try_internal_clock || (dev->phy_address == 0xffffffff &&
366 dev->phy_map == 0xffffffff)) {
367 /* No PHY: select internal loop clock before reset */
368 dcri_clrset(SDR0, SDR0_ETH_CFG,
369 0, SDR0_ETH_CFG_ECS << dev->cell_index);
370 } else {
371 /* PHY present: select external clock before reset */
372 dcri_clrset(SDR0, SDR0_ETH_CFG,
373 SDR0_ETH_CFG_ECS << dev->cell_index, 0);
374 }
375 }
376#endif
377
378 out_be32(&p->mr0, EMAC_MR0_SRST);
379 while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n)
380 --n;
381
382#ifdef CONFIG_PPC_DCR_NATIVE
383 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
384 if (!n && !try_internal_clock) {
385 /* first attempt has timed out. */
386 n = 20;
387 try_internal_clock = true;
388 goto do_retry;
389 }
390
391 if (try_internal_clock || (dev->phy_address == 0xffffffff &&
392 dev->phy_map == 0xffffffff)) {
393 /* No PHY: restore external clock source after reset */
394 dcri_clrset(SDR0, SDR0_ETH_CFG,
395 SDR0_ETH_CFG_ECS << dev->cell_index, 0);
396 }
397 }
398#endif
399
400 if (n) {
401 dev->reset_failed = 0;
402 return 0;
403 } else {
404 emac_report_timeout_error(dev, "reset timeout");
405 dev->reset_failed = 1;
406 return -ETIMEDOUT;
407 }
408}
409
410static void emac_hash_mc(struct emac_instance *dev)
411{
412 u32 __iomem *gaht_base = emac_gaht_base(dev);
413 const int regs = EMAC_XAHT_REGS(dev);
414 u32 gaht_temp[EMAC_XAHT_MAX_REGS];
415 struct netdev_hw_addr *ha;
416 int i;
417
418 DBG(dev, "hash_mc %d" NL, netdev_mc_count(dev->ndev));
419
420 memset(gaht_temp, 0, sizeof (gaht_temp));
421
422 netdev_for_each_mc_addr(ha, dev->ndev) {
423 int slot, reg, mask;
424 DBG2(dev, "mc %pM" NL, ha->addr);
425
426 slot = EMAC_XAHT_CRC_TO_SLOT(dev,
427 ether_crc(ETH_ALEN, ha->addr));
428 reg = EMAC_XAHT_SLOT_TO_REG(dev, slot);
429 mask = EMAC_XAHT_SLOT_TO_MASK(dev, slot);
430
431 gaht_temp[reg] |= mask;
432 }
433
434 for (i = 0; i < regs; i++)
435 out_be32(gaht_base + i, gaht_temp[i]);
436}
437
438static inline u32 emac_iff2rmr(struct net_device *ndev)
439{
440 struct emac_instance *dev = netdev_priv(ndev);
441 u32 r;
442
443 r = EMAC_RMR_SP | EMAC_RMR_SFCS | EMAC_RMR_IAE | EMAC_RMR_BAE;
444
445 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
446 r |= EMAC4_RMR_BASE;
447 else
448 r |= EMAC_RMR_BASE;
449
450 if (ndev->flags & IFF_PROMISC)
451 r |= EMAC_RMR_PME;
452 else if (ndev->flags & IFF_ALLMULTI ||
453 (netdev_mc_count(ndev) > EMAC_XAHT_SLOTS(dev)))
454 r |= EMAC_RMR_PMME;
455 else if (!netdev_mc_empty(ndev))
456 r |= EMAC_RMR_MAE;
457
458 if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) {
459 r &= ~EMAC4_RMR_MJS_MASK;
460 r |= EMAC4_RMR_MJS(ndev->mtu);
461 }
462
463 return r;
464}
465
466static u32 __emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
467{
468 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC_MR1_TR0_MULT;
469
470 DBG2(dev, "__emac_calc_base_mr1" NL);
471
472 switch(tx_size) {
473 case 2048:
474 ret |= EMAC_MR1_TFS_2K;
475 break;
476 default:
477 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n",
478 dev->ndev->name, tx_size);
479 }
480
481 switch(rx_size) {
482 case 16384:
483 ret |= EMAC_MR1_RFS_16K;
484 break;
485 case 4096:
486 ret |= EMAC_MR1_RFS_4K;
487 break;
488 default:
489 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
490 dev->ndev->name, rx_size);
491 }
492
493 return ret;
494}
495
496static u32 __emac4_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
497{
498 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC4_MR1_TR |
499 EMAC4_MR1_OBCI(dev->opb_bus_freq / 1000000);
500
501 DBG2(dev, "__emac4_calc_base_mr1" NL);
502
503 switch(tx_size) {
504 case 16384:
505 ret |= EMAC4_MR1_TFS_16K;
506 break;
507 case 8192:
508 ret |= EMAC4_MR1_TFS_8K;
509 break;
510 case 4096:
511 ret |= EMAC4_MR1_TFS_4K;
512 break;
513 case 2048:
514 ret |= EMAC4_MR1_TFS_2K;
515 break;
516 default:
517 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n",
518 dev->ndev->name, tx_size);
519 }
520
521 switch(rx_size) {
522 case 16384:
523 ret |= EMAC4_MR1_RFS_16K;
524 break;
525 case 8192:
526 ret |= EMAC4_MR1_RFS_8K;
527 break;
528 case 4096:
529 ret |= EMAC4_MR1_RFS_4K;
530 break;
531 case 2048:
532 ret |= EMAC4_MR1_RFS_2K;
533 break;
534 default:
535 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
536 dev->ndev->name, rx_size);
537 }
538
539 return ret;
540}
541
542static u32 emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
543{
544 return emac_has_feature(dev, EMAC_FTR_EMAC4) ?
545 __emac4_calc_base_mr1(dev, tx_size, rx_size) :
546 __emac_calc_base_mr1(dev, tx_size, rx_size);
547}
548
549static inline u32 emac_calc_trtr(struct emac_instance *dev, unsigned int size)
550{
551 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
552 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT_EMAC4;
553 else
554 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT;
555}
556
557static inline u32 emac_calc_rwmr(struct emac_instance *dev,
558 unsigned int low, unsigned int high)
559{
560 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
561 return (low << 22) | ( (high & 0x3ff) << 6);
562 else
563 return (low << 23) | ( (high & 0x1ff) << 7);
564}
565
566static int emac_configure(struct emac_instance *dev)
567{
568 struct emac_regs __iomem *p = dev->emacp;
569 struct net_device *ndev = dev->ndev;
570 int tx_size, rx_size, link = netif_carrier_ok(dev->ndev);
571 u32 r, mr1 = 0;
572
573 DBG(dev, "configure" NL);
574
575 if (!link) {
576 out_be32(&p->mr1, in_be32(&p->mr1)
577 | EMAC_MR1_FDE | EMAC_MR1_ILE);
578 udelay(100);
579 } else if (emac_reset(dev) < 0)
580 return -ETIMEDOUT;
581
582 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
583 tah_reset(dev->tah_dev);
584
585 DBG(dev, " link = %d duplex = %d, pause = %d, asym_pause = %d\n",
586 link, dev->phy.duplex, dev->phy.pause, dev->phy.asym_pause);
587
588 /* Default fifo sizes */
589 tx_size = dev->tx_fifo_size;
590 rx_size = dev->rx_fifo_size;
591
592 /* No link, force loopback */
593 if (!link)
594 mr1 = EMAC_MR1_FDE | EMAC_MR1_ILE;
595
596 /* Check for full duplex */
597 else if (dev->phy.duplex == DUPLEX_FULL)
598 mr1 |= EMAC_MR1_FDE | EMAC_MR1_MWSW_001;
599
600 /* Adjust fifo sizes, mr1 and timeouts based on link speed */
601 dev->stop_timeout = STOP_TIMEOUT_10;
602 switch (dev->phy.speed) {
603 case SPEED_1000:
604 if (emac_phy_gpcs(dev->phy.mode)) {
605 mr1 |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_MF_IPPA(
606 (dev->phy.gpcs_address != 0xffffffff) ?
607 dev->phy.gpcs_address : dev->phy.address);
608
609 /* Put some arbitrary OUI, Manuf & Rev IDs so we can
610 * identify this GPCS PHY later.
611 */
612 out_be32(&p->u1.emac4.ipcr, 0xdeadbeef);
613 } else
614 mr1 |= EMAC_MR1_MF_1000;
615
616 /* Extended fifo sizes */
617 tx_size = dev->tx_fifo_size_gige;
618 rx_size = dev->rx_fifo_size_gige;
619
620 if (dev->ndev->mtu > ETH_DATA_LEN) {
621 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
622 mr1 |= EMAC4_MR1_JPSM;
623 else
624 mr1 |= EMAC_MR1_JPSM;
625 dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO;
626 } else
627 dev->stop_timeout = STOP_TIMEOUT_1000;
628 break;
629 case SPEED_100:
630 mr1 |= EMAC_MR1_MF_100;
631 dev->stop_timeout = STOP_TIMEOUT_100;
632 break;
633 default: /* make gcc happy */
634 break;
635 }
636
637 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
638 rgmii_set_speed(dev->rgmii_dev, dev->rgmii_port,
639 dev->phy.speed);
640 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
641 zmii_set_speed(dev->zmii_dev, dev->zmii_port, dev->phy.speed);
642
643 /* on 40x erratum forces us to NOT use integrated flow control,
644 * let's hope it works on 44x ;)
645 */
646 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x) &&
647 dev->phy.duplex == DUPLEX_FULL) {
648 if (dev->phy.pause)
649 mr1 |= EMAC_MR1_EIFC | EMAC_MR1_APP;
650 else if (dev->phy.asym_pause)
651 mr1 |= EMAC_MR1_APP;
652 }
653
654 /* Add base settings & fifo sizes & program MR1 */
655 mr1 |= emac_calc_base_mr1(dev, tx_size, rx_size);
656 out_be32(&p->mr1, mr1);
657
658 /* Set individual MAC address */
659 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
660 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
661 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
662 ndev->dev_addr[5]);
663
664 /* VLAN Tag Protocol ID */
665 out_be32(&p->vtpid, 0x8100);
666
667 /* Receive mode register */
668 r = emac_iff2rmr(ndev);
669 if (r & EMAC_RMR_MAE)
670 emac_hash_mc(dev);
671 out_be32(&p->rmr, r);
672
673 /* FIFOs thresholds */
674 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
675 r = EMAC4_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
676 tx_size / 2 / dev->fifo_entry_size);
677 else
678 r = EMAC_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
679 tx_size / 2 / dev->fifo_entry_size);
680 out_be32(&p->tmr1, r);
681 out_be32(&p->trtr, emac_calc_trtr(dev, tx_size / 2));
682
683 /* PAUSE frame is sent when RX FIFO reaches its high-water mark,
684 there should be still enough space in FIFO to allow the our link
685 partner time to process this frame and also time to send PAUSE
686 frame itself.
687
688 Here is the worst case scenario for the RX FIFO "headroom"
689 (from "The Switch Book") (100Mbps, without preamble, inter-frame gap):
690
691 1) One maximum-length frame on TX 1522 bytes
692 2) One PAUSE frame time 64 bytes
693 3) PAUSE frame decode time allowance 64 bytes
694 4) One maximum-length frame on RX 1522 bytes
695 5) Round-trip propagation delay of the link (100Mb) 15 bytes
696 ----------
697 3187 bytes
698
699 I chose to set high-water mark to RX_FIFO_SIZE / 4 (1024 bytes)
700 low-water mark to RX_FIFO_SIZE / 8 (512 bytes)
701 */
702 r = emac_calc_rwmr(dev, rx_size / 8 / dev->fifo_entry_size,
703 rx_size / 4 / dev->fifo_entry_size);
704 out_be32(&p->rwmr, r);
705
706 /* Set PAUSE timer to the maximum */
707 out_be32(&p->ptr, 0xffff);
708
709 /* IRQ sources */
710 r = EMAC_ISR_OVR | EMAC_ISR_BP | EMAC_ISR_SE |
711 EMAC_ISR_ALE | EMAC_ISR_BFCS | EMAC_ISR_PTLE | EMAC_ISR_ORE |
712 EMAC_ISR_IRE | EMAC_ISR_TE;
713 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
714 r |= EMAC4_ISR_TXPE | EMAC4_ISR_RXPE /* | EMAC4_ISR_TXUE |
715 EMAC4_ISR_RXOE | */;
716 out_be32(&p->iser, r);
717
718 /* We need to take GPCS PHY out of isolate mode after EMAC reset */
719 if (emac_phy_gpcs(dev->phy.mode)) {
720 if (dev->phy.gpcs_address != 0xffffffff)
721 emac_mii_reset_gpcs(&dev->phy);
722 else
723 emac_mii_reset_phy(&dev->phy);
724 }
725
726 return 0;
727}
728
729static void emac_reinitialize(struct emac_instance *dev)
730{
731 DBG(dev, "reinitialize" NL);
732
733 emac_netif_stop(dev);
734 if (!emac_configure(dev)) {
735 emac_tx_enable(dev);
736 emac_rx_enable(dev);
737 }
738 emac_netif_start(dev);
739}
740
741static void emac_full_tx_reset(struct emac_instance *dev)
742{
743 DBG(dev, "full_tx_reset" NL);
744
745 emac_tx_disable(dev);
746 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
747 emac_clean_tx_ring(dev);
748 dev->tx_cnt = dev->tx_slot = dev->ack_slot = 0;
749
750 emac_configure(dev);
751
752 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
753 emac_tx_enable(dev);
754 emac_rx_enable(dev);
755}
756
757static void emac_reset_work(struct work_struct *work)
758{
759 struct emac_instance *dev = container_of(work, struct emac_instance, reset_work);
760
761 DBG(dev, "reset_work" NL);
762
763 mutex_lock(&dev->link_lock);
764 if (dev->opened) {
765 emac_netif_stop(dev);
766 emac_full_tx_reset(dev);
767 emac_netif_start(dev);
768 }
769 mutex_unlock(&dev->link_lock);
770}
771
772static void emac_tx_timeout(struct net_device *ndev, unsigned int txqueue)
773{
774 struct emac_instance *dev = netdev_priv(ndev);
775
776 DBG(dev, "tx_timeout" NL);
777
778 schedule_work(&dev->reset_work);
779}
780
781
782static inline int emac_phy_done(struct emac_instance *dev, u32 stacr)
783{
784 int done = !!(stacr & EMAC_STACR_OC);
785
786 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
787 done = !done;
788
789 return done;
790};
791
792static int __emac_mdio_read(struct emac_instance *dev, u8 id, u8 reg)
793{
794 struct emac_regs __iomem *p = dev->emacp;
795 u32 r = 0;
796 int n, err = -ETIMEDOUT;
797
798 mutex_lock(&dev->mdio_lock);
799
800 DBG2(dev, "mdio_read(%02x,%02x)" NL, id, reg);
801
802 /* Enable proper MDIO port */
803 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
804 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
805 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
806 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
807
808 /* Wait for management interface to become idle */
809 n = 20;
810 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
811 udelay(1);
812 if (!--n) {
813 DBG2(dev, " -> timeout wait idle\n");
814 goto bail;
815 }
816 }
817
818 /* Issue read command */
819 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
820 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
821 else
822 r = EMAC_STACR_BASE(dev->opb_bus_freq);
823 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
824 r |= EMAC_STACR_OC;
825 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
826 r |= EMACX_STACR_STAC_READ;
827 else
828 r |= EMAC_STACR_STAC_READ;
829 r |= (reg & EMAC_STACR_PRA_MASK)
830 | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT);
831 out_be32(&p->stacr, r);
832
833 /* Wait for read to complete */
834 n = 200;
835 while (!emac_phy_done(dev, (r = in_be32(&p->stacr)))) {
836 udelay(1);
837 if (!--n) {
838 DBG2(dev, " -> timeout wait complete\n");
839 goto bail;
840 }
841 }
842
843 if (unlikely(r & EMAC_STACR_PHYE)) {
844 DBG(dev, "mdio_read(%02x, %02x) failed" NL, id, reg);
845 err = -EREMOTEIO;
846 goto bail;
847 }
848
849 r = ((r >> EMAC_STACR_PHYD_SHIFT) & EMAC_STACR_PHYD_MASK);
850
851 DBG2(dev, "mdio_read -> %04x" NL, r);
852 err = 0;
853 bail:
854 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
855 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
856 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
857 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
858 mutex_unlock(&dev->mdio_lock);
859
860 return err == 0 ? r : err;
861}
862
863static void __emac_mdio_write(struct emac_instance *dev, u8 id, u8 reg,
864 u16 val)
865{
866 struct emac_regs __iomem *p = dev->emacp;
867 u32 r = 0;
868 int n;
869
870 mutex_lock(&dev->mdio_lock);
871
872 DBG2(dev, "mdio_write(%02x,%02x,%04x)" NL, id, reg, val);
873
874 /* Enable proper MDIO port */
875 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
876 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
877 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
878 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
879
880 /* Wait for management interface to be idle */
881 n = 20;
882 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
883 udelay(1);
884 if (!--n) {
885 DBG2(dev, " -> timeout wait idle\n");
886 goto bail;
887 }
888 }
889
890 /* Issue write command */
891 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
892 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
893 else
894 r = EMAC_STACR_BASE(dev->opb_bus_freq);
895 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
896 r |= EMAC_STACR_OC;
897 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
898 r |= EMACX_STACR_STAC_WRITE;
899 else
900 r |= EMAC_STACR_STAC_WRITE;
901 r |= (reg & EMAC_STACR_PRA_MASK) |
902 ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) |
903 (val << EMAC_STACR_PHYD_SHIFT);
904 out_be32(&p->stacr, r);
905
906 /* Wait for write to complete */
907 n = 200;
908 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
909 udelay(1);
910 if (!--n) {
911 DBG2(dev, " -> timeout wait complete\n");
912 goto bail;
913 }
914 }
915 bail:
916 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
917 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
918 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
919 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
920 mutex_unlock(&dev->mdio_lock);
921}
922
923static int emac_mdio_read(struct net_device *ndev, int id, int reg)
924{
925 struct emac_instance *dev = netdev_priv(ndev);
926 int res;
927
928 res = __emac_mdio_read((dev->mdio_instance &&
929 dev->phy.gpcs_address != id) ?
930 dev->mdio_instance : dev,
931 (u8) id, (u8) reg);
932 return res;
933}
934
935static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val)
936{
937 struct emac_instance *dev = netdev_priv(ndev);
938
939 __emac_mdio_write((dev->mdio_instance &&
940 dev->phy.gpcs_address != id) ?
941 dev->mdio_instance : dev,
942 (u8) id, (u8) reg, (u16) val);
943}
944
945/* Tx lock BH */
946static void __emac_set_multicast_list(struct emac_instance *dev)
947{
948 struct emac_regs __iomem *p = dev->emacp;
949 u32 rmr = emac_iff2rmr(dev->ndev);
950
951 DBG(dev, "__multicast %08x" NL, rmr);
952
953 /* I decided to relax register access rules here to avoid
954 * full EMAC reset.
955 *
956 * There is a real problem with EMAC4 core if we use MWSW_001 bit
957 * in MR1 register and do a full EMAC reset.
958 * One TX BD status update is delayed and, after EMAC reset, it
959 * never happens, resulting in TX hung (it'll be recovered by TX
960 * timeout handler eventually, but this is just gross).
961 * So we either have to do full TX reset or try to cheat here :)
962 *
963 * The only required change is to RX mode register, so I *think* all
964 * we need is just to stop RX channel. This seems to work on all
965 * tested SoCs. --ebs
966 *
967 */
968 dev->mcast_pending = 0;
969 emac_rx_disable(dev);
970 if (rmr & EMAC_RMR_MAE)
971 emac_hash_mc(dev);
972 out_be32(&p->rmr, rmr);
973 emac_rx_enable(dev);
974}
975
976/* Tx lock BH */
977static void emac_set_multicast_list(struct net_device *ndev)
978{
979 struct emac_instance *dev = netdev_priv(ndev);
980
981 DBG(dev, "multicast" NL);
982
983 BUG_ON(!netif_running(dev->ndev));
984
985 if (dev->no_mcast) {
986 dev->mcast_pending = 1;
987 return;
988 }
989
990 mutex_lock(&dev->link_lock);
991 __emac_set_multicast_list(dev);
992 mutex_unlock(&dev->link_lock);
993}
994
995static int emac_set_mac_address(struct net_device *ndev, void *sa)
996{
997 struct emac_instance *dev = netdev_priv(ndev);
998 struct sockaddr *addr = sa;
999 struct emac_regs __iomem *p = dev->emacp;
1000
1001 if (!is_valid_ether_addr(addr->sa_data))
1002 return -EADDRNOTAVAIL;
1003
1004 mutex_lock(&dev->link_lock);
1005
1006 eth_hw_addr_set(ndev, addr->sa_data);
1007
1008 emac_rx_disable(dev);
1009 emac_tx_disable(dev);
1010 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
1011 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
1012 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
1013 ndev->dev_addr[5]);
1014 emac_tx_enable(dev);
1015 emac_rx_enable(dev);
1016
1017 mutex_unlock(&dev->link_lock);
1018
1019 return 0;
1020}
1021
1022static int emac_resize_rx_ring(struct emac_instance *dev, int new_mtu)
1023{
1024 int rx_sync_size = emac_rx_sync_size(new_mtu);
1025 int rx_skb_size = emac_rx_skb_size(new_mtu);
1026 int i, ret = 0;
1027 int mr1_jumbo_bit_change = 0;
1028
1029 mutex_lock(&dev->link_lock);
1030 emac_netif_stop(dev);
1031 emac_rx_disable(dev);
1032 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
1033
1034 if (dev->rx_sg_skb) {
1035 ++dev->estats.rx_dropped_resize;
1036 dev_kfree_skb(dev->rx_sg_skb);
1037 dev->rx_sg_skb = NULL;
1038 }
1039
1040 /* Make a first pass over RX ring and mark BDs ready, dropping
1041 * non-processed packets on the way. We need this as a separate pass
1042 * to simplify error recovery in the case of allocation failure later.
1043 */
1044 for (i = 0; i < NUM_RX_BUFF; ++i) {
1045 if (dev->rx_desc[i].ctrl & MAL_RX_CTRL_FIRST)
1046 ++dev->estats.rx_dropped_resize;
1047
1048 dev->rx_desc[i].data_len = 0;
1049 dev->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY |
1050 (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1051 }
1052
1053 /* Reallocate RX ring only if bigger skb buffers are required */
1054 if (rx_skb_size <= dev->rx_skb_size)
1055 goto skip;
1056
1057 /* Second pass, allocate new skbs */
1058 for (i = 0; i < NUM_RX_BUFF; ++i) {
1059 struct sk_buff *skb;
1060
1061 skb = netdev_alloc_skb_ip_align(dev->ndev, rx_skb_size);
1062 if (!skb) {
1063 ret = -ENOMEM;
1064 goto oom;
1065 }
1066
1067 BUG_ON(!dev->rx_skb[i]);
1068 dev_kfree_skb(dev->rx_skb[i]);
1069
1070 dev->rx_desc[i].data_ptr =
1071 dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN,
1072 rx_sync_size, DMA_FROM_DEVICE)
1073 + NET_IP_ALIGN;
1074 dev->rx_skb[i] = skb;
1075 }
1076 skip:
1077 /* Check if we need to change "Jumbo" bit in MR1 */
1078 if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) {
1079 mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) ||
1080 (dev->ndev->mtu > ETH_DATA_LEN);
1081 } else {
1082 mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) ^
1083 (dev->ndev->mtu > ETH_DATA_LEN);
1084 }
1085
1086 if (mr1_jumbo_bit_change) {
1087 /* This is to prevent starting RX channel in emac_rx_enable() */
1088 set_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1089
1090 WRITE_ONCE(dev->ndev->mtu, new_mtu);
1091 emac_full_tx_reset(dev);
1092 }
1093
1094 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(new_mtu));
1095 oom:
1096 /* Restart RX */
1097 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1098 dev->rx_slot = 0;
1099 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1100 emac_rx_enable(dev);
1101 emac_netif_start(dev);
1102 mutex_unlock(&dev->link_lock);
1103
1104 return ret;
1105}
1106
1107/* Process ctx, rtnl_lock semaphore */
1108static int emac_change_mtu(struct net_device *ndev, int new_mtu)
1109{
1110 struct emac_instance *dev = netdev_priv(ndev);
1111 int ret = 0;
1112
1113 DBG(dev, "change_mtu(%d)" NL, new_mtu);
1114
1115 if (netif_running(ndev)) {
1116 /* Check if we really need to reinitialize RX ring */
1117 if (emac_rx_skb_size(ndev->mtu) != emac_rx_skb_size(new_mtu))
1118 ret = emac_resize_rx_ring(dev, new_mtu);
1119 }
1120
1121 if (!ret) {
1122 WRITE_ONCE(ndev->mtu, new_mtu);
1123 dev->rx_skb_size = emac_rx_skb_size(new_mtu);
1124 dev->rx_sync_size = emac_rx_sync_size(new_mtu);
1125 }
1126
1127 return ret;
1128}
1129
1130static void emac_clean_tx_ring(struct emac_instance *dev)
1131{
1132 int i;
1133
1134 for (i = 0; i < NUM_TX_BUFF; ++i) {
1135 if (dev->tx_skb[i]) {
1136 dev_kfree_skb(dev->tx_skb[i]);
1137 dev->tx_skb[i] = NULL;
1138 if (dev->tx_desc[i].ctrl & MAL_TX_CTRL_READY)
1139 ++dev->estats.tx_dropped;
1140 }
1141 dev->tx_desc[i].ctrl = 0;
1142 dev->tx_desc[i].data_ptr = 0;
1143 }
1144}
1145
1146static void emac_clean_rx_ring(struct emac_instance *dev)
1147{
1148 int i;
1149
1150 for (i = 0; i < NUM_RX_BUFF; ++i)
1151 if (dev->rx_skb[i]) {
1152 dev->rx_desc[i].ctrl = 0;
1153 dev_kfree_skb(dev->rx_skb[i]);
1154 dev->rx_skb[i] = NULL;
1155 dev->rx_desc[i].data_ptr = 0;
1156 }
1157
1158 if (dev->rx_sg_skb) {
1159 dev_kfree_skb(dev->rx_sg_skb);
1160 dev->rx_sg_skb = NULL;
1161 }
1162}
1163
1164static int
1165__emac_prepare_rx_skb(struct sk_buff *skb, struct emac_instance *dev, int slot)
1166{
1167 if (unlikely(!skb))
1168 return -ENOMEM;
1169
1170 dev->rx_skb[slot] = skb;
1171 dev->rx_desc[slot].data_len = 0;
1172
1173 dev->rx_desc[slot].data_ptr =
1174 dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN,
1175 dev->rx_sync_size, DMA_FROM_DEVICE) + NET_IP_ALIGN;
1176 wmb();
1177 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1178 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1179
1180 return 0;
1181}
1182
1183static int
1184emac_alloc_rx_skb(struct emac_instance *dev, int slot)
1185{
1186 struct sk_buff *skb;
1187
1188 skb = __netdev_alloc_skb_ip_align(dev->ndev, dev->rx_skb_size,
1189 GFP_KERNEL);
1190
1191 return __emac_prepare_rx_skb(skb, dev, slot);
1192}
1193
1194static int
1195emac_alloc_rx_skb_napi(struct emac_instance *dev, int slot)
1196{
1197 struct sk_buff *skb;
1198
1199 skb = napi_alloc_skb(&dev->mal->napi, dev->rx_skb_size);
1200
1201 return __emac_prepare_rx_skb(skb, dev, slot);
1202}
1203
1204static void emac_print_link_status(struct emac_instance *dev)
1205{
1206 if (netif_carrier_ok(dev->ndev))
1207 printk(KERN_INFO "%s: link is up, %d %s%s\n",
1208 dev->ndev->name, dev->phy.speed,
1209 dev->phy.duplex == DUPLEX_FULL ? "FDX" : "HDX",
1210 dev->phy.pause ? ", pause enabled" :
1211 dev->phy.asym_pause ? ", asymmetric pause enabled" : "");
1212 else
1213 printk(KERN_INFO "%s: link is down\n", dev->ndev->name);
1214}
1215
1216/* Process ctx, rtnl_lock semaphore */
1217static int emac_open(struct net_device *ndev)
1218{
1219 struct emac_instance *dev = netdev_priv(ndev);
1220 int i;
1221
1222 DBG(dev, "open" NL);
1223
1224 /* Allocate RX ring */
1225 for (i = 0; i < NUM_RX_BUFF; ++i)
1226 if (emac_alloc_rx_skb(dev, i)) {
1227 printk(KERN_ERR "%s: failed to allocate RX ring\n",
1228 ndev->name);
1229 goto oom;
1230 }
1231
1232 dev->tx_cnt = dev->tx_slot = dev->ack_slot = dev->rx_slot = 0;
1233 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1234 dev->rx_sg_skb = NULL;
1235
1236 mutex_lock(&dev->link_lock);
1237 dev->opened = 1;
1238
1239 /* Start PHY polling now.
1240 */
1241 if (dev->phy.address >= 0) {
1242 int link_poll_interval;
1243 if (dev->phy.def->ops->poll_link(&dev->phy)) {
1244 dev->phy.def->ops->read_link(&dev->phy);
1245 emac_rx_clk_default(dev);
1246 netif_carrier_on(dev->ndev);
1247 link_poll_interval = PHY_POLL_LINK_ON;
1248 } else {
1249 emac_rx_clk_tx(dev);
1250 netif_carrier_off(dev->ndev);
1251 link_poll_interval = PHY_POLL_LINK_OFF;
1252 }
1253 dev->link_polling = 1;
1254 wmb();
1255 schedule_delayed_work(&dev->link_work, link_poll_interval);
1256 emac_print_link_status(dev);
1257 } else
1258 netif_carrier_on(dev->ndev);
1259
1260 /* Required for Pause packet support in EMAC */
1261 dev_mc_add_global(ndev, default_mcast_addr);
1262
1263 emac_configure(dev);
1264 mal_poll_add(dev->mal, &dev->commac);
1265 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
1266 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(ndev->mtu));
1267 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1268 emac_tx_enable(dev);
1269 emac_rx_enable(dev);
1270 emac_netif_start(dev);
1271
1272 mutex_unlock(&dev->link_lock);
1273
1274 return 0;
1275 oom:
1276 emac_clean_rx_ring(dev);
1277 return -ENOMEM;
1278}
1279
1280/* BHs disabled */
1281#if 0
1282static int emac_link_differs(struct emac_instance *dev)
1283{
1284 u32 r = in_be32(&dev->emacp->mr1);
1285
1286 int duplex = r & EMAC_MR1_FDE ? DUPLEX_FULL : DUPLEX_HALF;
1287 int speed, pause, asym_pause;
1288
1289 if (r & EMAC_MR1_MF_1000)
1290 speed = SPEED_1000;
1291 else if (r & EMAC_MR1_MF_100)
1292 speed = SPEED_100;
1293 else
1294 speed = SPEED_10;
1295
1296 switch (r & (EMAC_MR1_EIFC | EMAC_MR1_APP)) {
1297 case (EMAC_MR1_EIFC | EMAC_MR1_APP):
1298 pause = 1;
1299 asym_pause = 0;
1300 break;
1301 case EMAC_MR1_APP:
1302 pause = 0;
1303 asym_pause = 1;
1304 break;
1305 default:
1306 pause = asym_pause = 0;
1307 }
1308 return speed != dev->phy.speed || duplex != dev->phy.duplex ||
1309 pause != dev->phy.pause || asym_pause != dev->phy.asym_pause;
1310}
1311#endif
1312
1313static void emac_link_timer(struct work_struct *work)
1314{
1315 struct emac_instance *dev =
1316 container_of(to_delayed_work(work),
1317 struct emac_instance, link_work);
1318 int link_poll_interval;
1319
1320 mutex_lock(&dev->link_lock);
1321 DBG2(dev, "link timer" NL);
1322
1323 if (!dev->opened)
1324 goto bail;
1325
1326 if (dev->phy.def->ops->poll_link(&dev->phy)) {
1327 if (!netif_carrier_ok(dev->ndev)) {
1328 emac_rx_clk_default(dev);
1329 /* Get new link parameters */
1330 dev->phy.def->ops->read_link(&dev->phy);
1331
1332 netif_carrier_on(dev->ndev);
1333 emac_netif_stop(dev);
1334 emac_full_tx_reset(dev);
1335 emac_netif_start(dev);
1336 emac_print_link_status(dev);
1337 }
1338 link_poll_interval = PHY_POLL_LINK_ON;
1339 } else {
1340 if (netif_carrier_ok(dev->ndev)) {
1341 emac_rx_clk_tx(dev);
1342 netif_carrier_off(dev->ndev);
1343 netif_tx_disable(dev->ndev);
1344 emac_reinitialize(dev);
1345 emac_print_link_status(dev);
1346 }
1347 link_poll_interval = PHY_POLL_LINK_OFF;
1348 }
1349 schedule_delayed_work(&dev->link_work, link_poll_interval);
1350 bail:
1351 mutex_unlock(&dev->link_lock);
1352}
1353
1354static void emac_force_link_update(struct emac_instance *dev)
1355{
1356 netif_carrier_off(dev->ndev);
1357 smp_rmb();
1358 if (dev->link_polling) {
1359 cancel_delayed_work_sync(&dev->link_work);
1360 if (dev->link_polling)
1361 schedule_delayed_work(&dev->link_work, PHY_POLL_LINK_OFF);
1362 }
1363}
1364
1365/* Process ctx, rtnl_lock semaphore */
1366static int emac_close(struct net_device *ndev)
1367{
1368 struct emac_instance *dev = netdev_priv(ndev);
1369
1370 DBG(dev, "close" NL);
1371
1372 if (dev->phy.address >= 0) {
1373 dev->link_polling = 0;
1374 cancel_delayed_work_sync(&dev->link_work);
1375 }
1376 mutex_lock(&dev->link_lock);
1377 emac_netif_stop(dev);
1378 dev->opened = 0;
1379 mutex_unlock(&dev->link_lock);
1380
1381 emac_rx_disable(dev);
1382 emac_tx_disable(dev);
1383 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
1384 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
1385 mal_poll_del(dev->mal, &dev->commac);
1386
1387 emac_clean_tx_ring(dev);
1388 emac_clean_rx_ring(dev);
1389
1390 netif_carrier_off(ndev);
1391
1392 return 0;
1393}
1394
1395static inline u16 emac_tx_csum(struct emac_instance *dev,
1396 struct sk_buff *skb)
1397{
1398 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
1399 (skb->ip_summed == CHECKSUM_PARTIAL)) {
1400 ++dev->stats.tx_packets_csum;
1401 return EMAC_TX_CTRL_TAH_CSUM;
1402 }
1403 return 0;
1404}
1405
1406static inline netdev_tx_t emac_xmit_finish(struct emac_instance *dev, int len)
1407{
1408 struct emac_regs __iomem *p = dev->emacp;
1409 struct net_device *ndev = dev->ndev;
1410
1411 /* Send the packet out. If the if makes a significant perf
1412 * difference, then we can store the TMR0 value in "dev"
1413 * instead
1414 */
1415 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
1416 out_be32(&p->tmr0, EMAC4_TMR0_XMIT);
1417 else
1418 out_be32(&p->tmr0, EMAC_TMR0_XMIT);
1419
1420 if (unlikely(++dev->tx_cnt == NUM_TX_BUFF)) {
1421 netif_stop_queue(ndev);
1422 DBG2(dev, "stopped TX queue" NL);
1423 }
1424
1425 netif_trans_update(ndev);
1426 ++dev->stats.tx_packets;
1427 dev->stats.tx_bytes += len;
1428
1429 return NETDEV_TX_OK;
1430}
1431
1432/* Tx lock BH */
1433static netdev_tx_t emac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1434{
1435 struct emac_instance *dev = netdev_priv(ndev);
1436 unsigned int len = skb->len;
1437 int slot;
1438
1439 u16 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1440 MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb);
1441
1442 slot = dev->tx_slot++;
1443 if (dev->tx_slot == NUM_TX_BUFF) {
1444 dev->tx_slot = 0;
1445 ctrl |= MAL_TX_CTRL_WRAP;
1446 }
1447
1448 DBG2(dev, "xmit(%u) %d" NL, len, slot);
1449
1450 dev->tx_skb[slot] = skb;
1451 dev->tx_desc[slot].data_ptr = dma_map_single(&dev->ofdev->dev,
1452 skb->data, len,
1453 DMA_TO_DEVICE);
1454 dev->tx_desc[slot].data_len = (u16) len;
1455 wmb();
1456 dev->tx_desc[slot].ctrl = ctrl;
1457
1458 return emac_xmit_finish(dev, len);
1459}
1460
1461static inline int emac_xmit_split(struct emac_instance *dev, int slot,
1462 u32 pd, int len, int last, u16 base_ctrl)
1463{
1464 while (1) {
1465 u16 ctrl = base_ctrl;
1466 int chunk = min(len, MAL_MAX_TX_SIZE);
1467 len -= chunk;
1468
1469 slot = (slot + 1) % NUM_TX_BUFF;
1470
1471 if (last && !len)
1472 ctrl |= MAL_TX_CTRL_LAST;
1473 if (slot == NUM_TX_BUFF - 1)
1474 ctrl |= MAL_TX_CTRL_WRAP;
1475
1476 dev->tx_skb[slot] = NULL;
1477 dev->tx_desc[slot].data_ptr = pd;
1478 dev->tx_desc[slot].data_len = (u16) chunk;
1479 dev->tx_desc[slot].ctrl = ctrl;
1480 ++dev->tx_cnt;
1481
1482 if (!len)
1483 break;
1484
1485 pd += chunk;
1486 }
1487 return slot;
1488}
1489
1490/* Tx lock BH disabled (SG version for TAH equipped EMACs) */
1491static netdev_tx_t
1492emac_start_xmit_sg(struct sk_buff *skb, struct net_device *ndev)
1493{
1494 struct emac_instance *dev = netdev_priv(ndev);
1495 int nr_frags = skb_shinfo(skb)->nr_frags;
1496 int len = skb->len, chunk;
1497 int slot, i;
1498 u16 ctrl;
1499 u32 pd;
1500
1501 /* This is common "fast" path */
1502 if (likely(!nr_frags && len <= MAL_MAX_TX_SIZE))
1503 return emac_start_xmit(skb, ndev);
1504
1505 len -= skb->data_len;
1506
1507 /* Note, this is only an *estimation*, we can still run out of empty
1508 * slots because of the additional fragmentation into
1509 * MAL_MAX_TX_SIZE-sized chunks
1510 */
1511 if (unlikely(dev->tx_cnt + nr_frags + mal_tx_chunks(len) > NUM_TX_BUFF))
1512 goto stop_queue;
1513
1514 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1515 emac_tx_csum(dev, skb);
1516 slot = dev->tx_slot;
1517
1518 /* skb data */
1519 dev->tx_skb[slot] = NULL;
1520 chunk = min(len, MAL_MAX_TX_SIZE);
1521 dev->tx_desc[slot].data_ptr = pd =
1522 dma_map_single(&dev->ofdev->dev, skb->data, len, DMA_TO_DEVICE);
1523 dev->tx_desc[slot].data_len = (u16) chunk;
1524 len -= chunk;
1525 if (unlikely(len))
1526 slot = emac_xmit_split(dev, slot, pd + chunk, len, !nr_frags,
1527 ctrl);
1528 /* skb fragments */
1529 for (i = 0; i < nr_frags; ++i) {
1530 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1531 len = skb_frag_size(frag);
1532
1533 if (unlikely(dev->tx_cnt + mal_tx_chunks(len) >= NUM_TX_BUFF))
1534 goto undo_frame;
1535
1536 pd = skb_frag_dma_map(&dev->ofdev->dev, frag, 0, len,
1537 DMA_TO_DEVICE);
1538
1539 slot = emac_xmit_split(dev, slot, pd, len, i == nr_frags - 1,
1540 ctrl);
1541 }
1542
1543 DBG2(dev, "xmit_sg(%u) %d - %d" NL, skb->len, dev->tx_slot, slot);
1544
1545 /* Attach skb to the last slot so we don't release it too early */
1546 dev->tx_skb[slot] = skb;
1547
1548 /* Send the packet out */
1549 if (dev->tx_slot == NUM_TX_BUFF - 1)
1550 ctrl |= MAL_TX_CTRL_WRAP;
1551 wmb();
1552 dev->tx_desc[dev->tx_slot].ctrl = ctrl;
1553 dev->tx_slot = (slot + 1) % NUM_TX_BUFF;
1554
1555 return emac_xmit_finish(dev, skb->len);
1556
1557 undo_frame:
1558 /* Well, too bad. Our previous estimation was overly optimistic.
1559 * Undo everything.
1560 */
1561 while (slot != dev->tx_slot) {
1562 dev->tx_desc[slot].ctrl = 0;
1563 --dev->tx_cnt;
1564 if (--slot < 0)
1565 slot = NUM_TX_BUFF - 1;
1566 }
1567 ++dev->estats.tx_undo;
1568
1569 stop_queue:
1570 netif_stop_queue(ndev);
1571 DBG2(dev, "stopped TX queue" NL);
1572 return NETDEV_TX_BUSY;
1573}
1574
1575/* Tx lock BHs */
1576static void emac_parse_tx_error(struct emac_instance *dev, u16 ctrl)
1577{
1578 struct emac_error_stats *st = &dev->estats;
1579
1580 DBG(dev, "BD TX error %04x" NL, ctrl);
1581
1582 ++st->tx_bd_errors;
1583 if (ctrl & EMAC_TX_ST_BFCS)
1584 ++st->tx_bd_bad_fcs;
1585 if (ctrl & EMAC_TX_ST_LCS)
1586 ++st->tx_bd_carrier_loss;
1587 if (ctrl & EMAC_TX_ST_ED)
1588 ++st->tx_bd_excessive_deferral;
1589 if (ctrl & EMAC_TX_ST_EC)
1590 ++st->tx_bd_excessive_collisions;
1591 if (ctrl & EMAC_TX_ST_LC)
1592 ++st->tx_bd_late_collision;
1593 if (ctrl & EMAC_TX_ST_MC)
1594 ++st->tx_bd_multple_collisions;
1595 if (ctrl & EMAC_TX_ST_SC)
1596 ++st->tx_bd_single_collision;
1597 if (ctrl & EMAC_TX_ST_UR)
1598 ++st->tx_bd_underrun;
1599 if (ctrl & EMAC_TX_ST_SQE)
1600 ++st->tx_bd_sqe;
1601}
1602
1603static void emac_poll_tx(void *param)
1604{
1605 struct emac_instance *dev = param;
1606 u32 bad_mask;
1607
1608 DBG2(dev, "poll_tx, %d %d" NL, dev->tx_cnt, dev->ack_slot);
1609
1610 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
1611 bad_mask = EMAC_IS_BAD_TX_TAH;
1612 else
1613 bad_mask = EMAC_IS_BAD_TX;
1614
1615 netif_tx_lock_bh(dev->ndev);
1616 if (dev->tx_cnt) {
1617 u16 ctrl;
1618 int slot = dev->ack_slot, n = 0;
1619 again:
1620 ctrl = dev->tx_desc[slot].ctrl;
1621 if (!(ctrl & MAL_TX_CTRL_READY)) {
1622 struct sk_buff *skb = dev->tx_skb[slot];
1623 ++n;
1624
1625 if (skb) {
1626 dev_kfree_skb(skb);
1627 dev->tx_skb[slot] = NULL;
1628 }
1629 slot = (slot + 1) % NUM_TX_BUFF;
1630
1631 if (unlikely(ctrl & bad_mask))
1632 emac_parse_tx_error(dev, ctrl);
1633
1634 if (--dev->tx_cnt)
1635 goto again;
1636 }
1637 if (n) {
1638 dev->ack_slot = slot;
1639 if (netif_queue_stopped(dev->ndev) &&
1640 dev->tx_cnt < EMAC_TX_WAKEUP_THRESH)
1641 netif_wake_queue(dev->ndev);
1642
1643 DBG2(dev, "tx %d pkts" NL, n);
1644 }
1645 }
1646 netif_tx_unlock_bh(dev->ndev);
1647}
1648
1649static inline void emac_recycle_rx_skb(struct emac_instance *dev, int slot,
1650 int len)
1651{
1652 struct sk_buff *skb = dev->rx_skb[slot];
1653
1654 DBG2(dev, "recycle %d %d" NL, slot, len);
1655
1656 if (len)
1657 dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN,
1658 SKB_DATA_ALIGN(len + NET_IP_ALIGN),
1659 DMA_FROM_DEVICE);
1660
1661 dev->rx_desc[slot].data_len = 0;
1662 wmb();
1663 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1664 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1665}
1666
1667static void emac_parse_rx_error(struct emac_instance *dev, u16 ctrl)
1668{
1669 struct emac_error_stats *st = &dev->estats;
1670
1671 DBG(dev, "BD RX error %04x" NL, ctrl);
1672
1673 ++st->rx_bd_errors;
1674 if (ctrl & EMAC_RX_ST_OE)
1675 ++st->rx_bd_overrun;
1676 if (ctrl & EMAC_RX_ST_BP)
1677 ++st->rx_bd_bad_packet;
1678 if (ctrl & EMAC_RX_ST_RP)
1679 ++st->rx_bd_runt_packet;
1680 if (ctrl & EMAC_RX_ST_SE)
1681 ++st->rx_bd_short_event;
1682 if (ctrl & EMAC_RX_ST_AE)
1683 ++st->rx_bd_alignment_error;
1684 if (ctrl & EMAC_RX_ST_BFCS)
1685 ++st->rx_bd_bad_fcs;
1686 if (ctrl & EMAC_RX_ST_PTL)
1687 ++st->rx_bd_packet_too_long;
1688 if (ctrl & EMAC_RX_ST_ORE)
1689 ++st->rx_bd_out_of_range;
1690 if (ctrl & EMAC_RX_ST_IRE)
1691 ++st->rx_bd_in_range;
1692}
1693
1694static inline void emac_rx_csum(struct emac_instance *dev,
1695 struct sk_buff *skb, u16 ctrl)
1696{
1697#ifdef CONFIG_IBM_EMAC_TAH
1698 if (!ctrl && dev->tah_dev) {
1699 skb->ip_summed = CHECKSUM_UNNECESSARY;
1700 ++dev->stats.rx_packets_csum;
1701 }
1702#endif
1703}
1704
1705static inline int emac_rx_sg_append(struct emac_instance *dev, int slot)
1706{
1707 if (likely(dev->rx_sg_skb != NULL)) {
1708 int len = dev->rx_desc[slot].data_len;
1709 int tot_len = dev->rx_sg_skb->len + len;
1710
1711 if (unlikely(tot_len + NET_IP_ALIGN > dev->rx_skb_size)) {
1712 ++dev->estats.rx_dropped_mtu;
1713 dev_kfree_skb(dev->rx_sg_skb);
1714 dev->rx_sg_skb = NULL;
1715 } else {
1716 memcpy(skb_tail_pointer(dev->rx_sg_skb),
1717 dev->rx_skb[slot]->data, len);
1718 skb_put(dev->rx_sg_skb, len);
1719 emac_recycle_rx_skb(dev, slot, len);
1720 return 0;
1721 }
1722 }
1723 emac_recycle_rx_skb(dev, slot, 0);
1724 return -1;
1725}
1726
1727/* NAPI poll context */
1728static int emac_poll_rx(void *param, int budget)
1729{
1730 LIST_HEAD(rx_list);
1731 struct emac_instance *dev = param;
1732 int slot = dev->rx_slot, received = 0;
1733
1734 DBG2(dev, "poll_rx(%d)" NL, budget);
1735
1736 again:
1737 while (budget > 0) {
1738 int len;
1739 struct sk_buff *skb;
1740 u16 ctrl = dev->rx_desc[slot].ctrl;
1741
1742 if (ctrl & MAL_RX_CTRL_EMPTY)
1743 break;
1744
1745 skb = dev->rx_skb[slot];
1746 mb();
1747 len = dev->rx_desc[slot].data_len;
1748
1749 if (unlikely(!MAL_IS_SINGLE_RX(ctrl)))
1750 goto sg;
1751
1752 ctrl &= EMAC_BAD_RX_MASK;
1753 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1754 emac_parse_rx_error(dev, ctrl);
1755 ++dev->estats.rx_dropped_error;
1756 emac_recycle_rx_skb(dev, slot, 0);
1757 len = 0;
1758 goto next;
1759 }
1760
1761 if (len < ETH_HLEN) {
1762 ++dev->estats.rx_dropped_stack;
1763 emac_recycle_rx_skb(dev, slot, len);
1764 goto next;
1765 }
1766
1767 if (len && len < EMAC_RX_COPY_THRESH) {
1768 struct sk_buff *copy_skb;
1769
1770 copy_skb = napi_alloc_skb(&dev->mal->napi, len);
1771 if (unlikely(!copy_skb))
1772 goto oom;
1773
1774 memcpy(copy_skb->data - NET_IP_ALIGN,
1775 skb->data - NET_IP_ALIGN,
1776 len + NET_IP_ALIGN);
1777 emac_recycle_rx_skb(dev, slot, len);
1778 skb = copy_skb;
1779 } else if (unlikely(emac_alloc_rx_skb_napi(dev, slot)))
1780 goto oom;
1781
1782 skb_put(skb, len);
1783 push_packet:
1784 skb->protocol = eth_type_trans(skb, dev->ndev);
1785 emac_rx_csum(dev, skb, ctrl);
1786
1787 list_add_tail(&skb->list, &rx_list);
1788 next:
1789 ++dev->stats.rx_packets;
1790 skip:
1791 dev->stats.rx_bytes += len;
1792 slot = (slot + 1) % NUM_RX_BUFF;
1793 --budget;
1794 ++received;
1795 continue;
1796 sg:
1797 if (ctrl & MAL_RX_CTRL_FIRST) {
1798 BUG_ON(dev->rx_sg_skb);
1799 if (unlikely(emac_alloc_rx_skb_napi(dev, slot))) {
1800 DBG(dev, "rx OOM %d" NL, slot);
1801 ++dev->estats.rx_dropped_oom;
1802 emac_recycle_rx_skb(dev, slot, 0);
1803 } else {
1804 dev->rx_sg_skb = skb;
1805 skb_put(skb, len);
1806 }
1807 } else if (!emac_rx_sg_append(dev, slot) &&
1808 (ctrl & MAL_RX_CTRL_LAST)) {
1809
1810 skb = dev->rx_sg_skb;
1811 dev->rx_sg_skb = NULL;
1812
1813 ctrl &= EMAC_BAD_RX_MASK;
1814 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1815 emac_parse_rx_error(dev, ctrl);
1816 ++dev->estats.rx_dropped_error;
1817 dev_kfree_skb(skb);
1818 len = 0;
1819 } else
1820 goto push_packet;
1821 }
1822 goto skip;
1823 oom:
1824 DBG(dev, "rx OOM %d" NL, slot);
1825 /* Drop the packet and recycle skb */
1826 ++dev->estats.rx_dropped_oom;
1827 emac_recycle_rx_skb(dev, slot, 0);
1828 goto next;
1829 }
1830
1831 netif_receive_skb_list(&rx_list);
1832
1833 if (received) {
1834 DBG2(dev, "rx %d BDs" NL, received);
1835 dev->rx_slot = slot;
1836 }
1837
1838 if (unlikely(budget && test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags))) {
1839 mb();
1840 if (!(dev->rx_desc[slot].ctrl & MAL_RX_CTRL_EMPTY)) {
1841 DBG2(dev, "rx restart" NL);
1842 received = 0;
1843 goto again;
1844 }
1845
1846 if (dev->rx_sg_skb) {
1847 DBG2(dev, "dropping partial rx packet" NL);
1848 ++dev->estats.rx_dropped_error;
1849 dev_kfree_skb(dev->rx_sg_skb);
1850 dev->rx_sg_skb = NULL;
1851 }
1852
1853 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1854 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1855 emac_rx_enable(dev);
1856 dev->rx_slot = 0;
1857 }
1858 return received;
1859}
1860
1861/* NAPI poll context */
1862static int emac_peek_rx(void *param)
1863{
1864 struct emac_instance *dev = param;
1865
1866 return !(dev->rx_desc[dev->rx_slot].ctrl & MAL_RX_CTRL_EMPTY);
1867}
1868
1869/* NAPI poll context */
1870static int emac_peek_rx_sg(void *param)
1871{
1872 struct emac_instance *dev = param;
1873
1874 int slot = dev->rx_slot;
1875 while (1) {
1876 u16 ctrl = dev->rx_desc[slot].ctrl;
1877 if (ctrl & MAL_RX_CTRL_EMPTY)
1878 return 0;
1879 else if (ctrl & MAL_RX_CTRL_LAST)
1880 return 1;
1881
1882 slot = (slot + 1) % NUM_RX_BUFF;
1883
1884 /* I'm just being paranoid here :) */
1885 if (unlikely(slot == dev->rx_slot))
1886 return 0;
1887 }
1888}
1889
1890/* Hard IRQ */
1891static void emac_rxde(void *param)
1892{
1893 struct emac_instance *dev = param;
1894
1895 ++dev->estats.rx_stopped;
1896 emac_rx_disable_async(dev);
1897}
1898
1899/* Hard IRQ */
1900static irqreturn_t emac_irq(int irq, void *dev_instance)
1901{
1902 struct emac_instance *dev = dev_instance;
1903 struct emac_regs __iomem *p = dev->emacp;
1904 struct emac_error_stats *st = &dev->estats;
1905 u32 isr;
1906
1907 spin_lock(&dev->lock);
1908
1909 isr = in_be32(&p->isr);
1910 out_be32(&p->isr, isr);
1911
1912 DBG(dev, "isr = %08x" NL, isr);
1913
1914 if (isr & EMAC4_ISR_TXPE)
1915 ++st->tx_parity;
1916 if (isr & EMAC4_ISR_RXPE)
1917 ++st->rx_parity;
1918 if (isr & EMAC4_ISR_TXUE)
1919 ++st->tx_underrun;
1920 if (isr & EMAC4_ISR_RXOE)
1921 ++st->rx_fifo_overrun;
1922 if (isr & EMAC_ISR_OVR)
1923 ++st->rx_overrun;
1924 if (isr & EMAC_ISR_BP)
1925 ++st->rx_bad_packet;
1926 if (isr & EMAC_ISR_RP)
1927 ++st->rx_runt_packet;
1928 if (isr & EMAC_ISR_SE)
1929 ++st->rx_short_event;
1930 if (isr & EMAC_ISR_ALE)
1931 ++st->rx_alignment_error;
1932 if (isr & EMAC_ISR_BFCS)
1933 ++st->rx_bad_fcs;
1934 if (isr & EMAC_ISR_PTLE)
1935 ++st->rx_packet_too_long;
1936 if (isr & EMAC_ISR_ORE)
1937 ++st->rx_out_of_range;
1938 if (isr & EMAC_ISR_IRE)
1939 ++st->rx_in_range;
1940 if (isr & EMAC_ISR_SQE)
1941 ++st->tx_sqe;
1942 if (isr & EMAC_ISR_TE)
1943 ++st->tx_errors;
1944
1945 spin_unlock(&dev->lock);
1946
1947 return IRQ_HANDLED;
1948}
1949
1950static struct net_device_stats *emac_stats(struct net_device *ndev)
1951{
1952 struct emac_instance *dev = netdev_priv(ndev);
1953 struct emac_stats *st = &dev->stats;
1954 struct emac_error_stats *est = &dev->estats;
1955 struct net_device_stats *nst = &ndev->stats;
1956 unsigned long flags;
1957
1958 DBG2(dev, "stats" NL);
1959
1960 /* Compute "legacy" statistics */
1961 spin_lock_irqsave(&dev->lock, flags);
1962 nst->rx_packets = (unsigned long)st->rx_packets;
1963 nst->rx_bytes = (unsigned long)st->rx_bytes;
1964 nst->tx_packets = (unsigned long)st->tx_packets;
1965 nst->tx_bytes = (unsigned long)st->tx_bytes;
1966 nst->rx_dropped = (unsigned long)(est->rx_dropped_oom +
1967 est->rx_dropped_error +
1968 est->rx_dropped_resize +
1969 est->rx_dropped_mtu);
1970 nst->tx_dropped = (unsigned long)est->tx_dropped;
1971
1972 nst->rx_errors = (unsigned long)est->rx_bd_errors;
1973 nst->rx_fifo_errors = (unsigned long)(est->rx_bd_overrun +
1974 est->rx_fifo_overrun +
1975 est->rx_overrun);
1976 nst->rx_frame_errors = (unsigned long)(est->rx_bd_alignment_error +
1977 est->rx_alignment_error);
1978 nst->rx_crc_errors = (unsigned long)(est->rx_bd_bad_fcs +
1979 est->rx_bad_fcs);
1980 nst->rx_length_errors = (unsigned long)(est->rx_bd_runt_packet +
1981 est->rx_bd_short_event +
1982 est->rx_bd_packet_too_long +
1983 est->rx_bd_out_of_range +
1984 est->rx_bd_in_range +
1985 est->rx_runt_packet +
1986 est->rx_short_event +
1987 est->rx_packet_too_long +
1988 est->rx_out_of_range +
1989 est->rx_in_range);
1990
1991 nst->tx_errors = (unsigned long)(est->tx_bd_errors + est->tx_errors);
1992 nst->tx_fifo_errors = (unsigned long)(est->tx_bd_underrun +
1993 est->tx_underrun);
1994 nst->tx_carrier_errors = (unsigned long)est->tx_bd_carrier_loss;
1995 nst->collisions = (unsigned long)(est->tx_bd_excessive_deferral +
1996 est->tx_bd_excessive_collisions +
1997 est->tx_bd_late_collision +
1998 est->tx_bd_multple_collisions);
1999 spin_unlock_irqrestore(&dev->lock, flags);
2000 return nst;
2001}
2002
2003static struct mal_commac_ops emac_commac_ops = {
2004 .poll_tx = &emac_poll_tx,
2005 .poll_rx = &emac_poll_rx,
2006 .peek_rx = &emac_peek_rx,
2007 .rxde = &emac_rxde,
2008};
2009
2010static struct mal_commac_ops emac_commac_sg_ops = {
2011 .poll_tx = &emac_poll_tx,
2012 .poll_rx = &emac_poll_rx,
2013 .peek_rx = &emac_peek_rx_sg,
2014 .rxde = &emac_rxde,
2015};
2016
2017/* Ethtool support */
2018static int emac_ethtool_get_link_ksettings(struct net_device *ndev,
2019 struct ethtool_link_ksettings *cmd)
2020{
2021 struct emac_instance *dev = netdev_priv(ndev);
2022 u32 supported, advertising;
2023
2024 supported = dev->phy.features;
2025 cmd->base.port = PORT_MII;
2026 cmd->base.phy_address = dev->phy.address;
2027
2028 mutex_lock(&dev->link_lock);
2029 advertising = dev->phy.advertising;
2030 cmd->base.autoneg = dev->phy.autoneg;
2031 cmd->base.speed = dev->phy.speed;
2032 cmd->base.duplex = dev->phy.duplex;
2033 mutex_unlock(&dev->link_lock);
2034
2035 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2036 supported);
2037 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2038 advertising);
2039
2040 return 0;
2041}
2042
2043static int
2044emac_ethtool_set_link_ksettings(struct net_device *ndev,
2045 const struct ethtool_link_ksettings *cmd)
2046{
2047 struct emac_instance *dev = netdev_priv(ndev);
2048 u32 f = dev->phy.features;
2049 u32 advertising;
2050
2051 ethtool_convert_link_mode_to_legacy_u32(&advertising,
2052 cmd->link_modes.advertising);
2053
2054 DBG(dev, "set_settings(%d, %d, %d, 0x%08x)" NL,
2055 cmd->base.autoneg, cmd->base.speed, cmd->base.duplex, advertising);
2056
2057 /* Basic sanity checks */
2058 if (dev->phy.address < 0)
2059 return -EOPNOTSUPP;
2060 if (cmd->base.autoneg != AUTONEG_ENABLE &&
2061 cmd->base.autoneg != AUTONEG_DISABLE)
2062 return -EINVAL;
2063 if (cmd->base.autoneg == AUTONEG_ENABLE && advertising == 0)
2064 return -EINVAL;
2065 if (cmd->base.duplex != DUPLEX_HALF && cmd->base.duplex != DUPLEX_FULL)
2066 return -EINVAL;
2067
2068 if (cmd->base.autoneg == AUTONEG_DISABLE) {
2069 switch (cmd->base.speed) {
2070 case SPEED_10:
2071 if (cmd->base.duplex == DUPLEX_HALF &&
2072 !(f & SUPPORTED_10baseT_Half))
2073 return -EINVAL;
2074 if (cmd->base.duplex == DUPLEX_FULL &&
2075 !(f & SUPPORTED_10baseT_Full))
2076 return -EINVAL;
2077 break;
2078 case SPEED_100:
2079 if (cmd->base.duplex == DUPLEX_HALF &&
2080 !(f & SUPPORTED_100baseT_Half))
2081 return -EINVAL;
2082 if (cmd->base.duplex == DUPLEX_FULL &&
2083 !(f & SUPPORTED_100baseT_Full))
2084 return -EINVAL;
2085 break;
2086 case SPEED_1000:
2087 if (cmd->base.duplex == DUPLEX_HALF &&
2088 !(f & SUPPORTED_1000baseT_Half))
2089 return -EINVAL;
2090 if (cmd->base.duplex == DUPLEX_FULL &&
2091 !(f & SUPPORTED_1000baseT_Full))
2092 return -EINVAL;
2093 break;
2094 default:
2095 return -EINVAL;
2096 }
2097
2098 mutex_lock(&dev->link_lock);
2099 dev->phy.def->ops->setup_forced(&dev->phy, cmd->base.speed,
2100 cmd->base.duplex);
2101 mutex_unlock(&dev->link_lock);
2102
2103 } else {
2104 if (!(f & SUPPORTED_Autoneg))
2105 return -EINVAL;
2106
2107 mutex_lock(&dev->link_lock);
2108 dev->phy.def->ops->setup_aneg(&dev->phy,
2109 (advertising & f) |
2110 (dev->phy.advertising &
2111 (ADVERTISED_Pause |
2112 ADVERTISED_Asym_Pause)));
2113 mutex_unlock(&dev->link_lock);
2114 }
2115 emac_force_link_update(dev);
2116
2117 return 0;
2118}
2119
2120static void
2121emac_ethtool_get_ringparam(struct net_device *ndev,
2122 struct ethtool_ringparam *rp,
2123 struct kernel_ethtool_ringparam *kernel_rp,
2124 struct netlink_ext_ack *extack)
2125{
2126 rp->rx_max_pending = rp->rx_pending = NUM_RX_BUFF;
2127 rp->tx_max_pending = rp->tx_pending = NUM_TX_BUFF;
2128}
2129
2130static void emac_ethtool_get_pauseparam(struct net_device *ndev,
2131 struct ethtool_pauseparam *pp)
2132{
2133 struct emac_instance *dev = netdev_priv(ndev);
2134
2135 mutex_lock(&dev->link_lock);
2136 if ((dev->phy.features & SUPPORTED_Autoneg) &&
2137 (dev->phy.advertising & (ADVERTISED_Pause | ADVERTISED_Asym_Pause)))
2138 pp->autoneg = 1;
2139
2140 if (dev->phy.duplex == DUPLEX_FULL) {
2141 if (dev->phy.pause)
2142 pp->rx_pause = pp->tx_pause = 1;
2143 else if (dev->phy.asym_pause)
2144 pp->tx_pause = 1;
2145 }
2146 mutex_unlock(&dev->link_lock);
2147}
2148
2149static int emac_get_regs_len(struct emac_instance *dev)
2150{
2151 return sizeof(struct emac_ethtool_regs_subhdr) +
2152 sizeof(struct emac_regs);
2153}
2154
2155static int emac_ethtool_get_regs_len(struct net_device *ndev)
2156{
2157 struct emac_instance *dev = netdev_priv(ndev);
2158 int size;
2159
2160 size = sizeof(struct emac_ethtool_regs_hdr) +
2161 emac_get_regs_len(dev) + mal_get_regs_len(dev->mal);
2162 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2163 size += zmii_get_regs_len(dev->zmii_dev);
2164 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2165 size += rgmii_get_regs_len(dev->rgmii_dev);
2166 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2167 size += tah_get_regs_len(dev->tah_dev);
2168
2169 return size;
2170}
2171
2172static void *emac_dump_regs(struct emac_instance *dev, void *buf)
2173{
2174 struct emac_ethtool_regs_subhdr *hdr = buf;
2175
2176 hdr->index = dev->cell_index;
2177 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) {
2178 hdr->version = EMAC4SYNC_ETHTOOL_REGS_VER;
2179 } else if (emac_has_feature(dev, EMAC_FTR_EMAC4)) {
2180 hdr->version = EMAC4_ETHTOOL_REGS_VER;
2181 } else {
2182 hdr->version = EMAC_ETHTOOL_REGS_VER;
2183 }
2184 memcpy_fromio(hdr + 1, dev->emacp, sizeof(struct emac_regs));
2185 return (void *)(hdr + 1) + sizeof(struct emac_regs);
2186}
2187
2188static void emac_ethtool_get_regs(struct net_device *ndev,
2189 struct ethtool_regs *regs, void *buf)
2190{
2191 struct emac_instance *dev = netdev_priv(ndev);
2192 struct emac_ethtool_regs_hdr *hdr = buf;
2193
2194 hdr->components = 0;
2195 buf = hdr + 1;
2196
2197 buf = mal_dump_regs(dev->mal, buf);
2198 buf = emac_dump_regs(dev, buf);
2199 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) {
2200 hdr->components |= EMAC_ETHTOOL_REGS_ZMII;
2201 buf = zmii_dump_regs(dev->zmii_dev, buf);
2202 }
2203 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) {
2204 hdr->components |= EMAC_ETHTOOL_REGS_RGMII;
2205 buf = rgmii_dump_regs(dev->rgmii_dev, buf);
2206 }
2207 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) {
2208 hdr->components |= EMAC_ETHTOOL_REGS_TAH;
2209 buf = tah_dump_regs(dev->tah_dev, buf);
2210 }
2211}
2212
2213static int emac_ethtool_nway_reset(struct net_device *ndev)
2214{
2215 struct emac_instance *dev = netdev_priv(ndev);
2216 int res = 0;
2217
2218 DBG(dev, "nway_reset" NL);
2219
2220 if (dev->phy.address < 0)
2221 return -EOPNOTSUPP;
2222
2223 mutex_lock(&dev->link_lock);
2224 if (!dev->phy.autoneg) {
2225 res = -EINVAL;
2226 goto out;
2227 }
2228
2229 dev->phy.def->ops->setup_aneg(&dev->phy, dev->phy.advertising);
2230 out:
2231 mutex_unlock(&dev->link_lock);
2232 emac_force_link_update(dev);
2233 return res;
2234}
2235
2236static int emac_ethtool_get_sset_count(struct net_device *ndev, int stringset)
2237{
2238 if (stringset == ETH_SS_STATS)
2239 return EMAC_ETHTOOL_STATS_COUNT;
2240 else
2241 return -EINVAL;
2242}
2243
2244static void emac_ethtool_get_strings(struct net_device *ndev, u32 stringset,
2245 u8 * buf)
2246{
2247 if (stringset == ETH_SS_STATS)
2248 memcpy(buf, &emac_stats_keys, sizeof(emac_stats_keys));
2249}
2250
2251static void emac_ethtool_get_ethtool_stats(struct net_device *ndev,
2252 struct ethtool_stats *estats,
2253 u64 * tmp_stats)
2254{
2255 struct emac_instance *dev = netdev_priv(ndev);
2256
2257 memcpy(tmp_stats, &dev->stats, sizeof(dev->stats));
2258 tmp_stats += sizeof(dev->stats) / sizeof(u64);
2259 memcpy(tmp_stats, &dev->estats, sizeof(dev->estats));
2260}
2261
2262static void emac_ethtool_get_drvinfo(struct net_device *ndev,
2263 struct ethtool_drvinfo *info)
2264{
2265 struct emac_instance *dev = netdev_priv(ndev);
2266
2267 strscpy(info->driver, "ibm_emac", sizeof(info->driver));
2268 strscpy(info->version, DRV_VERSION, sizeof(info->version));
2269 snprintf(info->bus_info, sizeof(info->bus_info), "PPC 4xx EMAC-%d %pOF",
2270 dev->cell_index, dev->ofdev->dev.of_node);
2271}
2272
2273static const struct ethtool_ops emac_ethtool_ops = {
2274 .get_drvinfo = emac_ethtool_get_drvinfo,
2275
2276 .get_regs_len = emac_ethtool_get_regs_len,
2277 .get_regs = emac_ethtool_get_regs,
2278
2279 .nway_reset = emac_ethtool_nway_reset,
2280
2281 .get_ringparam = emac_ethtool_get_ringparam,
2282 .get_pauseparam = emac_ethtool_get_pauseparam,
2283
2284 .get_strings = emac_ethtool_get_strings,
2285 .get_sset_count = emac_ethtool_get_sset_count,
2286 .get_ethtool_stats = emac_ethtool_get_ethtool_stats,
2287
2288 .get_link = ethtool_op_get_link,
2289 .get_link_ksettings = emac_ethtool_get_link_ksettings,
2290 .set_link_ksettings = emac_ethtool_set_link_ksettings,
2291};
2292
2293static int emac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2294{
2295 struct emac_instance *dev = netdev_priv(ndev);
2296 struct mii_ioctl_data *data = if_mii(rq);
2297
2298 DBG(dev, "ioctl %08x" NL, cmd);
2299
2300 if (dev->phy.address < 0)
2301 return -EOPNOTSUPP;
2302
2303 switch (cmd) {
2304 case SIOCGMIIPHY:
2305 data->phy_id = dev->phy.address;
2306 fallthrough;
2307 case SIOCGMIIREG:
2308 data->val_out = emac_mdio_read(ndev, dev->phy.address,
2309 data->reg_num);
2310 return 0;
2311
2312 case SIOCSMIIREG:
2313 emac_mdio_write(ndev, dev->phy.address, data->reg_num,
2314 data->val_in);
2315 return 0;
2316 default:
2317 return -EOPNOTSUPP;
2318 }
2319}
2320
2321struct emac_depentry {
2322 u32 phandle;
2323 struct device_node *node;
2324 struct platform_device *ofdev;
2325 void *drvdata;
2326};
2327
2328#define EMAC_DEP_MAL_IDX 0
2329#define EMAC_DEP_ZMII_IDX 1
2330#define EMAC_DEP_RGMII_IDX 2
2331#define EMAC_DEP_TAH_IDX 3
2332#define EMAC_DEP_MDIO_IDX 4
2333#define EMAC_DEP_PREV_IDX 5
2334#define EMAC_DEP_COUNT 6
2335
2336static int emac_check_deps(struct emac_instance *dev,
2337 struct emac_depentry *deps)
2338{
2339 int i, there = 0;
2340 struct device_node *np;
2341
2342 for (i = 0; i < EMAC_DEP_COUNT; i++) {
2343 /* no dependency on that item, allright */
2344 if (deps[i].phandle == 0) {
2345 there++;
2346 continue;
2347 }
2348 /* special case for blist as the dependency might go away */
2349 if (i == EMAC_DEP_PREV_IDX) {
2350 np = *(dev->blist - 1);
2351 if (np == NULL) {
2352 deps[i].phandle = 0;
2353 there++;
2354 continue;
2355 }
2356 if (deps[i].node == NULL)
2357 deps[i].node = of_node_get(np);
2358 }
2359 if (deps[i].node == NULL)
2360 deps[i].node = of_find_node_by_phandle(deps[i].phandle);
2361 if (deps[i].node == NULL)
2362 continue;
2363 if (deps[i].ofdev == NULL)
2364 deps[i].ofdev = of_find_device_by_node(deps[i].node);
2365 if (deps[i].ofdev == NULL)
2366 continue;
2367 if (deps[i].drvdata == NULL)
2368 deps[i].drvdata = platform_get_drvdata(deps[i].ofdev);
2369 if (deps[i].drvdata != NULL)
2370 there++;
2371 }
2372 if (there != EMAC_DEP_COUNT)
2373 return -EPROBE_DEFER;
2374 return 0;
2375}
2376
2377static void emac_put_deps(struct emac_instance *dev)
2378{
2379 platform_device_put(dev->mal_dev);
2380 platform_device_put(dev->zmii_dev);
2381 platform_device_put(dev->rgmii_dev);
2382 platform_device_put(dev->mdio_dev);
2383 platform_device_put(dev->tah_dev);
2384}
2385
2386static int emac_wait_deps(struct emac_instance *dev)
2387{
2388 struct emac_depentry deps[EMAC_DEP_COUNT];
2389 int i, err;
2390
2391 memset(&deps, 0, sizeof(deps));
2392
2393 deps[EMAC_DEP_MAL_IDX].phandle = dev->mal_ph;
2394 deps[EMAC_DEP_ZMII_IDX].phandle = dev->zmii_ph;
2395 deps[EMAC_DEP_RGMII_IDX].phandle = dev->rgmii_ph;
2396 if (dev->tah_ph)
2397 deps[EMAC_DEP_TAH_IDX].phandle = dev->tah_ph;
2398 if (dev->mdio_ph)
2399 deps[EMAC_DEP_MDIO_IDX].phandle = dev->mdio_ph;
2400 if (dev->blist && dev->blist > emac_boot_list)
2401 deps[EMAC_DEP_PREV_IDX].phandle = 0xffffffffu;
2402 err = emac_check_deps(dev, deps);
2403 for (i = 0; i < EMAC_DEP_COUNT; i++) {
2404 of_node_put(deps[i].node);
2405 if (err)
2406 platform_device_put(deps[i].ofdev);
2407 }
2408 if (!err) {
2409 dev->mal_dev = deps[EMAC_DEP_MAL_IDX].ofdev;
2410 dev->zmii_dev = deps[EMAC_DEP_ZMII_IDX].ofdev;
2411 dev->rgmii_dev = deps[EMAC_DEP_RGMII_IDX].ofdev;
2412 dev->tah_dev = deps[EMAC_DEP_TAH_IDX].ofdev;
2413 dev->mdio_dev = deps[EMAC_DEP_MDIO_IDX].ofdev;
2414 }
2415 platform_device_put(deps[EMAC_DEP_PREV_IDX].ofdev);
2416 return err;
2417}
2418
2419static int emac_read_uint_prop(struct device_node *np, const char *name,
2420 u32 *val, int fatal)
2421{
2422 int err;
2423
2424 err = of_property_read_u32(np, name, val);
2425 if (err) {
2426 if (fatal)
2427 pr_err("%pOF: missing %s property", np, name);
2428 return err;
2429 }
2430 return 0;
2431}
2432
2433static void emac_adjust_link(struct net_device *ndev)
2434{
2435 struct emac_instance *dev = netdev_priv(ndev);
2436 struct phy_device *phy = ndev->phydev;
2437
2438 dev->phy.autoneg = phy->autoneg;
2439 dev->phy.speed = phy->speed;
2440 dev->phy.duplex = phy->duplex;
2441 dev->phy.pause = phy->pause;
2442 dev->phy.asym_pause = phy->asym_pause;
2443 ethtool_convert_link_mode_to_legacy_u32(&dev->phy.advertising,
2444 phy->advertising);
2445}
2446
2447static int emac_mii_bus_read(struct mii_bus *bus, int addr, int regnum)
2448{
2449 int ret = emac_mdio_read(bus->priv, addr, regnum);
2450 /* This is a workaround for powered down ports/phys.
2451 * In the wild, this was seen on the Cisco Meraki MX60(W).
2452 * This hardware disables ports as part of the handoff
2453 * procedure. Accessing the ports will lead to errors
2454 * (-ETIMEDOUT, -EREMOTEIO) that do more harm than good.
2455 */
2456 return ret < 0 ? 0xffff : ret;
2457}
2458
2459static int emac_mii_bus_write(struct mii_bus *bus, int addr,
2460 int regnum, u16 val)
2461{
2462 emac_mdio_write(bus->priv, addr, regnum, val);
2463 return 0;
2464}
2465
2466static int emac_mii_bus_reset(struct mii_bus *bus)
2467{
2468 struct emac_instance *dev = netdev_priv(bus->priv);
2469
2470 return emac_reset(dev);
2471}
2472
2473static int emac_mdio_phy_start_aneg(struct mii_phy *phy,
2474 struct phy_device *phy_dev)
2475{
2476 phy_dev->autoneg = phy->autoneg;
2477 phy_dev->speed = phy->speed;
2478 phy_dev->duplex = phy->duplex;
2479 ethtool_convert_legacy_u32_to_link_mode(phy_dev->advertising,
2480 phy->advertising);
2481 return phy_start_aneg(phy_dev);
2482}
2483
2484static int emac_mdio_setup_aneg(struct mii_phy *phy, u32 advertise)
2485{
2486 struct net_device *ndev = phy->dev;
2487
2488 phy->autoneg = AUTONEG_ENABLE;
2489 phy->advertising = advertise;
2490 return emac_mdio_phy_start_aneg(phy, ndev->phydev);
2491}
2492
2493static int emac_mdio_setup_forced(struct mii_phy *phy, int speed, int fd)
2494{
2495 struct net_device *ndev = phy->dev;
2496
2497 phy->autoneg = AUTONEG_DISABLE;
2498 phy->speed = speed;
2499 phy->duplex = fd;
2500 return emac_mdio_phy_start_aneg(phy, ndev->phydev);
2501}
2502
2503static int emac_mdio_poll_link(struct mii_phy *phy)
2504{
2505 struct net_device *ndev = phy->dev;
2506 struct emac_instance *dev = netdev_priv(ndev);
2507 int res;
2508
2509 res = phy_read_status(ndev->phydev);
2510 if (res) {
2511 dev_err(&dev->ofdev->dev, "link update failed (%d).", res);
2512 return ethtool_op_get_link(ndev);
2513 }
2514
2515 return ndev->phydev->link;
2516}
2517
2518static int emac_mdio_read_link(struct mii_phy *phy)
2519{
2520 struct net_device *ndev = phy->dev;
2521 struct phy_device *phy_dev = ndev->phydev;
2522 int res;
2523
2524 res = phy_read_status(phy_dev);
2525 if (res)
2526 return res;
2527
2528 phy->speed = phy_dev->speed;
2529 phy->duplex = phy_dev->duplex;
2530 phy->pause = phy_dev->pause;
2531 phy->asym_pause = phy_dev->asym_pause;
2532 return 0;
2533}
2534
2535static int emac_mdio_init_phy(struct mii_phy *phy)
2536{
2537 struct net_device *ndev = phy->dev;
2538
2539 phy_start(ndev->phydev);
2540 return phy_init_hw(ndev->phydev);
2541}
2542
2543static const struct mii_phy_ops emac_dt_mdio_phy_ops = {
2544 .init = emac_mdio_init_phy,
2545 .setup_aneg = emac_mdio_setup_aneg,
2546 .setup_forced = emac_mdio_setup_forced,
2547 .poll_link = emac_mdio_poll_link,
2548 .read_link = emac_mdio_read_link,
2549};
2550
2551static int emac_dt_mdio_probe(struct emac_instance *dev)
2552{
2553 struct device_node *mii_np;
2554 struct mii_bus *bus;
2555 int res;
2556
2557 mii_np = of_get_child_by_name(dev->ofdev->dev.of_node, "mdio");
2558 if (!mii_np) {
2559 dev_err(&dev->ofdev->dev, "no mdio definition found.");
2560 return -ENODEV;
2561 }
2562
2563 if (!of_device_is_available(mii_np)) {
2564 res = -ENODEV;
2565 goto put_node;
2566 }
2567
2568 bus = devm_mdiobus_alloc(&dev->ofdev->dev);
2569 if (!bus) {
2570 res = -ENOMEM;
2571 goto put_node;
2572 }
2573
2574 bus->priv = dev->ndev;
2575 bus->parent = dev->ndev->dev.parent;
2576 bus->name = "emac_mdio";
2577 bus->read = &emac_mii_bus_read;
2578 bus->write = &emac_mii_bus_write;
2579 bus->reset = &emac_mii_bus_reset;
2580 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev->ofdev->name);
2581 res = devm_of_mdiobus_register(&dev->ofdev->dev, bus, mii_np);
2582 if (res) {
2583 dev_err(&dev->ofdev->dev, "cannot register MDIO bus %s (%d)",
2584 bus->name, res);
2585 }
2586
2587 put_node:
2588 of_node_put(mii_np);
2589 return res;
2590}
2591
2592static int emac_dt_phy_connect(struct emac_instance *dev,
2593 struct device_node *phy_handle)
2594{
2595 struct phy_device *phy_dev;
2596
2597 dev->phy.def = devm_kzalloc(&dev->ofdev->dev, sizeof(*dev->phy.def),
2598 GFP_KERNEL);
2599 if (!dev->phy.def)
2600 return -ENOMEM;
2601
2602 phy_dev = of_phy_connect(dev->ndev, phy_handle, &emac_adjust_link, 0,
2603 dev->phy_mode);
2604 if (!phy_dev) {
2605 dev_err(&dev->ofdev->dev, "failed to connect to PHY.\n");
2606 return -ENODEV;
2607 }
2608
2609 dev->phy.def->phy_id = phy_dev->drv->phy_id;
2610 dev->phy.def->phy_id_mask = phy_dev->drv->phy_id_mask;
2611 dev->phy.def->name = phy_dev->drv->name;
2612 dev->phy.def->ops = &emac_dt_mdio_phy_ops;
2613 ethtool_convert_link_mode_to_legacy_u32(&dev->phy.features,
2614 phy_dev->supported);
2615 dev->phy.address = phy_dev->mdio.addr;
2616 dev->phy.mode = phy_dev->interface;
2617 return 0;
2618}
2619
2620static int emac_dt_phy_probe(struct emac_instance *dev)
2621{
2622 struct device_node *np = dev->ofdev->dev.of_node;
2623 struct device_node *phy_handle;
2624 int res = 1;
2625
2626 phy_handle = of_parse_phandle(np, "phy-handle", 0);
2627
2628 if (phy_handle) {
2629 res = emac_dt_mdio_probe(dev);
2630 if (!res) {
2631 res = emac_dt_phy_connect(dev, phy_handle);
2632 }
2633 }
2634
2635 of_node_put(phy_handle);
2636 return res;
2637}
2638
2639static int emac_init_phy(struct emac_instance *dev)
2640{
2641 struct device_node *np = dev->ofdev->dev.of_node;
2642 struct net_device *ndev = dev->ndev;
2643 u32 phy_map, adv;
2644 int i;
2645
2646 dev->phy.dev = ndev;
2647 dev->phy.mode = dev->phy_mode;
2648
2649 /* PHY-less configuration. */
2650 if ((dev->phy_address == 0xffffffff && dev->phy_map == 0xffffffff) ||
2651 of_phy_is_fixed_link(np)) {
2652 emac_reset(dev);
2653
2654 /* PHY-less configuration. */
2655 dev->phy.address = -1;
2656 dev->phy.features = SUPPORTED_MII;
2657 if (emac_phy_supports_gige(dev->phy_mode))
2658 dev->phy.features |= SUPPORTED_1000baseT_Full;
2659 else
2660 dev->phy.features |= SUPPORTED_100baseT_Full;
2661 dev->phy.pause = 1;
2662
2663 if (of_phy_is_fixed_link(np)) {
2664 int res = emac_dt_mdio_probe(dev);
2665
2666 if (res)
2667 return res;
2668
2669 res = of_phy_register_fixed_link(np);
2670 ndev->phydev = of_phy_find_device(np);
2671 if (res || !ndev->phydev)
2672 return res ? res : -EINVAL;
2673 emac_adjust_link(dev->ndev);
2674 put_device(&ndev->phydev->mdio.dev);
2675 }
2676 return 0;
2677 }
2678
2679 mutex_lock(&emac_phy_map_lock);
2680 phy_map = dev->phy_map | busy_phy_map;
2681
2682 DBG(dev, "PHY maps %08x %08x" NL, dev->phy_map, busy_phy_map);
2683
2684 dev->phy.mdio_read = emac_mdio_read;
2685 dev->phy.mdio_write = emac_mdio_write;
2686
2687 /* Enable internal clock source */
2688#ifdef CONFIG_PPC_DCR_NATIVE
2689 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2690 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
2691#endif
2692 /* PHY clock workaround */
2693 emac_rx_clk_tx(dev);
2694
2695 /* Enable internal clock source on 440GX*/
2696#ifdef CONFIG_PPC_DCR_NATIVE
2697 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2698 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
2699#endif
2700 /* Configure EMAC with defaults so we can at least use MDIO
2701 * This is needed mostly for 440GX
2702 */
2703 if (emac_phy_gpcs(dev->phy.mode)) {
2704 /* XXX
2705 * Make GPCS PHY address equal to EMAC index.
2706 * We probably should take into account busy_phy_map
2707 * and/or phy_map here.
2708 *
2709 * Note that the busy_phy_map is currently global
2710 * while it should probably be per-ASIC...
2711 */
2712 dev->phy.gpcs_address = dev->gpcs_address;
2713 if (dev->phy.gpcs_address == 0xffffffff)
2714 dev->phy.address = dev->cell_index;
2715 }
2716
2717 emac_configure(dev);
2718
2719 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) {
2720 int res = emac_dt_phy_probe(dev);
2721
2722 switch (res) {
2723 case 1:
2724 /* No phy-handle property configured.
2725 * Continue with the existing phy probe
2726 * and setup code.
2727 */
2728 break;
2729
2730 case 0:
2731 mutex_unlock(&emac_phy_map_lock);
2732 goto init_phy;
2733
2734 default:
2735 mutex_unlock(&emac_phy_map_lock);
2736 dev_err(&dev->ofdev->dev, "failed to attach dt phy (%d).\n",
2737 res);
2738 return res;
2739 }
2740 }
2741
2742 if (dev->phy_address != 0xffffffff)
2743 phy_map = ~(1 << dev->phy_address);
2744
2745 for (i = 0; i < 0x20; phy_map >>= 1, ++i)
2746 if (!(phy_map & 1)) {
2747 int r;
2748 busy_phy_map |= 1 << i;
2749
2750 /* Quick check if there is a PHY at the address */
2751 r = emac_mdio_read(dev->ndev, i, MII_BMCR);
2752 if (r == 0xffff || r < 0)
2753 continue;
2754 if (!emac_mii_phy_probe(&dev->phy, i))
2755 break;
2756 }
2757
2758 /* Enable external clock source */
2759#ifdef CONFIG_PPC_DCR_NATIVE
2760 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2761 dcri_clrset(SDR0, SDR0_MFR, SDR0_MFR_ECS, 0);
2762#endif
2763 mutex_unlock(&emac_phy_map_lock);
2764 if (i == 0x20) {
2765 printk(KERN_WARNING "%pOF: can't find PHY!\n", np);
2766 return -ENXIO;
2767 }
2768
2769 init_phy:
2770 /* Init PHY */
2771 if (dev->phy.def->ops->init)
2772 dev->phy.def->ops->init(&dev->phy);
2773
2774 /* Disable any PHY features not supported by the platform */
2775 dev->phy.def->features &= ~dev->phy_feat_exc;
2776 dev->phy.features &= ~dev->phy_feat_exc;
2777
2778 /* Setup initial link parameters */
2779 if (dev->phy.features & SUPPORTED_Autoneg) {
2780 adv = dev->phy.features;
2781 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x))
2782 adv |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
2783 /* Restart autonegotiation */
2784 dev->phy.def->ops->setup_aneg(&dev->phy, adv);
2785 } else {
2786 u32 f = dev->phy.def->features;
2787 int speed = SPEED_10, fd = DUPLEX_HALF;
2788
2789 /* Select highest supported speed/duplex */
2790 if (f & SUPPORTED_1000baseT_Full) {
2791 speed = SPEED_1000;
2792 fd = DUPLEX_FULL;
2793 } else if (f & SUPPORTED_1000baseT_Half)
2794 speed = SPEED_1000;
2795 else if (f & SUPPORTED_100baseT_Full) {
2796 speed = SPEED_100;
2797 fd = DUPLEX_FULL;
2798 } else if (f & SUPPORTED_100baseT_Half)
2799 speed = SPEED_100;
2800 else if (f & SUPPORTED_10baseT_Full)
2801 fd = DUPLEX_FULL;
2802
2803 /* Force link parameters */
2804 dev->phy.def->ops->setup_forced(&dev->phy, speed, fd);
2805 }
2806 return 0;
2807}
2808
2809static int emac_init_config(struct emac_instance *dev)
2810{
2811 struct device_node *np = dev->ofdev->dev.of_node;
2812 int err;
2813
2814 /* Read config from device-tree */
2815 if (emac_read_uint_prop(np, "mal-device", &dev->mal_ph, 1))
2816 return -ENXIO;
2817 if (emac_read_uint_prop(np, "mal-tx-channel", &dev->mal_tx_chan, 1))
2818 return -ENXIO;
2819 if (emac_read_uint_prop(np, "mal-rx-channel", &dev->mal_rx_chan, 1))
2820 return -ENXIO;
2821 if (emac_read_uint_prop(np, "cell-index", &dev->cell_index, 1))
2822 return -ENXIO;
2823 if (emac_read_uint_prop(np, "max-frame-size", &dev->max_mtu, 0))
2824 dev->max_mtu = ETH_DATA_LEN;
2825 if (emac_read_uint_prop(np, "rx-fifo-size", &dev->rx_fifo_size, 0))
2826 dev->rx_fifo_size = 2048;
2827 if (emac_read_uint_prop(np, "tx-fifo-size", &dev->tx_fifo_size, 0))
2828 dev->tx_fifo_size = 2048;
2829 if (emac_read_uint_prop(np, "rx-fifo-size-gige", &dev->rx_fifo_size_gige, 0))
2830 dev->rx_fifo_size_gige = dev->rx_fifo_size;
2831 if (emac_read_uint_prop(np, "tx-fifo-size-gige", &dev->tx_fifo_size_gige, 0))
2832 dev->tx_fifo_size_gige = dev->tx_fifo_size;
2833 if (emac_read_uint_prop(np, "phy-address", &dev->phy_address, 0))
2834 dev->phy_address = 0xffffffff;
2835 if (emac_read_uint_prop(np, "phy-map", &dev->phy_map, 0))
2836 dev->phy_map = 0xffffffff;
2837 if (emac_read_uint_prop(np, "gpcs-address", &dev->gpcs_address, 0))
2838 dev->gpcs_address = 0xffffffff;
2839 if (emac_read_uint_prop(np->parent, "clock-frequency", &dev->opb_bus_freq, 1))
2840 return -ENXIO;
2841 if (emac_read_uint_prop(np, "tah-device", &dev->tah_ph, 0))
2842 dev->tah_ph = 0;
2843 if (emac_read_uint_prop(np, "tah-channel", &dev->tah_port, 0))
2844 dev->tah_port = 0;
2845 if (emac_read_uint_prop(np, "mdio-device", &dev->mdio_ph, 0))
2846 dev->mdio_ph = 0;
2847 if (emac_read_uint_prop(np, "zmii-device", &dev->zmii_ph, 0))
2848 dev->zmii_ph = 0;
2849 if (emac_read_uint_prop(np, "zmii-channel", &dev->zmii_port, 0))
2850 dev->zmii_port = 0xffffffff;
2851 if (emac_read_uint_prop(np, "rgmii-device", &dev->rgmii_ph, 0))
2852 dev->rgmii_ph = 0;
2853 if (emac_read_uint_prop(np, "rgmii-channel", &dev->rgmii_port, 0))
2854 dev->rgmii_port = 0xffffffff;
2855 if (emac_read_uint_prop(np, "fifo-entry-size", &dev->fifo_entry_size, 0))
2856 dev->fifo_entry_size = 16;
2857 if (emac_read_uint_prop(np, "mal-burst-size", &dev->mal_burst_size, 0))
2858 dev->mal_burst_size = 256;
2859
2860 /* PHY mode needs some decoding */
2861 err = of_get_phy_mode(np, &dev->phy_mode);
2862 if (err)
2863 dev->phy_mode = PHY_INTERFACE_MODE_NA;
2864
2865 /* Check EMAC version */
2866 if (of_device_is_compatible(np, "ibm,emac4sync")) {
2867 dev->features |= (EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC);
2868 if (of_device_is_compatible(np, "ibm,emac-460ex") ||
2869 of_device_is_compatible(np, "ibm,emac-460gt"))
2870 dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX;
2871 if (of_device_is_compatible(np, "ibm,emac-405ex") ||
2872 of_device_is_compatible(np, "ibm,emac-405exr"))
2873 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
2874 if (of_device_is_compatible(np, "ibm,emac-apm821xx")) {
2875 dev->features |= (EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE |
2876 EMAC_FTR_APM821XX_NO_HALF_DUPLEX |
2877 EMAC_FTR_460EX_PHY_CLK_FIX);
2878 }
2879 } else if (of_device_is_compatible(np, "ibm,emac4")) {
2880 dev->features |= EMAC_FTR_EMAC4;
2881 if (of_device_is_compatible(np, "ibm,emac-440gx"))
2882 dev->features |= EMAC_FTR_440GX_PHY_CLK_FIX;
2883 } else {
2884 if (of_device_is_compatible(np, "ibm,emac-440ep") ||
2885 of_device_is_compatible(np, "ibm,emac-440gr"))
2886 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
2887 if (of_device_is_compatible(np, "ibm,emac-405ez")) {
2888#ifdef CONFIG_IBM_EMAC_NO_FLOW_CTRL
2889 dev->features |= EMAC_FTR_NO_FLOW_CONTROL_40x;
2890#else
2891 printk(KERN_ERR "%pOF: Flow control not disabled!\n",
2892 np);
2893 return -ENXIO;
2894#endif
2895 }
2896
2897 }
2898
2899 /* Fixup some feature bits based on the device tree */
2900 if (of_property_read_bool(np, "has-inverted-stacr-oc"))
2901 dev->features |= EMAC_FTR_STACR_OC_INVERT;
2902 if (of_property_read_bool(np, "has-new-stacr-staopc"))
2903 dev->features |= EMAC_FTR_HAS_NEW_STACR;
2904
2905 /* CAB lacks the appropriate properties */
2906 if (of_device_is_compatible(np, "ibm,emac-axon"))
2907 dev->features |= EMAC_FTR_HAS_NEW_STACR |
2908 EMAC_FTR_STACR_OC_INVERT;
2909
2910 /* Enable TAH/ZMII/RGMII features as found */
2911 if (dev->tah_ph != 0) {
2912#ifdef CONFIG_IBM_EMAC_TAH
2913 dev->features |= EMAC_FTR_HAS_TAH;
2914#else
2915 printk(KERN_ERR "%pOF: TAH support not enabled !\n", np);
2916 return -ENXIO;
2917#endif
2918 }
2919
2920 if (dev->zmii_ph != 0) {
2921#ifdef CONFIG_IBM_EMAC_ZMII
2922 dev->features |= EMAC_FTR_HAS_ZMII;
2923#else
2924 printk(KERN_ERR "%pOF: ZMII support not enabled !\n", np);
2925 return -ENXIO;
2926#endif
2927 }
2928
2929 if (dev->rgmii_ph != 0) {
2930#ifdef CONFIG_IBM_EMAC_RGMII
2931 dev->features |= EMAC_FTR_HAS_RGMII;
2932#else
2933 printk(KERN_ERR "%pOF: RGMII support not enabled !\n", np);
2934 return -ENXIO;
2935#endif
2936 }
2937
2938 /* Read MAC-address */
2939 err = of_get_ethdev_address(np, dev->ndev);
2940 if (err == -EPROBE_DEFER)
2941 return err;
2942 if (err) {
2943 dev_warn(&dev->ofdev->dev, "Can't get valid mac-address. Generating random.");
2944 eth_hw_addr_random(dev->ndev);
2945 }
2946
2947 /* IAHT and GAHT filter parameterization */
2948 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) {
2949 dev->xaht_slots_shift = EMAC4SYNC_XAHT_SLOTS_SHIFT;
2950 dev->xaht_width_shift = EMAC4SYNC_XAHT_WIDTH_SHIFT;
2951 } else {
2952 dev->xaht_slots_shift = EMAC4_XAHT_SLOTS_SHIFT;
2953 dev->xaht_width_shift = EMAC4_XAHT_WIDTH_SHIFT;
2954 }
2955
2956 /* This should never happen */
2957 if (WARN_ON(EMAC_XAHT_REGS(dev) > EMAC_XAHT_MAX_REGS))
2958 return -ENXIO;
2959
2960 DBG(dev, "features : 0x%08x / 0x%08x\n", dev->features, EMAC_FTRS_POSSIBLE);
2961 DBG(dev, "tx_fifo_size : %d (%d gige)\n", dev->tx_fifo_size, dev->tx_fifo_size_gige);
2962 DBG(dev, "rx_fifo_size : %d (%d gige)\n", dev->rx_fifo_size, dev->rx_fifo_size_gige);
2963 DBG(dev, "max_mtu : %d\n", dev->max_mtu);
2964 DBG(dev, "OPB freq : %d\n", dev->opb_bus_freq);
2965
2966 return 0;
2967}
2968
2969static const struct net_device_ops emac_netdev_ops = {
2970 .ndo_open = emac_open,
2971 .ndo_stop = emac_close,
2972 .ndo_get_stats = emac_stats,
2973 .ndo_set_rx_mode = emac_set_multicast_list,
2974 .ndo_eth_ioctl = emac_ioctl,
2975 .ndo_tx_timeout = emac_tx_timeout,
2976 .ndo_validate_addr = eth_validate_addr,
2977 .ndo_set_mac_address = emac_set_mac_address,
2978 .ndo_start_xmit = emac_start_xmit,
2979};
2980
2981static const struct net_device_ops emac_gige_netdev_ops = {
2982 .ndo_open = emac_open,
2983 .ndo_stop = emac_close,
2984 .ndo_get_stats = emac_stats,
2985 .ndo_set_rx_mode = emac_set_multicast_list,
2986 .ndo_eth_ioctl = emac_ioctl,
2987 .ndo_tx_timeout = emac_tx_timeout,
2988 .ndo_validate_addr = eth_validate_addr,
2989 .ndo_set_mac_address = emac_set_mac_address,
2990 .ndo_start_xmit = emac_start_xmit_sg,
2991 .ndo_change_mtu = emac_change_mtu,
2992};
2993
2994static int emac_probe(struct platform_device *ofdev)
2995{
2996 struct net_device *ndev;
2997 struct emac_instance *dev;
2998 struct device_node *np = ofdev->dev.of_node;
2999 struct device_node **blist = NULL;
3000 int err, i;
3001
3002 /* Skip unused/unwired EMACS. We leave the check for an unused
3003 * property here for now, but new flat device trees should set a
3004 * status property to "disabled" instead.
3005 */
3006 if (of_property_read_bool(np, "unused") || !of_device_is_available(np))
3007 return -ENODEV;
3008
3009 /* Find ourselves in the bootlist if we are there */
3010 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
3011 if (emac_boot_list[i] == np)
3012 blist = &emac_boot_list[i];
3013
3014 /* Allocate our net_device structure */
3015 err = -ENOMEM;
3016 ndev = devm_alloc_etherdev(&ofdev->dev, sizeof(struct emac_instance));
3017 if (!ndev)
3018 goto err_gone;
3019
3020 dev = netdev_priv(ndev);
3021 dev->ndev = ndev;
3022 dev->ofdev = ofdev;
3023 dev->blist = blist;
3024 SET_NETDEV_DEV(ndev, &ofdev->dev);
3025
3026 /* Initialize some embedded data structures */
3027 err = devm_mutex_init(&ofdev->dev, &dev->mdio_lock);
3028 if (err)
3029 goto err_gone;
3030
3031 err = devm_mutex_init(&ofdev->dev, &dev->link_lock);
3032 if (err)
3033 goto err_gone;
3034
3035 spin_lock_init(&dev->lock);
3036 INIT_WORK(&dev->reset_work, emac_reset_work);
3037
3038 /* Init various config data based on device-tree */
3039 err = emac_init_config(dev);
3040 if (err)
3041 goto err_gone;
3042
3043 /* Setup error IRQ handler */
3044 dev->emac_irq = platform_get_irq(ofdev, 0);
3045 err = devm_request_irq(&ofdev->dev, dev->emac_irq, emac_irq, 0, "EMAC",
3046 dev);
3047 if (err) {
3048 dev_err_probe(&ofdev->dev, err, "failed to request IRQ %d",
3049 dev->emac_irq);
3050 goto err_gone;
3051 }
3052
3053 ndev->irq = dev->emac_irq;
3054
3055 dev->emacp = devm_platform_ioremap_resource(ofdev, 0);
3056 if (IS_ERR(dev->emacp)) {
3057 dev_err(&ofdev->dev, "can't map device registers");
3058 err = PTR_ERR(dev->emacp);
3059 goto err_gone;
3060 }
3061
3062 /* Wait for dependent devices */
3063 err = emac_wait_deps(dev);
3064 if (err)
3065 goto err_gone;
3066 dev->mal = platform_get_drvdata(dev->mal_dev);
3067 if (dev->mdio_dev != NULL)
3068 dev->mdio_instance = platform_get_drvdata(dev->mdio_dev);
3069
3070 /* Register with MAL */
3071 dev->commac.ops = &emac_commac_ops;
3072 dev->commac.dev = dev;
3073 dev->commac.tx_chan_mask = MAL_CHAN_MASK(dev->mal_tx_chan);
3074 dev->commac.rx_chan_mask = MAL_CHAN_MASK(dev->mal_rx_chan);
3075 err = mal_register_commac(dev->mal, &dev->commac);
3076 if (err) {
3077 printk(KERN_ERR "%pOF: failed to register with mal %pOF!\n",
3078 np, dev->mal_dev->dev.of_node);
3079 goto err_rel_deps;
3080 }
3081 dev->rx_skb_size = emac_rx_skb_size(ndev->mtu);
3082 dev->rx_sync_size = emac_rx_sync_size(ndev->mtu);
3083
3084 /* Get pointers to BD rings */
3085 dev->tx_desc =
3086 dev->mal->bd_virt + mal_tx_bd_offset(dev->mal, dev->mal_tx_chan);
3087 dev->rx_desc =
3088 dev->mal->bd_virt + mal_rx_bd_offset(dev->mal, dev->mal_rx_chan);
3089
3090 DBG(dev, "tx_desc %p" NL, dev->tx_desc);
3091 DBG(dev, "rx_desc %p" NL, dev->rx_desc);
3092
3093 /* Clean rings */
3094 memset(dev->tx_desc, 0, NUM_TX_BUFF * sizeof(struct mal_descriptor));
3095 memset(dev->rx_desc, 0, NUM_RX_BUFF * sizeof(struct mal_descriptor));
3096 memset(dev->tx_skb, 0, NUM_TX_BUFF * sizeof(struct sk_buff *));
3097 memset(dev->rx_skb, 0, NUM_RX_BUFF * sizeof(struct sk_buff *));
3098
3099 /* Attach to ZMII, if needed */
3100 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII) &&
3101 (err = zmii_attach(dev->zmii_dev, dev->zmii_port, &dev->phy_mode)) != 0)
3102 goto err_unreg_commac;
3103
3104 /* Attach to RGMII, if needed */
3105 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII) &&
3106 (err = rgmii_attach(dev->rgmii_dev, dev->rgmii_port, dev->phy_mode)) != 0)
3107 goto err_detach_zmii;
3108
3109 /* Attach to TAH, if needed */
3110 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
3111 (err = tah_attach(dev->tah_dev, dev->tah_port)) != 0)
3112 goto err_detach_rgmii;
3113
3114 /* Set some link defaults before we can find out real parameters */
3115 dev->phy.speed = SPEED_100;
3116 dev->phy.duplex = DUPLEX_FULL;
3117 dev->phy.autoneg = AUTONEG_DISABLE;
3118 dev->phy.pause = dev->phy.asym_pause = 0;
3119 dev->stop_timeout = STOP_TIMEOUT_100;
3120 INIT_DELAYED_WORK(&dev->link_work, emac_link_timer);
3121
3122 /* Some SoCs like APM821xx does not support Half Duplex mode. */
3123 if (emac_has_feature(dev, EMAC_FTR_APM821XX_NO_HALF_DUPLEX)) {
3124 dev->phy_feat_exc = (SUPPORTED_1000baseT_Half |
3125 SUPPORTED_100baseT_Half |
3126 SUPPORTED_10baseT_Half);
3127 }
3128
3129 /* Find PHY if any */
3130 err = emac_init_phy(dev);
3131 if (err != 0)
3132 goto err_detach_tah;
3133
3134 if (dev->tah_dev) {
3135 ndev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG;
3136 ndev->features |= ndev->hw_features | NETIF_F_RXCSUM;
3137 }
3138 ndev->watchdog_timeo = 5 * HZ;
3139 if (emac_phy_supports_gige(dev->phy_mode)) {
3140 ndev->netdev_ops = &emac_gige_netdev_ops;
3141 dev->commac.ops = &emac_commac_sg_ops;
3142 } else
3143 ndev->netdev_ops = &emac_netdev_ops;
3144 ndev->ethtool_ops = &emac_ethtool_ops;
3145
3146 /* MTU range: 46 - 1500 or whatever is in OF */
3147 ndev->min_mtu = EMAC_MIN_MTU;
3148 ndev->max_mtu = dev->max_mtu;
3149
3150 netif_carrier_off(ndev);
3151
3152 err = devm_register_netdev(&ofdev->dev, ndev);
3153 if (err) {
3154 printk(KERN_ERR "%pOF: failed to register net device (%d)!\n",
3155 np, err);
3156 goto err_detach_tah;
3157 }
3158
3159 /* Set our drvdata last as we don't want them visible until we are
3160 * fully initialized
3161 */
3162 wmb();
3163 platform_set_drvdata(ofdev, dev);
3164
3165 printk(KERN_INFO "%s: EMAC-%d %pOF, MAC %pM\n",
3166 ndev->name, dev->cell_index, np, ndev->dev_addr);
3167
3168 if (dev->phy_mode == PHY_INTERFACE_MODE_SGMII)
3169 printk(KERN_NOTICE "%s: in SGMII mode\n", ndev->name);
3170
3171 if (dev->phy.address >= 0)
3172 printk("%s: found %s PHY (0x%02x)\n", ndev->name,
3173 dev->phy.def->name, dev->phy.address);
3174
3175 /* Life is good */
3176 return 0;
3177
3178 /* I have a bad feeling about this ... */
3179
3180 err_detach_tah:
3181 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
3182 tah_detach(dev->tah_dev, dev->tah_port);
3183 err_detach_rgmii:
3184 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
3185 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
3186 err_detach_zmii:
3187 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
3188 zmii_detach(dev->zmii_dev, dev->zmii_port);
3189 err_unreg_commac:
3190 mal_unregister_commac(dev->mal, &dev->commac);
3191 err_rel_deps:
3192 emac_put_deps(dev);
3193 err_gone:
3194 if (blist)
3195 *blist = NULL;
3196 return err;
3197}
3198
3199static void emac_remove(struct platform_device *ofdev)
3200{
3201 struct emac_instance *dev = platform_get_drvdata(ofdev);
3202
3203 DBG(dev, "remove" NL);
3204
3205 cancel_work_sync(&dev->reset_work);
3206
3207 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
3208 tah_detach(dev->tah_dev, dev->tah_port);
3209 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
3210 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
3211 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
3212 zmii_detach(dev->zmii_dev, dev->zmii_port);
3213
3214 busy_phy_map &= ~(1 << dev->phy.address);
3215 DBG(dev, "busy_phy_map now %#x" NL, busy_phy_map);
3216
3217 mal_unregister_commac(dev->mal, &dev->commac);
3218 emac_put_deps(dev);
3219}
3220
3221/* XXX Features in here should be replaced by properties... */
3222static const struct of_device_id emac_match[] =
3223{
3224 {
3225 .type = "network",
3226 .compatible = "ibm,emac",
3227 },
3228 {
3229 .type = "network",
3230 .compatible = "ibm,emac4",
3231 },
3232 {
3233 .type = "network",
3234 .compatible = "ibm,emac4sync",
3235 },
3236 {},
3237};
3238MODULE_DEVICE_TABLE(of, emac_match);
3239
3240static struct platform_driver emac_driver = {
3241 .driver = {
3242 .name = "emac",
3243 .of_match_table = emac_match,
3244 },
3245 .probe = emac_probe,
3246 .remove = emac_remove,
3247};
3248
3249static void __init emac_make_bootlist(void)
3250{
3251 struct device_node *np = NULL;
3252 int j, max, i = 0;
3253 int cell_indices[EMAC_BOOT_LIST_SIZE];
3254
3255 /* Collect EMACs */
3256 while((np = of_find_all_nodes(np)) != NULL) {
3257 u32 idx;
3258
3259 if (of_match_node(emac_match, np) == NULL)
3260 continue;
3261 if (of_property_read_bool(np, "unused"))
3262 continue;
3263 if (of_property_read_u32(np, "cell-index", &idx))
3264 continue;
3265 cell_indices[i] = idx;
3266 emac_boot_list[i++] = of_node_get(np);
3267 if (i >= EMAC_BOOT_LIST_SIZE) {
3268 of_node_put(np);
3269 break;
3270 }
3271 }
3272 max = i;
3273
3274 /* Bubble sort them (doh, what a creative algorithm :-) */
3275 for (i = 0; max > 1 && (i < (max - 1)); i++)
3276 for (j = i; j < max; j++) {
3277 if (cell_indices[i] > cell_indices[j]) {
3278 swap(emac_boot_list[i], emac_boot_list[j]);
3279 swap(cell_indices[i], cell_indices[j]);
3280 }
3281 }
3282}
3283
3284static int __init emac_init(void)
3285{
3286 int rc;
3287
3288 printk(KERN_INFO DRV_DESC ", version " DRV_VERSION "\n");
3289
3290 /* Build EMAC boot list */
3291 emac_make_bootlist();
3292
3293 /* Init submodules */
3294 rc = mal_init();
3295 if (rc)
3296 goto err;
3297 rc = zmii_init();
3298 if (rc)
3299 goto err_mal;
3300 rc = rgmii_init();
3301 if (rc)
3302 goto err_zmii;
3303 rc = tah_init();
3304 if (rc)
3305 goto err_rgmii;
3306 rc = platform_driver_register(&emac_driver);
3307 if (rc)
3308 goto err_tah;
3309
3310 return 0;
3311
3312 err_tah:
3313 tah_exit();
3314 err_rgmii:
3315 rgmii_exit();
3316 err_zmii:
3317 zmii_exit();
3318 err_mal:
3319 mal_exit();
3320 err:
3321 return rc;
3322}
3323
3324static void __exit emac_exit(void)
3325{
3326 int i;
3327
3328 platform_driver_unregister(&emac_driver);
3329
3330 tah_exit();
3331 rgmii_exit();
3332 zmii_exit();
3333 mal_exit();
3334
3335 /* Destroy EMAC boot list */
3336 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
3337 of_node_put(emac_boot_list[i]);
3338}
3339
3340module_init(emac_init);
3341module_exit(emac_exit);
1/*
2 * drivers/net/ethernet/ibm/emac/core.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller.
5 *
6 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
7 * <benh@kernel.crashing.org>
8 *
9 * Based on the arch/ppc version of the driver:
10 *
11 * Copyright (c) 2004, 2005 Zultys Technologies.
12 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
13 *
14 * Based on original work by
15 * Matt Porter <mporter@kernel.crashing.org>
16 * (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
17 * Armin Kuster <akuster@mvista.com>
18 * Johnnie Peters <jpeters@mvista.com>
19 *
20 * This program is free software; you can redistribute it and/or modify it
21 * under the terms of the GNU General Public License as published by the
22 * Free Software Foundation; either version 2 of the License, or (at your
23 * option) any later version.
24 *
25 */
26
27#include <linux/module.h>
28#include <linux/sched.h>
29#include <linux/string.h>
30#include <linux/errno.h>
31#include <linux/delay.h>
32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/etherdevice.h>
35#include <linux/skbuff.h>
36#include <linux/crc32.h>
37#include <linux/ethtool.h>
38#include <linux/mii.h>
39#include <linux/bitops.h>
40#include <linux/workqueue.h>
41#include <linux/of.h>
42#include <linux/of_address.h>
43#include <linux/of_irq.h>
44#include <linux/of_net.h>
45#include <linux/of_mdio.h>
46#include <linux/slab.h>
47
48#include <asm/processor.h>
49#include <asm/io.h>
50#include <asm/dma.h>
51#include <linux/uaccess.h>
52#include <asm/dcr.h>
53#include <asm/dcr-regs.h>
54
55#include "core.h"
56
57/*
58 * Lack of dma_unmap_???? calls is intentional.
59 *
60 * API-correct usage requires additional support state information to be
61 * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to
62 * EMAC design (e.g. TX buffer passed from network stack can be split into
63 * several BDs, dma_map_single/dma_map_page can be used to map particular BD),
64 * maintaining such information will add additional overhead.
65 * Current DMA API implementation for 4xx processors only ensures cache coherency
66 * and dma_unmap_???? routines are empty and are likely to stay this way.
67 * I decided to omit dma_unmap_??? calls because I don't want to add additional
68 * complexity just for the sake of following some abstract API, when it doesn't
69 * add any real benefit to the driver. I understand that this decision maybe
70 * controversial, but I really tried to make code API-correct and efficient
71 * at the same time and didn't come up with code I liked :(. --ebs
72 */
73
74#define DRV_NAME "emac"
75#define DRV_VERSION "3.54"
76#define DRV_DESC "PPC 4xx OCP EMAC driver"
77
78MODULE_DESCRIPTION(DRV_DESC);
79MODULE_AUTHOR
80 ("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>");
81MODULE_LICENSE("GPL");
82
83/* minimum number of free TX descriptors required to wake up TX process */
84#define EMAC_TX_WAKEUP_THRESH (NUM_TX_BUFF / 4)
85
86/* If packet size is less than this number, we allocate small skb and copy packet
87 * contents into it instead of just sending original big skb up
88 */
89#define EMAC_RX_COPY_THRESH CONFIG_IBM_EMAC_RX_COPY_THRESHOLD
90
91/* Since multiple EMACs share MDIO lines in various ways, we need
92 * to avoid re-using the same PHY ID in cases where the arch didn't
93 * setup precise phy_map entries
94 *
95 * XXX This is something that needs to be reworked as we can have multiple
96 * EMAC "sets" (multiple ASICs containing several EMACs) though we can
97 * probably require in that case to have explicit PHY IDs in the device-tree
98 */
99static u32 busy_phy_map;
100static DEFINE_MUTEX(emac_phy_map_lock);
101
102/* This is the wait queue used to wait on any event related to probe, that
103 * is discovery of MALs, other EMACs, ZMII/RGMIIs, etc...
104 */
105static DECLARE_WAIT_QUEUE_HEAD(emac_probe_wait);
106
107/* Having stable interface names is a doomed idea. However, it would be nice
108 * if we didn't have completely random interface names at boot too :-) It's
109 * just a matter of making everybody's life easier. Since we are doing
110 * threaded probing, it's a bit harder though. The base idea here is that
111 * we make up a list of all emacs in the device-tree before we register the
112 * driver. Every emac will then wait for the previous one in the list to
113 * initialize before itself. We should also keep that list ordered by
114 * cell_index.
115 * That list is only 4 entries long, meaning that additional EMACs don't
116 * get ordering guarantees unless EMAC_BOOT_LIST_SIZE is increased.
117 */
118
119#define EMAC_BOOT_LIST_SIZE 4
120static struct device_node *emac_boot_list[EMAC_BOOT_LIST_SIZE];
121
122/* How long should I wait for dependent devices ? */
123#define EMAC_PROBE_DEP_TIMEOUT (HZ * 5)
124
125/* I don't want to litter system log with timeout errors
126 * when we have brain-damaged PHY.
127 */
128static inline void emac_report_timeout_error(struct emac_instance *dev,
129 const char *error)
130{
131 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX |
132 EMAC_FTR_460EX_PHY_CLK_FIX |
133 EMAC_FTR_440EP_PHY_CLK_FIX))
134 DBG(dev, "%s" NL, error);
135 else if (net_ratelimit())
136 printk(KERN_ERR "%pOF: %s\n", dev->ofdev->dev.of_node, error);
137}
138
139/* EMAC PHY clock workaround:
140 * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX,
141 * which allows controlling each EMAC clock
142 */
143static inline void emac_rx_clk_tx(struct emac_instance *dev)
144{
145#ifdef CONFIG_PPC_DCR_NATIVE
146 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
147 dcri_clrset(SDR0, SDR0_MFR,
148 0, SDR0_MFR_ECS >> dev->cell_index);
149#endif
150}
151
152static inline void emac_rx_clk_default(struct emac_instance *dev)
153{
154#ifdef CONFIG_PPC_DCR_NATIVE
155 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
156 dcri_clrset(SDR0, SDR0_MFR,
157 SDR0_MFR_ECS >> dev->cell_index, 0);
158#endif
159}
160
161/* PHY polling intervals */
162#define PHY_POLL_LINK_ON HZ
163#define PHY_POLL_LINK_OFF (HZ / 5)
164
165/* Graceful stop timeouts in us.
166 * We should allow up to 1 frame time (full-duplex, ignoring collisions)
167 */
168#define STOP_TIMEOUT_10 1230
169#define STOP_TIMEOUT_100 124
170#define STOP_TIMEOUT_1000 13
171#define STOP_TIMEOUT_1000_JUMBO 73
172
173static unsigned char default_mcast_addr[] = {
174 0x01, 0x80, 0xC2, 0x00, 0x00, 0x01
175};
176
177/* Please, keep in sync with struct ibm_emac_stats/ibm_emac_error_stats */
178static const char emac_stats_keys[EMAC_ETHTOOL_STATS_COUNT][ETH_GSTRING_LEN] = {
179 "rx_packets", "rx_bytes", "tx_packets", "tx_bytes", "rx_packets_csum",
180 "tx_packets_csum", "tx_undo", "rx_dropped_stack", "rx_dropped_oom",
181 "rx_dropped_error", "rx_dropped_resize", "rx_dropped_mtu",
182 "rx_stopped", "rx_bd_errors", "rx_bd_overrun", "rx_bd_bad_packet",
183 "rx_bd_runt_packet", "rx_bd_short_event", "rx_bd_alignment_error",
184 "rx_bd_bad_fcs", "rx_bd_packet_too_long", "rx_bd_out_of_range",
185 "rx_bd_in_range", "rx_parity", "rx_fifo_overrun", "rx_overrun",
186 "rx_bad_packet", "rx_runt_packet", "rx_short_event",
187 "rx_alignment_error", "rx_bad_fcs", "rx_packet_too_long",
188 "rx_out_of_range", "rx_in_range", "tx_dropped", "tx_bd_errors",
189 "tx_bd_bad_fcs", "tx_bd_carrier_loss", "tx_bd_excessive_deferral",
190 "tx_bd_excessive_collisions", "tx_bd_late_collision",
191 "tx_bd_multple_collisions", "tx_bd_single_collision",
192 "tx_bd_underrun", "tx_bd_sqe", "tx_parity", "tx_underrun", "tx_sqe",
193 "tx_errors"
194};
195
196static irqreturn_t emac_irq(int irq, void *dev_instance);
197static void emac_clean_tx_ring(struct emac_instance *dev);
198static void __emac_set_multicast_list(struct emac_instance *dev);
199
200static inline int emac_phy_supports_gige(int phy_mode)
201{
202 return phy_interface_mode_is_rgmii(phy_mode) ||
203 phy_mode == PHY_INTERFACE_MODE_GMII ||
204 phy_mode == PHY_INTERFACE_MODE_SGMII ||
205 phy_mode == PHY_INTERFACE_MODE_TBI ||
206 phy_mode == PHY_INTERFACE_MODE_RTBI;
207}
208
209static inline int emac_phy_gpcs(int phy_mode)
210{
211 return phy_mode == PHY_INTERFACE_MODE_SGMII ||
212 phy_mode == PHY_INTERFACE_MODE_TBI ||
213 phy_mode == PHY_INTERFACE_MODE_RTBI;
214}
215
216static inline void emac_tx_enable(struct emac_instance *dev)
217{
218 struct emac_regs __iomem *p = dev->emacp;
219 u32 r;
220
221 DBG(dev, "tx_enable" NL);
222
223 r = in_be32(&p->mr0);
224 if (!(r & EMAC_MR0_TXE))
225 out_be32(&p->mr0, r | EMAC_MR0_TXE);
226}
227
228static void emac_tx_disable(struct emac_instance *dev)
229{
230 struct emac_regs __iomem *p = dev->emacp;
231 u32 r;
232
233 DBG(dev, "tx_disable" NL);
234
235 r = in_be32(&p->mr0);
236 if (r & EMAC_MR0_TXE) {
237 int n = dev->stop_timeout;
238 out_be32(&p->mr0, r & ~EMAC_MR0_TXE);
239 while (!(in_be32(&p->mr0) & EMAC_MR0_TXI) && n) {
240 udelay(1);
241 --n;
242 }
243 if (unlikely(!n))
244 emac_report_timeout_error(dev, "TX disable timeout");
245 }
246}
247
248static void emac_rx_enable(struct emac_instance *dev)
249{
250 struct emac_regs __iomem *p = dev->emacp;
251 u32 r;
252
253 if (unlikely(test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags)))
254 goto out;
255
256 DBG(dev, "rx_enable" NL);
257
258 r = in_be32(&p->mr0);
259 if (!(r & EMAC_MR0_RXE)) {
260 if (unlikely(!(r & EMAC_MR0_RXI))) {
261 /* Wait if previous async disable is still in progress */
262 int n = dev->stop_timeout;
263 while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
264 udelay(1);
265 --n;
266 }
267 if (unlikely(!n))
268 emac_report_timeout_error(dev,
269 "RX disable timeout");
270 }
271 out_be32(&p->mr0, r | EMAC_MR0_RXE);
272 }
273 out:
274 ;
275}
276
277static void emac_rx_disable(struct emac_instance *dev)
278{
279 struct emac_regs __iomem *p = dev->emacp;
280 u32 r;
281
282 DBG(dev, "rx_disable" NL);
283
284 r = in_be32(&p->mr0);
285 if (r & EMAC_MR0_RXE) {
286 int n = dev->stop_timeout;
287 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
288 while (!(in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
289 udelay(1);
290 --n;
291 }
292 if (unlikely(!n))
293 emac_report_timeout_error(dev, "RX disable timeout");
294 }
295}
296
297static inline void emac_netif_stop(struct emac_instance *dev)
298{
299 netif_tx_lock_bh(dev->ndev);
300 netif_addr_lock(dev->ndev);
301 dev->no_mcast = 1;
302 netif_addr_unlock(dev->ndev);
303 netif_tx_unlock_bh(dev->ndev);
304 netif_trans_update(dev->ndev); /* prevent tx timeout */
305 mal_poll_disable(dev->mal, &dev->commac);
306 netif_tx_disable(dev->ndev);
307}
308
309static inline void emac_netif_start(struct emac_instance *dev)
310{
311 netif_tx_lock_bh(dev->ndev);
312 netif_addr_lock(dev->ndev);
313 dev->no_mcast = 0;
314 if (dev->mcast_pending && netif_running(dev->ndev))
315 __emac_set_multicast_list(dev);
316 netif_addr_unlock(dev->ndev);
317 netif_tx_unlock_bh(dev->ndev);
318
319 netif_wake_queue(dev->ndev);
320
321 /* NOTE: unconditional netif_wake_queue is only appropriate
322 * so long as all callers are assured to have free tx slots
323 * (taken from tg3... though the case where that is wrong is
324 * not terribly harmful)
325 */
326 mal_poll_enable(dev->mal, &dev->commac);
327}
328
329static inline void emac_rx_disable_async(struct emac_instance *dev)
330{
331 struct emac_regs __iomem *p = dev->emacp;
332 u32 r;
333
334 DBG(dev, "rx_disable_async" NL);
335
336 r = in_be32(&p->mr0);
337 if (r & EMAC_MR0_RXE)
338 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
339}
340
341static int emac_reset(struct emac_instance *dev)
342{
343 struct emac_regs __iomem *p = dev->emacp;
344 int n = 20;
345 bool __maybe_unused try_internal_clock = false;
346
347 DBG(dev, "reset" NL);
348
349 if (!dev->reset_failed) {
350 /* 40x erratum suggests stopping RX channel before reset,
351 * we stop TX as well
352 */
353 emac_rx_disable(dev);
354 emac_tx_disable(dev);
355 }
356
357#ifdef CONFIG_PPC_DCR_NATIVE
358do_retry:
359 /*
360 * PPC460EX/GT Embedded Processor Advanced User's Manual
361 * section 28.10.1 Mode Register 0 (EMACx_MR0) states:
362 * Note: The PHY must provide a TX Clk in order to perform a soft reset
363 * of the EMAC. If none is present, select the internal clock
364 * (SDR0_ETH_CFG[EMACx_PHY_CLK] = 1).
365 * After a soft reset, select the external clock.
366 *
367 * The AR8035-A PHY Meraki MR24 does not provide a TX Clk if the
368 * ethernet cable is not attached. This causes the reset to timeout
369 * and the PHY detection code in emac_init_phy() is unable to
370 * communicate and detect the AR8035-A PHY. As a result, the emac
371 * driver bails out early and the user has no ethernet.
372 * In order to stay compatible with existing configurations, the
373 * driver will temporarily switch to the internal clock, after
374 * the first reset fails.
375 */
376 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
377 if (try_internal_clock || (dev->phy_address == 0xffffffff &&
378 dev->phy_map == 0xffffffff)) {
379 /* No PHY: select internal loop clock before reset */
380 dcri_clrset(SDR0, SDR0_ETH_CFG,
381 0, SDR0_ETH_CFG_ECS << dev->cell_index);
382 } else {
383 /* PHY present: select external clock before reset */
384 dcri_clrset(SDR0, SDR0_ETH_CFG,
385 SDR0_ETH_CFG_ECS << dev->cell_index, 0);
386 }
387 }
388#endif
389
390 out_be32(&p->mr0, EMAC_MR0_SRST);
391 while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n)
392 --n;
393
394#ifdef CONFIG_PPC_DCR_NATIVE
395 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
396 if (!n && !try_internal_clock) {
397 /* first attempt has timed out. */
398 n = 20;
399 try_internal_clock = true;
400 goto do_retry;
401 }
402
403 if (try_internal_clock || (dev->phy_address == 0xffffffff &&
404 dev->phy_map == 0xffffffff)) {
405 /* No PHY: restore external clock source after reset */
406 dcri_clrset(SDR0, SDR0_ETH_CFG,
407 SDR0_ETH_CFG_ECS << dev->cell_index, 0);
408 }
409 }
410#endif
411
412 if (n) {
413 dev->reset_failed = 0;
414 return 0;
415 } else {
416 emac_report_timeout_error(dev, "reset timeout");
417 dev->reset_failed = 1;
418 return -ETIMEDOUT;
419 }
420}
421
422static void emac_hash_mc(struct emac_instance *dev)
423{
424 const int regs = EMAC_XAHT_REGS(dev);
425 u32 *gaht_base = emac_gaht_base(dev);
426 u32 gaht_temp[regs];
427 struct netdev_hw_addr *ha;
428 int i;
429
430 DBG(dev, "hash_mc %d" NL, netdev_mc_count(dev->ndev));
431
432 memset(gaht_temp, 0, sizeof (gaht_temp));
433
434 netdev_for_each_mc_addr(ha, dev->ndev) {
435 int slot, reg, mask;
436 DBG2(dev, "mc %pM" NL, ha->addr);
437
438 slot = EMAC_XAHT_CRC_TO_SLOT(dev,
439 ether_crc(ETH_ALEN, ha->addr));
440 reg = EMAC_XAHT_SLOT_TO_REG(dev, slot);
441 mask = EMAC_XAHT_SLOT_TO_MASK(dev, slot);
442
443 gaht_temp[reg] |= mask;
444 }
445
446 for (i = 0; i < regs; i++)
447 out_be32(gaht_base + i, gaht_temp[i]);
448}
449
450static inline u32 emac_iff2rmr(struct net_device *ndev)
451{
452 struct emac_instance *dev = netdev_priv(ndev);
453 u32 r;
454
455 r = EMAC_RMR_SP | EMAC_RMR_SFCS | EMAC_RMR_IAE | EMAC_RMR_BAE;
456
457 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
458 r |= EMAC4_RMR_BASE;
459 else
460 r |= EMAC_RMR_BASE;
461
462 if (ndev->flags & IFF_PROMISC)
463 r |= EMAC_RMR_PME;
464 else if (ndev->flags & IFF_ALLMULTI ||
465 (netdev_mc_count(ndev) > EMAC_XAHT_SLOTS(dev)))
466 r |= EMAC_RMR_PMME;
467 else if (!netdev_mc_empty(ndev))
468 r |= EMAC_RMR_MAE;
469
470 if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) {
471 r &= ~EMAC4_RMR_MJS_MASK;
472 r |= EMAC4_RMR_MJS(ndev->mtu);
473 }
474
475 return r;
476}
477
478static u32 __emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
479{
480 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC_MR1_TR0_MULT;
481
482 DBG2(dev, "__emac_calc_base_mr1" NL);
483
484 switch(tx_size) {
485 case 2048:
486 ret |= EMAC_MR1_TFS_2K;
487 break;
488 default:
489 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n",
490 dev->ndev->name, tx_size);
491 }
492
493 switch(rx_size) {
494 case 16384:
495 ret |= EMAC_MR1_RFS_16K;
496 break;
497 case 8192:
498 ret |= EMAC4_MR1_RFS_8K;
499 break;
500 case 4096:
501 ret |= EMAC_MR1_RFS_4K;
502 break;
503 default:
504 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
505 dev->ndev->name, rx_size);
506 }
507
508 return ret;
509}
510
511static u32 __emac4_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
512{
513 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC4_MR1_TR |
514 EMAC4_MR1_OBCI(dev->opb_bus_freq / 1000000);
515
516 DBG2(dev, "__emac4_calc_base_mr1" NL);
517
518 switch(tx_size) {
519 case 16384:
520 ret |= EMAC4_MR1_TFS_16K;
521 break;
522 case 8192:
523 ret |= EMAC4_MR1_TFS_8K;
524 break;
525 case 4096:
526 ret |= EMAC4_MR1_TFS_4K;
527 break;
528 case 2048:
529 ret |= EMAC4_MR1_TFS_2K;
530 break;
531 default:
532 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n",
533 dev->ndev->name, tx_size);
534 }
535
536 switch(rx_size) {
537 case 16384:
538 ret |= EMAC4_MR1_RFS_16K;
539 break;
540 case 4096:
541 ret |= EMAC4_MR1_RFS_4K;
542 break;
543 case 2048:
544 ret |= EMAC4_MR1_RFS_2K;
545 break;
546 default:
547 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
548 dev->ndev->name, rx_size);
549 }
550
551 return ret;
552}
553
554static u32 emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
555{
556 return emac_has_feature(dev, EMAC_FTR_EMAC4) ?
557 __emac4_calc_base_mr1(dev, tx_size, rx_size) :
558 __emac_calc_base_mr1(dev, tx_size, rx_size);
559}
560
561static inline u32 emac_calc_trtr(struct emac_instance *dev, unsigned int size)
562{
563 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
564 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT_EMAC4;
565 else
566 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT;
567}
568
569static inline u32 emac_calc_rwmr(struct emac_instance *dev,
570 unsigned int low, unsigned int high)
571{
572 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
573 return (low << 22) | ( (high & 0x3ff) << 6);
574 else
575 return (low << 23) | ( (high & 0x1ff) << 7);
576}
577
578static int emac_configure(struct emac_instance *dev)
579{
580 struct emac_regs __iomem *p = dev->emacp;
581 struct net_device *ndev = dev->ndev;
582 int tx_size, rx_size, link = netif_carrier_ok(dev->ndev);
583 u32 r, mr1 = 0;
584
585 DBG(dev, "configure" NL);
586
587 if (!link) {
588 out_be32(&p->mr1, in_be32(&p->mr1)
589 | EMAC_MR1_FDE | EMAC_MR1_ILE);
590 udelay(100);
591 } else if (emac_reset(dev) < 0)
592 return -ETIMEDOUT;
593
594 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
595 tah_reset(dev->tah_dev);
596
597 DBG(dev, " link = %d duplex = %d, pause = %d, asym_pause = %d\n",
598 link, dev->phy.duplex, dev->phy.pause, dev->phy.asym_pause);
599
600 /* Default fifo sizes */
601 tx_size = dev->tx_fifo_size;
602 rx_size = dev->rx_fifo_size;
603
604 /* No link, force loopback */
605 if (!link)
606 mr1 = EMAC_MR1_FDE | EMAC_MR1_ILE;
607
608 /* Check for full duplex */
609 else if (dev->phy.duplex == DUPLEX_FULL)
610 mr1 |= EMAC_MR1_FDE | EMAC_MR1_MWSW_001;
611
612 /* Adjust fifo sizes, mr1 and timeouts based on link speed */
613 dev->stop_timeout = STOP_TIMEOUT_10;
614 switch (dev->phy.speed) {
615 case SPEED_1000:
616 if (emac_phy_gpcs(dev->phy.mode)) {
617 mr1 |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_MF_IPPA(
618 (dev->phy.gpcs_address != 0xffffffff) ?
619 dev->phy.gpcs_address : dev->phy.address);
620
621 /* Put some arbitrary OUI, Manuf & Rev IDs so we can
622 * identify this GPCS PHY later.
623 */
624 out_be32(&p->u1.emac4.ipcr, 0xdeadbeef);
625 } else
626 mr1 |= EMAC_MR1_MF_1000;
627
628 /* Extended fifo sizes */
629 tx_size = dev->tx_fifo_size_gige;
630 rx_size = dev->rx_fifo_size_gige;
631
632 if (dev->ndev->mtu > ETH_DATA_LEN) {
633 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
634 mr1 |= EMAC4_MR1_JPSM;
635 else
636 mr1 |= EMAC_MR1_JPSM;
637 dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO;
638 } else
639 dev->stop_timeout = STOP_TIMEOUT_1000;
640 break;
641 case SPEED_100:
642 mr1 |= EMAC_MR1_MF_100;
643 dev->stop_timeout = STOP_TIMEOUT_100;
644 break;
645 default: /* make gcc happy */
646 break;
647 }
648
649 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
650 rgmii_set_speed(dev->rgmii_dev, dev->rgmii_port,
651 dev->phy.speed);
652 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
653 zmii_set_speed(dev->zmii_dev, dev->zmii_port, dev->phy.speed);
654
655 /* on 40x erratum forces us to NOT use integrated flow control,
656 * let's hope it works on 44x ;)
657 */
658 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x) &&
659 dev->phy.duplex == DUPLEX_FULL) {
660 if (dev->phy.pause)
661 mr1 |= EMAC_MR1_EIFC | EMAC_MR1_APP;
662 else if (dev->phy.asym_pause)
663 mr1 |= EMAC_MR1_APP;
664 }
665
666 /* Add base settings & fifo sizes & program MR1 */
667 mr1 |= emac_calc_base_mr1(dev, tx_size, rx_size);
668 out_be32(&p->mr1, mr1);
669
670 /* Set individual MAC address */
671 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
672 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
673 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
674 ndev->dev_addr[5]);
675
676 /* VLAN Tag Protocol ID */
677 out_be32(&p->vtpid, 0x8100);
678
679 /* Receive mode register */
680 r = emac_iff2rmr(ndev);
681 if (r & EMAC_RMR_MAE)
682 emac_hash_mc(dev);
683 out_be32(&p->rmr, r);
684
685 /* FIFOs thresholds */
686 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
687 r = EMAC4_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
688 tx_size / 2 / dev->fifo_entry_size);
689 else
690 r = EMAC_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
691 tx_size / 2 / dev->fifo_entry_size);
692 out_be32(&p->tmr1, r);
693 out_be32(&p->trtr, emac_calc_trtr(dev, tx_size / 2));
694
695 /* PAUSE frame is sent when RX FIFO reaches its high-water mark,
696 there should be still enough space in FIFO to allow the our link
697 partner time to process this frame and also time to send PAUSE
698 frame itself.
699
700 Here is the worst case scenario for the RX FIFO "headroom"
701 (from "The Switch Book") (100Mbps, without preamble, inter-frame gap):
702
703 1) One maximum-length frame on TX 1522 bytes
704 2) One PAUSE frame time 64 bytes
705 3) PAUSE frame decode time allowance 64 bytes
706 4) One maximum-length frame on RX 1522 bytes
707 5) Round-trip propagation delay of the link (100Mb) 15 bytes
708 ----------
709 3187 bytes
710
711 I chose to set high-water mark to RX_FIFO_SIZE / 4 (1024 bytes)
712 low-water mark to RX_FIFO_SIZE / 8 (512 bytes)
713 */
714 r = emac_calc_rwmr(dev, rx_size / 8 / dev->fifo_entry_size,
715 rx_size / 4 / dev->fifo_entry_size);
716 out_be32(&p->rwmr, r);
717
718 /* Set PAUSE timer to the maximum */
719 out_be32(&p->ptr, 0xffff);
720
721 /* IRQ sources */
722 r = EMAC_ISR_OVR | EMAC_ISR_BP | EMAC_ISR_SE |
723 EMAC_ISR_ALE | EMAC_ISR_BFCS | EMAC_ISR_PTLE | EMAC_ISR_ORE |
724 EMAC_ISR_IRE | EMAC_ISR_TE;
725 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
726 r |= EMAC4_ISR_TXPE | EMAC4_ISR_RXPE /* | EMAC4_ISR_TXUE |
727 EMAC4_ISR_RXOE | */;
728 out_be32(&p->iser, r);
729
730 /* We need to take GPCS PHY out of isolate mode after EMAC reset */
731 if (emac_phy_gpcs(dev->phy.mode)) {
732 if (dev->phy.gpcs_address != 0xffffffff)
733 emac_mii_reset_gpcs(&dev->phy);
734 else
735 emac_mii_reset_phy(&dev->phy);
736 }
737
738 return 0;
739}
740
741static void emac_reinitialize(struct emac_instance *dev)
742{
743 DBG(dev, "reinitialize" NL);
744
745 emac_netif_stop(dev);
746 if (!emac_configure(dev)) {
747 emac_tx_enable(dev);
748 emac_rx_enable(dev);
749 }
750 emac_netif_start(dev);
751}
752
753static void emac_full_tx_reset(struct emac_instance *dev)
754{
755 DBG(dev, "full_tx_reset" NL);
756
757 emac_tx_disable(dev);
758 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
759 emac_clean_tx_ring(dev);
760 dev->tx_cnt = dev->tx_slot = dev->ack_slot = 0;
761
762 emac_configure(dev);
763
764 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
765 emac_tx_enable(dev);
766 emac_rx_enable(dev);
767}
768
769static void emac_reset_work(struct work_struct *work)
770{
771 struct emac_instance *dev = container_of(work, struct emac_instance, reset_work);
772
773 DBG(dev, "reset_work" NL);
774
775 mutex_lock(&dev->link_lock);
776 if (dev->opened) {
777 emac_netif_stop(dev);
778 emac_full_tx_reset(dev);
779 emac_netif_start(dev);
780 }
781 mutex_unlock(&dev->link_lock);
782}
783
784static void emac_tx_timeout(struct net_device *ndev)
785{
786 struct emac_instance *dev = netdev_priv(ndev);
787
788 DBG(dev, "tx_timeout" NL);
789
790 schedule_work(&dev->reset_work);
791}
792
793
794static inline int emac_phy_done(struct emac_instance *dev, u32 stacr)
795{
796 int done = !!(stacr & EMAC_STACR_OC);
797
798 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
799 done = !done;
800
801 return done;
802};
803
804static int __emac_mdio_read(struct emac_instance *dev, u8 id, u8 reg)
805{
806 struct emac_regs __iomem *p = dev->emacp;
807 u32 r = 0;
808 int n, err = -ETIMEDOUT;
809
810 mutex_lock(&dev->mdio_lock);
811
812 DBG2(dev, "mdio_read(%02x,%02x)" NL, id, reg);
813
814 /* Enable proper MDIO port */
815 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
816 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
817 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
818 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
819
820 /* Wait for management interface to become idle */
821 n = 20;
822 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
823 udelay(1);
824 if (!--n) {
825 DBG2(dev, " -> timeout wait idle\n");
826 goto bail;
827 }
828 }
829
830 /* Issue read command */
831 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
832 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
833 else
834 r = EMAC_STACR_BASE(dev->opb_bus_freq);
835 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
836 r |= EMAC_STACR_OC;
837 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
838 r |= EMACX_STACR_STAC_READ;
839 else
840 r |= EMAC_STACR_STAC_READ;
841 r |= (reg & EMAC_STACR_PRA_MASK)
842 | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT);
843 out_be32(&p->stacr, r);
844
845 /* Wait for read to complete */
846 n = 200;
847 while (!emac_phy_done(dev, (r = in_be32(&p->stacr)))) {
848 udelay(1);
849 if (!--n) {
850 DBG2(dev, " -> timeout wait complete\n");
851 goto bail;
852 }
853 }
854
855 if (unlikely(r & EMAC_STACR_PHYE)) {
856 DBG(dev, "mdio_read(%02x, %02x) failed" NL, id, reg);
857 err = -EREMOTEIO;
858 goto bail;
859 }
860
861 r = ((r >> EMAC_STACR_PHYD_SHIFT) & EMAC_STACR_PHYD_MASK);
862
863 DBG2(dev, "mdio_read -> %04x" NL, r);
864 err = 0;
865 bail:
866 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
867 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
868 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
869 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
870 mutex_unlock(&dev->mdio_lock);
871
872 return err == 0 ? r : err;
873}
874
875static void __emac_mdio_write(struct emac_instance *dev, u8 id, u8 reg,
876 u16 val)
877{
878 struct emac_regs __iomem *p = dev->emacp;
879 u32 r = 0;
880 int n, err = -ETIMEDOUT;
881
882 mutex_lock(&dev->mdio_lock);
883
884 DBG2(dev, "mdio_write(%02x,%02x,%04x)" NL, id, reg, val);
885
886 /* Enable proper MDIO port */
887 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
888 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
889 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
890 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
891
892 /* Wait for management interface to be idle */
893 n = 20;
894 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
895 udelay(1);
896 if (!--n) {
897 DBG2(dev, " -> timeout wait idle\n");
898 goto bail;
899 }
900 }
901
902 /* Issue write command */
903 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
904 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
905 else
906 r = EMAC_STACR_BASE(dev->opb_bus_freq);
907 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
908 r |= EMAC_STACR_OC;
909 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
910 r |= EMACX_STACR_STAC_WRITE;
911 else
912 r |= EMAC_STACR_STAC_WRITE;
913 r |= (reg & EMAC_STACR_PRA_MASK) |
914 ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) |
915 (val << EMAC_STACR_PHYD_SHIFT);
916 out_be32(&p->stacr, r);
917
918 /* Wait for write to complete */
919 n = 200;
920 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
921 udelay(1);
922 if (!--n) {
923 DBG2(dev, " -> timeout wait complete\n");
924 goto bail;
925 }
926 }
927 err = 0;
928 bail:
929 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
930 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
931 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
932 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
933 mutex_unlock(&dev->mdio_lock);
934}
935
936static int emac_mdio_read(struct net_device *ndev, int id, int reg)
937{
938 struct emac_instance *dev = netdev_priv(ndev);
939 int res;
940
941 res = __emac_mdio_read((dev->mdio_instance &&
942 dev->phy.gpcs_address != id) ?
943 dev->mdio_instance : dev,
944 (u8) id, (u8) reg);
945 return res;
946}
947
948static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val)
949{
950 struct emac_instance *dev = netdev_priv(ndev);
951
952 __emac_mdio_write((dev->mdio_instance &&
953 dev->phy.gpcs_address != id) ?
954 dev->mdio_instance : dev,
955 (u8) id, (u8) reg, (u16) val);
956}
957
958/* Tx lock BH */
959static void __emac_set_multicast_list(struct emac_instance *dev)
960{
961 struct emac_regs __iomem *p = dev->emacp;
962 u32 rmr = emac_iff2rmr(dev->ndev);
963
964 DBG(dev, "__multicast %08x" NL, rmr);
965
966 /* I decided to relax register access rules here to avoid
967 * full EMAC reset.
968 *
969 * There is a real problem with EMAC4 core if we use MWSW_001 bit
970 * in MR1 register and do a full EMAC reset.
971 * One TX BD status update is delayed and, after EMAC reset, it
972 * never happens, resulting in TX hung (it'll be recovered by TX
973 * timeout handler eventually, but this is just gross).
974 * So we either have to do full TX reset or try to cheat here :)
975 *
976 * The only required change is to RX mode register, so I *think* all
977 * we need is just to stop RX channel. This seems to work on all
978 * tested SoCs. --ebs
979 *
980 * If we need the full reset, we might just trigger the workqueue
981 * and do it async... a bit nasty but should work --BenH
982 */
983 dev->mcast_pending = 0;
984 emac_rx_disable(dev);
985 if (rmr & EMAC_RMR_MAE)
986 emac_hash_mc(dev);
987 out_be32(&p->rmr, rmr);
988 emac_rx_enable(dev);
989}
990
991/* Tx lock BH */
992static void emac_set_multicast_list(struct net_device *ndev)
993{
994 struct emac_instance *dev = netdev_priv(ndev);
995
996 DBG(dev, "multicast" NL);
997
998 BUG_ON(!netif_running(dev->ndev));
999
1000 if (dev->no_mcast) {
1001 dev->mcast_pending = 1;
1002 return;
1003 }
1004
1005 mutex_lock(&dev->link_lock);
1006 __emac_set_multicast_list(dev);
1007 mutex_unlock(&dev->link_lock);
1008}
1009
1010static int emac_set_mac_address(struct net_device *ndev, void *sa)
1011{
1012 struct emac_instance *dev = netdev_priv(ndev);
1013 struct sockaddr *addr = sa;
1014 struct emac_regs __iomem *p = dev->emacp;
1015
1016 if (!is_valid_ether_addr(addr->sa_data))
1017 return -EADDRNOTAVAIL;
1018
1019 mutex_lock(&dev->link_lock);
1020
1021 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1022
1023 emac_rx_disable(dev);
1024 emac_tx_disable(dev);
1025 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
1026 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
1027 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
1028 ndev->dev_addr[5]);
1029 emac_tx_enable(dev);
1030 emac_rx_enable(dev);
1031
1032 mutex_unlock(&dev->link_lock);
1033
1034 return 0;
1035}
1036
1037static int emac_resize_rx_ring(struct emac_instance *dev, int new_mtu)
1038{
1039 int rx_sync_size = emac_rx_sync_size(new_mtu);
1040 int rx_skb_size = emac_rx_skb_size(new_mtu);
1041 int i, ret = 0;
1042 int mr1_jumbo_bit_change = 0;
1043
1044 mutex_lock(&dev->link_lock);
1045 emac_netif_stop(dev);
1046 emac_rx_disable(dev);
1047 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
1048
1049 if (dev->rx_sg_skb) {
1050 ++dev->estats.rx_dropped_resize;
1051 dev_kfree_skb(dev->rx_sg_skb);
1052 dev->rx_sg_skb = NULL;
1053 }
1054
1055 /* Make a first pass over RX ring and mark BDs ready, dropping
1056 * non-processed packets on the way. We need this as a separate pass
1057 * to simplify error recovery in the case of allocation failure later.
1058 */
1059 for (i = 0; i < NUM_RX_BUFF; ++i) {
1060 if (dev->rx_desc[i].ctrl & MAL_RX_CTRL_FIRST)
1061 ++dev->estats.rx_dropped_resize;
1062
1063 dev->rx_desc[i].data_len = 0;
1064 dev->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY |
1065 (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1066 }
1067
1068 /* Reallocate RX ring only if bigger skb buffers are required */
1069 if (rx_skb_size <= dev->rx_skb_size)
1070 goto skip;
1071
1072 /* Second pass, allocate new skbs */
1073 for (i = 0; i < NUM_RX_BUFF; ++i) {
1074 struct sk_buff *skb = alloc_skb(rx_skb_size, GFP_ATOMIC);
1075 if (!skb) {
1076 ret = -ENOMEM;
1077 goto oom;
1078 }
1079
1080 BUG_ON(!dev->rx_skb[i]);
1081 dev_kfree_skb(dev->rx_skb[i]);
1082
1083 skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
1084 dev->rx_desc[i].data_ptr =
1085 dma_map_single(&dev->ofdev->dev, skb->data - 2, rx_sync_size,
1086 DMA_FROM_DEVICE) + 2;
1087 dev->rx_skb[i] = skb;
1088 }
1089 skip:
1090 /* Check if we need to change "Jumbo" bit in MR1 */
1091 if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) {
1092 mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) ||
1093 (dev->ndev->mtu > ETH_DATA_LEN);
1094 } else {
1095 mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) ^
1096 (dev->ndev->mtu > ETH_DATA_LEN);
1097 }
1098
1099 if (mr1_jumbo_bit_change) {
1100 /* This is to prevent starting RX channel in emac_rx_enable() */
1101 set_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1102
1103 dev->ndev->mtu = new_mtu;
1104 emac_full_tx_reset(dev);
1105 }
1106
1107 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(new_mtu));
1108 oom:
1109 /* Restart RX */
1110 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1111 dev->rx_slot = 0;
1112 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1113 emac_rx_enable(dev);
1114 emac_netif_start(dev);
1115 mutex_unlock(&dev->link_lock);
1116
1117 return ret;
1118}
1119
1120/* Process ctx, rtnl_lock semaphore */
1121static int emac_change_mtu(struct net_device *ndev, int new_mtu)
1122{
1123 struct emac_instance *dev = netdev_priv(ndev);
1124 int ret = 0;
1125
1126 DBG(dev, "change_mtu(%d)" NL, new_mtu);
1127
1128 if (netif_running(ndev)) {
1129 /* Check if we really need to reinitialize RX ring */
1130 if (emac_rx_skb_size(ndev->mtu) != emac_rx_skb_size(new_mtu))
1131 ret = emac_resize_rx_ring(dev, new_mtu);
1132 }
1133
1134 if (!ret) {
1135 ndev->mtu = new_mtu;
1136 dev->rx_skb_size = emac_rx_skb_size(new_mtu);
1137 dev->rx_sync_size = emac_rx_sync_size(new_mtu);
1138 }
1139
1140 return ret;
1141}
1142
1143static void emac_clean_tx_ring(struct emac_instance *dev)
1144{
1145 int i;
1146
1147 for (i = 0; i < NUM_TX_BUFF; ++i) {
1148 if (dev->tx_skb[i]) {
1149 dev_kfree_skb(dev->tx_skb[i]);
1150 dev->tx_skb[i] = NULL;
1151 if (dev->tx_desc[i].ctrl & MAL_TX_CTRL_READY)
1152 ++dev->estats.tx_dropped;
1153 }
1154 dev->tx_desc[i].ctrl = 0;
1155 dev->tx_desc[i].data_ptr = 0;
1156 }
1157}
1158
1159static void emac_clean_rx_ring(struct emac_instance *dev)
1160{
1161 int i;
1162
1163 for (i = 0; i < NUM_RX_BUFF; ++i)
1164 if (dev->rx_skb[i]) {
1165 dev->rx_desc[i].ctrl = 0;
1166 dev_kfree_skb(dev->rx_skb[i]);
1167 dev->rx_skb[i] = NULL;
1168 dev->rx_desc[i].data_ptr = 0;
1169 }
1170
1171 if (dev->rx_sg_skb) {
1172 dev_kfree_skb(dev->rx_sg_skb);
1173 dev->rx_sg_skb = NULL;
1174 }
1175}
1176
1177static inline int emac_alloc_rx_skb(struct emac_instance *dev, int slot,
1178 gfp_t flags)
1179{
1180 struct sk_buff *skb = alloc_skb(dev->rx_skb_size, flags);
1181 if (unlikely(!skb))
1182 return -ENOMEM;
1183
1184 dev->rx_skb[slot] = skb;
1185 dev->rx_desc[slot].data_len = 0;
1186
1187 skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
1188 dev->rx_desc[slot].data_ptr =
1189 dma_map_single(&dev->ofdev->dev, skb->data - 2, dev->rx_sync_size,
1190 DMA_FROM_DEVICE) + 2;
1191 wmb();
1192 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1193 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1194
1195 return 0;
1196}
1197
1198static void emac_print_link_status(struct emac_instance *dev)
1199{
1200 if (netif_carrier_ok(dev->ndev))
1201 printk(KERN_INFO "%s: link is up, %d %s%s\n",
1202 dev->ndev->name, dev->phy.speed,
1203 dev->phy.duplex == DUPLEX_FULL ? "FDX" : "HDX",
1204 dev->phy.pause ? ", pause enabled" :
1205 dev->phy.asym_pause ? ", asymmetric pause enabled" : "");
1206 else
1207 printk(KERN_INFO "%s: link is down\n", dev->ndev->name);
1208}
1209
1210/* Process ctx, rtnl_lock semaphore */
1211static int emac_open(struct net_device *ndev)
1212{
1213 struct emac_instance *dev = netdev_priv(ndev);
1214 int err, i;
1215
1216 DBG(dev, "open" NL);
1217
1218 /* Setup error IRQ handler */
1219 err = request_irq(dev->emac_irq, emac_irq, 0, "EMAC", dev);
1220 if (err) {
1221 printk(KERN_ERR "%s: failed to request IRQ %d\n",
1222 ndev->name, dev->emac_irq);
1223 return err;
1224 }
1225
1226 /* Allocate RX ring */
1227 for (i = 0; i < NUM_RX_BUFF; ++i)
1228 if (emac_alloc_rx_skb(dev, i, GFP_KERNEL)) {
1229 printk(KERN_ERR "%s: failed to allocate RX ring\n",
1230 ndev->name);
1231 goto oom;
1232 }
1233
1234 dev->tx_cnt = dev->tx_slot = dev->ack_slot = dev->rx_slot = 0;
1235 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1236 dev->rx_sg_skb = NULL;
1237
1238 mutex_lock(&dev->link_lock);
1239 dev->opened = 1;
1240
1241 /* Start PHY polling now.
1242 */
1243 if (dev->phy.address >= 0) {
1244 int link_poll_interval;
1245 if (dev->phy.def->ops->poll_link(&dev->phy)) {
1246 dev->phy.def->ops->read_link(&dev->phy);
1247 emac_rx_clk_default(dev);
1248 netif_carrier_on(dev->ndev);
1249 link_poll_interval = PHY_POLL_LINK_ON;
1250 } else {
1251 emac_rx_clk_tx(dev);
1252 netif_carrier_off(dev->ndev);
1253 link_poll_interval = PHY_POLL_LINK_OFF;
1254 }
1255 dev->link_polling = 1;
1256 wmb();
1257 schedule_delayed_work(&dev->link_work, link_poll_interval);
1258 emac_print_link_status(dev);
1259 } else
1260 netif_carrier_on(dev->ndev);
1261
1262 /* Required for Pause packet support in EMAC */
1263 dev_mc_add_global(ndev, default_mcast_addr);
1264
1265 emac_configure(dev);
1266 mal_poll_add(dev->mal, &dev->commac);
1267 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
1268 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(ndev->mtu));
1269 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1270 emac_tx_enable(dev);
1271 emac_rx_enable(dev);
1272 emac_netif_start(dev);
1273
1274 mutex_unlock(&dev->link_lock);
1275
1276 return 0;
1277 oom:
1278 emac_clean_rx_ring(dev);
1279 free_irq(dev->emac_irq, dev);
1280
1281 return -ENOMEM;
1282}
1283
1284/* BHs disabled */
1285#if 0
1286static int emac_link_differs(struct emac_instance *dev)
1287{
1288 u32 r = in_be32(&dev->emacp->mr1);
1289
1290 int duplex = r & EMAC_MR1_FDE ? DUPLEX_FULL : DUPLEX_HALF;
1291 int speed, pause, asym_pause;
1292
1293 if (r & EMAC_MR1_MF_1000)
1294 speed = SPEED_1000;
1295 else if (r & EMAC_MR1_MF_100)
1296 speed = SPEED_100;
1297 else
1298 speed = SPEED_10;
1299
1300 switch (r & (EMAC_MR1_EIFC | EMAC_MR1_APP)) {
1301 case (EMAC_MR1_EIFC | EMAC_MR1_APP):
1302 pause = 1;
1303 asym_pause = 0;
1304 break;
1305 case EMAC_MR1_APP:
1306 pause = 0;
1307 asym_pause = 1;
1308 break;
1309 default:
1310 pause = asym_pause = 0;
1311 }
1312 return speed != dev->phy.speed || duplex != dev->phy.duplex ||
1313 pause != dev->phy.pause || asym_pause != dev->phy.asym_pause;
1314}
1315#endif
1316
1317static void emac_link_timer(struct work_struct *work)
1318{
1319 struct emac_instance *dev =
1320 container_of(to_delayed_work(work),
1321 struct emac_instance, link_work);
1322 int link_poll_interval;
1323
1324 mutex_lock(&dev->link_lock);
1325 DBG2(dev, "link timer" NL);
1326
1327 if (!dev->opened)
1328 goto bail;
1329
1330 if (dev->phy.def->ops->poll_link(&dev->phy)) {
1331 if (!netif_carrier_ok(dev->ndev)) {
1332 emac_rx_clk_default(dev);
1333 /* Get new link parameters */
1334 dev->phy.def->ops->read_link(&dev->phy);
1335
1336 netif_carrier_on(dev->ndev);
1337 emac_netif_stop(dev);
1338 emac_full_tx_reset(dev);
1339 emac_netif_start(dev);
1340 emac_print_link_status(dev);
1341 }
1342 link_poll_interval = PHY_POLL_LINK_ON;
1343 } else {
1344 if (netif_carrier_ok(dev->ndev)) {
1345 emac_rx_clk_tx(dev);
1346 netif_carrier_off(dev->ndev);
1347 netif_tx_disable(dev->ndev);
1348 emac_reinitialize(dev);
1349 emac_print_link_status(dev);
1350 }
1351 link_poll_interval = PHY_POLL_LINK_OFF;
1352 }
1353 schedule_delayed_work(&dev->link_work, link_poll_interval);
1354 bail:
1355 mutex_unlock(&dev->link_lock);
1356}
1357
1358static void emac_force_link_update(struct emac_instance *dev)
1359{
1360 netif_carrier_off(dev->ndev);
1361 smp_rmb();
1362 if (dev->link_polling) {
1363 cancel_delayed_work_sync(&dev->link_work);
1364 if (dev->link_polling)
1365 schedule_delayed_work(&dev->link_work, PHY_POLL_LINK_OFF);
1366 }
1367}
1368
1369/* Process ctx, rtnl_lock semaphore */
1370static int emac_close(struct net_device *ndev)
1371{
1372 struct emac_instance *dev = netdev_priv(ndev);
1373
1374 DBG(dev, "close" NL);
1375
1376 if (dev->phy.address >= 0) {
1377 dev->link_polling = 0;
1378 cancel_delayed_work_sync(&dev->link_work);
1379 }
1380 mutex_lock(&dev->link_lock);
1381 emac_netif_stop(dev);
1382 dev->opened = 0;
1383 mutex_unlock(&dev->link_lock);
1384
1385 emac_rx_disable(dev);
1386 emac_tx_disable(dev);
1387 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
1388 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
1389 mal_poll_del(dev->mal, &dev->commac);
1390
1391 emac_clean_tx_ring(dev);
1392 emac_clean_rx_ring(dev);
1393
1394 free_irq(dev->emac_irq, dev);
1395
1396 netif_carrier_off(ndev);
1397
1398 return 0;
1399}
1400
1401static inline u16 emac_tx_csum(struct emac_instance *dev,
1402 struct sk_buff *skb)
1403{
1404 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
1405 (skb->ip_summed == CHECKSUM_PARTIAL)) {
1406 ++dev->stats.tx_packets_csum;
1407 return EMAC_TX_CTRL_TAH_CSUM;
1408 }
1409 return 0;
1410}
1411
1412static inline int emac_xmit_finish(struct emac_instance *dev, int len)
1413{
1414 struct emac_regs __iomem *p = dev->emacp;
1415 struct net_device *ndev = dev->ndev;
1416
1417 /* Send the packet out. If the if makes a significant perf
1418 * difference, then we can store the TMR0 value in "dev"
1419 * instead
1420 */
1421 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
1422 out_be32(&p->tmr0, EMAC4_TMR0_XMIT);
1423 else
1424 out_be32(&p->tmr0, EMAC_TMR0_XMIT);
1425
1426 if (unlikely(++dev->tx_cnt == NUM_TX_BUFF)) {
1427 netif_stop_queue(ndev);
1428 DBG2(dev, "stopped TX queue" NL);
1429 }
1430
1431 netif_trans_update(ndev);
1432 ++dev->stats.tx_packets;
1433 dev->stats.tx_bytes += len;
1434
1435 return NETDEV_TX_OK;
1436}
1437
1438/* Tx lock BH */
1439static int emac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1440{
1441 struct emac_instance *dev = netdev_priv(ndev);
1442 unsigned int len = skb->len;
1443 int slot;
1444
1445 u16 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1446 MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb);
1447
1448 slot = dev->tx_slot++;
1449 if (dev->tx_slot == NUM_TX_BUFF) {
1450 dev->tx_slot = 0;
1451 ctrl |= MAL_TX_CTRL_WRAP;
1452 }
1453
1454 DBG2(dev, "xmit(%u) %d" NL, len, slot);
1455
1456 dev->tx_skb[slot] = skb;
1457 dev->tx_desc[slot].data_ptr = dma_map_single(&dev->ofdev->dev,
1458 skb->data, len,
1459 DMA_TO_DEVICE);
1460 dev->tx_desc[slot].data_len = (u16) len;
1461 wmb();
1462 dev->tx_desc[slot].ctrl = ctrl;
1463
1464 return emac_xmit_finish(dev, len);
1465}
1466
1467static inline int emac_xmit_split(struct emac_instance *dev, int slot,
1468 u32 pd, int len, int last, u16 base_ctrl)
1469{
1470 while (1) {
1471 u16 ctrl = base_ctrl;
1472 int chunk = min(len, MAL_MAX_TX_SIZE);
1473 len -= chunk;
1474
1475 slot = (slot + 1) % NUM_TX_BUFF;
1476
1477 if (last && !len)
1478 ctrl |= MAL_TX_CTRL_LAST;
1479 if (slot == NUM_TX_BUFF - 1)
1480 ctrl |= MAL_TX_CTRL_WRAP;
1481
1482 dev->tx_skb[slot] = NULL;
1483 dev->tx_desc[slot].data_ptr = pd;
1484 dev->tx_desc[slot].data_len = (u16) chunk;
1485 dev->tx_desc[slot].ctrl = ctrl;
1486 ++dev->tx_cnt;
1487
1488 if (!len)
1489 break;
1490
1491 pd += chunk;
1492 }
1493 return slot;
1494}
1495
1496/* Tx lock BH disabled (SG version for TAH equipped EMACs) */
1497static int emac_start_xmit_sg(struct sk_buff *skb, struct net_device *ndev)
1498{
1499 struct emac_instance *dev = netdev_priv(ndev);
1500 int nr_frags = skb_shinfo(skb)->nr_frags;
1501 int len = skb->len, chunk;
1502 int slot, i;
1503 u16 ctrl;
1504 u32 pd;
1505
1506 /* This is common "fast" path */
1507 if (likely(!nr_frags && len <= MAL_MAX_TX_SIZE))
1508 return emac_start_xmit(skb, ndev);
1509
1510 len -= skb->data_len;
1511
1512 /* Note, this is only an *estimation*, we can still run out of empty
1513 * slots because of the additional fragmentation into
1514 * MAL_MAX_TX_SIZE-sized chunks
1515 */
1516 if (unlikely(dev->tx_cnt + nr_frags + mal_tx_chunks(len) > NUM_TX_BUFF))
1517 goto stop_queue;
1518
1519 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1520 emac_tx_csum(dev, skb);
1521 slot = dev->tx_slot;
1522
1523 /* skb data */
1524 dev->tx_skb[slot] = NULL;
1525 chunk = min(len, MAL_MAX_TX_SIZE);
1526 dev->tx_desc[slot].data_ptr = pd =
1527 dma_map_single(&dev->ofdev->dev, skb->data, len, DMA_TO_DEVICE);
1528 dev->tx_desc[slot].data_len = (u16) chunk;
1529 len -= chunk;
1530 if (unlikely(len))
1531 slot = emac_xmit_split(dev, slot, pd + chunk, len, !nr_frags,
1532 ctrl);
1533 /* skb fragments */
1534 for (i = 0; i < nr_frags; ++i) {
1535 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
1536 len = skb_frag_size(frag);
1537
1538 if (unlikely(dev->tx_cnt + mal_tx_chunks(len) >= NUM_TX_BUFF))
1539 goto undo_frame;
1540
1541 pd = skb_frag_dma_map(&dev->ofdev->dev, frag, 0, len,
1542 DMA_TO_DEVICE);
1543
1544 slot = emac_xmit_split(dev, slot, pd, len, i == nr_frags - 1,
1545 ctrl);
1546 }
1547
1548 DBG2(dev, "xmit_sg(%u) %d - %d" NL, skb->len, dev->tx_slot, slot);
1549
1550 /* Attach skb to the last slot so we don't release it too early */
1551 dev->tx_skb[slot] = skb;
1552
1553 /* Send the packet out */
1554 if (dev->tx_slot == NUM_TX_BUFF - 1)
1555 ctrl |= MAL_TX_CTRL_WRAP;
1556 wmb();
1557 dev->tx_desc[dev->tx_slot].ctrl = ctrl;
1558 dev->tx_slot = (slot + 1) % NUM_TX_BUFF;
1559
1560 return emac_xmit_finish(dev, skb->len);
1561
1562 undo_frame:
1563 /* Well, too bad. Our previous estimation was overly optimistic.
1564 * Undo everything.
1565 */
1566 while (slot != dev->tx_slot) {
1567 dev->tx_desc[slot].ctrl = 0;
1568 --dev->tx_cnt;
1569 if (--slot < 0)
1570 slot = NUM_TX_BUFF - 1;
1571 }
1572 ++dev->estats.tx_undo;
1573
1574 stop_queue:
1575 netif_stop_queue(ndev);
1576 DBG2(dev, "stopped TX queue" NL);
1577 return NETDEV_TX_BUSY;
1578}
1579
1580/* Tx lock BHs */
1581static void emac_parse_tx_error(struct emac_instance *dev, u16 ctrl)
1582{
1583 struct emac_error_stats *st = &dev->estats;
1584
1585 DBG(dev, "BD TX error %04x" NL, ctrl);
1586
1587 ++st->tx_bd_errors;
1588 if (ctrl & EMAC_TX_ST_BFCS)
1589 ++st->tx_bd_bad_fcs;
1590 if (ctrl & EMAC_TX_ST_LCS)
1591 ++st->tx_bd_carrier_loss;
1592 if (ctrl & EMAC_TX_ST_ED)
1593 ++st->tx_bd_excessive_deferral;
1594 if (ctrl & EMAC_TX_ST_EC)
1595 ++st->tx_bd_excessive_collisions;
1596 if (ctrl & EMAC_TX_ST_LC)
1597 ++st->tx_bd_late_collision;
1598 if (ctrl & EMAC_TX_ST_MC)
1599 ++st->tx_bd_multple_collisions;
1600 if (ctrl & EMAC_TX_ST_SC)
1601 ++st->tx_bd_single_collision;
1602 if (ctrl & EMAC_TX_ST_UR)
1603 ++st->tx_bd_underrun;
1604 if (ctrl & EMAC_TX_ST_SQE)
1605 ++st->tx_bd_sqe;
1606}
1607
1608static void emac_poll_tx(void *param)
1609{
1610 struct emac_instance *dev = param;
1611 u32 bad_mask;
1612
1613 DBG2(dev, "poll_tx, %d %d" NL, dev->tx_cnt, dev->ack_slot);
1614
1615 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
1616 bad_mask = EMAC_IS_BAD_TX_TAH;
1617 else
1618 bad_mask = EMAC_IS_BAD_TX;
1619
1620 netif_tx_lock_bh(dev->ndev);
1621 if (dev->tx_cnt) {
1622 u16 ctrl;
1623 int slot = dev->ack_slot, n = 0;
1624 again:
1625 ctrl = dev->tx_desc[slot].ctrl;
1626 if (!(ctrl & MAL_TX_CTRL_READY)) {
1627 struct sk_buff *skb = dev->tx_skb[slot];
1628 ++n;
1629
1630 if (skb) {
1631 dev_kfree_skb(skb);
1632 dev->tx_skb[slot] = NULL;
1633 }
1634 slot = (slot + 1) % NUM_TX_BUFF;
1635
1636 if (unlikely(ctrl & bad_mask))
1637 emac_parse_tx_error(dev, ctrl);
1638
1639 if (--dev->tx_cnt)
1640 goto again;
1641 }
1642 if (n) {
1643 dev->ack_slot = slot;
1644 if (netif_queue_stopped(dev->ndev) &&
1645 dev->tx_cnt < EMAC_TX_WAKEUP_THRESH)
1646 netif_wake_queue(dev->ndev);
1647
1648 DBG2(dev, "tx %d pkts" NL, n);
1649 }
1650 }
1651 netif_tx_unlock_bh(dev->ndev);
1652}
1653
1654static inline void emac_recycle_rx_skb(struct emac_instance *dev, int slot,
1655 int len)
1656{
1657 struct sk_buff *skb = dev->rx_skb[slot];
1658
1659 DBG2(dev, "recycle %d %d" NL, slot, len);
1660
1661 if (len)
1662 dma_map_single(&dev->ofdev->dev, skb->data - 2,
1663 EMAC_DMA_ALIGN(len + 2), DMA_FROM_DEVICE);
1664
1665 dev->rx_desc[slot].data_len = 0;
1666 wmb();
1667 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1668 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1669}
1670
1671static void emac_parse_rx_error(struct emac_instance *dev, u16 ctrl)
1672{
1673 struct emac_error_stats *st = &dev->estats;
1674
1675 DBG(dev, "BD RX error %04x" NL, ctrl);
1676
1677 ++st->rx_bd_errors;
1678 if (ctrl & EMAC_RX_ST_OE)
1679 ++st->rx_bd_overrun;
1680 if (ctrl & EMAC_RX_ST_BP)
1681 ++st->rx_bd_bad_packet;
1682 if (ctrl & EMAC_RX_ST_RP)
1683 ++st->rx_bd_runt_packet;
1684 if (ctrl & EMAC_RX_ST_SE)
1685 ++st->rx_bd_short_event;
1686 if (ctrl & EMAC_RX_ST_AE)
1687 ++st->rx_bd_alignment_error;
1688 if (ctrl & EMAC_RX_ST_BFCS)
1689 ++st->rx_bd_bad_fcs;
1690 if (ctrl & EMAC_RX_ST_PTL)
1691 ++st->rx_bd_packet_too_long;
1692 if (ctrl & EMAC_RX_ST_ORE)
1693 ++st->rx_bd_out_of_range;
1694 if (ctrl & EMAC_RX_ST_IRE)
1695 ++st->rx_bd_in_range;
1696}
1697
1698static inline void emac_rx_csum(struct emac_instance *dev,
1699 struct sk_buff *skb, u16 ctrl)
1700{
1701#ifdef CONFIG_IBM_EMAC_TAH
1702 if (!ctrl && dev->tah_dev) {
1703 skb->ip_summed = CHECKSUM_UNNECESSARY;
1704 ++dev->stats.rx_packets_csum;
1705 }
1706#endif
1707}
1708
1709static inline int emac_rx_sg_append(struct emac_instance *dev, int slot)
1710{
1711 if (likely(dev->rx_sg_skb != NULL)) {
1712 int len = dev->rx_desc[slot].data_len;
1713 int tot_len = dev->rx_sg_skb->len + len;
1714
1715 if (unlikely(tot_len + 2 > dev->rx_skb_size)) {
1716 ++dev->estats.rx_dropped_mtu;
1717 dev_kfree_skb(dev->rx_sg_skb);
1718 dev->rx_sg_skb = NULL;
1719 } else {
1720 memcpy(skb_tail_pointer(dev->rx_sg_skb),
1721 dev->rx_skb[slot]->data, len);
1722 skb_put(dev->rx_sg_skb, len);
1723 emac_recycle_rx_skb(dev, slot, len);
1724 return 0;
1725 }
1726 }
1727 emac_recycle_rx_skb(dev, slot, 0);
1728 return -1;
1729}
1730
1731/* NAPI poll context */
1732static int emac_poll_rx(void *param, int budget)
1733{
1734 struct emac_instance *dev = param;
1735 int slot = dev->rx_slot, received = 0;
1736
1737 DBG2(dev, "poll_rx(%d)" NL, budget);
1738
1739 again:
1740 while (budget > 0) {
1741 int len;
1742 struct sk_buff *skb;
1743 u16 ctrl = dev->rx_desc[slot].ctrl;
1744
1745 if (ctrl & MAL_RX_CTRL_EMPTY)
1746 break;
1747
1748 skb = dev->rx_skb[slot];
1749 mb();
1750 len = dev->rx_desc[slot].data_len;
1751
1752 if (unlikely(!MAL_IS_SINGLE_RX(ctrl)))
1753 goto sg;
1754
1755 ctrl &= EMAC_BAD_RX_MASK;
1756 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1757 emac_parse_rx_error(dev, ctrl);
1758 ++dev->estats.rx_dropped_error;
1759 emac_recycle_rx_skb(dev, slot, 0);
1760 len = 0;
1761 goto next;
1762 }
1763
1764 if (len < ETH_HLEN) {
1765 ++dev->estats.rx_dropped_stack;
1766 emac_recycle_rx_skb(dev, slot, len);
1767 goto next;
1768 }
1769
1770 if (len && len < EMAC_RX_COPY_THRESH) {
1771 struct sk_buff *copy_skb =
1772 alloc_skb(len + EMAC_RX_SKB_HEADROOM + 2, GFP_ATOMIC);
1773 if (unlikely(!copy_skb))
1774 goto oom;
1775
1776 skb_reserve(copy_skb, EMAC_RX_SKB_HEADROOM + 2);
1777 memcpy(copy_skb->data - 2, skb->data - 2, len + 2);
1778 emac_recycle_rx_skb(dev, slot, len);
1779 skb = copy_skb;
1780 } else if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC)))
1781 goto oom;
1782
1783 skb_put(skb, len);
1784 push_packet:
1785 skb->protocol = eth_type_trans(skb, dev->ndev);
1786 emac_rx_csum(dev, skb, ctrl);
1787
1788 if (unlikely(netif_receive_skb(skb) == NET_RX_DROP))
1789 ++dev->estats.rx_dropped_stack;
1790 next:
1791 ++dev->stats.rx_packets;
1792 skip:
1793 dev->stats.rx_bytes += len;
1794 slot = (slot + 1) % NUM_RX_BUFF;
1795 --budget;
1796 ++received;
1797 continue;
1798 sg:
1799 if (ctrl & MAL_RX_CTRL_FIRST) {
1800 BUG_ON(dev->rx_sg_skb);
1801 if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC))) {
1802 DBG(dev, "rx OOM %d" NL, slot);
1803 ++dev->estats.rx_dropped_oom;
1804 emac_recycle_rx_skb(dev, slot, 0);
1805 } else {
1806 dev->rx_sg_skb = skb;
1807 skb_put(skb, len);
1808 }
1809 } else if (!emac_rx_sg_append(dev, slot) &&
1810 (ctrl & MAL_RX_CTRL_LAST)) {
1811
1812 skb = dev->rx_sg_skb;
1813 dev->rx_sg_skb = NULL;
1814
1815 ctrl &= EMAC_BAD_RX_MASK;
1816 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1817 emac_parse_rx_error(dev, ctrl);
1818 ++dev->estats.rx_dropped_error;
1819 dev_kfree_skb(skb);
1820 len = 0;
1821 } else
1822 goto push_packet;
1823 }
1824 goto skip;
1825 oom:
1826 DBG(dev, "rx OOM %d" NL, slot);
1827 /* Drop the packet and recycle skb */
1828 ++dev->estats.rx_dropped_oom;
1829 emac_recycle_rx_skb(dev, slot, 0);
1830 goto next;
1831 }
1832
1833 if (received) {
1834 DBG2(dev, "rx %d BDs" NL, received);
1835 dev->rx_slot = slot;
1836 }
1837
1838 if (unlikely(budget && test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags))) {
1839 mb();
1840 if (!(dev->rx_desc[slot].ctrl & MAL_RX_CTRL_EMPTY)) {
1841 DBG2(dev, "rx restart" NL);
1842 received = 0;
1843 goto again;
1844 }
1845
1846 if (dev->rx_sg_skb) {
1847 DBG2(dev, "dropping partial rx packet" NL);
1848 ++dev->estats.rx_dropped_error;
1849 dev_kfree_skb(dev->rx_sg_skb);
1850 dev->rx_sg_skb = NULL;
1851 }
1852
1853 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1854 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1855 emac_rx_enable(dev);
1856 dev->rx_slot = 0;
1857 }
1858 return received;
1859}
1860
1861/* NAPI poll context */
1862static int emac_peek_rx(void *param)
1863{
1864 struct emac_instance *dev = param;
1865
1866 return !(dev->rx_desc[dev->rx_slot].ctrl & MAL_RX_CTRL_EMPTY);
1867}
1868
1869/* NAPI poll context */
1870static int emac_peek_rx_sg(void *param)
1871{
1872 struct emac_instance *dev = param;
1873
1874 int slot = dev->rx_slot;
1875 while (1) {
1876 u16 ctrl = dev->rx_desc[slot].ctrl;
1877 if (ctrl & MAL_RX_CTRL_EMPTY)
1878 return 0;
1879 else if (ctrl & MAL_RX_CTRL_LAST)
1880 return 1;
1881
1882 slot = (slot + 1) % NUM_RX_BUFF;
1883
1884 /* I'm just being paranoid here :) */
1885 if (unlikely(slot == dev->rx_slot))
1886 return 0;
1887 }
1888}
1889
1890/* Hard IRQ */
1891static void emac_rxde(void *param)
1892{
1893 struct emac_instance *dev = param;
1894
1895 ++dev->estats.rx_stopped;
1896 emac_rx_disable_async(dev);
1897}
1898
1899/* Hard IRQ */
1900static irqreturn_t emac_irq(int irq, void *dev_instance)
1901{
1902 struct emac_instance *dev = dev_instance;
1903 struct emac_regs __iomem *p = dev->emacp;
1904 struct emac_error_stats *st = &dev->estats;
1905 u32 isr;
1906
1907 spin_lock(&dev->lock);
1908
1909 isr = in_be32(&p->isr);
1910 out_be32(&p->isr, isr);
1911
1912 DBG(dev, "isr = %08x" NL, isr);
1913
1914 if (isr & EMAC4_ISR_TXPE)
1915 ++st->tx_parity;
1916 if (isr & EMAC4_ISR_RXPE)
1917 ++st->rx_parity;
1918 if (isr & EMAC4_ISR_TXUE)
1919 ++st->tx_underrun;
1920 if (isr & EMAC4_ISR_RXOE)
1921 ++st->rx_fifo_overrun;
1922 if (isr & EMAC_ISR_OVR)
1923 ++st->rx_overrun;
1924 if (isr & EMAC_ISR_BP)
1925 ++st->rx_bad_packet;
1926 if (isr & EMAC_ISR_RP)
1927 ++st->rx_runt_packet;
1928 if (isr & EMAC_ISR_SE)
1929 ++st->rx_short_event;
1930 if (isr & EMAC_ISR_ALE)
1931 ++st->rx_alignment_error;
1932 if (isr & EMAC_ISR_BFCS)
1933 ++st->rx_bad_fcs;
1934 if (isr & EMAC_ISR_PTLE)
1935 ++st->rx_packet_too_long;
1936 if (isr & EMAC_ISR_ORE)
1937 ++st->rx_out_of_range;
1938 if (isr & EMAC_ISR_IRE)
1939 ++st->rx_in_range;
1940 if (isr & EMAC_ISR_SQE)
1941 ++st->tx_sqe;
1942 if (isr & EMAC_ISR_TE)
1943 ++st->tx_errors;
1944
1945 spin_unlock(&dev->lock);
1946
1947 return IRQ_HANDLED;
1948}
1949
1950static struct net_device_stats *emac_stats(struct net_device *ndev)
1951{
1952 struct emac_instance *dev = netdev_priv(ndev);
1953 struct emac_stats *st = &dev->stats;
1954 struct emac_error_stats *est = &dev->estats;
1955 struct net_device_stats *nst = &ndev->stats;
1956 unsigned long flags;
1957
1958 DBG2(dev, "stats" NL);
1959
1960 /* Compute "legacy" statistics */
1961 spin_lock_irqsave(&dev->lock, flags);
1962 nst->rx_packets = (unsigned long)st->rx_packets;
1963 nst->rx_bytes = (unsigned long)st->rx_bytes;
1964 nst->tx_packets = (unsigned long)st->tx_packets;
1965 nst->tx_bytes = (unsigned long)st->tx_bytes;
1966 nst->rx_dropped = (unsigned long)(est->rx_dropped_oom +
1967 est->rx_dropped_error +
1968 est->rx_dropped_resize +
1969 est->rx_dropped_mtu);
1970 nst->tx_dropped = (unsigned long)est->tx_dropped;
1971
1972 nst->rx_errors = (unsigned long)est->rx_bd_errors;
1973 nst->rx_fifo_errors = (unsigned long)(est->rx_bd_overrun +
1974 est->rx_fifo_overrun +
1975 est->rx_overrun);
1976 nst->rx_frame_errors = (unsigned long)(est->rx_bd_alignment_error +
1977 est->rx_alignment_error);
1978 nst->rx_crc_errors = (unsigned long)(est->rx_bd_bad_fcs +
1979 est->rx_bad_fcs);
1980 nst->rx_length_errors = (unsigned long)(est->rx_bd_runt_packet +
1981 est->rx_bd_short_event +
1982 est->rx_bd_packet_too_long +
1983 est->rx_bd_out_of_range +
1984 est->rx_bd_in_range +
1985 est->rx_runt_packet +
1986 est->rx_short_event +
1987 est->rx_packet_too_long +
1988 est->rx_out_of_range +
1989 est->rx_in_range);
1990
1991 nst->tx_errors = (unsigned long)(est->tx_bd_errors + est->tx_errors);
1992 nst->tx_fifo_errors = (unsigned long)(est->tx_bd_underrun +
1993 est->tx_underrun);
1994 nst->tx_carrier_errors = (unsigned long)est->tx_bd_carrier_loss;
1995 nst->collisions = (unsigned long)(est->tx_bd_excessive_deferral +
1996 est->tx_bd_excessive_collisions +
1997 est->tx_bd_late_collision +
1998 est->tx_bd_multple_collisions);
1999 spin_unlock_irqrestore(&dev->lock, flags);
2000 return nst;
2001}
2002
2003static struct mal_commac_ops emac_commac_ops = {
2004 .poll_tx = &emac_poll_tx,
2005 .poll_rx = &emac_poll_rx,
2006 .peek_rx = &emac_peek_rx,
2007 .rxde = &emac_rxde,
2008};
2009
2010static struct mal_commac_ops emac_commac_sg_ops = {
2011 .poll_tx = &emac_poll_tx,
2012 .poll_rx = &emac_poll_rx,
2013 .peek_rx = &emac_peek_rx_sg,
2014 .rxde = &emac_rxde,
2015};
2016
2017/* Ethtool support */
2018static int emac_ethtool_get_link_ksettings(struct net_device *ndev,
2019 struct ethtool_link_ksettings *cmd)
2020{
2021 struct emac_instance *dev = netdev_priv(ndev);
2022 u32 supported, advertising;
2023
2024 supported = dev->phy.features;
2025 cmd->base.port = PORT_MII;
2026 cmd->base.phy_address = dev->phy.address;
2027
2028 mutex_lock(&dev->link_lock);
2029 advertising = dev->phy.advertising;
2030 cmd->base.autoneg = dev->phy.autoneg;
2031 cmd->base.speed = dev->phy.speed;
2032 cmd->base.duplex = dev->phy.duplex;
2033 mutex_unlock(&dev->link_lock);
2034
2035 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2036 supported);
2037 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2038 advertising);
2039
2040 return 0;
2041}
2042
2043static int
2044emac_ethtool_set_link_ksettings(struct net_device *ndev,
2045 const struct ethtool_link_ksettings *cmd)
2046{
2047 struct emac_instance *dev = netdev_priv(ndev);
2048 u32 f = dev->phy.features;
2049 u32 advertising;
2050
2051 ethtool_convert_link_mode_to_legacy_u32(&advertising,
2052 cmd->link_modes.advertising);
2053
2054 DBG(dev, "set_settings(%d, %d, %d, 0x%08x)" NL,
2055 cmd->base.autoneg, cmd->base.speed, cmd->base.duplex, advertising);
2056
2057 /* Basic sanity checks */
2058 if (dev->phy.address < 0)
2059 return -EOPNOTSUPP;
2060 if (cmd->base.autoneg != AUTONEG_ENABLE &&
2061 cmd->base.autoneg != AUTONEG_DISABLE)
2062 return -EINVAL;
2063 if (cmd->base.autoneg == AUTONEG_ENABLE && advertising == 0)
2064 return -EINVAL;
2065 if (cmd->base.duplex != DUPLEX_HALF && cmd->base.duplex != DUPLEX_FULL)
2066 return -EINVAL;
2067
2068 if (cmd->base.autoneg == AUTONEG_DISABLE) {
2069 switch (cmd->base.speed) {
2070 case SPEED_10:
2071 if (cmd->base.duplex == DUPLEX_HALF &&
2072 !(f & SUPPORTED_10baseT_Half))
2073 return -EINVAL;
2074 if (cmd->base.duplex == DUPLEX_FULL &&
2075 !(f & SUPPORTED_10baseT_Full))
2076 return -EINVAL;
2077 break;
2078 case SPEED_100:
2079 if (cmd->base.duplex == DUPLEX_HALF &&
2080 !(f & SUPPORTED_100baseT_Half))
2081 return -EINVAL;
2082 if (cmd->base.duplex == DUPLEX_FULL &&
2083 !(f & SUPPORTED_100baseT_Full))
2084 return -EINVAL;
2085 break;
2086 case SPEED_1000:
2087 if (cmd->base.duplex == DUPLEX_HALF &&
2088 !(f & SUPPORTED_1000baseT_Half))
2089 return -EINVAL;
2090 if (cmd->base.duplex == DUPLEX_FULL &&
2091 !(f & SUPPORTED_1000baseT_Full))
2092 return -EINVAL;
2093 break;
2094 default:
2095 return -EINVAL;
2096 }
2097
2098 mutex_lock(&dev->link_lock);
2099 dev->phy.def->ops->setup_forced(&dev->phy, cmd->base.speed,
2100 cmd->base.duplex);
2101 mutex_unlock(&dev->link_lock);
2102
2103 } else {
2104 if (!(f & SUPPORTED_Autoneg))
2105 return -EINVAL;
2106
2107 mutex_lock(&dev->link_lock);
2108 dev->phy.def->ops->setup_aneg(&dev->phy,
2109 (advertising & f) |
2110 (dev->phy.advertising &
2111 (ADVERTISED_Pause |
2112 ADVERTISED_Asym_Pause)));
2113 mutex_unlock(&dev->link_lock);
2114 }
2115 emac_force_link_update(dev);
2116
2117 return 0;
2118}
2119
2120static void emac_ethtool_get_ringparam(struct net_device *ndev,
2121 struct ethtool_ringparam *rp)
2122{
2123 rp->rx_max_pending = rp->rx_pending = NUM_RX_BUFF;
2124 rp->tx_max_pending = rp->tx_pending = NUM_TX_BUFF;
2125}
2126
2127static void emac_ethtool_get_pauseparam(struct net_device *ndev,
2128 struct ethtool_pauseparam *pp)
2129{
2130 struct emac_instance *dev = netdev_priv(ndev);
2131
2132 mutex_lock(&dev->link_lock);
2133 if ((dev->phy.features & SUPPORTED_Autoneg) &&
2134 (dev->phy.advertising & (ADVERTISED_Pause | ADVERTISED_Asym_Pause)))
2135 pp->autoneg = 1;
2136
2137 if (dev->phy.duplex == DUPLEX_FULL) {
2138 if (dev->phy.pause)
2139 pp->rx_pause = pp->tx_pause = 1;
2140 else if (dev->phy.asym_pause)
2141 pp->tx_pause = 1;
2142 }
2143 mutex_unlock(&dev->link_lock);
2144}
2145
2146static int emac_get_regs_len(struct emac_instance *dev)
2147{
2148 return sizeof(struct emac_ethtool_regs_subhdr) +
2149 sizeof(struct emac_regs);
2150}
2151
2152static int emac_ethtool_get_regs_len(struct net_device *ndev)
2153{
2154 struct emac_instance *dev = netdev_priv(ndev);
2155 int size;
2156
2157 size = sizeof(struct emac_ethtool_regs_hdr) +
2158 emac_get_regs_len(dev) + mal_get_regs_len(dev->mal);
2159 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2160 size += zmii_get_regs_len(dev->zmii_dev);
2161 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2162 size += rgmii_get_regs_len(dev->rgmii_dev);
2163 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2164 size += tah_get_regs_len(dev->tah_dev);
2165
2166 return size;
2167}
2168
2169static void *emac_dump_regs(struct emac_instance *dev, void *buf)
2170{
2171 struct emac_ethtool_regs_subhdr *hdr = buf;
2172
2173 hdr->index = dev->cell_index;
2174 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) {
2175 hdr->version = EMAC4SYNC_ETHTOOL_REGS_VER;
2176 } else if (emac_has_feature(dev, EMAC_FTR_EMAC4)) {
2177 hdr->version = EMAC4_ETHTOOL_REGS_VER;
2178 } else {
2179 hdr->version = EMAC_ETHTOOL_REGS_VER;
2180 }
2181 memcpy_fromio(hdr + 1, dev->emacp, sizeof(struct emac_regs));
2182 return (void *)(hdr + 1) + sizeof(struct emac_regs);
2183}
2184
2185static void emac_ethtool_get_regs(struct net_device *ndev,
2186 struct ethtool_regs *regs, void *buf)
2187{
2188 struct emac_instance *dev = netdev_priv(ndev);
2189 struct emac_ethtool_regs_hdr *hdr = buf;
2190
2191 hdr->components = 0;
2192 buf = hdr + 1;
2193
2194 buf = mal_dump_regs(dev->mal, buf);
2195 buf = emac_dump_regs(dev, buf);
2196 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) {
2197 hdr->components |= EMAC_ETHTOOL_REGS_ZMII;
2198 buf = zmii_dump_regs(dev->zmii_dev, buf);
2199 }
2200 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) {
2201 hdr->components |= EMAC_ETHTOOL_REGS_RGMII;
2202 buf = rgmii_dump_regs(dev->rgmii_dev, buf);
2203 }
2204 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) {
2205 hdr->components |= EMAC_ETHTOOL_REGS_TAH;
2206 buf = tah_dump_regs(dev->tah_dev, buf);
2207 }
2208}
2209
2210static int emac_ethtool_nway_reset(struct net_device *ndev)
2211{
2212 struct emac_instance *dev = netdev_priv(ndev);
2213 int res = 0;
2214
2215 DBG(dev, "nway_reset" NL);
2216
2217 if (dev->phy.address < 0)
2218 return -EOPNOTSUPP;
2219
2220 mutex_lock(&dev->link_lock);
2221 if (!dev->phy.autoneg) {
2222 res = -EINVAL;
2223 goto out;
2224 }
2225
2226 dev->phy.def->ops->setup_aneg(&dev->phy, dev->phy.advertising);
2227 out:
2228 mutex_unlock(&dev->link_lock);
2229 emac_force_link_update(dev);
2230 return res;
2231}
2232
2233static int emac_ethtool_get_sset_count(struct net_device *ndev, int stringset)
2234{
2235 if (stringset == ETH_SS_STATS)
2236 return EMAC_ETHTOOL_STATS_COUNT;
2237 else
2238 return -EINVAL;
2239}
2240
2241static void emac_ethtool_get_strings(struct net_device *ndev, u32 stringset,
2242 u8 * buf)
2243{
2244 if (stringset == ETH_SS_STATS)
2245 memcpy(buf, &emac_stats_keys, sizeof(emac_stats_keys));
2246}
2247
2248static void emac_ethtool_get_ethtool_stats(struct net_device *ndev,
2249 struct ethtool_stats *estats,
2250 u64 * tmp_stats)
2251{
2252 struct emac_instance *dev = netdev_priv(ndev);
2253
2254 memcpy(tmp_stats, &dev->stats, sizeof(dev->stats));
2255 tmp_stats += sizeof(dev->stats) / sizeof(u64);
2256 memcpy(tmp_stats, &dev->estats, sizeof(dev->estats));
2257}
2258
2259static void emac_ethtool_get_drvinfo(struct net_device *ndev,
2260 struct ethtool_drvinfo *info)
2261{
2262 struct emac_instance *dev = netdev_priv(ndev);
2263
2264 strlcpy(info->driver, "ibm_emac", sizeof(info->driver));
2265 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2266 snprintf(info->bus_info, sizeof(info->bus_info), "PPC 4xx EMAC-%d %pOF",
2267 dev->cell_index, dev->ofdev->dev.of_node);
2268}
2269
2270static const struct ethtool_ops emac_ethtool_ops = {
2271 .get_drvinfo = emac_ethtool_get_drvinfo,
2272
2273 .get_regs_len = emac_ethtool_get_regs_len,
2274 .get_regs = emac_ethtool_get_regs,
2275
2276 .nway_reset = emac_ethtool_nway_reset,
2277
2278 .get_ringparam = emac_ethtool_get_ringparam,
2279 .get_pauseparam = emac_ethtool_get_pauseparam,
2280
2281 .get_strings = emac_ethtool_get_strings,
2282 .get_sset_count = emac_ethtool_get_sset_count,
2283 .get_ethtool_stats = emac_ethtool_get_ethtool_stats,
2284
2285 .get_link = ethtool_op_get_link,
2286 .get_link_ksettings = emac_ethtool_get_link_ksettings,
2287 .set_link_ksettings = emac_ethtool_set_link_ksettings,
2288};
2289
2290static int emac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2291{
2292 struct emac_instance *dev = netdev_priv(ndev);
2293 struct mii_ioctl_data *data = if_mii(rq);
2294
2295 DBG(dev, "ioctl %08x" NL, cmd);
2296
2297 if (dev->phy.address < 0)
2298 return -EOPNOTSUPP;
2299
2300 switch (cmd) {
2301 case SIOCGMIIPHY:
2302 data->phy_id = dev->phy.address;
2303 /* Fall through */
2304 case SIOCGMIIREG:
2305 data->val_out = emac_mdio_read(ndev, dev->phy.address,
2306 data->reg_num);
2307 return 0;
2308
2309 case SIOCSMIIREG:
2310 emac_mdio_write(ndev, dev->phy.address, data->reg_num,
2311 data->val_in);
2312 return 0;
2313 default:
2314 return -EOPNOTSUPP;
2315 }
2316}
2317
2318struct emac_depentry {
2319 u32 phandle;
2320 struct device_node *node;
2321 struct platform_device *ofdev;
2322 void *drvdata;
2323};
2324
2325#define EMAC_DEP_MAL_IDX 0
2326#define EMAC_DEP_ZMII_IDX 1
2327#define EMAC_DEP_RGMII_IDX 2
2328#define EMAC_DEP_TAH_IDX 3
2329#define EMAC_DEP_MDIO_IDX 4
2330#define EMAC_DEP_PREV_IDX 5
2331#define EMAC_DEP_COUNT 6
2332
2333static int emac_check_deps(struct emac_instance *dev,
2334 struct emac_depentry *deps)
2335{
2336 int i, there = 0;
2337 struct device_node *np;
2338
2339 for (i = 0; i < EMAC_DEP_COUNT; i++) {
2340 /* no dependency on that item, allright */
2341 if (deps[i].phandle == 0) {
2342 there++;
2343 continue;
2344 }
2345 /* special case for blist as the dependency might go away */
2346 if (i == EMAC_DEP_PREV_IDX) {
2347 np = *(dev->blist - 1);
2348 if (np == NULL) {
2349 deps[i].phandle = 0;
2350 there++;
2351 continue;
2352 }
2353 if (deps[i].node == NULL)
2354 deps[i].node = of_node_get(np);
2355 }
2356 if (deps[i].node == NULL)
2357 deps[i].node = of_find_node_by_phandle(deps[i].phandle);
2358 if (deps[i].node == NULL)
2359 continue;
2360 if (deps[i].ofdev == NULL)
2361 deps[i].ofdev = of_find_device_by_node(deps[i].node);
2362 if (deps[i].ofdev == NULL)
2363 continue;
2364 if (deps[i].drvdata == NULL)
2365 deps[i].drvdata = platform_get_drvdata(deps[i].ofdev);
2366 if (deps[i].drvdata != NULL)
2367 there++;
2368 }
2369 return there == EMAC_DEP_COUNT;
2370}
2371
2372static void emac_put_deps(struct emac_instance *dev)
2373{
2374 of_dev_put(dev->mal_dev);
2375 of_dev_put(dev->zmii_dev);
2376 of_dev_put(dev->rgmii_dev);
2377 of_dev_put(dev->mdio_dev);
2378 of_dev_put(dev->tah_dev);
2379}
2380
2381static int emac_of_bus_notify(struct notifier_block *nb, unsigned long action,
2382 void *data)
2383{
2384 /* We are only intereted in device addition */
2385 if (action == BUS_NOTIFY_BOUND_DRIVER)
2386 wake_up_all(&emac_probe_wait);
2387 return 0;
2388}
2389
2390static struct notifier_block emac_of_bus_notifier = {
2391 .notifier_call = emac_of_bus_notify
2392};
2393
2394static int emac_wait_deps(struct emac_instance *dev)
2395{
2396 struct emac_depentry deps[EMAC_DEP_COUNT];
2397 int i, err;
2398
2399 memset(&deps, 0, sizeof(deps));
2400
2401 deps[EMAC_DEP_MAL_IDX].phandle = dev->mal_ph;
2402 deps[EMAC_DEP_ZMII_IDX].phandle = dev->zmii_ph;
2403 deps[EMAC_DEP_RGMII_IDX].phandle = dev->rgmii_ph;
2404 if (dev->tah_ph)
2405 deps[EMAC_DEP_TAH_IDX].phandle = dev->tah_ph;
2406 if (dev->mdio_ph)
2407 deps[EMAC_DEP_MDIO_IDX].phandle = dev->mdio_ph;
2408 if (dev->blist && dev->blist > emac_boot_list)
2409 deps[EMAC_DEP_PREV_IDX].phandle = 0xffffffffu;
2410 bus_register_notifier(&platform_bus_type, &emac_of_bus_notifier);
2411 wait_event_timeout(emac_probe_wait,
2412 emac_check_deps(dev, deps),
2413 EMAC_PROBE_DEP_TIMEOUT);
2414 bus_unregister_notifier(&platform_bus_type, &emac_of_bus_notifier);
2415 err = emac_check_deps(dev, deps) ? 0 : -ENODEV;
2416 for (i = 0; i < EMAC_DEP_COUNT; i++) {
2417 of_node_put(deps[i].node);
2418 if (err)
2419 of_dev_put(deps[i].ofdev);
2420 }
2421 if (err == 0) {
2422 dev->mal_dev = deps[EMAC_DEP_MAL_IDX].ofdev;
2423 dev->zmii_dev = deps[EMAC_DEP_ZMII_IDX].ofdev;
2424 dev->rgmii_dev = deps[EMAC_DEP_RGMII_IDX].ofdev;
2425 dev->tah_dev = deps[EMAC_DEP_TAH_IDX].ofdev;
2426 dev->mdio_dev = deps[EMAC_DEP_MDIO_IDX].ofdev;
2427 }
2428 of_dev_put(deps[EMAC_DEP_PREV_IDX].ofdev);
2429 return err;
2430}
2431
2432static int emac_read_uint_prop(struct device_node *np, const char *name,
2433 u32 *val, int fatal)
2434{
2435 int len;
2436 const u32 *prop = of_get_property(np, name, &len);
2437 if (prop == NULL || len < sizeof(u32)) {
2438 if (fatal)
2439 printk(KERN_ERR "%pOF: missing %s property\n",
2440 np, name);
2441 return -ENODEV;
2442 }
2443 *val = *prop;
2444 return 0;
2445}
2446
2447static void emac_adjust_link(struct net_device *ndev)
2448{
2449 struct emac_instance *dev = netdev_priv(ndev);
2450 struct phy_device *phy = dev->phy_dev;
2451
2452 dev->phy.autoneg = phy->autoneg;
2453 dev->phy.speed = phy->speed;
2454 dev->phy.duplex = phy->duplex;
2455 dev->phy.pause = phy->pause;
2456 dev->phy.asym_pause = phy->asym_pause;
2457 dev->phy.advertising = phy->advertising;
2458}
2459
2460static int emac_mii_bus_read(struct mii_bus *bus, int addr, int regnum)
2461{
2462 int ret = emac_mdio_read(bus->priv, addr, regnum);
2463 /* This is a workaround for powered down ports/phys.
2464 * In the wild, this was seen on the Cisco Meraki MX60(W).
2465 * This hardware disables ports as part of the handoff
2466 * procedure. Accessing the ports will lead to errors
2467 * (-ETIMEDOUT, -EREMOTEIO) that do more harm than good.
2468 */
2469 return ret < 0 ? 0xffff : ret;
2470}
2471
2472static int emac_mii_bus_write(struct mii_bus *bus, int addr,
2473 int regnum, u16 val)
2474{
2475 emac_mdio_write(bus->priv, addr, regnum, val);
2476 return 0;
2477}
2478
2479static int emac_mii_bus_reset(struct mii_bus *bus)
2480{
2481 struct emac_instance *dev = netdev_priv(bus->priv);
2482
2483 return emac_reset(dev);
2484}
2485
2486static int emac_mdio_phy_start_aneg(struct mii_phy *phy,
2487 struct phy_device *phy_dev)
2488{
2489 phy_dev->autoneg = phy->autoneg;
2490 phy_dev->speed = phy->speed;
2491 phy_dev->duplex = phy->duplex;
2492 phy_dev->advertising = phy->advertising;
2493 return phy_start_aneg(phy_dev);
2494}
2495
2496static int emac_mdio_setup_aneg(struct mii_phy *phy, u32 advertise)
2497{
2498 struct net_device *ndev = phy->dev;
2499 struct emac_instance *dev = netdev_priv(ndev);
2500
2501 phy->autoneg = AUTONEG_ENABLE;
2502 phy->advertising = advertise;
2503 return emac_mdio_phy_start_aneg(phy, dev->phy_dev);
2504}
2505
2506static int emac_mdio_setup_forced(struct mii_phy *phy, int speed, int fd)
2507{
2508 struct net_device *ndev = phy->dev;
2509 struct emac_instance *dev = netdev_priv(ndev);
2510
2511 phy->autoneg = AUTONEG_DISABLE;
2512 phy->speed = speed;
2513 phy->duplex = fd;
2514 return emac_mdio_phy_start_aneg(phy, dev->phy_dev);
2515}
2516
2517static int emac_mdio_poll_link(struct mii_phy *phy)
2518{
2519 struct net_device *ndev = phy->dev;
2520 struct emac_instance *dev = netdev_priv(ndev);
2521 int res;
2522
2523 res = phy_read_status(dev->phy_dev);
2524 if (res) {
2525 dev_err(&dev->ofdev->dev, "link update failed (%d).", res);
2526 return ethtool_op_get_link(ndev);
2527 }
2528
2529 return dev->phy_dev->link;
2530}
2531
2532static int emac_mdio_read_link(struct mii_phy *phy)
2533{
2534 struct net_device *ndev = phy->dev;
2535 struct emac_instance *dev = netdev_priv(ndev);
2536 struct phy_device *phy_dev = dev->phy_dev;
2537 int res;
2538
2539 res = phy_read_status(phy_dev);
2540 if (res)
2541 return res;
2542
2543 phy->speed = phy_dev->speed;
2544 phy->duplex = phy_dev->duplex;
2545 phy->pause = phy_dev->pause;
2546 phy->asym_pause = phy_dev->asym_pause;
2547 return 0;
2548}
2549
2550static int emac_mdio_init_phy(struct mii_phy *phy)
2551{
2552 struct net_device *ndev = phy->dev;
2553 struct emac_instance *dev = netdev_priv(ndev);
2554
2555 phy_start(dev->phy_dev);
2556 return phy_init_hw(dev->phy_dev);
2557}
2558
2559static const struct mii_phy_ops emac_dt_mdio_phy_ops = {
2560 .init = emac_mdio_init_phy,
2561 .setup_aneg = emac_mdio_setup_aneg,
2562 .setup_forced = emac_mdio_setup_forced,
2563 .poll_link = emac_mdio_poll_link,
2564 .read_link = emac_mdio_read_link,
2565};
2566
2567static int emac_dt_mdio_probe(struct emac_instance *dev)
2568{
2569 struct device_node *mii_np;
2570 int res;
2571
2572 mii_np = of_get_child_by_name(dev->ofdev->dev.of_node, "mdio");
2573 if (!mii_np) {
2574 dev_err(&dev->ofdev->dev, "no mdio definition found.");
2575 return -ENODEV;
2576 }
2577
2578 if (!of_device_is_available(mii_np)) {
2579 res = -ENODEV;
2580 goto put_node;
2581 }
2582
2583 dev->mii_bus = devm_mdiobus_alloc(&dev->ofdev->dev);
2584 if (!dev->mii_bus) {
2585 res = -ENOMEM;
2586 goto put_node;
2587 }
2588
2589 dev->mii_bus->priv = dev->ndev;
2590 dev->mii_bus->parent = dev->ndev->dev.parent;
2591 dev->mii_bus->name = "emac_mdio";
2592 dev->mii_bus->read = &emac_mii_bus_read;
2593 dev->mii_bus->write = &emac_mii_bus_write;
2594 dev->mii_bus->reset = &emac_mii_bus_reset;
2595 snprintf(dev->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev->ofdev->name);
2596 res = of_mdiobus_register(dev->mii_bus, mii_np);
2597 if (res) {
2598 dev_err(&dev->ofdev->dev, "cannot register MDIO bus %s (%d)",
2599 dev->mii_bus->name, res);
2600 }
2601
2602 put_node:
2603 of_node_put(mii_np);
2604 return res;
2605}
2606
2607static int emac_dt_phy_connect(struct emac_instance *dev,
2608 struct device_node *phy_handle)
2609{
2610 dev->phy.def = devm_kzalloc(&dev->ofdev->dev, sizeof(*dev->phy.def),
2611 GFP_KERNEL);
2612 if (!dev->phy.def)
2613 return -ENOMEM;
2614
2615 dev->phy_dev = of_phy_connect(dev->ndev, phy_handle, &emac_adjust_link,
2616 0, dev->phy_mode);
2617 if (!dev->phy_dev) {
2618 dev_err(&dev->ofdev->dev, "failed to connect to PHY.\n");
2619 return -ENODEV;
2620 }
2621
2622 dev->phy.def->phy_id = dev->phy_dev->drv->phy_id;
2623 dev->phy.def->phy_id_mask = dev->phy_dev->drv->phy_id_mask;
2624 dev->phy.def->name = dev->phy_dev->drv->name;
2625 dev->phy.def->ops = &emac_dt_mdio_phy_ops;
2626 dev->phy.features = dev->phy_dev->supported;
2627 dev->phy.address = dev->phy_dev->mdio.addr;
2628 dev->phy.mode = dev->phy_dev->interface;
2629 return 0;
2630}
2631
2632static int emac_dt_phy_probe(struct emac_instance *dev)
2633{
2634 struct device_node *np = dev->ofdev->dev.of_node;
2635 struct device_node *phy_handle;
2636 int res = 1;
2637
2638 phy_handle = of_parse_phandle(np, "phy-handle", 0);
2639
2640 if (phy_handle) {
2641 res = emac_dt_mdio_probe(dev);
2642 if (!res) {
2643 res = emac_dt_phy_connect(dev, phy_handle);
2644 if (res)
2645 mdiobus_unregister(dev->mii_bus);
2646 }
2647 }
2648
2649 of_node_put(phy_handle);
2650 return res;
2651}
2652
2653static int emac_init_phy(struct emac_instance *dev)
2654{
2655 struct device_node *np = dev->ofdev->dev.of_node;
2656 struct net_device *ndev = dev->ndev;
2657 u32 phy_map, adv;
2658 int i;
2659
2660 dev->phy.dev = ndev;
2661 dev->phy.mode = dev->phy_mode;
2662
2663 /* PHY-less configuration. */
2664 if ((dev->phy_address == 0xffffffff && dev->phy_map == 0xffffffff) ||
2665 of_phy_is_fixed_link(np)) {
2666 emac_reset(dev);
2667
2668 /* PHY-less configuration. */
2669 dev->phy.address = -1;
2670 dev->phy.features = SUPPORTED_MII;
2671 if (emac_phy_supports_gige(dev->phy_mode))
2672 dev->phy.features |= SUPPORTED_1000baseT_Full;
2673 else
2674 dev->phy.features |= SUPPORTED_100baseT_Full;
2675 dev->phy.pause = 1;
2676
2677 if (of_phy_is_fixed_link(np)) {
2678 int res = emac_dt_mdio_probe(dev);
2679
2680 if (!res) {
2681 res = of_phy_register_fixed_link(np);
2682 if (res)
2683 mdiobus_unregister(dev->mii_bus);
2684 }
2685 return res;
2686 }
2687 return 0;
2688 }
2689
2690 mutex_lock(&emac_phy_map_lock);
2691 phy_map = dev->phy_map | busy_phy_map;
2692
2693 DBG(dev, "PHY maps %08x %08x" NL, dev->phy_map, busy_phy_map);
2694
2695 dev->phy.mdio_read = emac_mdio_read;
2696 dev->phy.mdio_write = emac_mdio_write;
2697
2698 /* Enable internal clock source */
2699#ifdef CONFIG_PPC_DCR_NATIVE
2700 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2701 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
2702#endif
2703 /* PHY clock workaround */
2704 emac_rx_clk_tx(dev);
2705
2706 /* Enable internal clock source on 440GX*/
2707#ifdef CONFIG_PPC_DCR_NATIVE
2708 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2709 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
2710#endif
2711 /* Configure EMAC with defaults so we can at least use MDIO
2712 * This is needed mostly for 440GX
2713 */
2714 if (emac_phy_gpcs(dev->phy.mode)) {
2715 /* XXX
2716 * Make GPCS PHY address equal to EMAC index.
2717 * We probably should take into account busy_phy_map
2718 * and/or phy_map here.
2719 *
2720 * Note that the busy_phy_map is currently global
2721 * while it should probably be per-ASIC...
2722 */
2723 dev->phy.gpcs_address = dev->gpcs_address;
2724 if (dev->phy.gpcs_address == 0xffffffff)
2725 dev->phy.address = dev->cell_index;
2726 }
2727
2728 emac_configure(dev);
2729
2730 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) {
2731 int res = emac_dt_phy_probe(dev);
2732
2733 switch (res) {
2734 case 1:
2735 /* No phy-handle property configured.
2736 * Continue with the existing phy probe
2737 * and setup code.
2738 */
2739 break;
2740
2741 case 0:
2742 mutex_unlock(&emac_phy_map_lock);
2743 goto init_phy;
2744
2745 default:
2746 mutex_unlock(&emac_phy_map_lock);
2747 dev_err(&dev->ofdev->dev, "failed to attach dt phy (%d).\n",
2748 res);
2749 return res;
2750 }
2751 }
2752
2753 if (dev->phy_address != 0xffffffff)
2754 phy_map = ~(1 << dev->phy_address);
2755
2756 for (i = 0; i < 0x20; phy_map >>= 1, ++i)
2757 if (!(phy_map & 1)) {
2758 int r;
2759 busy_phy_map |= 1 << i;
2760
2761 /* Quick check if there is a PHY at the address */
2762 r = emac_mdio_read(dev->ndev, i, MII_BMCR);
2763 if (r == 0xffff || r < 0)
2764 continue;
2765 if (!emac_mii_phy_probe(&dev->phy, i))
2766 break;
2767 }
2768
2769 /* Enable external clock source */
2770#ifdef CONFIG_PPC_DCR_NATIVE
2771 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2772 dcri_clrset(SDR0, SDR0_MFR, SDR0_MFR_ECS, 0);
2773#endif
2774 mutex_unlock(&emac_phy_map_lock);
2775 if (i == 0x20) {
2776 printk(KERN_WARNING "%pOF: can't find PHY!\n", np);
2777 return -ENXIO;
2778 }
2779
2780 init_phy:
2781 /* Init PHY */
2782 if (dev->phy.def->ops->init)
2783 dev->phy.def->ops->init(&dev->phy);
2784
2785 /* Disable any PHY features not supported by the platform */
2786 dev->phy.def->features &= ~dev->phy_feat_exc;
2787 dev->phy.features &= ~dev->phy_feat_exc;
2788
2789 /* Setup initial link parameters */
2790 if (dev->phy.features & SUPPORTED_Autoneg) {
2791 adv = dev->phy.features;
2792 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x))
2793 adv |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
2794 /* Restart autonegotiation */
2795 dev->phy.def->ops->setup_aneg(&dev->phy, adv);
2796 } else {
2797 u32 f = dev->phy.def->features;
2798 int speed = SPEED_10, fd = DUPLEX_HALF;
2799
2800 /* Select highest supported speed/duplex */
2801 if (f & SUPPORTED_1000baseT_Full) {
2802 speed = SPEED_1000;
2803 fd = DUPLEX_FULL;
2804 } else if (f & SUPPORTED_1000baseT_Half)
2805 speed = SPEED_1000;
2806 else if (f & SUPPORTED_100baseT_Full) {
2807 speed = SPEED_100;
2808 fd = DUPLEX_FULL;
2809 } else if (f & SUPPORTED_100baseT_Half)
2810 speed = SPEED_100;
2811 else if (f & SUPPORTED_10baseT_Full)
2812 fd = DUPLEX_FULL;
2813
2814 /* Force link parameters */
2815 dev->phy.def->ops->setup_forced(&dev->phy, speed, fd);
2816 }
2817 return 0;
2818}
2819
2820static int emac_init_config(struct emac_instance *dev)
2821{
2822 struct device_node *np = dev->ofdev->dev.of_node;
2823 const void *p;
2824
2825 /* Read config from device-tree */
2826 if (emac_read_uint_prop(np, "mal-device", &dev->mal_ph, 1))
2827 return -ENXIO;
2828 if (emac_read_uint_prop(np, "mal-tx-channel", &dev->mal_tx_chan, 1))
2829 return -ENXIO;
2830 if (emac_read_uint_prop(np, "mal-rx-channel", &dev->mal_rx_chan, 1))
2831 return -ENXIO;
2832 if (emac_read_uint_prop(np, "cell-index", &dev->cell_index, 1))
2833 return -ENXIO;
2834 if (emac_read_uint_prop(np, "max-frame-size", &dev->max_mtu, 0))
2835 dev->max_mtu = ETH_DATA_LEN;
2836 if (emac_read_uint_prop(np, "rx-fifo-size", &dev->rx_fifo_size, 0))
2837 dev->rx_fifo_size = 2048;
2838 if (emac_read_uint_prop(np, "tx-fifo-size", &dev->tx_fifo_size, 0))
2839 dev->tx_fifo_size = 2048;
2840 if (emac_read_uint_prop(np, "rx-fifo-size-gige", &dev->rx_fifo_size_gige, 0))
2841 dev->rx_fifo_size_gige = dev->rx_fifo_size;
2842 if (emac_read_uint_prop(np, "tx-fifo-size-gige", &dev->tx_fifo_size_gige, 0))
2843 dev->tx_fifo_size_gige = dev->tx_fifo_size;
2844 if (emac_read_uint_prop(np, "phy-address", &dev->phy_address, 0))
2845 dev->phy_address = 0xffffffff;
2846 if (emac_read_uint_prop(np, "phy-map", &dev->phy_map, 0))
2847 dev->phy_map = 0xffffffff;
2848 if (emac_read_uint_prop(np, "gpcs-address", &dev->gpcs_address, 0))
2849 dev->gpcs_address = 0xffffffff;
2850 if (emac_read_uint_prop(np->parent, "clock-frequency", &dev->opb_bus_freq, 1))
2851 return -ENXIO;
2852 if (emac_read_uint_prop(np, "tah-device", &dev->tah_ph, 0))
2853 dev->tah_ph = 0;
2854 if (emac_read_uint_prop(np, "tah-channel", &dev->tah_port, 0))
2855 dev->tah_port = 0;
2856 if (emac_read_uint_prop(np, "mdio-device", &dev->mdio_ph, 0))
2857 dev->mdio_ph = 0;
2858 if (emac_read_uint_prop(np, "zmii-device", &dev->zmii_ph, 0))
2859 dev->zmii_ph = 0;
2860 if (emac_read_uint_prop(np, "zmii-channel", &dev->zmii_port, 0))
2861 dev->zmii_port = 0xffffffff;
2862 if (emac_read_uint_prop(np, "rgmii-device", &dev->rgmii_ph, 0))
2863 dev->rgmii_ph = 0;
2864 if (emac_read_uint_prop(np, "rgmii-channel", &dev->rgmii_port, 0))
2865 dev->rgmii_port = 0xffffffff;
2866 if (emac_read_uint_prop(np, "fifo-entry-size", &dev->fifo_entry_size, 0))
2867 dev->fifo_entry_size = 16;
2868 if (emac_read_uint_prop(np, "mal-burst-size", &dev->mal_burst_size, 0))
2869 dev->mal_burst_size = 256;
2870
2871 /* PHY mode needs some decoding */
2872 dev->phy_mode = of_get_phy_mode(np);
2873 if (dev->phy_mode < 0)
2874 dev->phy_mode = PHY_INTERFACE_MODE_NA;
2875
2876 /* Check EMAC version */
2877 if (of_device_is_compatible(np, "ibm,emac4sync")) {
2878 dev->features |= (EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC);
2879 if (of_device_is_compatible(np, "ibm,emac-460ex") ||
2880 of_device_is_compatible(np, "ibm,emac-460gt"))
2881 dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX;
2882 if (of_device_is_compatible(np, "ibm,emac-405ex") ||
2883 of_device_is_compatible(np, "ibm,emac-405exr"))
2884 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
2885 if (of_device_is_compatible(np, "ibm,emac-apm821xx")) {
2886 dev->features |= (EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE |
2887 EMAC_FTR_APM821XX_NO_HALF_DUPLEX |
2888 EMAC_FTR_460EX_PHY_CLK_FIX);
2889 }
2890 } else if (of_device_is_compatible(np, "ibm,emac4")) {
2891 dev->features |= EMAC_FTR_EMAC4;
2892 if (of_device_is_compatible(np, "ibm,emac-440gx"))
2893 dev->features |= EMAC_FTR_440GX_PHY_CLK_FIX;
2894 } else {
2895 if (of_device_is_compatible(np, "ibm,emac-440ep") ||
2896 of_device_is_compatible(np, "ibm,emac-440gr"))
2897 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
2898 if (of_device_is_compatible(np, "ibm,emac-405ez")) {
2899#ifdef CONFIG_IBM_EMAC_NO_FLOW_CTRL
2900 dev->features |= EMAC_FTR_NO_FLOW_CONTROL_40x;
2901#else
2902 printk(KERN_ERR "%pOF: Flow control not disabled!\n",
2903 np);
2904 return -ENXIO;
2905#endif
2906 }
2907
2908 }
2909
2910 /* Fixup some feature bits based on the device tree */
2911 if (of_get_property(np, "has-inverted-stacr-oc", NULL))
2912 dev->features |= EMAC_FTR_STACR_OC_INVERT;
2913 if (of_get_property(np, "has-new-stacr-staopc", NULL))
2914 dev->features |= EMAC_FTR_HAS_NEW_STACR;
2915
2916 /* CAB lacks the appropriate properties */
2917 if (of_device_is_compatible(np, "ibm,emac-axon"))
2918 dev->features |= EMAC_FTR_HAS_NEW_STACR |
2919 EMAC_FTR_STACR_OC_INVERT;
2920
2921 /* Enable TAH/ZMII/RGMII features as found */
2922 if (dev->tah_ph != 0) {
2923#ifdef CONFIG_IBM_EMAC_TAH
2924 dev->features |= EMAC_FTR_HAS_TAH;
2925#else
2926 printk(KERN_ERR "%pOF: TAH support not enabled !\n", np);
2927 return -ENXIO;
2928#endif
2929 }
2930
2931 if (dev->zmii_ph != 0) {
2932#ifdef CONFIG_IBM_EMAC_ZMII
2933 dev->features |= EMAC_FTR_HAS_ZMII;
2934#else
2935 printk(KERN_ERR "%pOF: ZMII support not enabled !\n", np);
2936 return -ENXIO;
2937#endif
2938 }
2939
2940 if (dev->rgmii_ph != 0) {
2941#ifdef CONFIG_IBM_EMAC_RGMII
2942 dev->features |= EMAC_FTR_HAS_RGMII;
2943#else
2944 printk(KERN_ERR "%pOF: RGMII support not enabled !\n", np);
2945 return -ENXIO;
2946#endif
2947 }
2948
2949 /* Read MAC-address */
2950 p = of_get_property(np, "local-mac-address", NULL);
2951 if (p == NULL) {
2952 printk(KERN_ERR "%pOF: Can't find local-mac-address property\n",
2953 np);
2954 return -ENXIO;
2955 }
2956 memcpy(dev->ndev->dev_addr, p, ETH_ALEN);
2957
2958 /* IAHT and GAHT filter parameterization */
2959 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) {
2960 dev->xaht_slots_shift = EMAC4SYNC_XAHT_SLOTS_SHIFT;
2961 dev->xaht_width_shift = EMAC4SYNC_XAHT_WIDTH_SHIFT;
2962 } else {
2963 dev->xaht_slots_shift = EMAC4_XAHT_SLOTS_SHIFT;
2964 dev->xaht_width_shift = EMAC4_XAHT_WIDTH_SHIFT;
2965 }
2966
2967 DBG(dev, "features : 0x%08x / 0x%08x\n", dev->features, EMAC_FTRS_POSSIBLE);
2968 DBG(dev, "tx_fifo_size : %d (%d gige)\n", dev->tx_fifo_size, dev->tx_fifo_size_gige);
2969 DBG(dev, "rx_fifo_size : %d (%d gige)\n", dev->rx_fifo_size, dev->rx_fifo_size_gige);
2970 DBG(dev, "max_mtu : %d\n", dev->max_mtu);
2971 DBG(dev, "OPB freq : %d\n", dev->opb_bus_freq);
2972
2973 return 0;
2974}
2975
2976static const struct net_device_ops emac_netdev_ops = {
2977 .ndo_open = emac_open,
2978 .ndo_stop = emac_close,
2979 .ndo_get_stats = emac_stats,
2980 .ndo_set_rx_mode = emac_set_multicast_list,
2981 .ndo_do_ioctl = emac_ioctl,
2982 .ndo_tx_timeout = emac_tx_timeout,
2983 .ndo_validate_addr = eth_validate_addr,
2984 .ndo_set_mac_address = emac_set_mac_address,
2985 .ndo_start_xmit = emac_start_xmit,
2986};
2987
2988static const struct net_device_ops emac_gige_netdev_ops = {
2989 .ndo_open = emac_open,
2990 .ndo_stop = emac_close,
2991 .ndo_get_stats = emac_stats,
2992 .ndo_set_rx_mode = emac_set_multicast_list,
2993 .ndo_do_ioctl = emac_ioctl,
2994 .ndo_tx_timeout = emac_tx_timeout,
2995 .ndo_validate_addr = eth_validate_addr,
2996 .ndo_set_mac_address = emac_set_mac_address,
2997 .ndo_start_xmit = emac_start_xmit_sg,
2998 .ndo_change_mtu = emac_change_mtu,
2999};
3000
3001static int emac_probe(struct platform_device *ofdev)
3002{
3003 struct net_device *ndev;
3004 struct emac_instance *dev;
3005 struct device_node *np = ofdev->dev.of_node;
3006 struct device_node **blist = NULL;
3007 int err, i;
3008
3009 /* Skip unused/unwired EMACS. We leave the check for an unused
3010 * property here for now, but new flat device trees should set a
3011 * status property to "disabled" instead.
3012 */
3013 if (of_get_property(np, "unused", NULL) || !of_device_is_available(np))
3014 return -ENODEV;
3015
3016 /* Find ourselves in the bootlist if we are there */
3017 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
3018 if (emac_boot_list[i] == np)
3019 blist = &emac_boot_list[i];
3020
3021 /* Allocate our net_device structure */
3022 err = -ENOMEM;
3023 ndev = alloc_etherdev(sizeof(struct emac_instance));
3024 if (!ndev)
3025 goto err_gone;
3026
3027 dev = netdev_priv(ndev);
3028 dev->ndev = ndev;
3029 dev->ofdev = ofdev;
3030 dev->blist = blist;
3031 SET_NETDEV_DEV(ndev, &ofdev->dev);
3032
3033 /* Initialize some embedded data structures */
3034 mutex_init(&dev->mdio_lock);
3035 mutex_init(&dev->link_lock);
3036 spin_lock_init(&dev->lock);
3037 INIT_WORK(&dev->reset_work, emac_reset_work);
3038
3039 /* Init various config data based on device-tree */
3040 err = emac_init_config(dev);
3041 if (err)
3042 goto err_free;
3043
3044 /* Get interrupts. EMAC irq is mandatory, WOL irq is optional */
3045 dev->emac_irq = irq_of_parse_and_map(np, 0);
3046 dev->wol_irq = irq_of_parse_and_map(np, 1);
3047 if (!dev->emac_irq) {
3048 printk(KERN_ERR "%pOF: Can't map main interrupt\n", np);
3049 err = -ENODEV;
3050 goto err_free;
3051 }
3052 ndev->irq = dev->emac_irq;
3053
3054 /* Map EMAC regs */
3055 // TODO : platform_get_resource() and devm_ioremap_resource()
3056 dev->emacp = of_iomap(np, 0);
3057 if (dev->emacp == NULL) {
3058 printk(KERN_ERR "%pOF: Can't map device registers!\n", np);
3059 err = -ENOMEM;
3060 goto err_irq_unmap;
3061 }
3062
3063 /* Wait for dependent devices */
3064 err = emac_wait_deps(dev);
3065 if (err) {
3066 printk(KERN_ERR
3067 "%pOF: Timeout waiting for dependent devices\n", np);
3068 /* display more info about what's missing ? */
3069 goto err_reg_unmap;
3070 }
3071 dev->mal = platform_get_drvdata(dev->mal_dev);
3072 if (dev->mdio_dev != NULL)
3073 dev->mdio_instance = platform_get_drvdata(dev->mdio_dev);
3074
3075 /* Register with MAL */
3076 dev->commac.ops = &emac_commac_ops;
3077 dev->commac.dev = dev;
3078 dev->commac.tx_chan_mask = MAL_CHAN_MASK(dev->mal_tx_chan);
3079 dev->commac.rx_chan_mask = MAL_CHAN_MASK(dev->mal_rx_chan);
3080 err = mal_register_commac(dev->mal, &dev->commac);
3081 if (err) {
3082 printk(KERN_ERR "%pOF: failed to register with mal %pOF!\n",
3083 np, dev->mal_dev->dev.of_node);
3084 goto err_rel_deps;
3085 }
3086 dev->rx_skb_size = emac_rx_skb_size(ndev->mtu);
3087 dev->rx_sync_size = emac_rx_sync_size(ndev->mtu);
3088
3089 /* Get pointers to BD rings */
3090 dev->tx_desc =
3091 dev->mal->bd_virt + mal_tx_bd_offset(dev->mal, dev->mal_tx_chan);
3092 dev->rx_desc =
3093 dev->mal->bd_virt + mal_rx_bd_offset(dev->mal, dev->mal_rx_chan);
3094
3095 DBG(dev, "tx_desc %p" NL, dev->tx_desc);
3096 DBG(dev, "rx_desc %p" NL, dev->rx_desc);
3097
3098 /* Clean rings */
3099 memset(dev->tx_desc, 0, NUM_TX_BUFF * sizeof(struct mal_descriptor));
3100 memset(dev->rx_desc, 0, NUM_RX_BUFF * sizeof(struct mal_descriptor));
3101 memset(dev->tx_skb, 0, NUM_TX_BUFF * sizeof(struct sk_buff *));
3102 memset(dev->rx_skb, 0, NUM_RX_BUFF * sizeof(struct sk_buff *));
3103
3104 /* Attach to ZMII, if needed */
3105 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII) &&
3106 (err = zmii_attach(dev->zmii_dev, dev->zmii_port, &dev->phy_mode)) != 0)
3107 goto err_unreg_commac;
3108
3109 /* Attach to RGMII, if needed */
3110 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII) &&
3111 (err = rgmii_attach(dev->rgmii_dev, dev->rgmii_port, dev->phy_mode)) != 0)
3112 goto err_detach_zmii;
3113
3114 /* Attach to TAH, if needed */
3115 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
3116 (err = tah_attach(dev->tah_dev, dev->tah_port)) != 0)
3117 goto err_detach_rgmii;
3118
3119 /* Set some link defaults before we can find out real parameters */
3120 dev->phy.speed = SPEED_100;
3121 dev->phy.duplex = DUPLEX_FULL;
3122 dev->phy.autoneg = AUTONEG_DISABLE;
3123 dev->phy.pause = dev->phy.asym_pause = 0;
3124 dev->stop_timeout = STOP_TIMEOUT_100;
3125 INIT_DELAYED_WORK(&dev->link_work, emac_link_timer);
3126
3127 /* Some SoCs like APM821xx does not support Half Duplex mode. */
3128 if (emac_has_feature(dev, EMAC_FTR_APM821XX_NO_HALF_DUPLEX)) {
3129 dev->phy_feat_exc = (SUPPORTED_1000baseT_Half |
3130 SUPPORTED_100baseT_Half |
3131 SUPPORTED_10baseT_Half);
3132 }
3133
3134 /* Find PHY if any */
3135 err = emac_init_phy(dev);
3136 if (err != 0)
3137 goto err_detach_tah;
3138
3139 if (dev->tah_dev) {
3140 ndev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG;
3141 ndev->features |= ndev->hw_features | NETIF_F_RXCSUM;
3142 }
3143 ndev->watchdog_timeo = 5 * HZ;
3144 if (emac_phy_supports_gige(dev->phy_mode)) {
3145 ndev->netdev_ops = &emac_gige_netdev_ops;
3146 dev->commac.ops = &emac_commac_sg_ops;
3147 } else
3148 ndev->netdev_ops = &emac_netdev_ops;
3149 ndev->ethtool_ops = &emac_ethtool_ops;
3150
3151 /* MTU range: 46 - 1500 or whatever is in OF */
3152 ndev->min_mtu = EMAC_MIN_MTU;
3153 ndev->max_mtu = dev->max_mtu;
3154
3155 netif_carrier_off(ndev);
3156
3157 err = register_netdev(ndev);
3158 if (err) {
3159 printk(KERN_ERR "%pOF: failed to register net device (%d)!\n",
3160 np, err);
3161 goto err_detach_tah;
3162 }
3163
3164 /* Set our drvdata last as we don't want them visible until we are
3165 * fully initialized
3166 */
3167 wmb();
3168 platform_set_drvdata(ofdev, dev);
3169
3170 /* There's a new kid in town ! Let's tell everybody */
3171 wake_up_all(&emac_probe_wait);
3172
3173
3174 printk(KERN_INFO "%s: EMAC-%d %pOF, MAC %pM\n",
3175 ndev->name, dev->cell_index, np, ndev->dev_addr);
3176
3177 if (dev->phy_mode == PHY_INTERFACE_MODE_SGMII)
3178 printk(KERN_NOTICE "%s: in SGMII mode\n", ndev->name);
3179
3180 if (dev->phy.address >= 0)
3181 printk("%s: found %s PHY (0x%02x)\n", ndev->name,
3182 dev->phy.def->name, dev->phy.address);
3183
3184 /* Life is good */
3185 return 0;
3186
3187 /* I have a bad feeling about this ... */
3188
3189 err_detach_tah:
3190 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
3191 tah_detach(dev->tah_dev, dev->tah_port);
3192 err_detach_rgmii:
3193 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
3194 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
3195 err_detach_zmii:
3196 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
3197 zmii_detach(dev->zmii_dev, dev->zmii_port);
3198 err_unreg_commac:
3199 mal_unregister_commac(dev->mal, &dev->commac);
3200 err_rel_deps:
3201 emac_put_deps(dev);
3202 err_reg_unmap:
3203 iounmap(dev->emacp);
3204 err_irq_unmap:
3205 if (dev->wol_irq)
3206 irq_dispose_mapping(dev->wol_irq);
3207 if (dev->emac_irq)
3208 irq_dispose_mapping(dev->emac_irq);
3209 err_free:
3210 free_netdev(ndev);
3211 err_gone:
3212 /* if we were on the bootlist, remove us as we won't show up and
3213 * wake up all waiters to notify them in case they were waiting
3214 * on us
3215 */
3216 if (blist) {
3217 *blist = NULL;
3218 wake_up_all(&emac_probe_wait);
3219 }
3220 return err;
3221}
3222
3223static int emac_remove(struct platform_device *ofdev)
3224{
3225 struct emac_instance *dev = platform_get_drvdata(ofdev);
3226
3227 DBG(dev, "remove" NL);
3228
3229 unregister_netdev(dev->ndev);
3230
3231 cancel_work_sync(&dev->reset_work);
3232
3233 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
3234 tah_detach(dev->tah_dev, dev->tah_port);
3235 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
3236 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
3237 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
3238 zmii_detach(dev->zmii_dev, dev->zmii_port);
3239
3240 if (dev->phy_dev)
3241 phy_disconnect(dev->phy_dev);
3242
3243 if (dev->mii_bus)
3244 mdiobus_unregister(dev->mii_bus);
3245
3246 busy_phy_map &= ~(1 << dev->phy.address);
3247 DBG(dev, "busy_phy_map now %#x" NL, busy_phy_map);
3248
3249 mal_unregister_commac(dev->mal, &dev->commac);
3250 emac_put_deps(dev);
3251
3252 iounmap(dev->emacp);
3253
3254 if (dev->wol_irq)
3255 irq_dispose_mapping(dev->wol_irq);
3256 if (dev->emac_irq)
3257 irq_dispose_mapping(dev->emac_irq);
3258
3259 free_netdev(dev->ndev);
3260
3261 return 0;
3262}
3263
3264/* XXX Features in here should be replaced by properties... */
3265static const struct of_device_id emac_match[] =
3266{
3267 {
3268 .type = "network",
3269 .compatible = "ibm,emac",
3270 },
3271 {
3272 .type = "network",
3273 .compatible = "ibm,emac4",
3274 },
3275 {
3276 .type = "network",
3277 .compatible = "ibm,emac4sync",
3278 },
3279 {},
3280};
3281MODULE_DEVICE_TABLE(of, emac_match);
3282
3283static struct platform_driver emac_driver = {
3284 .driver = {
3285 .name = "emac",
3286 .of_match_table = emac_match,
3287 },
3288 .probe = emac_probe,
3289 .remove = emac_remove,
3290};
3291
3292static void __init emac_make_bootlist(void)
3293{
3294 struct device_node *np = NULL;
3295 int j, max, i = 0;
3296 int cell_indices[EMAC_BOOT_LIST_SIZE];
3297
3298 /* Collect EMACs */
3299 while((np = of_find_all_nodes(np)) != NULL) {
3300 const u32 *idx;
3301
3302 if (of_match_node(emac_match, np) == NULL)
3303 continue;
3304 if (of_get_property(np, "unused", NULL))
3305 continue;
3306 idx = of_get_property(np, "cell-index", NULL);
3307 if (idx == NULL)
3308 continue;
3309 cell_indices[i] = *idx;
3310 emac_boot_list[i++] = of_node_get(np);
3311 if (i >= EMAC_BOOT_LIST_SIZE) {
3312 of_node_put(np);
3313 break;
3314 }
3315 }
3316 max = i;
3317
3318 /* Bubble sort them (doh, what a creative algorithm :-) */
3319 for (i = 0; max > 1 && (i < (max - 1)); i++)
3320 for (j = i; j < max; j++) {
3321 if (cell_indices[i] > cell_indices[j]) {
3322 swap(emac_boot_list[i], emac_boot_list[j]);
3323 swap(cell_indices[i], cell_indices[j]);
3324 }
3325 }
3326}
3327
3328static int __init emac_init(void)
3329{
3330 int rc;
3331
3332 printk(KERN_INFO DRV_DESC ", version " DRV_VERSION "\n");
3333
3334 /* Build EMAC boot list */
3335 emac_make_bootlist();
3336
3337 /* Init submodules */
3338 rc = mal_init();
3339 if (rc)
3340 goto err;
3341 rc = zmii_init();
3342 if (rc)
3343 goto err_mal;
3344 rc = rgmii_init();
3345 if (rc)
3346 goto err_zmii;
3347 rc = tah_init();
3348 if (rc)
3349 goto err_rgmii;
3350 rc = platform_driver_register(&emac_driver);
3351 if (rc)
3352 goto err_tah;
3353
3354 return 0;
3355
3356 err_tah:
3357 tah_exit();
3358 err_rgmii:
3359 rgmii_exit();
3360 err_zmii:
3361 zmii_exit();
3362 err_mal:
3363 mal_exit();
3364 err:
3365 return rc;
3366}
3367
3368static void __exit emac_exit(void)
3369{
3370 int i;
3371
3372 platform_driver_unregister(&emac_driver);
3373
3374 tah_exit();
3375 rgmii_exit();
3376 zmii_exit();
3377 mal_exit();
3378
3379 /* Destroy EMAC boot list */
3380 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
3381 of_node_put(emac_boot_list[i]);
3382}
3383
3384module_init(emac_init);
3385module_exit(emac_exit);