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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * drivers/net/ethernet/ibm/emac/core.c
4 *
5 * Driver for PowerPC 4xx on-chip ethernet controller.
6 *
7 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
8 * <benh@kernel.crashing.org>
9 *
10 * Based on the arch/ppc version of the driver:
11 *
12 * Copyright (c) 2004, 2005 Zultys Technologies.
13 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
14 *
15 * Based on original work by
16 * Matt Porter <mporter@kernel.crashing.org>
17 * (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
18 * Armin Kuster <akuster@mvista.com>
19 * Johnnie Peters <jpeters@mvista.com>
20 */
21
22#include <linux/module.h>
23#include <linux/sched.h>
24#include <linux/string.h>
25#include <linux/errno.h>
26#include <linux/delay.h>
27#include <linux/types.h>
28#include <linux/pci.h>
29#include <linux/etherdevice.h>
30#include <linux/skbuff.h>
31#include <linux/crc32.h>
32#include <linux/ethtool.h>
33#include <linux/mii.h>
34#include <linux/bitops.h>
35#include <linux/of.h>
36#include <linux/of_address.h>
37#include <linux/of_irq.h>
38#include <linux/of_net.h>
39#include <linux/of_mdio.h>
40#include <linux/of_platform.h>
41#include <linux/platform_device.h>
42#include <linux/slab.h>
43
44#include <asm/processor.h>
45#include <asm/io.h>
46#include <asm/dma.h>
47#include <linux/uaccess.h>
48#include <asm/dcr.h>
49#include <asm/dcr-regs.h>
50
51#include "core.h"
52
53/*
54 * Lack of dma_unmap_???? calls is intentional.
55 *
56 * API-correct usage requires additional support state information to be
57 * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to
58 * EMAC design (e.g. TX buffer passed from network stack can be split into
59 * several BDs, dma_map_single/dma_map_page can be used to map particular BD),
60 * maintaining such information will add additional overhead.
61 * Current DMA API implementation for 4xx processors only ensures cache coherency
62 * and dma_unmap_???? routines are empty and are likely to stay this way.
63 * I decided to omit dma_unmap_??? calls because I don't want to add additional
64 * complexity just for the sake of following some abstract API, when it doesn't
65 * add any real benefit to the driver. I understand that this decision maybe
66 * controversial, but I really tried to make code API-correct and efficient
67 * at the same time and didn't come up with code I liked :(. --ebs
68 */
69
70#define DRV_NAME "emac"
71#define DRV_VERSION "3.54"
72#define DRV_DESC "PPC 4xx OCP EMAC driver"
73
74MODULE_DESCRIPTION(DRV_DESC);
75MODULE_AUTHOR
76 ("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>");
77MODULE_LICENSE("GPL");
78
79/* minimum number of free TX descriptors required to wake up TX process */
80#define EMAC_TX_WAKEUP_THRESH (NUM_TX_BUFF / 4)
81
82/* If packet size is less than this number, we allocate small skb and copy packet
83 * contents into it instead of just sending original big skb up
84 */
85#define EMAC_RX_COPY_THRESH CONFIG_IBM_EMAC_RX_COPY_THRESHOLD
86
87/* Since multiple EMACs share MDIO lines in various ways, we need
88 * to avoid re-using the same PHY ID in cases where the arch didn't
89 * setup precise phy_map entries
90 *
91 * XXX This is something that needs to be reworked as we can have multiple
92 * EMAC "sets" (multiple ASICs containing several EMACs) though we can
93 * probably require in that case to have explicit PHY IDs in the device-tree
94 */
95static u32 busy_phy_map;
96static DEFINE_MUTEX(emac_phy_map_lock);
97
98/* Having stable interface names is a doomed idea. However, it would be nice
99 * if we didn't have completely random interface names at boot too :-) It's
100 * just a matter of making everybody's life easier. Since we are doing
101 * threaded probing, it's a bit harder though. The base idea here is that
102 * we make up a list of all emacs in the device-tree before we register the
103 * driver. Every emac will then wait for the previous one in the list to
104 * initialize before itself. We should also keep that list ordered by
105 * cell_index.
106 * That list is only 4 entries long, meaning that additional EMACs don't
107 * get ordering guarantees unless EMAC_BOOT_LIST_SIZE is increased.
108 */
109
110#define EMAC_BOOT_LIST_SIZE 4
111static struct device_node *emac_boot_list[EMAC_BOOT_LIST_SIZE];
112
113/* I don't want to litter system log with timeout errors
114 * when we have brain-damaged PHY.
115 */
116static inline void emac_report_timeout_error(struct emac_instance *dev,
117 const char *error)
118{
119 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX |
120 EMAC_FTR_460EX_PHY_CLK_FIX |
121 EMAC_FTR_440EP_PHY_CLK_FIX))
122 DBG(dev, "%s" NL, error);
123 else if (net_ratelimit())
124 printk(KERN_ERR "%pOF: %s\n", dev->ofdev->dev.of_node, error);
125}
126
127/* EMAC PHY clock workaround:
128 * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX,
129 * which allows controlling each EMAC clock
130 */
131static inline void emac_rx_clk_tx(struct emac_instance *dev)
132{
133#ifdef CONFIG_PPC_DCR_NATIVE
134 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
135 dcri_clrset(SDR0, SDR0_MFR,
136 0, SDR0_MFR_ECS >> dev->cell_index);
137#endif
138}
139
140static inline void emac_rx_clk_default(struct emac_instance *dev)
141{
142#ifdef CONFIG_PPC_DCR_NATIVE
143 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
144 dcri_clrset(SDR0, SDR0_MFR,
145 SDR0_MFR_ECS >> dev->cell_index, 0);
146#endif
147}
148
149/* PHY polling intervals */
150#define PHY_POLL_LINK_ON HZ
151#define PHY_POLL_LINK_OFF (HZ / 5)
152
153/* Graceful stop timeouts in us.
154 * We should allow up to 1 frame time (full-duplex, ignoring collisions)
155 */
156#define STOP_TIMEOUT_10 1230
157#define STOP_TIMEOUT_100 124
158#define STOP_TIMEOUT_1000 13
159#define STOP_TIMEOUT_1000_JUMBO 73
160
161static unsigned char default_mcast_addr[] = {
162 0x01, 0x80, 0xC2, 0x00, 0x00, 0x01
163};
164
165/* Please, keep in sync with struct ibm_emac_stats/ibm_emac_error_stats */
166static const char emac_stats_keys[EMAC_ETHTOOL_STATS_COUNT][ETH_GSTRING_LEN] = {
167 "rx_packets", "rx_bytes", "tx_packets", "tx_bytes", "rx_packets_csum",
168 "tx_packets_csum", "tx_undo", "rx_dropped_stack", "rx_dropped_oom",
169 "rx_dropped_error", "rx_dropped_resize", "rx_dropped_mtu",
170 "rx_stopped", "rx_bd_errors", "rx_bd_overrun", "rx_bd_bad_packet",
171 "rx_bd_runt_packet", "rx_bd_short_event", "rx_bd_alignment_error",
172 "rx_bd_bad_fcs", "rx_bd_packet_too_long", "rx_bd_out_of_range",
173 "rx_bd_in_range", "rx_parity", "rx_fifo_overrun", "rx_overrun",
174 "rx_bad_packet", "rx_runt_packet", "rx_short_event",
175 "rx_alignment_error", "rx_bad_fcs", "rx_packet_too_long",
176 "rx_out_of_range", "rx_in_range", "tx_dropped", "tx_bd_errors",
177 "tx_bd_bad_fcs", "tx_bd_carrier_loss", "tx_bd_excessive_deferral",
178 "tx_bd_excessive_collisions", "tx_bd_late_collision",
179 "tx_bd_multple_collisions", "tx_bd_single_collision",
180 "tx_bd_underrun", "tx_bd_sqe", "tx_parity", "tx_underrun", "tx_sqe",
181 "tx_errors"
182};
183
184static irqreturn_t emac_irq(int irq, void *dev_instance);
185static void emac_clean_tx_ring(struct emac_instance *dev);
186static void __emac_set_multicast_list(struct emac_instance *dev);
187
188static inline int emac_phy_supports_gige(int phy_mode)
189{
190 return phy_interface_mode_is_rgmii(phy_mode) ||
191 phy_mode == PHY_INTERFACE_MODE_GMII ||
192 phy_mode == PHY_INTERFACE_MODE_SGMII ||
193 phy_mode == PHY_INTERFACE_MODE_TBI ||
194 phy_mode == PHY_INTERFACE_MODE_RTBI;
195}
196
197static inline int emac_phy_gpcs(int phy_mode)
198{
199 return phy_mode == PHY_INTERFACE_MODE_SGMII ||
200 phy_mode == PHY_INTERFACE_MODE_TBI ||
201 phy_mode == PHY_INTERFACE_MODE_RTBI;
202}
203
204static inline void emac_tx_enable(struct emac_instance *dev)
205{
206 struct emac_regs __iomem *p = dev->emacp;
207 u32 r;
208
209 DBG(dev, "tx_enable" NL);
210
211 r = in_be32(&p->mr0);
212 if (!(r & EMAC_MR0_TXE))
213 out_be32(&p->mr0, r | EMAC_MR0_TXE);
214}
215
216static void emac_tx_disable(struct emac_instance *dev)
217{
218 struct emac_regs __iomem *p = dev->emacp;
219 u32 r;
220
221 DBG(dev, "tx_disable" NL);
222
223 r = in_be32(&p->mr0);
224 if (r & EMAC_MR0_TXE) {
225 int n = dev->stop_timeout;
226 out_be32(&p->mr0, r & ~EMAC_MR0_TXE);
227 while (!(in_be32(&p->mr0) & EMAC_MR0_TXI) && n) {
228 udelay(1);
229 --n;
230 }
231 if (unlikely(!n))
232 emac_report_timeout_error(dev, "TX disable timeout");
233 }
234}
235
236static void emac_rx_enable(struct emac_instance *dev)
237{
238 struct emac_regs __iomem *p = dev->emacp;
239 u32 r;
240
241 if (unlikely(test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags)))
242 goto out;
243
244 DBG(dev, "rx_enable" NL);
245
246 r = in_be32(&p->mr0);
247 if (!(r & EMAC_MR0_RXE)) {
248 if (unlikely(!(r & EMAC_MR0_RXI))) {
249 /* Wait if previous async disable is still in progress */
250 int n = dev->stop_timeout;
251 while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
252 udelay(1);
253 --n;
254 }
255 if (unlikely(!n))
256 emac_report_timeout_error(dev,
257 "RX disable timeout");
258 }
259 out_be32(&p->mr0, r | EMAC_MR0_RXE);
260 }
261 out:
262 ;
263}
264
265static void emac_rx_disable(struct emac_instance *dev)
266{
267 struct emac_regs __iomem *p = dev->emacp;
268 u32 r;
269
270 DBG(dev, "rx_disable" NL);
271
272 r = in_be32(&p->mr0);
273 if (r & EMAC_MR0_RXE) {
274 int n = dev->stop_timeout;
275 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
276 while (!(in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
277 udelay(1);
278 --n;
279 }
280 if (unlikely(!n))
281 emac_report_timeout_error(dev, "RX disable timeout");
282 }
283}
284
285static inline void emac_netif_stop(struct emac_instance *dev)
286{
287 netif_tx_lock_bh(dev->ndev);
288 netif_addr_lock(dev->ndev);
289 dev->no_mcast = 1;
290 netif_addr_unlock(dev->ndev);
291 netif_tx_unlock_bh(dev->ndev);
292 netif_trans_update(dev->ndev); /* prevent tx timeout */
293 mal_poll_disable(dev->mal, &dev->commac);
294 netif_tx_disable(dev->ndev);
295}
296
297static inline void emac_netif_start(struct emac_instance *dev)
298{
299 netif_tx_lock_bh(dev->ndev);
300 netif_addr_lock(dev->ndev);
301 dev->no_mcast = 0;
302 if (dev->mcast_pending && netif_running(dev->ndev))
303 __emac_set_multicast_list(dev);
304 netif_addr_unlock(dev->ndev);
305 netif_tx_unlock_bh(dev->ndev);
306
307 netif_wake_queue(dev->ndev);
308
309 /* NOTE: unconditional netif_wake_queue is only appropriate
310 * so long as all callers are assured to have free tx slots
311 * (taken from tg3... though the case where that is wrong is
312 * not terribly harmful)
313 */
314 mal_poll_enable(dev->mal, &dev->commac);
315}
316
317static inline void emac_rx_disable_async(struct emac_instance *dev)
318{
319 struct emac_regs __iomem *p = dev->emacp;
320 u32 r;
321
322 DBG(dev, "rx_disable_async" NL);
323
324 r = in_be32(&p->mr0);
325 if (r & EMAC_MR0_RXE)
326 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
327}
328
329static int emac_reset(struct emac_instance *dev)
330{
331 struct emac_regs __iomem *p = dev->emacp;
332 int n = 20;
333 bool __maybe_unused try_internal_clock = false;
334
335 DBG(dev, "reset" NL);
336
337 if (!dev->reset_failed) {
338 /* 40x erratum suggests stopping RX channel before reset,
339 * we stop TX as well
340 */
341 emac_rx_disable(dev);
342 emac_tx_disable(dev);
343 }
344
345#ifdef CONFIG_PPC_DCR_NATIVE
346do_retry:
347 /*
348 * PPC460EX/GT Embedded Processor Advanced User's Manual
349 * section 28.10.1 Mode Register 0 (EMACx_MR0) states:
350 * Note: The PHY must provide a TX Clk in order to perform a soft reset
351 * of the EMAC. If none is present, select the internal clock
352 * (SDR0_ETH_CFG[EMACx_PHY_CLK] = 1).
353 * After a soft reset, select the external clock.
354 *
355 * The AR8035-A PHY Meraki MR24 does not provide a TX Clk if the
356 * ethernet cable is not attached. This causes the reset to timeout
357 * and the PHY detection code in emac_init_phy() is unable to
358 * communicate and detect the AR8035-A PHY. As a result, the emac
359 * driver bails out early and the user has no ethernet.
360 * In order to stay compatible with existing configurations, the
361 * driver will temporarily switch to the internal clock, after
362 * the first reset fails.
363 */
364 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
365 if (try_internal_clock || (dev->phy_address == 0xffffffff &&
366 dev->phy_map == 0xffffffff)) {
367 /* No PHY: select internal loop clock before reset */
368 dcri_clrset(SDR0, SDR0_ETH_CFG,
369 0, SDR0_ETH_CFG_ECS << dev->cell_index);
370 } else {
371 /* PHY present: select external clock before reset */
372 dcri_clrset(SDR0, SDR0_ETH_CFG,
373 SDR0_ETH_CFG_ECS << dev->cell_index, 0);
374 }
375 }
376#endif
377
378 out_be32(&p->mr0, EMAC_MR0_SRST);
379 while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n)
380 --n;
381
382#ifdef CONFIG_PPC_DCR_NATIVE
383 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX)) {
384 if (!n && !try_internal_clock) {
385 /* first attempt has timed out. */
386 n = 20;
387 try_internal_clock = true;
388 goto do_retry;
389 }
390
391 if (try_internal_clock || (dev->phy_address == 0xffffffff &&
392 dev->phy_map == 0xffffffff)) {
393 /* No PHY: restore external clock source after reset */
394 dcri_clrset(SDR0, SDR0_ETH_CFG,
395 SDR0_ETH_CFG_ECS << dev->cell_index, 0);
396 }
397 }
398#endif
399
400 if (n) {
401 dev->reset_failed = 0;
402 return 0;
403 } else {
404 emac_report_timeout_error(dev, "reset timeout");
405 dev->reset_failed = 1;
406 return -ETIMEDOUT;
407 }
408}
409
410static void emac_hash_mc(struct emac_instance *dev)
411{
412 u32 __iomem *gaht_base = emac_gaht_base(dev);
413 const int regs = EMAC_XAHT_REGS(dev);
414 u32 gaht_temp[EMAC_XAHT_MAX_REGS];
415 struct netdev_hw_addr *ha;
416 int i;
417
418 DBG(dev, "hash_mc %d" NL, netdev_mc_count(dev->ndev));
419
420 memset(gaht_temp, 0, sizeof (gaht_temp));
421
422 netdev_for_each_mc_addr(ha, dev->ndev) {
423 int slot, reg, mask;
424 DBG2(dev, "mc %pM" NL, ha->addr);
425
426 slot = EMAC_XAHT_CRC_TO_SLOT(dev,
427 ether_crc(ETH_ALEN, ha->addr));
428 reg = EMAC_XAHT_SLOT_TO_REG(dev, slot);
429 mask = EMAC_XAHT_SLOT_TO_MASK(dev, slot);
430
431 gaht_temp[reg] |= mask;
432 }
433
434 for (i = 0; i < regs; i++)
435 out_be32(gaht_base + i, gaht_temp[i]);
436}
437
438static inline u32 emac_iff2rmr(struct net_device *ndev)
439{
440 struct emac_instance *dev = netdev_priv(ndev);
441 u32 r;
442
443 r = EMAC_RMR_SP | EMAC_RMR_SFCS | EMAC_RMR_IAE | EMAC_RMR_BAE;
444
445 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
446 r |= EMAC4_RMR_BASE;
447 else
448 r |= EMAC_RMR_BASE;
449
450 if (ndev->flags & IFF_PROMISC)
451 r |= EMAC_RMR_PME;
452 else if (ndev->flags & IFF_ALLMULTI ||
453 (netdev_mc_count(ndev) > EMAC_XAHT_SLOTS(dev)))
454 r |= EMAC_RMR_PMME;
455 else if (!netdev_mc_empty(ndev))
456 r |= EMAC_RMR_MAE;
457
458 if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) {
459 r &= ~EMAC4_RMR_MJS_MASK;
460 r |= EMAC4_RMR_MJS(ndev->mtu);
461 }
462
463 return r;
464}
465
466static u32 __emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
467{
468 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC_MR1_TR0_MULT;
469
470 DBG2(dev, "__emac_calc_base_mr1" NL);
471
472 switch(tx_size) {
473 case 2048:
474 ret |= EMAC_MR1_TFS_2K;
475 break;
476 default:
477 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n",
478 dev->ndev->name, tx_size);
479 }
480
481 switch(rx_size) {
482 case 16384:
483 ret |= EMAC_MR1_RFS_16K;
484 break;
485 case 4096:
486 ret |= EMAC_MR1_RFS_4K;
487 break;
488 default:
489 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
490 dev->ndev->name, rx_size);
491 }
492
493 return ret;
494}
495
496static u32 __emac4_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
497{
498 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC4_MR1_TR |
499 EMAC4_MR1_OBCI(dev->opb_bus_freq / 1000000);
500
501 DBG2(dev, "__emac4_calc_base_mr1" NL);
502
503 switch(tx_size) {
504 case 16384:
505 ret |= EMAC4_MR1_TFS_16K;
506 break;
507 case 8192:
508 ret |= EMAC4_MR1_TFS_8K;
509 break;
510 case 4096:
511 ret |= EMAC4_MR1_TFS_4K;
512 break;
513 case 2048:
514 ret |= EMAC4_MR1_TFS_2K;
515 break;
516 default:
517 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n",
518 dev->ndev->name, tx_size);
519 }
520
521 switch(rx_size) {
522 case 16384:
523 ret |= EMAC4_MR1_RFS_16K;
524 break;
525 case 8192:
526 ret |= EMAC4_MR1_RFS_8K;
527 break;
528 case 4096:
529 ret |= EMAC4_MR1_RFS_4K;
530 break;
531 case 2048:
532 ret |= EMAC4_MR1_RFS_2K;
533 break;
534 default:
535 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
536 dev->ndev->name, rx_size);
537 }
538
539 return ret;
540}
541
542static u32 emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
543{
544 return emac_has_feature(dev, EMAC_FTR_EMAC4) ?
545 __emac4_calc_base_mr1(dev, tx_size, rx_size) :
546 __emac_calc_base_mr1(dev, tx_size, rx_size);
547}
548
549static inline u32 emac_calc_trtr(struct emac_instance *dev, unsigned int size)
550{
551 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
552 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT_EMAC4;
553 else
554 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT;
555}
556
557static inline u32 emac_calc_rwmr(struct emac_instance *dev,
558 unsigned int low, unsigned int high)
559{
560 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
561 return (low << 22) | ( (high & 0x3ff) << 6);
562 else
563 return (low << 23) | ( (high & 0x1ff) << 7);
564}
565
566static int emac_configure(struct emac_instance *dev)
567{
568 struct emac_regs __iomem *p = dev->emacp;
569 struct net_device *ndev = dev->ndev;
570 int tx_size, rx_size, link = netif_carrier_ok(dev->ndev);
571 u32 r, mr1 = 0;
572
573 DBG(dev, "configure" NL);
574
575 if (!link) {
576 out_be32(&p->mr1, in_be32(&p->mr1)
577 | EMAC_MR1_FDE | EMAC_MR1_ILE);
578 udelay(100);
579 } else if (emac_reset(dev) < 0)
580 return -ETIMEDOUT;
581
582 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
583 tah_reset(dev->tah_dev);
584
585 DBG(dev, " link = %d duplex = %d, pause = %d, asym_pause = %d\n",
586 link, dev->phy.duplex, dev->phy.pause, dev->phy.asym_pause);
587
588 /* Default fifo sizes */
589 tx_size = dev->tx_fifo_size;
590 rx_size = dev->rx_fifo_size;
591
592 /* No link, force loopback */
593 if (!link)
594 mr1 = EMAC_MR1_FDE | EMAC_MR1_ILE;
595
596 /* Check for full duplex */
597 else if (dev->phy.duplex == DUPLEX_FULL)
598 mr1 |= EMAC_MR1_FDE | EMAC_MR1_MWSW_001;
599
600 /* Adjust fifo sizes, mr1 and timeouts based on link speed */
601 dev->stop_timeout = STOP_TIMEOUT_10;
602 switch (dev->phy.speed) {
603 case SPEED_1000:
604 if (emac_phy_gpcs(dev->phy.mode)) {
605 mr1 |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_MF_IPPA(
606 (dev->phy.gpcs_address != 0xffffffff) ?
607 dev->phy.gpcs_address : dev->phy.address);
608
609 /* Put some arbitrary OUI, Manuf & Rev IDs so we can
610 * identify this GPCS PHY later.
611 */
612 out_be32(&p->u1.emac4.ipcr, 0xdeadbeef);
613 } else
614 mr1 |= EMAC_MR1_MF_1000;
615
616 /* Extended fifo sizes */
617 tx_size = dev->tx_fifo_size_gige;
618 rx_size = dev->rx_fifo_size_gige;
619
620 if (dev->ndev->mtu > ETH_DATA_LEN) {
621 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
622 mr1 |= EMAC4_MR1_JPSM;
623 else
624 mr1 |= EMAC_MR1_JPSM;
625 dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO;
626 } else
627 dev->stop_timeout = STOP_TIMEOUT_1000;
628 break;
629 case SPEED_100:
630 mr1 |= EMAC_MR1_MF_100;
631 dev->stop_timeout = STOP_TIMEOUT_100;
632 break;
633 default: /* make gcc happy */
634 break;
635 }
636
637 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
638 rgmii_set_speed(dev->rgmii_dev, dev->rgmii_port,
639 dev->phy.speed);
640 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
641 zmii_set_speed(dev->zmii_dev, dev->zmii_port, dev->phy.speed);
642
643 /* on 40x erratum forces us to NOT use integrated flow control,
644 * let's hope it works on 44x ;)
645 */
646 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x) &&
647 dev->phy.duplex == DUPLEX_FULL) {
648 if (dev->phy.pause)
649 mr1 |= EMAC_MR1_EIFC | EMAC_MR1_APP;
650 else if (dev->phy.asym_pause)
651 mr1 |= EMAC_MR1_APP;
652 }
653
654 /* Add base settings & fifo sizes & program MR1 */
655 mr1 |= emac_calc_base_mr1(dev, tx_size, rx_size);
656 out_be32(&p->mr1, mr1);
657
658 /* Set individual MAC address */
659 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
660 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
661 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
662 ndev->dev_addr[5]);
663
664 /* VLAN Tag Protocol ID */
665 out_be32(&p->vtpid, 0x8100);
666
667 /* Receive mode register */
668 r = emac_iff2rmr(ndev);
669 if (r & EMAC_RMR_MAE)
670 emac_hash_mc(dev);
671 out_be32(&p->rmr, r);
672
673 /* FIFOs thresholds */
674 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
675 r = EMAC4_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
676 tx_size / 2 / dev->fifo_entry_size);
677 else
678 r = EMAC_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
679 tx_size / 2 / dev->fifo_entry_size);
680 out_be32(&p->tmr1, r);
681 out_be32(&p->trtr, emac_calc_trtr(dev, tx_size / 2));
682
683 /* PAUSE frame is sent when RX FIFO reaches its high-water mark,
684 there should be still enough space in FIFO to allow the our link
685 partner time to process this frame and also time to send PAUSE
686 frame itself.
687
688 Here is the worst case scenario for the RX FIFO "headroom"
689 (from "The Switch Book") (100Mbps, without preamble, inter-frame gap):
690
691 1) One maximum-length frame on TX 1522 bytes
692 2) One PAUSE frame time 64 bytes
693 3) PAUSE frame decode time allowance 64 bytes
694 4) One maximum-length frame on RX 1522 bytes
695 5) Round-trip propagation delay of the link (100Mb) 15 bytes
696 ----------
697 3187 bytes
698
699 I chose to set high-water mark to RX_FIFO_SIZE / 4 (1024 bytes)
700 low-water mark to RX_FIFO_SIZE / 8 (512 bytes)
701 */
702 r = emac_calc_rwmr(dev, rx_size / 8 / dev->fifo_entry_size,
703 rx_size / 4 / dev->fifo_entry_size);
704 out_be32(&p->rwmr, r);
705
706 /* Set PAUSE timer to the maximum */
707 out_be32(&p->ptr, 0xffff);
708
709 /* IRQ sources */
710 r = EMAC_ISR_OVR | EMAC_ISR_BP | EMAC_ISR_SE |
711 EMAC_ISR_ALE | EMAC_ISR_BFCS | EMAC_ISR_PTLE | EMAC_ISR_ORE |
712 EMAC_ISR_IRE | EMAC_ISR_TE;
713 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
714 r |= EMAC4_ISR_TXPE | EMAC4_ISR_RXPE /* | EMAC4_ISR_TXUE |
715 EMAC4_ISR_RXOE | */;
716 out_be32(&p->iser, r);
717
718 /* We need to take GPCS PHY out of isolate mode after EMAC reset */
719 if (emac_phy_gpcs(dev->phy.mode)) {
720 if (dev->phy.gpcs_address != 0xffffffff)
721 emac_mii_reset_gpcs(&dev->phy);
722 else
723 emac_mii_reset_phy(&dev->phy);
724 }
725
726 return 0;
727}
728
729static void emac_reinitialize(struct emac_instance *dev)
730{
731 DBG(dev, "reinitialize" NL);
732
733 emac_netif_stop(dev);
734 if (!emac_configure(dev)) {
735 emac_tx_enable(dev);
736 emac_rx_enable(dev);
737 }
738 emac_netif_start(dev);
739}
740
741static void emac_full_tx_reset(struct emac_instance *dev)
742{
743 DBG(dev, "full_tx_reset" NL);
744
745 emac_tx_disable(dev);
746 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
747 emac_clean_tx_ring(dev);
748 dev->tx_cnt = dev->tx_slot = dev->ack_slot = 0;
749
750 emac_configure(dev);
751
752 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
753 emac_tx_enable(dev);
754 emac_rx_enable(dev);
755}
756
757static void emac_reset_work(struct work_struct *work)
758{
759 struct emac_instance *dev = container_of(work, struct emac_instance, reset_work);
760
761 DBG(dev, "reset_work" NL);
762
763 mutex_lock(&dev->link_lock);
764 if (dev->opened) {
765 emac_netif_stop(dev);
766 emac_full_tx_reset(dev);
767 emac_netif_start(dev);
768 }
769 mutex_unlock(&dev->link_lock);
770}
771
772static void emac_tx_timeout(struct net_device *ndev, unsigned int txqueue)
773{
774 struct emac_instance *dev = netdev_priv(ndev);
775
776 DBG(dev, "tx_timeout" NL);
777
778 schedule_work(&dev->reset_work);
779}
780
781
782static inline int emac_phy_done(struct emac_instance *dev, u32 stacr)
783{
784 int done = !!(stacr & EMAC_STACR_OC);
785
786 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
787 done = !done;
788
789 return done;
790};
791
792static int __emac_mdio_read(struct emac_instance *dev, u8 id, u8 reg)
793{
794 struct emac_regs __iomem *p = dev->emacp;
795 u32 r = 0;
796 int n, err = -ETIMEDOUT;
797
798 mutex_lock(&dev->mdio_lock);
799
800 DBG2(dev, "mdio_read(%02x,%02x)" NL, id, reg);
801
802 /* Enable proper MDIO port */
803 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
804 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
805 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
806 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
807
808 /* Wait for management interface to become idle */
809 n = 20;
810 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
811 udelay(1);
812 if (!--n) {
813 DBG2(dev, " -> timeout wait idle\n");
814 goto bail;
815 }
816 }
817
818 /* Issue read command */
819 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
820 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
821 else
822 r = EMAC_STACR_BASE(dev->opb_bus_freq);
823 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
824 r |= EMAC_STACR_OC;
825 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
826 r |= EMACX_STACR_STAC_READ;
827 else
828 r |= EMAC_STACR_STAC_READ;
829 r |= (reg & EMAC_STACR_PRA_MASK)
830 | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT);
831 out_be32(&p->stacr, r);
832
833 /* Wait for read to complete */
834 n = 200;
835 while (!emac_phy_done(dev, (r = in_be32(&p->stacr)))) {
836 udelay(1);
837 if (!--n) {
838 DBG2(dev, " -> timeout wait complete\n");
839 goto bail;
840 }
841 }
842
843 if (unlikely(r & EMAC_STACR_PHYE)) {
844 DBG(dev, "mdio_read(%02x, %02x) failed" NL, id, reg);
845 err = -EREMOTEIO;
846 goto bail;
847 }
848
849 r = ((r >> EMAC_STACR_PHYD_SHIFT) & EMAC_STACR_PHYD_MASK);
850
851 DBG2(dev, "mdio_read -> %04x" NL, r);
852 err = 0;
853 bail:
854 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
855 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
856 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
857 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
858 mutex_unlock(&dev->mdio_lock);
859
860 return err == 0 ? r : err;
861}
862
863static void __emac_mdio_write(struct emac_instance *dev, u8 id, u8 reg,
864 u16 val)
865{
866 struct emac_regs __iomem *p = dev->emacp;
867 u32 r = 0;
868 int n;
869
870 mutex_lock(&dev->mdio_lock);
871
872 DBG2(dev, "mdio_write(%02x,%02x,%04x)" NL, id, reg, val);
873
874 /* Enable proper MDIO port */
875 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
876 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
877 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
878 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
879
880 /* Wait for management interface to be idle */
881 n = 20;
882 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
883 udelay(1);
884 if (!--n) {
885 DBG2(dev, " -> timeout wait idle\n");
886 goto bail;
887 }
888 }
889
890 /* Issue write command */
891 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
892 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
893 else
894 r = EMAC_STACR_BASE(dev->opb_bus_freq);
895 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
896 r |= EMAC_STACR_OC;
897 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
898 r |= EMACX_STACR_STAC_WRITE;
899 else
900 r |= EMAC_STACR_STAC_WRITE;
901 r |= (reg & EMAC_STACR_PRA_MASK) |
902 ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) |
903 (val << EMAC_STACR_PHYD_SHIFT);
904 out_be32(&p->stacr, r);
905
906 /* Wait for write to complete */
907 n = 200;
908 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
909 udelay(1);
910 if (!--n) {
911 DBG2(dev, " -> timeout wait complete\n");
912 goto bail;
913 }
914 }
915 bail:
916 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
917 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
918 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
919 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
920 mutex_unlock(&dev->mdio_lock);
921}
922
923static int emac_mdio_read(struct net_device *ndev, int id, int reg)
924{
925 struct emac_instance *dev = netdev_priv(ndev);
926 int res;
927
928 res = __emac_mdio_read((dev->mdio_instance &&
929 dev->phy.gpcs_address != id) ?
930 dev->mdio_instance : dev,
931 (u8) id, (u8) reg);
932 return res;
933}
934
935static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val)
936{
937 struct emac_instance *dev = netdev_priv(ndev);
938
939 __emac_mdio_write((dev->mdio_instance &&
940 dev->phy.gpcs_address != id) ?
941 dev->mdio_instance : dev,
942 (u8) id, (u8) reg, (u16) val);
943}
944
945/* Tx lock BH */
946static void __emac_set_multicast_list(struct emac_instance *dev)
947{
948 struct emac_regs __iomem *p = dev->emacp;
949 u32 rmr = emac_iff2rmr(dev->ndev);
950
951 DBG(dev, "__multicast %08x" NL, rmr);
952
953 /* I decided to relax register access rules here to avoid
954 * full EMAC reset.
955 *
956 * There is a real problem with EMAC4 core if we use MWSW_001 bit
957 * in MR1 register and do a full EMAC reset.
958 * One TX BD status update is delayed and, after EMAC reset, it
959 * never happens, resulting in TX hung (it'll be recovered by TX
960 * timeout handler eventually, but this is just gross).
961 * So we either have to do full TX reset or try to cheat here :)
962 *
963 * The only required change is to RX mode register, so I *think* all
964 * we need is just to stop RX channel. This seems to work on all
965 * tested SoCs. --ebs
966 *
967 */
968 dev->mcast_pending = 0;
969 emac_rx_disable(dev);
970 if (rmr & EMAC_RMR_MAE)
971 emac_hash_mc(dev);
972 out_be32(&p->rmr, rmr);
973 emac_rx_enable(dev);
974}
975
976/* Tx lock BH */
977static void emac_set_multicast_list(struct net_device *ndev)
978{
979 struct emac_instance *dev = netdev_priv(ndev);
980
981 DBG(dev, "multicast" NL);
982
983 BUG_ON(!netif_running(dev->ndev));
984
985 if (dev->no_mcast) {
986 dev->mcast_pending = 1;
987 return;
988 }
989
990 mutex_lock(&dev->link_lock);
991 __emac_set_multicast_list(dev);
992 mutex_unlock(&dev->link_lock);
993}
994
995static int emac_set_mac_address(struct net_device *ndev, void *sa)
996{
997 struct emac_instance *dev = netdev_priv(ndev);
998 struct sockaddr *addr = sa;
999 struct emac_regs __iomem *p = dev->emacp;
1000
1001 if (!is_valid_ether_addr(addr->sa_data))
1002 return -EADDRNOTAVAIL;
1003
1004 mutex_lock(&dev->link_lock);
1005
1006 eth_hw_addr_set(ndev, addr->sa_data);
1007
1008 emac_rx_disable(dev);
1009 emac_tx_disable(dev);
1010 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
1011 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
1012 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
1013 ndev->dev_addr[5]);
1014 emac_tx_enable(dev);
1015 emac_rx_enable(dev);
1016
1017 mutex_unlock(&dev->link_lock);
1018
1019 return 0;
1020}
1021
1022static int emac_resize_rx_ring(struct emac_instance *dev, int new_mtu)
1023{
1024 int rx_sync_size = emac_rx_sync_size(new_mtu);
1025 int rx_skb_size = emac_rx_skb_size(new_mtu);
1026 int i, ret = 0;
1027 int mr1_jumbo_bit_change = 0;
1028
1029 mutex_lock(&dev->link_lock);
1030 emac_netif_stop(dev);
1031 emac_rx_disable(dev);
1032 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
1033
1034 if (dev->rx_sg_skb) {
1035 ++dev->estats.rx_dropped_resize;
1036 dev_kfree_skb(dev->rx_sg_skb);
1037 dev->rx_sg_skb = NULL;
1038 }
1039
1040 /* Make a first pass over RX ring and mark BDs ready, dropping
1041 * non-processed packets on the way. We need this as a separate pass
1042 * to simplify error recovery in the case of allocation failure later.
1043 */
1044 for (i = 0; i < NUM_RX_BUFF; ++i) {
1045 if (dev->rx_desc[i].ctrl & MAL_RX_CTRL_FIRST)
1046 ++dev->estats.rx_dropped_resize;
1047
1048 dev->rx_desc[i].data_len = 0;
1049 dev->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY |
1050 (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1051 }
1052
1053 /* Reallocate RX ring only if bigger skb buffers are required */
1054 if (rx_skb_size <= dev->rx_skb_size)
1055 goto skip;
1056
1057 /* Second pass, allocate new skbs */
1058 for (i = 0; i < NUM_RX_BUFF; ++i) {
1059 struct sk_buff *skb;
1060
1061 skb = netdev_alloc_skb_ip_align(dev->ndev, rx_skb_size);
1062 if (!skb) {
1063 ret = -ENOMEM;
1064 goto oom;
1065 }
1066
1067 BUG_ON(!dev->rx_skb[i]);
1068 dev_kfree_skb(dev->rx_skb[i]);
1069
1070 dev->rx_desc[i].data_ptr =
1071 dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN,
1072 rx_sync_size, DMA_FROM_DEVICE)
1073 + NET_IP_ALIGN;
1074 dev->rx_skb[i] = skb;
1075 }
1076 skip:
1077 /* Check if we need to change "Jumbo" bit in MR1 */
1078 if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) {
1079 mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) ||
1080 (dev->ndev->mtu > ETH_DATA_LEN);
1081 } else {
1082 mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) ^
1083 (dev->ndev->mtu > ETH_DATA_LEN);
1084 }
1085
1086 if (mr1_jumbo_bit_change) {
1087 /* This is to prevent starting RX channel in emac_rx_enable() */
1088 set_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1089
1090 WRITE_ONCE(dev->ndev->mtu, new_mtu);
1091 emac_full_tx_reset(dev);
1092 }
1093
1094 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(new_mtu));
1095 oom:
1096 /* Restart RX */
1097 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1098 dev->rx_slot = 0;
1099 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1100 emac_rx_enable(dev);
1101 emac_netif_start(dev);
1102 mutex_unlock(&dev->link_lock);
1103
1104 return ret;
1105}
1106
1107/* Process ctx, rtnl_lock semaphore */
1108static int emac_change_mtu(struct net_device *ndev, int new_mtu)
1109{
1110 struct emac_instance *dev = netdev_priv(ndev);
1111 int ret = 0;
1112
1113 DBG(dev, "change_mtu(%d)" NL, new_mtu);
1114
1115 if (netif_running(ndev)) {
1116 /* Check if we really need to reinitialize RX ring */
1117 if (emac_rx_skb_size(ndev->mtu) != emac_rx_skb_size(new_mtu))
1118 ret = emac_resize_rx_ring(dev, new_mtu);
1119 }
1120
1121 if (!ret) {
1122 WRITE_ONCE(ndev->mtu, new_mtu);
1123 dev->rx_skb_size = emac_rx_skb_size(new_mtu);
1124 dev->rx_sync_size = emac_rx_sync_size(new_mtu);
1125 }
1126
1127 return ret;
1128}
1129
1130static void emac_clean_tx_ring(struct emac_instance *dev)
1131{
1132 int i;
1133
1134 for (i = 0; i < NUM_TX_BUFF; ++i) {
1135 if (dev->tx_skb[i]) {
1136 dev_kfree_skb(dev->tx_skb[i]);
1137 dev->tx_skb[i] = NULL;
1138 if (dev->tx_desc[i].ctrl & MAL_TX_CTRL_READY)
1139 ++dev->estats.tx_dropped;
1140 }
1141 dev->tx_desc[i].ctrl = 0;
1142 dev->tx_desc[i].data_ptr = 0;
1143 }
1144}
1145
1146static void emac_clean_rx_ring(struct emac_instance *dev)
1147{
1148 int i;
1149
1150 for (i = 0; i < NUM_RX_BUFF; ++i)
1151 if (dev->rx_skb[i]) {
1152 dev->rx_desc[i].ctrl = 0;
1153 dev_kfree_skb(dev->rx_skb[i]);
1154 dev->rx_skb[i] = NULL;
1155 dev->rx_desc[i].data_ptr = 0;
1156 }
1157
1158 if (dev->rx_sg_skb) {
1159 dev_kfree_skb(dev->rx_sg_skb);
1160 dev->rx_sg_skb = NULL;
1161 }
1162}
1163
1164static int
1165__emac_prepare_rx_skb(struct sk_buff *skb, struct emac_instance *dev, int slot)
1166{
1167 if (unlikely(!skb))
1168 return -ENOMEM;
1169
1170 dev->rx_skb[slot] = skb;
1171 dev->rx_desc[slot].data_len = 0;
1172
1173 dev->rx_desc[slot].data_ptr =
1174 dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN,
1175 dev->rx_sync_size, DMA_FROM_DEVICE) + NET_IP_ALIGN;
1176 wmb();
1177 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1178 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1179
1180 return 0;
1181}
1182
1183static int
1184emac_alloc_rx_skb(struct emac_instance *dev, int slot)
1185{
1186 struct sk_buff *skb;
1187
1188 skb = __netdev_alloc_skb_ip_align(dev->ndev, dev->rx_skb_size,
1189 GFP_KERNEL);
1190
1191 return __emac_prepare_rx_skb(skb, dev, slot);
1192}
1193
1194static int
1195emac_alloc_rx_skb_napi(struct emac_instance *dev, int slot)
1196{
1197 struct sk_buff *skb;
1198
1199 skb = napi_alloc_skb(&dev->mal->napi, dev->rx_skb_size);
1200
1201 return __emac_prepare_rx_skb(skb, dev, slot);
1202}
1203
1204static void emac_print_link_status(struct emac_instance *dev)
1205{
1206 if (netif_carrier_ok(dev->ndev))
1207 printk(KERN_INFO "%s: link is up, %d %s%s\n",
1208 dev->ndev->name, dev->phy.speed,
1209 dev->phy.duplex == DUPLEX_FULL ? "FDX" : "HDX",
1210 dev->phy.pause ? ", pause enabled" :
1211 dev->phy.asym_pause ? ", asymmetric pause enabled" : "");
1212 else
1213 printk(KERN_INFO "%s: link is down\n", dev->ndev->name);
1214}
1215
1216/* Process ctx, rtnl_lock semaphore */
1217static int emac_open(struct net_device *ndev)
1218{
1219 struct emac_instance *dev = netdev_priv(ndev);
1220 int i;
1221
1222 DBG(dev, "open" NL);
1223
1224 /* Allocate RX ring */
1225 for (i = 0; i < NUM_RX_BUFF; ++i)
1226 if (emac_alloc_rx_skb(dev, i)) {
1227 printk(KERN_ERR "%s: failed to allocate RX ring\n",
1228 ndev->name);
1229 goto oom;
1230 }
1231
1232 dev->tx_cnt = dev->tx_slot = dev->ack_slot = dev->rx_slot = 0;
1233 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1234 dev->rx_sg_skb = NULL;
1235
1236 mutex_lock(&dev->link_lock);
1237 dev->opened = 1;
1238
1239 /* Start PHY polling now.
1240 */
1241 if (dev->phy.address >= 0) {
1242 int link_poll_interval;
1243 if (dev->phy.def->ops->poll_link(&dev->phy)) {
1244 dev->phy.def->ops->read_link(&dev->phy);
1245 emac_rx_clk_default(dev);
1246 netif_carrier_on(dev->ndev);
1247 link_poll_interval = PHY_POLL_LINK_ON;
1248 } else {
1249 emac_rx_clk_tx(dev);
1250 netif_carrier_off(dev->ndev);
1251 link_poll_interval = PHY_POLL_LINK_OFF;
1252 }
1253 dev->link_polling = 1;
1254 wmb();
1255 schedule_delayed_work(&dev->link_work, link_poll_interval);
1256 emac_print_link_status(dev);
1257 } else
1258 netif_carrier_on(dev->ndev);
1259
1260 /* Required for Pause packet support in EMAC */
1261 dev_mc_add_global(ndev, default_mcast_addr);
1262
1263 emac_configure(dev);
1264 mal_poll_add(dev->mal, &dev->commac);
1265 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
1266 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(ndev->mtu));
1267 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1268 emac_tx_enable(dev);
1269 emac_rx_enable(dev);
1270 emac_netif_start(dev);
1271
1272 mutex_unlock(&dev->link_lock);
1273
1274 return 0;
1275 oom:
1276 emac_clean_rx_ring(dev);
1277 return -ENOMEM;
1278}
1279
1280/* BHs disabled */
1281#if 0
1282static int emac_link_differs(struct emac_instance *dev)
1283{
1284 u32 r = in_be32(&dev->emacp->mr1);
1285
1286 int duplex = r & EMAC_MR1_FDE ? DUPLEX_FULL : DUPLEX_HALF;
1287 int speed, pause, asym_pause;
1288
1289 if (r & EMAC_MR1_MF_1000)
1290 speed = SPEED_1000;
1291 else if (r & EMAC_MR1_MF_100)
1292 speed = SPEED_100;
1293 else
1294 speed = SPEED_10;
1295
1296 switch (r & (EMAC_MR1_EIFC | EMAC_MR1_APP)) {
1297 case (EMAC_MR1_EIFC | EMAC_MR1_APP):
1298 pause = 1;
1299 asym_pause = 0;
1300 break;
1301 case EMAC_MR1_APP:
1302 pause = 0;
1303 asym_pause = 1;
1304 break;
1305 default:
1306 pause = asym_pause = 0;
1307 }
1308 return speed != dev->phy.speed || duplex != dev->phy.duplex ||
1309 pause != dev->phy.pause || asym_pause != dev->phy.asym_pause;
1310}
1311#endif
1312
1313static void emac_link_timer(struct work_struct *work)
1314{
1315 struct emac_instance *dev =
1316 container_of(to_delayed_work(work),
1317 struct emac_instance, link_work);
1318 int link_poll_interval;
1319
1320 mutex_lock(&dev->link_lock);
1321 DBG2(dev, "link timer" NL);
1322
1323 if (!dev->opened)
1324 goto bail;
1325
1326 if (dev->phy.def->ops->poll_link(&dev->phy)) {
1327 if (!netif_carrier_ok(dev->ndev)) {
1328 emac_rx_clk_default(dev);
1329 /* Get new link parameters */
1330 dev->phy.def->ops->read_link(&dev->phy);
1331
1332 netif_carrier_on(dev->ndev);
1333 emac_netif_stop(dev);
1334 emac_full_tx_reset(dev);
1335 emac_netif_start(dev);
1336 emac_print_link_status(dev);
1337 }
1338 link_poll_interval = PHY_POLL_LINK_ON;
1339 } else {
1340 if (netif_carrier_ok(dev->ndev)) {
1341 emac_rx_clk_tx(dev);
1342 netif_carrier_off(dev->ndev);
1343 netif_tx_disable(dev->ndev);
1344 emac_reinitialize(dev);
1345 emac_print_link_status(dev);
1346 }
1347 link_poll_interval = PHY_POLL_LINK_OFF;
1348 }
1349 schedule_delayed_work(&dev->link_work, link_poll_interval);
1350 bail:
1351 mutex_unlock(&dev->link_lock);
1352}
1353
1354static void emac_force_link_update(struct emac_instance *dev)
1355{
1356 netif_carrier_off(dev->ndev);
1357 smp_rmb();
1358 if (dev->link_polling) {
1359 cancel_delayed_work_sync(&dev->link_work);
1360 if (dev->link_polling)
1361 schedule_delayed_work(&dev->link_work, PHY_POLL_LINK_OFF);
1362 }
1363}
1364
1365/* Process ctx, rtnl_lock semaphore */
1366static int emac_close(struct net_device *ndev)
1367{
1368 struct emac_instance *dev = netdev_priv(ndev);
1369
1370 DBG(dev, "close" NL);
1371
1372 if (dev->phy.address >= 0) {
1373 dev->link_polling = 0;
1374 cancel_delayed_work_sync(&dev->link_work);
1375 }
1376 mutex_lock(&dev->link_lock);
1377 emac_netif_stop(dev);
1378 dev->opened = 0;
1379 mutex_unlock(&dev->link_lock);
1380
1381 emac_rx_disable(dev);
1382 emac_tx_disable(dev);
1383 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
1384 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
1385 mal_poll_del(dev->mal, &dev->commac);
1386
1387 emac_clean_tx_ring(dev);
1388 emac_clean_rx_ring(dev);
1389
1390 netif_carrier_off(ndev);
1391
1392 return 0;
1393}
1394
1395static inline u16 emac_tx_csum(struct emac_instance *dev,
1396 struct sk_buff *skb)
1397{
1398 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
1399 (skb->ip_summed == CHECKSUM_PARTIAL)) {
1400 ++dev->stats.tx_packets_csum;
1401 return EMAC_TX_CTRL_TAH_CSUM;
1402 }
1403 return 0;
1404}
1405
1406static inline netdev_tx_t emac_xmit_finish(struct emac_instance *dev, int len)
1407{
1408 struct emac_regs __iomem *p = dev->emacp;
1409 struct net_device *ndev = dev->ndev;
1410
1411 /* Send the packet out. If the if makes a significant perf
1412 * difference, then we can store the TMR0 value in "dev"
1413 * instead
1414 */
1415 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
1416 out_be32(&p->tmr0, EMAC4_TMR0_XMIT);
1417 else
1418 out_be32(&p->tmr0, EMAC_TMR0_XMIT);
1419
1420 if (unlikely(++dev->tx_cnt == NUM_TX_BUFF)) {
1421 netif_stop_queue(ndev);
1422 DBG2(dev, "stopped TX queue" NL);
1423 }
1424
1425 netif_trans_update(ndev);
1426 ++dev->stats.tx_packets;
1427 dev->stats.tx_bytes += len;
1428
1429 return NETDEV_TX_OK;
1430}
1431
1432/* Tx lock BH */
1433static netdev_tx_t emac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1434{
1435 struct emac_instance *dev = netdev_priv(ndev);
1436 unsigned int len = skb->len;
1437 int slot;
1438
1439 u16 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1440 MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb);
1441
1442 slot = dev->tx_slot++;
1443 if (dev->tx_slot == NUM_TX_BUFF) {
1444 dev->tx_slot = 0;
1445 ctrl |= MAL_TX_CTRL_WRAP;
1446 }
1447
1448 DBG2(dev, "xmit(%u) %d" NL, len, slot);
1449
1450 dev->tx_skb[slot] = skb;
1451 dev->tx_desc[slot].data_ptr = dma_map_single(&dev->ofdev->dev,
1452 skb->data, len,
1453 DMA_TO_DEVICE);
1454 dev->tx_desc[slot].data_len = (u16) len;
1455 wmb();
1456 dev->tx_desc[slot].ctrl = ctrl;
1457
1458 return emac_xmit_finish(dev, len);
1459}
1460
1461static inline int emac_xmit_split(struct emac_instance *dev, int slot,
1462 u32 pd, int len, int last, u16 base_ctrl)
1463{
1464 while (1) {
1465 u16 ctrl = base_ctrl;
1466 int chunk = min(len, MAL_MAX_TX_SIZE);
1467 len -= chunk;
1468
1469 slot = (slot + 1) % NUM_TX_BUFF;
1470
1471 if (last && !len)
1472 ctrl |= MAL_TX_CTRL_LAST;
1473 if (slot == NUM_TX_BUFF - 1)
1474 ctrl |= MAL_TX_CTRL_WRAP;
1475
1476 dev->tx_skb[slot] = NULL;
1477 dev->tx_desc[slot].data_ptr = pd;
1478 dev->tx_desc[slot].data_len = (u16) chunk;
1479 dev->tx_desc[slot].ctrl = ctrl;
1480 ++dev->tx_cnt;
1481
1482 if (!len)
1483 break;
1484
1485 pd += chunk;
1486 }
1487 return slot;
1488}
1489
1490/* Tx lock BH disabled (SG version for TAH equipped EMACs) */
1491static netdev_tx_t
1492emac_start_xmit_sg(struct sk_buff *skb, struct net_device *ndev)
1493{
1494 struct emac_instance *dev = netdev_priv(ndev);
1495 int nr_frags = skb_shinfo(skb)->nr_frags;
1496 int len = skb->len, chunk;
1497 int slot, i;
1498 u16 ctrl;
1499 u32 pd;
1500
1501 /* This is common "fast" path */
1502 if (likely(!nr_frags && len <= MAL_MAX_TX_SIZE))
1503 return emac_start_xmit(skb, ndev);
1504
1505 len -= skb->data_len;
1506
1507 /* Note, this is only an *estimation*, we can still run out of empty
1508 * slots because of the additional fragmentation into
1509 * MAL_MAX_TX_SIZE-sized chunks
1510 */
1511 if (unlikely(dev->tx_cnt + nr_frags + mal_tx_chunks(len) > NUM_TX_BUFF))
1512 goto stop_queue;
1513
1514 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1515 emac_tx_csum(dev, skb);
1516 slot = dev->tx_slot;
1517
1518 /* skb data */
1519 dev->tx_skb[slot] = NULL;
1520 chunk = min(len, MAL_MAX_TX_SIZE);
1521 dev->tx_desc[slot].data_ptr = pd =
1522 dma_map_single(&dev->ofdev->dev, skb->data, len, DMA_TO_DEVICE);
1523 dev->tx_desc[slot].data_len = (u16) chunk;
1524 len -= chunk;
1525 if (unlikely(len))
1526 slot = emac_xmit_split(dev, slot, pd + chunk, len, !nr_frags,
1527 ctrl);
1528 /* skb fragments */
1529 for (i = 0; i < nr_frags; ++i) {
1530 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1531 len = skb_frag_size(frag);
1532
1533 if (unlikely(dev->tx_cnt + mal_tx_chunks(len) >= NUM_TX_BUFF))
1534 goto undo_frame;
1535
1536 pd = skb_frag_dma_map(&dev->ofdev->dev, frag, 0, len,
1537 DMA_TO_DEVICE);
1538
1539 slot = emac_xmit_split(dev, slot, pd, len, i == nr_frags - 1,
1540 ctrl);
1541 }
1542
1543 DBG2(dev, "xmit_sg(%u) %d - %d" NL, skb->len, dev->tx_slot, slot);
1544
1545 /* Attach skb to the last slot so we don't release it too early */
1546 dev->tx_skb[slot] = skb;
1547
1548 /* Send the packet out */
1549 if (dev->tx_slot == NUM_TX_BUFF - 1)
1550 ctrl |= MAL_TX_CTRL_WRAP;
1551 wmb();
1552 dev->tx_desc[dev->tx_slot].ctrl = ctrl;
1553 dev->tx_slot = (slot + 1) % NUM_TX_BUFF;
1554
1555 return emac_xmit_finish(dev, skb->len);
1556
1557 undo_frame:
1558 /* Well, too bad. Our previous estimation was overly optimistic.
1559 * Undo everything.
1560 */
1561 while (slot != dev->tx_slot) {
1562 dev->tx_desc[slot].ctrl = 0;
1563 --dev->tx_cnt;
1564 if (--slot < 0)
1565 slot = NUM_TX_BUFF - 1;
1566 }
1567 ++dev->estats.tx_undo;
1568
1569 stop_queue:
1570 netif_stop_queue(ndev);
1571 DBG2(dev, "stopped TX queue" NL);
1572 return NETDEV_TX_BUSY;
1573}
1574
1575/* Tx lock BHs */
1576static void emac_parse_tx_error(struct emac_instance *dev, u16 ctrl)
1577{
1578 struct emac_error_stats *st = &dev->estats;
1579
1580 DBG(dev, "BD TX error %04x" NL, ctrl);
1581
1582 ++st->tx_bd_errors;
1583 if (ctrl & EMAC_TX_ST_BFCS)
1584 ++st->tx_bd_bad_fcs;
1585 if (ctrl & EMAC_TX_ST_LCS)
1586 ++st->tx_bd_carrier_loss;
1587 if (ctrl & EMAC_TX_ST_ED)
1588 ++st->tx_bd_excessive_deferral;
1589 if (ctrl & EMAC_TX_ST_EC)
1590 ++st->tx_bd_excessive_collisions;
1591 if (ctrl & EMAC_TX_ST_LC)
1592 ++st->tx_bd_late_collision;
1593 if (ctrl & EMAC_TX_ST_MC)
1594 ++st->tx_bd_multple_collisions;
1595 if (ctrl & EMAC_TX_ST_SC)
1596 ++st->tx_bd_single_collision;
1597 if (ctrl & EMAC_TX_ST_UR)
1598 ++st->tx_bd_underrun;
1599 if (ctrl & EMAC_TX_ST_SQE)
1600 ++st->tx_bd_sqe;
1601}
1602
1603static void emac_poll_tx(void *param)
1604{
1605 struct emac_instance *dev = param;
1606 u32 bad_mask;
1607
1608 DBG2(dev, "poll_tx, %d %d" NL, dev->tx_cnt, dev->ack_slot);
1609
1610 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
1611 bad_mask = EMAC_IS_BAD_TX_TAH;
1612 else
1613 bad_mask = EMAC_IS_BAD_TX;
1614
1615 netif_tx_lock_bh(dev->ndev);
1616 if (dev->tx_cnt) {
1617 u16 ctrl;
1618 int slot = dev->ack_slot, n = 0;
1619 again:
1620 ctrl = dev->tx_desc[slot].ctrl;
1621 if (!(ctrl & MAL_TX_CTRL_READY)) {
1622 struct sk_buff *skb = dev->tx_skb[slot];
1623 ++n;
1624
1625 if (skb) {
1626 dev_kfree_skb(skb);
1627 dev->tx_skb[slot] = NULL;
1628 }
1629 slot = (slot + 1) % NUM_TX_BUFF;
1630
1631 if (unlikely(ctrl & bad_mask))
1632 emac_parse_tx_error(dev, ctrl);
1633
1634 if (--dev->tx_cnt)
1635 goto again;
1636 }
1637 if (n) {
1638 dev->ack_slot = slot;
1639 if (netif_queue_stopped(dev->ndev) &&
1640 dev->tx_cnt < EMAC_TX_WAKEUP_THRESH)
1641 netif_wake_queue(dev->ndev);
1642
1643 DBG2(dev, "tx %d pkts" NL, n);
1644 }
1645 }
1646 netif_tx_unlock_bh(dev->ndev);
1647}
1648
1649static inline void emac_recycle_rx_skb(struct emac_instance *dev, int slot,
1650 int len)
1651{
1652 struct sk_buff *skb = dev->rx_skb[slot];
1653
1654 DBG2(dev, "recycle %d %d" NL, slot, len);
1655
1656 if (len)
1657 dma_map_single(&dev->ofdev->dev, skb->data - NET_IP_ALIGN,
1658 SKB_DATA_ALIGN(len + NET_IP_ALIGN),
1659 DMA_FROM_DEVICE);
1660
1661 dev->rx_desc[slot].data_len = 0;
1662 wmb();
1663 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1664 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1665}
1666
1667static void emac_parse_rx_error(struct emac_instance *dev, u16 ctrl)
1668{
1669 struct emac_error_stats *st = &dev->estats;
1670
1671 DBG(dev, "BD RX error %04x" NL, ctrl);
1672
1673 ++st->rx_bd_errors;
1674 if (ctrl & EMAC_RX_ST_OE)
1675 ++st->rx_bd_overrun;
1676 if (ctrl & EMAC_RX_ST_BP)
1677 ++st->rx_bd_bad_packet;
1678 if (ctrl & EMAC_RX_ST_RP)
1679 ++st->rx_bd_runt_packet;
1680 if (ctrl & EMAC_RX_ST_SE)
1681 ++st->rx_bd_short_event;
1682 if (ctrl & EMAC_RX_ST_AE)
1683 ++st->rx_bd_alignment_error;
1684 if (ctrl & EMAC_RX_ST_BFCS)
1685 ++st->rx_bd_bad_fcs;
1686 if (ctrl & EMAC_RX_ST_PTL)
1687 ++st->rx_bd_packet_too_long;
1688 if (ctrl & EMAC_RX_ST_ORE)
1689 ++st->rx_bd_out_of_range;
1690 if (ctrl & EMAC_RX_ST_IRE)
1691 ++st->rx_bd_in_range;
1692}
1693
1694static inline void emac_rx_csum(struct emac_instance *dev,
1695 struct sk_buff *skb, u16 ctrl)
1696{
1697#ifdef CONFIG_IBM_EMAC_TAH
1698 if (!ctrl && dev->tah_dev) {
1699 skb->ip_summed = CHECKSUM_UNNECESSARY;
1700 ++dev->stats.rx_packets_csum;
1701 }
1702#endif
1703}
1704
1705static inline int emac_rx_sg_append(struct emac_instance *dev, int slot)
1706{
1707 if (likely(dev->rx_sg_skb != NULL)) {
1708 int len = dev->rx_desc[slot].data_len;
1709 int tot_len = dev->rx_sg_skb->len + len;
1710
1711 if (unlikely(tot_len + NET_IP_ALIGN > dev->rx_skb_size)) {
1712 ++dev->estats.rx_dropped_mtu;
1713 dev_kfree_skb(dev->rx_sg_skb);
1714 dev->rx_sg_skb = NULL;
1715 } else {
1716 memcpy(skb_tail_pointer(dev->rx_sg_skb),
1717 dev->rx_skb[slot]->data, len);
1718 skb_put(dev->rx_sg_skb, len);
1719 emac_recycle_rx_skb(dev, slot, len);
1720 return 0;
1721 }
1722 }
1723 emac_recycle_rx_skb(dev, slot, 0);
1724 return -1;
1725}
1726
1727/* NAPI poll context */
1728static int emac_poll_rx(void *param, int budget)
1729{
1730 LIST_HEAD(rx_list);
1731 struct emac_instance *dev = param;
1732 int slot = dev->rx_slot, received = 0;
1733
1734 DBG2(dev, "poll_rx(%d)" NL, budget);
1735
1736 again:
1737 while (budget > 0) {
1738 int len;
1739 struct sk_buff *skb;
1740 u16 ctrl = dev->rx_desc[slot].ctrl;
1741
1742 if (ctrl & MAL_RX_CTRL_EMPTY)
1743 break;
1744
1745 skb = dev->rx_skb[slot];
1746 mb();
1747 len = dev->rx_desc[slot].data_len;
1748
1749 if (unlikely(!MAL_IS_SINGLE_RX(ctrl)))
1750 goto sg;
1751
1752 ctrl &= EMAC_BAD_RX_MASK;
1753 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1754 emac_parse_rx_error(dev, ctrl);
1755 ++dev->estats.rx_dropped_error;
1756 emac_recycle_rx_skb(dev, slot, 0);
1757 len = 0;
1758 goto next;
1759 }
1760
1761 if (len < ETH_HLEN) {
1762 ++dev->estats.rx_dropped_stack;
1763 emac_recycle_rx_skb(dev, slot, len);
1764 goto next;
1765 }
1766
1767 if (len && len < EMAC_RX_COPY_THRESH) {
1768 struct sk_buff *copy_skb;
1769
1770 copy_skb = napi_alloc_skb(&dev->mal->napi, len);
1771 if (unlikely(!copy_skb))
1772 goto oom;
1773
1774 memcpy(copy_skb->data - NET_IP_ALIGN,
1775 skb->data - NET_IP_ALIGN,
1776 len + NET_IP_ALIGN);
1777 emac_recycle_rx_skb(dev, slot, len);
1778 skb = copy_skb;
1779 } else if (unlikely(emac_alloc_rx_skb_napi(dev, slot)))
1780 goto oom;
1781
1782 skb_put(skb, len);
1783 push_packet:
1784 skb->protocol = eth_type_trans(skb, dev->ndev);
1785 emac_rx_csum(dev, skb, ctrl);
1786
1787 list_add_tail(&skb->list, &rx_list);
1788 next:
1789 ++dev->stats.rx_packets;
1790 skip:
1791 dev->stats.rx_bytes += len;
1792 slot = (slot + 1) % NUM_RX_BUFF;
1793 --budget;
1794 ++received;
1795 continue;
1796 sg:
1797 if (ctrl & MAL_RX_CTRL_FIRST) {
1798 BUG_ON(dev->rx_sg_skb);
1799 if (unlikely(emac_alloc_rx_skb_napi(dev, slot))) {
1800 DBG(dev, "rx OOM %d" NL, slot);
1801 ++dev->estats.rx_dropped_oom;
1802 emac_recycle_rx_skb(dev, slot, 0);
1803 } else {
1804 dev->rx_sg_skb = skb;
1805 skb_put(skb, len);
1806 }
1807 } else if (!emac_rx_sg_append(dev, slot) &&
1808 (ctrl & MAL_RX_CTRL_LAST)) {
1809
1810 skb = dev->rx_sg_skb;
1811 dev->rx_sg_skb = NULL;
1812
1813 ctrl &= EMAC_BAD_RX_MASK;
1814 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1815 emac_parse_rx_error(dev, ctrl);
1816 ++dev->estats.rx_dropped_error;
1817 dev_kfree_skb(skb);
1818 len = 0;
1819 } else
1820 goto push_packet;
1821 }
1822 goto skip;
1823 oom:
1824 DBG(dev, "rx OOM %d" NL, slot);
1825 /* Drop the packet and recycle skb */
1826 ++dev->estats.rx_dropped_oom;
1827 emac_recycle_rx_skb(dev, slot, 0);
1828 goto next;
1829 }
1830
1831 netif_receive_skb_list(&rx_list);
1832
1833 if (received) {
1834 DBG2(dev, "rx %d BDs" NL, received);
1835 dev->rx_slot = slot;
1836 }
1837
1838 if (unlikely(budget && test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags))) {
1839 mb();
1840 if (!(dev->rx_desc[slot].ctrl & MAL_RX_CTRL_EMPTY)) {
1841 DBG2(dev, "rx restart" NL);
1842 received = 0;
1843 goto again;
1844 }
1845
1846 if (dev->rx_sg_skb) {
1847 DBG2(dev, "dropping partial rx packet" NL);
1848 ++dev->estats.rx_dropped_error;
1849 dev_kfree_skb(dev->rx_sg_skb);
1850 dev->rx_sg_skb = NULL;
1851 }
1852
1853 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1854 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1855 emac_rx_enable(dev);
1856 dev->rx_slot = 0;
1857 }
1858 return received;
1859}
1860
1861/* NAPI poll context */
1862static int emac_peek_rx(void *param)
1863{
1864 struct emac_instance *dev = param;
1865
1866 return !(dev->rx_desc[dev->rx_slot].ctrl & MAL_RX_CTRL_EMPTY);
1867}
1868
1869/* NAPI poll context */
1870static int emac_peek_rx_sg(void *param)
1871{
1872 struct emac_instance *dev = param;
1873
1874 int slot = dev->rx_slot;
1875 while (1) {
1876 u16 ctrl = dev->rx_desc[slot].ctrl;
1877 if (ctrl & MAL_RX_CTRL_EMPTY)
1878 return 0;
1879 else if (ctrl & MAL_RX_CTRL_LAST)
1880 return 1;
1881
1882 slot = (slot + 1) % NUM_RX_BUFF;
1883
1884 /* I'm just being paranoid here :) */
1885 if (unlikely(slot == dev->rx_slot))
1886 return 0;
1887 }
1888}
1889
1890/* Hard IRQ */
1891static void emac_rxde(void *param)
1892{
1893 struct emac_instance *dev = param;
1894
1895 ++dev->estats.rx_stopped;
1896 emac_rx_disable_async(dev);
1897}
1898
1899/* Hard IRQ */
1900static irqreturn_t emac_irq(int irq, void *dev_instance)
1901{
1902 struct emac_instance *dev = dev_instance;
1903 struct emac_regs __iomem *p = dev->emacp;
1904 struct emac_error_stats *st = &dev->estats;
1905 u32 isr;
1906
1907 spin_lock(&dev->lock);
1908
1909 isr = in_be32(&p->isr);
1910 out_be32(&p->isr, isr);
1911
1912 DBG(dev, "isr = %08x" NL, isr);
1913
1914 if (isr & EMAC4_ISR_TXPE)
1915 ++st->tx_parity;
1916 if (isr & EMAC4_ISR_RXPE)
1917 ++st->rx_parity;
1918 if (isr & EMAC4_ISR_TXUE)
1919 ++st->tx_underrun;
1920 if (isr & EMAC4_ISR_RXOE)
1921 ++st->rx_fifo_overrun;
1922 if (isr & EMAC_ISR_OVR)
1923 ++st->rx_overrun;
1924 if (isr & EMAC_ISR_BP)
1925 ++st->rx_bad_packet;
1926 if (isr & EMAC_ISR_RP)
1927 ++st->rx_runt_packet;
1928 if (isr & EMAC_ISR_SE)
1929 ++st->rx_short_event;
1930 if (isr & EMAC_ISR_ALE)
1931 ++st->rx_alignment_error;
1932 if (isr & EMAC_ISR_BFCS)
1933 ++st->rx_bad_fcs;
1934 if (isr & EMAC_ISR_PTLE)
1935 ++st->rx_packet_too_long;
1936 if (isr & EMAC_ISR_ORE)
1937 ++st->rx_out_of_range;
1938 if (isr & EMAC_ISR_IRE)
1939 ++st->rx_in_range;
1940 if (isr & EMAC_ISR_SQE)
1941 ++st->tx_sqe;
1942 if (isr & EMAC_ISR_TE)
1943 ++st->tx_errors;
1944
1945 spin_unlock(&dev->lock);
1946
1947 return IRQ_HANDLED;
1948}
1949
1950static struct net_device_stats *emac_stats(struct net_device *ndev)
1951{
1952 struct emac_instance *dev = netdev_priv(ndev);
1953 struct emac_stats *st = &dev->stats;
1954 struct emac_error_stats *est = &dev->estats;
1955 struct net_device_stats *nst = &ndev->stats;
1956 unsigned long flags;
1957
1958 DBG2(dev, "stats" NL);
1959
1960 /* Compute "legacy" statistics */
1961 spin_lock_irqsave(&dev->lock, flags);
1962 nst->rx_packets = (unsigned long)st->rx_packets;
1963 nst->rx_bytes = (unsigned long)st->rx_bytes;
1964 nst->tx_packets = (unsigned long)st->tx_packets;
1965 nst->tx_bytes = (unsigned long)st->tx_bytes;
1966 nst->rx_dropped = (unsigned long)(est->rx_dropped_oom +
1967 est->rx_dropped_error +
1968 est->rx_dropped_resize +
1969 est->rx_dropped_mtu);
1970 nst->tx_dropped = (unsigned long)est->tx_dropped;
1971
1972 nst->rx_errors = (unsigned long)est->rx_bd_errors;
1973 nst->rx_fifo_errors = (unsigned long)(est->rx_bd_overrun +
1974 est->rx_fifo_overrun +
1975 est->rx_overrun);
1976 nst->rx_frame_errors = (unsigned long)(est->rx_bd_alignment_error +
1977 est->rx_alignment_error);
1978 nst->rx_crc_errors = (unsigned long)(est->rx_bd_bad_fcs +
1979 est->rx_bad_fcs);
1980 nst->rx_length_errors = (unsigned long)(est->rx_bd_runt_packet +
1981 est->rx_bd_short_event +
1982 est->rx_bd_packet_too_long +
1983 est->rx_bd_out_of_range +
1984 est->rx_bd_in_range +
1985 est->rx_runt_packet +
1986 est->rx_short_event +
1987 est->rx_packet_too_long +
1988 est->rx_out_of_range +
1989 est->rx_in_range);
1990
1991 nst->tx_errors = (unsigned long)(est->tx_bd_errors + est->tx_errors);
1992 nst->tx_fifo_errors = (unsigned long)(est->tx_bd_underrun +
1993 est->tx_underrun);
1994 nst->tx_carrier_errors = (unsigned long)est->tx_bd_carrier_loss;
1995 nst->collisions = (unsigned long)(est->tx_bd_excessive_deferral +
1996 est->tx_bd_excessive_collisions +
1997 est->tx_bd_late_collision +
1998 est->tx_bd_multple_collisions);
1999 spin_unlock_irqrestore(&dev->lock, flags);
2000 return nst;
2001}
2002
2003static struct mal_commac_ops emac_commac_ops = {
2004 .poll_tx = &emac_poll_tx,
2005 .poll_rx = &emac_poll_rx,
2006 .peek_rx = &emac_peek_rx,
2007 .rxde = &emac_rxde,
2008};
2009
2010static struct mal_commac_ops emac_commac_sg_ops = {
2011 .poll_tx = &emac_poll_tx,
2012 .poll_rx = &emac_poll_rx,
2013 .peek_rx = &emac_peek_rx_sg,
2014 .rxde = &emac_rxde,
2015};
2016
2017/* Ethtool support */
2018static int emac_ethtool_get_link_ksettings(struct net_device *ndev,
2019 struct ethtool_link_ksettings *cmd)
2020{
2021 struct emac_instance *dev = netdev_priv(ndev);
2022 u32 supported, advertising;
2023
2024 supported = dev->phy.features;
2025 cmd->base.port = PORT_MII;
2026 cmd->base.phy_address = dev->phy.address;
2027
2028 mutex_lock(&dev->link_lock);
2029 advertising = dev->phy.advertising;
2030 cmd->base.autoneg = dev->phy.autoneg;
2031 cmd->base.speed = dev->phy.speed;
2032 cmd->base.duplex = dev->phy.duplex;
2033 mutex_unlock(&dev->link_lock);
2034
2035 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2036 supported);
2037 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2038 advertising);
2039
2040 return 0;
2041}
2042
2043static int
2044emac_ethtool_set_link_ksettings(struct net_device *ndev,
2045 const struct ethtool_link_ksettings *cmd)
2046{
2047 struct emac_instance *dev = netdev_priv(ndev);
2048 u32 f = dev->phy.features;
2049 u32 advertising;
2050
2051 ethtool_convert_link_mode_to_legacy_u32(&advertising,
2052 cmd->link_modes.advertising);
2053
2054 DBG(dev, "set_settings(%d, %d, %d, 0x%08x)" NL,
2055 cmd->base.autoneg, cmd->base.speed, cmd->base.duplex, advertising);
2056
2057 /* Basic sanity checks */
2058 if (dev->phy.address < 0)
2059 return -EOPNOTSUPP;
2060 if (cmd->base.autoneg != AUTONEG_ENABLE &&
2061 cmd->base.autoneg != AUTONEG_DISABLE)
2062 return -EINVAL;
2063 if (cmd->base.autoneg == AUTONEG_ENABLE && advertising == 0)
2064 return -EINVAL;
2065 if (cmd->base.duplex != DUPLEX_HALF && cmd->base.duplex != DUPLEX_FULL)
2066 return -EINVAL;
2067
2068 if (cmd->base.autoneg == AUTONEG_DISABLE) {
2069 switch (cmd->base.speed) {
2070 case SPEED_10:
2071 if (cmd->base.duplex == DUPLEX_HALF &&
2072 !(f & SUPPORTED_10baseT_Half))
2073 return -EINVAL;
2074 if (cmd->base.duplex == DUPLEX_FULL &&
2075 !(f & SUPPORTED_10baseT_Full))
2076 return -EINVAL;
2077 break;
2078 case SPEED_100:
2079 if (cmd->base.duplex == DUPLEX_HALF &&
2080 !(f & SUPPORTED_100baseT_Half))
2081 return -EINVAL;
2082 if (cmd->base.duplex == DUPLEX_FULL &&
2083 !(f & SUPPORTED_100baseT_Full))
2084 return -EINVAL;
2085 break;
2086 case SPEED_1000:
2087 if (cmd->base.duplex == DUPLEX_HALF &&
2088 !(f & SUPPORTED_1000baseT_Half))
2089 return -EINVAL;
2090 if (cmd->base.duplex == DUPLEX_FULL &&
2091 !(f & SUPPORTED_1000baseT_Full))
2092 return -EINVAL;
2093 break;
2094 default:
2095 return -EINVAL;
2096 }
2097
2098 mutex_lock(&dev->link_lock);
2099 dev->phy.def->ops->setup_forced(&dev->phy, cmd->base.speed,
2100 cmd->base.duplex);
2101 mutex_unlock(&dev->link_lock);
2102
2103 } else {
2104 if (!(f & SUPPORTED_Autoneg))
2105 return -EINVAL;
2106
2107 mutex_lock(&dev->link_lock);
2108 dev->phy.def->ops->setup_aneg(&dev->phy,
2109 (advertising & f) |
2110 (dev->phy.advertising &
2111 (ADVERTISED_Pause |
2112 ADVERTISED_Asym_Pause)));
2113 mutex_unlock(&dev->link_lock);
2114 }
2115 emac_force_link_update(dev);
2116
2117 return 0;
2118}
2119
2120static void
2121emac_ethtool_get_ringparam(struct net_device *ndev,
2122 struct ethtool_ringparam *rp,
2123 struct kernel_ethtool_ringparam *kernel_rp,
2124 struct netlink_ext_ack *extack)
2125{
2126 rp->rx_max_pending = rp->rx_pending = NUM_RX_BUFF;
2127 rp->tx_max_pending = rp->tx_pending = NUM_TX_BUFF;
2128}
2129
2130static void emac_ethtool_get_pauseparam(struct net_device *ndev,
2131 struct ethtool_pauseparam *pp)
2132{
2133 struct emac_instance *dev = netdev_priv(ndev);
2134
2135 mutex_lock(&dev->link_lock);
2136 if ((dev->phy.features & SUPPORTED_Autoneg) &&
2137 (dev->phy.advertising & (ADVERTISED_Pause | ADVERTISED_Asym_Pause)))
2138 pp->autoneg = 1;
2139
2140 if (dev->phy.duplex == DUPLEX_FULL) {
2141 if (dev->phy.pause)
2142 pp->rx_pause = pp->tx_pause = 1;
2143 else if (dev->phy.asym_pause)
2144 pp->tx_pause = 1;
2145 }
2146 mutex_unlock(&dev->link_lock);
2147}
2148
2149static int emac_get_regs_len(struct emac_instance *dev)
2150{
2151 return sizeof(struct emac_ethtool_regs_subhdr) +
2152 sizeof(struct emac_regs);
2153}
2154
2155static int emac_ethtool_get_regs_len(struct net_device *ndev)
2156{
2157 struct emac_instance *dev = netdev_priv(ndev);
2158 int size;
2159
2160 size = sizeof(struct emac_ethtool_regs_hdr) +
2161 emac_get_regs_len(dev) + mal_get_regs_len(dev->mal);
2162 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2163 size += zmii_get_regs_len(dev->zmii_dev);
2164 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2165 size += rgmii_get_regs_len(dev->rgmii_dev);
2166 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2167 size += tah_get_regs_len(dev->tah_dev);
2168
2169 return size;
2170}
2171
2172static void *emac_dump_regs(struct emac_instance *dev, void *buf)
2173{
2174 struct emac_ethtool_regs_subhdr *hdr = buf;
2175
2176 hdr->index = dev->cell_index;
2177 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) {
2178 hdr->version = EMAC4SYNC_ETHTOOL_REGS_VER;
2179 } else if (emac_has_feature(dev, EMAC_FTR_EMAC4)) {
2180 hdr->version = EMAC4_ETHTOOL_REGS_VER;
2181 } else {
2182 hdr->version = EMAC_ETHTOOL_REGS_VER;
2183 }
2184 memcpy_fromio(hdr + 1, dev->emacp, sizeof(struct emac_regs));
2185 return (void *)(hdr + 1) + sizeof(struct emac_regs);
2186}
2187
2188static void emac_ethtool_get_regs(struct net_device *ndev,
2189 struct ethtool_regs *regs, void *buf)
2190{
2191 struct emac_instance *dev = netdev_priv(ndev);
2192 struct emac_ethtool_regs_hdr *hdr = buf;
2193
2194 hdr->components = 0;
2195 buf = hdr + 1;
2196
2197 buf = mal_dump_regs(dev->mal, buf);
2198 buf = emac_dump_regs(dev, buf);
2199 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) {
2200 hdr->components |= EMAC_ETHTOOL_REGS_ZMII;
2201 buf = zmii_dump_regs(dev->zmii_dev, buf);
2202 }
2203 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) {
2204 hdr->components |= EMAC_ETHTOOL_REGS_RGMII;
2205 buf = rgmii_dump_regs(dev->rgmii_dev, buf);
2206 }
2207 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) {
2208 hdr->components |= EMAC_ETHTOOL_REGS_TAH;
2209 buf = tah_dump_regs(dev->tah_dev, buf);
2210 }
2211}
2212
2213static int emac_ethtool_nway_reset(struct net_device *ndev)
2214{
2215 struct emac_instance *dev = netdev_priv(ndev);
2216 int res = 0;
2217
2218 DBG(dev, "nway_reset" NL);
2219
2220 if (dev->phy.address < 0)
2221 return -EOPNOTSUPP;
2222
2223 mutex_lock(&dev->link_lock);
2224 if (!dev->phy.autoneg) {
2225 res = -EINVAL;
2226 goto out;
2227 }
2228
2229 dev->phy.def->ops->setup_aneg(&dev->phy, dev->phy.advertising);
2230 out:
2231 mutex_unlock(&dev->link_lock);
2232 emac_force_link_update(dev);
2233 return res;
2234}
2235
2236static int emac_ethtool_get_sset_count(struct net_device *ndev, int stringset)
2237{
2238 if (stringset == ETH_SS_STATS)
2239 return EMAC_ETHTOOL_STATS_COUNT;
2240 else
2241 return -EINVAL;
2242}
2243
2244static void emac_ethtool_get_strings(struct net_device *ndev, u32 stringset,
2245 u8 * buf)
2246{
2247 if (stringset == ETH_SS_STATS)
2248 memcpy(buf, &emac_stats_keys, sizeof(emac_stats_keys));
2249}
2250
2251static void emac_ethtool_get_ethtool_stats(struct net_device *ndev,
2252 struct ethtool_stats *estats,
2253 u64 * tmp_stats)
2254{
2255 struct emac_instance *dev = netdev_priv(ndev);
2256
2257 memcpy(tmp_stats, &dev->stats, sizeof(dev->stats));
2258 tmp_stats += sizeof(dev->stats) / sizeof(u64);
2259 memcpy(tmp_stats, &dev->estats, sizeof(dev->estats));
2260}
2261
2262static void emac_ethtool_get_drvinfo(struct net_device *ndev,
2263 struct ethtool_drvinfo *info)
2264{
2265 struct emac_instance *dev = netdev_priv(ndev);
2266
2267 strscpy(info->driver, "ibm_emac", sizeof(info->driver));
2268 strscpy(info->version, DRV_VERSION, sizeof(info->version));
2269 snprintf(info->bus_info, sizeof(info->bus_info), "PPC 4xx EMAC-%d %pOF",
2270 dev->cell_index, dev->ofdev->dev.of_node);
2271}
2272
2273static const struct ethtool_ops emac_ethtool_ops = {
2274 .get_drvinfo = emac_ethtool_get_drvinfo,
2275
2276 .get_regs_len = emac_ethtool_get_regs_len,
2277 .get_regs = emac_ethtool_get_regs,
2278
2279 .nway_reset = emac_ethtool_nway_reset,
2280
2281 .get_ringparam = emac_ethtool_get_ringparam,
2282 .get_pauseparam = emac_ethtool_get_pauseparam,
2283
2284 .get_strings = emac_ethtool_get_strings,
2285 .get_sset_count = emac_ethtool_get_sset_count,
2286 .get_ethtool_stats = emac_ethtool_get_ethtool_stats,
2287
2288 .get_link = ethtool_op_get_link,
2289 .get_link_ksettings = emac_ethtool_get_link_ksettings,
2290 .set_link_ksettings = emac_ethtool_set_link_ksettings,
2291};
2292
2293static int emac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2294{
2295 struct emac_instance *dev = netdev_priv(ndev);
2296 struct mii_ioctl_data *data = if_mii(rq);
2297
2298 DBG(dev, "ioctl %08x" NL, cmd);
2299
2300 if (dev->phy.address < 0)
2301 return -EOPNOTSUPP;
2302
2303 switch (cmd) {
2304 case SIOCGMIIPHY:
2305 data->phy_id = dev->phy.address;
2306 fallthrough;
2307 case SIOCGMIIREG:
2308 data->val_out = emac_mdio_read(ndev, dev->phy.address,
2309 data->reg_num);
2310 return 0;
2311
2312 case SIOCSMIIREG:
2313 emac_mdio_write(ndev, dev->phy.address, data->reg_num,
2314 data->val_in);
2315 return 0;
2316 default:
2317 return -EOPNOTSUPP;
2318 }
2319}
2320
2321struct emac_depentry {
2322 u32 phandle;
2323 struct device_node *node;
2324 struct platform_device *ofdev;
2325 void *drvdata;
2326};
2327
2328#define EMAC_DEP_MAL_IDX 0
2329#define EMAC_DEP_ZMII_IDX 1
2330#define EMAC_DEP_RGMII_IDX 2
2331#define EMAC_DEP_TAH_IDX 3
2332#define EMAC_DEP_MDIO_IDX 4
2333#define EMAC_DEP_PREV_IDX 5
2334#define EMAC_DEP_COUNT 6
2335
2336static int emac_check_deps(struct emac_instance *dev,
2337 struct emac_depentry *deps)
2338{
2339 int i, there = 0;
2340 struct device_node *np;
2341
2342 for (i = 0; i < EMAC_DEP_COUNT; i++) {
2343 /* no dependency on that item, allright */
2344 if (deps[i].phandle == 0) {
2345 there++;
2346 continue;
2347 }
2348 /* special case for blist as the dependency might go away */
2349 if (i == EMAC_DEP_PREV_IDX) {
2350 np = *(dev->blist - 1);
2351 if (np == NULL) {
2352 deps[i].phandle = 0;
2353 there++;
2354 continue;
2355 }
2356 if (deps[i].node == NULL)
2357 deps[i].node = of_node_get(np);
2358 }
2359 if (deps[i].node == NULL)
2360 deps[i].node = of_find_node_by_phandle(deps[i].phandle);
2361 if (deps[i].node == NULL)
2362 continue;
2363 if (deps[i].ofdev == NULL)
2364 deps[i].ofdev = of_find_device_by_node(deps[i].node);
2365 if (deps[i].ofdev == NULL)
2366 continue;
2367 if (deps[i].drvdata == NULL)
2368 deps[i].drvdata = platform_get_drvdata(deps[i].ofdev);
2369 if (deps[i].drvdata != NULL)
2370 there++;
2371 }
2372 if (there != EMAC_DEP_COUNT)
2373 return -EPROBE_DEFER;
2374 return 0;
2375}
2376
2377static void emac_put_deps(struct emac_instance *dev)
2378{
2379 platform_device_put(dev->mal_dev);
2380 platform_device_put(dev->zmii_dev);
2381 platform_device_put(dev->rgmii_dev);
2382 platform_device_put(dev->mdio_dev);
2383 platform_device_put(dev->tah_dev);
2384}
2385
2386static int emac_wait_deps(struct emac_instance *dev)
2387{
2388 struct emac_depentry deps[EMAC_DEP_COUNT];
2389 int i, err;
2390
2391 memset(&deps, 0, sizeof(deps));
2392
2393 deps[EMAC_DEP_MAL_IDX].phandle = dev->mal_ph;
2394 deps[EMAC_DEP_ZMII_IDX].phandle = dev->zmii_ph;
2395 deps[EMAC_DEP_RGMII_IDX].phandle = dev->rgmii_ph;
2396 if (dev->tah_ph)
2397 deps[EMAC_DEP_TAH_IDX].phandle = dev->tah_ph;
2398 if (dev->mdio_ph)
2399 deps[EMAC_DEP_MDIO_IDX].phandle = dev->mdio_ph;
2400 if (dev->blist && dev->blist > emac_boot_list)
2401 deps[EMAC_DEP_PREV_IDX].phandle = 0xffffffffu;
2402 err = emac_check_deps(dev, deps);
2403 for (i = 0; i < EMAC_DEP_COUNT; i++) {
2404 of_node_put(deps[i].node);
2405 if (err)
2406 platform_device_put(deps[i].ofdev);
2407 }
2408 if (!err) {
2409 dev->mal_dev = deps[EMAC_DEP_MAL_IDX].ofdev;
2410 dev->zmii_dev = deps[EMAC_DEP_ZMII_IDX].ofdev;
2411 dev->rgmii_dev = deps[EMAC_DEP_RGMII_IDX].ofdev;
2412 dev->tah_dev = deps[EMAC_DEP_TAH_IDX].ofdev;
2413 dev->mdio_dev = deps[EMAC_DEP_MDIO_IDX].ofdev;
2414 }
2415 platform_device_put(deps[EMAC_DEP_PREV_IDX].ofdev);
2416 return err;
2417}
2418
2419static int emac_read_uint_prop(struct device_node *np, const char *name,
2420 u32 *val, int fatal)
2421{
2422 int err;
2423
2424 err = of_property_read_u32(np, name, val);
2425 if (err) {
2426 if (fatal)
2427 pr_err("%pOF: missing %s property", np, name);
2428 return err;
2429 }
2430 return 0;
2431}
2432
2433static void emac_adjust_link(struct net_device *ndev)
2434{
2435 struct emac_instance *dev = netdev_priv(ndev);
2436 struct phy_device *phy = ndev->phydev;
2437
2438 dev->phy.autoneg = phy->autoneg;
2439 dev->phy.speed = phy->speed;
2440 dev->phy.duplex = phy->duplex;
2441 dev->phy.pause = phy->pause;
2442 dev->phy.asym_pause = phy->asym_pause;
2443 ethtool_convert_link_mode_to_legacy_u32(&dev->phy.advertising,
2444 phy->advertising);
2445}
2446
2447static int emac_mii_bus_read(struct mii_bus *bus, int addr, int regnum)
2448{
2449 int ret = emac_mdio_read(bus->priv, addr, regnum);
2450 /* This is a workaround for powered down ports/phys.
2451 * In the wild, this was seen on the Cisco Meraki MX60(W).
2452 * This hardware disables ports as part of the handoff
2453 * procedure. Accessing the ports will lead to errors
2454 * (-ETIMEDOUT, -EREMOTEIO) that do more harm than good.
2455 */
2456 return ret < 0 ? 0xffff : ret;
2457}
2458
2459static int emac_mii_bus_write(struct mii_bus *bus, int addr,
2460 int regnum, u16 val)
2461{
2462 emac_mdio_write(bus->priv, addr, regnum, val);
2463 return 0;
2464}
2465
2466static int emac_mii_bus_reset(struct mii_bus *bus)
2467{
2468 struct emac_instance *dev = netdev_priv(bus->priv);
2469
2470 return emac_reset(dev);
2471}
2472
2473static int emac_mdio_phy_start_aneg(struct mii_phy *phy,
2474 struct phy_device *phy_dev)
2475{
2476 phy_dev->autoneg = phy->autoneg;
2477 phy_dev->speed = phy->speed;
2478 phy_dev->duplex = phy->duplex;
2479 ethtool_convert_legacy_u32_to_link_mode(phy_dev->advertising,
2480 phy->advertising);
2481 return phy_start_aneg(phy_dev);
2482}
2483
2484static int emac_mdio_setup_aneg(struct mii_phy *phy, u32 advertise)
2485{
2486 struct net_device *ndev = phy->dev;
2487
2488 phy->autoneg = AUTONEG_ENABLE;
2489 phy->advertising = advertise;
2490 return emac_mdio_phy_start_aneg(phy, ndev->phydev);
2491}
2492
2493static int emac_mdio_setup_forced(struct mii_phy *phy, int speed, int fd)
2494{
2495 struct net_device *ndev = phy->dev;
2496
2497 phy->autoneg = AUTONEG_DISABLE;
2498 phy->speed = speed;
2499 phy->duplex = fd;
2500 return emac_mdio_phy_start_aneg(phy, ndev->phydev);
2501}
2502
2503static int emac_mdio_poll_link(struct mii_phy *phy)
2504{
2505 struct net_device *ndev = phy->dev;
2506 struct emac_instance *dev = netdev_priv(ndev);
2507 int res;
2508
2509 res = phy_read_status(ndev->phydev);
2510 if (res) {
2511 dev_err(&dev->ofdev->dev, "link update failed (%d).", res);
2512 return ethtool_op_get_link(ndev);
2513 }
2514
2515 return ndev->phydev->link;
2516}
2517
2518static int emac_mdio_read_link(struct mii_phy *phy)
2519{
2520 struct net_device *ndev = phy->dev;
2521 struct phy_device *phy_dev = ndev->phydev;
2522 int res;
2523
2524 res = phy_read_status(phy_dev);
2525 if (res)
2526 return res;
2527
2528 phy->speed = phy_dev->speed;
2529 phy->duplex = phy_dev->duplex;
2530 phy->pause = phy_dev->pause;
2531 phy->asym_pause = phy_dev->asym_pause;
2532 return 0;
2533}
2534
2535static int emac_mdio_init_phy(struct mii_phy *phy)
2536{
2537 struct net_device *ndev = phy->dev;
2538
2539 phy_start(ndev->phydev);
2540 return phy_init_hw(ndev->phydev);
2541}
2542
2543static const struct mii_phy_ops emac_dt_mdio_phy_ops = {
2544 .init = emac_mdio_init_phy,
2545 .setup_aneg = emac_mdio_setup_aneg,
2546 .setup_forced = emac_mdio_setup_forced,
2547 .poll_link = emac_mdio_poll_link,
2548 .read_link = emac_mdio_read_link,
2549};
2550
2551static int emac_dt_mdio_probe(struct emac_instance *dev)
2552{
2553 struct device_node *mii_np;
2554 struct mii_bus *bus;
2555 int res;
2556
2557 mii_np = of_get_child_by_name(dev->ofdev->dev.of_node, "mdio");
2558 if (!mii_np) {
2559 dev_err(&dev->ofdev->dev, "no mdio definition found.");
2560 return -ENODEV;
2561 }
2562
2563 if (!of_device_is_available(mii_np)) {
2564 res = -ENODEV;
2565 goto put_node;
2566 }
2567
2568 bus = devm_mdiobus_alloc(&dev->ofdev->dev);
2569 if (!bus) {
2570 res = -ENOMEM;
2571 goto put_node;
2572 }
2573
2574 bus->priv = dev->ndev;
2575 bus->parent = dev->ndev->dev.parent;
2576 bus->name = "emac_mdio";
2577 bus->read = &emac_mii_bus_read;
2578 bus->write = &emac_mii_bus_write;
2579 bus->reset = &emac_mii_bus_reset;
2580 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev->ofdev->name);
2581 res = devm_of_mdiobus_register(&dev->ofdev->dev, bus, mii_np);
2582 if (res) {
2583 dev_err(&dev->ofdev->dev, "cannot register MDIO bus %s (%d)",
2584 bus->name, res);
2585 }
2586
2587 put_node:
2588 of_node_put(mii_np);
2589 return res;
2590}
2591
2592static int emac_dt_phy_connect(struct emac_instance *dev,
2593 struct device_node *phy_handle)
2594{
2595 struct phy_device *phy_dev;
2596
2597 dev->phy.def = devm_kzalloc(&dev->ofdev->dev, sizeof(*dev->phy.def),
2598 GFP_KERNEL);
2599 if (!dev->phy.def)
2600 return -ENOMEM;
2601
2602 phy_dev = of_phy_connect(dev->ndev, phy_handle, &emac_adjust_link, 0,
2603 dev->phy_mode);
2604 if (!phy_dev) {
2605 dev_err(&dev->ofdev->dev, "failed to connect to PHY.\n");
2606 return -ENODEV;
2607 }
2608
2609 dev->phy.def->phy_id = phy_dev->drv->phy_id;
2610 dev->phy.def->phy_id_mask = phy_dev->drv->phy_id_mask;
2611 dev->phy.def->name = phy_dev->drv->name;
2612 dev->phy.def->ops = &emac_dt_mdio_phy_ops;
2613 ethtool_convert_link_mode_to_legacy_u32(&dev->phy.features,
2614 phy_dev->supported);
2615 dev->phy.address = phy_dev->mdio.addr;
2616 dev->phy.mode = phy_dev->interface;
2617 return 0;
2618}
2619
2620static int emac_dt_phy_probe(struct emac_instance *dev)
2621{
2622 struct device_node *np = dev->ofdev->dev.of_node;
2623 struct device_node *phy_handle;
2624 int res = 1;
2625
2626 phy_handle = of_parse_phandle(np, "phy-handle", 0);
2627
2628 if (phy_handle) {
2629 res = emac_dt_mdio_probe(dev);
2630 if (!res) {
2631 res = emac_dt_phy_connect(dev, phy_handle);
2632 }
2633 }
2634
2635 of_node_put(phy_handle);
2636 return res;
2637}
2638
2639static int emac_init_phy(struct emac_instance *dev)
2640{
2641 struct device_node *np = dev->ofdev->dev.of_node;
2642 struct net_device *ndev = dev->ndev;
2643 u32 phy_map, adv;
2644 int i;
2645
2646 dev->phy.dev = ndev;
2647 dev->phy.mode = dev->phy_mode;
2648
2649 /* PHY-less configuration. */
2650 if ((dev->phy_address == 0xffffffff && dev->phy_map == 0xffffffff) ||
2651 of_phy_is_fixed_link(np)) {
2652 emac_reset(dev);
2653
2654 /* PHY-less configuration. */
2655 dev->phy.address = -1;
2656 dev->phy.features = SUPPORTED_MII;
2657 if (emac_phy_supports_gige(dev->phy_mode))
2658 dev->phy.features |= SUPPORTED_1000baseT_Full;
2659 else
2660 dev->phy.features |= SUPPORTED_100baseT_Full;
2661 dev->phy.pause = 1;
2662
2663 if (of_phy_is_fixed_link(np)) {
2664 int res = emac_dt_mdio_probe(dev);
2665
2666 if (res)
2667 return res;
2668
2669 res = of_phy_register_fixed_link(np);
2670 ndev->phydev = of_phy_find_device(np);
2671 if (res || !ndev->phydev)
2672 return res ? res : -EINVAL;
2673 emac_adjust_link(dev->ndev);
2674 put_device(&ndev->phydev->mdio.dev);
2675 }
2676 return 0;
2677 }
2678
2679 mutex_lock(&emac_phy_map_lock);
2680 phy_map = dev->phy_map | busy_phy_map;
2681
2682 DBG(dev, "PHY maps %08x %08x" NL, dev->phy_map, busy_phy_map);
2683
2684 dev->phy.mdio_read = emac_mdio_read;
2685 dev->phy.mdio_write = emac_mdio_write;
2686
2687 /* Enable internal clock source */
2688#ifdef CONFIG_PPC_DCR_NATIVE
2689 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2690 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
2691#endif
2692 /* PHY clock workaround */
2693 emac_rx_clk_tx(dev);
2694
2695 /* Enable internal clock source on 440GX*/
2696#ifdef CONFIG_PPC_DCR_NATIVE
2697 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2698 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
2699#endif
2700 /* Configure EMAC with defaults so we can at least use MDIO
2701 * This is needed mostly for 440GX
2702 */
2703 if (emac_phy_gpcs(dev->phy.mode)) {
2704 /* XXX
2705 * Make GPCS PHY address equal to EMAC index.
2706 * We probably should take into account busy_phy_map
2707 * and/or phy_map here.
2708 *
2709 * Note that the busy_phy_map is currently global
2710 * while it should probably be per-ASIC...
2711 */
2712 dev->phy.gpcs_address = dev->gpcs_address;
2713 if (dev->phy.gpcs_address == 0xffffffff)
2714 dev->phy.address = dev->cell_index;
2715 }
2716
2717 emac_configure(dev);
2718
2719 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) {
2720 int res = emac_dt_phy_probe(dev);
2721
2722 switch (res) {
2723 case 1:
2724 /* No phy-handle property configured.
2725 * Continue with the existing phy probe
2726 * and setup code.
2727 */
2728 break;
2729
2730 case 0:
2731 mutex_unlock(&emac_phy_map_lock);
2732 goto init_phy;
2733
2734 default:
2735 mutex_unlock(&emac_phy_map_lock);
2736 dev_err(&dev->ofdev->dev, "failed to attach dt phy (%d).\n",
2737 res);
2738 return res;
2739 }
2740 }
2741
2742 if (dev->phy_address != 0xffffffff)
2743 phy_map = ~(1 << dev->phy_address);
2744
2745 for (i = 0; i < 0x20; phy_map >>= 1, ++i)
2746 if (!(phy_map & 1)) {
2747 int r;
2748 busy_phy_map |= 1 << i;
2749
2750 /* Quick check if there is a PHY at the address */
2751 r = emac_mdio_read(dev->ndev, i, MII_BMCR);
2752 if (r == 0xffff || r < 0)
2753 continue;
2754 if (!emac_mii_phy_probe(&dev->phy, i))
2755 break;
2756 }
2757
2758 /* Enable external clock source */
2759#ifdef CONFIG_PPC_DCR_NATIVE
2760 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2761 dcri_clrset(SDR0, SDR0_MFR, SDR0_MFR_ECS, 0);
2762#endif
2763 mutex_unlock(&emac_phy_map_lock);
2764 if (i == 0x20) {
2765 printk(KERN_WARNING "%pOF: can't find PHY!\n", np);
2766 return -ENXIO;
2767 }
2768
2769 init_phy:
2770 /* Init PHY */
2771 if (dev->phy.def->ops->init)
2772 dev->phy.def->ops->init(&dev->phy);
2773
2774 /* Disable any PHY features not supported by the platform */
2775 dev->phy.def->features &= ~dev->phy_feat_exc;
2776 dev->phy.features &= ~dev->phy_feat_exc;
2777
2778 /* Setup initial link parameters */
2779 if (dev->phy.features & SUPPORTED_Autoneg) {
2780 adv = dev->phy.features;
2781 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x))
2782 adv |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
2783 /* Restart autonegotiation */
2784 dev->phy.def->ops->setup_aneg(&dev->phy, adv);
2785 } else {
2786 u32 f = dev->phy.def->features;
2787 int speed = SPEED_10, fd = DUPLEX_HALF;
2788
2789 /* Select highest supported speed/duplex */
2790 if (f & SUPPORTED_1000baseT_Full) {
2791 speed = SPEED_1000;
2792 fd = DUPLEX_FULL;
2793 } else if (f & SUPPORTED_1000baseT_Half)
2794 speed = SPEED_1000;
2795 else if (f & SUPPORTED_100baseT_Full) {
2796 speed = SPEED_100;
2797 fd = DUPLEX_FULL;
2798 } else if (f & SUPPORTED_100baseT_Half)
2799 speed = SPEED_100;
2800 else if (f & SUPPORTED_10baseT_Full)
2801 fd = DUPLEX_FULL;
2802
2803 /* Force link parameters */
2804 dev->phy.def->ops->setup_forced(&dev->phy, speed, fd);
2805 }
2806 return 0;
2807}
2808
2809static int emac_init_config(struct emac_instance *dev)
2810{
2811 struct device_node *np = dev->ofdev->dev.of_node;
2812 int err;
2813
2814 /* Read config from device-tree */
2815 if (emac_read_uint_prop(np, "mal-device", &dev->mal_ph, 1))
2816 return -ENXIO;
2817 if (emac_read_uint_prop(np, "mal-tx-channel", &dev->mal_tx_chan, 1))
2818 return -ENXIO;
2819 if (emac_read_uint_prop(np, "mal-rx-channel", &dev->mal_rx_chan, 1))
2820 return -ENXIO;
2821 if (emac_read_uint_prop(np, "cell-index", &dev->cell_index, 1))
2822 return -ENXIO;
2823 if (emac_read_uint_prop(np, "max-frame-size", &dev->max_mtu, 0))
2824 dev->max_mtu = ETH_DATA_LEN;
2825 if (emac_read_uint_prop(np, "rx-fifo-size", &dev->rx_fifo_size, 0))
2826 dev->rx_fifo_size = 2048;
2827 if (emac_read_uint_prop(np, "tx-fifo-size", &dev->tx_fifo_size, 0))
2828 dev->tx_fifo_size = 2048;
2829 if (emac_read_uint_prop(np, "rx-fifo-size-gige", &dev->rx_fifo_size_gige, 0))
2830 dev->rx_fifo_size_gige = dev->rx_fifo_size;
2831 if (emac_read_uint_prop(np, "tx-fifo-size-gige", &dev->tx_fifo_size_gige, 0))
2832 dev->tx_fifo_size_gige = dev->tx_fifo_size;
2833 if (emac_read_uint_prop(np, "phy-address", &dev->phy_address, 0))
2834 dev->phy_address = 0xffffffff;
2835 if (emac_read_uint_prop(np, "phy-map", &dev->phy_map, 0))
2836 dev->phy_map = 0xffffffff;
2837 if (emac_read_uint_prop(np, "gpcs-address", &dev->gpcs_address, 0))
2838 dev->gpcs_address = 0xffffffff;
2839 if (emac_read_uint_prop(np->parent, "clock-frequency", &dev->opb_bus_freq, 1))
2840 return -ENXIO;
2841 if (emac_read_uint_prop(np, "tah-device", &dev->tah_ph, 0))
2842 dev->tah_ph = 0;
2843 if (emac_read_uint_prop(np, "tah-channel", &dev->tah_port, 0))
2844 dev->tah_port = 0;
2845 if (emac_read_uint_prop(np, "mdio-device", &dev->mdio_ph, 0))
2846 dev->mdio_ph = 0;
2847 if (emac_read_uint_prop(np, "zmii-device", &dev->zmii_ph, 0))
2848 dev->zmii_ph = 0;
2849 if (emac_read_uint_prop(np, "zmii-channel", &dev->zmii_port, 0))
2850 dev->zmii_port = 0xffffffff;
2851 if (emac_read_uint_prop(np, "rgmii-device", &dev->rgmii_ph, 0))
2852 dev->rgmii_ph = 0;
2853 if (emac_read_uint_prop(np, "rgmii-channel", &dev->rgmii_port, 0))
2854 dev->rgmii_port = 0xffffffff;
2855 if (emac_read_uint_prop(np, "fifo-entry-size", &dev->fifo_entry_size, 0))
2856 dev->fifo_entry_size = 16;
2857 if (emac_read_uint_prop(np, "mal-burst-size", &dev->mal_burst_size, 0))
2858 dev->mal_burst_size = 256;
2859
2860 /* PHY mode needs some decoding */
2861 err = of_get_phy_mode(np, &dev->phy_mode);
2862 if (err)
2863 dev->phy_mode = PHY_INTERFACE_MODE_NA;
2864
2865 /* Check EMAC version */
2866 if (of_device_is_compatible(np, "ibm,emac4sync")) {
2867 dev->features |= (EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC);
2868 if (of_device_is_compatible(np, "ibm,emac-460ex") ||
2869 of_device_is_compatible(np, "ibm,emac-460gt"))
2870 dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX;
2871 if (of_device_is_compatible(np, "ibm,emac-405ex") ||
2872 of_device_is_compatible(np, "ibm,emac-405exr"))
2873 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
2874 if (of_device_is_compatible(np, "ibm,emac-apm821xx")) {
2875 dev->features |= (EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE |
2876 EMAC_FTR_APM821XX_NO_HALF_DUPLEX |
2877 EMAC_FTR_460EX_PHY_CLK_FIX);
2878 }
2879 } else if (of_device_is_compatible(np, "ibm,emac4")) {
2880 dev->features |= EMAC_FTR_EMAC4;
2881 if (of_device_is_compatible(np, "ibm,emac-440gx"))
2882 dev->features |= EMAC_FTR_440GX_PHY_CLK_FIX;
2883 } else {
2884 if (of_device_is_compatible(np, "ibm,emac-440ep") ||
2885 of_device_is_compatible(np, "ibm,emac-440gr"))
2886 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
2887 if (of_device_is_compatible(np, "ibm,emac-405ez")) {
2888#ifdef CONFIG_IBM_EMAC_NO_FLOW_CTRL
2889 dev->features |= EMAC_FTR_NO_FLOW_CONTROL_40x;
2890#else
2891 printk(KERN_ERR "%pOF: Flow control not disabled!\n",
2892 np);
2893 return -ENXIO;
2894#endif
2895 }
2896
2897 }
2898
2899 /* Fixup some feature bits based on the device tree */
2900 if (of_property_read_bool(np, "has-inverted-stacr-oc"))
2901 dev->features |= EMAC_FTR_STACR_OC_INVERT;
2902 if (of_property_read_bool(np, "has-new-stacr-staopc"))
2903 dev->features |= EMAC_FTR_HAS_NEW_STACR;
2904
2905 /* CAB lacks the appropriate properties */
2906 if (of_device_is_compatible(np, "ibm,emac-axon"))
2907 dev->features |= EMAC_FTR_HAS_NEW_STACR |
2908 EMAC_FTR_STACR_OC_INVERT;
2909
2910 /* Enable TAH/ZMII/RGMII features as found */
2911 if (dev->tah_ph != 0) {
2912#ifdef CONFIG_IBM_EMAC_TAH
2913 dev->features |= EMAC_FTR_HAS_TAH;
2914#else
2915 printk(KERN_ERR "%pOF: TAH support not enabled !\n", np);
2916 return -ENXIO;
2917#endif
2918 }
2919
2920 if (dev->zmii_ph != 0) {
2921#ifdef CONFIG_IBM_EMAC_ZMII
2922 dev->features |= EMAC_FTR_HAS_ZMII;
2923#else
2924 printk(KERN_ERR "%pOF: ZMII support not enabled !\n", np);
2925 return -ENXIO;
2926#endif
2927 }
2928
2929 if (dev->rgmii_ph != 0) {
2930#ifdef CONFIG_IBM_EMAC_RGMII
2931 dev->features |= EMAC_FTR_HAS_RGMII;
2932#else
2933 printk(KERN_ERR "%pOF: RGMII support not enabled !\n", np);
2934 return -ENXIO;
2935#endif
2936 }
2937
2938 /* Read MAC-address */
2939 err = of_get_ethdev_address(np, dev->ndev);
2940 if (err == -EPROBE_DEFER)
2941 return err;
2942 if (err) {
2943 dev_warn(&dev->ofdev->dev, "Can't get valid mac-address. Generating random.");
2944 eth_hw_addr_random(dev->ndev);
2945 }
2946
2947 /* IAHT and GAHT filter parameterization */
2948 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) {
2949 dev->xaht_slots_shift = EMAC4SYNC_XAHT_SLOTS_SHIFT;
2950 dev->xaht_width_shift = EMAC4SYNC_XAHT_WIDTH_SHIFT;
2951 } else {
2952 dev->xaht_slots_shift = EMAC4_XAHT_SLOTS_SHIFT;
2953 dev->xaht_width_shift = EMAC4_XAHT_WIDTH_SHIFT;
2954 }
2955
2956 /* This should never happen */
2957 if (WARN_ON(EMAC_XAHT_REGS(dev) > EMAC_XAHT_MAX_REGS))
2958 return -ENXIO;
2959
2960 DBG(dev, "features : 0x%08x / 0x%08x\n", dev->features, EMAC_FTRS_POSSIBLE);
2961 DBG(dev, "tx_fifo_size : %d (%d gige)\n", dev->tx_fifo_size, dev->tx_fifo_size_gige);
2962 DBG(dev, "rx_fifo_size : %d (%d gige)\n", dev->rx_fifo_size, dev->rx_fifo_size_gige);
2963 DBG(dev, "max_mtu : %d\n", dev->max_mtu);
2964 DBG(dev, "OPB freq : %d\n", dev->opb_bus_freq);
2965
2966 return 0;
2967}
2968
2969static const struct net_device_ops emac_netdev_ops = {
2970 .ndo_open = emac_open,
2971 .ndo_stop = emac_close,
2972 .ndo_get_stats = emac_stats,
2973 .ndo_set_rx_mode = emac_set_multicast_list,
2974 .ndo_eth_ioctl = emac_ioctl,
2975 .ndo_tx_timeout = emac_tx_timeout,
2976 .ndo_validate_addr = eth_validate_addr,
2977 .ndo_set_mac_address = emac_set_mac_address,
2978 .ndo_start_xmit = emac_start_xmit,
2979};
2980
2981static const struct net_device_ops emac_gige_netdev_ops = {
2982 .ndo_open = emac_open,
2983 .ndo_stop = emac_close,
2984 .ndo_get_stats = emac_stats,
2985 .ndo_set_rx_mode = emac_set_multicast_list,
2986 .ndo_eth_ioctl = emac_ioctl,
2987 .ndo_tx_timeout = emac_tx_timeout,
2988 .ndo_validate_addr = eth_validate_addr,
2989 .ndo_set_mac_address = emac_set_mac_address,
2990 .ndo_start_xmit = emac_start_xmit_sg,
2991 .ndo_change_mtu = emac_change_mtu,
2992};
2993
2994static int emac_probe(struct platform_device *ofdev)
2995{
2996 struct net_device *ndev;
2997 struct emac_instance *dev;
2998 struct device_node *np = ofdev->dev.of_node;
2999 struct device_node **blist = NULL;
3000 int err, i;
3001
3002 /* Skip unused/unwired EMACS. We leave the check for an unused
3003 * property here for now, but new flat device trees should set a
3004 * status property to "disabled" instead.
3005 */
3006 if (of_property_read_bool(np, "unused") || !of_device_is_available(np))
3007 return -ENODEV;
3008
3009 /* Find ourselves in the bootlist if we are there */
3010 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
3011 if (emac_boot_list[i] == np)
3012 blist = &emac_boot_list[i];
3013
3014 /* Allocate our net_device structure */
3015 err = -ENOMEM;
3016 ndev = devm_alloc_etherdev(&ofdev->dev, sizeof(struct emac_instance));
3017 if (!ndev)
3018 goto err_gone;
3019
3020 dev = netdev_priv(ndev);
3021 dev->ndev = ndev;
3022 dev->ofdev = ofdev;
3023 dev->blist = blist;
3024 SET_NETDEV_DEV(ndev, &ofdev->dev);
3025
3026 /* Initialize some embedded data structures */
3027 err = devm_mutex_init(&ofdev->dev, &dev->mdio_lock);
3028 if (err)
3029 goto err_gone;
3030
3031 err = devm_mutex_init(&ofdev->dev, &dev->link_lock);
3032 if (err)
3033 goto err_gone;
3034
3035 spin_lock_init(&dev->lock);
3036 INIT_WORK(&dev->reset_work, emac_reset_work);
3037
3038 /* Init various config data based on device-tree */
3039 err = emac_init_config(dev);
3040 if (err)
3041 goto err_gone;
3042
3043 /* Setup error IRQ handler */
3044 dev->emac_irq = platform_get_irq(ofdev, 0);
3045 err = devm_request_irq(&ofdev->dev, dev->emac_irq, emac_irq, 0, "EMAC",
3046 dev);
3047 if (err) {
3048 dev_err_probe(&ofdev->dev, err, "failed to request IRQ %d",
3049 dev->emac_irq);
3050 goto err_gone;
3051 }
3052
3053 ndev->irq = dev->emac_irq;
3054
3055 dev->emacp = devm_platform_ioremap_resource(ofdev, 0);
3056 if (IS_ERR(dev->emacp)) {
3057 dev_err(&ofdev->dev, "can't map device registers");
3058 err = PTR_ERR(dev->emacp);
3059 goto err_gone;
3060 }
3061
3062 /* Wait for dependent devices */
3063 err = emac_wait_deps(dev);
3064 if (err)
3065 goto err_gone;
3066 dev->mal = platform_get_drvdata(dev->mal_dev);
3067 if (dev->mdio_dev != NULL)
3068 dev->mdio_instance = platform_get_drvdata(dev->mdio_dev);
3069
3070 /* Register with MAL */
3071 dev->commac.ops = &emac_commac_ops;
3072 dev->commac.dev = dev;
3073 dev->commac.tx_chan_mask = MAL_CHAN_MASK(dev->mal_tx_chan);
3074 dev->commac.rx_chan_mask = MAL_CHAN_MASK(dev->mal_rx_chan);
3075 err = mal_register_commac(dev->mal, &dev->commac);
3076 if (err) {
3077 printk(KERN_ERR "%pOF: failed to register with mal %pOF!\n",
3078 np, dev->mal_dev->dev.of_node);
3079 goto err_rel_deps;
3080 }
3081 dev->rx_skb_size = emac_rx_skb_size(ndev->mtu);
3082 dev->rx_sync_size = emac_rx_sync_size(ndev->mtu);
3083
3084 /* Get pointers to BD rings */
3085 dev->tx_desc =
3086 dev->mal->bd_virt + mal_tx_bd_offset(dev->mal, dev->mal_tx_chan);
3087 dev->rx_desc =
3088 dev->mal->bd_virt + mal_rx_bd_offset(dev->mal, dev->mal_rx_chan);
3089
3090 DBG(dev, "tx_desc %p" NL, dev->tx_desc);
3091 DBG(dev, "rx_desc %p" NL, dev->rx_desc);
3092
3093 /* Clean rings */
3094 memset(dev->tx_desc, 0, NUM_TX_BUFF * sizeof(struct mal_descriptor));
3095 memset(dev->rx_desc, 0, NUM_RX_BUFF * sizeof(struct mal_descriptor));
3096 memset(dev->tx_skb, 0, NUM_TX_BUFF * sizeof(struct sk_buff *));
3097 memset(dev->rx_skb, 0, NUM_RX_BUFF * sizeof(struct sk_buff *));
3098
3099 /* Attach to ZMII, if needed */
3100 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII) &&
3101 (err = zmii_attach(dev->zmii_dev, dev->zmii_port, &dev->phy_mode)) != 0)
3102 goto err_unreg_commac;
3103
3104 /* Attach to RGMII, if needed */
3105 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII) &&
3106 (err = rgmii_attach(dev->rgmii_dev, dev->rgmii_port, dev->phy_mode)) != 0)
3107 goto err_detach_zmii;
3108
3109 /* Attach to TAH, if needed */
3110 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
3111 (err = tah_attach(dev->tah_dev, dev->tah_port)) != 0)
3112 goto err_detach_rgmii;
3113
3114 /* Set some link defaults before we can find out real parameters */
3115 dev->phy.speed = SPEED_100;
3116 dev->phy.duplex = DUPLEX_FULL;
3117 dev->phy.autoneg = AUTONEG_DISABLE;
3118 dev->phy.pause = dev->phy.asym_pause = 0;
3119 dev->stop_timeout = STOP_TIMEOUT_100;
3120 INIT_DELAYED_WORK(&dev->link_work, emac_link_timer);
3121
3122 /* Some SoCs like APM821xx does not support Half Duplex mode. */
3123 if (emac_has_feature(dev, EMAC_FTR_APM821XX_NO_HALF_DUPLEX)) {
3124 dev->phy_feat_exc = (SUPPORTED_1000baseT_Half |
3125 SUPPORTED_100baseT_Half |
3126 SUPPORTED_10baseT_Half);
3127 }
3128
3129 /* Find PHY if any */
3130 err = emac_init_phy(dev);
3131 if (err != 0)
3132 goto err_detach_tah;
3133
3134 if (dev->tah_dev) {
3135 ndev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG;
3136 ndev->features |= ndev->hw_features | NETIF_F_RXCSUM;
3137 }
3138 ndev->watchdog_timeo = 5 * HZ;
3139 if (emac_phy_supports_gige(dev->phy_mode)) {
3140 ndev->netdev_ops = &emac_gige_netdev_ops;
3141 dev->commac.ops = &emac_commac_sg_ops;
3142 } else
3143 ndev->netdev_ops = &emac_netdev_ops;
3144 ndev->ethtool_ops = &emac_ethtool_ops;
3145
3146 /* MTU range: 46 - 1500 or whatever is in OF */
3147 ndev->min_mtu = EMAC_MIN_MTU;
3148 ndev->max_mtu = dev->max_mtu;
3149
3150 netif_carrier_off(ndev);
3151
3152 err = devm_register_netdev(&ofdev->dev, ndev);
3153 if (err) {
3154 printk(KERN_ERR "%pOF: failed to register net device (%d)!\n",
3155 np, err);
3156 goto err_detach_tah;
3157 }
3158
3159 /* Set our drvdata last as we don't want them visible until we are
3160 * fully initialized
3161 */
3162 wmb();
3163 platform_set_drvdata(ofdev, dev);
3164
3165 printk(KERN_INFO "%s: EMAC-%d %pOF, MAC %pM\n",
3166 ndev->name, dev->cell_index, np, ndev->dev_addr);
3167
3168 if (dev->phy_mode == PHY_INTERFACE_MODE_SGMII)
3169 printk(KERN_NOTICE "%s: in SGMII mode\n", ndev->name);
3170
3171 if (dev->phy.address >= 0)
3172 printk("%s: found %s PHY (0x%02x)\n", ndev->name,
3173 dev->phy.def->name, dev->phy.address);
3174
3175 /* Life is good */
3176 return 0;
3177
3178 /* I have a bad feeling about this ... */
3179
3180 err_detach_tah:
3181 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
3182 tah_detach(dev->tah_dev, dev->tah_port);
3183 err_detach_rgmii:
3184 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
3185 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
3186 err_detach_zmii:
3187 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
3188 zmii_detach(dev->zmii_dev, dev->zmii_port);
3189 err_unreg_commac:
3190 mal_unregister_commac(dev->mal, &dev->commac);
3191 err_rel_deps:
3192 emac_put_deps(dev);
3193 err_gone:
3194 if (blist)
3195 *blist = NULL;
3196 return err;
3197}
3198
3199static void emac_remove(struct platform_device *ofdev)
3200{
3201 struct emac_instance *dev = platform_get_drvdata(ofdev);
3202
3203 DBG(dev, "remove" NL);
3204
3205 cancel_work_sync(&dev->reset_work);
3206
3207 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
3208 tah_detach(dev->tah_dev, dev->tah_port);
3209 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
3210 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
3211 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
3212 zmii_detach(dev->zmii_dev, dev->zmii_port);
3213
3214 busy_phy_map &= ~(1 << dev->phy.address);
3215 DBG(dev, "busy_phy_map now %#x" NL, busy_phy_map);
3216
3217 mal_unregister_commac(dev->mal, &dev->commac);
3218 emac_put_deps(dev);
3219}
3220
3221/* XXX Features in here should be replaced by properties... */
3222static const struct of_device_id emac_match[] =
3223{
3224 {
3225 .type = "network",
3226 .compatible = "ibm,emac",
3227 },
3228 {
3229 .type = "network",
3230 .compatible = "ibm,emac4",
3231 },
3232 {
3233 .type = "network",
3234 .compatible = "ibm,emac4sync",
3235 },
3236 {},
3237};
3238MODULE_DEVICE_TABLE(of, emac_match);
3239
3240static struct platform_driver emac_driver = {
3241 .driver = {
3242 .name = "emac",
3243 .of_match_table = emac_match,
3244 },
3245 .probe = emac_probe,
3246 .remove = emac_remove,
3247};
3248
3249static void __init emac_make_bootlist(void)
3250{
3251 struct device_node *np = NULL;
3252 int j, max, i = 0;
3253 int cell_indices[EMAC_BOOT_LIST_SIZE];
3254
3255 /* Collect EMACs */
3256 while((np = of_find_all_nodes(np)) != NULL) {
3257 u32 idx;
3258
3259 if (of_match_node(emac_match, np) == NULL)
3260 continue;
3261 if (of_property_read_bool(np, "unused"))
3262 continue;
3263 if (of_property_read_u32(np, "cell-index", &idx))
3264 continue;
3265 cell_indices[i] = idx;
3266 emac_boot_list[i++] = of_node_get(np);
3267 if (i >= EMAC_BOOT_LIST_SIZE) {
3268 of_node_put(np);
3269 break;
3270 }
3271 }
3272 max = i;
3273
3274 /* Bubble sort them (doh, what a creative algorithm :-) */
3275 for (i = 0; max > 1 && (i < (max - 1)); i++)
3276 for (j = i; j < max; j++) {
3277 if (cell_indices[i] > cell_indices[j]) {
3278 swap(emac_boot_list[i], emac_boot_list[j]);
3279 swap(cell_indices[i], cell_indices[j]);
3280 }
3281 }
3282}
3283
3284static int __init emac_init(void)
3285{
3286 int rc;
3287
3288 printk(KERN_INFO DRV_DESC ", version " DRV_VERSION "\n");
3289
3290 /* Build EMAC boot list */
3291 emac_make_bootlist();
3292
3293 /* Init submodules */
3294 rc = mal_init();
3295 if (rc)
3296 goto err;
3297 rc = zmii_init();
3298 if (rc)
3299 goto err_mal;
3300 rc = rgmii_init();
3301 if (rc)
3302 goto err_zmii;
3303 rc = tah_init();
3304 if (rc)
3305 goto err_rgmii;
3306 rc = platform_driver_register(&emac_driver);
3307 if (rc)
3308 goto err_tah;
3309
3310 return 0;
3311
3312 err_tah:
3313 tah_exit();
3314 err_rgmii:
3315 rgmii_exit();
3316 err_zmii:
3317 zmii_exit();
3318 err_mal:
3319 mal_exit();
3320 err:
3321 return rc;
3322}
3323
3324static void __exit emac_exit(void)
3325{
3326 int i;
3327
3328 platform_driver_unregister(&emac_driver);
3329
3330 tah_exit();
3331 rgmii_exit();
3332 zmii_exit();
3333 mal_exit();
3334
3335 /* Destroy EMAC boot list */
3336 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
3337 of_node_put(emac_boot_list[i]);
3338}
3339
3340module_init(emac_init);
3341module_exit(emac_exit);
1/*
2 * drivers/net/ethernet/ibm/emac/core.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller.
5 *
6 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
7 * <benh@kernel.crashing.org>
8 *
9 * Based on the arch/ppc version of the driver:
10 *
11 * Copyright (c) 2004, 2005 Zultys Technologies.
12 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
13 *
14 * Based on original work by
15 * Matt Porter <mporter@kernel.crashing.org>
16 * (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
17 * Armin Kuster <akuster@mvista.com>
18 * Johnnie Peters <jpeters@mvista.com>
19 *
20 * This program is free software; you can redistribute it and/or modify it
21 * under the terms of the GNU General Public License as published by the
22 * Free Software Foundation; either version 2 of the License, or (at your
23 * option) any later version.
24 *
25 */
26
27#include <linux/module.h>
28#include <linux/sched.h>
29#include <linux/string.h>
30#include <linux/errno.h>
31#include <linux/delay.h>
32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/etherdevice.h>
35#include <linux/skbuff.h>
36#include <linux/crc32.h>
37#include <linux/ethtool.h>
38#include <linux/mii.h>
39#include <linux/bitops.h>
40#include <linux/workqueue.h>
41#include <linux/of.h>
42#include <linux/of_net.h>
43#include <linux/slab.h>
44
45#include <asm/processor.h>
46#include <asm/io.h>
47#include <asm/dma.h>
48#include <asm/uaccess.h>
49#include <asm/dcr.h>
50#include <asm/dcr-regs.h>
51
52#include "core.h"
53
54/*
55 * Lack of dma_unmap_???? calls is intentional.
56 *
57 * API-correct usage requires additional support state information to be
58 * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to
59 * EMAC design (e.g. TX buffer passed from network stack can be split into
60 * several BDs, dma_map_single/dma_map_page can be used to map particular BD),
61 * maintaining such information will add additional overhead.
62 * Current DMA API implementation for 4xx processors only ensures cache coherency
63 * and dma_unmap_???? routines are empty and are likely to stay this way.
64 * I decided to omit dma_unmap_??? calls because I don't want to add additional
65 * complexity just for the sake of following some abstract API, when it doesn't
66 * add any real benefit to the driver. I understand that this decision maybe
67 * controversial, but I really tried to make code API-correct and efficient
68 * at the same time and didn't come up with code I liked :(. --ebs
69 */
70
71#define DRV_NAME "emac"
72#define DRV_VERSION "3.54"
73#define DRV_DESC "PPC 4xx OCP EMAC driver"
74
75MODULE_DESCRIPTION(DRV_DESC);
76MODULE_AUTHOR
77 ("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>");
78MODULE_LICENSE("GPL");
79
80/*
81 * PPC64 doesn't (yet) have a cacheable_memcpy
82 */
83#ifdef CONFIG_PPC64
84#define cacheable_memcpy(d,s,n) memcpy((d),(s),(n))
85#endif
86
87/* minimum number of free TX descriptors required to wake up TX process */
88#define EMAC_TX_WAKEUP_THRESH (NUM_TX_BUFF / 4)
89
90/* If packet size is less than this number, we allocate small skb and copy packet
91 * contents into it instead of just sending original big skb up
92 */
93#define EMAC_RX_COPY_THRESH CONFIG_IBM_EMAC_RX_COPY_THRESHOLD
94
95/* Since multiple EMACs share MDIO lines in various ways, we need
96 * to avoid re-using the same PHY ID in cases where the arch didn't
97 * setup precise phy_map entries
98 *
99 * XXX This is something that needs to be reworked as we can have multiple
100 * EMAC "sets" (multiple ASICs containing several EMACs) though we can
101 * probably require in that case to have explicit PHY IDs in the device-tree
102 */
103static u32 busy_phy_map;
104static DEFINE_MUTEX(emac_phy_map_lock);
105
106/* This is the wait queue used to wait on any event related to probe, that
107 * is discovery of MALs, other EMACs, ZMII/RGMIIs, etc...
108 */
109static DECLARE_WAIT_QUEUE_HEAD(emac_probe_wait);
110
111/* Having stable interface names is a doomed idea. However, it would be nice
112 * if we didn't have completely random interface names at boot too :-) It's
113 * just a matter of making everybody's life easier. Since we are doing
114 * threaded probing, it's a bit harder though. The base idea here is that
115 * we make up a list of all emacs in the device-tree before we register the
116 * driver. Every emac will then wait for the previous one in the list to
117 * initialize before itself. We should also keep that list ordered by
118 * cell_index.
119 * That list is only 4 entries long, meaning that additional EMACs don't
120 * get ordering guarantees unless EMAC_BOOT_LIST_SIZE is increased.
121 */
122
123#define EMAC_BOOT_LIST_SIZE 4
124static struct device_node *emac_boot_list[EMAC_BOOT_LIST_SIZE];
125
126/* How long should I wait for dependent devices ? */
127#define EMAC_PROBE_DEP_TIMEOUT (HZ * 5)
128
129/* I don't want to litter system log with timeout errors
130 * when we have brain-damaged PHY.
131 */
132static inline void emac_report_timeout_error(struct emac_instance *dev,
133 const char *error)
134{
135 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX |
136 EMAC_FTR_460EX_PHY_CLK_FIX |
137 EMAC_FTR_440EP_PHY_CLK_FIX))
138 DBG(dev, "%s" NL, error);
139 else if (net_ratelimit())
140 printk(KERN_ERR "%s: %s\n", dev->ofdev->dev.of_node->full_name,
141 error);
142}
143
144/* EMAC PHY clock workaround:
145 * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX,
146 * which allows controlling each EMAC clock
147 */
148static inline void emac_rx_clk_tx(struct emac_instance *dev)
149{
150#ifdef CONFIG_PPC_DCR_NATIVE
151 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
152 dcri_clrset(SDR0, SDR0_MFR,
153 0, SDR0_MFR_ECS >> dev->cell_index);
154#endif
155}
156
157static inline void emac_rx_clk_default(struct emac_instance *dev)
158{
159#ifdef CONFIG_PPC_DCR_NATIVE
160 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
161 dcri_clrset(SDR0, SDR0_MFR,
162 SDR0_MFR_ECS >> dev->cell_index, 0);
163#endif
164}
165
166/* PHY polling intervals */
167#define PHY_POLL_LINK_ON HZ
168#define PHY_POLL_LINK_OFF (HZ / 5)
169
170/* Graceful stop timeouts in us.
171 * We should allow up to 1 frame time (full-duplex, ignoring collisions)
172 */
173#define STOP_TIMEOUT_10 1230
174#define STOP_TIMEOUT_100 124
175#define STOP_TIMEOUT_1000 13
176#define STOP_TIMEOUT_1000_JUMBO 73
177
178static unsigned char default_mcast_addr[] = {
179 0x01, 0x80, 0xC2, 0x00, 0x00, 0x01
180};
181
182/* Please, keep in sync with struct ibm_emac_stats/ibm_emac_error_stats */
183static const char emac_stats_keys[EMAC_ETHTOOL_STATS_COUNT][ETH_GSTRING_LEN] = {
184 "rx_packets", "rx_bytes", "tx_packets", "tx_bytes", "rx_packets_csum",
185 "tx_packets_csum", "tx_undo", "rx_dropped_stack", "rx_dropped_oom",
186 "rx_dropped_error", "rx_dropped_resize", "rx_dropped_mtu",
187 "rx_stopped", "rx_bd_errors", "rx_bd_overrun", "rx_bd_bad_packet",
188 "rx_bd_runt_packet", "rx_bd_short_event", "rx_bd_alignment_error",
189 "rx_bd_bad_fcs", "rx_bd_packet_too_long", "rx_bd_out_of_range",
190 "rx_bd_in_range", "rx_parity", "rx_fifo_overrun", "rx_overrun",
191 "rx_bad_packet", "rx_runt_packet", "rx_short_event",
192 "rx_alignment_error", "rx_bad_fcs", "rx_packet_too_long",
193 "rx_out_of_range", "rx_in_range", "tx_dropped", "tx_bd_errors",
194 "tx_bd_bad_fcs", "tx_bd_carrier_loss", "tx_bd_excessive_deferral",
195 "tx_bd_excessive_collisions", "tx_bd_late_collision",
196 "tx_bd_multple_collisions", "tx_bd_single_collision",
197 "tx_bd_underrun", "tx_bd_sqe", "tx_parity", "tx_underrun", "tx_sqe",
198 "tx_errors"
199};
200
201static irqreturn_t emac_irq(int irq, void *dev_instance);
202static void emac_clean_tx_ring(struct emac_instance *dev);
203static void __emac_set_multicast_list(struct emac_instance *dev);
204
205static inline int emac_phy_supports_gige(int phy_mode)
206{
207 return phy_mode == PHY_MODE_GMII ||
208 phy_mode == PHY_MODE_RGMII ||
209 phy_mode == PHY_MODE_SGMII ||
210 phy_mode == PHY_MODE_TBI ||
211 phy_mode == PHY_MODE_RTBI;
212}
213
214static inline int emac_phy_gpcs(int phy_mode)
215{
216 return phy_mode == PHY_MODE_SGMII ||
217 phy_mode == PHY_MODE_TBI ||
218 phy_mode == PHY_MODE_RTBI;
219}
220
221static inline void emac_tx_enable(struct emac_instance *dev)
222{
223 struct emac_regs __iomem *p = dev->emacp;
224 u32 r;
225
226 DBG(dev, "tx_enable" NL);
227
228 r = in_be32(&p->mr0);
229 if (!(r & EMAC_MR0_TXE))
230 out_be32(&p->mr0, r | EMAC_MR0_TXE);
231}
232
233static void emac_tx_disable(struct emac_instance *dev)
234{
235 struct emac_regs __iomem *p = dev->emacp;
236 u32 r;
237
238 DBG(dev, "tx_disable" NL);
239
240 r = in_be32(&p->mr0);
241 if (r & EMAC_MR0_TXE) {
242 int n = dev->stop_timeout;
243 out_be32(&p->mr0, r & ~EMAC_MR0_TXE);
244 while (!(in_be32(&p->mr0) & EMAC_MR0_TXI) && n) {
245 udelay(1);
246 --n;
247 }
248 if (unlikely(!n))
249 emac_report_timeout_error(dev, "TX disable timeout");
250 }
251}
252
253static void emac_rx_enable(struct emac_instance *dev)
254{
255 struct emac_regs __iomem *p = dev->emacp;
256 u32 r;
257
258 if (unlikely(test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags)))
259 goto out;
260
261 DBG(dev, "rx_enable" NL);
262
263 r = in_be32(&p->mr0);
264 if (!(r & EMAC_MR0_RXE)) {
265 if (unlikely(!(r & EMAC_MR0_RXI))) {
266 /* Wait if previous async disable is still in progress */
267 int n = dev->stop_timeout;
268 while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
269 udelay(1);
270 --n;
271 }
272 if (unlikely(!n))
273 emac_report_timeout_error(dev,
274 "RX disable timeout");
275 }
276 out_be32(&p->mr0, r | EMAC_MR0_RXE);
277 }
278 out:
279 ;
280}
281
282static void emac_rx_disable(struct emac_instance *dev)
283{
284 struct emac_regs __iomem *p = dev->emacp;
285 u32 r;
286
287 DBG(dev, "rx_disable" NL);
288
289 r = in_be32(&p->mr0);
290 if (r & EMAC_MR0_RXE) {
291 int n = dev->stop_timeout;
292 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
293 while (!(in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
294 udelay(1);
295 --n;
296 }
297 if (unlikely(!n))
298 emac_report_timeout_error(dev, "RX disable timeout");
299 }
300}
301
302static inline void emac_netif_stop(struct emac_instance *dev)
303{
304 netif_tx_lock_bh(dev->ndev);
305 netif_addr_lock(dev->ndev);
306 dev->no_mcast = 1;
307 netif_addr_unlock(dev->ndev);
308 netif_tx_unlock_bh(dev->ndev);
309 dev->ndev->trans_start = jiffies; /* prevent tx timeout */
310 mal_poll_disable(dev->mal, &dev->commac);
311 netif_tx_disable(dev->ndev);
312}
313
314static inline void emac_netif_start(struct emac_instance *dev)
315{
316 netif_tx_lock_bh(dev->ndev);
317 netif_addr_lock(dev->ndev);
318 dev->no_mcast = 0;
319 if (dev->mcast_pending && netif_running(dev->ndev))
320 __emac_set_multicast_list(dev);
321 netif_addr_unlock(dev->ndev);
322 netif_tx_unlock_bh(dev->ndev);
323
324 netif_wake_queue(dev->ndev);
325
326 /* NOTE: unconditional netif_wake_queue is only appropriate
327 * so long as all callers are assured to have free tx slots
328 * (taken from tg3... though the case where that is wrong is
329 * not terribly harmful)
330 */
331 mal_poll_enable(dev->mal, &dev->commac);
332}
333
334static inline void emac_rx_disable_async(struct emac_instance *dev)
335{
336 struct emac_regs __iomem *p = dev->emacp;
337 u32 r;
338
339 DBG(dev, "rx_disable_async" NL);
340
341 r = in_be32(&p->mr0);
342 if (r & EMAC_MR0_RXE)
343 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
344}
345
346static int emac_reset(struct emac_instance *dev)
347{
348 struct emac_regs __iomem *p = dev->emacp;
349 int n = 20;
350
351 DBG(dev, "reset" NL);
352
353 if (!dev->reset_failed) {
354 /* 40x erratum suggests stopping RX channel before reset,
355 * we stop TX as well
356 */
357 emac_rx_disable(dev);
358 emac_tx_disable(dev);
359 }
360
361#ifdef CONFIG_PPC_DCR_NATIVE
362 /* Enable internal clock source */
363 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX))
364 dcri_clrset(SDR0, SDR0_ETH_CFG,
365 0, SDR0_ETH_CFG_ECS << dev->cell_index);
366#endif
367
368 out_be32(&p->mr0, EMAC_MR0_SRST);
369 while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n)
370 --n;
371
372#ifdef CONFIG_PPC_DCR_NATIVE
373 /* Enable external clock source */
374 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX))
375 dcri_clrset(SDR0, SDR0_ETH_CFG,
376 SDR0_ETH_CFG_ECS << dev->cell_index, 0);
377#endif
378
379 if (n) {
380 dev->reset_failed = 0;
381 return 0;
382 } else {
383 emac_report_timeout_error(dev, "reset timeout");
384 dev->reset_failed = 1;
385 return -ETIMEDOUT;
386 }
387}
388
389static void emac_hash_mc(struct emac_instance *dev)
390{
391 const int regs = EMAC_XAHT_REGS(dev);
392 u32 *gaht_base = emac_gaht_base(dev);
393 u32 gaht_temp[regs];
394 struct netdev_hw_addr *ha;
395 int i;
396
397 DBG(dev, "hash_mc %d" NL, netdev_mc_count(dev->ndev));
398
399 memset(gaht_temp, 0, sizeof (gaht_temp));
400
401 netdev_for_each_mc_addr(ha, dev->ndev) {
402 int slot, reg, mask;
403 DBG2(dev, "mc %pM" NL, ha->addr);
404
405 slot = EMAC_XAHT_CRC_TO_SLOT(dev,
406 ether_crc(ETH_ALEN, ha->addr));
407 reg = EMAC_XAHT_SLOT_TO_REG(dev, slot);
408 mask = EMAC_XAHT_SLOT_TO_MASK(dev, slot);
409
410 gaht_temp[reg] |= mask;
411 }
412
413 for (i = 0; i < regs; i++)
414 out_be32(gaht_base + i, gaht_temp[i]);
415}
416
417static inline u32 emac_iff2rmr(struct net_device *ndev)
418{
419 struct emac_instance *dev = netdev_priv(ndev);
420 u32 r;
421
422 r = EMAC_RMR_SP | EMAC_RMR_SFCS | EMAC_RMR_IAE | EMAC_RMR_BAE;
423
424 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
425 r |= EMAC4_RMR_BASE;
426 else
427 r |= EMAC_RMR_BASE;
428
429 if (ndev->flags & IFF_PROMISC)
430 r |= EMAC_RMR_PME;
431 else if (ndev->flags & IFF_ALLMULTI ||
432 (netdev_mc_count(ndev) > EMAC_XAHT_SLOTS(dev)))
433 r |= EMAC_RMR_PMME;
434 else if (!netdev_mc_empty(ndev))
435 r |= EMAC_RMR_MAE;
436
437 if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) {
438 r &= ~EMAC4_RMR_MJS_MASK;
439 r |= EMAC4_RMR_MJS(ndev->mtu);
440 }
441
442 return r;
443}
444
445static u32 __emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
446{
447 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC_MR1_TR0_MULT;
448
449 DBG2(dev, "__emac_calc_base_mr1" NL);
450
451 switch(tx_size) {
452 case 2048:
453 ret |= EMAC_MR1_TFS_2K;
454 break;
455 default:
456 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n",
457 dev->ndev->name, tx_size);
458 }
459
460 switch(rx_size) {
461 case 16384:
462 ret |= EMAC_MR1_RFS_16K;
463 break;
464 case 4096:
465 ret |= EMAC_MR1_RFS_4K;
466 break;
467 default:
468 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
469 dev->ndev->name, rx_size);
470 }
471
472 return ret;
473}
474
475static u32 __emac4_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
476{
477 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC4_MR1_TR |
478 EMAC4_MR1_OBCI(dev->opb_bus_freq / 1000000);
479
480 DBG2(dev, "__emac4_calc_base_mr1" NL);
481
482 switch(tx_size) {
483 case 16384:
484 ret |= EMAC4_MR1_TFS_16K;
485 break;
486 case 4096:
487 ret |= EMAC4_MR1_TFS_4K;
488 break;
489 case 2048:
490 ret |= EMAC4_MR1_TFS_2K;
491 break;
492 default:
493 printk(KERN_WARNING "%s: Unknown Tx FIFO size %d\n",
494 dev->ndev->name, tx_size);
495 }
496
497 switch(rx_size) {
498 case 16384:
499 ret |= EMAC4_MR1_RFS_16K;
500 break;
501 case 4096:
502 ret |= EMAC4_MR1_RFS_4K;
503 break;
504 case 2048:
505 ret |= EMAC4_MR1_RFS_2K;
506 break;
507 default:
508 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
509 dev->ndev->name, rx_size);
510 }
511
512 return ret;
513}
514
515static u32 emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
516{
517 return emac_has_feature(dev, EMAC_FTR_EMAC4) ?
518 __emac4_calc_base_mr1(dev, tx_size, rx_size) :
519 __emac_calc_base_mr1(dev, tx_size, rx_size);
520}
521
522static inline u32 emac_calc_trtr(struct emac_instance *dev, unsigned int size)
523{
524 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
525 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT_EMAC4;
526 else
527 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT;
528}
529
530static inline u32 emac_calc_rwmr(struct emac_instance *dev,
531 unsigned int low, unsigned int high)
532{
533 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
534 return (low << 22) | ( (high & 0x3ff) << 6);
535 else
536 return (low << 23) | ( (high & 0x1ff) << 7);
537}
538
539static int emac_configure(struct emac_instance *dev)
540{
541 struct emac_regs __iomem *p = dev->emacp;
542 struct net_device *ndev = dev->ndev;
543 int tx_size, rx_size, link = netif_carrier_ok(dev->ndev);
544 u32 r, mr1 = 0;
545
546 DBG(dev, "configure" NL);
547
548 if (!link) {
549 out_be32(&p->mr1, in_be32(&p->mr1)
550 | EMAC_MR1_FDE | EMAC_MR1_ILE);
551 udelay(100);
552 } else if (emac_reset(dev) < 0)
553 return -ETIMEDOUT;
554
555 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
556 tah_reset(dev->tah_dev);
557
558 DBG(dev, " link = %d duplex = %d, pause = %d, asym_pause = %d\n",
559 link, dev->phy.duplex, dev->phy.pause, dev->phy.asym_pause);
560
561 /* Default fifo sizes */
562 tx_size = dev->tx_fifo_size;
563 rx_size = dev->rx_fifo_size;
564
565 /* No link, force loopback */
566 if (!link)
567 mr1 = EMAC_MR1_FDE | EMAC_MR1_ILE;
568
569 /* Check for full duplex */
570 else if (dev->phy.duplex == DUPLEX_FULL)
571 mr1 |= EMAC_MR1_FDE | EMAC_MR1_MWSW_001;
572
573 /* Adjust fifo sizes, mr1 and timeouts based on link speed */
574 dev->stop_timeout = STOP_TIMEOUT_10;
575 switch (dev->phy.speed) {
576 case SPEED_1000:
577 if (emac_phy_gpcs(dev->phy.mode)) {
578 mr1 |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_MF_IPPA(
579 (dev->phy.gpcs_address != 0xffffffff) ?
580 dev->phy.gpcs_address : dev->phy.address);
581
582 /* Put some arbitrary OUI, Manuf & Rev IDs so we can
583 * identify this GPCS PHY later.
584 */
585 out_be32(&p->u1.emac4.ipcr, 0xdeadbeef);
586 } else
587 mr1 |= EMAC_MR1_MF_1000;
588
589 /* Extended fifo sizes */
590 tx_size = dev->tx_fifo_size_gige;
591 rx_size = dev->rx_fifo_size_gige;
592
593 if (dev->ndev->mtu > ETH_DATA_LEN) {
594 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
595 mr1 |= EMAC4_MR1_JPSM;
596 else
597 mr1 |= EMAC_MR1_JPSM;
598 dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO;
599 } else
600 dev->stop_timeout = STOP_TIMEOUT_1000;
601 break;
602 case SPEED_100:
603 mr1 |= EMAC_MR1_MF_100;
604 dev->stop_timeout = STOP_TIMEOUT_100;
605 break;
606 default: /* make gcc happy */
607 break;
608 }
609
610 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
611 rgmii_set_speed(dev->rgmii_dev, dev->rgmii_port,
612 dev->phy.speed);
613 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
614 zmii_set_speed(dev->zmii_dev, dev->zmii_port, dev->phy.speed);
615
616 /* on 40x erratum forces us to NOT use integrated flow control,
617 * let's hope it works on 44x ;)
618 */
619 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x) &&
620 dev->phy.duplex == DUPLEX_FULL) {
621 if (dev->phy.pause)
622 mr1 |= EMAC_MR1_EIFC | EMAC_MR1_APP;
623 else if (dev->phy.asym_pause)
624 mr1 |= EMAC_MR1_APP;
625 }
626
627 /* Add base settings & fifo sizes & program MR1 */
628 mr1 |= emac_calc_base_mr1(dev, tx_size, rx_size);
629 out_be32(&p->mr1, mr1);
630
631 /* Set individual MAC address */
632 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
633 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
634 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
635 ndev->dev_addr[5]);
636
637 /* VLAN Tag Protocol ID */
638 out_be32(&p->vtpid, 0x8100);
639
640 /* Receive mode register */
641 r = emac_iff2rmr(ndev);
642 if (r & EMAC_RMR_MAE)
643 emac_hash_mc(dev);
644 out_be32(&p->rmr, r);
645
646 /* FIFOs thresholds */
647 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
648 r = EMAC4_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
649 tx_size / 2 / dev->fifo_entry_size);
650 else
651 r = EMAC_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
652 tx_size / 2 / dev->fifo_entry_size);
653 out_be32(&p->tmr1, r);
654 out_be32(&p->trtr, emac_calc_trtr(dev, tx_size / 2));
655
656 /* PAUSE frame is sent when RX FIFO reaches its high-water mark,
657 there should be still enough space in FIFO to allow the our link
658 partner time to process this frame and also time to send PAUSE
659 frame itself.
660
661 Here is the worst case scenario for the RX FIFO "headroom"
662 (from "The Switch Book") (100Mbps, without preamble, inter-frame gap):
663
664 1) One maximum-length frame on TX 1522 bytes
665 2) One PAUSE frame time 64 bytes
666 3) PAUSE frame decode time allowance 64 bytes
667 4) One maximum-length frame on RX 1522 bytes
668 5) Round-trip propagation delay of the link (100Mb) 15 bytes
669 ----------
670 3187 bytes
671
672 I chose to set high-water mark to RX_FIFO_SIZE / 4 (1024 bytes)
673 low-water mark to RX_FIFO_SIZE / 8 (512 bytes)
674 */
675 r = emac_calc_rwmr(dev, rx_size / 8 / dev->fifo_entry_size,
676 rx_size / 4 / dev->fifo_entry_size);
677 out_be32(&p->rwmr, r);
678
679 /* Set PAUSE timer to the maximum */
680 out_be32(&p->ptr, 0xffff);
681
682 /* IRQ sources */
683 r = EMAC_ISR_OVR | EMAC_ISR_BP | EMAC_ISR_SE |
684 EMAC_ISR_ALE | EMAC_ISR_BFCS | EMAC_ISR_PTLE | EMAC_ISR_ORE |
685 EMAC_ISR_IRE | EMAC_ISR_TE;
686 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
687 r |= EMAC4_ISR_TXPE | EMAC4_ISR_RXPE /* | EMAC4_ISR_TXUE |
688 EMAC4_ISR_RXOE | */;
689 out_be32(&p->iser, r);
690
691 /* We need to take GPCS PHY out of isolate mode after EMAC reset */
692 if (emac_phy_gpcs(dev->phy.mode)) {
693 if (dev->phy.gpcs_address != 0xffffffff)
694 emac_mii_reset_gpcs(&dev->phy);
695 else
696 emac_mii_reset_phy(&dev->phy);
697 }
698
699 return 0;
700}
701
702static void emac_reinitialize(struct emac_instance *dev)
703{
704 DBG(dev, "reinitialize" NL);
705
706 emac_netif_stop(dev);
707 if (!emac_configure(dev)) {
708 emac_tx_enable(dev);
709 emac_rx_enable(dev);
710 }
711 emac_netif_start(dev);
712}
713
714static void emac_full_tx_reset(struct emac_instance *dev)
715{
716 DBG(dev, "full_tx_reset" NL);
717
718 emac_tx_disable(dev);
719 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
720 emac_clean_tx_ring(dev);
721 dev->tx_cnt = dev->tx_slot = dev->ack_slot = 0;
722
723 emac_configure(dev);
724
725 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
726 emac_tx_enable(dev);
727 emac_rx_enable(dev);
728}
729
730static void emac_reset_work(struct work_struct *work)
731{
732 struct emac_instance *dev = container_of(work, struct emac_instance, reset_work);
733
734 DBG(dev, "reset_work" NL);
735
736 mutex_lock(&dev->link_lock);
737 if (dev->opened) {
738 emac_netif_stop(dev);
739 emac_full_tx_reset(dev);
740 emac_netif_start(dev);
741 }
742 mutex_unlock(&dev->link_lock);
743}
744
745static void emac_tx_timeout(struct net_device *ndev)
746{
747 struct emac_instance *dev = netdev_priv(ndev);
748
749 DBG(dev, "tx_timeout" NL);
750
751 schedule_work(&dev->reset_work);
752}
753
754
755static inline int emac_phy_done(struct emac_instance *dev, u32 stacr)
756{
757 int done = !!(stacr & EMAC_STACR_OC);
758
759 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
760 done = !done;
761
762 return done;
763};
764
765static int __emac_mdio_read(struct emac_instance *dev, u8 id, u8 reg)
766{
767 struct emac_regs __iomem *p = dev->emacp;
768 u32 r = 0;
769 int n, err = -ETIMEDOUT;
770
771 mutex_lock(&dev->mdio_lock);
772
773 DBG2(dev, "mdio_read(%02x,%02x)" NL, id, reg);
774
775 /* Enable proper MDIO port */
776 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
777 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
778 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
779 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
780
781 /* Wait for management interface to become idle */
782 n = 20;
783 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
784 udelay(1);
785 if (!--n) {
786 DBG2(dev, " -> timeout wait idle\n");
787 goto bail;
788 }
789 }
790
791 /* Issue read command */
792 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
793 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
794 else
795 r = EMAC_STACR_BASE(dev->opb_bus_freq);
796 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
797 r |= EMAC_STACR_OC;
798 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
799 r |= EMACX_STACR_STAC_READ;
800 else
801 r |= EMAC_STACR_STAC_READ;
802 r |= (reg & EMAC_STACR_PRA_MASK)
803 | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT);
804 out_be32(&p->stacr, r);
805
806 /* Wait for read to complete */
807 n = 200;
808 while (!emac_phy_done(dev, (r = in_be32(&p->stacr)))) {
809 udelay(1);
810 if (!--n) {
811 DBG2(dev, " -> timeout wait complete\n");
812 goto bail;
813 }
814 }
815
816 if (unlikely(r & EMAC_STACR_PHYE)) {
817 DBG(dev, "mdio_read(%02x, %02x) failed" NL, id, reg);
818 err = -EREMOTEIO;
819 goto bail;
820 }
821
822 r = ((r >> EMAC_STACR_PHYD_SHIFT) & EMAC_STACR_PHYD_MASK);
823
824 DBG2(dev, "mdio_read -> %04x" NL, r);
825 err = 0;
826 bail:
827 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
828 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
829 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
830 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
831 mutex_unlock(&dev->mdio_lock);
832
833 return err == 0 ? r : err;
834}
835
836static void __emac_mdio_write(struct emac_instance *dev, u8 id, u8 reg,
837 u16 val)
838{
839 struct emac_regs __iomem *p = dev->emacp;
840 u32 r = 0;
841 int n, err = -ETIMEDOUT;
842
843 mutex_lock(&dev->mdio_lock);
844
845 DBG2(dev, "mdio_write(%02x,%02x,%04x)" NL, id, reg, val);
846
847 /* Enable proper MDIO port */
848 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
849 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
850 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
851 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
852
853 /* Wait for management interface to be idle */
854 n = 20;
855 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
856 udelay(1);
857 if (!--n) {
858 DBG2(dev, " -> timeout wait idle\n");
859 goto bail;
860 }
861 }
862
863 /* Issue write command */
864 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
865 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
866 else
867 r = EMAC_STACR_BASE(dev->opb_bus_freq);
868 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
869 r |= EMAC_STACR_OC;
870 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
871 r |= EMACX_STACR_STAC_WRITE;
872 else
873 r |= EMAC_STACR_STAC_WRITE;
874 r |= (reg & EMAC_STACR_PRA_MASK) |
875 ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) |
876 (val << EMAC_STACR_PHYD_SHIFT);
877 out_be32(&p->stacr, r);
878
879 /* Wait for write to complete */
880 n = 200;
881 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
882 udelay(1);
883 if (!--n) {
884 DBG2(dev, " -> timeout wait complete\n");
885 goto bail;
886 }
887 }
888 err = 0;
889 bail:
890 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
891 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
892 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
893 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
894 mutex_unlock(&dev->mdio_lock);
895}
896
897static int emac_mdio_read(struct net_device *ndev, int id, int reg)
898{
899 struct emac_instance *dev = netdev_priv(ndev);
900 int res;
901
902 res = __emac_mdio_read((dev->mdio_instance &&
903 dev->phy.gpcs_address != id) ?
904 dev->mdio_instance : dev,
905 (u8) id, (u8) reg);
906 return res;
907}
908
909static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val)
910{
911 struct emac_instance *dev = netdev_priv(ndev);
912
913 __emac_mdio_write((dev->mdio_instance &&
914 dev->phy.gpcs_address != id) ?
915 dev->mdio_instance : dev,
916 (u8) id, (u8) reg, (u16) val);
917}
918
919/* Tx lock BH */
920static void __emac_set_multicast_list(struct emac_instance *dev)
921{
922 struct emac_regs __iomem *p = dev->emacp;
923 u32 rmr = emac_iff2rmr(dev->ndev);
924
925 DBG(dev, "__multicast %08x" NL, rmr);
926
927 /* I decided to relax register access rules here to avoid
928 * full EMAC reset.
929 *
930 * There is a real problem with EMAC4 core if we use MWSW_001 bit
931 * in MR1 register and do a full EMAC reset.
932 * One TX BD status update is delayed and, after EMAC reset, it
933 * never happens, resulting in TX hung (it'll be recovered by TX
934 * timeout handler eventually, but this is just gross).
935 * So we either have to do full TX reset or try to cheat here :)
936 *
937 * The only required change is to RX mode register, so I *think* all
938 * we need is just to stop RX channel. This seems to work on all
939 * tested SoCs. --ebs
940 *
941 * If we need the full reset, we might just trigger the workqueue
942 * and do it async... a bit nasty but should work --BenH
943 */
944 dev->mcast_pending = 0;
945 emac_rx_disable(dev);
946 if (rmr & EMAC_RMR_MAE)
947 emac_hash_mc(dev);
948 out_be32(&p->rmr, rmr);
949 emac_rx_enable(dev);
950}
951
952/* Tx lock BH */
953static void emac_set_multicast_list(struct net_device *ndev)
954{
955 struct emac_instance *dev = netdev_priv(ndev);
956
957 DBG(dev, "multicast" NL);
958
959 BUG_ON(!netif_running(dev->ndev));
960
961 if (dev->no_mcast) {
962 dev->mcast_pending = 1;
963 return;
964 }
965 __emac_set_multicast_list(dev);
966}
967
968static int emac_resize_rx_ring(struct emac_instance *dev, int new_mtu)
969{
970 int rx_sync_size = emac_rx_sync_size(new_mtu);
971 int rx_skb_size = emac_rx_skb_size(new_mtu);
972 int i, ret = 0;
973 int mr1_jumbo_bit_change = 0;
974
975 mutex_lock(&dev->link_lock);
976 emac_netif_stop(dev);
977 emac_rx_disable(dev);
978 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
979
980 if (dev->rx_sg_skb) {
981 ++dev->estats.rx_dropped_resize;
982 dev_kfree_skb(dev->rx_sg_skb);
983 dev->rx_sg_skb = NULL;
984 }
985
986 /* Make a first pass over RX ring and mark BDs ready, dropping
987 * non-processed packets on the way. We need this as a separate pass
988 * to simplify error recovery in the case of allocation failure later.
989 */
990 for (i = 0; i < NUM_RX_BUFF; ++i) {
991 if (dev->rx_desc[i].ctrl & MAL_RX_CTRL_FIRST)
992 ++dev->estats.rx_dropped_resize;
993
994 dev->rx_desc[i].data_len = 0;
995 dev->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY |
996 (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
997 }
998
999 /* Reallocate RX ring only if bigger skb buffers are required */
1000 if (rx_skb_size <= dev->rx_skb_size)
1001 goto skip;
1002
1003 /* Second pass, allocate new skbs */
1004 for (i = 0; i < NUM_RX_BUFF; ++i) {
1005 struct sk_buff *skb = alloc_skb(rx_skb_size, GFP_ATOMIC);
1006 if (!skb) {
1007 ret = -ENOMEM;
1008 goto oom;
1009 }
1010
1011 BUG_ON(!dev->rx_skb[i]);
1012 dev_kfree_skb(dev->rx_skb[i]);
1013
1014 skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
1015 dev->rx_desc[i].data_ptr =
1016 dma_map_single(&dev->ofdev->dev, skb->data - 2, rx_sync_size,
1017 DMA_FROM_DEVICE) + 2;
1018 dev->rx_skb[i] = skb;
1019 }
1020 skip:
1021 /* Check if we need to change "Jumbo" bit in MR1 */
1022 if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) {
1023 mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) ||
1024 (dev->ndev->mtu > ETH_DATA_LEN);
1025 } else {
1026 mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) ^
1027 (dev->ndev->mtu > ETH_DATA_LEN);
1028 }
1029
1030 if (mr1_jumbo_bit_change) {
1031 /* This is to prevent starting RX channel in emac_rx_enable() */
1032 set_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1033
1034 dev->ndev->mtu = new_mtu;
1035 emac_full_tx_reset(dev);
1036 }
1037
1038 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(new_mtu));
1039 oom:
1040 /* Restart RX */
1041 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1042 dev->rx_slot = 0;
1043 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1044 emac_rx_enable(dev);
1045 emac_netif_start(dev);
1046 mutex_unlock(&dev->link_lock);
1047
1048 return ret;
1049}
1050
1051/* Process ctx, rtnl_lock semaphore */
1052static int emac_change_mtu(struct net_device *ndev, int new_mtu)
1053{
1054 struct emac_instance *dev = netdev_priv(ndev);
1055 int ret = 0;
1056
1057 if (new_mtu < EMAC_MIN_MTU || new_mtu > dev->max_mtu)
1058 return -EINVAL;
1059
1060 DBG(dev, "change_mtu(%d)" NL, new_mtu);
1061
1062 if (netif_running(ndev)) {
1063 /* Check if we really need to reinitialize RX ring */
1064 if (emac_rx_skb_size(ndev->mtu) != emac_rx_skb_size(new_mtu))
1065 ret = emac_resize_rx_ring(dev, new_mtu);
1066 }
1067
1068 if (!ret) {
1069 ndev->mtu = new_mtu;
1070 dev->rx_skb_size = emac_rx_skb_size(new_mtu);
1071 dev->rx_sync_size = emac_rx_sync_size(new_mtu);
1072 }
1073
1074 return ret;
1075}
1076
1077static void emac_clean_tx_ring(struct emac_instance *dev)
1078{
1079 int i;
1080
1081 for (i = 0; i < NUM_TX_BUFF; ++i) {
1082 if (dev->tx_skb[i]) {
1083 dev_kfree_skb(dev->tx_skb[i]);
1084 dev->tx_skb[i] = NULL;
1085 if (dev->tx_desc[i].ctrl & MAL_TX_CTRL_READY)
1086 ++dev->estats.tx_dropped;
1087 }
1088 dev->tx_desc[i].ctrl = 0;
1089 dev->tx_desc[i].data_ptr = 0;
1090 }
1091}
1092
1093static void emac_clean_rx_ring(struct emac_instance *dev)
1094{
1095 int i;
1096
1097 for (i = 0; i < NUM_RX_BUFF; ++i)
1098 if (dev->rx_skb[i]) {
1099 dev->rx_desc[i].ctrl = 0;
1100 dev_kfree_skb(dev->rx_skb[i]);
1101 dev->rx_skb[i] = NULL;
1102 dev->rx_desc[i].data_ptr = 0;
1103 }
1104
1105 if (dev->rx_sg_skb) {
1106 dev_kfree_skb(dev->rx_sg_skb);
1107 dev->rx_sg_skb = NULL;
1108 }
1109}
1110
1111static inline int emac_alloc_rx_skb(struct emac_instance *dev, int slot,
1112 gfp_t flags)
1113{
1114 struct sk_buff *skb = alloc_skb(dev->rx_skb_size, flags);
1115 if (unlikely(!skb))
1116 return -ENOMEM;
1117
1118 dev->rx_skb[slot] = skb;
1119 dev->rx_desc[slot].data_len = 0;
1120
1121 skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
1122 dev->rx_desc[slot].data_ptr =
1123 dma_map_single(&dev->ofdev->dev, skb->data - 2, dev->rx_sync_size,
1124 DMA_FROM_DEVICE) + 2;
1125 wmb();
1126 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1127 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1128
1129 return 0;
1130}
1131
1132static void emac_print_link_status(struct emac_instance *dev)
1133{
1134 if (netif_carrier_ok(dev->ndev))
1135 printk(KERN_INFO "%s: link is up, %d %s%s\n",
1136 dev->ndev->name, dev->phy.speed,
1137 dev->phy.duplex == DUPLEX_FULL ? "FDX" : "HDX",
1138 dev->phy.pause ? ", pause enabled" :
1139 dev->phy.asym_pause ? ", asymmetric pause enabled" : "");
1140 else
1141 printk(KERN_INFO "%s: link is down\n", dev->ndev->name);
1142}
1143
1144/* Process ctx, rtnl_lock semaphore */
1145static int emac_open(struct net_device *ndev)
1146{
1147 struct emac_instance *dev = netdev_priv(ndev);
1148 int err, i;
1149
1150 DBG(dev, "open" NL);
1151
1152 /* Setup error IRQ handler */
1153 err = request_irq(dev->emac_irq, emac_irq, 0, "EMAC", dev);
1154 if (err) {
1155 printk(KERN_ERR "%s: failed to request IRQ %d\n",
1156 ndev->name, dev->emac_irq);
1157 return err;
1158 }
1159
1160 /* Allocate RX ring */
1161 for (i = 0; i < NUM_RX_BUFF; ++i)
1162 if (emac_alloc_rx_skb(dev, i, GFP_KERNEL)) {
1163 printk(KERN_ERR "%s: failed to allocate RX ring\n",
1164 ndev->name);
1165 goto oom;
1166 }
1167
1168 dev->tx_cnt = dev->tx_slot = dev->ack_slot = dev->rx_slot = 0;
1169 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1170 dev->rx_sg_skb = NULL;
1171
1172 mutex_lock(&dev->link_lock);
1173 dev->opened = 1;
1174
1175 /* Start PHY polling now.
1176 */
1177 if (dev->phy.address >= 0) {
1178 int link_poll_interval;
1179 if (dev->phy.def->ops->poll_link(&dev->phy)) {
1180 dev->phy.def->ops->read_link(&dev->phy);
1181 emac_rx_clk_default(dev);
1182 netif_carrier_on(dev->ndev);
1183 link_poll_interval = PHY_POLL_LINK_ON;
1184 } else {
1185 emac_rx_clk_tx(dev);
1186 netif_carrier_off(dev->ndev);
1187 link_poll_interval = PHY_POLL_LINK_OFF;
1188 }
1189 dev->link_polling = 1;
1190 wmb();
1191 schedule_delayed_work(&dev->link_work, link_poll_interval);
1192 emac_print_link_status(dev);
1193 } else
1194 netif_carrier_on(dev->ndev);
1195
1196 /* Required for Pause packet support in EMAC */
1197 dev_mc_add_global(ndev, default_mcast_addr);
1198
1199 emac_configure(dev);
1200 mal_poll_add(dev->mal, &dev->commac);
1201 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
1202 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(ndev->mtu));
1203 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1204 emac_tx_enable(dev);
1205 emac_rx_enable(dev);
1206 emac_netif_start(dev);
1207
1208 mutex_unlock(&dev->link_lock);
1209
1210 return 0;
1211 oom:
1212 emac_clean_rx_ring(dev);
1213 free_irq(dev->emac_irq, dev);
1214
1215 return -ENOMEM;
1216}
1217
1218/* BHs disabled */
1219#if 0
1220static int emac_link_differs(struct emac_instance *dev)
1221{
1222 u32 r = in_be32(&dev->emacp->mr1);
1223
1224 int duplex = r & EMAC_MR1_FDE ? DUPLEX_FULL : DUPLEX_HALF;
1225 int speed, pause, asym_pause;
1226
1227 if (r & EMAC_MR1_MF_1000)
1228 speed = SPEED_1000;
1229 else if (r & EMAC_MR1_MF_100)
1230 speed = SPEED_100;
1231 else
1232 speed = SPEED_10;
1233
1234 switch (r & (EMAC_MR1_EIFC | EMAC_MR1_APP)) {
1235 case (EMAC_MR1_EIFC | EMAC_MR1_APP):
1236 pause = 1;
1237 asym_pause = 0;
1238 break;
1239 case EMAC_MR1_APP:
1240 pause = 0;
1241 asym_pause = 1;
1242 break;
1243 default:
1244 pause = asym_pause = 0;
1245 }
1246 return speed != dev->phy.speed || duplex != dev->phy.duplex ||
1247 pause != dev->phy.pause || asym_pause != dev->phy.asym_pause;
1248}
1249#endif
1250
1251static void emac_link_timer(struct work_struct *work)
1252{
1253 struct emac_instance *dev =
1254 container_of(to_delayed_work(work),
1255 struct emac_instance, link_work);
1256 int link_poll_interval;
1257
1258 mutex_lock(&dev->link_lock);
1259 DBG2(dev, "link timer" NL);
1260
1261 if (!dev->opened)
1262 goto bail;
1263
1264 if (dev->phy.def->ops->poll_link(&dev->phy)) {
1265 if (!netif_carrier_ok(dev->ndev)) {
1266 emac_rx_clk_default(dev);
1267 /* Get new link parameters */
1268 dev->phy.def->ops->read_link(&dev->phy);
1269
1270 netif_carrier_on(dev->ndev);
1271 emac_netif_stop(dev);
1272 emac_full_tx_reset(dev);
1273 emac_netif_start(dev);
1274 emac_print_link_status(dev);
1275 }
1276 link_poll_interval = PHY_POLL_LINK_ON;
1277 } else {
1278 if (netif_carrier_ok(dev->ndev)) {
1279 emac_rx_clk_tx(dev);
1280 netif_carrier_off(dev->ndev);
1281 netif_tx_disable(dev->ndev);
1282 emac_reinitialize(dev);
1283 emac_print_link_status(dev);
1284 }
1285 link_poll_interval = PHY_POLL_LINK_OFF;
1286 }
1287 schedule_delayed_work(&dev->link_work, link_poll_interval);
1288 bail:
1289 mutex_unlock(&dev->link_lock);
1290}
1291
1292static void emac_force_link_update(struct emac_instance *dev)
1293{
1294 netif_carrier_off(dev->ndev);
1295 smp_rmb();
1296 if (dev->link_polling) {
1297 cancel_delayed_work_sync(&dev->link_work);
1298 if (dev->link_polling)
1299 schedule_delayed_work(&dev->link_work, PHY_POLL_LINK_OFF);
1300 }
1301}
1302
1303/* Process ctx, rtnl_lock semaphore */
1304static int emac_close(struct net_device *ndev)
1305{
1306 struct emac_instance *dev = netdev_priv(ndev);
1307
1308 DBG(dev, "close" NL);
1309
1310 if (dev->phy.address >= 0) {
1311 dev->link_polling = 0;
1312 cancel_delayed_work_sync(&dev->link_work);
1313 }
1314 mutex_lock(&dev->link_lock);
1315 emac_netif_stop(dev);
1316 dev->opened = 0;
1317 mutex_unlock(&dev->link_lock);
1318
1319 emac_rx_disable(dev);
1320 emac_tx_disable(dev);
1321 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
1322 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
1323 mal_poll_del(dev->mal, &dev->commac);
1324
1325 emac_clean_tx_ring(dev);
1326 emac_clean_rx_ring(dev);
1327
1328 free_irq(dev->emac_irq, dev);
1329
1330 netif_carrier_off(ndev);
1331
1332 return 0;
1333}
1334
1335static inline u16 emac_tx_csum(struct emac_instance *dev,
1336 struct sk_buff *skb)
1337{
1338 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
1339 (skb->ip_summed == CHECKSUM_PARTIAL)) {
1340 ++dev->stats.tx_packets_csum;
1341 return EMAC_TX_CTRL_TAH_CSUM;
1342 }
1343 return 0;
1344}
1345
1346static inline int emac_xmit_finish(struct emac_instance *dev, int len)
1347{
1348 struct emac_regs __iomem *p = dev->emacp;
1349 struct net_device *ndev = dev->ndev;
1350
1351 /* Send the packet out. If the if makes a significant perf
1352 * difference, then we can store the TMR0 value in "dev"
1353 * instead
1354 */
1355 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
1356 out_be32(&p->tmr0, EMAC4_TMR0_XMIT);
1357 else
1358 out_be32(&p->tmr0, EMAC_TMR0_XMIT);
1359
1360 if (unlikely(++dev->tx_cnt == NUM_TX_BUFF)) {
1361 netif_stop_queue(ndev);
1362 DBG2(dev, "stopped TX queue" NL);
1363 }
1364
1365 ndev->trans_start = jiffies;
1366 ++dev->stats.tx_packets;
1367 dev->stats.tx_bytes += len;
1368
1369 return NETDEV_TX_OK;
1370}
1371
1372/* Tx lock BH */
1373static int emac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1374{
1375 struct emac_instance *dev = netdev_priv(ndev);
1376 unsigned int len = skb->len;
1377 int slot;
1378
1379 u16 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1380 MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb);
1381
1382 slot = dev->tx_slot++;
1383 if (dev->tx_slot == NUM_TX_BUFF) {
1384 dev->tx_slot = 0;
1385 ctrl |= MAL_TX_CTRL_WRAP;
1386 }
1387
1388 DBG2(dev, "xmit(%u) %d" NL, len, slot);
1389
1390 dev->tx_skb[slot] = skb;
1391 dev->tx_desc[slot].data_ptr = dma_map_single(&dev->ofdev->dev,
1392 skb->data, len,
1393 DMA_TO_DEVICE);
1394 dev->tx_desc[slot].data_len = (u16) len;
1395 wmb();
1396 dev->tx_desc[slot].ctrl = ctrl;
1397
1398 return emac_xmit_finish(dev, len);
1399}
1400
1401static inline int emac_xmit_split(struct emac_instance *dev, int slot,
1402 u32 pd, int len, int last, u16 base_ctrl)
1403{
1404 while (1) {
1405 u16 ctrl = base_ctrl;
1406 int chunk = min(len, MAL_MAX_TX_SIZE);
1407 len -= chunk;
1408
1409 slot = (slot + 1) % NUM_TX_BUFF;
1410
1411 if (last && !len)
1412 ctrl |= MAL_TX_CTRL_LAST;
1413 if (slot == NUM_TX_BUFF - 1)
1414 ctrl |= MAL_TX_CTRL_WRAP;
1415
1416 dev->tx_skb[slot] = NULL;
1417 dev->tx_desc[slot].data_ptr = pd;
1418 dev->tx_desc[slot].data_len = (u16) chunk;
1419 dev->tx_desc[slot].ctrl = ctrl;
1420 ++dev->tx_cnt;
1421
1422 if (!len)
1423 break;
1424
1425 pd += chunk;
1426 }
1427 return slot;
1428}
1429
1430/* Tx lock BH disabled (SG version for TAH equipped EMACs) */
1431static int emac_start_xmit_sg(struct sk_buff *skb, struct net_device *ndev)
1432{
1433 struct emac_instance *dev = netdev_priv(ndev);
1434 int nr_frags = skb_shinfo(skb)->nr_frags;
1435 int len = skb->len, chunk;
1436 int slot, i;
1437 u16 ctrl;
1438 u32 pd;
1439
1440 /* This is common "fast" path */
1441 if (likely(!nr_frags && len <= MAL_MAX_TX_SIZE))
1442 return emac_start_xmit(skb, ndev);
1443
1444 len -= skb->data_len;
1445
1446 /* Note, this is only an *estimation*, we can still run out of empty
1447 * slots because of the additional fragmentation into
1448 * MAL_MAX_TX_SIZE-sized chunks
1449 */
1450 if (unlikely(dev->tx_cnt + nr_frags + mal_tx_chunks(len) > NUM_TX_BUFF))
1451 goto stop_queue;
1452
1453 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1454 emac_tx_csum(dev, skb);
1455 slot = dev->tx_slot;
1456
1457 /* skb data */
1458 dev->tx_skb[slot] = NULL;
1459 chunk = min(len, MAL_MAX_TX_SIZE);
1460 dev->tx_desc[slot].data_ptr = pd =
1461 dma_map_single(&dev->ofdev->dev, skb->data, len, DMA_TO_DEVICE);
1462 dev->tx_desc[slot].data_len = (u16) chunk;
1463 len -= chunk;
1464 if (unlikely(len))
1465 slot = emac_xmit_split(dev, slot, pd + chunk, len, !nr_frags,
1466 ctrl);
1467 /* skb fragments */
1468 for (i = 0; i < nr_frags; ++i) {
1469 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
1470 len = skb_frag_size(frag);
1471
1472 if (unlikely(dev->tx_cnt + mal_tx_chunks(len) >= NUM_TX_BUFF))
1473 goto undo_frame;
1474
1475 pd = skb_frag_dma_map(&dev->ofdev->dev, frag, 0, len,
1476 DMA_TO_DEVICE);
1477
1478 slot = emac_xmit_split(dev, slot, pd, len, i == nr_frags - 1,
1479 ctrl);
1480 }
1481
1482 DBG2(dev, "xmit_sg(%u) %d - %d" NL, skb->len, dev->tx_slot, slot);
1483
1484 /* Attach skb to the last slot so we don't release it too early */
1485 dev->tx_skb[slot] = skb;
1486
1487 /* Send the packet out */
1488 if (dev->tx_slot == NUM_TX_BUFF - 1)
1489 ctrl |= MAL_TX_CTRL_WRAP;
1490 wmb();
1491 dev->tx_desc[dev->tx_slot].ctrl = ctrl;
1492 dev->tx_slot = (slot + 1) % NUM_TX_BUFF;
1493
1494 return emac_xmit_finish(dev, skb->len);
1495
1496 undo_frame:
1497 /* Well, too bad. Our previous estimation was overly optimistic.
1498 * Undo everything.
1499 */
1500 while (slot != dev->tx_slot) {
1501 dev->tx_desc[slot].ctrl = 0;
1502 --dev->tx_cnt;
1503 if (--slot < 0)
1504 slot = NUM_TX_BUFF - 1;
1505 }
1506 ++dev->estats.tx_undo;
1507
1508 stop_queue:
1509 netif_stop_queue(ndev);
1510 DBG2(dev, "stopped TX queue" NL);
1511 return NETDEV_TX_BUSY;
1512}
1513
1514/* Tx lock BHs */
1515static void emac_parse_tx_error(struct emac_instance *dev, u16 ctrl)
1516{
1517 struct emac_error_stats *st = &dev->estats;
1518
1519 DBG(dev, "BD TX error %04x" NL, ctrl);
1520
1521 ++st->tx_bd_errors;
1522 if (ctrl & EMAC_TX_ST_BFCS)
1523 ++st->tx_bd_bad_fcs;
1524 if (ctrl & EMAC_TX_ST_LCS)
1525 ++st->tx_bd_carrier_loss;
1526 if (ctrl & EMAC_TX_ST_ED)
1527 ++st->tx_bd_excessive_deferral;
1528 if (ctrl & EMAC_TX_ST_EC)
1529 ++st->tx_bd_excessive_collisions;
1530 if (ctrl & EMAC_TX_ST_LC)
1531 ++st->tx_bd_late_collision;
1532 if (ctrl & EMAC_TX_ST_MC)
1533 ++st->tx_bd_multple_collisions;
1534 if (ctrl & EMAC_TX_ST_SC)
1535 ++st->tx_bd_single_collision;
1536 if (ctrl & EMAC_TX_ST_UR)
1537 ++st->tx_bd_underrun;
1538 if (ctrl & EMAC_TX_ST_SQE)
1539 ++st->tx_bd_sqe;
1540}
1541
1542static void emac_poll_tx(void *param)
1543{
1544 struct emac_instance *dev = param;
1545 u32 bad_mask;
1546
1547 DBG2(dev, "poll_tx, %d %d" NL, dev->tx_cnt, dev->ack_slot);
1548
1549 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
1550 bad_mask = EMAC_IS_BAD_TX_TAH;
1551 else
1552 bad_mask = EMAC_IS_BAD_TX;
1553
1554 netif_tx_lock_bh(dev->ndev);
1555 if (dev->tx_cnt) {
1556 u16 ctrl;
1557 int slot = dev->ack_slot, n = 0;
1558 again:
1559 ctrl = dev->tx_desc[slot].ctrl;
1560 if (!(ctrl & MAL_TX_CTRL_READY)) {
1561 struct sk_buff *skb = dev->tx_skb[slot];
1562 ++n;
1563
1564 if (skb) {
1565 dev_kfree_skb(skb);
1566 dev->tx_skb[slot] = NULL;
1567 }
1568 slot = (slot + 1) % NUM_TX_BUFF;
1569
1570 if (unlikely(ctrl & bad_mask))
1571 emac_parse_tx_error(dev, ctrl);
1572
1573 if (--dev->tx_cnt)
1574 goto again;
1575 }
1576 if (n) {
1577 dev->ack_slot = slot;
1578 if (netif_queue_stopped(dev->ndev) &&
1579 dev->tx_cnt < EMAC_TX_WAKEUP_THRESH)
1580 netif_wake_queue(dev->ndev);
1581
1582 DBG2(dev, "tx %d pkts" NL, n);
1583 }
1584 }
1585 netif_tx_unlock_bh(dev->ndev);
1586}
1587
1588static inline void emac_recycle_rx_skb(struct emac_instance *dev, int slot,
1589 int len)
1590{
1591 struct sk_buff *skb = dev->rx_skb[slot];
1592
1593 DBG2(dev, "recycle %d %d" NL, slot, len);
1594
1595 if (len)
1596 dma_map_single(&dev->ofdev->dev, skb->data - 2,
1597 EMAC_DMA_ALIGN(len + 2), DMA_FROM_DEVICE);
1598
1599 dev->rx_desc[slot].data_len = 0;
1600 wmb();
1601 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1602 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1603}
1604
1605static void emac_parse_rx_error(struct emac_instance *dev, u16 ctrl)
1606{
1607 struct emac_error_stats *st = &dev->estats;
1608
1609 DBG(dev, "BD RX error %04x" NL, ctrl);
1610
1611 ++st->rx_bd_errors;
1612 if (ctrl & EMAC_RX_ST_OE)
1613 ++st->rx_bd_overrun;
1614 if (ctrl & EMAC_RX_ST_BP)
1615 ++st->rx_bd_bad_packet;
1616 if (ctrl & EMAC_RX_ST_RP)
1617 ++st->rx_bd_runt_packet;
1618 if (ctrl & EMAC_RX_ST_SE)
1619 ++st->rx_bd_short_event;
1620 if (ctrl & EMAC_RX_ST_AE)
1621 ++st->rx_bd_alignment_error;
1622 if (ctrl & EMAC_RX_ST_BFCS)
1623 ++st->rx_bd_bad_fcs;
1624 if (ctrl & EMAC_RX_ST_PTL)
1625 ++st->rx_bd_packet_too_long;
1626 if (ctrl & EMAC_RX_ST_ORE)
1627 ++st->rx_bd_out_of_range;
1628 if (ctrl & EMAC_RX_ST_IRE)
1629 ++st->rx_bd_in_range;
1630}
1631
1632static inline void emac_rx_csum(struct emac_instance *dev,
1633 struct sk_buff *skb, u16 ctrl)
1634{
1635#ifdef CONFIG_IBM_EMAC_TAH
1636 if (!ctrl && dev->tah_dev) {
1637 skb->ip_summed = CHECKSUM_UNNECESSARY;
1638 ++dev->stats.rx_packets_csum;
1639 }
1640#endif
1641}
1642
1643static inline int emac_rx_sg_append(struct emac_instance *dev, int slot)
1644{
1645 if (likely(dev->rx_sg_skb != NULL)) {
1646 int len = dev->rx_desc[slot].data_len;
1647 int tot_len = dev->rx_sg_skb->len + len;
1648
1649 if (unlikely(tot_len + 2 > dev->rx_skb_size)) {
1650 ++dev->estats.rx_dropped_mtu;
1651 dev_kfree_skb(dev->rx_sg_skb);
1652 dev->rx_sg_skb = NULL;
1653 } else {
1654 cacheable_memcpy(skb_tail_pointer(dev->rx_sg_skb),
1655 dev->rx_skb[slot]->data, len);
1656 skb_put(dev->rx_sg_skb, len);
1657 emac_recycle_rx_skb(dev, slot, len);
1658 return 0;
1659 }
1660 }
1661 emac_recycle_rx_skb(dev, slot, 0);
1662 return -1;
1663}
1664
1665/* NAPI poll context */
1666static int emac_poll_rx(void *param, int budget)
1667{
1668 struct emac_instance *dev = param;
1669 int slot = dev->rx_slot, received = 0;
1670
1671 DBG2(dev, "poll_rx(%d)" NL, budget);
1672
1673 again:
1674 while (budget > 0) {
1675 int len;
1676 struct sk_buff *skb;
1677 u16 ctrl = dev->rx_desc[slot].ctrl;
1678
1679 if (ctrl & MAL_RX_CTRL_EMPTY)
1680 break;
1681
1682 skb = dev->rx_skb[slot];
1683 mb();
1684 len = dev->rx_desc[slot].data_len;
1685
1686 if (unlikely(!MAL_IS_SINGLE_RX(ctrl)))
1687 goto sg;
1688
1689 ctrl &= EMAC_BAD_RX_MASK;
1690 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1691 emac_parse_rx_error(dev, ctrl);
1692 ++dev->estats.rx_dropped_error;
1693 emac_recycle_rx_skb(dev, slot, 0);
1694 len = 0;
1695 goto next;
1696 }
1697
1698 if (len < ETH_HLEN) {
1699 ++dev->estats.rx_dropped_stack;
1700 emac_recycle_rx_skb(dev, slot, len);
1701 goto next;
1702 }
1703
1704 if (len && len < EMAC_RX_COPY_THRESH) {
1705 struct sk_buff *copy_skb =
1706 alloc_skb(len + EMAC_RX_SKB_HEADROOM + 2, GFP_ATOMIC);
1707 if (unlikely(!copy_skb))
1708 goto oom;
1709
1710 skb_reserve(copy_skb, EMAC_RX_SKB_HEADROOM + 2);
1711 cacheable_memcpy(copy_skb->data - 2, skb->data - 2,
1712 len + 2);
1713 emac_recycle_rx_skb(dev, slot, len);
1714 skb = copy_skb;
1715 } else if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC)))
1716 goto oom;
1717
1718 skb_put(skb, len);
1719 push_packet:
1720 skb->protocol = eth_type_trans(skb, dev->ndev);
1721 emac_rx_csum(dev, skb, ctrl);
1722
1723 if (unlikely(netif_receive_skb(skb) == NET_RX_DROP))
1724 ++dev->estats.rx_dropped_stack;
1725 next:
1726 ++dev->stats.rx_packets;
1727 skip:
1728 dev->stats.rx_bytes += len;
1729 slot = (slot + 1) % NUM_RX_BUFF;
1730 --budget;
1731 ++received;
1732 continue;
1733 sg:
1734 if (ctrl & MAL_RX_CTRL_FIRST) {
1735 BUG_ON(dev->rx_sg_skb);
1736 if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC))) {
1737 DBG(dev, "rx OOM %d" NL, slot);
1738 ++dev->estats.rx_dropped_oom;
1739 emac_recycle_rx_skb(dev, slot, 0);
1740 } else {
1741 dev->rx_sg_skb = skb;
1742 skb_put(skb, len);
1743 }
1744 } else if (!emac_rx_sg_append(dev, slot) &&
1745 (ctrl & MAL_RX_CTRL_LAST)) {
1746
1747 skb = dev->rx_sg_skb;
1748 dev->rx_sg_skb = NULL;
1749
1750 ctrl &= EMAC_BAD_RX_MASK;
1751 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1752 emac_parse_rx_error(dev, ctrl);
1753 ++dev->estats.rx_dropped_error;
1754 dev_kfree_skb(skb);
1755 len = 0;
1756 } else
1757 goto push_packet;
1758 }
1759 goto skip;
1760 oom:
1761 DBG(dev, "rx OOM %d" NL, slot);
1762 /* Drop the packet and recycle skb */
1763 ++dev->estats.rx_dropped_oom;
1764 emac_recycle_rx_skb(dev, slot, 0);
1765 goto next;
1766 }
1767
1768 if (received) {
1769 DBG2(dev, "rx %d BDs" NL, received);
1770 dev->rx_slot = slot;
1771 }
1772
1773 if (unlikely(budget && test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags))) {
1774 mb();
1775 if (!(dev->rx_desc[slot].ctrl & MAL_RX_CTRL_EMPTY)) {
1776 DBG2(dev, "rx restart" NL);
1777 received = 0;
1778 goto again;
1779 }
1780
1781 if (dev->rx_sg_skb) {
1782 DBG2(dev, "dropping partial rx packet" NL);
1783 ++dev->estats.rx_dropped_error;
1784 dev_kfree_skb(dev->rx_sg_skb);
1785 dev->rx_sg_skb = NULL;
1786 }
1787
1788 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1789 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1790 emac_rx_enable(dev);
1791 dev->rx_slot = 0;
1792 }
1793 return received;
1794}
1795
1796/* NAPI poll context */
1797static int emac_peek_rx(void *param)
1798{
1799 struct emac_instance *dev = param;
1800
1801 return !(dev->rx_desc[dev->rx_slot].ctrl & MAL_RX_CTRL_EMPTY);
1802}
1803
1804/* NAPI poll context */
1805static int emac_peek_rx_sg(void *param)
1806{
1807 struct emac_instance *dev = param;
1808
1809 int slot = dev->rx_slot;
1810 while (1) {
1811 u16 ctrl = dev->rx_desc[slot].ctrl;
1812 if (ctrl & MAL_RX_CTRL_EMPTY)
1813 return 0;
1814 else if (ctrl & MAL_RX_CTRL_LAST)
1815 return 1;
1816
1817 slot = (slot + 1) % NUM_RX_BUFF;
1818
1819 /* I'm just being paranoid here :) */
1820 if (unlikely(slot == dev->rx_slot))
1821 return 0;
1822 }
1823}
1824
1825/* Hard IRQ */
1826static void emac_rxde(void *param)
1827{
1828 struct emac_instance *dev = param;
1829
1830 ++dev->estats.rx_stopped;
1831 emac_rx_disable_async(dev);
1832}
1833
1834/* Hard IRQ */
1835static irqreturn_t emac_irq(int irq, void *dev_instance)
1836{
1837 struct emac_instance *dev = dev_instance;
1838 struct emac_regs __iomem *p = dev->emacp;
1839 struct emac_error_stats *st = &dev->estats;
1840 u32 isr;
1841
1842 spin_lock(&dev->lock);
1843
1844 isr = in_be32(&p->isr);
1845 out_be32(&p->isr, isr);
1846
1847 DBG(dev, "isr = %08x" NL, isr);
1848
1849 if (isr & EMAC4_ISR_TXPE)
1850 ++st->tx_parity;
1851 if (isr & EMAC4_ISR_RXPE)
1852 ++st->rx_parity;
1853 if (isr & EMAC4_ISR_TXUE)
1854 ++st->tx_underrun;
1855 if (isr & EMAC4_ISR_RXOE)
1856 ++st->rx_fifo_overrun;
1857 if (isr & EMAC_ISR_OVR)
1858 ++st->rx_overrun;
1859 if (isr & EMAC_ISR_BP)
1860 ++st->rx_bad_packet;
1861 if (isr & EMAC_ISR_RP)
1862 ++st->rx_runt_packet;
1863 if (isr & EMAC_ISR_SE)
1864 ++st->rx_short_event;
1865 if (isr & EMAC_ISR_ALE)
1866 ++st->rx_alignment_error;
1867 if (isr & EMAC_ISR_BFCS)
1868 ++st->rx_bad_fcs;
1869 if (isr & EMAC_ISR_PTLE)
1870 ++st->rx_packet_too_long;
1871 if (isr & EMAC_ISR_ORE)
1872 ++st->rx_out_of_range;
1873 if (isr & EMAC_ISR_IRE)
1874 ++st->rx_in_range;
1875 if (isr & EMAC_ISR_SQE)
1876 ++st->tx_sqe;
1877 if (isr & EMAC_ISR_TE)
1878 ++st->tx_errors;
1879
1880 spin_unlock(&dev->lock);
1881
1882 return IRQ_HANDLED;
1883}
1884
1885static struct net_device_stats *emac_stats(struct net_device *ndev)
1886{
1887 struct emac_instance *dev = netdev_priv(ndev);
1888 struct emac_stats *st = &dev->stats;
1889 struct emac_error_stats *est = &dev->estats;
1890 struct net_device_stats *nst = &dev->nstats;
1891 unsigned long flags;
1892
1893 DBG2(dev, "stats" NL);
1894
1895 /* Compute "legacy" statistics */
1896 spin_lock_irqsave(&dev->lock, flags);
1897 nst->rx_packets = (unsigned long)st->rx_packets;
1898 nst->rx_bytes = (unsigned long)st->rx_bytes;
1899 nst->tx_packets = (unsigned long)st->tx_packets;
1900 nst->tx_bytes = (unsigned long)st->tx_bytes;
1901 nst->rx_dropped = (unsigned long)(est->rx_dropped_oom +
1902 est->rx_dropped_error +
1903 est->rx_dropped_resize +
1904 est->rx_dropped_mtu);
1905 nst->tx_dropped = (unsigned long)est->tx_dropped;
1906
1907 nst->rx_errors = (unsigned long)est->rx_bd_errors;
1908 nst->rx_fifo_errors = (unsigned long)(est->rx_bd_overrun +
1909 est->rx_fifo_overrun +
1910 est->rx_overrun);
1911 nst->rx_frame_errors = (unsigned long)(est->rx_bd_alignment_error +
1912 est->rx_alignment_error);
1913 nst->rx_crc_errors = (unsigned long)(est->rx_bd_bad_fcs +
1914 est->rx_bad_fcs);
1915 nst->rx_length_errors = (unsigned long)(est->rx_bd_runt_packet +
1916 est->rx_bd_short_event +
1917 est->rx_bd_packet_too_long +
1918 est->rx_bd_out_of_range +
1919 est->rx_bd_in_range +
1920 est->rx_runt_packet +
1921 est->rx_short_event +
1922 est->rx_packet_too_long +
1923 est->rx_out_of_range +
1924 est->rx_in_range);
1925
1926 nst->tx_errors = (unsigned long)(est->tx_bd_errors + est->tx_errors);
1927 nst->tx_fifo_errors = (unsigned long)(est->tx_bd_underrun +
1928 est->tx_underrun);
1929 nst->tx_carrier_errors = (unsigned long)est->tx_bd_carrier_loss;
1930 nst->collisions = (unsigned long)(est->tx_bd_excessive_deferral +
1931 est->tx_bd_excessive_collisions +
1932 est->tx_bd_late_collision +
1933 est->tx_bd_multple_collisions);
1934 spin_unlock_irqrestore(&dev->lock, flags);
1935 return nst;
1936}
1937
1938static struct mal_commac_ops emac_commac_ops = {
1939 .poll_tx = &emac_poll_tx,
1940 .poll_rx = &emac_poll_rx,
1941 .peek_rx = &emac_peek_rx,
1942 .rxde = &emac_rxde,
1943};
1944
1945static struct mal_commac_ops emac_commac_sg_ops = {
1946 .poll_tx = &emac_poll_tx,
1947 .poll_rx = &emac_poll_rx,
1948 .peek_rx = &emac_peek_rx_sg,
1949 .rxde = &emac_rxde,
1950};
1951
1952/* Ethtool support */
1953static int emac_ethtool_get_settings(struct net_device *ndev,
1954 struct ethtool_cmd *cmd)
1955{
1956 struct emac_instance *dev = netdev_priv(ndev);
1957
1958 cmd->supported = dev->phy.features;
1959 cmd->port = PORT_MII;
1960 cmd->phy_address = dev->phy.address;
1961 cmd->transceiver =
1962 dev->phy.address >= 0 ? XCVR_EXTERNAL : XCVR_INTERNAL;
1963
1964 mutex_lock(&dev->link_lock);
1965 cmd->advertising = dev->phy.advertising;
1966 cmd->autoneg = dev->phy.autoneg;
1967 cmd->speed = dev->phy.speed;
1968 cmd->duplex = dev->phy.duplex;
1969 mutex_unlock(&dev->link_lock);
1970
1971 return 0;
1972}
1973
1974static int emac_ethtool_set_settings(struct net_device *ndev,
1975 struct ethtool_cmd *cmd)
1976{
1977 struct emac_instance *dev = netdev_priv(ndev);
1978 u32 f = dev->phy.features;
1979
1980 DBG(dev, "set_settings(%d, %d, %d, 0x%08x)" NL,
1981 cmd->autoneg, cmd->speed, cmd->duplex, cmd->advertising);
1982
1983 /* Basic sanity checks */
1984 if (dev->phy.address < 0)
1985 return -EOPNOTSUPP;
1986 if (cmd->autoneg != AUTONEG_ENABLE && cmd->autoneg != AUTONEG_DISABLE)
1987 return -EINVAL;
1988 if (cmd->autoneg == AUTONEG_ENABLE && cmd->advertising == 0)
1989 return -EINVAL;
1990 if (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL)
1991 return -EINVAL;
1992
1993 if (cmd->autoneg == AUTONEG_DISABLE) {
1994 switch (cmd->speed) {
1995 case SPEED_10:
1996 if (cmd->duplex == DUPLEX_HALF &&
1997 !(f & SUPPORTED_10baseT_Half))
1998 return -EINVAL;
1999 if (cmd->duplex == DUPLEX_FULL &&
2000 !(f & SUPPORTED_10baseT_Full))
2001 return -EINVAL;
2002 break;
2003 case SPEED_100:
2004 if (cmd->duplex == DUPLEX_HALF &&
2005 !(f & SUPPORTED_100baseT_Half))
2006 return -EINVAL;
2007 if (cmd->duplex == DUPLEX_FULL &&
2008 !(f & SUPPORTED_100baseT_Full))
2009 return -EINVAL;
2010 break;
2011 case SPEED_1000:
2012 if (cmd->duplex == DUPLEX_HALF &&
2013 !(f & SUPPORTED_1000baseT_Half))
2014 return -EINVAL;
2015 if (cmd->duplex == DUPLEX_FULL &&
2016 !(f & SUPPORTED_1000baseT_Full))
2017 return -EINVAL;
2018 break;
2019 default:
2020 return -EINVAL;
2021 }
2022
2023 mutex_lock(&dev->link_lock);
2024 dev->phy.def->ops->setup_forced(&dev->phy, cmd->speed,
2025 cmd->duplex);
2026 mutex_unlock(&dev->link_lock);
2027
2028 } else {
2029 if (!(f & SUPPORTED_Autoneg))
2030 return -EINVAL;
2031
2032 mutex_lock(&dev->link_lock);
2033 dev->phy.def->ops->setup_aneg(&dev->phy,
2034 (cmd->advertising & f) |
2035 (dev->phy.advertising &
2036 (ADVERTISED_Pause |
2037 ADVERTISED_Asym_Pause)));
2038 mutex_unlock(&dev->link_lock);
2039 }
2040 emac_force_link_update(dev);
2041
2042 return 0;
2043}
2044
2045static void emac_ethtool_get_ringparam(struct net_device *ndev,
2046 struct ethtool_ringparam *rp)
2047{
2048 rp->rx_max_pending = rp->rx_pending = NUM_RX_BUFF;
2049 rp->tx_max_pending = rp->tx_pending = NUM_TX_BUFF;
2050}
2051
2052static void emac_ethtool_get_pauseparam(struct net_device *ndev,
2053 struct ethtool_pauseparam *pp)
2054{
2055 struct emac_instance *dev = netdev_priv(ndev);
2056
2057 mutex_lock(&dev->link_lock);
2058 if ((dev->phy.features & SUPPORTED_Autoneg) &&
2059 (dev->phy.advertising & (ADVERTISED_Pause | ADVERTISED_Asym_Pause)))
2060 pp->autoneg = 1;
2061
2062 if (dev->phy.duplex == DUPLEX_FULL) {
2063 if (dev->phy.pause)
2064 pp->rx_pause = pp->tx_pause = 1;
2065 else if (dev->phy.asym_pause)
2066 pp->tx_pause = 1;
2067 }
2068 mutex_unlock(&dev->link_lock);
2069}
2070
2071static int emac_get_regs_len(struct emac_instance *dev)
2072{
2073 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
2074 return sizeof(struct emac_ethtool_regs_subhdr) +
2075 EMAC4_ETHTOOL_REGS_SIZE(dev);
2076 else
2077 return sizeof(struct emac_ethtool_regs_subhdr) +
2078 EMAC_ETHTOOL_REGS_SIZE(dev);
2079}
2080
2081static int emac_ethtool_get_regs_len(struct net_device *ndev)
2082{
2083 struct emac_instance *dev = netdev_priv(ndev);
2084 int size;
2085
2086 size = sizeof(struct emac_ethtool_regs_hdr) +
2087 emac_get_regs_len(dev) + mal_get_regs_len(dev->mal);
2088 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2089 size += zmii_get_regs_len(dev->zmii_dev);
2090 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2091 size += rgmii_get_regs_len(dev->rgmii_dev);
2092 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2093 size += tah_get_regs_len(dev->tah_dev);
2094
2095 return size;
2096}
2097
2098static void *emac_dump_regs(struct emac_instance *dev, void *buf)
2099{
2100 struct emac_ethtool_regs_subhdr *hdr = buf;
2101
2102 hdr->index = dev->cell_index;
2103 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) {
2104 hdr->version = EMAC4_ETHTOOL_REGS_VER;
2105 memcpy_fromio(hdr + 1, dev->emacp, EMAC4_ETHTOOL_REGS_SIZE(dev));
2106 return (void *)(hdr + 1) + EMAC4_ETHTOOL_REGS_SIZE(dev);
2107 } else {
2108 hdr->version = EMAC_ETHTOOL_REGS_VER;
2109 memcpy_fromio(hdr + 1, dev->emacp, EMAC_ETHTOOL_REGS_SIZE(dev));
2110 return (void *)(hdr + 1) + EMAC_ETHTOOL_REGS_SIZE(dev);
2111 }
2112}
2113
2114static void emac_ethtool_get_regs(struct net_device *ndev,
2115 struct ethtool_regs *regs, void *buf)
2116{
2117 struct emac_instance *dev = netdev_priv(ndev);
2118 struct emac_ethtool_regs_hdr *hdr = buf;
2119
2120 hdr->components = 0;
2121 buf = hdr + 1;
2122
2123 buf = mal_dump_regs(dev->mal, buf);
2124 buf = emac_dump_regs(dev, buf);
2125 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) {
2126 hdr->components |= EMAC_ETHTOOL_REGS_ZMII;
2127 buf = zmii_dump_regs(dev->zmii_dev, buf);
2128 }
2129 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) {
2130 hdr->components |= EMAC_ETHTOOL_REGS_RGMII;
2131 buf = rgmii_dump_regs(dev->rgmii_dev, buf);
2132 }
2133 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) {
2134 hdr->components |= EMAC_ETHTOOL_REGS_TAH;
2135 buf = tah_dump_regs(dev->tah_dev, buf);
2136 }
2137}
2138
2139static int emac_ethtool_nway_reset(struct net_device *ndev)
2140{
2141 struct emac_instance *dev = netdev_priv(ndev);
2142 int res = 0;
2143
2144 DBG(dev, "nway_reset" NL);
2145
2146 if (dev->phy.address < 0)
2147 return -EOPNOTSUPP;
2148
2149 mutex_lock(&dev->link_lock);
2150 if (!dev->phy.autoneg) {
2151 res = -EINVAL;
2152 goto out;
2153 }
2154
2155 dev->phy.def->ops->setup_aneg(&dev->phy, dev->phy.advertising);
2156 out:
2157 mutex_unlock(&dev->link_lock);
2158 emac_force_link_update(dev);
2159 return res;
2160}
2161
2162static int emac_ethtool_get_sset_count(struct net_device *ndev, int stringset)
2163{
2164 if (stringset == ETH_SS_STATS)
2165 return EMAC_ETHTOOL_STATS_COUNT;
2166 else
2167 return -EINVAL;
2168}
2169
2170static void emac_ethtool_get_strings(struct net_device *ndev, u32 stringset,
2171 u8 * buf)
2172{
2173 if (stringset == ETH_SS_STATS)
2174 memcpy(buf, &emac_stats_keys, sizeof(emac_stats_keys));
2175}
2176
2177static void emac_ethtool_get_ethtool_stats(struct net_device *ndev,
2178 struct ethtool_stats *estats,
2179 u64 * tmp_stats)
2180{
2181 struct emac_instance *dev = netdev_priv(ndev);
2182
2183 memcpy(tmp_stats, &dev->stats, sizeof(dev->stats));
2184 tmp_stats += sizeof(dev->stats) / sizeof(u64);
2185 memcpy(tmp_stats, &dev->estats, sizeof(dev->estats));
2186}
2187
2188static void emac_ethtool_get_drvinfo(struct net_device *ndev,
2189 struct ethtool_drvinfo *info)
2190{
2191 struct emac_instance *dev = netdev_priv(ndev);
2192
2193 strcpy(info->driver, "ibm_emac");
2194 strcpy(info->version, DRV_VERSION);
2195 info->fw_version[0] = '\0';
2196 sprintf(info->bus_info, "PPC 4xx EMAC-%d %s",
2197 dev->cell_index, dev->ofdev->dev.of_node->full_name);
2198 info->regdump_len = emac_ethtool_get_regs_len(ndev);
2199}
2200
2201static const struct ethtool_ops emac_ethtool_ops = {
2202 .get_settings = emac_ethtool_get_settings,
2203 .set_settings = emac_ethtool_set_settings,
2204 .get_drvinfo = emac_ethtool_get_drvinfo,
2205
2206 .get_regs_len = emac_ethtool_get_regs_len,
2207 .get_regs = emac_ethtool_get_regs,
2208
2209 .nway_reset = emac_ethtool_nway_reset,
2210
2211 .get_ringparam = emac_ethtool_get_ringparam,
2212 .get_pauseparam = emac_ethtool_get_pauseparam,
2213
2214 .get_strings = emac_ethtool_get_strings,
2215 .get_sset_count = emac_ethtool_get_sset_count,
2216 .get_ethtool_stats = emac_ethtool_get_ethtool_stats,
2217
2218 .get_link = ethtool_op_get_link,
2219};
2220
2221static int emac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2222{
2223 struct emac_instance *dev = netdev_priv(ndev);
2224 struct mii_ioctl_data *data = if_mii(rq);
2225
2226 DBG(dev, "ioctl %08x" NL, cmd);
2227
2228 if (dev->phy.address < 0)
2229 return -EOPNOTSUPP;
2230
2231 switch (cmd) {
2232 case SIOCGMIIPHY:
2233 data->phy_id = dev->phy.address;
2234 /* Fall through */
2235 case SIOCGMIIREG:
2236 data->val_out = emac_mdio_read(ndev, dev->phy.address,
2237 data->reg_num);
2238 return 0;
2239
2240 case SIOCSMIIREG:
2241 emac_mdio_write(ndev, dev->phy.address, data->reg_num,
2242 data->val_in);
2243 return 0;
2244 default:
2245 return -EOPNOTSUPP;
2246 }
2247}
2248
2249struct emac_depentry {
2250 u32 phandle;
2251 struct device_node *node;
2252 struct platform_device *ofdev;
2253 void *drvdata;
2254};
2255
2256#define EMAC_DEP_MAL_IDX 0
2257#define EMAC_DEP_ZMII_IDX 1
2258#define EMAC_DEP_RGMII_IDX 2
2259#define EMAC_DEP_TAH_IDX 3
2260#define EMAC_DEP_MDIO_IDX 4
2261#define EMAC_DEP_PREV_IDX 5
2262#define EMAC_DEP_COUNT 6
2263
2264static int __devinit emac_check_deps(struct emac_instance *dev,
2265 struct emac_depentry *deps)
2266{
2267 int i, there = 0;
2268 struct device_node *np;
2269
2270 for (i = 0; i < EMAC_DEP_COUNT; i++) {
2271 /* no dependency on that item, allright */
2272 if (deps[i].phandle == 0) {
2273 there++;
2274 continue;
2275 }
2276 /* special case for blist as the dependency might go away */
2277 if (i == EMAC_DEP_PREV_IDX) {
2278 np = *(dev->blist - 1);
2279 if (np == NULL) {
2280 deps[i].phandle = 0;
2281 there++;
2282 continue;
2283 }
2284 if (deps[i].node == NULL)
2285 deps[i].node = of_node_get(np);
2286 }
2287 if (deps[i].node == NULL)
2288 deps[i].node = of_find_node_by_phandle(deps[i].phandle);
2289 if (deps[i].node == NULL)
2290 continue;
2291 if (deps[i].ofdev == NULL)
2292 deps[i].ofdev = of_find_device_by_node(deps[i].node);
2293 if (deps[i].ofdev == NULL)
2294 continue;
2295 if (deps[i].drvdata == NULL)
2296 deps[i].drvdata = dev_get_drvdata(&deps[i].ofdev->dev);
2297 if (deps[i].drvdata != NULL)
2298 there++;
2299 }
2300 return there == EMAC_DEP_COUNT;
2301}
2302
2303static void emac_put_deps(struct emac_instance *dev)
2304{
2305 if (dev->mal_dev)
2306 of_dev_put(dev->mal_dev);
2307 if (dev->zmii_dev)
2308 of_dev_put(dev->zmii_dev);
2309 if (dev->rgmii_dev)
2310 of_dev_put(dev->rgmii_dev);
2311 if (dev->mdio_dev)
2312 of_dev_put(dev->mdio_dev);
2313 if (dev->tah_dev)
2314 of_dev_put(dev->tah_dev);
2315}
2316
2317static int __devinit emac_of_bus_notify(struct notifier_block *nb,
2318 unsigned long action, void *data)
2319{
2320 /* We are only intereted in device addition */
2321 if (action == BUS_NOTIFY_BOUND_DRIVER)
2322 wake_up_all(&emac_probe_wait);
2323 return 0;
2324}
2325
2326static struct notifier_block emac_of_bus_notifier __devinitdata = {
2327 .notifier_call = emac_of_bus_notify
2328};
2329
2330static int __devinit emac_wait_deps(struct emac_instance *dev)
2331{
2332 struct emac_depentry deps[EMAC_DEP_COUNT];
2333 int i, err;
2334
2335 memset(&deps, 0, sizeof(deps));
2336
2337 deps[EMAC_DEP_MAL_IDX].phandle = dev->mal_ph;
2338 deps[EMAC_DEP_ZMII_IDX].phandle = dev->zmii_ph;
2339 deps[EMAC_DEP_RGMII_IDX].phandle = dev->rgmii_ph;
2340 if (dev->tah_ph)
2341 deps[EMAC_DEP_TAH_IDX].phandle = dev->tah_ph;
2342 if (dev->mdio_ph)
2343 deps[EMAC_DEP_MDIO_IDX].phandle = dev->mdio_ph;
2344 if (dev->blist && dev->blist > emac_boot_list)
2345 deps[EMAC_DEP_PREV_IDX].phandle = 0xffffffffu;
2346 bus_register_notifier(&platform_bus_type, &emac_of_bus_notifier);
2347 wait_event_timeout(emac_probe_wait,
2348 emac_check_deps(dev, deps),
2349 EMAC_PROBE_DEP_TIMEOUT);
2350 bus_unregister_notifier(&platform_bus_type, &emac_of_bus_notifier);
2351 err = emac_check_deps(dev, deps) ? 0 : -ENODEV;
2352 for (i = 0; i < EMAC_DEP_COUNT; i++) {
2353 if (deps[i].node)
2354 of_node_put(deps[i].node);
2355 if (err && deps[i].ofdev)
2356 of_dev_put(deps[i].ofdev);
2357 }
2358 if (err == 0) {
2359 dev->mal_dev = deps[EMAC_DEP_MAL_IDX].ofdev;
2360 dev->zmii_dev = deps[EMAC_DEP_ZMII_IDX].ofdev;
2361 dev->rgmii_dev = deps[EMAC_DEP_RGMII_IDX].ofdev;
2362 dev->tah_dev = deps[EMAC_DEP_TAH_IDX].ofdev;
2363 dev->mdio_dev = deps[EMAC_DEP_MDIO_IDX].ofdev;
2364 }
2365 if (deps[EMAC_DEP_PREV_IDX].ofdev)
2366 of_dev_put(deps[EMAC_DEP_PREV_IDX].ofdev);
2367 return err;
2368}
2369
2370static int __devinit emac_read_uint_prop(struct device_node *np, const char *name,
2371 u32 *val, int fatal)
2372{
2373 int len;
2374 const u32 *prop = of_get_property(np, name, &len);
2375 if (prop == NULL || len < sizeof(u32)) {
2376 if (fatal)
2377 printk(KERN_ERR "%s: missing %s property\n",
2378 np->full_name, name);
2379 return -ENODEV;
2380 }
2381 *val = *prop;
2382 return 0;
2383}
2384
2385static int __devinit emac_init_phy(struct emac_instance *dev)
2386{
2387 struct device_node *np = dev->ofdev->dev.of_node;
2388 struct net_device *ndev = dev->ndev;
2389 u32 phy_map, adv;
2390 int i;
2391
2392 dev->phy.dev = ndev;
2393 dev->phy.mode = dev->phy_mode;
2394
2395 /* PHY-less configuration.
2396 * XXX I probably should move these settings to the dev tree
2397 */
2398 if (dev->phy_address == 0xffffffff && dev->phy_map == 0xffffffff) {
2399 emac_reset(dev);
2400
2401 /* PHY-less configuration.
2402 * XXX I probably should move these settings to the dev tree
2403 */
2404 dev->phy.address = -1;
2405 dev->phy.features = SUPPORTED_MII;
2406 if (emac_phy_supports_gige(dev->phy_mode))
2407 dev->phy.features |= SUPPORTED_1000baseT_Full;
2408 else
2409 dev->phy.features |= SUPPORTED_100baseT_Full;
2410 dev->phy.pause = 1;
2411
2412 return 0;
2413 }
2414
2415 mutex_lock(&emac_phy_map_lock);
2416 phy_map = dev->phy_map | busy_phy_map;
2417
2418 DBG(dev, "PHY maps %08x %08x" NL, dev->phy_map, busy_phy_map);
2419
2420 dev->phy.mdio_read = emac_mdio_read;
2421 dev->phy.mdio_write = emac_mdio_write;
2422
2423 /* Enable internal clock source */
2424#ifdef CONFIG_PPC_DCR_NATIVE
2425 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2426 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
2427#endif
2428 /* PHY clock workaround */
2429 emac_rx_clk_tx(dev);
2430
2431 /* Enable internal clock source on 440GX*/
2432#ifdef CONFIG_PPC_DCR_NATIVE
2433 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2434 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
2435#endif
2436 /* Configure EMAC with defaults so we can at least use MDIO
2437 * This is needed mostly for 440GX
2438 */
2439 if (emac_phy_gpcs(dev->phy.mode)) {
2440 /* XXX
2441 * Make GPCS PHY address equal to EMAC index.
2442 * We probably should take into account busy_phy_map
2443 * and/or phy_map here.
2444 *
2445 * Note that the busy_phy_map is currently global
2446 * while it should probably be per-ASIC...
2447 */
2448 dev->phy.gpcs_address = dev->gpcs_address;
2449 if (dev->phy.gpcs_address == 0xffffffff)
2450 dev->phy.address = dev->cell_index;
2451 }
2452
2453 emac_configure(dev);
2454
2455 if (dev->phy_address != 0xffffffff)
2456 phy_map = ~(1 << dev->phy_address);
2457
2458 for (i = 0; i < 0x20; phy_map >>= 1, ++i)
2459 if (!(phy_map & 1)) {
2460 int r;
2461 busy_phy_map |= 1 << i;
2462
2463 /* Quick check if there is a PHY at the address */
2464 r = emac_mdio_read(dev->ndev, i, MII_BMCR);
2465 if (r == 0xffff || r < 0)
2466 continue;
2467 if (!emac_mii_phy_probe(&dev->phy, i))
2468 break;
2469 }
2470
2471 /* Enable external clock source */
2472#ifdef CONFIG_PPC_DCR_NATIVE
2473 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2474 dcri_clrset(SDR0, SDR0_MFR, SDR0_MFR_ECS, 0);
2475#endif
2476 mutex_unlock(&emac_phy_map_lock);
2477 if (i == 0x20) {
2478 printk(KERN_WARNING "%s: can't find PHY!\n", np->full_name);
2479 return -ENXIO;
2480 }
2481
2482 /* Init PHY */
2483 if (dev->phy.def->ops->init)
2484 dev->phy.def->ops->init(&dev->phy);
2485
2486 /* Disable any PHY features not supported by the platform */
2487 dev->phy.def->features &= ~dev->phy_feat_exc;
2488 dev->phy.features &= ~dev->phy_feat_exc;
2489
2490 /* Setup initial link parameters */
2491 if (dev->phy.features & SUPPORTED_Autoneg) {
2492 adv = dev->phy.features;
2493 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x))
2494 adv |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
2495 /* Restart autonegotiation */
2496 dev->phy.def->ops->setup_aneg(&dev->phy, adv);
2497 } else {
2498 u32 f = dev->phy.def->features;
2499 int speed = SPEED_10, fd = DUPLEX_HALF;
2500
2501 /* Select highest supported speed/duplex */
2502 if (f & SUPPORTED_1000baseT_Full) {
2503 speed = SPEED_1000;
2504 fd = DUPLEX_FULL;
2505 } else if (f & SUPPORTED_1000baseT_Half)
2506 speed = SPEED_1000;
2507 else if (f & SUPPORTED_100baseT_Full) {
2508 speed = SPEED_100;
2509 fd = DUPLEX_FULL;
2510 } else if (f & SUPPORTED_100baseT_Half)
2511 speed = SPEED_100;
2512 else if (f & SUPPORTED_10baseT_Full)
2513 fd = DUPLEX_FULL;
2514
2515 /* Force link parameters */
2516 dev->phy.def->ops->setup_forced(&dev->phy, speed, fd);
2517 }
2518 return 0;
2519}
2520
2521static int __devinit emac_init_config(struct emac_instance *dev)
2522{
2523 struct device_node *np = dev->ofdev->dev.of_node;
2524 const void *p;
2525
2526 /* Read config from device-tree */
2527 if (emac_read_uint_prop(np, "mal-device", &dev->mal_ph, 1))
2528 return -ENXIO;
2529 if (emac_read_uint_prop(np, "mal-tx-channel", &dev->mal_tx_chan, 1))
2530 return -ENXIO;
2531 if (emac_read_uint_prop(np, "mal-rx-channel", &dev->mal_rx_chan, 1))
2532 return -ENXIO;
2533 if (emac_read_uint_prop(np, "cell-index", &dev->cell_index, 1))
2534 return -ENXIO;
2535 if (emac_read_uint_prop(np, "max-frame-size", &dev->max_mtu, 0))
2536 dev->max_mtu = 1500;
2537 if (emac_read_uint_prop(np, "rx-fifo-size", &dev->rx_fifo_size, 0))
2538 dev->rx_fifo_size = 2048;
2539 if (emac_read_uint_prop(np, "tx-fifo-size", &dev->tx_fifo_size, 0))
2540 dev->tx_fifo_size = 2048;
2541 if (emac_read_uint_prop(np, "rx-fifo-size-gige", &dev->rx_fifo_size_gige, 0))
2542 dev->rx_fifo_size_gige = dev->rx_fifo_size;
2543 if (emac_read_uint_prop(np, "tx-fifo-size-gige", &dev->tx_fifo_size_gige, 0))
2544 dev->tx_fifo_size_gige = dev->tx_fifo_size;
2545 if (emac_read_uint_prop(np, "phy-address", &dev->phy_address, 0))
2546 dev->phy_address = 0xffffffff;
2547 if (emac_read_uint_prop(np, "phy-map", &dev->phy_map, 0))
2548 dev->phy_map = 0xffffffff;
2549 if (emac_read_uint_prop(np, "gpcs-address", &dev->gpcs_address, 0))
2550 dev->gpcs_address = 0xffffffff;
2551 if (emac_read_uint_prop(np->parent, "clock-frequency", &dev->opb_bus_freq, 1))
2552 return -ENXIO;
2553 if (emac_read_uint_prop(np, "tah-device", &dev->tah_ph, 0))
2554 dev->tah_ph = 0;
2555 if (emac_read_uint_prop(np, "tah-channel", &dev->tah_port, 0))
2556 dev->tah_port = 0;
2557 if (emac_read_uint_prop(np, "mdio-device", &dev->mdio_ph, 0))
2558 dev->mdio_ph = 0;
2559 if (emac_read_uint_prop(np, "zmii-device", &dev->zmii_ph, 0))
2560 dev->zmii_ph = 0;
2561 if (emac_read_uint_prop(np, "zmii-channel", &dev->zmii_port, 0))
2562 dev->zmii_port = 0xffffffff;
2563 if (emac_read_uint_prop(np, "rgmii-device", &dev->rgmii_ph, 0))
2564 dev->rgmii_ph = 0;
2565 if (emac_read_uint_prop(np, "rgmii-channel", &dev->rgmii_port, 0))
2566 dev->rgmii_port = 0xffffffff;
2567 if (emac_read_uint_prop(np, "fifo-entry-size", &dev->fifo_entry_size, 0))
2568 dev->fifo_entry_size = 16;
2569 if (emac_read_uint_prop(np, "mal-burst-size", &dev->mal_burst_size, 0))
2570 dev->mal_burst_size = 256;
2571
2572 /* PHY mode needs some decoding */
2573 dev->phy_mode = of_get_phy_mode(np);
2574 if (dev->phy_mode < 0)
2575 dev->phy_mode = PHY_MODE_NA;
2576
2577 /* Check EMAC version */
2578 if (of_device_is_compatible(np, "ibm,emac4sync")) {
2579 dev->features |= (EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC);
2580 if (of_device_is_compatible(np, "ibm,emac-460ex") ||
2581 of_device_is_compatible(np, "ibm,emac-460gt"))
2582 dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX;
2583 if (of_device_is_compatible(np, "ibm,emac-405ex") ||
2584 of_device_is_compatible(np, "ibm,emac-405exr"))
2585 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
2586 if (of_device_is_compatible(np, "ibm,emac-apm821xx")) {
2587 dev->features |= (EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE |
2588 EMAC_FTR_APM821XX_NO_HALF_DUPLEX |
2589 EMAC_FTR_460EX_PHY_CLK_FIX);
2590 }
2591 } else if (of_device_is_compatible(np, "ibm,emac4")) {
2592 dev->features |= EMAC_FTR_EMAC4;
2593 if (of_device_is_compatible(np, "ibm,emac-440gx"))
2594 dev->features |= EMAC_FTR_440GX_PHY_CLK_FIX;
2595 } else {
2596 if (of_device_is_compatible(np, "ibm,emac-440ep") ||
2597 of_device_is_compatible(np, "ibm,emac-440gr"))
2598 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
2599 if (of_device_is_compatible(np, "ibm,emac-405ez")) {
2600#ifdef CONFIG_IBM_EMAC_NO_FLOW_CTRL
2601 dev->features |= EMAC_FTR_NO_FLOW_CONTROL_40x;
2602#else
2603 printk(KERN_ERR "%s: Flow control not disabled!\n",
2604 np->full_name);
2605 return -ENXIO;
2606#endif
2607 }
2608
2609 }
2610
2611 /* Fixup some feature bits based on the device tree */
2612 if (of_get_property(np, "has-inverted-stacr-oc", NULL))
2613 dev->features |= EMAC_FTR_STACR_OC_INVERT;
2614 if (of_get_property(np, "has-new-stacr-staopc", NULL))
2615 dev->features |= EMAC_FTR_HAS_NEW_STACR;
2616
2617 /* CAB lacks the appropriate properties */
2618 if (of_device_is_compatible(np, "ibm,emac-axon"))
2619 dev->features |= EMAC_FTR_HAS_NEW_STACR |
2620 EMAC_FTR_STACR_OC_INVERT;
2621
2622 /* Enable TAH/ZMII/RGMII features as found */
2623 if (dev->tah_ph != 0) {
2624#ifdef CONFIG_IBM_EMAC_TAH
2625 dev->features |= EMAC_FTR_HAS_TAH;
2626#else
2627 printk(KERN_ERR "%s: TAH support not enabled !\n",
2628 np->full_name);
2629 return -ENXIO;
2630#endif
2631 }
2632
2633 if (dev->zmii_ph != 0) {
2634#ifdef CONFIG_IBM_EMAC_ZMII
2635 dev->features |= EMAC_FTR_HAS_ZMII;
2636#else
2637 printk(KERN_ERR "%s: ZMII support not enabled !\n",
2638 np->full_name);
2639 return -ENXIO;
2640#endif
2641 }
2642
2643 if (dev->rgmii_ph != 0) {
2644#ifdef CONFIG_IBM_EMAC_RGMII
2645 dev->features |= EMAC_FTR_HAS_RGMII;
2646#else
2647 printk(KERN_ERR "%s: RGMII support not enabled !\n",
2648 np->full_name);
2649 return -ENXIO;
2650#endif
2651 }
2652
2653 /* Read MAC-address */
2654 p = of_get_property(np, "local-mac-address", NULL);
2655 if (p == NULL) {
2656 printk(KERN_ERR "%s: Can't find local-mac-address property\n",
2657 np->full_name);
2658 return -ENXIO;
2659 }
2660 memcpy(dev->ndev->dev_addr, p, 6);
2661
2662 /* IAHT and GAHT filter parameterization */
2663 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) {
2664 dev->xaht_slots_shift = EMAC4SYNC_XAHT_SLOTS_SHIFT;
2665 dev->xaht_width_shift = EMAC4SYNC_XAHT_WIDTH_SHIFT;
2666 } else {
2667 dev->xaht_slots_shift = EMAC4_XAHT_SLOTS_SHIFT;
2668 dev->xaht_width_shift = EMAC4_XAHT_WIDTH_SHIFT;
2669 }
2670
2671 DBG(dev, "features : 0x%08x / 0x%08x\n", dev->features, EMAC_FTRS_POSSIBLE);
2672 DBG(dev, "tx_fifo_size : %d (%d gige)\n", dev->tx_fifo_size, dev->tx_fifo_size_gige);
2673 DBG(dev, "rx_fifo_size : %d (%d gige)\n", dev->rx_fifo_size, dev->rx_fifo_size_gige);
2674 DBG(dev, "max_mtu : %d\n", dev->max_mtu);
2675 DBG(dev, "OPB freq : %d\n", dev->opb_bus_freq);
2676
2677 return 0;
2678}
2679
2680static const struct net_device_ops emac_netdev_ops = {
2681 .ndo_open = emac_open,
2682 .ndo_stop = emac_close,
2683 .ndo_get_stats = emac_stats,
2684 .ndo_set_rx_mode = emac_set_multicast_list,
2685 .ndo_do_ioctl = emac_ioctl,
2686 .ndo_tx_timeout = emac_tx_timeout,
2687 .ndo_validate_addr = eth_validate_addr,
2688 .ndo_set_mac_address = eth_mac_addr,
2689 .ndo_start_xmit = emac_start_xmit,
2690 .ndo_change_mtu = eth_change_mtu,
2691};
2692
2693static const struct net_device_ops emac_gige_netdev_ops = {
2694 .ndo_open = emac_open,
2695 .ndo_stop = emac_close,
2696 .ndo_get_stats = emac_stats,
2697 .ndo_set_rx_mode = emac_set_multicast_list,
2698 .ndo_do_ioctl = emac_ioctl,
2699 .ndo_tx_timeout = emac_tx_timeout,
2700 .ndo_validate_addr = eth_validate_addr,
2701 .ndo_set_mac_address = eth_mac_addr,
2702 .ndo_start_xmit = emac_start_xmit_sg,
2703 .ndo_change_mtu = emac_change_mtu,
2704};
2705
2706static int __devinit emac_probe(struct platform_device *ofdev)
2707{
2708 struct net_device *ndev;
2709 struct emac_instance *dev;
2710 struct device_node *np = ofdev->dev.of_node;
2711 struct device_node **blist = NULL;
2712 int err, i;
2713
2714 /* Skip unused/unwired EMACS. We leave the check for an unused
2715 * property here for now, but new flat device trees should set a
2716 * status property to "disabled" instead.
2717 */
2718 if (of_get_property(np, "unused", NULL) || !of_device_is_available(np))
2719 return -ENODEV;
2720
2721 /* Find ourselves in the bootlist if we are there */
2722 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
2723 if (emac_boot_list[i] == np)
2724 blist = &emac_boot_list[i];
2725
2726 /* Allocate our net_device structure */
2727 err = -ENOMEM;
2728 ndev = alloc_etherdev(sizeof(struct emac_instance));
2729 if (!ndev)
2730 goto err_gone;
2731
2732 dev = netdev_priv(ndev);
2733 dev->ndev = ndev;
2734 dev->ofdev = ofdev;
2735 dev->blist = blist;
2736 SET_NETDEV_DEV(ndev, &ofdev->dev);
2737
2738 /* Initialize some embedded data structures */
2739 mutex_init(&dev->mdio_lock);
2740 mutex_init(&dev->link_lock);
2741 spin_lock_init(&dev->lock);
2742 INIT_WORK(&dev->reset_work, emac_reset_work);
2743
2744 /* Init various config data based on device-tree */
2745 err = emac_init_config(dev);
2746 if (err != 0)
2747 goto err_free;
2748
2749 /* Get interrupts. EMAC irq is mandatory, WOL irq is optional */
2750 dev->emac_irq = irq_of_parse_and_map(np, 0);
2751 dev->wol_irq = irq_of_parse_and_map(np, 1);
2752 if (dev->emac_irq == NO_IRQ) {
2753 printk(KERN_ERR "%s: Can't map main interrupt\n", np->full_name);
2754 goto err_free;
2755 }
2756 ndev->irq = dev->emac_irq;
2757
2758 /* Map EMAC regs */
2759 if (of_address_to_resource(np, 0, &dev->rsrc_regs)) {
2760 printk(KERN_ERR "%s: Can't get registers address\n",
2761 np->full_name);
2762 goto err_irq_unmap;
2763 }
2764 // TODO : request_mem_region
2765 dev->emacp = ioremap(dev->rsrc_regs.start,
2766 resource_size(&dev->rsrc_regs));
2767 if (dev->emacp == NULL) {
2768 printk(KERN_ERR "%s: Can't map device registers!\n",
2769 np->full_name);
2770 err = -ENOMEM;
2771 goto err_irq_unmap;
2772 }
2773
2774 /* Wait for dependent devices */
2775 err = emac_wait_deps(dev);
2776 if (err) {
2777 printk(KERN_ERR
2778 "%s: Timeout waiting for dependent devices\n",
2779 np->full_name);
2780 /* display more info about what's missing ? */
2781 goto err_reg_unmap;
2782 }
2783 dev->mal = dev_get_drvdata(&dev->mal_dev->dev);
2784 if (dev->mdio_dev != NULL)
2785 dev->mdio_instance = dev_get_drvdata(&dev->mdio_dev->dev);
2786
2787 /* Register with MAL */
2788 dev->commac.ops = &emac_commac_ops;
2789 dev->commac.dev = dev;
2790 dev->commac.tx_chan_mask = MAL_CHAN_MASK(dev->mal_tx_chan);
2791 dev->commac.rx_chan_mask = MAL_CHAN_MASK(dev->mal_rx_chan);
2792 err = mal_register_commac(dev->mal, &dev->commac);
2793 if (err) {
2794 printk(KERN_ERR "%s: failed to register with mal %s!\n",
2795 np->full_name, dev->mal_dev->dev.of_node->full_name);
2796 goto err_rel_deps;
2797 }
2798 dev->rx_skb_size = emac_rx_skb_size(ndev->mtu);
2799 dev->rx_sync_size = emac_rx_sync_size(ndev->mtu);
2800
2801 /* Get pointers to BD rings */
2802 dev->tx_desc =
2803 dev->mal->bd_virt + mal_tx_bd_offset(dev->mal, dev->mal_tx_chan);
2804 dev->rx_desc =
2805 dev->mal->bd_virt + mal_rx_bd_offset(dev->mal, dev->mal_rx_chan);
2806
2807 DBG(dev, "tx_desc %p" NL, dev->tx_desc);
2808 DBG(dev, "rx_desc %p" NL, dev->rx_desc);
2809
2810 /* Clean rings */
2811 memset(dev->tx_desc, 0, NUM_TX_BUFF * sizeof(struct mal_descriptor));
2812 memset(dev->rx_desc, 0, NUM_RX_BUFF * sizeof(struct mal_descriptor));
2813 memset(dev->tx_skb, 0, NUM_TX_BUFF * sizeof(struct sk_buff *));
2814 memset(dev->rx_skb, 0, NUM_RX_BUFF * sizeof(struct sk_buff *));
2815
2816 /* Attach to ZMII, if needed */
2817 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII) &&
2818 (err = zmii_attach(dev->zmii_dev, dev->zmii_port, &dev->phy_mode)) != 0)
2819 goto err_unreg_commac;
2820
2821 /* Attach to RGMII, if needed */
2822 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII) &&
2823 (err = rgmii_attach(dev->rgmii_dev, dev->rgmii_port, dev->phy_mode)) != 0)
2824 goto err_detach_zmii;
2825
2826 /* Attach to TAH, if needed */
2827 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
2828 (err = tah_attach(dev->tah_dev, dev->tah_port)) != 0)
2829 goto err_detach_rgmii;
2830
2831 /* Set some link defaults before we can find out real parameters */
2832 dev->phy.speed = SPEED_100;
2833 dev->phy.duplex = DUPLEX_FULL;
2834 dev->phy.autoneg = AUTONEG_DISABLE;
2835 dev->phy.pause = dev->phy.asym_pause = 0;
2836 dev->stop_timeout = STOP_TIMEOUT_100;
2837 INIT_DELAYED_WORK(&dev->link_work, emac_link_timer);
2838
2839 /* Some SoCs like APM821xx does not support Half Duplex mode. */
2840 if (emac_has_feature(dev, EMAC_FTR_APM821XX_NO_HALF_DUPLEX)) {
2841 dev->phy_feat_exc = (SUPPORTED_1000baseT_Half |
2842 SUPPORTED_100baseT_Half |
2843 SUPPORTED_10baseT_Half);
2844 }
2845
2846 /* Find PHY if any */
2847 err = emac_init_phy(dev);
2848 if (err != 0)
2849 goto err_detach_tah;
2850
2851 if (dev->tah_dev) {
2852 ndev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG;
2853 ndev->features |= ndev->hw_features | NETIF_F_RXCSUM;
2854 }
2855 ndev->watchdog_timeo = 5 * HZ;
2856 if (emac_phy_supports_gige(dev->phy_mode)) {
2857 ndev->netdev_ops = &emac_gige_netdev_ops;
2858 dev->commac.ops = &emac_commac_sg_ops;
2859 } else
2860 ndev->netdev_ops = &emac_netdev_ops;
2861 SET_ETHTOOL_OPS(ndev, &emac_ethtool_ops);
2862
2863 netif_carrier_off(ndev);
2864
2865 err = register_netdev(ndev);
2866 if (err) {
2867 printk(KERN_ERR "%s: failed to register net device (%d)!\n",
2868 np->full_name, err);
2869 goto err_detach_tah;
2870 }
2871
2872 /* Set our drvdata last as we don't want them visible until we are
2873 * fully initialized
2874 */
2875 wmb();
2876 dev_set_drvdata(&ofdev->dev, dev);
2877
2878 /* There's a new kid in town ! Let's tell everybody */
2879 wake_up_all(&emac_probe_wait);
2880
2881
2882 printk(KERN_INFO "%s: EMAC-%d %s, MAC %pM\n",
2883 ndev->name, dev->cell_index, np->full_name, ndev->dev_addr);
2884
2885 if (dev->phy_mode == PHY_MODE_SGMII)
2886 printk(KERN_NOTICE "%s: in SGMII mode\n", ndev->name);
2887
2888 if (dev->phy.address >= 0)
2889 printk("%s: found %s PHY (0x%02x)\n", ndev->name,
2890 dev->phy.def->name, dev->phy.address);
2891
2892 emac_dbg_register(dev);
2893
2894 /* Life is good */
2895 return 0;
2896
2897 /* I have a bad feeling about this ... */
2898
2899 err_detach_tah:
2900 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2901 tah_detach(dev->tah_dev, dev->tah_port);
2902 err_detach_rgmii:
2903 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2904 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
2905 err_detach_zmii:
2906 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2907 zmii_detach(dev->zmii_dev, dev->zmii_port);
2908 err_unreg_commac:
2909 mal_unregister_commac(dev->mal, &dev->commac);
2910 err_rel_deps:
2911 emac_put_deps(dev);
2912 err_reg_unmap:
2913 iounmap(dev->emacp);
2914 err_irq_unmap:
2915 if (dev->wol_irq != NO_IRQ)
2916 irq_dispose_mapping(dev->wol_irq);
2917 if (dev->emac_irq != NO_IRQ)
2918 irq_dispose_mapping(dev->emac_irq);
2919 err_free:
2920 free_netdev(ndev);
2921 err_gone:
2922 /* if we were on the bootlist, remove us as we won't show up and
2923 * wake up all waiters to notify them in case they were waiting
2924 * on us
2925 */
2926 if (blist) {
2927 *blist = NULL;
2928 wake_up_all(&emac_probe_wait);
2929 }
2930 return err;
2931}
2932
2933static int __devexit emac_remove(struct platform_device *ofdev)
2934{
2935 struct emac_instance *dev = dev_get_drvdata(&ofdev->dev);
2936
2937 DBG(dev, "remove" NL);
2938
2939 dev_set_drvdata(&ofdev->dev, NULL);
2940
2941 unregister_netdev(dev->ndev);
2942
2943 cancel_work_sync(&dev->reset_work);
2944
2945 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2946 tah_detach(dev->tah_dev, dev->tah_port);
2947 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2948 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
2949 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2950 zmii_detach(dev->zmii_dev, dev->zmii_port);
2951
2952 busy_phy_map &= ~(1 << dev->phy.address);
2953 DBG(dev, "busy_phy_map now %#x" NL, busy_phy_map);
2954
2955 mal_unregister_commac(dev->mal, &dev->commac);
2956 emac_put_deps(dev);
2957
2958 emac_dbg_unregister(dev);
2959 iounmap(dev->emacp);
2960
2961 if (dev->wol_irq != NO_IRQ)
2962 irq_dispose_mapping(dev->wol_irq);
2963 if (dev->emac_irq != NO_IRQ)
2964 irq_dispose_mapping(dev->emac_irq);
2965
2966 free_netdev(dev->ndev);
2967
2968 return 0;
2969}
2970
2971/* XXX Features in here should be replaced by properties... */
2972static struct of_device_id emac_match[] =
2973{
2974 {
2975 .type = "network",
2976 .compatible = "ibm,emac",
2977 },
2978 {
2979 .type = "network",
2980 .compatible = "ibm,emac4",
2981 },
2982 {
2983 .type = "network",
2984 .compatible = "ibm,emac4sync",
2985 },
2986 {},
2987};
2988MODULE_DEVICE_TABLE(of, emac_match);
2989
2990static struct platform_driver emac_driver = {
2991 .driver = {
2992 .name = "emac",
2993 .owner = THIS_MODULE,
2994 .of_match_table = emac_match,
2995 },
2996 .probe = emac_probe,
2997 .remove = emac_remove,
2998};
2999
3000static void __init emac_make_bootlist(void)
3001{
3002 struct device_node *np = NULL;
3003 int j, max, i = 0, k;
3004 int cell_indices[EMAC_BOOT_LIST_SIZE];
3005
3006 /* Collect EMACs */
3007 while((np = of_find_all_nodes(np)) != NULL) {
3008 const u32 *idx;
3009
3010 if (of_match_node(emac_match, np) == NULL)
3011 continue;
3012 if (of_get_property(np, "unused", NULL))
3013 continue;
3014 idx = of_get_property(np, "cell-index", NULL);
3015 if (idx == NULL)
3016 continue;
3017 cell_indices[i] = *idx;
3018 emac_boot_list[i++] = of_node_get(np);
3019 if (i >= EMAC_BOOT_LIST_SIZE) {
3020 of_node_put(np);
3021 break;
3022 }
3023 }
3024 max = i;
3025
3026 /* Bubble sort them (doh, what a creative algorithm :-) */
3027 for (i = 0; max > 1 && (i < (max - 1)); i++)
3028 for (j = i; j < max; j++) {
3029 if (cell_indices[i] > cell_indices[j]) {
3030 np = emac_boot_list[i];
3031 emac_boot_list[i] = emac_boot_list[j];
3032 emac_boot_list[j] = np;
3033 k = cell_indices[i];
3034 cell_indices[i] = cell_indices[j];
3035 cell_indices[j] = k;
3036 }
3037 }
3038}
3039
3040static int __init emac_init(void)
3041{
3042 int rc;
3043
3044 printk(KERN_INFO DRV_DESC ", version " DRV_VERSION "\n");
3045
3046 /* Init debug stuff */
3047 emac_init_debug();
3048
3049 /* Build EMAC boot list */
3050 emac_make_bootlist();
3051
3052 /* Init submodules */
3053 rc = mal_init();
3054 if (rc)
3055 goto err;
3056 rc = zmii_init();
3057 if (rc)
3058 goto err_mal;
3059 rc = rgmii_init();
3060 if (rc)
3061 goto err_zmii;
3062 rc = tah_init();
3063 if (rc)
3064 goto err_rgmii;
3065 rc = platform_driver_register(&emac_driver);
3066 if (rc)
3067 goto err_tah;
3068
3069 return 0;
3070
3071 err_tah:
3072 tah_exit();
3073 err_rgmii:
3074 rgmii_exit();
3075 err_zmii:
3076 zmii_exit();
3077 err_mal:
3078 mal_exit();
3079 err:
3080 return rc;
3081}
3082
3083static void __exit emac_exit(void)
3084{
3085 int i;
3086
3087 platform_driver_unregister(&emac_driver);
3088
3089 tah_exit();
3090 rgmii_exit();
3091 zmii_exit();
3092 mal_exit();
3093 emac_fini_debug();
3094
3095 /* Destroy EMAC boot list */
3096 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
3097 if (emac_boot_list[i])
3098 of_node_put(emac_boot_list[i]);
3099}
3100
3101module_init(emac_init);
3102module_exit(emac_exit);