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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * IOMMU API for Rockchip
4 *
5 * Module Authors: Simon Xue <xxm@rock-chips.com>
6 * Daniel Kurtz <djkurtz@chromium.org>
7 */
8
9#include <linux/clk.h>
10#include <linux/compiler.h>
11#include <linux/delay.h>
12#include <linux/device.h>
13#include <linux/dma-mapping.h>
14#include <linux/errno.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/iommu.h>
18#include <linux/iopoll.h>
19#include <linux/list.h>
20#include <linux/mm.h>
21#include <linux/init.h>
22#include <linux/of.h>
23#include <linux/of_platform.h>
24#include <linux/platform_device.h>
25#include <linux/pm_runtime.h>
26#include <linux/slab.h>
27#include <linux/spinlock.h>
28
29#include "iommu-pages.h"
30
31/** MMU register offsets */
32#define RK_MMU_DTE_ADDR 0x00 /* Directory table address */
33#define RK_MMU_STATUS 0x04
34#define RK_MMU_COMMAND 0x08
35#define RK_MMU_PAGE_FAULT_ADDR 0x0C /* IOVA of last page fault */
36#define RK_MMU_ZAP_ONE_LINE 0x10 /* Shootdown one IOTLB entry */
37#define RK_MMU_INT_RAWSTAT 0x14 /* IRQ status ignoring mask */
38#define RK_MMU_INT_CLEAR 0x18 /* Acknowledge and re-arm irq */
39#define RK_MMU_INT_MASK 0x1C /* IRQ enable */
40#define RK_MMU_INT_STATUS 0x20 /* IRQ status after masking */
41#define RK_MMU_AUTO_GATING 0x24
42
43#define DTE_ADDR_DUMMY 0xCAFEBABE
44
45#define RK_MMU_POLL_PERIOD_US 100
46#define RK_MMU_FORCE_RESET_TIMEOUT_US 100000
47#define RK_MMU_POLL_TIMEOUT_US 1000
48
49/* RK_MMU_STATUS fields */
50#define RK_MMU_STATUS_PAGING_ENABLED BIT(0)
51#define RK_MMU_STATUS_PAGE_FAULT_ACTIVE BIT(1)
52#define RK_MMU_STATUS_STALL_ACTIVE BIT(2)
53#define RK_MMU_STATUS_IDLE BIT(3)
54#define RK_MMU_STATUS_REPLAY_BUFFER_EMPTY BIT(4)
55#define RK_MMU_STATUS_PAGE_FAULT_IS_WRITE BIT(5)
56#define RK_MMU_STATUS_STALL_NOT_ACTIVE BIT(31)
57
58/* RK_MMU_COMMAND command values */
59#define RK_MMU_CMD_ENABLE_PAGING 0 /* Enable memory translation */
60#define RK_MMU_CMD_DISABLE_PAGING 1 /* Disable memory translation */
61#define RK_MMU_CMD_ENABLE_STALL 2 /* Stall paging to allow other cmds */
62#define RK_MMU_CMD_DISABLE_STALL 3 /* Stop stall re-enables paging */
63#define RK_MMU_CMD_ZAP_CACHE 4 /* Shoot down entire IOTLB */
64#define RK_MMU_CMD_PAGE_FAULT_DONE 5 /* Clear page fault */
65#define RK_MMU_CMD_FORCE_RESET 6 /* Reset all registers */
66
67/* RK_MMU_INT_* register fields */
68#define RK_MMU_IRQ_PAGE_FAULT 0x01 /* page fault */
69#define RK_MMU_IRQ_BUS_ERROR 0x02 /* bus read error */
70#define RK_MMU_IRQ_MASK (RK_MMU_IRQ_PAGE_FAULT | RK_MMU_IRQ_BUS_ERROR)
71
72#define NUM_DT_ENTRIES 1024
73#define NUM_PT_ENTRIES 1024
74
75#define SPAGE_ORDER 12
76#define SPAGE_SIZE (1 << SPAGE_ORDER)
77
78 /*
79 * Support mapping any size that fits in one page table:
80 * 4 KiB to 4 MiB
81 */
82#define RK_IOMMU_PGSIZE_BITMAP 0x007ff000
83
84struct rk_iommu_domain {
85 struct list_head iommus;
86 u32 *dt; /* page directory table */
87 dma_addr_t dt_dma;
88 spinlock_t iommus_lock; /* lock for iommus list */
89 spinlock_t dt_lock; /* lock for modifying page directory table */
90
91 struct iommu_domain domain;
92};
93
94/* list of clocks required by IOMMU */
95static const char * const rk_iommu_clocks[] = {
96 "aclk", "iface",
97};
98
99struct rk_iommu_ops {
100 phys_addr_t (*pt_address)(u32 dte);
101 u32 (*mk_dtentries)(dma_addr_t pt_dma);
102 u32 (*mk_ptentries)(phys_addr_t page, int prot);
103 u64 dma_bit_mask;
104 gfp_t gfp_flags;
105};
106
107struct rk_iommu {
108 struct device *dev;
109 void __iomem **bases;
110 int num_mmu;
111 int num_irq;
112 struct clk_bulk_data *clocks;
113 int num_clocks;
114 bool reset_disabled;
115 struct iommu_device iommu;
116 struct list_head node; /* entry in rk_iommu_domain.iommus */
117 struct iommu_domain *domain; /* domain to which iommu is attached */
118};
119
120struct rk_iommudata {
121 struct device_link *link; /* runtime PM link from IOMMU to master */
122 struct rk_iommu *iommu;
123};
124
125static struct device *dma_dev;
126static const struct rk_iommu_ops *rk_ops;
127static struct iommu_domain rk_identity_domain;
128
129static inline void rk_table_flush(struct rk_iommu_domain *dom, dma_addr_t dma,
130 unsigned int count)
131{
132 size_t size = count * sizeof(u32); /* count of u32 entry */
133
134 dma_sync_single_for_device(dma_dev, dma, size, DMA_TO_DEVICE);
135}
136
137static struct rk_iommu_domain *to_rk_domain(struct iommu_domain *dom)
138{
139 return container_of(dom, struct rk_iommu_domain, domain);
140}
141
142/*
143 * The Rockchip rk3288 iommu uses a 2-level page table.
144 * The first level is the "Directory Table" (DT).
145 * The DT consists of 1024 4-byte Directory Table Entries (DTEs), each pointing
146 * to a "Page Table".
147 * The second level is the 1024 Page Tables (PT).
148 * Each PT consists of 1024 4-byte Page Table Entries (PTEs), each pointing to
149 * a 4 KB page of physical memory.
150 *
151 * The DT and each PT fits in a single 4 KB page (4-bytes * 1024 entries).
152 * Each iommu device has a MMU_DTE_ADDR register that contains the physical
153 * address of the start of the DT page.
154 *
155 * The structure of the page table is as follows:
156 *
157 * DT
158 * MMU_DTE_ADDR -> +-----+
159 * | |
160 * +-----+ PT
161 * | DTE | -> +-----+
162 * +-----+ | | Memory
163 * | | +-----+ Page
164 * | | | PTE | -> +-----+
165 * +-----+ +-----+ | |
166 * | | | |
167 * | | | |
168 * +-----+ | |
169 * | |
170 * | |
171 * +-----+
172 */
173
174/*
175 * Each DTE has a PT address and a valid bit:
176 * +---------------------+-----------+-+
177 * | PT address | Reserved |V|
178 * +---------------------+-----------+-+
179 * 31:12 - PT address (PTs always starts on a 4 KB boundary)
180 * 11: 1 - Reserved
181 * 0 - 1 if PT @ PT address is valid
182 */
183#define RK_DTE_PT_ADDRESS_MASK 0xfffff000
184#define RK_DTE_PT_VALID BIT(0)
185
186static inline phys_addr_t rk_dte_pt_address(u32 dte)
187{
188 return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK;
189}
190
191/*
192 * In v2:
193 * 31:12 - PT address bit 31:0
194 * 11: 8 - PT address bit 35:32
195 * 7: 4 - PT address bit 39:36
196 * 3: 1 - Reserved
197 * 0 - 1 if PT @ PT address is valid
198 */
199#define RK_DTE_PT_ADDRESS_MASK_V2 GENMASK_ULL(31, 4)
200#define DTE_HI_MASK1 GENMASK(11, 8)
201#define DTE_HI_MASK2 GENMASK(7, 4)
202#define DTE_HI_SHIFT1 24 /* shift bit 8 to bit 32 */
203#define DTE_HI_SHIFT2 32 /* shift bit 4 to bit 36 */
204#define PAGE_DESC_HI_MASK1 GENMASK_ULL(35, 32)
205#define PAGE_DESC_HI_MASK2 GENMASK_ULL(39, 36)
206
207static inline phys_addr_t rk_dte_pt_address_v2(u32 dte)
208{
209 u64 dte_v2 = dte;
210
211 dte_v2 = ((dte_v2 & DTE_HI_MASK2) << DTE_HI_SHIFT2) |
212 ((dte_v2 & DTE_HI_MASK1) << DTE_HI_SHIFT1) |
213 (dte_v2 & RK_DTE_PT_ADDRESS_MASK);
214
215 return (phys_addr_t)dte_v2;
216}
217
218static inline bool rk_dte_is_pt_valid(u32 dte)
219{
220 return dte & RK_DTE_PT_VALID;
221}
222
223static inline u32 rk_mk_dte(dma_addr_t pt_dma)
224{
225 return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID;
226}
227
228static inline u32 rk_mk_dte_v2(dma_addr_t pt_dma)
229{
230 pt_dma = (pt_dma & RK_DTE_PT_ADDRESS_MASK) |
231 ((pt_dma & PAGE_DESC_HI_MASK1) >> DTE_HI_SHIFT1) |
232 (pt_dma & PAGE_DESC_HI_MASK2) >> DTE_HI_SHIFT2;
233
234 return (pt_dma & RK_DTE_PT_ADDRESS_MASK_V2) | RK_DTE_PT_VALID;
235}
236
237/*
238 * Each PTE has a Page address, some flags and a valid bit:
239 * +---------------------+---+-------+-+
240 * | Page address |Rsv| Flags |V|
241 * +---------------------+---+-------+-+
242 * 31:12 - Page address (Pages always start on a 4 KB boundary)
243 * 11: 9 - Reserved
244 * 8: 1 - Flags
245 * 8 - Read allocate - allocate cache space on read misses
246 * 7 - Read cache - enable cache & prefetch of data
247 * 6 - Write buffer - enable delaying writes on their way to memory
248 * 5 - Write allocate - allocate cache space on write misses
249 * 4 - Write cache - different writes can be merged together
250 * 3 - Override cache attributes
251 * if 1, bits 4-8 control cache attributes
252 * if 0, the system bus defaults are used
253 * 2 - Writable
254 * 1 - Readable
255 * 0 - 1 if Page @ Page address is valid
256 */
257#define RK_PTE_PAGE_ADDRESS_MASK 0xfffff000
258#define RK_PTE_PAGE_FLAGS_MASK 0x000001fe
259#define RK_PTE_PAGE_WRITABLE BIT(2)
260#define RK_PTE_PAGE_READABLE BIT(1)
261#define RK_PTE_PAGE_VALID BIT(0)
262
263static inline bool rk_pte_is_page_valid(u32 pte)
264{
265 return pte & RK_PTE_PAGE_VALID;
266}
267
268/* TODO: set cache flags per prot IOMMU_CACHE */
269static u32 rk_mk_pte(phys_addr_t page, int prot)
270{
271 u32 flags = 0;
272 flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0;
273 flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0;
274 page &= RK_PTE_PAGE_ADDRESS_MASK;
275 return page | flags | RK_PTE_PAGE_VALID;
276}
277
278/*
279 * In v2:
280 * 31:12 - Page address bit 31:0
281 * 11: 8 - Page address bit 35:32
282 * 7: 4 - Page address bit 39:36
283 * 3 - Security
284 * 2 - Writable
285 * 1 - Readable
286 * 0 - 1 if Page @ Page address is valid
287 */
288
289static u32 rk_mk_pte_v2(phys_addr_t page, int prot)
290{
291 u32 flags = 0;
292
293 flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0;
294 flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0;
295
296 return rk_mk_dte_v2(page) | flags;
297}
298
299static u32 rk_mk_pte_invalid(u32 pte)
300{
301 return pte & ~RK_PTE_PAGE_VALID;
302}
303
304/*
305 * rk3288 iova (IOMMU Virtual Address) format
306 * 31 22.21 12.11 0
307 * +-----------+-----------+-------------+
308 * | DTE index | PTE index | Page offset |
309 * +-----------+-----------+-------------+
310 * 31:22 - DTE index - index of DTE in DT
311 * 21:12 - PTE index - index of PTE in PT @ DTE.pt_address
312 * 11: 0 - Page offset - offset into page @ PTE.page_address
313 */
314#define RK_IOVA_DTE_MASK 0xffc00000
315#define RK_IOVA_DTE_SHIFT 22
316#define RK_IOVA_PTE_MASK 0x003ff000
317#define RK_IOVA_PTE_SHIFT 12
318#define RK_IOVA_PAGE_MASK 0x00000fff
319#define RK_IOVA_PAGE_SHIFT 0
320
321static u32 rk_iova_dte_index(dma_addr_t iova)
322{
323 return (u32)(iova & RK_IOVA_DTE_MASK) >> RK_IOVA_DTE_SHIFT;
324}
325
326static u32 rk_iova_pte_index(dma_addr_t iova)
327{
328 return (u32)(iova & RK_IOVA_PTE_MASK) >> RK_IOVA_PTE_SHIFT;
329}
330
331static u32 rk_iova_page_offset(dma_addr_t iova)
332{
333 return (u32)(iova & RK_IOVA_PAGE_MASK) >> RK_IOVA_PAGE_SHIFT;
334}
335
336static u32 rk_iommu_read(void __iomem *base, u32 offset)
337{
338 return readl(base + offset);
339}
340
341static void rk_iommu_write(void __iomem *base, u32 offset, u32 value)
342{
343 writel(value, base + offset);
344}
345
346static void rk_iommu_command(struct rk_iommu *iommu, u32 command)
347{
348 int i;
349
350 for (i = 0; i < iommu->num_mmu; i++)
351 writel(command, iommu->bases[i] + RK_MMU_COMMAND);
352}
353
354static void rk_iommu_base_command(void __iomem *base, u32 command)
355{
356 writel(command, base + RK_MMU_COMMAND);
357}
358static void rk_iommu_zap_lines(struct rk_iommu *iommu, dma_addr_t iova_start,
359 size_t size)
360{
361 int i;
362 dma_addr_t iova_end = iova_start + size;
363 /*
364 * TODO(djkurtz): Figure out when it is more efficient to shootdown the
365 * entire iotlb rather than iterate over individual iovas.
366 */
367 for (i = 0; i < iommu->num_mmu; i++) {
368 dma_addr_t iova;
369
370 for (iova = iova_start; iova < iova_end; iova += SPAGE_SIZE)
371 rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova);
372 }
373}
374
375static bool rk_iommu_is_stall_active(struct rk_iommu *iommu)
376{
377 bool active = true;
378 int i;
379
380 for (i = 0; i < iommu->num_mmu; i++)
381 active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) &
382 RK_MMU_STATUS_STALL_ACTIVE);
383
384 return active;
385}
386
387static bool rk_iommu_is_paging_enabled(struct rk_iommu *iommu)
388{
389 bool enable = true;
390 int i;
391
392 for (i = 0; i < iommu->num_mmu; i++)
393 enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) &
394 RK_MMU_STATUS_PAGING_ENABLED);
395
396 return enable;
397}
398
399static bool rk_iommu_is_reset_done(struct rk_iommu *iommu)
400{
401 bool done = true;
402 int i;
403
404 for (i = 0; i < iommu->num_mmu; i++)
405 done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0;
406
407 return done;
408}
409
410static int rk_iommu_enable_stall(struct rk_iommu *iommu)
411{
412 int ret, i;
413 bool val;
414
415 if (rk_iommu_is_stall_active(iommu))
416 return 0;
417
418 /* Stall can only be enabled if paging is enabled */
419 if (!rk_iommu_is_paging_enabled(iommu))
420 return 0;
421
422 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_STALL);
423
424 ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val,
425 val, RK_MMU_POLL_PERIOD_US,
426 RK_MMU_POLL_TIMEOUT_US);
427 if (ret)
428 for (i = 0; i < iommu->num_mmu; i++)
429 dev_err(iommu->dev, "Enable stall request timed out, status: %#08x\n",
430 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
431
432 return ret;
433}
434
435static int rk_iommu_disable_stall(struct rk_iommu *iommu)
436{
437 int ret, i;
438 bool val;
439
440 if (!rk_iommu_is_stall_active(iommu))
441 return 0;
442
443 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_STALL);
444
445 ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val,
446 !val, RK_MMU_POLL_PERIOD_US,
447 RK_MMU_POLL_TIMEOUT_US);
448 if (ret)
449 for (i = 0; i < iommu->num_mmu; i++)
450 dev_err(iommu->dev, "Disable stall request timed out, status: %#08x\n",
451 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
452
453 return ret;
454}
455
456static int rk_iommu_enable_paging(struct rk_iommu *iommu)
457{
458 int ret, i;
459 bool val;
460
461 if (rk_iommu_is_paging_enabled(iommu))
462 return 0;
463
464 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_PAGING);
465
466 ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val,
467 val, RK_MMU_POLL_PERIOD_US,
468 RK_MMU_POLL_TIMEOUT_US);
469 if (ret)
470 for (i = 0; i < iommu->num_mmu; i++)
471 dev_err(iommu->dev, "Enable paging request timed out, status: %#08x\n",
472 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
473
474 return ret;
475}
476
477static int rk_iommu_disable_paging(struct rk_iommu *iommu)
478{
479 int ret, i;
480 bool val;
481
482 if (!rk_iommu_is_paging_enabled(iommu))
483 return 0;
484
485 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_PAGING);
486
487 ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val,
488 !val, RK_MMU_POLL_PERIOD_US,
489 RK_MMU_POLL_TIMEOUT_US);
490 if (ret)
491 for (i = 0; i < iommu->num_mmu; i++)
492 dev_err(iommu->dev, "Disable paging request timed out, status: %#08x\n",
493 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
494
495 return ret;
496}
497
498static int rk_iommu_force_reset(struct rk_iommu *iommu)
499{
500 int ret, i;
501 u32 dte_addr;
502 bool val;
503
504 if (iommu->reset_disabled)
505 return 0;
506
507 /*
508 * Check if register DTE_ADDR is working by writing DTE_ADDR_DUMMY
509 * and verifying that upper 5 (v1) or 7 (v2) nybbles are read back.
510 */
511 for (i = 0; i < iommu->num_mmu; i++) {
512 dte_addr = rk_ops->pt_address(DTE_ADDR_DUMMY);
513 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, dte_addr);
514
515 if (dte_addr != rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR)) {
516 dev_err(iommu->dev, "Error during raw reset. MMU_DTE_ADDR is not functioning\n");
517 return -EFAULT;
518 }
519 }
520
521 rk_iommu_command(iommu, RK_MMU_CMD_FORCE_RESET);
522
523 ret = readx_poll_timeout(rk_iommu_is_reset_done, iommu, val,
524 val, RK_MMU_FORCE_RESET_TIMEOUT_US,
525 RK_MMU_POLL_TIMEOUT_US);
526 if (ret) {
527 dev_err(iommu->dev, "FORCE_RESET command timed out\n");
528 return ret;
529 }
530
531 return 0;
532}
533
534static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova)
535{
536 void __iomem *base = iommu->bases[index];
537 u32 dte_index, pte_index, page_offset;
538 u32 mmu_dte_addr;
539 phys_addr_t mmu_dte_addr_phys, dte_addr_phys;
540 u32 *dte_addr;
541 u32 dte;
542 phys_addr_t pte_addr_phys = 0;
543 u32 *pte_addr = NULL;
544 u32 pte = 0;
545 phys_addr_t page_addr_phys = 0;
546 u32 page_flags = 0;
547
548 dte_index = rk_iova_dte_index(iova);
549 pte_index = rk_iova_pte_index(iova);
550 page_offset = rk_iova_page_offset(iova);
551
552 mmu_dte_addr = rk_iommu_read(base, RK_MMU_DTE_ADDR);
553 mmu_dte_addr_phys = rk_ops->pt_address(mmu_dte_addr);
554
555 dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index);
556 dte_addr = phys_to_virt(dte_addr_phys);
557 dte = *dte_addr;
558
559 if (!rk_dte_is_pt_valid(dte))
560 goto print_it;
561
562 pte_addr_phys = rk_ops->pt_address(dte) + (pte_index * 4);
563 pte_addr = phys_to_virt(pte_addr_phys);
564 pte = *pte_addr;
565
566 if (!rk_pte_is_page_valid(pte))
567 goto print_it;
568
569 page_addr_phys = rk_ops->pt_address(pte) + page_offset;
570 page_flags = pte & RK_PTE_PAGE_FLAGS_MASK;
571
572print_it:
573 dev_err(iommu->dev, "iova = %pad: dte_index: %#03x pte_index: %#03x page_offset: %#03x\n",
574 &iova, dte_index, pte_index, page_offset);
575 dev_err(iommu->dev, "mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa flags: %#03x\n",
576 &mmu_dte_addr_phys, &dte_addr_phys, dte,
577 rk_dte_is_pt_valid(dte), &pte_addr_phys, pte,
578 rk_pte_is_page_valid(pte), &page_addr_phys, page_flags);
579}
580
581static irqreturn_t rk_iommu_irq(int irq, void *dev_id)
582{
583 struct rk_iommu *iommu = dev_id;
584 u32 status;
585 u32 int_status;
586 dma_addr_t iova;
587 irqreturn_t ret = IRQ_NONE;
588 int i, err;
589
590 err = pm_runtime_get_if_in_use(iommu->dev);
591 if (!err || WARN_ON_ONCE(err < 0))
592 return ret;
593
594 if (WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks)))
595 goto out;
596
597 for (i = 0; i < iommu->num_mmu; i++) {
598 int_status = rk_iommu_read(iommu->bases[i], RK_MMU_INT_STATUS);
599 if (int_status == 0)
600 continue;
601
602 ret = IRQ_HANDLED;
603 iova = rk_iommu_read(iommu->bases[i], RK_MMU_PAGE_FAULT_ADDR);
604
605 if (int_status & RK_MMU_IRQ_PAGE_FAULT) {
606 int flags;
607
608 status = rk_iommu_read(iommu->bases[i], RK_MMU_STATUS);
609 flags = (status & RK_MMU_STATUS_PAGE_FAULT_IS_WRITE) ?
610 IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
611
612 dev_err(iommu->dev, "Page fault at %pad of type %s\n",
613 &iova,
614 (flags == IOMMU_FAULT_WRITE) ? "write" : "read");
615
616 log_iova(iommu, i, iova);
617
618 /*
619 * Report page fault to any installed handlers.
620 * Ignore the return code, though, since we always zap cache
621 * and clear the page fault anyway.
622 */
623 if (iommu->domain != &rk_identity_domain)
624 report_iommu_fault(iommu->domain, iommu->dev, iova,
625 flags);
626 else
627 dev_err(iommu->dev, "Page fault while iommu not attached to domain?\n");
628
629 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
630 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_PAGE_FAULT_DONE);
631 }
632
633 if (int_status & RK_MMU_IRQ_BUS_ERROR)
634 dev_err(iommu->dev, "BUS_ERROR occurred at %pad\n", &iova);
635
636 if (int_status & ~RK_MMU_IRQ_MASK)
637 dev_err(iommu->dev, "unexpected int_status: %#08x\n",
638 int_status);
639
640 rk_iommu_write(iommu->bases[i], RK_MMU_INT_CLEAR, int_status);
641 }
642
643 clk_bulk_disable(iommu->num_clocks, iommu->clocks);
644
645out:
646 pm_runtime_put(iommu->dev);
647 return ret;
648}
649
650static phys_addr_t rk_iommu_iova_to_phys(struct iommu_domain *domain,
651 dma_addr_t iova)
652{
653 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
654 unsigned long flags;
655 phys_addr_t pt_phys, phys = 0;
656 u32 dte, pte;
657 u32 *page_table;
658
659 spin_lock_irqsave(&rk_domain->dt_lock, flags);
660
661 dte = rk_domain->dt[rk_iova_dte_index(iova)];
662 if (!rk_dte_is_pt_valid(dte))
663 goto out;
664
665 pt_phys = rk_ops->pt_address(dte);
666 page_table = (u32 *)phys_to_virt(pt_phys);
667 pte = page_table[rk_iova_pte_index(iova)];
668 if (!rk_pte_is_page_valid(pte))
669 goto out;
670
671 phys = rk_ops->pt_address(pte) + rk_iova_page_offset(iova);
672out:
673 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
674
675 return phys;
676}
677
678static void rk_iommu_zap_iova(struct rk_iommu_domain *rk_domain,
679 dma_addr_t iova, size_t size)
680{
681 struct list_head *pos;
682 unsigned long flags;
683
684 /* shootdown these iova from all iommus using this domain */
685 spin_lock_irqsave(&rk_domain->iommus_lock, flags);
686 list_for_each(pos, &rk_domain->iommus) {
687 struct rk_iommu *iommu;
688 int ret;
689
690 iommu = list_entry(pos, struct rk_iommu, node);
691
692 /* Only zap TLBs of IOMMUs that are powered on. */
693 ret = pm_runtime_get_if_in_use(iommu->dev);
694 if (WARN_ON_ONCE(ret < 0))
695 continue;
696 if (ret) {
697 WARN_ON(clk_bulk_enable(iommu->num_clocks,
698 iommu->clocks));
699 rk_iommu_zap_lines(iommu, iova, size);
700 clk_bulk_disable(iommu->num_clocks, iommu->clocks);
701 pm_runtime_put(iommu->dev);
702 }
703 }
704 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
705}
706
707static void rk_iommu_zap_iova_first_last(struct rk_iommu_domain *rk_domain,
708 dma_addr_t iova, size_t size)
709{
710 rk_iommu_zap_iova(rk_domain, iova, SPAGE_SIZE);
711 if (size > SPAGE_SIZE)
712 rk_iommu_zap_iova(rk_domain, iova + size - SPAGE_SIZE,
713 SPAGE_SIZE);
714}
715
716static u32 *rk_dte_get_page_table(struct rk_iommu_domain *rk_domain,
717 dma_addr_t iova)
718{
719 u32 *page_table, *dte_addr;
720 u32 dte_index, dte;
721 phys_addr_t pt_phys;
722 dma_addr_t pt_dma;
723
724 assert_spin_locked(&rk_domain->dt_lock);
725
726 dte_index = rk_iova_dte_index(iova);
727 dte_addr = &rk_domain->dt[dte_index];
728 dte = *dte_addr;
729 if (rk_dte_is_pt_valid(dte))
730 goto done;
731
732 page_table = iommu_alloc_page(GFP_ATOMIC | rk_ops->gfp_flags);
733 if (!page_table)
734 return ERR_PTR(-ENOMEM);
735
736 pt_dma = dma_map_single(dma_dev, page_table, SPAGE_SIZE, DMA_TO_DEVICE);
737 if (dma_mapping_error(dma_dev, pt_dma)) {
738 dev_err(dma_dev, "DMA mapping error while allocating page table\n");
739 iommu_free_page(page_table);
740 return ERR_PTR(-ENOMEM);
741 }
742
743 dte = rk_ops->mk_dtentries(pt_dma);
744 *dte_addr = dte;
745
746 rk_table_flush(rk_domain,
747 rk_domain->dt_dma + dte_index * sizeof(u32), 1);
748done:
749 pt_phys = rk_ops->pt_address(dte);
750 return (u32 *)phys_to_virt(pt_phys);
751}
752
753static size_t rk_iommu_unmap_iova(struct rk_iommu_domain *rk_domain,
754 u32 *pte_addr, dma_addr_t pte_dma,
755 size_t size)
756{
757 unsigned int pte_count;
758 unsigned int pte_total = size / SPAGE_SIZE;
759
760 assert_spin_locked(&rk_domain->dt_lock);
761
762 for (pte_count = 0; pte_count < pte_total; pte_count++) {
763 u32 pte = pte_addr[pte_count];
764 if (!rk_pte_is_page_valid(pte))
765 break;
766
767 pte_addr[pte_count] = rk_mk_pte_invalid(pte);
768 }
769
770 rk_table_flush(rk_domain, pte_dma, pte_count);
771
772 return pte_count * SPAGE_SIZE;
773}
774
775static int rk_iommu_map_iova(struct rk_iommu_domain *rk_domain, u32 *pte_addr,
776 dma_addr_t pte_dma, dma_addr_t iova,
777 phys_addr_t paddr, size_t size, int prot)
778{
779 unsigned int pte_count;
780 unsigned int pte_total = size / SPAGE_SIZE;
781 phys_addr_t page_phys;
782
783 assert_spin_locked(&rk_domain->dt_lock);
784
785 for (pte_count = 0; pte_count < pte_total; pte_count++) {
786 u32 pte = pte_addr[pte_count];
787
788 if (rk_pte_is_page_valid(pte))
789 goto unwind;
790
791 pte_addr[pte_count] = rk_ops->mk_ptentries(paddr, prot);
792
793 paddr += SPAGE_SIZE;
794 }
795
796 rk_table_flush(rk_domain, pte_dma, pte_total);
797
798 /*
799 * Zap the first and last iova to evict from iotlb any previously
800 * mapped cachelines holding stale values for its dte and pte.
801 * We only zap the first and last iova, since only they could have
802 * dte or pte shared with an existing mapping.
803 */
804 rk_iommu_zap_iova_first_last(rk_domain, iova, size);
805
806 return 0;
807unwind:
808 /* Unmap the range of iovas that we just mapped */
809 rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma,
810 pte_count * SPAGE_SIZE);
811
812 iova += pte_count * SPAGE_SIZE;
813 page_phys = rk_ops->pt_address(pte_addr[pte_count]);
814 pr_err("iova: %pad already mapped to %pa cannot remap to phys: %pa prot: %#x\n",
815 &iova, &page_phys, &paddr, prot);
816
817 return -EADDRINUSE;
818}
819
820static int rk_iommu_map(struct iommu_domain *domain, unsigned long _iova,
821 phys_addr_t paddr, size_t size, size_t count,
822 int prot, gfp_t gfp, size_t *mapped)
823{
824 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
825 unsigned long flags;
826 dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
827 u32 *page_table, *pte_addr;
828 u32 dte_index, pte_index;
829 int ret;
830
831 spin_lock_irqsave(&rk_domain->dt_lock, flags);
832
833 /*
834 * pgsize_bitmap specifies iova sizes that fit in one page table
835 * (1024 4-KiB pages = 4 MiB).
836 * So, size will always be 4096 <= size <= 4194304.
837 * Since iommu_map() guarantees that both iova and size will be
838 * aligned, we will always only be mapping from a single dte here.
839 */
840 page_table = rk_dte_get_page_table(rk_domain, iova);
841 if (IS_ERR(page_table)) {
842 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
843 return PTR_ERR(page_table);
844 }
845
846 dte_index = rk_domain->dt[rk_iova_dte_index(iova)];
847 pte_index = rk_iova_pte_index(iova);
848 pte_addr = &page_table[pte_index];
849
850 pte_dma = rk_ops->pt_address(dte_index) + pte_index * sizeof(u32);
851 ret = rk_iommu_map_iova(rk_domain, pte_addr, pte_dma, iova,
852 paddr, size, prot);
853
854 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
855 if (!ret)
856 *mapped = size;
857
858 return ret;
859}
860
861static size_t rk_iommu_unmap(struct iommu_domain *domain, unsigned long _iova,
862 size_t size, size_t count, struct iommu_iotlb_gather *gather)
863{
864 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
865 unsigned long flags;
866 dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
867 phys_addr_t pt_phys;
868 u32 dte;
869 u32 *pte_addr;
870 size_t unmap_size;
871
872 spin_lock_irqsave(&rk_domain->dt_lock, flags);
873
874 /*
875 * pgsize_bitmap specifies iova sizes that fit in one page table
876 * (1024 4-KiB pages = 4 MiB).
877 * So, size will always be 4096 <= size <= 4194304.
878 * Since iommu_unmap() guarantees that both iova and size will be
879 * aligned, we will always only be unmapping from a single dte here.
880 */
881 dte = rk_domain->dt[rk_iova_dte_index(iova)];
882 /* Just return 0 if iova is unmapped */
883 if (!rk_dte_is_pt_valid(dte)) {
884 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
885 return 0;
886 }
887
888 pt_phys = rk_ops->pt_address(dte);
889 pte_addr = (u32 *)phys_to_virt(pt_phys) + rk_iova_pte_index(iova);
890 pte_dma = pt_phys + rk_iova_pte_index(iova) * sizeof(u32);
891 unmap_size = rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma, size);
892
893 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
894
895 /* Shootdown iotlb entries for iova range that was just unmapped */
896 rk_iommu_zap_iova(rk_domain, iova, unmap_size);
897
898 return unmap_size;
899}
900
901static struct rk_iommu *rk_iommu_from_dev(struct device *dev)
902{
903 struct rk_iommudata *data = dev_iommu_priv_get(dev);
904
905 return data ? data->iommu : NULL;
906}
907
908/* Must be called with iommu powered on and attached */
909static void rk_iommu_disable(struct rk_iommu *iommu)
910{
911 int i;
912
913 /* Ignore error while disabling, just keep going */
914 WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks));
915 rk_iommu_enable_stall(iommu);
916 rk_iommu_disable_paging(iommu);
917 for (i = 0; i < iommu->num_mmu; i++) {
918 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, 0);
919 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 0);
920 }
921 rk_iommu_disable_stall(iommu);
922 clk_bulk_disable(iommu->num_clocks, iommu->clocks);
923}
924
925/* Must be called with iommu powered on and attached */
926static int rk_iommu_enable(struct rk_iommu *iommu)
927{
928 struct iommu_domain *domain = iommu->domain;
929 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
930 int ret, i;
931
932 ret = clk_bulk_enable(iommu->num_clocks, iommu->clocks);
933 if (ret)
934 return ret;
935
936 ret = rk_iommu_enable_stall(iommu);
937 if (ret)
938 goto out_disable_clocks;
939
940 ret = rk_iommu_force_reset(iommu);
941 if (ret)
942 goto out_disable_stall;
943
944 for (i = 0; i < iommu->num_mmu; i++) {
945 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR,
946 rk_ops->mk_dtentries(rk_domain->dt_dma));
947 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
948 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK);
949 }
950
951 ret = rk_iommu_enable_paging(iommu);
952
953out_disable_stall:
954 rk_iommu_disable_stall(iommu);
955out_disable_clocks:
956 clk_bulk_disable(iommu->num_clocks, iommu->clocks);
957 return ret;
958}
959
960static int rk_iommu_identity_attach(struct iommu_domain *identity_domain,
961 struct device *dev)
962{
963 struct rk_iommu *iommu;
964 struct rk_iommu_domain *rk_domain;
965 unsigned long flags;
966 int ret;
967
968 /* Allow 'virtual devices' (eg drm) to detach from domain */
969 iommu = rk_iommu_from_dev(dev);
970 if (!iommu)
971 return -ENODEV;
972
973 rk_domain = to_rk_domain(iommu->domain);
974
975 dev_dbg(dev, "Detaching from iommu domain\n");
976
977 if (iommu->domain == identity_domain)
978 return 0;
979
980 iommu->domain = identity_domain;
981
982 spin_lock_irqsave(&rk_domain->iommus_lock, flags);
983 list_del_init(&iommu->node);
984 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
985
986 ret = pm_runtime_get_if_in_use(iommu->dev);
987 WARN_ON_ONCE(ret < 0);
988 if (ret > 0) {
989 rk_iommu_disable(iommu);
990 pm_runtime_put(iommu->dev);
991 }
992
993 return 0;
994}
995
996static struct iommu_domain_ops rk_identity_ops = {
997 .attach_dev = rk_iommu_identity_attach,
998};
999
1000static struct iommu_domain rk_identity_domain = {
1001 .type = IOMMU_DOMAIN_IDENTITY,
1002 .ops = &rk_identity_ops,
1003};
1004
1005static int rk_iommu_attach_device(struct iommu_domain *domain,
1006 struct device *dev)
1007{
1008 struct rk_iommu *iommu;
1009 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
1010 unsigned long flags;
1011 int ret;
1012
1013 /*
1014 * Allow 'virtual devices' (e.g., drm) to attach to domain.
1015 * Such a device does not belong to an iommu group.
1016 */
1017 iommu = rk_iommu_from_dev(dev);
1018 if (!iommu)
1019 return 0;
1020
1021 dev_dbg(dev, "Attaching to iommu domain\n");
1022
1023 /* iommu already attached */
1024 if (iommu->domain == domain)
1025 return 0;
1026
1027 ret = rk_iommu_identity_attach(&rk_identity_domain, dev);
1028 if (ret)
1029 return ret;
1030
1031 iommu->domain = domain;
1032
1033 spin_lock_irqsave(&rk_domain->iommus_lock, flags);
1034 list_add_tail(&iommu->node, &rk_domain->iommus);
1035 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
1036
1037 ret = pm_runtime_get_if_in_use(iommu->dev);
1038 if (!ret || WARN_ON_ONCE(ret < 0))
1039 return 0;
1040
1041 ret = rk_iommu_enable(iommu);
1042 if (ret)
1043 WARN_ON(rk_iommu_identity_attach(&rk_identity_domain, dev));
1044
1045 pm_runtime_put(iommu->dev);
1046
1047 return ret;
1048}
1049
1050static struct iommu_domain *rk_iommu_domain_alloc_paging(struct device *dev)
1051{
1052 struct rk_iommu_domain *rk_domain;
1053
1054 if (!dma_dev)
1055 return NULL;
1056
1057 rk_domain = kzalloc(sizeof(*rk_domain), GFP_KERNEL);
1058 if (!rk_domain)
1059 return NULL;
1060
1061 /*
1062 * rk32xx iommus use a 2 level pagetable.
1063 * Each level1 (dt) and level2 (pt) table has 1024 4-byte entries.
1064 * Allocate one 4 KiB page for each table.
1065 */
1066 rk_domain->dt = iommu_alloc_page(GFP_KERNEL | rk_ops->gfp_flags);
1067 if (!rk_domain->dt)
1068 goto err_free_domain;
1069
1070 rk_domain->dt_dma = dma_map_single(dma_dev, rk_domain->dt,
1071 SPAGE_SIZE, DMA_TO_DEVICE);
1072 if (dma_mapping_error(dma_dev, rk_domain->dt_dma)) {
1073 dev_err(dma_dev, "DMA map error for DT\n");
1074 goto err_free_dt;
1075 }
1076
1077 spin_lock_init(&rk_domain->iommus_lock);
1078 spin_lock_init(&rk_domain->dt_lock);
1079 INIT_LIST_HEAD(&rk_domain->iommus);
1080
1081 rk_domain->domain.geometry.aperture_start = 0;
1082 rk_domain->domain.geometry.aperture_end = DMA_BIT_MASK(32);
1083 rk_domain->domain.geometry.force_aperture = true;
1084
1085 return &rk_domain->domain;
1086
1087err_free_dt:
1088 iommu_free_page(rk_domain->dt);
1089err_free_domain:
1090 kfree(rk_domain);
1091
1092 return NULL;
1093}
1094
1095static void rk_iommu_domain_free(struct iommu_domain *domain)
1096{
1097 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
1098 int i;
1099
1100 WARN_ON(!list_empty(&rk_domain->iommus));
1101
1102 for (i = 0; i < NUM_DT_ENTRIES; i++) {
1103 u32 dte = rk_domain->dt[i];
1104 if (rk_dte_is_pt_valid(dte)) {
1105 phys_addr_t pt_phys = rk_ops->pt_address(dte);
1106 u32 *page_table = phys_to_virt(pt_phys);
1107 dma_unmap_single(dma_dev, pt_phys,
1108 SPAGE_SIZE, DMA_TO_DEVICE);
1109 iommu_free_page(page_table);
1110 }
1111 }
1112
1113 dma_unmap_single(dma_dev, rk_domain->dt_dma,
1114 SPAGE_SIZE, DMA_TO_DEVICE);
1115 iommu_free_page(rk_domain->dt);
1116
1117 kfree(rk_domain);
1118}
1119
1120static struct iommu_device *rk_iommu_probe_device(struct device *dev)
1121{
1122 struct rk_iommudata *data;
1123 struct rk_iommu *iommu;
1124
1125 data = dev_iommu_priv_get(dev);
1126 if (!data)
1127 return ERR_PTR(-ENODEV);
1128
1129 iommu = rk_iommu_from_dev(dev);
1130
1131 data->link = device_link_add(dev, iommu->dev,
1132 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
1133
1134 return &iommu->iommu;
1135}
1136
1137static void rk_iommu_release_device(struct device *dev)
1138{
1139 struct rk_iommudata *data = dev_iommu_priv_get(dev);
1140
1141 device_link_del(data->link);
1142}
1143
1144static int rk_iommu_of_xlate(struct device *dev,
1145 const struct of_phandle_args *args)
1146{
1147 struct platform_device *iommu_dev;
1148 struct rk_iommudata *data;
1149
1150 data = devm_kzalloc(dma_dev, sizeof(*data), GFP_KERNEL);
1151 if (!data)
1152 return -ENOMEM;
1153
1154 iommu_dev = of_find_device_by_node(args->np);
1155
1156 data->iommu = platform_get_drvdata(iommu_dev);
1157 data->iommu->domain = &rk_identity_domain;
1158 dev_iommu_priv_set(dev, data);
1159
1160 platform_device_put(iommu_dev);
1161
1162 return 0;
1163}
1164
1165static const struct iommu_ops rk_iommu_ops = {
1166 .identity_domain = &rk_identity_domain,
1167 .domain_alloc_paging = rk_iommu_domain_alloc_paging,
1168 .probe_device = rk_iommu_probe_device,
1169 .release_device = rk_iommu_release_device,
1170 .device_group = generic_single_device_group,
1171 .pgsize_bitmap = RK_IOMMU_PGSIZE_BITMAP,
1172 .of_xlate = rk_iommu_of_xlate,
1173 .default_domain_ops = &(const struct iommu_domain_ops) {
1174 .attach_dev = rk_iommu_attach_device,
1175 .map_pages = rk_iommu_map,
1176 .unmap_pages = rk_iommu_unmap,
1177 .iova_to_phys = rk_iommu_iova_to_phys,
1178 .free = rk_iommu_domain_free,
1179 }
1180};
1181
1182static int rk_iommu_probe(struct platform_device *pdev)
1183{
1184 struct device *dev = &pdev->dev;
1185 struct rk_iommu *iommu;
1186 struct resource *res;
1187 const struct rk_iommu_ops *ops;
1188 int num_res = pdev->num_resources;
1189 int err, i;
1190
1191 iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL);
1192 if (!iommu)
1193 return -ENOMEM;
1194
1195 platform_set_drvdata(pdev, iommu);
1196 iommu->dev = dev;
1197 iommu->num_mmu = 0;
1198
1199 ops = of_device_get_match_data(dev);
1200 if (!rk_ops)
1201 rk_ops = ops;
1202
1203 /*
1204 * That should not happen unless different versions of the
1205 * hardware block are embedded the same SoC
1206 */
1207 if (WARN_ON(rk_ops != ops))
1208 return -EINVAL;
1209
1210 iommu->bases = devm_kcalloc(dev, num_res, sizeof(*iommu->bases),
1211 GFP_KERNEL);
1212 if (!iommu->bases)
1213 return -ENOMEM;
1214
1215 for (i = 0; i < num_res; i++) {
1216 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1217 if (!res)
1218 continue;
1219 iommu->bases[i] = devm_ioremap_resource(&pdev->dev, res);
1220 if (IS_ERR(iommu->bases[i]))
1221 continue;
1222 iommu->num_mmu++;
1223 }
1224 if (iommu->num_mmu == 0)
1225 return PTR_ERR(iommu->bases[0]);
1226
1227 iommu->num_irq = platform_irq_count(pdev);
1228 if (iommu->num_irq < 0)
1229 return iommu->num_irq;
1230
1231 iommu->reset_disabled = device_property_read_bool(dev,
1232 "rockchip,disable-mmu-reset");
1233
1234 iommu->num_clocks = ARRAY_SIZE(rk_iommu_clocks);
1235 iommu->clocks = devm_kcalloc(iommu->dev, iommu->num_clocks,
1236 sizeof(*iommu->clocks), GFP_KERNEL);
1237 if (!iommu->clocks)
1238 return -ENOMEM;
1239
1240 for (i = 0; i < iommu->num_clocks; ++i)
1241 iommu->clocks[i].id = rk_iommu_clocks[i];
1242
1243 /*
1244 * iommu clocks should be present for all new devices and devicetrees
1245 * but there are older devicetrees without clocks out in the wild.
1246 * So clocks as optional for the time being.
1247 */
1248 err = devm_clk_bulk_get(iommu->dev, iommu->num_clocks, iommu->clocks);
1249 if (err == -ENOENT)
1250 iommu->num_clocks = 0;
1251 else if (err)
1252 return err;
1253
1254 err = clk_bulk_prepare(iommu->num_clocks, iommu->clocks);
1255 if (err)
1256 return err;
1257
1258 err = iommu_device_sysfs_add(&iommu->iommu, dev, NULL, dev_name(dev));
1259 if (err)
1260 goto err_unprepare_clocks;
1261
1262 err = iommu_device_register(&iommu->iommu, &rk_iommu_ops, dev);
1263 if (err)
1264 goto err_remove_sysfs;
1265
1266 /*
1267 * Use the first registered IOMMU device for domain to use with DMA
1268 * API, since a domain might not physically correspond to a single
1269 * IOMMU device..
1270 */
1271 if (!dma_dev)
1272 dma_dev = &pdev->dev;
1273
1274 pm_runtime_enable(dev);
1275
1276 for (i = 0; i < iommu->num_irq; i++) {
1277 int irq = platform_get_irq(pdev, i);
1278
1279 if (irq < 0) {
1280 err = irq;
1281 goto err_pm_disable;
1282 }
1283
1284 err = devm_request_irq(iommu->dev, irq, rk_iommu_irq,
1285 IRQF_SHARED, dev_name(dev), iommu);
1286 if (err)
1287 goto err_pm_disable;
1288 }
1289
1290 dma_set_mask_and_coherent(dev, rk_ops->dma_bit_mask);
1291
1292 return 0;
1293err_pm_disable:
1294 pm_runtime_disable(dev);
1295err_remove_sysfs:
1296 iommu_device_sysfs_remove(&iommu->iommu);
1297err_unprepare_clocks:
1298 clk_bulk_unprepare(iommu->num_clocks, iommu->clocks);
1299 return err;
1300}
1301
1302static void rk_iommu_shutdown(struct platform_device *pdev)
1303{
1304 struct rk_iommu *iommu = platform_get_drvdata(pdev);
1305 int i;
1306
1307 for (i = 0; i < iommu->num_irq; i++) {
1308 int irq = platform_get_irq(pdev, i);
1309
1310 devm_free_irq(iommu->dev, irq, iommu);
1311 }
1312
1313 pm_runtime_force_suspend(&pdev->dev);
1314}
1315
1316static int __maybe_unused rk_iommu_suspend(struct device *dev)
1317{
1318 struct rk_iommu *iommu = dev_get_drvdata(dev);
1319
1320 if (iommu->domain == &rk_identity_domain)
1321 return 0;
1322
1323 rk_iommu_disable(iommu);
1324 return 0;
1325}
1326
1327static int __maybe_unused rk_iommu_resume(struct device *dev)
1328{
1329 struct rk_iommu *iommu = dev_get_drvdata(dev);
1330
1331 if (iommu->domain == &rk_identity_domain)
1332 return 0;
1333
1334 return rk_iommu_enable(iommu);
1335}
1336
1337static const struct dev_pm_ops rk_iommu_pm_ops = {
1338 SET_RUNTIME_PM_OPS(rk_iommu_suspend, rk_iommu_resume, NULL)
1339 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1340 pm_runtime_force_resume)
1341};
1342
1343static struct rk_iommu_ops iommu_data_ops_v1 = {
1344 .pt_address = &rk_dte_pt_address,
1345 .mk_dtentries = &rk_mk_dte,
1346 .mk_ptentries = &rk_mk_pte,
1347 .dma_bit_mask = DMA_BIT_MASK(32),
1348 .gfp_flags = GFP_DMA32,
1349};
1350
1351static struct rk_iommu_ops iommu_data_ops_v2 = {
1352 .pt_address = &rk_dte_pt_address_v2,
1353 .mk_dtentries = &rk_mk_dte_v2,
1354 .mk_ptentries = &rk_mk_pte_v2,
1355 .dma_bit_mask = DMA_BIT_MASK(40),
1356 .gfp_flags = 0,
1357};
1358
1359static const struct of_device_id rk_iommu_dt_ids[] = {
1360 { .compatible = "rockchip,iommu",
1361 .data = &iommu_data_ops_v1,
1362 },
1363 { .compatible = "rockchip,rk3568-iommu",
1364 .data = &iommu_data_ops_v2,
1365 },
1366 { /* sentinel */ }
1367};
1368
1369static struct platform_driver rk_iommu_driver = {
1370 .probe = rk_iommu_probe,
1371 .shutdown = rk_iommu_shutdown,
1372 .driver = {
1373 .name = "rk_iommu",
1374 .of_match_table = rk_iommu_dt_ids,
1375 .pm = &rk_iommu_pm_ops,
1376 .suppress_bind_attrs = true,
1377 },
1378};
1379builtin_platform_driver(rk_iommu_driver);
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 */
6
7#include <linux/clk.h>
8#include <linux/compiler.h>
9#include <linux/delay.h>
10#include <linux/device.h>
11#include <linux/dma-iommu.h>
12#include <linux/dma-mapping.h>
13#include <linux/errno.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/iommu.h>
17#include <linux/iopoll.h>
18#include <linux/list.h>
19#include <linux/mm.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_iommu.h>
23#include <linux/of_platform.h>
24#include <linux/platform_device.h>
25#include <linux/pm_runtime.h>
26#include <linux/slab.h>
27#include <linux/spinlock.h>
28
29/** MMU register offsets */
30#define RK_MMU_DTE_ADDR 0x00 /* Directory table address */
31#define RK_MMU_STATUS 0x04
32#define RK_MMU_COMMAND 0x08
33#define RK_MMU_PAGE_FAULT_ADDR 0x0C /* IOVA of last page fault */
34#define RK_MMU_ZAP_ONE_LINE 0x10 /* Shootdown one IOTLB entry */
35#define RK_MMU_INT_RAWSTAT 0x14 /* IRQ status ignoring mask */
36#define RK_MMU_INT_CLEAR 0x18 /* Acknowledge and re-arm irq */
37#define RK_MMU_INT_MASK 0x1C /* IRQ enable */
38#define RK_MMU_INT_STATUS 0x20 /* IRQ status after masking */
39#define RK_MMU_AUTO_GATING 0x24
40
41#define DTE_ADDR_DUMMY 0xCAFEBABE
42
43#define RK_MMU_POLL_PERIOD_US 100
44#define RK_MMU_FORCE_RESET_TIMEOUT_US 100000
45#define RK_MMU_POLL_TIMEOUT_US 1000
46
47/* RK_MMU_STATUS fields */
48#define RK_MMU_STATUS_PAGING_ENABLED BIT(0)
49#define RK_MMU_STATUS_PAGE_FAULT_ACTIVE BIT(1)
50#define RK_MMU_STATUS_STALL_ACTIVE BIT(2)
51#define RK_MMU_STATUS_IDLE BIT(3)
52#define RK_MMU_STATUS_REPLAY_BUFFER_EMPTY BIT(4)
53#define RK_MMU_STATUS_PAGE_FAULT_IS_WRITE BIT(5)
54#define RK_MMU_STATUS_STALL_NOT_ACTIVE BIT(31)
55
56/* RK_MMU_COMMAND command values */
57#define RK_MMU_CMD_ENABLE_PAGING 0 /* Enable memory translation */
58#define RK_MMU_CMD_DISABLE_PAGING 1 /* Disable memory translation */
59#define RK_MMU_CMD_ENABLE_STALL 2 /* Stall paging to allow other cmds */
60#define RK_MMU_CMD_DISABLE_STALL 3 /* Stop stall re-enables paging */
61#define RK_MMU_CMD_ZAP_CACHE 4 /* Shoot down entire IOTLB */
62#define RK_MMU_CMD_PAGE_FAULT_DONE 5 /* Clear page fault */
63#define RK_MMU_CMD_FORCE_RESET 6 /* Reset all registers */
64
65/* RK_MMU_INT_* register fields */
66#define RK_MMU_IRQ_PAGE_FAULT 0x01 /* page fault */
67#define RK_MMU_IRQ_BUS_ERROR 0x02 /* bus read error */
68#define RK_MMU_IRQ_MASK (RK_MMU_IRQ_PAGE_FAULT | RK_MMU_IRQ_BUS_ERROR)
69
70#define NUM_DT_ENTRIES 1024
71#define NUM_PT_ENTRIES 1024
72
73#define SPAGE_ORDER 12
74#define SPAGE_SIZE (1 << SPAGE_ORDER)
75
76 /*
77 * Support mapping any size that fits in one page table:
78 * 4 KiB to 4 MiB
79 */
80#define RK_IOMMU_PGSIZE_BITMAP 0x007ff000
81
82struct rk_iommu_domain {
83 struct list_head iommus;
84 u32 *dt; /* page directory table */
85 dma_addr_t dt_dma;
86 spinlock_t iommus_lock; /* lock for iommus list */
87 spinlock_t dt_lock; /* lock for modifying page directory table */
88
89 struct iommu_domain domain;
90};
91
92/* list of clocks required by IOMMU */
93static const char * const rk_iommu_clocks[] = {
94 "aclk", "iface",
95};
96
97struct rk_iommu {
98 struct device *dev;
99 void __iomem **bases;
100 int num_mmu;
101 struct clk_bulk_data *clocks;
102 int num_clocks;
103 bool reset_disabled;
104 struct iommu_device iommu;
105 struct list_head node; /* entry in rk_iommu_domain.iommus */
106 struct iommu_domain *domain; /* domain to which iommu is attached */
107 struct iommu_group *group;
108};
109
110struct rk_iommudata {
111 struct device_link *link; /* runtime PM link from IOMMU to master */
112 struct rk_iommu *iommu;
113};
114
115static struct device *dma_dev;
116
117static inline void rk_table_flush(struct rk_iommu_domain *dom, dma_addr_t dma,
118 unsigned int count)
119{
120 size_t size = count * sizeof(u32); /* count of u32 entry */
121
122 dma_sync_single_for_device(dma_dev, dma, size, DMA_TO_DEVICE);
123}
124
125static struct rk_iommu_domain *to_rk_domain(struct iommu_domain *dom)
126{
127 return container_of(dom, struct rk_iommu_domain, domain);
128}
129
130/*
131 * The Rockchip rk3288 iommu uses a 2-level page table.
132 * The first level is the "Directory Table" (DT).
133 * The DT consists of 1024 4-byte Directory Table Entries (DTEs), each pointing
134 * to a "Page Table".
135 * The second level is the 1024 Page Tables (PT).
136 * Each PT consists of 1024 4-byte Page Table Entries (PTEs), each pointing to
137 * a 4 KB page of physical memory.
138 *
139 * The DT and each PT fits in a single 4 KB page (4-bytes * 1024 entries).
140 * Each iommu device has a MMU_DTE_ADDR register that contains the physical
141 * address of the start of the DT page.
142 *
143 * The structure of the page table is as follows:
144 *
145 * DT
146 * MMU_DTE_ADDR -> +-----+
147 * | |
148 * +-----+ PT
149 * | DTE | -> +-----+
150 * +-----+ | | Memory
151 * | | +-----+ Page
152 * | | | PTE | -> +-----+
153 * +-----+ +-----+ | |
154 * | | | |
155 * | | | |
156 * +-----+ | |
157 * | |
158 * | |
159 * +-----+
160 */
161
162/*
163 * Each DTE has a PT address and a valid bit:
164 * +---------------------+-----------+-+
165 * | PT address | Reserved |V|
166 * +---------------------+-----------+-+
167 * 31:12 - PT address (PTs always starts on a 4 KB boundary)
168 * 11: 1 - Reserved
169 * 0 - 1 if PT @ PT address is valid
170 */
171#define RK_DTE_PT_ADDRESS_MASK 0xfffff000
172#define RK_DTE_PT_VALID BIT(0)
173
174static inline phys_addr_t rk_dte_pt_address(u32 dte)
175{
176 return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK;
177}
178
179static inline bool rk_dte_is_pt_valid(u32 dte)
180{
181 return dte & RK_DTE_PT_VALID;
182}
183
184static inline u32 rk_mk_dte(dma_addr_t pt_dma)
185{
186 return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID;
187}
188
189/*
190 * Each PTE has a Page address, some flags and a valid bit:
191 * +---------------------+---+-------+-+
192 * | Page address |Rsv| Flags |V|
193 * +---------------------+---+-------+-+
194 * 31:12 - Page address (Pages always start on a 4 KB boundary)
195 * 11: 9 - Reserved
196 * 8: 1 - Flags
197 * 8 - Read allocate - allocate cache space on read misses
198 * 7 - Read cache - enable cache & prefetch of data
199 * 6 - Write buffer - enable delaying writes on their way to memory
200 * 5 - Write allocate - allocate cache space on write misses
201 * 4 - Write cache - different writes can be merged together
202 * 3 - Override cache attributes
203 * if 1, bits 4-8 control cache attributes
204 * if 0, the system bus defaults are used
205 * 2 - Writable
206 * 1 - Readable
207 * 0 - 1 if Page @ Page address is valid
208 */
209#define RK_PTE_PAGE_ADDRESS_MASK 0xfffff000
210#define RK_PTE_PAGE_FLAGS_MASK 0x000001fe
211#define RK_PTE_PAGE_WRITABLE BIT(2)
212#define RK_PTE_PAGE_READABLE BIT(1)
213#define RK_PTE_PAGE_VALID BIT(0)
214
215static inline phys_addr_t rk_pte_page_address(u32 pte)
216{
217 return (phys_addr_t)pte & RK_PTE_PAGE_ADDRESS_MASK;
218}
219
220static inline bool rk_pte_is_page_valid(u32 pte)
221{
222 return pte & RK_PTE_PAGE_VALID;
223}
224
225/* TODO: set cache flags per prot IOMMU_CACHE */
226static u32 rk_mk_pte(phys_addr_t page, int prot)
227{
228 u32 flags = 0;
229 flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0;
230 flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0;
231 page &= RK_PTE_PAGE_ADDRESS_MASK;
232 return page | flags | RK_PTE_PAGE_VALID;
233}
234
235static u32 rk_mk_pte_invalid(u32 pte)
236{
237 return pte & ~RK_PTE_PAGE_VALID;
238}
239
240/*
241 * rk3288 iova (IOMMU Virtual Address) format
242 * 31 22.21 12.11 0
243 * +-----------+-----------+-------------+
244 * | DTE index | PTE index | Page offset |
245 * +-----------+-----------+-------------+
246 * 31:22 - DTE index - index of DTE in DT
247 * 21:12 - PTE index - index of PTE in PT @ DTE.pt_address
248 * 11: 0 - Page offset - offset into page @ PTE.page_address
249 */
250#define RK_IOVA_DTE_MASK 0xffc00000
251#define RK_IOVA_DTE_SHIFT 22
252#define RK_IOVA_PTE_MASK 0x003ff000
253#define RK_IOVA_PTE_SHIFT 12
254#define RK_IOVA_PAGE_MASK 0x00000fff
255#define RK_IOVA_PAGE_SHIFT 0
256
257static u32 rk_iova_dte_index(dma_addr_t iova)
258{
259 return (u32)(iova & RK_IOVA_DTE_MASK) >> RK_IOVA_DTE_SHIFT;
260}
261
262static u32 rk_iova_pte_index(dma_addr_t iova)
263{
264 return (u32)(iova & RK_IOVA_PTE_MASK) >> RK_IOVA_PTE_SHIFT;
265}
266
267static u32 rk_iova_page_offset(dma_addr_t iova)
268{
269 return (u32)(iova & RK_IOVA_PAGE_MASK) >> RK_IOVA_PAGE_SHIFT;
270}
271
272static u32 rk_iommu_read(void __iomem *base, u32 offset)
273{
274 return readl(base + offset);
275}
276
277static void rk_iommu_write(void __iomem *base, u32 offset, u32 value)
278{
279 writel(value, base + offset);
280}
281
282static void rk_iommu_command(struct rk_iommu *iommu, u32 command)
283{
284 int i;
285
286 for (i = 0; i < iommu->num_mmu; i++)
287 writel(command, iommu->bases[i] + RK_MMU_COMMAND);
288}
289
290static void rk_iommu_base_command(void __iomem *base, u32 command)
291{
292 writel(command, base + RK_MMU_COMMAND);
293}
294static void rk_iommu_zap_lines(struct rk_iommu *iommu, dma_addr_t iova_start,
295 size_t size)
296{
297 int i;
298 dma_addr_t iova_end = iova_start + size;
299 /*
300 * TODO(djkurtz): Figure out when it is more efficient to shootdown the
301 * entire iotlb rather than iterate over individual iovas.
302 */
303 for (i = 0; i < iommu->num_mmu; i++) {
304 dma_addr_t iova;
305
306 for (iova = iova_start; iova < iova_end; iova += SPAGE_SIZE)
307 rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova);
308 }
309}
310
311static bool rk_iommu_is_stall_active(struct rk_iommu *iommu)
312{
313 bool active = true;
314 int i;
315
316 for (i = 0; i < iommu->num_mmu; i++)
317 active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) &
318 RK_MMU_STATUS_STALL_ACTIVE);
319
320 return active;
321}
322
323static bool rk_iommu_is_paging_enabled(struct rk_iommu *iommu)
324{
325 bool enable = true;
326 int i;
327
328 for (i = 0; i < iommu->num_mmu; i++)
329 enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) &
330 RK_MMU_STATUS_PAGING_ENABLED);
331
332 return enable;
333}
334
335static bool rk_iommu_is_reset_done(struct rk_iommu *iommu)
336{
337 bool done = true;
338 int i;
339
340 for (i = 0; i < iommu->num_mmu; i++)
341 done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0;
342
343 return done;
344}
345
346static int rk_iommu_enable_stall(struct rk_iommu *iommu)
347{
348 int ret, i;
349 bool val;
350
351 if (rk_iommu_is_stall_active(iommu))
352 return 0;
353
354 /* Stall can only be enabled if paging is enabled */
355 if (!rk_iommu_is_paging_enabled(iommu))
356 return 0;
357
358 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_STALL);
359
360 ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val,
361 val, RK_MMU_POLL_PERIOD_US,
362 RK_MMU_POLL_TIMEOUT_US);
363 if (ret)
364 for (i = 0; i < iommu->num_mmu; i++)
365 dev_err(iommu->dev, "Enable stall request timed out, status: %#08x\n",
366 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
367
368 return ret;
369}
370
371static int rk_iommu_disable_stall(struct rk_iommu *iommu)
372{
373 int ret, i;
374 bool val;
375
376 if (!rk_iommu_is_stall_active(iommu))
377 return 0;
378
379 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_STALL);
380
381 ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val,
382 !val, RK_MMU_POLL_PERIOD_US,
383 RK_MMU_POLL_TIMEOUT_US);
384 if (ret)
385 for (i = 0; i < iommu->num_mmu; i++)
386 dev_err(iommu->dev, "Disable stall request timed out, status: %#08x\n",
387 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
388
389 return ret;
390}
391
392static int rk_iommu_enable_paging(struct rk_iommu *iommu)
393{
394 int ret, i;
395 bool val;
396
397 if (rk_iommu_is_paging_enabled(iommu))
398 return 0;
399
400 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_PAGING);
401
402 ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val,
403 val, RK_MMU_POLL_PERIOD_US,
404 RK_MMU_POLL_TIMEOUT_US);
405 if (ret)
406 for (i = 0; i < iommu->num_mmu; i++)
407 dev_err(iommu->dev, "Enable paging request timed out, status: %#08x\n",
408 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
409
410 return ret;
411}
412
413static int rk_iommu_disable_paging(struct rk_iommu *iommu)
414{
415 int ret, i;
416 bool val;
417
418 if (!rk_iommu_is_paging_enabled(iommu))
419 return 0;
420
421 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_PAGING);
422
423 ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val,
424 !val, RK_MMU_POLL_PERIOD_US,
425 RK_MMU_POLL_TIMEOUT_US);
426 if (ret)
427 for (i = 0; i < iommu->num_mmu; i++)
428 dev_err(iommu->dev, "Disable paging request timed out, status: %#08x\n",
429 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
430
431 return ret;
432}
433
434static int rk_iommu_force_reset(struct rk_iommu *iommu)
435{
436 int ret, i;
437 u32 dte_addr;
438 bool val;
439
440 if (iommu->reset_disabled)
441 return 0;
442
443 /*
444 * Check if register DTE_ADDR is working by writing DTE_ADDR_DUMMY
445 * and verifying that upper 5 nybbles are read back.
446 */
447 for (i = 0; i < iommu->num_mmu; i++) {
448 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, DTE_ADDR_DUMMY);
449
450 dte_addr = rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR);
451 if (dte_addr != (DTE_ADDR_DUMMY & RK_DTE_PT_ADDRESS_MASK)) {
452 dev_err(iommu->dev, "Error during raw reset. MMU_DTE_ADDR is not functioning\n");
453 return -EFAULT;
454 }
455 }
456
457 rk_iommu_command(iommu, RK_MMU_CMD_FORCE_RESET);
458
459 ret = readx_poll_timeout(rk_iommu_is_reset_done, iommu, val,
460 val, RK_MMU_FORCE_RESET_TIMEOUT_US,
461 RK_MMU_POLL_TIMEOUT_US);
462 if (ret) {
463 dev_err(iommu->dev, "FORCE_RESET command timed out\n");
464 return ret;
465 }
466
467 return 0;
468}
469
470static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova)
471{
472 void __iomem *base = iommu->bases[index];
473 u32 dte_index, pte_index, page_offset;
474 u32 mmu_dte_addr;
475 phys_addr_t mmu_dte_addr_phys, dte_addr_phys;
476 u32 *dte_addr;
477 u32 dte;
478 phys_addr_t pte_addr_phys = 0;
479 u32 *pte_addr = NULL;
480 u32 pte = 0;
481 phys_addr_t page_addr_phys = 0;
482 u32 page_flags = 0;
483
484 dte_index = rk_iova_dte_index(iova);
485 pte_index = rk_iova_pte_index(iova);
486 page_offset = rk_iova_page_offset(iova);
487
488 mmu_dte_addr = rk_iommu_read(base, RK_MMU_DTE_ADDR);
489 mmu_dte_addr_phys = (phys_addr_t)mmu_dte_addr;
490
491 dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index);
492 dte_addr = phys_to_virt(dte_addr_phys);
493 dte = *dte_addr;
494
495 if (!rk_dte_is_pt_valid(dte))
496 goto print_it;
497
498 pte_addr_phys = rk_dte_pt_address(dte) + (pte_index * 4);
499 pte_addr = phys_to_virt(pte_addr_phys);
500 pte = *pte_addr;
501
502 if (!rk_pte_is_page_valid(pte))
503 goto print_it;
504
505 page_addr_phys = rk_pte_page_address(pte) + page_offset;
506 page_flags = pte & RK_PTE_PAGE_FLAGS_MASK;
507
508print_it:
509 dev_err(iommu->dev, "iova = %pad: dte_index: %#03x pte_index: %#03x page_offset: %#03x\n",
510 &iova, dte_index, pte_index, page_offset);
511 dev_err(iommu->dev, "mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa flags: %#03x\n",
512 &mmu_dte_addr_phys, &dte_addr_phys, dte,
513 rk_dte_is_pt_valid(dte), &pte_addr_phys, pte,
514 rk_pte_is_page_valid(pte), &page_addr_phys, page_flags);
515}
516
517static irqreturn_t rk_iommu_irq(int irq, void *dev_id)
518{
519 struct rk_iommu *iommu = dev_id;
520 u32 status;
521 u32 int_status;
522 dma_addr_t iova;
523 irqreturn_t ret = IRQ_NONE;
524 int i;
525
526 if (WARN_ON(!pm_runtime_get_if_in_use(iommu->dev)))
527 return 0;
528
529 if (WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks)))
530 goto out;
531
532 for (i = 0; i < iommu->num_mmu; i++) {
533 int_status = rk_iommu_read(iommu->bases[i], RK_MMU_INT_STATUS);
534 if (int_status == 0)
535 continue;
536
537 ret = IRQ_HANDLED;
538 iova = rk_iommu_read(iommu->bases[i], RK_MMU_PAGE_FAULT_ADDR);
539
540 if (int_status & RK_MMU_IRQ_PAGE_FAULT) {
541 int flags;
542
543 status = rk_iommu_read(iommu->bases[i], RK_MMU_STATUS);
544 flags = (status & RK_MMU_STATUS_PAGE_FAULT_IS_WRITE) ?
545 IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
546
547 dev_err(iommu->dev, "Page fault at %pad of type %s\n",
548 &iova,
549 (flags == IOMMU_FAULT_WRITE) ? "write" : "read");
550
551 log_iova(iommu, i, iova);
552
553 /*
554 * Report page fault to any installed handlers.
555 * Ignore the return code, though, since we always zap cache
556 * and clear the page fault anyway.
557 */
558 if (iommu->domain)
559 report_iommu_fault(iommu->domain, iommu->dev, iova,
560 flags);
561 else
562 dev_err(iommu->dev, "Page fault while iommu not attached to domain?\n");
563
564 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
565 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_PAGE_FAULT_DONE);
566 }
567
568 if (int_status & RK_MMU_IRQ_BUS_ERROR)
569 dev_err(iommu->dev, "BUS_ERROR occurred at %pad\n", &iova);
570
571 if (int_status & ~RK_MMU_IRQ_MASK)
572 dev_err(iommu->dev, "unexpected int_status: %#08x\n",
573 int_status);
574
575 rk_iommu_write(iommu->bases[i], RK_MMU_INT_CLEAR, int_status);
576 }
577
578 clk_bulk_disable(iommu->num_clocks, iommu->clocks);
579
580out:
581 pm_runtime_put(iommu->dev);
582 return ret;
583}
584
585static phys_addr_t rk_iommu_iova_to_phys(struct iommu_domain *domain,
586 dma_addr_t iova)
587{
588 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
589 unsigned long flags;
590 phys_addr_t pt_phys, phys = 0;
591 u32 dte, pte;
592 u32 *page_table;
593
594 spin_lock_irqsave(&rk_domain->dt_lock, flags);
595
596 dte = rk_domain->dt[rk_iova_dte_index(iova)];
597 if (!rk_dte_is_pt_valid(dte))
598 goto out;
599
600 pt_phys = rk_dte_pt_address(dte);
601 page_table = (u32 *)phys_to_virt(pt_phys);
602 pte = page_table[rk_iova_pte_index(iova)];
603 if (!rk_pte_is_page_valid(pte))
604 goto out;
605
606 phys = rk_pte_page_address(pte) + rk_iova_page_offset(iova);
607out:
608 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
609
610 return phys;
611}
612
613static void rk_iommu_zap_iova(struct rk_iommu_domain *rk_domain,
614 dma_addr_t iova, size_t size)
615{
616 struct list_head *pos;
617 unsigned long flags;
618
619 /* shootdown these iova from all iommus using this domain */
620 spin_lock_irqsave(&rk_domain->iommus_lock, flags);
621 list_for_each(pos, &rk_domain->iommus) {
622 struct rk_iommu *iommu;
623
624 iommu = list_entry(pos, struct rk_iommu, node);
625
626 /* Only zap TLBs of IOMMUs that are powered on. */
627 if (pm_runtime_get_if_in_use(iommu->dev)) {
628 WARN_ON(clk_bulk_enable(iommu->num_clocks,
629 iommu->clocks));
630 rk_iommu_zap_lines(iommu, iova, size);
631 clk_bulk_disable(iommu->num_clocks, iommu->clocks);
632 pm_runtime_put(iommu->dev);
633 }
634 }
635 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
636}
637
638static void rk_iommu_zap_iova_first_last(struct rk_iommu_domain *rk_domain,
639 dma_addr_t iova, size_t size)
640{
641 rk_iommu_zap_iova(rk_domain, iova, SPAGE_SIZE);
642 if (size > SPAGE_SIZE)
643 rk_iommu_zap_iova(rk_domain, iova + size - SPAGE_SIZE,
644 SPAGE_SIZE);
645}
646
647static u32 *rk_dte_get_page_table(struct rk_iommu_domain *rk_domain,
648 dma_addr_t iova)
649{
650 u32 *page_table, *dte_addr;
651 u32 dte_index, dte;
652 phys_addr_t pt_phys;
653 dma_addr_t pt_dma;
654
655 assert_spin_locked(&rk_domain->dt_lock);
656
657 dte_index = rk_iova_dte_index(iova);
658 dte_addr = &rk_domain->dt[dte_index];
659 dte = *dte_addr;
660 if (rk_dte_is_pt_valid(dte))
661 goto done;
662
663 page_table = (u32 *)get_zeroed_page(GFP_ATOMIC | GFP_DMA32);
664 if (!page_table)
665 return ERR_PTR(-ENOMEM);
666
667 pt_dma = dma_map_single(dma_dev, page_table, SPAGE_SIZE, DMA_TO_DEVICE);
668 if (dma_mapping_error(dma_dev, pt_dma)) {
669 dev_err(dma_dev, "DMA mapping error while allocating page table\n");
670 free_page((unsigned long)page_table);
671 return ERR_PTR(-ENOMEM);
672 }
673
674 dte = rk_mk_dte(pt_dma);
675 *dte_addr = dte;
676
677 rk_table_flush(rk_domain, pt_dma, NUM_PT_ENTRIES);
678 rk_table_flush(rk_domain,
679 rk_domain->dt_dma + dte_index * sizeof(u32), 1);
680done:
681 pt_phys = rk_dte_pt_address(dte);
682 return (u32 *)phys_to_virt(pt_phys);
683}
684
685static size_t rk_iommu_unmap_iova(struct rk_iommu_domain *rk_domain,
686 u32 *pte_addr, dma_addr_t pte_dma,
687 size_t size)
688{
689 unsigned int pte_count;
690 unsigned int pte_total = size / SPAGE_SIZE;
691
692 assert_spin_locked(&rk_domain->dt_lock);
693
694 for (pte_count = 0; pte_count < pte_total; pte_count++) {
695 u32 pte = pte_addr[pte_count];
696 if (!rk_pte_is_page_valid(pte))
697 break;
698
699 pte_addr[pte_count] = rk_mk_pte_invalid(pte);
700 }
701
702 rk_table_flush(rk_domain, pte_dma, pte_count);
703
704 return pte_count * SPAGE_SIZE;
705}
706
707static int rk_iommu_map_iova(struct rk_iommu_domain *rk_domain, u32 *pte_addr,
708 dma_addr_t pte_dma, dma_addr_t iova,
709 phys_addr_t paddr, size_t size, int prot)
710{
711 unsigned int pte_count;
712 unsigned int pte_total = size / SPAGE_SIZE;
713 phys_addr_t page_phys;
714
715 assert_spin_locked(&rk_domain->dt_lock);
716
717 for (pte_count = 0; pte_count < pte_total; pte_count++) {
718 u32 pte = pte_addr[pte_count];
719
720 if (rk_pte_is_page_valid(pte))
721 goto unwind;
722
723 pte_addr[pte_count] = rk_mk_pte(paddr, prot);
724
725 paddr += SPAGE_SIZE;
726 }
727
728 rk_table_flush(rk_domain, pte_dma, pte_total);
729
730 /*
731 * Zap the first and last iova to evict from iotlb any previously
732 * mapped cachelines holding stale values for its dte and pte.
733 * We only zap the first and last iova, since only they could have
734 * dte or pte shared with an existing mapping.
735 */
736 rk_iommu_zap_iova_first_last(rk_domain, iova, size);
737
738 return 0;
739unwind:
740 /* Unmap the range of iovas that we just mapped */
741 rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma,
742 pte_count * SPAGE_SIZE);
743
744 iova += pte_count * SPAGE_SIZE;
745 page_phys = rk_pte_page_address(pte_addr[pte_count]);
746 pr_err("iova: %pad already mapped to %pa cannot remap to phys: %pa prot: %#x\n",
747 &iova, &page_phys, &paddr, prot);
748
749 return -EADDRINUSE;
750}
751
752static int rk_iommu_map(struct iommu_domain *domain, unsigned long _iova,
753 phys_addr_t paddr, size_t size, int prot)
754{
755 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
756 unsigned long flags;
757 dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
758 u32 *page_table, *pte_addr;
759 u32 dte_index, pte_index;
760 int ret;
761
762 spin_lock_irqsave(&rk_domain->dt_lock, flags);
763
764 /*
765 * pgsize_bitmap specifies iova sizes that fit in one page table
766 * (1024 4-KiB pages = 4 MiB).
767 * So, size will always be 4096 <= size <= 4194304.
768 * Since iommu_map() guarantees that both iova and size will be
769 * aligned, we will always only be mapping from a single dte here.
770 */
771 page_table = rk_dte_get_page_table(rk_domain, iova);
772 if (IS_ERR(page_table)) {
773 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
774 return PTR_ERR(page_table);
775 }
776
777 dte_index = rk_domain->dt[rk_iova_dte_index(iova)];
778 pte_index = rk_iova_pte_index(iova);
779 pte_addr = &page_table[pte_index];
780 pte_dma = rk_dte_pt_address(dte_index) + pte_index * sizeof(u32);
781 ret = rk_iommu_map_iova(rk_domain, pte_addr, pte_dma, iova,
782 paddr, size, prot);
783
784 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
785
786 return ret;
787}
788
789static size_t rk_iommu_unmap(struct iommu_domain *domain, unsigned long _iova,
790 size_t size)
791{
792 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
793 unsigned long flags;
794 dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
795 phys_addr_t pt_phys;
796 u32 dte;
797 u32 *pte_addr;
798 size_t unmap_size;
799
800 spin_lock_irqsave(&rk_domain->dt_lock, flags);
801
802 /*
803 * pgsize_bitmap specifies iova sizes that fit in one page table
804 * (1024 4-KiB pages = 4 MiB).
805 * So, size will always be 4096 <= size <= 4194304.
806 * Since iommu_unmap() guarantees that both iova and size will be
807 * aligned, we will always only be unmapping from a single dte here.
808 */
809 dte = rk_domain->dt[rk_iova_dte_index(iova)];
810 /* Just return 0 if iova is unmapped */
811 if (!rk_dte_is_pt_valid(dte)) {
812 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
813 return 0;
814 }
815
816 pt_phys = rk_dte_pt_address(dte);
817 pte_addr = (u32 *)phys_to_virt(pt_phys) + rk_iova_pte_index(iova);
818 pte_dma = pt_phys + rk_iova_pte_index(iova) * sizeof(u32);
819 unmap_size = rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma, size);
820
821 spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
822
823 /* Shootdown iotlb entries for iova range that was just unmapped */
824 rk_iommu_zap_iova(rk_domain, iova, unmap_size);
825
826 return unmap_size;
827}
828
829static struct rk_iommu *rk_iommu_from_dev(struct device *dev)
830{
831 struct rk_iommudata *data = dev->archdata.iommu;
832
833 return data ? data->iommu : NULL;
834}
835
836/* Must be called with iommu powered on and attached */
837static void rk_iommu_disable(struct rk_iommu *iommu)
838{
839 int i;
840
841 /* Ignore error while disabling, just keep going */
842 WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks));
843 rk_iommu_enable_stall(iommu);
844 rk_iommu_disable_paging(iommu);
845 for (i = 0; i < iommu->num_mmu; i++) {
846 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, 0);
847 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 0);
848 }
849 rk_iommu_disable_stall(iommu);
850 clk_bulk_disable(iommu->num_clocks, iommu->clocks);
851}
852
853/* Must be called with iommu powered on and attached */
854static int rk_iommu_enable(struct rk_iommu *iommu)
855{
856 struct iommu_domain *domain = iommu->domain;
857 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
858 int ret, i;
859
860 ret = clk_bulk_enable(iommu->num_clocks, iommu->clocks);
861 if (ret)
862 return ret;
863
864 ret = rk_iommu_enable_stall(iommu);
865 if (ret)
866 goto out_disable_clocks;
867
868 ret = rk_iommu_force_reset(iommu);
869 if (ret)
870 goto out_disable_stall;
871
872 for (i = 0; i < iommu->num_mmu; i++) {
873 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR,
874 rk_domain->dt_dma);
875 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
876 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK);
877 }
878
879 ret = rk_iommu_enable_paging(iommu);
880
881out_disable_stall:
882 rk_iommu_disable_stall(iommu);
883out_disable_clocks:
884 clk_bulk_disable(iommu->num_clocks, iommu->clocks);
885 return ret;
886}
887
888static void rk_iommu_detach_device(struct iommu_domain *domain,
889 struct device *dev)
890{
891 struct rk_iommu *iommu;
892 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
893 unsigned long flags;
894
895 /* Allow 'virtual devices' (eg drm) to detach from domain */
896 iommu = rk_iommu_from_dev(dev);
897 if (!iommu)
898 return;
899
900 dev_dbg(dev, "Detaching from iommu domain\n");
901
902 /* iommu already detached */
903 if (iommu->domain != domain)
904 return;
905
906 iommu->domain = NULL;
907
908 spin_lock_irqsave(&rk_domain->iommus_lock, flags);
909 list_del_init(&iommu->node);
910 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
911
912 if (pm_runtime_get_if_in_use(iommu->dev)) {
913 rk_iommu_disable(iommu);
914 pm_runtime_put(iommu->dev);
915 }
916}
917
918static int rk_iommu_attach_device(struct iommu_domain *domain,
919 struct device *dev)
920{
921 struct rk_iommu *iommu;
922 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
923 unsigned long flags;
924 int ret;
925
926 /*
927 * Allow 'virtual devices' (e.g., drm) to attach to domain.
928 * Such a device does not belong to an iommu group.
929 */
930 iommu = rk_iommu_from_dev(dev);
931 if (!iommu)
932 return 0;
933
934 dev_dbg(dev, "Attaching to iommu domain\n");
935
936 /* iommu already attached */
937 if (iommu->domain == domain)
938 return 0;
939
940 if (iommu->domain)
941 rk_iommu_detach_device(iommu->domain, dev);
942
943 iommu->domain = domain;
944
945 spin_lock_irqsave(&rk_domain->iommus_lock, flags);
946 list_add_tail(&iommu->node, &rk_domain->iommus);
947 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
948
949 if (!pm_runtime_get_if_in_use(iommu->dev))
950 return 0;
951
952 ret = rk_iommu_enable(iommu);
953 if (ret)
954 rk_iommu_detach_device(iommu->domain, dev);
955
956 pm_runtime_put(iommu->dev);
957
958 return ret;
959}
960
961static struct iommu_domain *rk_iommu_domain_alloc(unsigned type)
962{
963 struct rk_iommu_domain *rk_domain;
964
965 if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
966 return NULL;
967
968 if (!dma_dev)
969 return NULL;
970
971 rk_domain = devm_kzalloc(dma_dev, sizeof(*rk_domain), GFP_KERNEL);
972 if (!rk_domain)
973 return NULL;
974
975 if (type == IOMMU_DOMAIN_DMA &&
976 iommu_get_dma_cookie(&rk_domain->domain))
977 return NULL;
978
979 /*
980 * rk32xx iommus use a 2 level pagetable.
981 * Each level1 (dt) and level2 (pt) table has 1024 4-byte entries.
982 * Allocate one 4 KiB page for each table.
983 */
984 rk_domain->dt = (u32 *)get_zeroed_page(GFP_KERNEL | GFP_DMA32);
985 if (!rk_domain->dt)
986 goto err_put_cookie;
987
988 rk_domain->dt_dma = dma_map_single(dma_dev, rk_domain->dt,
989 SPAGE_SIZE, DMA_TO_DEVICE);
990 if (dma_mapping_error(dma_dev, rk_domain->dt_dma)) {
991 dev_err(dma_dev, "DMA map error for DT\n");
992 goto err_free_dt;
993 }
994
995 rk_table_flush(rk_domain, rk_domain->dt_dma, NUM_DT_ENTRIES);
996
997 spin_lock_init(&rk_domain->iommus_lock);
998 spin_lock_init(&rk_domain->dt_lock);
999 INIT_LIST_HEAD(&rk_domain->iommus);
1000
1001 rk_domain->domain.geometry.aperture_start = 0;
1002 rk_domain->domain.geometry.aperture_end = DMA_BIT_MASK(32);
1003 rk_domain->domain.geometry.force_aperture = true;
1004
1005 return &rk_domain->domain;
1006
1007err_free_dt:
1008 free_page((unsigned long)rk_domain->dt);
1009err_put_cookie:
1010 if (type == IOMMU_DOMAIN_DMA)
1011 iommu_put_dma_cookie(&rk_domain->domain);
1012
1013 return NULL;
1014}
1015
1016static void rk_iommu_domain_free(struct iommu_domain *domain)
1017{
1018 struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
1019 int i;
1020
1021 WARN_ON(!list_empty(&rk_domain->iommus));
1022
1023 for (i = 0; i < NUM_DT_ENTRIES; i++) {
1024 u32 dte = rk_domain->dt[i];
1025 if (rk_dte_is_pt_valid(dte)) {
1026 phys_addr_t pt_phys = rk_dte_pt_address(dte);
1027 u32 *page_table = phys_to_virt(pt_phys);
1028 dma_unmap_single(dma_dev, pt_phys,
1029 SPAGE_SIZE, DMA_TO_DEVICE);
1030 free_page((unsigned long)page_table);
1031 }
1032 }
1033
1034 dma_unmap_single(dma_dev, rk_domain->dt_dma,
1035 SPAGE_SIZE, DMA_TO_DEVICE);
1036 free_page((unsigned long)rk_domain->dt);
1037
1038 if (domain->type == IOMMU_DOMAIN_DMA)
1039 iommu_put_dma_cookie(&rk_domain->domain);
1040}
1041
1042static int rk_iommu_add_device(struct device *dev)
1043{
1044 struct iommu_group *group;
1045 struct rk_iommu *iommu;
1046 struct rk_iommudata *data;
1047
1048 data = dev->archdata.iommu;
1049 if (!data)
1050 return -ENODEV;
1051
1052 iommu = rk_iommu_from_dev(dev);
1053
1054 group = iommu_group_get_for_dev(dev);
1055 if (IS_ERR(group))
1056 return PTR_ERR(group);
1057 iommu_group_put(group);
1058
1059 iommu_device_link(&iommu->iommu, dev);
1060 data->link = device_link_add(dev, iommu->dev, DL_FLAG_PM_RUNTIME);
1061
1062 return 0;
1063}
1064
1065static void rk_iommu_remove_device(struct device *dev)
1066{
1067 struct rk_iommu *iommu;
1068 struct rk_iommudata *data = dev->archdata.iommu;
1069
1070 iommu = rk_iommu_from_dev(dev);
1071
1072 device_link_del(data->link);
1073 iommu_device_unlink(&iommu->iommu, dev);
1074 iommu_group_remove_device(dev);
1075}
1076
1077static struct iommu_group *rk_iommu_device_group(struct device *dev)
1078{
1079 struct rk_iommu *iommu;
1080
1081 iommu = rk_iommu_from_dev(dev);
1082
1083 return iommu_group_ref_get(iommu->group);
1084}
1085
1086static int rk_iommu_of_xlate(struct device *dev,
1087 struct of_phandle_args *args)
1088{
1089 struct platform_device *iommu_dev;
1090 struct rk_iommudata *data;
1091
1092 data = devm_kzalloc(dma_dev, sizeof(*data), GFP_KERNEL);
1093 if (!data)
1094 return -ENOMEM;
1095
1096 iommu_dev = of_find_device_by_node(args->np);
1097
1098 data->iommu = platform_get_drvdata(iommu_dev);
1099 dev->archdata.iommu = data;
1100
1101 platform_device_put(iommu_dev);
1102
1103 return 0;
1104}
1105
1106static const struct iommu_ops rk_iommu_ops = {
1107 .domain_alloc = rk_iommu_domain_alloc,
1108 .domain_free = rk_iommu_domain_free,
1109 .attach_dev = rk_iommu_attach_device,
1110 .detach_dev = rk_iommu_detach_device,
1111 .map = rk_iommu_map,
1112 .unmap = rk_iommu_unmap,
1113 .map_sg = default_iommu_map_sg,
1114 .add_device = rk_iommu_add_device,
1115 .remove_device = rk_iommu_remove_device,
1116 .iova_to_phys = rk_iommu_iova_to_phys,
1117 .device_group = rk_iommu_device_group,
1118 .pgsize_bitmap = RK_IOMMU_PGSIZE_BITMAP,
1119 .of_xlate = rk_iommu_of_xlate,
1120};
1121
1122static int rk_iommu_probe(struct platform_device *pdev)
1123{
1124 struct device *dev = &pdev->dev;
1125 struct rk_iommu *iommu;
1126 struct resource *res;
1127 int num_res = pdev->num_resources;
1128 int err, i, irq;
1129
1130 iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL);
1131 if (!iommu)
1132 return -ENOMEM;
1133
1134 platform_set_drvdata(pdev, iommu);
1135 iommu->dev = dev;
1136 iommu->num_mmu = 0;
1137
1138 iommu->bases = devm_kzalloc(dev, sizeof(*iommu->bases) * num_res,
1139 GFP_KERNEL);
1140 if (!iommu->bases)
1141 return -ENOMEM;
1142
1143 for (i = 0; i < num_res; i++) {
1144 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1145 if (!res)
1146 continue;
1147 iommu->bases[i] = devm_ioremap_resource(&pdev->dev, res);
1148 if (IS_ERR(iommu->bases[i]))
1149 continue;
1150 iommu->num_mmu++;
1151 }
1152 if (iommu->num_mmu == 0)
1153 return PTR_ERR(iommu->bases[0]);
1154
1155 i = 0;
1156 while ((irq = platform_get_irq(pdev, i++)) != -ENXIO) {
1157 if (irq < 0)
1158 return irq;
1159
1160 err = devm_request_irq(iommu->dev, irq, rk_iommu_irq,
1161 IRQF_SHARED, dev_name(dev), iommu);
1162 if (err)
1163 return err;
1164 }
1165
1166 iommu->reset_disabled = device_property_read_bool(dev,
1167 "rockchip,disable-mmu-reset");
1168
1169 iommu->num_clocks = ARRAY_SIZE(rk_iommu_clocks);
1170 iommu->clocks = devm_kcalloc(iommu->dev, iommu->num_clocks,
1171 sizeof(*iommu->clocks), GFP_KERNEL);
1172 if (!iommu->clocks)
1173 return -ENOMEM;
1174
1175 for (i = 0; i < iommu->num_clocks; ++i)
1176 iommu->clocks[i].id = rk_iommu_clocks[i];
1177
1178 /*
1179 * iommu clocks should be present for all new devices and devicetrees
1180 * but there are older devicetrees without clocks out in the wild.
1181 * So clocks as optional for the time being.
1182 */
1183 err = devm_clk_bulk_get(iommu->dev, iommu->num_clocks, iommu->clocks);
1184 if (err == -ENOENT)
1185 iommu->num_clocks = 0;
1186 else if (err)
1187 return err;
1188
1189 err = clk_bulk_prepare(iommu->num_clocks, iommu->clocks);
1190 if (err)
1191 return err;
1192
1193 iommu->group = iommu_group_alloc();
1194 if (IS_ERR(iommu->group)) {
1195 err = PTR_ERR(iommu->group);
1196 goto err_unprepare_clocks;
1197 }
1198
1199 err = iommu_device_sysfs_add(&iommu->iommu, dev, NULL, dev_name(dev));
1200 if (err)
1201 goto err_put_group;
1202
1203 iommu_device_set_ops(&iommu->iommu, &rk_iommu_ops);
1204 iommu_device_set_fwnode(&iommu->iommu, &dev->of_node->fwnode);
1205
1206 err = iommu_device_register(&iommu->iommu);
1207 if (err)
1208 goto err_remove_sysfs;
1209
1210 /*
1211 * Use the first registered IOMMU device for domain to use with DMA
1212 * API, since a domain might not physically correspond to a single
1213 * IOMMU device..
1214 */
1215 if (!dma_dev)
1216 dma_dev = &pdev->dev;
1217
1218 bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
1219
1220 pm_runtime_enable(dev);
1221
1222 return 0;
1223err_remove_sysfs:
1224 iommu_device_sysfs_remove(&iommu->iommu);
1225err_put_group:
1226 iommu_group_put(iommu->group);
1227err_unprepare_clocks:
1228 clk_bulk_unprepare(iommu->num_clocks, iommu->clocks);
1229 return err;
1230}
1231
1232static void rk_iommu_shutdown(struct platform_device *pdev)
1233{
1234 pm_runtime_force_suspend(&pdev->dev);
1235}
1236
1237static int __maybe_unused rk_iommu_suspend(struct device *dev)
1238{
1239 struct rk_iommu *iommu = dev_get_drvdata(dev);
1240
1241 if (!iommu->domain)
1242 return 0;
1243
1244 rk_iommu_disable(iommu);
1245 return 0;
1246}
1247
1248static int __maybe_unused rk_iommu_resume(struct device *dev)
1249{
1250 struct rk_iommu *iommu = dev_get_drvdata(dev);
1251
1252 if (!iommu->domain)
1253 return 0;
1254
1255 return rk_iommu_enable(iommu);
1256}
1257
1258static const struct dev_pm_ops rk_iommu_pm_ops = {
1259 SET_RUNTIME_PM_OPS(rk_iommu_suspend, rk_iommu_resume, NULL)
1260 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1261 pm_runtime_force_resume)
1262};
1263
1264static const struct of_device_id rk_iommu_dt_ids[] = {
1265 { .compatible = "rockchip,iommu" },
1266 { /* sentinel */ }
1267};
1268MODULE_DEVICE_TABLE(of, rk_iommu_dt_ids);
1269
1270static struct platform_driver rk_iommu_driver = {
1271 .probe = rk_iommu_probe,
1272 .shutdown = rk_iommu_shutdown,
1273 .driver = {
1274 .name = "rk_iommu",
1275 .of_match_table = rk_iommu_dt_ids,
1276 .pm = &rk_iommu_pm_ops,
1277 .suppress_bind_attrs = true,
1278 },
1279};
1280
1281static int __init rk_iommu_init(void)
1282{
1283 return platform_driver_register(&rk_iommu_driver);
1284}
1285subsys_initcall(rk_iommu_init);
1286
1287IOMMU_OF_DECLARE(rk_iommu_of, "rockchip,iommu");
1288
1289MODULE_DESCRIPTION("IOMMU API for Rockchip");
1290MODULE_AUTHOR("Simon Xue <xxm@rock-chips.com> and Daniel Kurtz <djkurtz@chromium.org>");
1291MODULE_ALIAS("platform:rockchip-iommu");
1292MODULE_LICENSE("GPL v2");