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1/*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#include <drm/drm_color_mgmt.h>
26#include <drm/drm_drv.h>
27#include <drm/intel/pciids.h>
28
29#include "display/intel_display_driver.h"
30#include "gt/intel_gt_regs.h"
31#include "gt/intel_sa_media.h"
32#include "gem/i915_gem_object_types.h"
33
34#include "i915_driver.h"
35#include "i915_drv.h"
36#include "i915_pci.h"
37#include "i915_reg.h"
38#include "intel_pci_config.h"
39
40__diag_push();
41__diag_ignore_all("-Woverride-init", "Allow field initialization overrides for device info");
42
43#define PLATFORM(x) .platform = (x)
44#define GEN(x) \
45 .__runtime.graphics.ip.ver = (x), \
46 .__runtime.media.ip.ver = (x)
47
48#define LEGACY_CACHELEVEL \
49 .cachelevel_to_pat = { \
50 [I915_CACHE_NONE] = 0, \
51 [I915_CACHE_LLC] = 1, \
52 [I915_CACHE_L3_LLC] = 2, \
53 [I915_CACHE_WT] = 3, \
54 }
55
56#define TGL_CACHELEVEL \
57 .cachelevel_to_pat = { \
58 [I915_CACHE_NONE] = 3, \
59 [I915_CACHE_LLC] = 0, \
60 [I915_CACHE_L3_LLC] = 0, \
61 [I915_CACHE_WT] = 2, \
62 }
63
64#define MTL_CACHELEVEL \
65 .cachelevel_to_pat = { \
66 [I915_CACHE_NONE] = 2, \
67 [I915_CACHE_LLC] = 3, \
68 [I915_CACHE_L3_LLC] = 3, \
69 [I915_CACHE_WT] = 1, \
70 }
71
72/* Keep in gen based order, and chronological order within a gen */
73
74#define GEN_DEFAULT_PAGE_SIZES \
75 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K
76
77#define GEN_DEFAULT_REGIONS \
78 .memory_regions = BIT(INTEL_REGION_SMEM) | BIT(INTEL_REGION_STOLEN_SMEM)
79
80#define I830_FEATURES \
81 GEN(2), \
82 .is_mobile = 1, \
83 .gpu_reset_clobbers_display = true, \
84 .has_3d_pipeline = 1, \
85 .hws_needs_physical = 1, \
86 .unfenced_needs_alignment = 1, \
87 .platform_engine_mask = BIT(RCS0), \
88 .has_snoop = true, \
89 .has_coherent_ggtt = false, \
90 .dma_mask_size = 32, \
91 .max_pat_index = 3, \
92 GEN_DEFAULT_PAGE_SIZES, \
93 GEN_DEFAULT_REGIONS, \
94 LEGACY_CACHELEVEL
95
96#define I845_FEATURES \
97 GEN(2), \
98 .has_3d_pipeline = 1, \
99 .gpu_reset_clobbers_display = true, \
100 .hws_needs_physical = 1, \
101 .unfenced_needs_alignment = 1, \
102 .platform_engine_mask = BIT(RCS0), \
103 .has_snoop = true, \
104 .has_coherent_ggtt = false, \
105 .dma_mask_size = 32, \
106 .max_pat_index = 3, \
107 GEN_DEFAULT_PAGE_SIZES, \
108 GEN_DEFAULT_REGIONS, \
109 LEGACY_CACHELEVEL
110
111static const struct intel_device_info i830_info = {
112 I830_FEATURES,
113 PLATFORM(INTEL_I830),
114};
115
116static const struct intel_device_info i845g_info = {
117 I845_FEATURES,
118 PLATFORM(INTEL_I845G),
119};
120
121static const struct intel_device_info i85x_info = {
122 I830_FEATURES,
123 PLATFORM(INTEL_I85X),
124};
125
126static const struct intel_device_info i865g_info = {
127 I845_FEATURES,
128 PLATFORM(INTEL_I865G),
129};
130
131#define GEN3_FEATURES \
132 GEN(3), \
133 .gpu_reset_clobbers_display = true, \
134 .platform_engine_mask = BIT(RCS0), \
135 .has_3d_pipeline = 1, \
136 .has_snoop = true, \
137 .has_coherent_ggtt = true, \
138 .dma_mask_size = 32, \
139 .max_pat_index = 3, \
140 GEN_DEFAULT_PAGE_SIZES, \
141 GEN_DEFAULT_REGIONS, \
142 LEGACY_CACHELEVEL
143
144static const struct intel_device_info i915g_info = {
145 GEN3_FEATURES,
146 PLATFORM(INTEL_I915G),
147 .has_coherent_ggtt = false,
148 .hws_needs_physical = 1,
149 .unfenced_needs_alignment = 1,
150};
151
152static const struct intel_device_info i915gm_info = {
153 GEN3_FEATURES,
154 PLATFORM(INTEL_I915GM),
155 .is_mobile = 1,
156 .hws_needs_physical = 1,
157 .unfenced_needs_alignment = 1,
158};
159
160static const struct intel_device_info i945g_info = {
161 GEN3_FEATURES,
162 PLATFORM(INTEL_I945G),
163 .hws_needs_physical = 1,
164 .unfenced_needs_alignment = 1,
165};
166
167static const struct intel_device_info i945gm_info = {
168 GEN3_FEATURES,
169 PLATFORM(INTEL_I945GM),
170 .is_mobile = 1,
171 .hws_needs_physical = 1,
172 .unfenced_needs_alignment = 1,
173};
174
175static const struct intel_device_info g33_info = {
176 GEN3_FEATURES,
177 PLATFORM(INTEL_G33),
178 .dma_mask_size = 36,
179};
180
181static const struct intel_device_info pnv_g_info = {
182 GEN3_FEATURES,
183 PLATFORM(INTEL_PINEVIEW),
184 .dma_mask_size = 36,
185};
186
187static const struct intel_device_info pnv_m_info = {
188 GEN3_FEATURES,
189 PLATFORM(INTEL_PINEVIEW),
190 .is_mobile = 1,
191 .dma_mask_size = 36,
192};
193
194#define GEN4_FEATURES \
195 GEN(4), \
196 .gpu_reset_clobbers_display = true, \
197 .platform_engine_mask = BIT(RCS0), \
198 .has_3d_pipeline = 1, \
199 .has_snoop = true, \
200 .has_coherent_ggtt = true, \
201 .dma_mask_size = 36, \
202 .max_pat_index = 3, \
203 GEN_DEFAULT_PAGE_SIZES, \
204 GEN_DEFAULT_REGIONS, \
205 LEGACY_CACHELEVEL
206
207static const struct intel_device_info i965g_info = {
208 GEN4_FEATURES,
209 PLATFORM(INTEL_I965G),
210 .hws_needs_physical = 1,
211 .has_snoop = false,
212};
213
214static const struct intel_device_info i965gm_info = {
215 GEN4_FEATURES,
216 PLATFORM(INTEL_I965GM),
217 .is_mobile = 1,
218 .hws_needs_physical = 1,
219 .has_snoop = false,
220};
221
222static const struct intel_device_info g45_info = {
223 GEN4_FEATURES,
224 PLATFORM(INTEL_G45),
225 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
226 .gpu_reset_clobbers_display = false,
227};
228
229static const struct intel_device_info gm45_info = {
230 GEN4_FEATURES,
231 PLATFORM(INTEL_GM45),
232 .is_mobile = 1,
233 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
234 .gpu_reset_clobbers_display = false,
235};
236
237#define GEN5_FEATURES \
238 GEN(5), \
239 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
240 .has_3d_pipeline = 1, \
241 .has_snoop = true, \
242 .has_coherent_ggtt = true, \
243 /* ilk does support rc6, but we do not implement [power] contexts */ \
244 .has_rc6 = 0, \
245 .dma_mask_size = 36, \
246 .max_pat_index = 3, \
247 GEN_DEFAULT_PAGE_SIZES, \
248 GEN_DEFAULT_REGIONS, \
249 LEGACY_CACHELEVEL
250
251static const struct intel_device_info ilk_d_info = {
252 GEN5_FEATURES,
253 PLATFORM(INTEL_IRONLAKE),
254};
255
256static const struct intel_device_info ilk_m_info = {
257 GEN5_FEATURES,
258 PLATFORM(INTEL_IRONLAKE),
259 .is_mobile = 1,
260 .has_rps = true,
261};
262
263#define GEN6_FEATURES \
264 GEN(6), \
265 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
266 .has_3d_pipeline = 1, \
267 .has_coherent_ggtt = true, \
268 .has_llc = 1, \
269 .has_rc6 = 1, \
270 /* snb does support rc6p, but enabling it causes various issues */ \
271 .has_rc6p = 0, \
272 .has_rps = true, \
273 .dma_mask_size = 40, \
274 .max_pat_index = 3, \
275 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
276 .__runtime.ppgtt_size = 31, \
277 GEN_DEFAULT_PAGE_SIZES, \
278 GEN_DEFAULT_REGIONS, \
279 LEGACY_CACHELEVEL
280
281#define SNB_D_PLATFORM \
282 GEN6_FEATURES, \
283 PLATFORM(INTEL_SANDYBRIDGE)
284
285static const struct intel_device_info snb_d_gt1_info = {
286 SNB_D_PLATFORM,
287 .gt = 1,
288};
289
290static const struct intel_device_info snb_d_gt2_info = {
291 SNB_D_PLATFORM,
292 .gt = 2,
293};
294
295#define SNB_M_PLATFORM \
296 GEN6_FEATURES, \
297 PLATFORM(INTEL_SANDYBRIDGE), \
298 .is_mobile = 1
299
300
301static const struct intel_device_info snb_m_gt1_info = {
302 SNB_M_PLATFORM,
303 .gt = 1,
304};
305
306static const struct intel_device_info snb_m_gt2_info = {
307 SNB_M_PLATFORM,
308 .gt = 2,
309};
310
311#define GEN7_FEATURES \
312 GEN(7), \
313 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
314 .has_3d_pipeline = 1, \
315 .has_coherent_ggtt = true, \
316 .has_llc = 1, \
317 .has_rc6 = 1, \
318 .has_rc6p = 1, \
319 .has_reset_engine = true, \
320 .has_rps = true, \
321 .dma_mask_size = 40, \
322 .max_pat_index = 3, \
323 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
324 .__runtime.ppgtt_size = 31, \
325 GEN_DEFAULT_PAGE_SIZES, \
326 GEN_DEFAULT_REGIONS, \
327 LEGACY_CACHELEVEL
328
329#define IVB_D_PLATFORM \
330 GEN7_FEATURES, \
331 PLATFORM(INTEL_IVYBRIDGE), \
332 .has_l3_dpf = 1
333
334static const struct intel_device_info ivb_d_gt1_info = {
335 IVB_D_PLATFORM,
336 .gt = 1,
337};
338
339static const struct intel_device_info ivb_d_gt2_info = {
340 IVB_D_PLATFORM,
341 .gt = 2,
342};
343
344#define IVB_M_PLATFORM \
345 GEN7_FEATURES, \
346 PLATFORM(INTEL_IVYBRIDGE), \
347 .is_mobile = 1, \
348 .has_l3_dpf = 1
349
350static const struct intel_device_info ivb_m_gt1_info = {
351 IVB_M_PLATFORM,
352 .gt = 1,
353};
354
355static const struct intel_device_info ivb_m_gt2_info = {
356 IVB_M_PLATFORM,
357 .gt = 2,
358};
359
360static const struct intel_device_info ivb_q_info = {
361 GEN7_FEATURES,
362 PLATFORM(INTEL_IVYBRIDGE),
363 .gt = 2,
364 .has_l3_dpf = 1,
365};
366
367static const struct intel_device_info vlv_info = {
368 PLATFORM(INTEL_VALLEYVIEW),
369 GEN(7),
370 .has_runtime_pm = 1,
371 .has_rc6 = 1,
372 .has_reset_engine = true,
373 .has_rps = true,
374 .dma_mask_size = 40,
375 .max_pat_index = 3,
376 .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING,
377 .__runtime.ppgtt_size = 31,
378 .has_snoop = true,
379 .has_coherent_ggtt = false,
380 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
381 GEN_DEFAULT_PAGE_SIZES,
382 GEN_DEFAULT_REGIONS,
383 LEGACY_CACHELEVEL,
384};
385
386#define G75_FEATURES \
387 GEN7_FEATURES, \
388 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
389 .has_rc6p = 0 /* RC6p removed-by HSW */, \
390 .has_runtime_pm = 1
391
392#define HSW_PLATFORM \
393 G75_FEATURES, \
394 PLATFORM(INTEL_HASWELL), \
395 .has_l3_dpf = 1
396
397static const struct intel_device_info hsw_gt1_info = {
398 HSW_PLATFORM,
399 .gt = 1,
400};
401
402static const struct intel_device_info hsw_gt2_info = {
403 HSW_PLATFORM,
404 .gt = 2,
405};
406
407static const struct intel_device_info hsw_gt3_info = {
408 HSW_PLATFORM,
409 .gt = 3,
410};
411
412#define GEN8_FEATURES \
413 G75_FEATURES, \
414 GEN(8), \
415 .has_logical_ring_contexts = 1, \
416 .dma_mask_size = 39, \
417 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \
418 .__runtime.ppgtt_size = 48, \
419 .has_64bit_reloc = 1
420
421#define BDW_PLATFORM \
422 GEN8_FEATURES, \
423 PLATFORM(INTEL_BROADWELL)
424
425static const struct intel_device_info bdw_gt1_info = {
426 BDW_PLATFORM,
427 .gt = 1,
428};
429
430static const struct intel_device_info bdw_gt2_info = {
431 BDW_PLATFORM,
432 .gt = 2,
433};
434
435static const struct intel_device_info bdw_rsvd_info = {
436 BDW_PLATFORM,
437 .gt = 3,
438 /* According to the device ID those devices are GT3, they were
439 * previously treated as not GT3, keep it like that.
440 */
441};
442
443static const struct intel_device_info bdw_gt3_info = {
444 BDW_PLATFORM,
445 .gt = 3,
446 .platform_engine_mask =
447 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
448};
449
450static const struct intel_device_info chv_info = {
451 PLATFORM(INTEL_CHERRYVIEW),
452 GEN(8),
453 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
454 .has_64bit_reloc = 1,
455 .has_runtime_pm = 1,
456 .has_rc6 = 1,
457 .has_rps = true,
458 .has_logical_ring_contexts = 1,
459 .dma_mask_size = 39,
460 .max_pat_index = 3,
461 .__runtime.ppgtt_type = INTEL_PPGTT_FULL,
462 .__runtime.ppgtt_size = 32,
463 .has_reset_engine = 1,
464 .has_snoop = true,
465 .has_coherent_ggtt = false,
466 GEN_DEFAULT_PAGE_SIZES,
467 GEN_DEFAULT_REGIONS,
468 LEGACY_CACHELEVEL,
469};
470
471#define GEN9_DEFAULT_PAGE_SIZES \
472 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \
473 I915_GTT_PAGE_SIZE_64K
474
475#define GEN9_FEATURES \
476 GEN8_FEATURES, \
477 GEN(9), \
478 GEN9_DEFAULT_PAGE_SIZES, \
479 .has_gt_uc = 1
480
481#define SKL_PLATFORM \
482 GEN9_FEATURES, \
483 PLATFORM(INTEL_SKYLAKE)
484
485static const struct intel_device_info skl_gt1_info = {
486 SKL_PLATFORM,
487 .gt = 1,
488};
489
490static const struct intel_device_info skl_gt2_info = {
491 SKL_PLATFORM,
492 .gt = 2,
493};
494
495#define SKL_GT3_PLUS_PLATFORM \
496 SKL_PLATFORM, \
497 .platform_engine_mask = \
498 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
499
500
501static const struct intel_device_info skl_gt3_info = {
502 SKL_GT3_PLUS_PLATFORM,
503 .gt = 3,
504};
505
506static const struct intel_device_info skl_gt4_info = {
507 SKL_GT3_PLUS_PLATFORM,
508 .gt = 4,
509};
510
511#define GEN9_LP_FEATURES \
512 GEN(9), \
513 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
514 .has_3d_pipeline = 1, \
515 .has_64bit_reloc = 1, \
516 .has_runtime_pm = 1, \
517 .has_rc6 = 1, \
518 .has_rps = true, \
519 .has_logical_ring_contexts = 1, \
520 .has_gt_uc = 1, \
521 .dma_mask_size = 39, \
522 .__runtime.ppgtt_type = INTEL_PPGTT_FULL, \
523 .__runtime.ppgtt_size = 48, \
524 .has_reset_engine = 1, \
525 .has_snoop = true, \
526 .has_coherent_ggtt = false, \
527 .max_pat_index = 3, \
528 GEN9_DEFAULT_PAGE_SIZES, \
529 GEN_DEFAULT_REGIONS, \
530 LEGACY_CACHELEVEL
531
532static const struct intel_device_info bxt_info = {
533 GEN9_LP_FEATURES,
534 PLATFORM(INTEL_BROXTON),
535};
536
537static const struct intel_device_info glk_info = {
538 GEN9_LP_FEATURES,
539 PLATFORM(INTEL_GEMINILAKE),
540};
541
542#define KBL_PLATFORM \
543 GEN9_FEATURES, \
544 PLATFORM(INTEL_KABYLAKE)
545
546static const struct intel_device_info kbl_gt1_info = {
547 KBL_PLATFORM,
548 .gt = 1,
549};
550
551static const struct intel_device_info kbl_gt2_info = {
552 KBL_PLATFORM,
553 .gt = 2,
554};
555
556static const struct intel_device_info kbl_gt3_info = {
557 KBL_PLATFORM,
558 .gt = 3,
559 .platform_engine_mask =
560 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
561};
562
563#define CFL_PLATFORM \
564 GEN9_FEATURES, \
565 PLATFORM(INTEL_COFFEELAKE)
566
567static const struct intel_device_info cfl_gt1_info = {
568 CFL_PLATFORM,
569 .gt = 1,
570};
571
572static const struct intel_device_info cfl_gt2_info = {
573 CFL_PLATFORM,
574 .gt = 2,
575};
576
577static const struct intel_device_info cfl_gt3_info = {
578 CFL_PLATFORM,
579 .gt = 3,
580 .platform_engine_mask =
581 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
582};
583
584#define CML_PLATFORM \
585 GEN9_FEATURES, \
586 PLATFORM(INTEL_COMETLAKE)
587
588static const struct intel_device_info cml_gt1_info = {
589 CML_PLATFORM,
590 .gt = 1,
591};
592
593static const struct intel_device_info cml_gt2_info = {
594 CML_PLATFORM,
595 .gt = 2,
596};
597
598#define GEN11_DEFAULT_PAGE_SIZES \
599 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \
600 I915_GTT_PAGE_SIZE_64K | \
601 I915_GTT_PAGE_SIZE_2M
602
603#define GEN11_FEATURES \
604 GEN9_FEATURES, \
605 GEN11_DEFAULT_PAGE_SIZES, \
606 GEN(11), \
607 .has_coherent_ggtt = false, \
608 .has_logical_ring_elsq = 1
609
610static const struct intel_device_info icl_info = {
611 GEN11_FEATURES,
612 PLATFORM(INTEL_ICELAKE),
613 .platform_engine_mask =
614 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
615};
616
617static const struct intel_device_info ehl_info = {
618 GEN11_FEATURES,
619 PLATFORM(INTEL_ELKHARTLAKE),
620 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
621 .__runtime.ppgtt_size = 36,
622};
623
624static const struct intel_device_info jsl_info = {
625 GEN11_FEATURES,
626 PLATFORM(INTEL_JASPERLAKE),
627 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
628 .__runtime.ppgtt_size = 36,
629};
630
631#define GEN12_FEATURES \
632 GEN11_FEATURES, \
633 GEN(12), \
634 TGL_CACHELEVEL, \
635 .has_global_mocs = 1, \
636 .has_pxp = 1, \
637 .max_pat_index = 3
638
639static const struct intel_device_info tgl_info = {
640 GEN12_FEATURES,
641 PLATFORM(INTEL_TIGERLAKE),
642 .platform_engine_mask =
643 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
644};
645
646static const struct intel_device_info rkl_info = {
647 GEN12_FEATURES,
648 PLATFORM(INTEL_ROCKETLAKE),
649 .platform_engine_mask =
650 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
651};
652
653#define DGFX_FEATURES \
654 .memory_regions = BIT(INTEL_REGION_SMEM) | BIT(INTEL_REGION_LMEM_0) | BIT(INTEL_REGION_STOLEN_LMEM), \
655 .has_llc = 0, \
656 .has_pxp = 0, \
657 .has_snoop = 1, \
658 .is_dgfx = 1, \
659 .has_heci_gscfi = 1
660
661static const struct intel_device_info dg1_info = {
662 GEN12_FEATURES,
663 DGFX_FEATURES,
664 .__runtime.graphics.ip.rel = 10,
665 PLATFORM(INTEL_DG1),
666 .require_force_probe = 1,
667 .platform_engine_mask =
668 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
669 BIT(VCS0) | BIT(VCS2),
670 /* Wa_16011227922 */
671 .__runtime.ppgtt_size = 47,
672};
673
674static const struct intel_device_info adl_s_info = {
675 GEN12_FEATURES,
676 PLATFORM(INTEL_ALDERLAKE_S),
677 .platform_engine_mask =
678 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
679 .dma_mask_size = 39,
680};
681
682static const struct intel_device_info adl_p_info = {
683 GEN12_FEATURES,
684 PLATFORM(INTEL_ALDERLAKE_P),
685 .platform_engine_mask =
686 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
687 .__runtime.ppgtt_size = 48,
688 .dma_mask_size = 39,
689};
690
691#undef GEN
692
693#define XE_HP_PAGE_SIZES \
694 .__runtime.page_sizes = I915_GTT_PAGE_SIZE_4K | \
695 I915_GTT_PAGE_SIZE_64K | \
696 I915_GTT_PAGE_SIZE_2M
697
698#define XE_HP_FEATURES \
699 XE_HP_PAGE_SIZES, \
700 TGL_CACHELEVEL, \
701 .dma_mask_size = 46, \
702 .has_3d_pipeline = 1, \
703 .has_64bit_reloc = 1, \
704 .has_flat_ccs = 1, \
705 .has_global_mocs = 1, \
706 .has_gt_uc = 1, \
707 .has_llc = 1, \
708 .has_logical_ring_contexts = 1, \
709 .has_logical_ring_elsq = 1, \
710 .has_mslice_steering = 1, \
711 .has_oa_bpc_reporting = 1, \
712 .has_oa_slice_contrib_limits = 1, \
713 .has_oam = 1, \
714 .has_rc6 = 1, \
715 .has_reset_engine = 1, \
716 .has_rps = 1, \
717 .has_runtime_pm = 1, \
718 .max_pat_index = 3, \
719 .__runtime.ppgtt_size = 48, \
720 .__runtime.ppgtt_type = INTEL_PPGTT_FULL
721
722#define DG2_FEATURES \
723 XE_HP_FEATURES, \
724 DGFX_FEATURES, \
725 .__runtime.graphics.ip.ver = 12, \
726 .__runtime.graphics.ip.rel = 55, \
727 .__runtime.media.ip.ver = 12, \
728 .__runtime.media.ip.rel = 55, \
729 PLATFORM(INTEL_DG2), \
730 .has_64k_pages = 1, \
731 .has_guc_deprivilege = 1, \
732 .has_heci_pxp = 1, \
733 .has_media_ratio_mode = 1, \
734 .platform_engine_mask = \
735 BIT(RCS0) | BIT(BCS0) | \
736 BIT(VECS0) | BIT(VECS1) | \
737 BIT(VCS0) | BIT(VCS2) | \
738 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
739
740static const struct intel_device_info dg2_info = {
741 DG2_FEATURES,
742};
743
744static const struct intel_device_info ats_m_info = {
745 DG2_FEATURES,
746 .require_force_probe = 1,
747 .tuning_thread_rr_after_dep = 1,
748};
749
750static const struct intel_gt_definition xelpmp_extra_gt[] = {
751 {
752 .type = GT_MEDIA,
753 .name = "Standalone Media GT",
754 .gsi_offset = MTL_MEDIA_GSI_BASE,
755 .engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2) | BIT(GSC0),
756 },
757 {}
758};
759
760static const struct intel_device_info mtl_info = {
761 XE_HP_FEATURES,
762 /*
763 * Real graphics IP version will be obtained from hardware GMD_ID
764 * register. Value provided here is just for sanity checking.
765 */
766 .__runtime.graphics.ip.ver = 12,
767 .__runtime.graphics.ip.rel = 70,
768 .__runtime.media.ip.ver = 13,
769 PLATFORM(INTEL_METEORLAKE),
770 .extra_gt_list = xelpmp_extra_gt,
771 .has_flat_ccs = 0,
772 .has_gmd_id = 1,
773 .has_guc_deprivilege = 1,
774 .has_guc_tlb_invalidation = 1,
775 .has_llc = 0,
776 .has_mslice_steering = 0,
777 .has_snoop = 1,
778 .max_pat_index = 4,
779 .has_pxp = 1,
780 .memory_regions = BIT(INTEL_REGION_SMEM) | BIT(INTEL_REGION_STOLEN_LMEM),
781 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
782 MTL_CACHELEVEL,
783};
784
785#undef PLATFORM
786
787__diag_pop();
788
789/*
790 * Make sure any device matches here are from most specific to most
791 * general. For example, since the Quanta match is based on the subsystem
792 * and subvendor IDs, we need it to come before the more general IVB
793 * PCI ID matches, otherwise we'll use the wrong info struct above.
794 */
795static const struct pci_device_id pciidlist[] = {
796 INTEL_I830_IDS(INTEL_VGA_DEVICE, &i830_info),
797 INTEL_I845G_IDS(INTEL_VGA_DEVICE, &i845g_info),
798 INTEL_I85X_IDS(INTEL_VGA_DEVICE, &i85x_info),
799 INTEL_I865G_IDS(INTEL_VGA_DEVICE, &i865g_info),
800 INTEL_I915G_IDS(INTEL_VGA_DEVICE, &i915g_info),
801 INTEL_I915GM_IDS(INTEL_VGA_DEVICE, &i915gm_info),
802 INTEL_I945G_IDS(INTEL_VGA_DEVICE, &i945g_info),
803 INTEL_I945GM_IDS(INTEL_VGA_DEVICE, &i945gm_info),
804 INTEL_I965G_IDS(INTEL_VGA_DEVICE, &i965g_info),
805 INTEL_G33_IDS(INTEL_VGA_DEVICE, &g33_info),
806 INTEL_I965GM_IDS(INTEL_VGA_DEVICE, &i965gm_info),
807 INTEL_GM45_IDS(INTEL_VGA_DEVICE, &gm45_info),
808 INTEL_G45_IDS(INTEL_VGA_DEVICE, &g45_info),
809 INTEL_PNV_G_IDS(INTEL_VGA_DEVICE, &pnv_g_info),
810 INTEL_PNV_M_IDS(INTEL_VGA_DEVICE, &pnv_m_info),
811 INTEL_ILK_D_IDS(INTEL_VGA_DEVICE, &ilk_d_info),
812 INTEL_ILK_M_IDS(INTEL_VGA_DEVICE, &ilk_m_info),
813 INTEL_SNB_D_GT1_IDS(INTEL_VGA_DEVICE, &snb_d_gt1_info),
814 INTEL_SNB_D_GT2_IDS(INTEL_VGA_DEVICE, &snb_d_gt2_info),
815 INTEL_SNB_M_GT1_IDS(INTEL_VGA_DEVICE, &snb_m_gt1_info),
816 INTEL_SNB_M_GT2_IDS(INTEL_VGA_DEVICE, &snb_m_gt2_info),
817 INTEL_IVB_Q_IDS(INTEL_VGA_DEVICE, &ivb_q_info), /* must be first IVB */
818 INTEL_IVB_M_GT1_IDS(INTEL_VGA_DEVICE, &ivb_m_gt1_info),
819 INTEL_IVB_M_GT2_IDS(INTEL_VGA_DEVICE, &ivb_m_gt2_info),
820 INTEL_IVB_D_GT1_IDS(INTEL_VGA_DEVICE, &ivb_d_gt1_info),
821 INTEL_IVB_D_GT2_IDS(INTEL_VGA_DEVICE, &ivb_d_gt2_info),
822 INTEL_HSW_GT1_IDS(INTEL_VGA_DEVICE, &hsw_gt1_info),
823 INTEL_HSW_GT2_IDS(INTEL_VGA_DEVICE, &hsw_gt2_info),
824 INTEL_HSW_GT3_IDS(INTEL_VGA_DEVICE, &hsw_gt3_info),
825 INTEL_VLV_IDS(INTEL_VGA_DEVICE, &vlv_info),
826 INTEL_BDW_GT1_IDS(INTEL_VGA_DEVICE, &bdw_gt1_info),
827 INTEL_BDW_GT2_IDS(INTEL_VGA_DEVICE, &bdw_gt2_info),
828 INTEL_BDW_GT3_IDS(INTEL_VGA_DEVICE, &bdw_gt3_info),
829 INTEL_BDW_RSVD_IDS(INTEL_VGA_DEVICE, &bdw_rsvd_info),
830 INTEL_CHV_IDS(INTEL_VGA_DEVICE, &chv_info),
831 INTEL_SKL_GT1_IDS(INTEL_VGA_DEVICE, &skl_gt1_info),
832 INTEL_SKL_GT2_IDS(INTEL_VGA_DEVICE, &skl_gt2_info),
833 INTEL_SKL_GT3_IDS(INTEL_VGA_DEVICE, &skl_gt3_info),
834 INTEL_SKL_GT4_IDS(INTEL_VGA_DEVICE, &skl_gt4_info),
835 INTEL_BXT_IDS(INTEL_VGA_DEVICE, &bxt_info),
836 INTEL_GLK_IDS(INTEL_VGA_DEVICE, &glk_info),
837 INTEL_KBL_GT1_IDS(INTEL_VGA_DEVICE, &kbl_gt1_info),
838 INTEL_KBL_GT2_IDS(INTEL_VGA_DEVICE, &kbl_gt2_info),
839 INTEL_KBL_GT3_IDS(INTEL_VGA_DEVICE, &kbl_gt3_info),
840 INTEL_KBL_GT4_IDS(INTEL_VGA_DEVICE, &kbl_gt3_info),
841 INTEL_AML_KBL_GT2_IDS(INTEL_VGA_DEVICE, &kbl_gt2_info),
842 INTEL_CFL_S_GT1_IDS(INTEL_VGA_DEVICE, &cfl_gt1_info),
843 INTEL_CFL_S_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info),
844 INTEL_CFL_H_GT1_IDS(INTEL_VGA_DEVICE, &cfl_gt1_info),
845 INTEL_CFL_H_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info),
846 INTEL_CFL_U_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info),
847 INTEL_CFL_U_GT3_IDS(INTEL_VGA_DEVICE, &cfl_gt3_info),
848 INTEL_WHL_U_GT1_IDS(INTEL_VGA_DEVICE, &cfl_gt1_info),
849 INTEL_WHL_U_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info),
850 INTEL_AML_CFL_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info),
851 INTEL_WHL_U_GT3_IDS(INTEL_VGA_DEVICE, &cfl_gt3_info),
852 INTEL_CML_GT1_IDS(INTEL_VGA_DEVICE, &cml_gt1_info),
853 INTEL_CML_GT2_IDS(INTEL_VGA_DEVICE, &cml_gt2_info),
854 INTEL_CML_U_GT1_IDS(INTEL_VGA_DEVICE, &cml_gt1_info),
855 INTEL_CML_U_GT2_IDS(INTEL_VGA_DEVICE, &cml_gt2_info),
856 INTEL_ICL_IDS(INTEL_VGA_DEVICE, &icl_info),
857 INTEL_EHL_IDS(INTEL_VGA_DEVICE, &ehl_info),
858 INTEL_JSL_IDS(INTEL_VGA_DEVICE, &jsl_info),
859 INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_info),
860 INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_info),
861 INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_info),
862 INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_info),
863 INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_p_info),
864 INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_info),
865 INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_info),
866 INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_info),
867 INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_info),
868 INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_info),
869 INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_info),
870 INTEL_ARL_IDS(INTEL_VGA_DEVICE, &mtl_info),
871 INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_info),
872 {}
873};
874MODULE_DEVICE_TABLE(pci, pciidlist);
875
876static void i915_pci_remove(struct pci_dev *pdev)
877{
878 struct drm_i915_private *i915;
879
880 i915 = pdev_to_i915(pdev);
881 if (!i915) /* driver load aborted, nothing to cleanup */
882 return;
883
884 i915_driver_remove(i915);
885 pci_set_drvdata(pdev, NULL);
886}
887
888/* is device_id present in comma separated list of ids */
889static bool device_id_in_list(u16 device_id, const char *devices, bool negative)
890{
891 char *s, *p, *tok;
892 bool ret;
893
894 if (!devices || !*devices)
895 return false;
896
897 /* match everything */
898 if (negative && strcmp(devices, "!*") == 0)
899 return true;
900 if (!negative && strcmp(devices, "*") == 0)
901 return true;
902
903 s = kstrdup(devices, GFP_KERNEL);
904 if (!s)
905 return false;
906
907 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
908 u16 val;
909
910 if (negative && tok[0] == '!')
911 tok++;
912 else if ((negative && tok[0] != '!') ||
913 (!negative && tok[0] == '!'))
914 continue;
915
916 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
917 ret = true;
918 break;
919 }
920 }
921
922 kfree(s);
923
924 return ret;
925}
926
927static bool id_forced(u16 device_id)
928{
929 return device_id_in_list(device_id, i915_modparams.force_probe, false);
930}
931
932static bool id_blocked(u16 device_id)
933{
934 return device_id_in_list(device_id, i915_modparams.force_probe, true);
935}
936
937bool i915_pci_resource_valid(struct pci_dev *pdev, int bar)
938{
939 if (!pci_resource_flags(pdev, bar))
940 return false;
941
942 if (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET)
943 return false;
944
945 if (!pci_resource_len(pdev, bar))
946 return false;
947
948 return true;
949}
950
951static bool intel_mmio_bar_valid(struct pci_dev *pdev, struct intel_device_info *intel_info)
952{
953 return i915_pci_resource_valid(pdev, intel_mmio_bar(intel_info->__runtime.graphics.ip.ver));
954}
955
956static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
957{
958 struct intel_device_info *intel_info =
959 (struct intel_device_info *) ent->driver_data;
960 int err;
961
962 if (intel_info->require_force_probe && !id_forced(pdev->device)) {
963 dev_info(&pdev->dev,
964 "Your graphics device %04x is not properly supported by i915 in this\n"
965 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
966 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
967 "or (recommended) check for kernel updates.\n",
968 pdev->device, pdev->device, pdev->device);
969 return -ENODEV;
970 }
971
972 if (id_blocked(pdev->device)) {
973 dev_info(&pdev->dev, "I915 probe blocked for Device ID %04x.\n",
974 pdev->device);
975 return -ENODEV;
976 }
977
978 if (intel_info->require_force_probe) {
979 dev_info(&pdev->dev, "Force probing unsupported Device ID %04x, tainting kernel\n",
980 pdev->device);
981 add_taint(TAINT_USER, LOCKDEP_STILL_OK);
982 }
983
984 /* Only bind to function 0 of the device. Early generations
985 * used function 1 as a placeholder for multi-head. This causes
986 * us confusion instead, especially on the systems where both
987 * functions have the same PCI-ID!
988 */
989 if (PCI_FUNC(pdev->devfn))
990 return -ENODEV;
991
992 if (!intel_mmio_bar_valid(pdev, intel_info))
993 return -ENXIO;
994
995 /* Detect if we need to wait for other drivers early on */
996 if (intel_display_driver_probe_defer(pdev))
997 return -EPROBE_DEFER;
998
999 err = i915_driver_probe(pdev, ent);
1000 if (err)
1001 return err;
1002
1003 if (i915_inject_probe_failure(pdev_to_i915(pdev))) {
1004 i915_pci_remove(pdev);
1005 return -ENODEV;
1006 }
1007
1008 err = i915_live_selftests(pdev);
1009 if (err) {
1010 i915_pci_remove(pdev);
1011 return err > 0 ? -ENOTTY : err;
1012 }
1013
1014 err = i915_perf_selftests(pdev);
1015 if (err) {
1016 i915_pci_remove(pdev);
1017 return err > 0 ? -ENOTTY : err;
1018 }
1019
1020 return 0;
1021}
1022
1023static void i915_pci_shutdown(struct pci_dev *pdev)
1024{
1025 struct drm_i915_private *i915 = pdev_to_i915(pdev);
1026
1027 i915_driver_shutdown(i915);
1028}
1029
1030static struct pci_driver i915_pci_driver = {
1031 .name = DRIVER_NAME,
1032 .id_table = pciidlist,
1033 .probe = i915_pci_probe,
1034 .remove = i915_pci_remove,
1035 .shutdown = i915_pci_shutdown,
1036 .driver.pm = &i915_pm_ops,
1037};
1038
1039int i915_pci_register_driver(void)
1040{
1041 return pci_register_driver(&i915_pci_driver);
1042}
1043
1044void i915_pci_unregister_driver(void)
1045{
1046 pci_unregister_driver(&i915_pci_driver);
1047}
1/*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#include <linux/console.h>
26#include <linux/vgaarb.h>
27#include <linux/vga_switcheroo.h>
28
29#include "i915_drv.h"
30#include "i915_selftest.h"
31
32#define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
33#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
34
35#define GEN_DEFAULT_PIPEOFFSETS \
36 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
37 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
38 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
39 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
40 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
41
42#define GEN_CHV_PIPEOFFSETS \
43 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
44 CHV_PIPE_C_OFFSET }, \
45 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
46 CHV_TRANSCODER_C_OFFSET, }, \
47 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
48 CHV_PALETTE_C_OFFSET }
49
50#define CURSOR_OFFSETS \
51 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
52
53#define IVB_CURSOR_OFFSETS \
54 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
55
56#define BDW_COLORS \
57 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
58#define CHV_COLORS \
59 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
60#define GLK_COLORS \
61 .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
62
63/* Keep in gen based order, and chronological order within a gen */
64
65#define GEN_DEFAULT_PAGE_SIZES \
66 .page_sizes = I915_GTT_PAGE_SIZE_4K
67
68#define GEN2_FEATURES \
69 GEN(2), \
70 .num_pipes = 1, \
71 .has_overlay = 1, .overlay_needs_physical = 1, \
72 .has_gmch_display = 1, \
73 .hws_needs_physical = 1, \
74 .unfenced_needs_alignment = 1, \
75 .ring_mask = RENDER_RING, \
76 .has_snoop = true, \
77 GEN_DEFAULT_PIPEOFFSETS, \
78 GEN_DEFAULT_PAGE_SIZES, \
79 CURSOR_OFFSETS
80
81static const struct intel_device_info intel_i830_info = {
82 GEN2_FEATURES,
83 PLATFORM(INTEL_I830),
84 .is_mobile = 1, .cursor_needs_physical = 1,
85 .num_pipes = 2, /* legal, last one wins */
86};
87
88static const struct intel_device_info intel_i845g_info = {
89 GEN2_FEATURES,
90 PLATFORM(INTEL_I845G),
91};
92
93static const struct intel_device_info intel_i85x_info = {
94 GEN2_FEATURES,
95 PLATFORM(INTEL_I85X),
96 .is_mobile = 1,
97 .num_pipes = 2, /* legal, last one wins */
98 .cursor_needs_physical = 1,
99 .has_fbc = 1,
100};
101
102static const struct intel_device_info intel_i865g_info = {
103 GEN2_FEATURES,
104 PLATFORM(INTEL_I865G),
105};
106
107#define GEN3_FEATURES \
108 GEN(3), \
109 .num_pipes = 2, \
110 .has_gmch_display = 1, \
111 .ring_mask = RENDER_RING, \
112 .has_snoop = true, \
113 GEN_DEFAULT_PIPEOFFSETS, \
114 GEN_DEFAULT_PAGE_SIZES, \
115 CURSOR_OFFSETS
116
117static const struct intel_device_info intel_i915g_info = {
118 GEN3_FEATURES,
119 PLATFORM(INTEL_I915G),
120 .cursor_needs_physical = 1,
121 .has_overlay = 1, .overlay_needs_physical = 1,
122 .hws_needs_physical = 1,
123 .unfenced_needs_alignment = 1,
124};
125
126static const struct intel_device_info intel_i915gm_info = {
127 GEN3_FEATURES,
128 PLATFORM(INTEL_I915GM),
129 .is_mobile = 1,
130 .cursor_needs_physical = 1,
131 .has_overlay = 1, .overlay_needs_physical = 1,
132 .supports_tv = 1,
133 .has_fbc = 1,
134 .hws_needs_physical = 1,
135 .unfenced_needs_alignment = 1,
136};
137
138static const struct intel_device_info intel_i945g_info = {
139 GEN3_FEATURES,
140 PLATFORM(INTEL_I945G),
141 .has_hotplug = 1, .cursor_needs_physical = 1,
142 .has_overlay = 1, .overlay_needs_physical = 1,
143 .hws_needs_physical = 1,
144 .unfenced_needs_alignment = 1,
145};
146
147static const struct intel_device_info intel_i945gm_info = {
148 GEN3_FEATURES,
149 PLATFORM(INTEL_I945GM),
150 .is_mobile = 1,
151 .has_hotplug = 1, .cursor_needs_physical = 1,
152 .has_overlay = 1, .overlay_needs_physical = 1,
153 .supports_tv = 1,
154 .has_fbc = 1,
155 .hws_needs_physical = 1,
156 .unfenced_needs_alignment = 1,
157};
158
159static const struct intel_device_info intel_g33_info = {
160 GEN3_FEATURES,
161 PLATFORM(INTEL_G33),
162 .has_hotplug = 1,
163 .has_overlay = 1,
164};
165
166static const struct intel_device_info intel_pineview_info = {
167 GEN3_FEATURES,
168 PLATFORM(INTEL_PINEVIEW),
169 .is_mobile = 1,
170 .has_hotplug = 1,
171 .has_overlay = 1,
172};
173
174#define GEN4_FEATURES \
175 GEN(4), \
176 .num_pipes = 2, \
177 .has_hotplug = 1, \
178 .has_gmch_display = 1, \
179 .ring_mask = RENDER_RING, \
180 .has_snoop = true, \
181 GEN_DEFAULT_PIPEOFFSETS, \
182 GEN_DEFAULT_PAGE_SIZES, \
183 CURSOR_OFFSETS
184
185static const struct intel_device_info intel_i965g_info = {
186 GEN4_FEATURES,
187 PLATFORM(INTEL_I965G),
188 .has_overlay = 1,
189 .hws_needs_physical = 1,
190 .has_snoop = false,
191};
192
193static const struct intel_device_info intel_i965gm_info = {
194 GEN4_FEATURES,
195 PLATFORM(INTEL_I965GM),
196 .is_mobile = 1, .has_fbc = 1,
197 .has_overlay = 1,
198 .supports_tv = 1,
199 .hws_needs_physical = 1,
200 .has_snoop = false,
201};
202
203static const struct intel_device_info intel_g45_info = {
204 GEN4_FEATURES,
205 PLATFORM(INTEL_G45),
206 .ring_mask = RENDER_RING | BSD_RING,
207};
208
209static const struct intel_device_info intel_gm45_info = {
210 GEN4_FEATURES,
211 PLATFORM(INTEL_GM45),
212 .is_mobile = 1, .has_fbc = 1,
213 .supports_tv = 1,
214 .ring_mask = RENDER_RING | BSD_RING,
215};
216
217#define GEN5_FEATURES \
218 GEN(5), \
219 .num_pipes = 2, \
220 .has_hotplug = 1, \
221 .ring_mask = RENDER_RING | BSD_RING, \
222 .has_snoop = true, \
223 /* ilk does support rc6, but we do not implement [power] contexts */ \
224 .has_rc6 = 0, \
225 GEN_DEFAULT_PIPEOFFSETS, \
226 GEN_DEFAULT_PAGE_SIZES, \
227 CURSOR_OFFSETS
228
229static const struct intel_device_info intel_ironlake_d_info = {
230 GEN5_FEATURES,
231 PLATFORM(INTEL_IRONLAKE),
232};
233
234static const struct intel_device_info intel_ironlake_m_info = {
235 GEN5_FEATURES,
236 PLATFORM(INTEL_IRONLAKE),
237 .is_mobile = 1, .has_fbc = 1,
238};
239
240#define GEN6_FEATURES \
241 GEN(6), \
242 .num_pipes = 2, \
243 .has_hotplug = 1, \
244 .has_fbc = 1, \
245 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
246 .has_llc = 1, \
247 .has_rc6 = 1, \
248 .has_rc6p = 1, \
249 .has_aliasing_ppgtt = 1, \
250 GEN_DEFAULT_PIPEOFFSETS, \
251 GEN_DEFAULT_PAGE_SIZES, \
252 CURSOR_OFFSETS
253
254#define SNB_D_PLATFORM \
255 GEN6_FEATURES, \
256 PLATFORM(INTEL_SANDYBRIDGE)
257
258static const struct intel_device_info intel_sandybridge_d_gt1_info = {
259 SNB_D_PLATFORM,
260 .gt = 1,
261};
262
263static const struct intel_device_info intel_sandybridge_d_gt2_info = {
264 SNB_D_PLATFORM,
265 .gt = 2,
266};
267
268#define SNB_M_PLATFORM \
269 GEN6_FEATURES, \
270 PLATFORM(INTEL_SANDYBRIDGE), \
271 .is_mobile = 1
272
273
274static const struct intel_device_info intel_sandybridge_m_gt1_info = {
275 SNB_M_PLATFORM,
276 .gt = 1,
277};
278
279static const struct intel_device_info intel_sandybridge_m_gt2_info = {
280 SNB_M_PLATFORM,
281 .gt = 2,
282};
283
284#define GEN7_FEATURES \
285 GEN(7), \
286 .num_pipes = 3, \
287 .has_hotplug = 1, \
288 .has_fbc = 1, \
289 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
290 .has_llc = 1, \
291 .has_rc6 = 1, \
292 .has_rc6p = 1, \
293 .has_aliasing_ppgtt = 1, \
294 .has_full_ppgtt = 1, \
295 GEN_DEFAULT_PIPEOFFSETS, \
296 GEN_DEFAULT_PAGE_SIZES, \
297 IVB_CURSOR_OFFSETS
298
299#define IVB_D_PLATFORM \
300 GEN7_FEATURES, \
301 PLATFORM(INTEL_IVYBRIDGE), \
302 .has_l3_dpf = 1
303
304static const struct intel_device_info intel_ivybridge_d_gt1_info = {
305 IVB_D_PLATFORM,
306 .gt = 1,
307};
308
309static const struct intel_device_info intel_ivybridge_d_gt2_info = {
310 IVB_D_PLATFORM,
311 .gt = 2,
312};
313
314#define IVB_M_PLATFORM \
315 GEN7_FEATURES, \
316 PLATFORM(INTEL_IVYBRIDGE), \
317 .is_mobile = 1, \
318 .has_l3_dpf = 1
319
320static const struct intel_device_info intel_ivybridge_m_gt1_info = {
321 IVB_M_PLATFORM,
322 .gt = 1,
323};
324
325static const struct intel_device_info intel_ivybridge_m_gt2_info = {
326 IVB_M_PLATFORM,
327 .gt = 2,
328};
329
330static const struct intel_device_info intel_ivybridge_q_info = {
331 GEN7_FEATURES,
332 PLATFORM(INTEL_IVYBRIDGE),
333 .gt = 2,
334 .num_pipes = 0, /* legal, last one wins */
335 .has_l3_dpf = 1,
336};
337
338static const struct intel_device_info intel_valleyview_info = {
339 PLATFORM(INTEL_VALLEYVIEW),
340 GEN(7),
341 .is_lp = 1,
342 .num_pipes = 2,
343 .has_psr = 1,
344 .has_runtime_pm = 1,
345 .has_rc6 = 1,
346 .has_gmch_display = 1,
347 .has_hotplug = 1,
348 .has_aliasing_ppgtt = 1,
349 .has_full_ppgtt = 1,
350 .has_snoop = true,
351 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
352 .display_mmio_offset = VLV_DISPLAY_BASE,
353 GEN_DEFAULT_PAGE_SIZES,
354 GEN_DEFAULT_PIPEOFFSETS,
355 CURSOR_OFFSETS
356};
357
358#define G75_FEATURES \
359 GEN7_FEATURES, \
360 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
361 .has_ddi = 1, \
362 .has_fpga_dbg = 1, \
363 .has_psr = 1, \
364 .has_resource_streamer = 1, \
365 .has_dp_mst = 1, \
366 .has_rc6p = 0 /* RC6p removed-by HSW */, \
367 .has_runtime_pm = 1
368
369#define HSW_PLATFORM \
370 G75_FEATURES, \
371 PLATFORM(INTEL_HASWELL), \
372 .has_l3_dpf = 1
373
374static const struct intel_device_info intel_haswell_gt1_info = {
375 HSW_PLATFORM,
376 .gt = 1,
377};
378
379static const struct intel_device_info intel_haswell_gt2_info = {
380 HSW_PLATFORM,
381 .gt = 2,
382};
383
384static const struct intel_device_info intel_haswell_gt3_info = {
385 HSW_PLATFORM,
386 .gt = 3,
387};
388
389#define GEN8_FEATURES \
390 G75_FEATURES, \
391 GEN(8), \
392 BDW_COLORS, \
393 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
394 I915_GTT_PAGE_SIZE_2M, \
395 .has_logical_ring_contexts = 1, \
396 .has_full_48bit_ppgtt = 1, \
397 .has_64bit_reloc = 1, \
398 .has_reset_engine = 1
399
400#define BDW_PLATFORM \
401 GEN8_FEATURES, \
402 PLATFORM(INTEL_BROADWELL)
403
404static const struct intel_device_info intel_broadwell_gt1_info = {
405 BDW_PLATFORM,
406 .gt = 1,
407};
408
409static const struct intel_device_info intel_broadwell_gt2_info = {
410 BDW_PLATFORM,
411 .gt = 2,
412};
413
414static const struct intel_device_info intel_broadwell_rsvd_info = {
415 BDW_PLATFORM,
416 .gt = 3,
417 /* According to the device ID those devices are GT3, they were
418 * previously treated as not GT3, keep it like that.
419 */
420};
421
422static const struct intel_device_info intel_broadwell_gt3_info = {
423 BDW_PLATFORM,
424 .gt = 3,
425 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
426};
427
428static const struct intel_device_info intel_cherryview_info = {
429 PLATFORM(INTEL_CHERRYVIEW),
430 GEN(8),
431 .num_pipes = 3,
432 .has_hotplug = 1,
433 .is_lp = 1,
434 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
435 .has_64bit_reloc = 1,
436 .has_psr = 1,
437 .has_runtime_pm = 1,
438 .has_resource_streamer = 1,
439 .has_rc6 = 1,
440 .has_logical_ring_contexts = 1,
441 .has_gmch_display = 1,
442 .has_aliasing_ppgtt = 1,
443 .has_full_ppgtt = 1,
444 .has_reset_engine = 1,
445 .has_snoop = true,
446 .display_mmio_offset = VLV_DISPLAY_BASE,
447 GEN_DEFAULT_PAGE_SIZES,
448 GEN_CHV_PIPEOFFSETS,
449 CURSOR_OFFSETS,
450 CHV_COLORS,
451};
452
453#define GEN9_DEFAULT_PAGE_SIZES \
454 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
455 I915_GTT_PAGE_SIZE_64K | \
456 I915_GTT_PAGE_SIZE_2M
457
458#define GEN9_FEATURES \
459 GEN8_FEATURES, \
460 GEN(9), \
461 GEN9_DEFAULT_PAGE_SIZES, \
462 .has_logical_ring_preemption = 1, \
463 .has_csr = 1, \
464 .has_guc = 1, \
465 .has_ipc = 1, \
466 .ddb_size = 896
467
468#define SKL_PLATFORM \
469 GEN9_FEATURES, \
470 PLATFORM(INTEL_SKYLAKE)
471
472static const struct intel_device_info intel_skylake_gt1_info = {
473 SKL_PLATFORM,
474 .gt = 1,
475};
476
477static const struct intel_device_info intel_skylake_gt2_info = {
478 SKL_PLATFORM,
479 .gt = 2,
480};
481
482#define SKL_GT3_PLUS_PLATFORM \
483 SKL_PLATFORM, \
484 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
485
486
487static const struct intel_device_info intel_skylake_gt3_info = {
488 SKL_GT3_PLUS_PLATFORM,
489 .gt = 3,
490};
491
492static const struct intel_device_info intel_skylake_gt4_info = {
493 SKL_GT3_PLUS_PLATFORM,
494 .gt = 4,
495};
496
497#define GEN9_LP_FEATURES \
498 GEN(9), \
499 .is_lp = 1, \
500 .has_hotplug = 1, \
501 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
502 .num_pipes = 3, \
503 .has_64bit_reloc = 1, \
504 .has_ddi = 1, \
505 .has_fpga_dbg = 1, \
506 .has_fbc = 1, \
507 .has_psr = 1, \
508 .has_runtime_pm = 1, \
509 .has_pooled_eu = 0, \
510 .has_csr = 1, \
511 .has_resource_streamer = 1, \
512 .has_rc6 = 1, \
513 .has_dp_mst = 1, \
514 .has_logical_ring_contexts = 1, \
515 .has_logical_ring_preemption = 1, \
516 .has_guc = 1, \
517 .has_aliasing_ppgtt = 1, \
518 .has_full_ppgtt = 1, \
519 .has_full_48bit_ppgtt = 1, \
520 .has_reset_engine = 1, \
521 .has_snoop = true, \
522 .has_ipc = 1, \
523 GEN9_DEFAULT_PAGE_SIZES, \
524 GEN_DEFAULT_PIPEOFFSETS, \
525 IVB_CURSOR_OFFSETS, \
526 BDW_COLORS
527
528static const struct intel_device_info intel_broxton_info = {
529 GEN9_LP_FEATURES,
530 PLATFORM(INTEL_BROXTON),
531 .ddb_size = 512,
532};
533
534static const struct intel_device_info intel_geminilake_info = {
535 GEN9_LP_FEATURES,
536 PLATFORM(INTEL_GEMINILAKE),
537 .ddb_size = 1024,
538 GLK_COLORS,
539};
540
541#define KBL_PLATFORM \
542 GEN9_FEATURES, \
543 PLATFORM(INTEL_KABYLAKE)
544
545static const struct intel_device_info intel_kabylake_gt1_info = {
546 KBL_PLATFORM,
547 .gt = 1,
548};
549
550static const struct intel_device_info intel_kabylake_gt2_info = {
551 KBL_PLATFORM,
552 .gt = 2,
553};
554
555static const struct intel_device_info intel_kabylake_gt3_info = {
556 KBL_PLATFORM,
557 .gt = 3,
558 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
559};
560
561#define CFL_PLATFORM \
562 GEN9_FEATURES, \
563 PLATFORM(INTEL_COFFEELAKE)
564
565static const struct intel_device_info intel_coffeelake_gt1_info = {
566 CFL_PLATFORM,
567 .gt = 1,
568};
569
570static const struct intel_device_info intel_coffeelake_gt2_info = {
571 CFL_PLATFORM,
572 .gt = 2,
573};
574
575static const struct intel_device_info intel_coffeelake_gt3_info = {
576 CFL_PLATFORM,
577 .gt = 3,
578 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
579};
580
581#define GEN10_FEATURES \
582 GEN9_FEATURES, \
583 GEN(10), \
584 .ddb_size = 1024, \
585 GLK_COLORS
586
587static const struct intel_device_info intel_cannonlake_info = {
588 GEN10_FEATURES,
589 PLATFORM(INTEL_CANNONLAKE),
590 .gt = 2,
591};
592
593#define GEN11_FEATURES \
594 GEN10_FEATURES, \
595 GEN(11), \
596 .ddb_size = 2048, \
597 .has_csr = 0, \
598 .has_logical_ring_elsq = 1
599
600static const struct intel_device_info intel_icelake_11_info = {
601 GEN11_FEATURES,
602 PLATFORM(INTEL_ICELAKE),
603 .is_alpha_support = 1,
604 .has_resource_streamer = 0,
605};
606
607#undef GEN
608#undef PLATFORM
609
610/*
611 * Make sure any device matches here are from most specific to most
612 * general. For example, since the Quanta match is based on the subsystem
613 * and subvendor IDs, we need it to come before the more general IVB
614 * PCI ID matches, otherwise we'll use the wrong info struct above.
615 */
616static const struct pci_device_id pciidlist[] = {
617 INTEL_I830_IDS(&intel_i830_info),
618 INTEL_I845G_IDS(&intel_i845g_info),
619 INTEL_I85X_IDS(&intel_i85x_info),
620 INTEL_I865G_IDS(&intel_i865g_info),
621 INTEL_I915G_IDS(&intel_i915g_info),
622 INTEL_I915GM_IDS(&intel_i915gm_info),
623 INTEL_I945G_IDS(&intel_i945g_info),
624 INTEL_I945GM_IDS(&intel_i945gm_info),
625 INTEL_I965G_IDS(&intel_i965g_info),
626 INTEL_G33_IDS(&intel_g33_info),
627 INTEL_I965GM_IDS(&intel_i965gm_info),
628 INTEL_GM45_IDS(&intel_gm45_info),
629 INTEL_G45_IDS(&intel_g45_info),
630 INTEL_PINEVIEW_IDS(&intel_pineview_info),
631 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
632 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
633 INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
634 INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
635 INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
636 INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
637 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
638 INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
639 INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
640 INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
641 INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
642 INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
643 INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
644 INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
645 INTEL_VLV_IDS(&intel_valleyview_info),
646 INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
647 INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
648 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
649 INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
650 INTEL_CHV_IDS(&intel_cherryview_info),
651 INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
652 INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
653 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
654 INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
655 INTEL_BXT_IDS(&intel_broxton_info),
656 INTEL_GLK_IDS(&intel_geminilake_info),
657 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
658 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
659 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
660 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
661 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
662 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
663 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
664 INTEL_CFL_U_GT1_IDS(&intel_coffeelake_gt1_info),
665 INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
666 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
667 INTEL_CNL_IDS(&intel_cannonlake_info),
668 INTEL_ICL_11_IDS(&intel_icelake_11_info),
669 {0, 0, 0}
670};
671MODULE_DEVICE_TABLE(pci, pciidlist);
672
673static void i915_pci_remove(struct pci_dev *pdev)
674{
675 struct drm_device *dev = pci_get_drvdata(pdev);
676
677 i915_driver_unload(dev);
678 drm_dev_put(dev);
679}
680
681static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
682{
683 struct intel_device_info *intel_info =
684 (struct intel_device_info *) ent->driver_data;
685 int err;
686
687 if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) {
688 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
689 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
690 "to enable support in this kernel version, or check for kernel updates.\n");
691 return -ENODEV;
692 }
693
694 /* Only bind to function 0 of the device. Early generations
695 * used function 1 as a placeholder for multi-head. This causes
696 * us confusion instead, especially on the systems where both
697 * functions have the same PCI-ID!
698 */
699 if (PCI_FUNC(pdev->devfn))
700 return -ENODEV;
701
702 /*
703 * apple-gmux is needed on dual GPU MacBook Pro
704 * to probe the panel if we're the inactive GPU.
705 */
706 if (vga_switcheroo_client_probe_defer(pdev))
707 return -EPROBE_DEFER;
708
709 err = i915_driver_load(pdev, ent);
710 if (err)
711 return err;
712
713 err = i915_live_selftests(pdev);
714 if (err) {
715 i915_pci_remove(pdev);
716 return err > 0 ? -ENOTTY : err;
717 }
718
719 return 0;
720}
721
722static struct pci_driver i915_pci_driver = {
723 .name = DRIVER_NAME,
724 .id_table = pciidlist,
725 .probe = i915_pci_probe,
726 .remove = i915_pci_remove,
727 .driver.pm = &i915_pm_ops,
728};
729
730static int __init i915_init(void)
731{
732 bool use_kms = true;
733 int err;
734
735 err = i915_mock_selftests();
736 if (err)
737 return err > 0 ? 0 : err;
738
739 /*
740 * Enable KMS by default, unless explicitly overriden by
741 * either the i915.modeset prarameter or by the
742 * vga_text_mode_force boot option.
743 */
744
745 if (i915_modparams.modeset == 0)
746 use_kms = false;
747
748 if (vgacon_text_force() && i915_modparams.modeset == -1)
749 use_kms = false;
750
751 if (!use_kms) {
752 /* Silently fail loading to not upset userspace. */
753 DRM_DEBUG_DRIVER("KMS disabled.\n");
754 return 0;
755 }
756
757 return pci_register_driver(&i915_pci_driver);
758}
759
760static void __exit i915_exit(void)
761{
762 if (!i915_pci_driver.driver.owner)
763 return;
764
765 pci_unregister_driver(&i915_pci_driver);
766}
767
768module_init(i915_init);
769module_exit(i915_exit);
770
771MODULE_AUTHOR("Tungsten Graphics, Inc.");
772MODULE_AUTHOR("Intel Corporation");
773
774MODULE_DESCRIPTION(DRIVER_DESC);
775MODULE_LICENSE("GPL and additional rights");