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1// SPDX-License-Identifier: GPL-2.0
2//
3// sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
4//
5// Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
6
7#include <linux/module.h>
8#include <linux/moduleparam.h>
9#include <linux/init.h>
10#include <linux/delay.h>
11#include <linux/slab.h>
12#include <linux/pm.h>
13#include <linux/i2c.h>
14#include <linux/clk.h>
15#include <linux/log2.h>
16#include <linux/of.h>
17#include <linux/regmap.h>
18#include <linux/regulator/driver.h>
19#include <linux/regulator/machine.h>
20#include <linux/regulator/consumer.h>
21#include <sound/core.h>
22#include <sound/tlv.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28
29#include "sgtl5000.h"
30
31#define SGTL5000_DAP_REG_OFFSET 0x0100
32#define SGTL5000_MAX_REG_OFFSET 0x013A
33
34/* Delay for the VAG ramp up */
35#define SGTL5000_VAG_POWERUP_DELAY 500 /* ms */
36/* Delay for the VAG ramp down */
37#define SGTL5000_VAG_POWERDOWN_DELAY 500 /* ms */
38
39#define SGTL5000_OUTPUTS_MUTE (SGTL5000_HP_MUTE | SGTL5000_LINE_OUT_MUTE)
40
41/* default value of sgtl5000 registers */
42static const struct reg_default sgtl5000_reg_defaults[] = {
43 { SGTL5000_CHIP_DIG_POWER, 0x0000 },
44 { SGTL5000_CHIP_I2S_CTRL, 0x0010 },
45 { SGTL5000_CHIP_SSS_CTRL, 0x0010 },
46 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c },
47 { SGTL5000_CHIP_DAC_VOL, 0x3c3c },
48 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
49 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 },
50 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
51 { SGTL5000_CHIP_ANA_CTRL, 0x0111 },
52 { SGTL5000_CHIP_REF_CTRL, 0x0000 },
53 { SGTL5000_CHIP_MIC_CTRL, 0x0000 },
54 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 },
55 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
56 { SGTL5000_CHIP_PLL_CTRL, 0x5000 },
57 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 },
58 { SGTL5000_CHIP_ANA_STATUS, 0x0000 },
59 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 },
60 { SGTL5000_CHIP_ANA_TEST2, 0x0000 },
61 { SGTL5000_DAP_CTRL, 0x0000 },
62 { SGTL5000_DAP_PEQ, 0x0000 },
63 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
64 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
65 { SGTL5000_DAP_AUDIO_EQ, 0x0000 },
66 { SGTL5000_DAP_SURROUND, 0x0040 },
67 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
68 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
69 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f },
70 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
71 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
72 { SGTL5000_DAP_MAIN_CHAN, 0x8000 },
73 { SGTL5000_DAP_MIX_CHAN, 0x0000 },
74 { SGTL5000_DAP_AVC_CTRL, 0x5100 },
75 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
76 { SGTL5000_DAP_AVC_ATTACK, 0x0028 },
77 { SGTL5000_DAP_AVC_DECAY, 0x0050 },
78};
79
80/* AVC: Threshold dB -> register: pre-calculated values */
81static const u16 avc_thr_db2reg[97] = {
82 0x5168, 0x488E, 0x40AA, 0x39A1, 0x335D, 0x2DC7, 0x28CC, 0x245D, 0x2068,
83 0x1CE2, 0x19BE, 0x16F1, 0x1472, 0x1239, 0x103E, 0x0E7A, 0x0CE6, 0x0B7F,
84 0x0A3F, 0x0922, 0x0824, 0x0741, 0x0677, 0x05C3, 0x0522, 0x0493, 0x0414,
85 0x03A2, 0x033D, 0x02E3, 0x0293, 0x024B, 0x020B, 0x01D2, 0x019F, 0x0172,
86 0x014A, 0x0126, 0x0106, 0x00E9, 0x00D0, 0x00B9, 0x00A5, 0x0093, 0x0083,
87 0x0075, 0x0068, 0x005D, 0x0052, 0x0049, 0x0041, 0x003A, 0x0034, 0x002E,
88 0x0029, 0x0025, 0x0021, 0x001D, 0x001A, 0x0017, 0x0014, 0x0012, 0x0010,
89 0x000E, 0x000D, 0x000B, 0x000A, 0x0009, 0x0008, 0x0007, 0x0006, 0x0005,
90 0x0005, 0x0004, 0x0004, 0x0003, 0x0003, 0x0002, 0x0002, 0x0002, 0x0002,
91 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0000, 0x0000, 0x0000,
92 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000};
93
94/* regulator supplies for sgtl5000, VDDD is an optional external supply */
95enum sgtl5000_regulator_supplies {
96 VDDA,
97 VDDIO,
98 VDDD,
99 SGTL5000_SUPPLY_NUM
100};
101
102/* vddd is optional supply */
103static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
104 "VDDA",
105 "VDDIO",
106 "VDDD"
107};
108
109#define LDO_VOLTAGE 1200000
110#define LINREG_VDDD ((1600 - LDO_VOLTAGE / 1000) / 50)
111
112enum sgtl5000_micbias_resistor {
113 SGTL5000_MICBIAS_OFF = 0,
114 SGTL5000_MICBIAS_2K = 2,
115 SGTL5000_MICBIAS_4K = 4,
116 SGTL5000_MICBIAS_8K = 8,
117};
118
119enum {
120 I2S_LRCLK_STRENGTH_DISABLE,
121 I2S_LRCLK_STRENGTH_LOW,
122 I2S_LRCLK_STRENGTH_MEDIUM,
123 I2S_LRCLK_STRENGTH_HIGH,
124};
125
126enum {
127 I2S_SCLK_STRENGTH_DISABLE,
128 I2S_SCLK_STRENGTH_LOW,
129 I2S_SCLK_STRENGTH_MEDIUM,
130 I2S_SCLK_STRENGTH_HIGH,
131};
132
133enum {
134 HP_POWER_EVENT,
135 DAC_POWER_EVENT,
136 ADC_POWER_EVENT,
137 LAST_POWER_EVENT = ADC_POWER_EVENT
138};
139
140/* sgtl5000 private structure in codec */
141struct sgtl5000_priv {
142 int sysclk; /* sysclk rate */
143 int master; /* i2s master or not */
144 int fmt; /* i2s data format */
145 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
146 int num_supplies;
147 struct regmap *regmap;
148 struct clk *mclk;
149 int revision;
150 u8 micbias_resistor;
151 u8 micbias_voltage;
152 u8 lrclk_strength;
153 u8 sclk_strength;
154 u16 mute_state[LAST_POWER_EVENT + 1];
155};
156
157static inline int hp_sel_input(struct snd_soc_component *component)
158{
159 return (snd_soc_component_read(component, SGTL5000_CHIP_ANA_CTRL) &
160 SGTL5000_HP_SEL_MASK) >> SGTL5000_HP_SEL_SHIFT;
161}
162
163static inline u16 mute_output(struct snd_soc_component *component,
164 u16 mute_mask)
165{
166 u16 mute_reg = snd_soc_component_read(component,
167 SGTL5000_CHIP_ANA_CTRL);
168
169 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL,
170 mute_mask, mute_mask);
171 return mute_reg;
172}
173
174static inline void restore_output(struct snd_soc_component *component,
175 u16 mute_mask, u16 mute_reg)
176{
177 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL,
178 mute_mask, mute_reg);
179}
180
181static void vag_power_on(struct snd_soc_component *component, u32 source)
182{
183 if (snd_soc_component_read(component, SGTL5000_CHIP_ANA_POWER) &
184 SGTL5000_VAG_POWERUP)
185 return;
186
187 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
188 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
189
190 /* When VAG powering on to get local loop from Line-In, the sleep
191 * is required to avoid loud pop.
192 */
193 if (hp_sel_input(component) == SGTL5000_HP_SEL_LINE_IN &&
194 source == HP_POWER_EVENT)
195 msleep(SGTL5000_VAG_POWERUP_DELAY);
196}
197
198static int vag_power_consumers(struct snd_soc_component *component,
199 u16 ana_pwr_reg, u32 source)
200{
201 int consumers = 0;
202
203 /* count dac/adc consumers unconditional */
204 if (ana_pwr_reg & SGTL5000_DAC_POWERUP)
205 consumers++;
206 if (ana_pwr_reg & SGTL5000_ADC_POWERUP)
207 consumers++;
208
209 /*
210 * If the event comes from HP and Line-In is selected,
211 * current action is 'DAC to be powered down'.
212 * As HP_POWERUP is not set when HP muxed to line-in,
213 * we need to keep VAG power ON.
214 */
215 if (source == HP_POWER_EVENT) {
216 if (hp_sel_input(component) == SGTL5000_HP_SEL_LINE_IN)
217 consumers++;
218 } else {
219 if (ana_pwr_reg & SGTL5000_HP_POWERUP)
220 consumers++;
221 }
222
223 return consumers;
224}
225
226static void vag_power_off(struct snd_soc_component *component, u32 source)
227{
228 u16 ana_pwr = snd_soc_component_read(component,
229 SGTL5000_CHIP_ANA_POWER);
230
231 if (!(ana_pwr & SGTL5000_VAG_POWERUP))
232 return;
233
234 /*
235 * This function calls when any of VAG power consumers is disappearing.
236 * Thus, if there is more than one consumer at the moment, as minimum
237 * one consumer will definitely stay after the end of the current
238 * event.
239 * Don't clear VAG_POWERUP if 2 or more consumers of VAG present:
240 * - LINE_IN (for HP events) / HP (for DAC/ADC events)
241 * - DAC
242 * - ADC
243 * (the current consumer is disappearing right now)
244 */
245 if (vag_power_consumers(component, ana_pwr, source) >= 2)
246 return;
247
248 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
249 SGTL5000_VAG_POWERUP, 0);
250 /* In power down case, we need wait 400-1000 ms
251 * when VAG fully ramped down.
252 * As longer we wait, as smaller pop we've got.
253 */
254 msleep(SGTL5000_VAG_POWERDOWN_DELAY);
255}
256
257/*
258 * mic_bias power on/off share the same register bits with
259 * output impedance of mic bias, when power on mic bias, we
260 * need reclaim it to impedance value.
261 * 0x0 = Powered off
262 * 0x1 = 2Kohm
263 * 0x2 = 4Kohm
264 * 0x3 = 8Kohm
265 */
266static int mic_bias_event(struct snd_soc_dapm_widget *w,
267 struct snd_kcontrol *kcontrol, int event)
268{
269 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
270 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
271
272 switch (event) {
273 case SND_SOC_DAPM_POST_PMU:
274 /* change mic bias resistor */
275 snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
276 SGTL5000_BIAS_R_MASK,
277 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
278 break;
279
280 case SND_SOC_DAPM_PRE_PMD:
281 snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
282 SGTL5000_BIAS_R_MASK, 0);
283 break;
284 }
285 return 0;
286}
287
288static int vag_and_mute_control(struct snd_soc_component *component,
289 int event, int event_source)
290{
291 static const u16 mute_mask[] = {
292 /*
293 * Mask for HP_POWER_EVENT.
294 * Muxing Headphones have to be wrapped with mute/unmute
295 * headphones only.
296 */
297 SGTL5000_HP_MUTE,
298 /*
299 * Masks for DAC_POWER_EVENT/ADC_POWER_EVENT.
300 * Muxing DAC or ADC block have to wrapped with mute/unmute
301 * both headphones and line-out.
302 */
303 SGTL5000_OUTPUTS_MUTE,
304 SGTL5000_OUTPUTS_MUTE
305 };
306
307 struct sgtl5000_priv *sgtl5000 =
308 snd_soc_component_get_drvdata(component);
309
310 switch (event) {
311 case SND_SOC_DAPM_PRE_PMU:
312 sgtl5000->mute_state[event_source] =
313 mute_output(component, mute_mask[event_source]);
314 break;
315 case SND_SOC_DAPM_POST_PMU:
316 vag_power_on(component, event_source);
317 restore_output(component, mute_mask[event_source],
318 sgtl5000->mute_state[event_source]);
319 break;
320 case SND_SOC_DAPM_PRE_PMD:
321 sgtl5000->mute_state[event_source] =
322 mute_output(component, mute_mask[event_source]);
323 vag_power_off(component, event_source);
324 break;
325 case SND_SOC_DAPM_POST_PMD:
326 restore_output(component, mute_mask[event_source],
327 sgtl5000->mute_state[event_source]);
328 break;
329 default:
330 break;
331 }
332
333 return 0;
334}
335
336/*
337 * Mute Headphone when power it up/down.
338 * Control VAG power on HP power path.
339 */
340static int headphone_pga_event(struct snd_soc_dapm_widget *w,
341 struct snd_kcontrol *kcontrol, int event)
342{
343 struct snd_soc_component *component =
344 snd_soc_dapm_to_component(w->dapm);
345
346 return vag_and_mute_control(component, event, HP_POWER_EVENT);
347}
348
349/* As manual describes, ADC/DAC powering up/down requires
350 * to mute outputs to avoid pops.
351 * Control VAG power on ADC/DAC power path.
352 */
353static int adc_updown_depop(struct snd_soc_dapm_widget *w,
354 struct snd_kcontrol *kcontrol, int event)
355{
356 struct snd_soc_component *component =
357 snd_soc_dapm_to_component(w->dapm);
358
359 return vag_and_mute_control(component, event, ADC_POWER_EVENT);
360}
361
362static int dac_updown_depop(struct snd_soc_dapm_widget *w,
363 struct snd_kcontrol *kcontrol, int event)
364{
365 struct snd_soc_component *component =
366 snd_soc_dapm_to_component(w->dapm);
367
368 return vag_and_mute_control(component, event, DAC_POWER_EVENT);
369}
370
371/* input sources for ADC */
372static const char *adc_mux_text[] = {
373 "MIC_IN", "LINE_IN"
374};
375
376static SOC_ENUM_SINGLE_DECL(adc_enum,
377 SGTL5000_CHIP_ANA_CTRL, 2,
378 adc_mux_text);
379
380static const struct snd_kcontrol_new adc_mux =
381SOC_DAPM_ENUM("Capture Mux", adc_enum);
382
383/* input sources for headphone */
384static const char *hp_mux_text[] = {
385 "DAC", "LINE_IN"
386};
387
388static SOC_ENUM_SINGLE_DECL(hp_enum,
389 SGTL5000_CHIP_ANA_CTRL, 6,
390 hp_mux_text);
391
392static const struct snd_kcontrol_new hp_mux =
393SOC_DAPM_ENUM("Headphone Mux", hp_enum);
394
395/* input sources for DAC */
396static const char *dac_mux_text[] = {
397 "ADC", "I2S", "Rsvrd", "DAP"
398};
399
400static SOC_ENUM_SINGLE_DECL(dac_enum,
401 SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAC_SEL_SHIFT,
402 dac_mux_text);
403
404static const struct snd_kcontrol_new dac_mux =
405SOC_DAPM_ENUM("Digital Input Mux", dac_enum);
406
407/* input sources for DAP */
408static const char *dap_mux_text[] = {
409 "ADC", "I2S"
410};
411
412static SOC_ENUM_SINGLE_DECL(dap_enum,
413 SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAP_SEL_SHIFT,
414 dap_mux_text);
415
416static const struct snd_kcontrol_new dap_mux =
417SOC_DAPM_ENUM("DAP Mux", dap_enum);
418
419/* input sources for DAP mix */
420static const char *dapmix_mux_text[] = {
421 "ADC", "I2S"
422};
423
424static SOC_ENUM_SINGLE_DECL(dapmix_enum,
425 SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAP_MIX_SEL_SHIFT,
426 dapmix_mux_text);
427
428static const struct snd_kcontrol_new dapmix_mux =
429SOC_DAPM_ENUM("DAP MIX Mux", dapmix_enum);
430
431
432static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
433 SND_SOC_DAPM_INPUT("LINE_IN"),
434 SND_SOC_DAPM_INPUT("MIC_IN"),
435
436 SND_SOC_DAPM_OUTPUT("HP_OUT"),
437 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
438
439 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
440 mic_bias_event,
441 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
442
443 SND_SOC_DAPM_PGA_E("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0,
444 headphone_pga_event,
445 SND_SOC_DAPM_PRE_POST_PMU |
446 SND_SOC_DAPM_PRE_POST_PMD),
447 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
448
449 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
450 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &hp_mux),
451 SND_SOC_DAPM_MUX("Digital Input Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
452 SND_SOC_DAPM_MUX("DAP Mux", SGTL5000_DAP_CTRL, 0, 0, &dap_mux),
453 SND_SOC_DAPM_MUX("DAP MIX Mux", SGTL5000_DAP_CTRL, 4, 0, &dapmix_mux),
454 SND_SOC_DAPM_MIXER("DAP", SGTL5000_CHIP_DIG_POWER, 4, 0, NULL, 0),
455
456
457 /* aif for i2s input */
458 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
459 0, SGTL5000_CHIP_DIG_POWER,
460 0, 0),
461
462 /* aif for i2s output */
463 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
464 0, SGTL5000_CHIP_DIG_POWER,
465 1, 0),
466
467 SND_SOC_DAPM_ADC_E("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0,
468 adc_updown_depop, SND_SOC_DAPM_PRE_POST_PMU |
469 SND_SOC_DAPM_PRE_POST_PMD),
470 SND_SOC_DAPM_DAC_E("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0,
471 dac_updown_depop, SND_SOC_DAPM_PRE_POST_PMU |
472 SND_SOC_DAPM_PRE_POST_PMD),
473};
474
475/* routes for sgtl5000 */
476static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
477 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
478 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
479
480 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
481 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
482
483 {"DAP Mux", "ADC", "ADC"}, /* adc --> DAP mux */
484 {"DAP Mux", NULL, "AIFIN"}, /* i2s --> DAP mux */
485 {"DAP", NULL, "DAP Mux"}, /* DAP mux --> dap */
486
487 {"DAP MIX Mux", "ADC", "ADC"}, /* adc --> DAP MIX mux */
488 {"DAP MIX Mux", NULL, "AIFIN"}, /* i2s --> DAP MIX mux */
489 {"DAP", NULL, "DAP MIX Mux"}, /* DAP MIX mux --> dap */
490
491 {"Digital Input Mux", "ADC", "ADC"}, /* adc --> audio mux */
492 {"Digital Input Mux", NULL, "AIFIN"}, /* i2s --> audio mux */
493 {"Digital Input Mux", NULL, "DAP"}, /* dap --> audio mux */
494 {"DAC", NULL, "Digital Input Mux"}, /* audio mux --> dac */
495
496 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
497 {"LO", NULL, "DAC"}, /* dac --> line_out */
498
499 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
500 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
501
502 {"LINE_OUT", NULL, "LO"},
503 {"HP_OUT", NULL, "HP"},
504};
505
506/* custom function to fetch info of PCM playback volume */
507static int dac_info_volsw(struct snd_kcontrol *kcontrol,
508 struct snd_ctl_elem_info *uinfo)
509{
510 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
511 uinfo->count = 2;
512 uinfo->value.integer.min = 0;
513 uinfo->value.integer.max = 0xfc - 0x3c;
514 return 0;
515}
516
517/*
518 * custom function to get of PCM playback volume
519 *
520 * dac volume register
521 * 15-------------8-7--------------0
522 * | R channel vol | L channel vol |
523 * -------------------------------
524 *
525 * PCM volume with 0.5017 dB steps from 0 to -90 dB
526 *
527 * register values map to dB
528 * 0x3B and less = Reserved
529 * 0x3C = 0 dB
530 * 0x3D = -0.5 dB
531 * 0xF0 = -90 dB
532 * 0xFC and greater = Muted
533 *
534 * register value map to userspace value
535 *
536 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
537 * ------------------------------
538 * userspace value 0xc0 0
539 */
540static int dac_get_volsw(struct snd_kcontrol *kcontrol,
541 struct snd_ctl_elem_value *ucontrol)
542{
543 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
544 int reg;
545 int l;
546 int r;
547
548 reg = snd_soc_component_read(component, SGTL5000_CHIP_DAC_VOL);
549
550 /* get left channel volume */
551 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
552
553 /* get right channel volume */
554 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
555
556 /* make sure value fall in (0x3c,0xfc) */
557 l = clamp(l, 0x3c, 0xfc);
558 r = clamp(r, 0x3c, 0xfc);
559
560 /* invert it and map to userspace value */
561 l = 0xfc - l;
562 r = 0xfc - r;
563
564 ucontrol->value.integer.value[0] = l;
565 ucontrol->value.integer.value[1] = r;
566
567 return 0;
568}
569
570/*
571 * custom function to put of PCM playback volume
572 *
573 * dac volume register
574 * 15-------------8-7--------------0
575 * | R channel vol | L channel vol |
576 * -------------------------------
577 *
578 * PCM volume with 0.5017 dB steps from 0 to -90 dB
579 *
580 * register values map to dB
581 * 0x3B and less = Reserved
582 * 0x3C = 0 dB
583 * 0x3D = -0.5 dB
584 * 0xF0 = -90 dB
585 * 0xFC and greater = Muted
586 *
587 * userspace value map to register value
588 *
589 * userspace value 0xc0 0
590 * ------------------------------
591 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
592 */
593static int dac_put_volsw(struct snd_kcontrol *kcontrol,
594 struct snd_ctl_elem_value *ucontrol)
595{
596 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
597 int reg;
598 int l;
599 int r;
600
601 l = ucontrol->value.integer.value[0];
602 r = ucontrol->value.integer.value[1];
603
604 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
605 l = clamp(l, 0, 0xfc - 0x3c);
606 r = clamp(r, 0, 0xfc - 0x3c);
607
608 /* invert it, get the value can be set to register */
609 l = 0xfc - l;
610 r = 0xfc - r;
611
612 /* shift to get the register value */
613 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
614 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
615
616 snd_soc_component_write(component, SGTL5000_CHIP_DAC_VOL, reg);
617
618 return 0;
619}
620
621/*
622 * custom function to get AVC threshold
623 *
624 * The threshold dB is calculated by rearranging the calculation from the
625 * avc_put_threshold function: register_value = 10^(dB/20) * 0.636 * 2^15 ==>
626 * dB = ( fls(register_value) - 14.347 ) * 6.02
627 *
628 * As this calculation is expensive and the threshold dB values may not exceed
629 * 0 to 96 we use pre-calculated values.
630 */
631static int avc_get_threshold(struct snd_kcontrol *kcontrol,
632 struct snd_ctl_elem_value *ucontrol)
633{
634 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
635 int db, i;
636 u16 reg = snd_soc_component_read(component, SGTL5000_DAP_AVC_THRESHOLD);
637
638 /* register value 0 => -96dB */
639 if (!reg) {
640 ucontrol->value.integer.value[0] = 96;
641 ucontrol->value.integer.value[1] = 96;
642 return 0;
643 }
644
645 /* get dB from register value (rounded down) */
646 for (i = 0; avc_thr_db2reg[i] > reg; i++)
647 ;
648 db = i;
649
650 ucontrol->value.integer.value[0] = db;
651 ucontrol->value.integer.value[1] = db;
652
653 return 0;
654}
655
656/*
657 * custom function to put AVC threshold
658 *
659 * The register value is calculated by following formula:
660 * register_value = 10^(dB/20) * 0.636 * 2^15
661 * As this calculation is expensive and the threshold dB values may not exceed
662 * 0 to 96 we use pre-calculated values.
663 */
664static int avc_put_threshold(struct snd_kcontrol *kcontrol,
665 struct snd_ctl_elem_value *ucontrol)
666{
667 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
668 int db;
669 u16 reg;
670
671 db = (int)ucontrol->value.integer.value[0];
672 if (db < 0 || db > 96)
673 return -EINVAL;
674 reg = avc_thr_db2reg[db];
675 snd_soc_component_write(component, SGTL5000_DAP_AVC_THRESHOLD, reg);
676
677 return 0;
678}
679
680static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
681
682/* tlv for mic gain, 0db 20db 30db 40db */
683static const DECLARE_TLV_DB_RANGE(mic_gain_tlv,
684 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
685 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0)
686);
687
688/* tlv for DAP channels, 0% - 100% - 200% */
689static const DECLARE_TLV_DB_SCALE(dap_volume, 0, 1, 0);
690
691/* tlv for bass bands, -11.75db to 12.0db, step .25db */
692static const DECLARE_TLV_DB_SCALE(bass_band, -1175, 25, 0);
693
694/* tlv for hp volume, -51.5db to 12.0db, step .5db */
695static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
696
697/* tlv for lineout volume, 31 steps of .5db each */
698static const DECLARE_TLV_DB_SCALE(lineout_volume, -1550, 50, 0);
699
700/* tlv for dap avc max gain, 0db, 6db, 12db */
701static const DECLARE_TLV_DB_SCALE(avc_max_gain, 0, 600, 0);
702
703/* tlv for dap avc threshold, */
704static const DECLARE_TLV_DB_MINMAX(avc_threshold, 0, 9600);
705
706static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
707 /* SOC_DOUBLE_S8_TLV with invert */
708 {
709 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
710 .name = "PCM Playback Volume",
711 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
712 SNDRV_CTL_ELEM_ACCESS_READWRITE,
713 .info = dac_info_volsw,
714 .get = dac_get_volsw,
715 .put = dac_put_volsw,
716 },
717
718 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
719 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
720 SGTL5000_CHIP_ANA_ADC_CTRL,
721 8, 1, 0, capture_6db_attenuate),
722 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
723 SOC_SINGLE("Capture Switch", SGTL5000_CHIP_ANA_CTRL, 0, 1, 1),
724
725 SOC_DOUBLE_TLV("Headphone Playback Volume",
726 SGTL5000_CHIP_ANA_HP_CTRL,
727 0, 8,
728 0x7f, 1,
729 headphone_volume),
730 SOC_SINGLE("Headphone Playback Switch", SGTL5000_CHIP_ANA_CTRL,
731 4, 1, 1),
732 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
733 5, 1, 0),
734
735 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
736 0, 3, 0, mic_gain_tlv),
737
738 SOC_DOUBLE_TLV("Lineout Playback Volume",
739 SGTL5000_CHIP_LINE_OUT_VOL,
740 SGTL5000_LINE_OUT_VOL_LEFT_SHIFT,
741 SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT,
742 0x1f, 1,
743 lineout_volume),
744 SOC_SINGLE("Lineout Playback Switch", SGTL5000_CHIP_ANA_CTRL, 8, 1, 1),
745
746 SOC_SINGLE_TLV("DAP Main channel", SGTL5000_DAP_MAIN_CHAN,
747 0, 0xffff, 0, dap_volume),
748
749 SOC_SINGLE_TLV("DAP Mix channel", SGTL5000_DAP_MIX_CHAN,
750 0, 0xffff, 0, dap_volume),
751 /* Automatic Volume Control (DAP AVC) */
752 SOC_SINGLE("AVC Switch", SGTL5000_DAP_AVC_CTRL, 0, 1, 0),
753 SOC_SINGLE("AVC Hard Limiter Switch", SGTL5000_DAP_AVC_CTRL, 5, 1, 0),
754 SOC_SINGLE_TLV("AVC Max Gain Volume", SGTL5000_DAP_AVC_CTRL, 12, 2, 0,
755 avc_max_gain),
756 SOC_SINGLE("AVC Integrator Response", SGTL5000_DAP_AVC_CTRL, 8, 3, 0),
757 SOC_SINGLE_EXT_TLV("AVC Threshold Volume", SGTL5000_DAP_AVC_THRESHOLD,
758 0, 96, 0, avc_get_threshold, avc_put_threshold,
759 avc_threshold),
760
761 SOC_SINGLE_TLV("BASS 0", SGTL5000_DAP_EQ_BASS_BAND0,
762 0, 0x5F, 0, bass_band),
763
764 SOC_SINGLE_TLV("BASS 1", SGTL5000_DAP_EQ_BASS_BAND1,
765 0, 0x5F, 0, bass_band),
766
767 SOC_SINGLE_TLV("BASS 2", SGTL5000_DAP_EQ_BASS_BAND2,
768 0, 0x5F, 0, bass_band),
769
770 SOC_SINGLE_TLV("BASS 3", SGTL5000_DAP_EQ_BASS_BAND3,
771 0, 0x5F, 0, bass_band),
772
773 SOC_SINGLE_TLV("BASS 4", SGTL5000_DAP_EQ_BASS_BAND4,
774 0, 0x5F, 0, bass_band),
775};
776
777/* mute the codec used by alsa core */
778static int sgtl5000_mute_stream(struct snd_soc_dai *codec_dai, int mute, int direction)
779{
780 struct snd_soc_component *component = codec_dai->component;
781 u16 i2s_pwr = SGTL5000_I2S_IN_POWERUP;
782
783 /*
784 * During 'digital mute' do not mute DAC
785 * because LINE_IN would be muted aswell. We want to mute
786 * only I2S block - this can be done by powering it off
787 */
788 snd_soc_component_update_bits(component, SGTL5000_CHIP_DIG_POWER,
789 i2s_pwr, mute ? 0 : i2s_pwr);
790
791 return 0;
792}
793
794/* set codec format */
795static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
796{
797 struct snd_soc_component *component = codec_dai->component;
798 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
799 u16 i2sctl = 0;
800
801 sgtl5000->master = 0;
802 /*
803 * i2s clock and frame master setting.
804 * ONLY support:
805 * - clock and frame slave,
806 * - clock and frame master
807 */
808 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
809 case SND_SOC_DAIFMT_CBS_CFS:
810 break;
811 case SND_SOC_DAIFMT_CBM_CFM:
812 i2sctl |= SGTL5000_I2S_MASTER;
813 sgtl5000->master = 1;
814 break;
815 default:
816 return -EINVAL;
817 }
818
819 /* setting i2s data format */
820 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
821 case SND_SOC_DAIFMT_DSP_A:
822 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
823 break;
824 case SND_SOC_DAIFMT_DSP_B:
825 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
826 i2sctl |= SGTL5000_I2S_LRALIGN;
827 break;
828 case SND_SOC_DAIFMT_I2S:
829 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
830 break;
831 case SND_SOC_DAIFMT_RIGHT_J:
832 i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT;
833 i2sctl |= SGTL5000_I2S_LRPOL;
834 break;
835 case SND_SOC_DAIFMT_LEFT_J:
836 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
837 i2sctl |= SGTL5000_I2S_LRALIGN;
838 break;
839 default:
840 return -EINVAL;
841 }
842
843 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
844
845 /* Clock inversion */
846 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
847 case SND_SOC_DAIFMT_NB_NF:
848 break;
849 case SND_SOC_DAIFMT_IB_NF:
850 i2sctl |= SGTL5000_I2S_SCLK_INV;
851 break;
852 default:
853 return -EINVAL;
854 }
855
856 snd_soc_component_write(component, SGTL5000_CHIP_I2S_CTRL, i2sctl);
857
858 return 0;
859}
860
861/* set codec sysclk */
862static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
863 int clk_id, unsigned int freq, int dir)
864{
865 struct snd_soc_component *component = codec_dai->component;
866 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
867
868 switch (clk_id) {
869 case SGTL5000_SYSCLK:
870 sgtl5000->sysclk = freq;
871 break;
872 default:
873 return -EINVAL;
874 }
875
876 return 0;
877}
878
879/*
880 * set clock according to i2s frame clock,
881 * sgtl5000 provides 2 clock sources:
882 * 1. sys_mclk: sample freq can only be configured to
883 * 1/256, 1/384, 1/512 of sys_mclk.
884 * 2. pll: can derive any audio clocks.
885 *
886 * clock setting rules:
887 * 1. in slave mode, only sys_mclk can be used
888 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
889 * and above.
890 * 3. usage of sys_mclk is preferred over pll to save power.
891 */
892static int sgtl5000_set_clock(struct snd_soc_component *component, int frame_rate)
893{
894 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
895 int clk_ctl = 0;
896 int sys_fs; /* sample freq */
897
898 /*
899 * sample freq should be divided by frame clock,
900 * if frame clock is lower than 44.1 kHz, sample freq should be set to
901 * 32 kHz or 44.1 kHz.
902 */
903 switch (frame_rate) {
904 case 8000:
905 case 16000:
906 sys_fs = 32000;
907 break;
908 case 11025:
909 case 22050:
910 sys_fs = 44100;
911 break;
912 default:
913 sys_fs = frame_rate;
914 break;
915 }
916
917 /* set divided factor of frame clock */
918 switch (sys_fs / frame_rate) {
919 case 4:
920 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
921 break;
922 case 2:
923 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
924 break;
925 case 1:
926 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
927 break;
928 default:
929 return -EINVAL;
930 }
931
932 /* set the sys_fs according to frame rate */
933 switch (sys_fs) {
934 case 32000:
935 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
936 break;
937 case 44100:
938 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
939 break;
940 case 48000:
941 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
942 break;
943 case 96000:
944 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
945 break;
946 default:
947 dev_err(component->dev, "frame rate %d not supported\n",
948 frame_rate);
949 return -EINVAL;
950 }
951
952 /*
953 * calculate the divider of mclk/sample_freq,
954 * factor of freq = 96 kHz can only be 256, since mclk is in the range
955 * of 8 MHz - 27 MHz
956 */
957 switch (sgtl5000->sysclk / frame_rate) {
958 case 256:
959 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
960 SGTL5000_MCLK_FREQ_SHIFT;
961 break;
962 case 384:
963 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
964 SGTL5000_MCLK_FREQ_SHIFT;
965 break;
966 case 512:
967 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
968 SGTL5000_MCLK_FREQ_SHIFT;
969 break;
970 default:
971 /* if mclk does not satisfy the divider, use pll */
972 if (sgtl5000->master) {
973 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
974 SGTL5000_MCLK_FREQ_SHIFT;
975 } else {
976 dev_err(component->dev,
977 "PLL not supported in slave mode\n");
978 dev_err(component->dev, "%d ratio is not supported. "
979 "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
980 sgtl5000->sysclk / frame_rate);
981 return -EINVAL;
982 }
983 }
984
985 /* if using pll, please check manual 6.4.2 for detail */
986 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
987 u64 out, t;
988 int div2;
989 int pll_ctl;
990 unsigned int in, int_div, frac_div;
991
992 if (sgtl5000->sysclk > 17000000) {
993 div2 = 1;
994 in = sgtl5000->sysclk / 2;
995 } else {
996 div2 = 0;
997 in = sgtl5000->sysclk;
998 }
999 if (sys_fs == 44100)
1000 out = 180633600;
1001 else
1002 out = 196608000;
1003 t = do_div(out, in);
1004 int_div = out;
1005 t *= 2048;
1006 do_div(t, in);
1007 frac_div = t;
1008 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
1009 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
1010
1011 snd_soc_component_write(component, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
1012 if (div2)
1013 snd_soc_component_update_bits(component,
1014 SGTL5000_CHIP_CLK_TOP_CTRL,
1015 SGTL5000_INPUT_FREQ_DIV2,
1016 SGTL5000_INPUT_FREQ_DIV2);
1017 else
1018 snd_soc_component_update_bits(component,
1019 SGTL5000_CHIP_CLK_TOP_CTRL,
1020 SGTL5000_INPUT_FREQ_DIV2,
1021 0);
1022
1023 /* power up pll */
1024 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
1025 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
1026 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
1027
1028 /* if using pll, clk_ctrl must be set after pll power up */
1029 snd_soc_component_write(component, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
1030 } else {
1031 /* otherwise, clk_ctrl must be set before pll power down */
1032 snd_soc_component_write(component, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
1033
1034 /* power down pll */
1035 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
1036 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
1037 0);
1038 }
1039
1040 return 0;
1041}
1042
1043/*
1044 * Set PCM DAI bit size and sample rate.
1045 * input: params_rate, params_fmt
1046 */
1047static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
1048 struct snd_pcm_hw_params *params,
1049 struct snd_soc_dai *dai)
1050{
1051 struct snd_soc_component *component = dai->component;
1052 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
1053 int channels = params_channels(params);
1054 int i2s_ctl = 0;
1055 int stereo;
1056 int ret;
1057
1058 /* sysclk should already set */
1059 if (!sgtl5000->sysclk) {
1060 dev_err(component->dev, "%s: set sysclk first!\n", __func__);
1061 return -EFAULT;
1062 }
1063
1064 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1065 stereo = SGTL5000_DAC_STEREO;
1066 else
1067 stereo = SGTL5000_ADC_STEREO;
1068
1069 /* set mono to save power */
1070 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER, stereo,
1071 channels == 1 ? 0 : stereo);
1072
1073 /* set codec clock base on lrclk */
1074 ret = sgtl5000_set_clock(component, params_rate(params));
1075 if (ret)
1076 return ret;
1077
1078 /* set i2s data format */
1079 switch (params_width(params)) {
1080 case 16:
1081 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
1082 return -EINVAL;
1083 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
1084 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
1085 SGTL5000_I2S_SCLKFREQ_SHIFT;
1086 break;
1087 case 20:
1088 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
1089 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
1090 SGTL5000_I2S_SCLKFREQ_SHIFT;
1091 break;
1092 case 24:
1093 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
1094 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
1095 SGTL5000_I2S_SCLKFREQ_SHIFT;
1096 break;
1097 case 32:
1098 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
1099 return -EINVAL;
1100 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
1101 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
1102 SGTL5000_I2S_SCLKFREQ_SHIFT;
1103 break;
1104 default:
1105 return -EINVAL;
1106 }
1107
1108 snd_soc_component_update_bits(component, SGTL5000_CHIP_I2S_CTRL,
1109 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
1110 i2s_ctl);
1111
1112 return 0;
1113}
1114
1115/*
1116 * set dac bias
1117 * common state changes:
1118 * startup:
1119 * off --> standby --> prepare --> on
1120 * standby --> prepare --> on
1121 *
1122 * stop:
1123 * on --> prepare --> standby
1124 */
1125static int sgtl5000_set_bias_level(struct snd_soc_component *component,
1126 enum snd_soc_bias_level level)
1127{
1128 struct sgtl5000_priv *sgtl = snd_soc_component_get_drvdata(component);
1129 int ret;
1130
1131 switch (level) {
1132 case SND_SOC_BIAS_ON:
1133 case SND_SOC_BIAS_PREPARE:
1134 case SND_SOC_BIAS_STANDBY:
1135 regcache_cache_only(sgtl->regmap, false);
1136 ret = regcache_sync(sgtl->regmap);
1137 if (ret) {
1138 regcache_cache_only(sgtl->regmap, true);
1139 return ret;
1140 }
1141
1142 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
1143 SGTL5000_REFTOP_POWERUP,
1144 SGTL5000_REFTOP_POWERUP);
1145 break;
1146 case SND_SOC_BIAS_OFF:
1147 regcache_cache_only(sgtl->regmap, true);
1148 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
1149 SGTL5000_REFTOP_POWERUP, 0);
1150 break;
1151 }
1152
1153 return 0;
1154}
1155
1156#define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1157 SNDRV_PCM_FMTBIT_S20_3LE |\
1158 SNDRV_PCM_FMTBIT_S24_LE |\
1159 SNDRV_PCM_FMTBIT_S32_LE)
1160
1161static const struct snd_soc_dai_ops sgtl5000_ops = {
1162 .hw_params = sgtl5000_pcm_hw_params,
1163 .mute_stream = sgtl5000_mute_stream,
1164 .set_fmt = sgtl5000_set_dai_fmt,
1165 .set_sysclk = sgtl5000_set_dai_sysclk,
1166 .no_capture_mute = 1,
1167};
1168
1169static struct snd_soc_dai_driver sgtl5000_dai = {
1170 .name = "sgtl5000",
1171 .playback = {
1172 .stream_name = "Playback",
1173 .channels_min = 1,
1174 .channels_max = 2,
1175 /*
1176 * only support 8~48K + 96K,
1177 * TODO modify hw_param to support more
1178 */
1179 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1180 .formats = SGTL5000_FORMATS,
1181 },
1182 .capture = {
1183 .stream_name = "Capture",
1184 .channels_min = 1,
1185 .channels_max = 2,
1186 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1187 .formats = SGTL5000_FORMATS,
1188 },
1189 .ops = &sgtl5000_ops,
1190 .symmetric_rate = 1,
1191};
1192
1193static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
1194{
1195 switch (reg) {
1196 case SGTL5000_CHIP_ID:
1197 case SGTL5000_CHIP_ADCDAC_CTRL:
1198 case SGTL5000_CHIP_ANA_STATUS:
1199 return true;
1200 }
1201
1202 return false;
1203}
1204
1205static bool sgtl5000_readable(struct device *dev, unsigned int reg)
1206{
1207 switch (reg) {
1208 case SGTL5000_CHIP_ID:
1209 case SGTL5000_CHIP_DIG_POWER:
1210 case SGTL5000_CHIP_CLK_CTRL:
1211 case SGTL5000_CHIP_I2S_CTRL:
1212 case SGTL5000_CHIP_SSS_CTRL:
1213 case SGTL5000_CHIP_ADCDAC_CTRL:
1214 case SGTL5000_CHIP_DAC_VOL:
1215 case SGTL5000_CHIP_PAD_STRENGTH:
1216 case SGTL5000_CHIP_ANA_ADC_CTRL:
1217 case SGTL5000_CHIP_ANA_HP_CTRL:
1218 case SGTL5000_CHIP_ANA_CTRL:
1219 case SGTL5000_CHIP_LINREG_CTRL:
1220 case SGTL5000_CHIP_REF_CTRL:
1221 case SGTL5000_CHIP_MIC_CTRL:
1222 case SGTL5000_CHIP_LINE_OUT_CTRL:
1223 case SGTL5000_CHIP_LINE_OUT_VOL:
1224 case SGTL5000_CHIP_ANA_POWER:
1225 case SGTL5000_CHIP_PLL_CTRL:
1226 case SGTL5000_CHIP_CLK_TOP_CTRL:
1227 case SGTL5000_CHIP_ANA_STATUS:
1228 case SGTL5000_CHIP_SHORT_CTRL:
1229 case SGTL5000_CHIP_ANA_TEST2:
1230 case SGTL5000_DAP_CTRL:
1231 case SGTL5000_DAP_PEQ:
1232 case SGTL5000_DAP_BASS_ENHANCE:
1233 case SGTL5000_DAP_BASS_ENHANCE_CTRL:
1234 case SGTL5000_DAP_AUDIO_EQ:
1235 case SGTL5000_DAP_SURROUND:
1236 case SGTL5000_DAP_FLT_COEF_ACCESS:
1237 case SGTL5000_DAP_COEF_WR_B0_MSB:
1238 case SGTL5000_DAP_COEF_WR_B0_LSB:
1239 case SGTL5000_DAP_EQ_BASS_BAND0:
1240 case SGTL5000_DAP_EQ_BASS_BAND1:
1241 case SGTL5000_DAP_EQ_BASS_BAND2:
1242 case SGTL5000_DAP_EQ_BASS_BAND3:
1243 case SGTL5000_DAP_EQ_BASS_BAND4:
1244 case SGTL5000_DAP_MAIN_CHAN:
1245 case SGTL5000_DAP_MIX_CHAN:
1246 case SGTL5000_DAP_AVC_CTRL:
1247 case SGTL5000_DAP_AVC_THRESHOLD:
1248 case SGTL5000_DAP_AVC_ATTACK:
1249 case SGTL5000_DAP_AVC_DECAY:
1250 case SGTL5000_DAP_COEF_WR_B1_MSB:
1251 case SGTL5000_DAP_COEF_WR_B1_LSB:
1252 case SGTL5000_DAP_COEF_WR_B2_MSB:
1253 case SGTL5000_DAP_COEF_WR_B2_LSB:
1254 case SGTL5000_DAP_COEF_WR_A1_MSB:
1255 case SGTL5000_DAP_COEF_WR_A1_LSB:
1256 case SGTL5000_DAP_COEF_WR_A2_MSB:
1257 case SGTL5000_DAP_COEF_WR_A2_LSB:
1258 return true;
1259
1260 default:
1261 return false;
1262 }
1263}
1264
1265/*
1266 * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results
1267 * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL
1268 * The calculatation was done for all possible register values which
1269 * is the array index and the following formula: 10^((idx−15)/40) * 100
1270 */
1271static const u8 vol_quot_table[] = {
1272 42, 45, 47, 50, 53, 56, 60, 63,
1273 67, 71, 75, 79, 84, 89, 94, 100,
1274 106, 112, 119, 126, 133, 141, 150, 158,
1275 168, 178, 188, 200, 211, 224, 237, 251
1276};
1277
1278/*
1279 * sgtl5000 has 3 internal power supplies:
1280 * 1. VAG, normally set to vdda/2
1281 * 2. charge pump, set to different value
1282 * according to voltage of vdda and vddio
1283 * 3. line out VAG, normally set to vddio/2
1284 *
1285 * and should be set according to:
1286 * 1. vddd provided by external or not
1287 * 2. vdda and vddio voltage value. > 3.1v or not
1288 */
1289static int sgtl5000_set_power_regs(struct snd_soc_component *component)
1290{
1291 int vddd;
1292 int vdda;
1293 int vddio;
1294 u16 ana_pwr;
1295 u16 lreg_ctrl;
1296 int vag;
1297 int lo_vag;
1298 int vol_quot;
1299 int lo_vol;
1300 size_t i;
1301 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
1302
1303 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1304 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
1305 vddd = (sgtl5000->num_supplies > VDDD)
1306 ? regulator_get_voltage(sgtl5000->supplies[VDDD].consumer)
1307 : LDO_VOLTAGE;
1308
1309 vdda = vdda / 1000;
1310 vddio = vddio / 1000;
1311 vddd = vddd / 1000;
1312
1313 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1314 dev_err(component->dev, "regulator voltage not set correctly\n");
1315
1316 return -EINVAL;
1317 }
1318
1319 /* according to datasheet, maximum voltage of supplies */
1320 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1321 dev_err(component->dev,
1322 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
1323 vdda, vddio, vddd);
1324
1325 return -EINVAL;
1326 }
1327
1328 /* reset value */
1329 ana_pwr = snd_soc_component_read(component, SGTL5000_CHIP_ANA_POWER);
1330 ana_pwr |= SGTL5000_DAC_STEREO |
1331 SGTL5000_ADC_STEREO |
1332 SGTL5000_REFTOP_POWERUP;
1333 lreg_ctrl = snd_soc_component_read(component, SGTL5000_CHIP_LINREG_CTRL);
1334
1335 if (vddio < 3100 && vdda < 3100) {
1336 /* enable internal oscillator used for charge pump */
1337 snd_soc_component_update_bits(component, SGTL5000_CHIP_CLK_TOP_CTRL,
1338 SGTL5000_INT_OSC_EN,
1339 SGTL5000_INT_OSC_EN);
1340 /* Enable VDDC charge pump */
1341 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1342 } else {
1343 ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
1344 /*
1345 * if vddio == vdda the source of charge pump should be
1346 * assigned manually to VDDIO
1347 */
1348 if (regulator_is_equal(sgtl5000->supplies[VDDA].consumer,
1349 sgtl5000->supplies[VDDIO].consumer)) {
1350 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1351 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1352 SGTL5000_VDDC_MAN_ASSN_SHIFT;
1353 }
1354 }
1355
1356 snd_soc_component_write(component, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1357
1358 snd_soc_component_write(component, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1359
1360 /*
1361 * set ADC/DAC VAG to vdda / 2,
1362 * should stay in range (0.8v, 1.575v)
1363 */
1364 vag = vdda / 2;
1365 if (vag <= SGTL5000_ANA_GND_BASE)
1366 vag = 0;
1367 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1368 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1369 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1370 else
1371 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1372
1373 snd_soc_component_update_bits(component, SGTL5000_CHIP_REF_CTRL,
1374 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
1375
1376 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1377 lo_vag = vddio / 2;
1378 if (lo_vag <= SGTL5000_LINE_OUT_GND_BASE)
1379 lo_vag = 0;
1380 else if (lo_vag >= SGTL5000_LINE_OUT_GND_BASE +
1381 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
1382 lo_vag = SGTL5000_LINE_OUT_GND_MAX;
1383 else
1384 lo_vag = (lo_vag - SGTL5000_LINE_OUT_GND_BASE) /
1385 SGTL5000_LINE_OUT_GND_STP;
1386
1387 snd_soc_component_update_bits(component, SGTL5000_CHIP_LINE_OUT_CTRL,
1388 SGTL5000_LINE_OUT_CURRENT_MASK |
1389 SGTL5000_LINE_OUT_GND_MASK,
1390 lo_vag << SGTL5000_LINE_OUT_GND_SHIFT |
1391 SGTL5000_LINE_OUT_CURRENT_360u <<
1392 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1393
1394 /*
1395 * Set lineout output level in range (0..31)
1396 * the same value is used for right and left channel
1397 *
1398 * Searching for a suitable index solving this formula:
1399 * idx = 40 * log10(vag_val / lo_cagcntrl) + 15
1400 */
1401 vol_quot = lo_vag ? (vag * 100) / lo_vag : 0;
1402 lo_vol = 0;
1403 for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) {
1404 if (vol_quot >= vol_quot_table[i])
1405 lo_vol = i;
1406 else
1407 break;
1408 }
1409
1410 snd_soc_component_update_bits(component, SGTL5000_CHIP_LINE_OUT_VOL,
1411 SGTL5000_LINE_OUT_VOL_RIGHT_MASK |
1412 SGTL5000_LINE_OUT_VOL_LEFT_MASK,
1413 lo_vol << SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT |
1414 lo_vol << SGTL5000_LINE_OUT_VOL_LEFT_SHIFT);
1415
1416 return 0;
1417}
1418
1419static int sgtl5000_enable_regulators(struct i2c_client *client)
1420{
1421 int ret;
1422 int i;
1423 int external_vddd = 0;
1424 struct regulator *vddd;
1425 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1426
1427 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1428 sgtl5000->supplies[i].supply = supply_names[i];
1429
1430 vddd = regulator_get_optional(&client->dev, "VDDD");
1431 if (IS_ERR(vddd)) {
1432 /* See if it's just not registered yet */
1433 if (PTR_ERR(vddd) == -EPROBE_DEFER)
1434 return -EPROBE_DEFER;
1435 } else {
1436 external_vddd = 1;
1437 regulator_put(vddd);
1438 }
1439
1440 sgtl5000->num_supplies = ARRAY_SIZE(sgtl5000->supplies)
1441 - 1 + external_vddd;
1442 ret = regulator_bulk_get(&client->dev, sgtl5000->num_supplies,
1443 sgtl5000->supplies);
1444 if (ret)
1445 return ret;
1446
1447 ret = regulator_bulk_enable(sgtl5000->num_supplies,
1448 sgtl5000->supplies);
1449 if (!ret)
1450 usleep_range(10, 20);
1451 else
1452 regulator_bulk_free(sgtl5000->num_supplies,
1453 sgtl5000->supplies);
1454
1455 return ret;
1456}
1457
1458static int sgtl5000_probe(struct snd_soc_component *component)
1459{
1460 int ret;
1461 u16 reg;
1462 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
1463 unsigned int zcd_mask = SGTL5000_HP_ZCD_EN | SGTL5000_ADC_ZCD_EN;
1464
1465 /* power up sgtl5000 */
1466 ret = sgtl5000_set_power_regs(component);
1467 if (ret)
1468 goto err;
1469
1470 /* enable small pop, introduce 400ms delay in turning off */
1471 snd_soc_component_update_bits(component, SGTL5000_CHIP_REF_CTRL,
1472 SGTL5000_SMALL_POP, SGTL5000_SMALL_POP);
1473
1474 /* disable short cut detector */
1475 snd_soc_component_write(component, SGTL5000_CHIP_SHORT_CTRL, 0);
1476
1477 snd_soc_component_write(component, SGTL5000_CHIP_DIG_POWER,
1478 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1479
1480 /* enable dac volume ramp by default */
1481 snd_soc_component_write(component, SGTL5000_CHIP_ADCDAC_CTRL,
1482 SGTL5000_DAC_VOL_RAMP_EN |
1483 SGTL5000_DAC_MUTE_RIGHT |
1484 SGTL5000_DAC_MUTE_LEFT);
1485
1486 reg = ((sgtl5000->lrclk_strength) << SGTL5000_PAD_I2S_LRCLK_SHIFT |
1487 (sgtl5000->sclk_strength) << SGTL5000_PAD_I2S_SCLK_SHIFT |
1488 0x1f);
1489 snd_soc_component_write(component, SGTL5000_CHIP_PAD_STRENGTH, reg);
1490
1491 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL,
1492 zcd_mask, zcd_mask);
1493
1494 snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
1495 SGTL5000_BIAS_R_MASK,
1496 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
1497
1498 snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
1499 SGTL5000_BIAS_VOLT_MASK,
1500 sgtl5000->micbias_voltage << SGTL5000_BIAS_VOLT_SHIFT);
1501 /*
1502 * enable DAP Graphic EQ
1503 * TODO:
1504 * Add control for changing between PEQ/Tone Control/GEQ
1505 */
1506 snd_soc_component_write(component, SGTL5000_DAP_AUDIO_EQ, SGTL5000_DAP_SEL_GEQ);
1507
1508 /* Unmute DAC after start */
1509 snd_soc_component_update_bits(component, SGTL5000_CHIP_ADCDAC_CTRL,
1510 SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT, 0);
1511
1512 return 0;
1513
1514err:
1515 return ret;
1516}
1517
1518static int sgtl5000_of_xlate_dai_id(struct snd_soc_component *component,
1519 struct device_node *endpoint)
1520{
1521 /* return dai id 0, whatever the endpoint index */
1522 return 0;
1523}
1524
1525static const struct snd_soc_component_driver sgtl5000_driver = {
1526 .probe = sgtl5000_probe,
1527 .set_bias_level = sgtl5000_set_bias_level,
1528 .controls = sgtl5000_snd_controls,
1529 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
1530 .dapm_widgets = sgtl5000_dapm_widgets,
1531 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
1532 .dapm_routes = sgtl5000_dapm_routes,
1533 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
1534 .of_xlate_dai_id = sgtl5000_of_xlate_dai_id,
1535 .suspend_bias_off = 1,
1536 .idle_bias_on = 1,
1537 .use_pmdown_time = 1,
1538 .endianness = 1,
1539};
1540
1541static const struct regmap_config sgtl5000_regmap = {
1542 .reg_bits = 16,
1543 .val_bits = 16,
1544 .reg_stride = 2,
1545
1546 .max_register = SGTL5000_MAX_REG_OFFSET,
1547 .volatile_reg = sgtl5000_volatile,
1548 .readable_reg = sgtl5000_readable,
1549
1550 .cache_type = REGCACHE_RBTREE,
1551 .reg_defaults = sgtl5000_reg_defaults,
1552 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
1553};
1554
1555/*
1556 * Write all the default values from sgtl5000_reg_defaults[] array into the
1557 * sgtl5000 registers, to make sure we always start with the sane registers
1558 * values as stated in the datasheet.
1559 *
1560 * Since sgtl5000 does not have a reset line, nor a reset command in software,
1561 * we follow this approach to guarantee we always start from the default values
1562 * and avoid problems like, not being able to probe after an audio playback
1563 * followed by a system reset or a 'reboot' command in Linux
1564 */
1565static void sgtl5000_fill_defaults(struct i2c_client *client)
1566{
1567 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1568 int i, ret, val, index;
1569
1570 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
1571 val = sgtl5000_reg_defaults[i].def;
1572 index = sgtl5000_reg_defaults[i].reg;
1573 ret = regmap_write(sgtl5000->regmap, index, val);
1574 if (ret)
1575 dev_err(&client->dev,
1576 "%s: error %d setting reg 0x%02x to 0x%04x\n",
1577 __func__, ret, index, val);
1578 }
1579}
1580
1581static int sgtl5000_i2c_probe(struct i2c_client *client)
1582{
1583 struct sgtl5000_priv *sgtl5000;
1584 int ret, reg, rev;
1585 struct device_node *np = client->dev.of_node;
1586 u32 value;
1587 u16 ana_pwr;
1588
1589 sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL);
1590 if (!sgtl5000)
1591 return -ENOMEM;
1592
1593 i2c_set_clientdata(client, sgtl5000);
1594
1595 ret = sgtl5000_enable_regulators(client);
1596 if (ret)
1597 return ret;
1598
1599 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
1600 if (IS_ERR(sgtl5000->regmap)) {
1601 ret = PTR_ERR(sgtl5000->regmap);
1602 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
1603 goto disable_regs;
1604 }
1605
1606 sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
1607 if (IS_ERR(sgtl5000->mclk)) {
1608 ret = PTR_ERR(sgtl5000->mclk);
1609 /* Defer the probe to see if the clk will be provided later */
1610 if (ret == -ENOENT)
1611 ret = -EPROBE_DEFER;
1612
1613 dev_err_probe(&client->dev, ret, "Failed to get mclock\n");
1614
1615 goto disable_regs;
1616 }
1617
1618 ret = clk_prepare_enable(sgtl5000->mclk);
1619 if (ret) {
1620 dev_err(&client->dev, "Error enabling clock %d\n", ret);
1621 goto disable_regs;
1622 }
1623
1624 /* Need 8 clocks before I2C accesses */
1625 udelay(1);
1626
1627 /* read chip information */
1628 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®);
1629 if (ret) {
1630 dev_err(&client->dev, "Error reading chip id %d\n", ret);
1631 goto disable_clk;
1632 }
1633
1634 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1635 SGTL5000_PARTID_PART_ID) {
1636 dev_err(&client->dev,
1637 "Device with ID register %x is not a sgtl5000\n", reg);
1638 ret = -ENODEV;
1639 goto disable_clk;
1640 }
1641
1642 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1643 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
1644 sgtl5000->revision = rev;
1645
1646 /* reconfigure the clocks in case we're using the PLL */
1647 ret = regmap_write(sgtl5000->regmap,
1648 SGTL5000_CHIP_CLK_CTRL,
1649 SGTL5000_CHIP_CLK_CTRL_DEFAULT);
1650 if (ret)
1651 dev_err(&client->dev,
1652 "Error %d initializing CHIP_CLK_CTRL\n", ret);
1653
1654 /* Mute everything to avoid pop from the following power-up */
1655 ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_CTRL,
1656 SGTL5000_CHIP_ANA_CTRL_DEFAULT);
1657 if (ret) {
1658 dev_err(&client->dev,
1659 "Error %d muting outputs via CHIP_ANA_CTRL\n", ret);
1660 goto disable_clk;
1661 }
1662
1663 /*
1664 * If VAG is powered-on (e.g. from previous boot), it would be disabled
1665 * by the write to ANA_POWER in later steps of the probe code. This
1666 * may create a loud pop even with all outputs muted. The proper way
1667 * to circumvent this is disabling the bit first and waiting the proper
1668 * cool-down time.
1669 */
1670 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, &value);
1671 if (ret) {
1672 dev_err(&client->dev, "Failed to read ANA_POWER: %d\n", ret);
1673 goto disable_clk;
1674 }
1675 if (value & SGTL5000_VAG_POWERUP) {
1676 ret = regmap_update_bits(sgtl5000->regmap,
1677 SGTL5000_CHIP_ANA_POWER,
1678 SGTL5000_VAG_POWERUP,
1679 0);
1680 if (ret) {
1681 dev_err(&client->dev, "Error %d disabling VAG\n", ret);
1682 goto disable_clk;
1683 }
1684
1685 msleep(SGTL5000_VAG_POWERDOWN_DELAY);
1686 }
1687
1688 /* Follow section 2.2.1.1 of AN3663 */
1689 ana_pwr = SGTL5000_ANA_POWER_DEFAULT;
1690 if (sgtl5000->num_supplies <= VDDD) {
1691 /* internal VDDD at 1.2V */
1692 ret = regmap_update_bits(sgtl5000->regmap,
1693 SGTL5000_CHIP_LINREG_CTRL,
1694 SGTL5000_LINREG_VDDD_MASK,
1695 LINREG_VDDD);
1696 if (ret)
1697 dev_err(&client->dev,
1698 "Error %d setting LINREG_VDDD\n", ret);
1699
1700 ana_pwr |= SGTL5000_LINEREG_D_POWERUP;
1701 dev_info(&client->dev,
1702 "Using internal LDO instead of VDDD: check ER1 erratum\n");
1703 } else {
1704 /* using external LDO for VDDD
1705 * Clear startup powerup and simple powerup
1706 * bits to save power
1707 */
1708 ana_pwr &= ~(SGTL5000_STARTUP_POWERUP
1709 | SGTL5000_LINREG_SIMPLE_POWERUP);
1710 dev_dbg(&client->dev, "Using external VDDD\n");
1711 }
1712 ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1713 if (ret)
1714 dev_err(&client->dev,
1715 "Error %d setting CHIP_ANA_POWER to %04x\n",
1716 ret, ana_pwr);
1717
1718 if (np) {
1719 if (!of_property_read_u32(np,
1720 "micbias-resistor-k-ohms", &value)) {
1721 switch (value) {
1722 case SGTL5000_MICBIAS_OFF:
1723 sgtl5000->micbias_resistor = 0;
1724 break;
1725 case SGTL5000_MICBIAS_2K:
1726 sgtl5000->micbias_resistor = 1;
1727 break;
1728 case SGTL5000_MICBIAS_4K:
1729 sgtl5000->micbias_resistor = 2;
1730 break;
1731 case SGTL5000_MICBIAS_8K:
1732 sgtl5000->micbias_resistor = 3;
1733 break;
1734 default:
1735 sgtl5000->micbias_resistor = 2;
1736 dev_err(&client->dev,
1737 "Unsuitable MicBias resistor\n");
1738 }
1739 } else {
1740 /* default is 4Kohms */
1741 sgtl5000->micbias_resistor = 2;
1742 }
1743 if (!of_property_read_u32(np,
1744 "micbias-voltage-m-volts", &value)) {
1745 /* 1250mV => 0 */
1746 /* steps of 250mV */
1747 if ((value >= 1250) && (value <= 3000))
1748 sgtl5000->micbias_voltage = (value / 250) - 5;
1749 else {
1750 sgtl5000->micbias_voltage = 0;
1751 dev_err(&client->dev,
1752 "Unsuitable MicBias voltage\n");
1753 }
1754 } else {
1755 sgtl5000->micbias_voltage = 0;
1756 }
1757 }
1758
1759 sgtl5000->lrclk_strength = I2S_LRCLK_STRENGTH_LOW;
1760 if (!of_property_read_u32(np, "lrclk-strength", &value)) {
1761 if (value > I2S_LRCLK_STRENGTH_HIGH)
1762 value = I2S_LRCLK_STRENGTH_LOW;
1763 sgtl5000->lrclk_strength = value;
1764 }
1765
1766 sgtl5000->sclk_strength = I2S_SCLK_STRENGTH_LOW;
1767 if (!of_property_read_u32(np, "sclk-strength", &value)) {
1768 if (value > I2S_SCLK_STRENGTH_HIGH)
1769 value = I2S_SCLK_STRENGTH_LOW;
1770 sgtl5000->sclk_strength = value;
1771 }
1772
1773 /* Ensure sgtl5000 will start with sane register values */
1774 sgtl5000_fill_defaults(client);
1775
1776 ret = devm_snd_soc_register_component(&client->dev,
1777 &sgtl5000_driver, &sgtl5000_dai, 1);
1778 if (ret)
1779 goto disable_clk;
1780
1781 return 0;
1782
1783disable_clk:
1784 clk_disable_unprepare(sgtl5000->mclk);
1785
1786disable_regs:
1787 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1788 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1789
1790 return ret;
1791}
1792
1793static void sgtl5000_i2c_remove(struct i2c_client *client)
1794{
1795 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1796
1797 regmap_write(sgtl5000->regmap, SGTL5000_CHIP_CLK_CTRL, SGTL5000_CHIP_CLK_CTRL_DEFAULT);
1798 regmap_write(sgtl5000->regmap, SGTL5000_CHIP_DIG_POWER, SGTL5000_DIG_POWER_DEFAULT);
1799 regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, SGTL5000_ANA_POWER_DEFAULT);
1800
1801 clk_disable_unprepare(sgtl5000->mclk);
1802 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1803 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1804}
1805
1806static void sgtl5000_i2c_shutdown(struct i2c_client *client)
1807{
1808 sgtl5000_i2c_remove(client);
1809}
1810
1811static const struct i2c_device_id sgtl5000_id[] = {
1812 {"sgtl5000"},
1813 {},
1814};
1815
1816MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1817
1818static const struct of_device_id sgtl5000_dt_ids[] = {
1819 { .compatible = "fsl,sgtl5000", },
1820 { /* sentinel */ }
1821};
1822MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
1823
1824static struct i2c_driver sgtl5000_i2c_driver = {
1825 .driver = {
1826 .name = "sgtl5000",
1827 .of_match_table = sgtl5000_dt_ids,
1828 },
1829 .probe = sgtl5000_i2c_probe,
1830 .remove = sgtl5000_i2c_remove,
1831 .shutdown = sgtl5000_i2c_shutdown,
1832 .id_table = sgtl5000_id,
1833};
1834
1835module_i2c_driver(sgtl5000_i2c_driver);
1836
1837MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1838MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
1839MODULE_LICENSE("GPL");
1/*
2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
3 *
4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/slab.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/clk.h>
19#include <linux/log2.h>
20#include <linux/regmap.h>
21#include <linux/regulator/driver.h>
22#include <linux/regulator/machine.h>
23#include <linux/regulator/consumer.h>
24#include <linux/of_device.h>
25#include <sound/core.h>
26#include <sound/tlv.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
32
33#include "sgtl5000.h"
34
35#define SGTL5000_DAP_REG_OFFSET 0x0100
36#define SGTL5000_MAX_REG_OFFSET 0x013A
37
38/* default value of sgtl5000 registers */
39static const struct reg_default sgtl5000_reg_defaults[] = {
40 { SGTL5000_CHIP_DIG_POWER, 0x0000 },
41 { SGTL5000_CHIP_I2S_CTRL, 0x0010 },
42 { SGTL5000_CHIP_SSS_CTRL, 0x0010 },
43 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c },
44 { SGTL5000_CHIP_DAC_VOL, 0x3c3c },
45 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
46 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 },
47 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
48 { SGTL5000_CHIP_ANA_CTRL, 0x0111 },
49 { SGTL5000_CHIP_REF_CTRL, 0x0000 },
50 { SGTL5000_CHIP_MIC_CTRL, 0x0000 },
51 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 },
52 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
53 { SGTL5000_CHIP_PLL_CTRL, 0x5000 },
54 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 },
55 { SGTL5000_CHIP_ANA_STATUS, 0x0000 },
56 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 },
57 { SGTL5000_CHIP_ANA_TEST2, 0x0000 },
58 { SGTL5000_DAP_CTRL, 0x0000 },
59 { SGTL5000_DAP_PEQ, 0x0000 },
60 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
61 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
62 { SGTL5000_DAP_AUDIO_EQ, 0x0000 },
63 { SGTL5000_DAP_SURROUND, 0x0040 },
64 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
65 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
66 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f },
67 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
68 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
69 { SGTL5000_DAP_MAIN_CHAN, 0x8000 },
70 { SGTL5000_DAP_MIX_CHAN, 0x0000 },
71 { SGTL5000_DAP_AVC_CTRL, 0x0510 },
72 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
73 { SGTL5000_DAP_AVC_ATTACK, 0x0028 },
74 { SGTL5000_DAP_AVC_DECAY, 0x0050 },
75};
76
77/* regulator supplies for sgtl5000, VDDD is an optional external supply */
78enum sgtl5000_regulator_supplies {
79 VDDA,
80 VDDIO,
81 VDDD,
82 SGTL5000_SUPPLY_NUM
83};
84
85/* vddd is optional supply */
86static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
87 "VDDA",
88 "VDDIO",
89 "VDDD"
90};
91
92#define LDO_VOLTAGE 1200000
93#define LINREG_VDDD ((1600 - LDO_VOLTAGE / 1000) / 50)
94
95enum sgtl5000_micbias_resistor {
96 SGTL5000_MICBIAS_OFF = 0,
97 SGTL5000_MICBIAS_2K = 2,
98 SGTL5000_MICBIAS_4K = 4,
99 SGTL5000_MICBIAS_8K = 8,
100};
101
102/* sgtl5000 private structure in codec */
103struct sgtl5000_priv {
104 int sysclk; /* sysclk rate */
105 int master; /* i2s master or not */
106 int fmt; /* i2s data format */
107 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
108 int num_supplies;
109 struct regmap *regmap;
110 struct clk *mclk;
111 int revision;
112 u8 micbias_resistor;
113 u8 micbias_voltage;
114};
115
116/*
117 * mic_bias power on/off share the same register bits with
118 * output impedance of mic bias, when power on mic bias, we
119 * need reclaim it to impedance value.
120 * 0x0 = Powered off
121 * 0x1 = 2Kohm
122 * 0x2 = 4Kohm
123 * 0x3 = 8Kohm
124 */
125static int mic_bias_event(struct snd_soc_dapm_widget *w,
126 struct snd_kcontrol *kcontrol, int event)
127{
128 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
129 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
130
131 switch (event) {
132 case SND_SOC_DAPM_POST_PMU:
133 /* change mic bias resistor */
134 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
135 SGTL5000_BIAS_R_MASK,
136 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
137 break;
138
139 case SND_SOC_DAPM_PRE_PMD:
140 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
141 SGTL5000_BIAS_R_MASK, 0);
142 break;
143 }
144 return 0;
145}
146
147/*
148 * As manual described, ADC/DAC only works when VAG powerup,
149 * So enabled VAG before ADC/DAC up.
150 * In power down case, we need wait 400ms when vag fully ramped down.
151 */
152static int power_vag_event(struct snd_soc_dapm_widget *w,
153 struct snd_kcontrol *kcontrol, int event)
154{
155 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
156 const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP;
157
158 switch (event) {
159 case SND_SOC_DAPM_POST_PMU:
160 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
161 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
162 msleep(400);
163 break;
164
165 case SND_SOC_DAPM_PRE_PMD:
166 /*
167 * Don't clear VAG_POWERUP, when both DAC and ADC are
168 * operational to prevent inadvertently starving the
169 * other one of them.
170 */
171 if ((snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER) &
172 mask) != mask) {
173 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
174 SGTL5000_VAG_POWERUP, 0);
175 msleep(400);
176 }
177 break;
178 default:
179 break;
180 }
181
182 return 0;
183}
184
185/* input sources for ADC */
186static const char *adc_mux_text[] = {
187 "MIC_IN", "LINE_IN"
188};
189
190static SOC_ENUM_SINGLE_DECL(adc_enum,
191 SGTL5000_CHIP_ANA_CTRL, 2,
192 adc_mux_text);
193
194static const struct snd_kcontrol_new adc_mux =
195SOC_DAPM_ENUM("Capture Mux", adc_enum);
196
197/* input sources for DAC */
198static const char *dac_mux_text[] = {
199 "DAC", "LINE_IN"
200};
201
202static SOC_ENUM_SINGLE_DECL(dac_enum,
203 SGTL5000_CHIP_ANA_CTRL, 6,
204 dac_mux_text);
205
206static const struct snd_kcontrol_new dac_mux =
207SOC_DAPM_ENUM("Headphone Mux", dac_enum);
208
209static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
210 SND_SOC_DAPM_INPUT("LINE_IN"),
211 SND_SOC_DAPM_INPUT("MIC_IN"),
212
213 SND_SOC_DAPM_OUTPUT("HP_OUT"),
214 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
215
216 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
217 mic_bias_event,
218 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
219
220 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0),
221 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
222
223 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
224 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
225
226 /* aif for i2s input */
227 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
228 0, SGTL5000_CHIP_DIG_POWER,
229 0, 0),
230
231 /* aif for i2s output */
232 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
233 0, SGTL5000_CHIP_DIG_POWER,
234 1, 0),
235
236 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
237 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
238
239 SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event),
240 SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event),
241};
242
243/* routes for sgtl5000 */
244static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
245 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
246 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
247
248 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
249 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
250
251 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */
252 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
253 {"LO", NULL, "DAC"}, /* dac --> line_out */
254
255 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
256 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
257
258 {"LINE_OUT", NULL, "LO"},
259 {"HP_OUT", NULL, "HP"},
260};
261
262/* custom function to fetch info of PCM playback volume */
263static int dac_info_volsw(struct snd_kcontrol *kcontrol,
264 struct snd_ctl_elem_info *uinfo)
265{
266 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
267 uinfo->count = 2;
268 uinfo->value.integer.min = 0;
269 uinfo->value.integer.max = 0xfc - 0x3c;
270 return 0;
271}
272
273/*
274 * custom function to get of PCM playback volume
275 *
276 * dac volume register
277 * 15-------------8-7--------------0
278 * | R channel vol | L channel vol |
279 * -------------------------------
280 *
281 * PCM volume with 0.5017 dB steps from 0 to -90 dB
282 *
283 * register values map to dB
284 * 0x3B and less = Reserved
285 * 0x3C = 0 dB
286 * 0x3D = -0.5 dB
287 * 0xF0 = -90 dB
288 * 0xFC and greater = Muted
289 *
290 * register value map to userspace value
291 *
292 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
293 * ------------------------------
294 * userspace value 0xc0 0
295 */
296static int dac_get_volsw(struct snd_kcontrol *kcontrol,
297 struct snd_ctl_elem_value *ucontrol)
298{
299 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
300 int reg;
301 int l;
302 int r;
303
304 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
305
306 /* get left channel volume */
307 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
308
309 /* get right channel volume */
310 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
311
312 /* make sure value fall in (0x3c,0xfc) */
313 l = clamp(l, 0x3c, 0xfc);
314 r = clamp(r, 0x3c, 0xfc);
315
316 /* invert it and map to userspace value */
317 l = 0xfc - l;
318 r = 0xfc - r;
319
320 ucontrol->value.integer.value[0] = l;
321 ucontrol->value.integer.value[1] = r;
322
323 return 0;
324}
325
326/*
327 * custom function to put of PCM playback volume
328 *
329 * dac volume register
330 * 15-------------8-7--------------0
331 * | R channel vol | L channel vol |
332 * -------------------------------
333 *
334 * PCM volume with 0.5017 dB steps from 0 to -90 dB
335 *
336 * register values map to dB
337 * 0x3B and less = Reserved
338 * 0x3C = 0 dB
339 * 0x3D = -0.5 dB
340 * 0xF0 = -90 dB
341 * 0xFC and greater = Muted
342 *
343 * userspace value map to register value
344 *
345 * userspace value 0xc0 0
346 * ------------------------------
347 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
348 */
349static int dac_put_volsw(struct snd_kcontrol *kcontrol,
350 struct snd_ctl_elem_value *ucontrol)
351{
352 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
353 int reg;
354 int l;
355 int r;
356
357 l = ucontrol->value.integer.value[0];
358 r = ucontrol->value.integer.value[1];
359
360 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
361 l = clamp(l, 0, 0xfc - 0x3c);
362 r = clamp(r, 0, 0xfc - 0x3c);
363
364 /* invert it, get the value can be set to register */
365 l = 0xfc - l;
366 r = 0xfc - r;
367
368 /* shift to get the register value */
369 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
370 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
371
372 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
373
374 return 0;
375}
376
377static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
378
379/* tlv for mic gain, 0db 20db 30db 40db */
380static const DECLARE_TLV_DB_RANGE(mic_gain_tlv,
381 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
382 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0)
383);
384
385/* tlv for hp volume, -51.5db to 12.0db, step .5db */
386static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
387
388/* tlv for lineout volume, 31 steps of .5db each */
389static const DECLARE_TLV_DB_SCALE(lineout_volume, -1550, 50, 0);
390
391static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
392 /* SOC_DOUBLE_S8_TLV with invert */
393 {
394 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
395 .name = "PCM Playback Volume",
396 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
397 SNDRV_CTL_ELEM_ACCESS_READWRITE,
398 .info = dac_info_volsw,
399 .get = dac_get_volsw,
400 .put = dac_put_volsw,
401 },
402
403 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
404 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
405 SGTL5000_CHIP_ANA_ADC_CTRL,
406 8, 1, 0, capture_6db_attenuate),
407 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
408
409 SOC_DOUBLE_TLV("Headphone Playback Volume",
410 SGTL5000_CHIP_ANA_HP_CTRL,
411 0, 8,
412 0x7f, 1,
413 headphone_volume),
414 SOC_SINGLE("Headphone Playback Switch", SGTL5000_CHIP_ANA_CTRL,
415 4, 1, 1),
416 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
417 5, 1, 0),
418
419 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
420 0, 3, 0, mic_gain_tlv),
421
422 SOC_DOUBLE_TLV("Lineout Playback Volume",
423 SGTL5000_CHIP_LINE_OUT_VOL,
424 SGTL5000_LINE_OUT_VOL_LEFT_SHIFT,
425 SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT,
426 0x1f, 1,
427 lineout_volume),
428 SOC_SINGLE("Lineout Playback Switch", SGTL5000_CHIP_ANA_CTRL, 8, 1, 1),
429};
430
431/* mute the codec used by alsa core */
432static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
433{
434 struct snd_soc_codec *codec = codec_dai->codec;
435 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
436
437 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
438 adcdac_ctrl, mute ? adcdac_ctrl : 0);
439
440 return 0;
441}
442
443/* set codec format */
444static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
445{
446 struct snd_soc_codec *codec = codec_dai->codec;
447 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
448 u16 i2sctl = 0;
449
450 sgtl5000->master = 0;
451 /*
452 * i2s clock and frame master setting.
453 * ONLY support:
454 * - clock and frame slave,
455 * - clock and frame master
456 */
457 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
458 case SND_SOC_DAIFMT_CBS_CFS:
459 break;
460 case SND_SOC_DAIFMT_CBM_CFM:
461 i2sctl |= SGTL5000_I2S_MASTER;
462 sgtl5000->master = 1;
463 break;
464 default:
465 return -EINVAL;
466 }
467
468 /* setting i2s data format */
469 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
470 case SND_SOC_DAIFMT_DSP_A:
471 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
472 break;
473 case SND_SOC_DAIFMT_DSP_B:
474 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
475 i2sctl |= SGTL5000_I2S_LRALIGN;
476 break;
477 case SND_SOC_DAIFMT_I2S:
478 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
479 break;
480 case SND_SOC_DAIFMT_RIGHT_J:
481 i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT;
482 i2sctl |= SGTL5000_I2S_LRPOL;
483 break;
484 case SND_SOC_DAIFMT_LEFT_J:
485 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
486 i2sctl |= SGTL5000_I2S_LRALIGN;
487 break;
488 default:
489 return -EINVAL;
490 }
491
492 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
493
494 /* Clock inversion */
495 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
496 case SND_SOC_DAIFMT_NB_NF:
497 break;
498 case SND_SOC_DAIFMT_IB_NF:
499 i2sctl |= SGTL5000_I2S_SCLK_INV;
500 break;
501 default:
502 return -EINVAL;
503 }
504
505 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
506
507 return 0;
508}
509
510/* set codec sysclk */
511static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
512 int clk_id, unsigned int freq, int dir)
513{
514 struct snd_soc_codec *codec = codec_dai->codec;
515 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
516
517 switch (clk_id) {
518 case SGTL5000_SYSCLK:
519 sgtl5000->sysclk = freq;
520 break;
521 default:
522 return -EINVAL;
523 }
524
525 return 0;
526}
527
528/*
529 * set clock according to i2s frame clock,
530 * sgtl5000 provides 2 clock sources:
531 * 1. sys_mclk: sample freq can only be configured to
532 * 1/256, 1/384, 1/512 of sys_mclk.
533 * 2. pll: can derive any audio clocks.
534 *
535 * clock setting rules:
536 * 1. in slave mode, only sys_mclk can be used
537 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
538 * and above.
539 * 3. usage of sys_mclk is preferred over pll to save power.
540 */
541static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
542{
543 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
544 int clk_ctl = 0;
545 int sys_fs; /* sample freq */
546
547 /*
548 * sample freq should be divided by frame clock,
549 * if frame clock is lower than 44.1 kHz, sample freq should be set to
550 * 32 kHz or 44.1 kHz.
551 */
552 switch (frame_rate) {
553 case 8000:
554 case 16000:
555 sys_fs = 32000;
556 break;
557 case 11025:
558 case 22050:
559 sys_fs = 44100;
560 break;
561 default:
562 sys_fs = frame_rate;
563 break;
564 }
565
566 /* set divided factor of frame clock */
567 switch (sys_fs / frame_rate) {
568 case 4:
569 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
570 break;
571 case 2:
572 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
573 break;
574 case 1:
575 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
576 break;
577 default:
578 return -EINVAL;
579 }
580
581 /* set the sys_fs according to frame rate */
582 switch (sys_fs) {
583 case 32000:
584 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
585 break;
586 case 44100:
587 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
588 break;
589 case 48000:
590 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
591 break;
592 case 96000:
593 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
594 break;
595 default:
596 dev_err(codec->dev, "frame rate %d not supported\n",
597 frame_rate);
598 return -EINVAL;
599 }
600
601 /*
602 * calculate the divider of mclk/sample_freq,
603 * factor of freq = 96 kHz can only be 256, since mclk is in the range
604 * of 8 MHz - 27 MHz
605 */
606 switch (sgtl5000->sysclk / frame_rate) {
607 case 256:
608 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
609 SGTL5000_MCLK_FREQ_SHIFT;
610 break;
611 case 384:
612 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
613 SGTL5000_MCLK_FREQ_SHIFT;
614 break;
615 case 512:
616 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
617 SGTL5000_MCLK_FREQ_SHIFT;
618 break;
619 default:
620 /* if mclk does not satisfy the divider, use pll */
621 if (sgtl5000->master) {
622 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
623 SGTL5000_MCLK_FREQ_SHIFT;
624 } else {
625 dev_err(codec->dev,
626 "PLL not supported in slave mode\n");
627 dev_err(codec->dev, "%d ratio is not supported. "
628 "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
629 sgtl5000->sysclk / frame_rate);
630 return -EINVAL;
631 }
632 }
633
634 /* if using pll, please check manual 6.4.2 for detail */
635 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
636 u64 out, t;
637 int div2;
638 int pll_ctl;
639 unsigned int in, int_div, frac_div;
640
641 if (sgtl5000->sysclk > 17000000) {
642 div2 = 1;
643 in = sgtl5000->sysclk / 2;
644 } else {
645 div2 = 0;
646 in = sgtl5000->sysclk;
647 }
648 if (sys_fs == 44100)
649 out = 180633600;
650 else
651 out = 196608000;
652 t = do_div(out, in);
653 int_div = out;
654 t *= 2048;
655 do_div(t, in);
656 frac_div = t;
657 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
658 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
659
660 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
661 if (div2)
662 snd_soc_update_bits(codec,
663 SGTL5000_CHIP_CLK_TOP_CTRL,
664 SGTL5000_INPUT_FREQ_DIV2,
665 SGTL5000_INPUT_FREQ_DIV2);
666 else
667 snd_soc_update_bits(codec,
668 SGTL5000_CHIP_CLK_TOP_CTRL,
669 SGTL5000_INPUT_FREQ_DIV2,
670 0);
671
672 /* power up pll */
673 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
674 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
675 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
676
677 /* if using pll, clk_ctrl must be set after pll power up */
678 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
679 } else {
680 /* otherwise, clk_ctrl must be set before pll power down */
681 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
682
683 /* power down pll */
684 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
685 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
686 0);
687 }
688
689 return 0;
690}
691
692/*
693 * Set PCM DAI bit size and sample rate.
694 * input: params_rate, params_fmt
695 */
696static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
697 struct snd_pcm_hw_params *params,
698 struct snd_soc_dai *dai)
699{
700 struct snd_soc_codec *codec = dai->codec;
701 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
702 int channels = params_channels(params);
703 int i2s_ctl = 0;
704 int stereo;
705 int ret;
706
707 /* sysclk should already set */
708 if (!sgtl5000->sysclk) {
709 dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
710 return -EFAULT;
711 }
712
713 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
714 stereo = SGTL5000_DAC_STEREO;
715 else
716 stereo = SGTL5000_ADC_STEREO;
717
718 /* set mono to save power */
719 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
720 channels == 1 ? 0 : stereo);
721
722 /* set codec clock base on lrclk */
723 ret = sgtl5000_set_clock(codec, params_rate(params));
724 if (ret)
725 return ret;
726
727 /* set i2s data format */
728 switch (params_width(params)) {
729 case 16:
730 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
731 return -EINVAL;
732 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
733 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
734 SGTL5000_I2S_SCLKFREQ_SHIFT;
735 break;
736 case 20:
737 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
738 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
739 SGTL5000_I2S_SCLKFREQ_SHIFT;
740 break;
741 case 24:
742 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
743 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
744 SGTL5000_I2S_SCLKFREQ_SHIFT;
745 break;
746 case 32:
747 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
748 return -EINVAL;
749 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
750 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
751 SGTL5000_I2S_SCLKFREQ_SHIFT;
752 break;
753 default:
754 return -EINVAL;
755 }
756
757 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL,
758 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
759 i2s_ctl);
760
761 return 0;
762}
763
764/*
765 * set dac bias
766 * common state changes:
767 * startup:
768 * off --> standby --> prepare --> on
769 * standby --> prepare --> on
770 *
771 * stop:
772 * on --> prepare --> standby
773 */
774static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
775 enum snd_soc_bias_level level)
776{
777 switch (level) {
778 case SND_SOC_BIAS_ON:
779 case SND_SOC_BIAS_PREPARE:
780 case SND_SOC_BIAS_STANDBY:
781 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
782 SGTL5000_REFTOP_POWERUP,
783 SGTL5000_REFTOP_POWERUP);
784 break;
785 case SND_SOC_BIAS_OFF:
786 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
787 SGTL5000_REFTOP_POWERUP, 0);
788 break;
789 }
790
791 return 0;
792}
793
794#define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
795 SNDRV_PCM_FMTBIT_S20_3LE |\
796 SNDRV_PCM_FMTBIT_S24_LE |\
797 SNDRV_PCM_FMTBIT_S32_LE)
798
799static const struct snd_soc_dai_ops sgtl5000_ops = {
800 .hw_params = sgtl5000_pcm_hw_params,
801 .digital_mute = sgtl5000_digital_mute,
802 .set_fmt = sgtl5000_set_dai_fmt,
803 .set_sysclk = sgtl5000_set_dai_sysclk,
804};
805
806static struct snd_soc_dai_driver sgtl5000_dai = {
807 .name = "sgtl5000",
808 .playback = {
809 .stream_name = "Playback",
810 .channels_min = 1,
811 .channels_max = 2,
812 /*
813 * only support 8~48K + 96K,
814 * TODO modify hw_param to support more
815 */
816 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
817 .formats = SGTL5000_FORMATS,
818 },
819 .capture = {
820 .stream_name = "Capture",
821 .channels_min = 1,
822 .channels_max = 2,
823 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
824 .formats = SGTL5000_FORMATS,
825 },
826 .ops = &sgtl5000_ops,
827 .symmetric_rates = 1,
828};
829
830static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
831{
832 switch (reg) {
833 case SGTL5000_CHIP_ID:
834 case SGTL5000_CHIP_ADCDAC_CTRL:
835 case SGTL5000_CHIP_ANA_STATUS:
836 return true;
837 }
838
839 return false;
840}
841
842static bool sgtl5000_readable(struct device *dev, unsigned int reg)
843{
844 switch (reg) {
845 case SGTL5000_CHIP_ID:
846 case SGTL5000_CHIP_DIG_POWER:
847 case SGTL5000_CHIP_CLK_CTRL:
848 case SGTL5000_CHIP_I2S_CTRL:
849 case SGTL5000_CHIP_SSS_CTRL:
850 case SGTL5000_CHIP_ADCDAC_CTRL:
851 case SGTL5000_CHIP_DAC_VOL:
852 case SGTL5000_CHIP_PAD_STRENGTH:
853 case SGTL5000_CHIP_ANA_ADC_CTRL:
854 case SGTL5000_CHIP_ANA_HP_CTRL:
855 case SGTL5000_CHIP_ANA_CTRL:
856 case SGTL5000_CHIP_LINREG_CTRL:
857 case SGTL5000_CHIP_REF_CTRL:
858 case SGTL5000_CHIP_MIC_CTRL:
859 case SGTL5000_CHIP_LINE_OUT_CTRL:
860 case SGTL5000_CHIP_LINE_OUT_VOL:
861 case SGTL5000_CHIP_ANA_POWER:
862 case SGTL5000_CHIP_PLL_CTRL:
863 case SGTL5000_CHIP_CLK_TOP_CTRL:
864 case SGTL5000_CHIP_ANA_STATUS:
865 case SGTL5000_CHIP_SHORT_CTRL:
866 case SGTL5000_CHIP_ANA_TEST2:
867 case SGTL5000_DAP_CTRL:
868 case SGTL5000_DAP_PEQ:
869 case SGTL5000_DAP_BASS_ENHANCE:
870 case SGTL5000_DAP_BASS_ENHANCE_CTRL:
871 case SGTL5000_DAP_AUDIO_EQ:
872 case SGTL5000_DAP_SURROUND:
873 case SGTL5000_DAP_FLT_COEF_ACCESS:
874 case SGTL5000_DAP_COEF_WR_B0_MSB:
875 case SGTL5000_DAP_COEF_WR_B0_LSB:
876 case SGTL5000_DAP_EQ_BASS_BAND0:
877 case SGTL5000_DAP_EQ_BASS_BAND1:
878 case SGTL5000_DAP_EQ_BASS_BAND2:
879 case SGTL5000_DAP_EQ_BASS_BAND3:
880 case SGTL5000_DAP_EQ_BASS_BAND4:
881 case SGTL5000_DAP_MAIN_CHAN:
882 case SGTL5000_DAP_MIX_CHAN:
883 case SGTL5000_DAP_AVC_CTRL:
884 case SGTL5000_DAP_AVC_THRESHOLD:
885 case SGTL5000_DAP_AVC_ATTACK:
886 case SGTL5000_DAP_AVC_DECAY:
887 case SGTL5000_DAP_COEF_WR_B1_MSB:
888 case SGTL5000_DAP_COEF_WR_B1_LSB:
889 case SGTL5000_DAP_COEF_WR_B2_MSB:
890 case SGTL5000_DAP_COEF_WR_B2_LSB:
891 case SGTL5000_DAP_COEF_WR_A1_MSB:
892 case SGTL5000_DAP_COEF_WR_A1_LSB:
893 case SGTL5000_DAP_COEF_WR_A2_MSB:
894 case SGTL5000_DAP_COEF_WR_A2_LSB:
895 return true;
896
897 default:
898 return false;
899 }
900}
901
902/*
903 * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results
904 * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL
905 * The calculatation was done for all possible register values which
906 * is the array index and the following formula: 10^((idx−15)/40) * 100
907 */
908static const u8 vol_quot_table[] = {
909 42, 45, 47, 50, 53, 56, 60, 63,
910 67, 71, 75, 79, 84, 89, 94, 100,
911 106, 112, 119, 126, 133, 141, 150, 158,
912 168, 178, 188, 200, 211, 224, 237, 251
913};
914
915/*
916 * sgtl5000 has 3 internal power supplies:
917 * 1. VAG, normally set to vdda/2
918 * 2. charge pump, set to different value
919 * according to voltage of vdda and vddio
920 * 3. line out VAG, normally set to vddio/2
921 *
922 * and should be set according to:
923 * 1. vddd provided by external or not
924 * 2. vdda and vddio voltage value. > 3.1v or not
925 */
926static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
927{
928 int vddd;
929 int vdda;
930 int vddio;
931 u16 ana_pwr;
932 u16 lreg_ctrl;
933 int vag;
934 int lo_vag;
935 int vol_quot;
936 int lo_vol;
937 size_t i;
938 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
939
940 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
941 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
942 vddd = (sgtl5000->num_supplies > VDDD)
943 ? regulator_get_voltage(sgtl5000->supplies[VDDD].consumer)
944 : LDO_VOLTAGE;
945
946 vdda = vdda / 1000;
947 vddio = vddio / 1000;
948 vddd = vddd / 1000;
949
950 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
951 dev_err(codec->dev, "regulator voltage not set correctly\n");
952
953 return -EINVAL;
954 }
955
956 /* according to datasheet, maximum voltage of supplies */
957 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
958 dev_err(codec->dev,
959 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
960 vdda, vddio, vddd);
961
962 return -EINVAL;
963 }
964
965 /* reset value */
966 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
967 ana_pwr |= SGTL5000_DAC_STEREO |
968 SGTL5000_ADC_STEREO |
969 SGTL5000_REFTOP_POWERUP;
970 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
971
972 if (vddio < 3100 && vdda < 3100) {
973 /* enable internal oscillator used for charge pump */
974 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
975 SGTL5000_INT_OSC_EN,
976 SGTL5000_INT_OSC_EN);
977 /* Enable VDDC charge pump */
978 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
979 } else if (vddio >= 3100 && vdda >= 3100) {
980 ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
981 /* VDDC use VDDIO rail */
982 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
983 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
984 SGTL5000_VDDC_MAN_ASSN_SHIFT;
985 }
986
987 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
988
989 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
990
991 /*
992 * set ADC/DAC VAG to vdda / 2,
993 * should stay in range (0.8v, 1.575v)
994 */
995 vag = vdda / 2;
996 if (vag <= SGTL5000_ANA_GND_BASE)
997 vag = 0;
998 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
999 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1000 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1001 else
1002 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1003
1004 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1005 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
1006
1007 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1008 lo_vag = vddio / 2;
1009 if (lo_vag <= SGTL5000_LINE_OUT_GND_BASE)
1010 lo_vag = 0;
1011 else if (lo_vag >= SGTL5000_LINE_OUT_GND_BASE +
1012 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
1013 lo_vag = SGTL5000_LINE_OUT_GND_MAX;
1014 else
1015 lo_vag = (lo_vag - SGTL5000_LINE_OUT_GND_BASE) /
1016 SGTL5000_LINE_OUT_GND_STP;
1017
1018 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
1019 SGTL5000_LINE_OUT_CURRENT_MASK |
1020 SGTL5000_LINE_OUT_GND_MASK,
1021 lo_vag << SGTL5000_LINE_OUT_GND_SHIFT |
1022 SGTL5000_LINE_OUT_CURRENT_360u <<
1023 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1024
1025 /*
1026 * Set lineout output level in range (0..31)
1027 * the same value is used for right and left channel
1028 *
1029 * Searching for a suitable index solving this formula:
1030 * idx = 40 * log10(vag_val / lo_cagcntrl) + 15
1031 */
1032 vol_quot = (vag * 100) / lo_vag;
1033 lo_vol = 0;
1034 for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) {
1035 if (vol_quot >= vol_quot_table[i])
1036 lo_vol = i;
1037 else
1038 break;
1039 }
1040
1041 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_VOL,
1042 SGTL5000_LINE_OUT_VOL_RIGHT_MASK |
1043 SGTL5000_LINE_OUT_VOL_LEFT_MASK,
1044 lo_vol << SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT |
1045 lo_vol << SGTL5000_LINE_OUT_VOL_LEFT_SHIFT);
1046
1047 return 0;
1048}
1049
1050static int sgtl5000_enable_regulators(struct i2c_client *client)
1051{
1052 int ret;
1053 int i;
1054 int external_vddd = 0;
1055 struct regulator *vddd;
1056 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1057
1058 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1059 sgtl5000->supplies[i].supply = supply_names[i];
1060
1061 vddd = regulator_get_optional(&client->dev, "VDDD");
1062 if (IS_ERR(vddd)) {
1063 /* See if it's just not registered yet */
1064 if (PTR_ERR(vddd) == -EPROBE_DEFER)
1065 return -EPROBE_DEFER;
1066 } else {
1067 external_vddd = 1;
1068 regulator_put(vddd);
1069 }
1070
1071 sgtl5000->num_supplies = ARRAY_SIZE(sgtl5000->supplies)
1072 - 1 + external_vddd;
1073 ret = regulator_bulk_get(&client->dev, sgtl5000->num_supplies,
1074 sgtl5000->supplies);
1075 if (ret)
1076 return ret;
1077
1078 ret = regulator_bulk_enable(sgtl5000->num_supplies,
1079 sgtl5000->supplies);
1080 if (!ret)
1081 usleep_range(10, 20);
1082 else
1083 regulator_bulk_free(sgtl5000->num_supplies,
1084 sgtl5000->supplies);
1085
1086 return ret;
1087}
1088
1089static int sgtl5000_probe(struct snd_soc_codec *codec)
1090{
1091 int ret;
1092 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1093
1094 /* power up sgtl5000 */
1095 ret = sgtl5000_set_power_regs(codec);
1096 if (ret)
1097 goto err;
1098
1099 /* enable small pop, introduce 400ms delay in turning off */
1100 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1101 SGTL5000_SMALL_POP, 1);
1102
1103 /* disable short cut detector */
1104 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1105
1106 /*
1107 * set i2s as default input of sound switch
1108 * TODO: add sound switch to control and dapm widge.
1109 */
1110 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1111 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1112 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1113 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1114
1115 /* enable dac volume ramp by default */
1116 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1117 SGTL5000_DAC_VOL_RAMP_EN |
1118 SGTL5000_DAC_MUTE_RIGHT |
1119 SGTL5000_DAC_MUTE_LEFT);
1120
1121 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
1122
1123 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1124 SGTL5000_HP_ZCD_EN |
1125 SGTL5000_ADC_ZCD_EN);
1126
1127 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
1128 SGTL5000_BIAS_R_MASK,
1129 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
1130
1131 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
1132 SGTL5000_BIAS_VOLT_MASK,
1133 sgtl5000->micbias_voltage << SGTL5000_BIAS_VOLT_SHIFT);
1134 /*
1135 * disable DAP
1136 * TODO:
1137 * Enable DAP in kcontrol and dapm.
1138 */
1139 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1140
1141 return 0;
1142
1143err:
1144 return ret;
1145}
1146
1147static int sgtl5000_remove(struct snd_soc_codec *codec)
1148{
1149 return 0;
1150}
1151
1152static struct snd_soc_codec_driver sgtl5000_driver = {
1153 .probe = sgtl5000_probe,
1154 .remove = sgtl5000_remove,
1155 .set_bias_level = sgtl5000_set_bias_level,
1156 .suspend_bias_off = true,
1157 .component_driver = {
1158 .controls = sgtl5000_snd_controls,
1159 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
1160 .dapm_widgets = sgtl5000_dapm_widgets,
1161 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
1162 .dapm_routes = sgtl5000_dapm_routes,
1163 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
1164 },
1165};
1166
1167static const struct regmap_config sgtl5000_regmap = {
1168 .reg_bits = 16,
1169 .val_bits = 16,
1170 .reg_stride = 2,
1171
1172 .max_register = SGTL5000_MAX_REG_OFFSET,
1173 .volatile_reg = sgtl5000_volatile,
1174 .readable_reg = sgtl5000_readable,
1175
1176 .cache_type = REGCACHE_RBTREE,
1177 .reg_defaults = sgtl5000_reg_defaults,
1178 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
1179};
1180
1181/*
1182 * Write all the default values from sgtl5000_reg_defaults[] array into the
1183 * sgtl5000 registers, to make sure we always start with the sane registers
1184 * values as stated in the datasheet.
1185 *
1186 * Since sgtl5000 does not have a reset line, nor a reset command in software,
1187 * we follow this approach to guarantee we always start from the default values
1188 * and avoid problems like, not being able to probe after an audio playback
1189 * followed by a system reset or a 'reboot' command in Linux
1190 */
1191static void sgtl5000_fill_defaults(struct i2c_client *client)
1192{
1193 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1194 int i, ret, val, index;
1195
1196 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
1197 val = sgtl5000_reg_defaults[i].def;
1198 index = sgtl5000_reg_defaults[i].reg;
1199 ret = regmap_write(sgtl5000->regmap, index, val);
1200 if (ret)
1201 dev_err(&client->dev,
1202 "%s: error %d setting reg 0x%02x to 0x%04x\n",
1203 __func__, ret, index, val);
1204 }
1205}
1206
1207static int sgtl5000_i2c_probe(struct i2c_client *client,
1208 const struct i2c_device_id *id)
1209{
1210 struct sgtl5000_priv *sgtl5000;
1211 int ret, reg, rev;
1212 struct device_node *np = client->dev.of_node;
1213 u32 value;
1214 u16 ana_pwr;
1215
1216 sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL);
1217 if (!sgtl5000)
1218 return -ENOMEM;
1219
1220 i2c_set_clientdata(client, sgtl5000);
1221
1222 ret = sgtl5000_enable_regulators(client);
1223 if (ret)
1224 return ret;
1225
1226 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
1227 if (IS_ERR(sgtl5000->regmap)) {
1228 ret = PTR_ERR(sgtl5000->regmap);
1229 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
1230 goto disable_regs;
1231 }
1232
1233 sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
1234 if (IS_ERR(sgtl5000->mclk)) {
1235 ret = PTR_ERR(sgtl5000->mclk);
1236 dev_err(&client->dev, "Failed to get mclock: %d\n", ret);
1237 /* Defer the probe to see if the clk will be provided later */
1238 if (ret == -ENOENT)
1239 ret = -EPROBE_DEFER;
1240 goto disable_regs;
1241 }
1242
1243 ret = clk_prepare_enable(sgtl5000->mclk);
1244 if (ret) {
1245 dev_err(&client->dev, "Error enabling clock %d\n", ret);
1246 goto disable_regs;
1247 }
1248
1249 /* Need 8 clocks before I2C accesses */
1250 udelay(1);
1251
1252 /* read chip information */
1253 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®);
1254 if (ret) {
1255 dev_err(&client->dev, "Error reading chip id %d\n", ret);
1256 goto disable_clk;
1257 }
1258
1259 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1260 SGTL5000_PARTID_PART_ID) {
1261 dev_err(&client->dev,
1262 "Device with ID register %x is not a sgtl5000\n", reg);
1263 ret = -ENODEV;
1264 goto disable_clk;
1265 }
1266
1267 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1268 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
1269 sgtl5000->revision = rev;
1270
1271 /* reconfigure the clocks in case we're using the PLL */
1272 ret = regmap_write(sgtl5000->regmap,
1273 SGTL5000_CHIP_CLK_CTRL,
1274 SGTL5000_CHIP_CLK_CTRL_DEFAULT);
1275 if (ret)
1276 dev_err(&client->dev,
1277 "Error %d initializing CHIP_CLK_CTRL\n", ret);
1278
1279 /* Follow section 2.2.1.1 of AN3663 */
1280 ana_pwr = SGTL5000_ANA_POWER_DEFAULT;
1281 if (sgtl5000->num_supplies <= VDDD) {
1282 /* internal VDDD at 1.2V */
1283 ret = regmap_update_bits(sgtl5000->regmap,
1284 SGTL5000_CHIP_LINREG_CTRL,
1285 SGTL5000_LINREG_VDDD_MASK,
1286 LINREG_VDDD);
1287 if (ret)
1288 dev_err(&client->dev,
1289 "Error %d setting LINREG_VDDD\n", ret);
1290
1291 ana_pwr |= SGTL5000_LINEREG_D_POWERUP;
1292 dev_info(&client->dev,
1293 "Using internal LDO instead of VDDD: check ER1\n");
1294 } else {
1295 /* using external LDO for VDDD
1296 * Clear startup powerup and simple powerup
1297 * bits to save power
1298 */
1299 ana_pwr &= ~(SGTL5000_STARTUP_POWERUP
1300 | SGTL5000_LINREG_SIMPLE_POWERUP);
1301 dev_dbg(&client->dev, "Using external VDDD\n");
1302 }
1303 ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1304 if (ret)
1305 dev_err(&client->dev,
1306 "Error %d setting CHIP_ANA_POWER to %04x\n",
1307 ret, ana_pwr);
1308
1309 if (np) {
1310 if (!of_property_read_u32(np,
1311 "micbias-resistor-k-ohms", &value)) {
1312 switch (value) {
1313 case SGTL5000_MICBIAS_OFF:
1314 sgtl5000->micbias_resistor = 0;
1315 break;
1316 case SGTL5000_MICBIAS_2K:
1317 sgtl5000->micbias_resistor = 1;
1318 break;
1319 case SGTL5000_MICBIAS_4K:
1320 sgtl5000->micbias_resistor = 2;
1321 break;
1322 case SGTL5000_MICBIAS_8K:
1323 sgtl5000->micbias_resistor = 3;
1324 break;
1325 default:
1326 sgtl5000->micbias_resistor = 2;
1327 dev_err(&client->dev,
1328 "Unsuitable MicBias resistor\n");
1329 }
1330 } else {
1331 /* default is 4Kohms */
1332 sgtl5000->micbias_resistor = 2;
1333 }
1334 if (!of_property_read_u32(np,
1335 "micbias-voltage-m-volts", &value)) {
1336 /* 1250mV => 0 */
1337 /* steps of 250mV */
1338 if ((value >= 1250) && (value <= 3000))
1339 sgtl5000->micbias_voltage = (value / 250) - 5;
1340 else {
1341 sgtl5000->micbias_voltage = 0;
1342 dev_err(&client->dev,
1343 "Unsuitable MicBias voltage\n");
1344 }
1345 } else {
1346 sgtl5000->micbias_voltage = 0;
1347 }
1348 }
1349
1350 /* Ensure sgtl5000 will start with sane register values */
1351 sgtl5000_fill_defaults(client);
1352
1353 ret = snd_soc_register_codec(&client->dev,
1354 &sgtl5000_driver, &sgtl5000_dai, 1);
1355 if (ret)
1356 goto disable_clk;
1357
1358 return 0;
1359
1360disable_clk:
1361 clk_disable_unprepare(sgtl5000->mclk);
1362
1363disable_regs:
1364 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1365 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1366
1367 return ret;
1368}
1369
1370static int sgtl5000_i2c_remove(struct i2c_client *client)
1371{
1372 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1373
1374 snd_soc_unregister_codec(&client->dev);
1375 clk_disable_unprepare(sgtl5000->mclk);
1376 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1377 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1378
1379 return 0;
1380}
1381
1382static const struct i2c_device_id sgtl5000_id[] = {
1383 {"sgtl5000", 0},
1384 {},
1385};
1386
1387MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1388
1389static const struct of_device_id sgtl5000_dt_ids[] = {
1390 { .compatible = "fsl,sgtl5000", },
1391 { /* sentinel */ }
1392};
1393MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
1394
1395static struct i2c_driver sgtl5000_i2c_driver = {
1396 .driver = {
1397 .name = "sgtl5000",
1398 .of_match_table = sgtl5000_dt_ids,
1399 },
1400 .probe = sgtl5000_i2c_probe,
1401 .remove = sgtl5000_i2c_remove,
1402 .id_table = sgtl5000_id,
1403};
1404
1405module_i2c_driver(sgtl5000_i2c_driver);
1406
1407MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1408MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
1409MODULE_LICENSE("GPL");