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1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2/* QLogic qed NIC Driver
3 * Copyright (c) 2015-2017 QLogic Corporation
4 * Copyright (c) 2019-2020 Marvell International Ltd.
5 */
6
7#include <linux/types.h>
8#include <asm/byteorder.h>
9#include <linux/io.h>
10#include <linux/bitops.h>
11#include <linux/delay.h>
12#include <linux/dma-mapping.h>
13#include <linux/errno.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/pci.h>
17#include <linux/slab.h>
18#include <linux/string.h>
19#include "qed.h"
20#include "qed_hsi.h"
21#include "qed_hw.h"
22#include "qed_init_ops.h"
23#include "qed_int.h"
24#include "qed_mcp.h"
25#include "qed_reg_addr.h"
26#include "qed_sp.h"
27#include "qed_sriov.h"
28#include "qed_vf.h"
29
30struct qed_pi_info {
31 qed_int_comp_cb_t comp_cb;
32 void *cookie;
33};
34
35struct qed_sb_sp_info {
36 struct qed_sb_info sb_info;
37
38 /* per protocol index data */
39 struct qed_pi_info pi_info_arr[PIS_PER_SB];
40};
41
42enum qed_attention_type {
43 QED_ATTN_TYPE_ATTN,
44 QED_ATTN_TYPE_PARITY,
45};
46
47#define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
48 ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
49
50struct aeu_invert_reg_bit {
51 char bit_name[30];
52
53#define ATTENTION_PARITY (1 << 0)
54
55#define ATTENTION_LENGTH_MASK (0x00000ff0)
56#define ATTENTION_LENGTH_SHIFT (4)
57#define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \
58 ATTENTION_LENGTH_SHIFT)
59#define ATTENTION_SINGLE BIT(ATTENTION_LENGTH_SHIFT)
60#define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY)
61#define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \
62 ATTENTION_PARITY)
63
64/* Multiple bits start with this offset */
65#define ATTENTION_OFFSET_MASK (0x000ff000)
66#define ATTENTION_OFFSET_SHIFT (12)
67
68#define ATTENTION_BB_MASK (0x00700000)
69#define ATTENTION_BB_SHIFT (20)
70#define ATTENTION_BB(value) (value << ATTENTION_BB_SHIFT)
71#define ATTENTION_BB_DIFFERENT BIT(23)
72
73#define ATTENTION_CLEAR_ENABLE BIT(28)
74 unsigned int flags;
75
76 /* Callback to call if attention will be triggered */
77 int (*cb)(struct qed_hwfn *p_hwfn);
78
79 enum block_id block_index;
80};
81
82struct aeu_invert_reg {
83 struct aeu_invert_reg_bit bits[32];
84};
85
86#define MAX_ATTN_GRPS (8)
87#define NUM_ATTN_REGS (9)
88
89/* Specific HW attention callbacks */
90static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn)
91{
92 u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE);
93
94 /* This might occur on certain instances; Log it once then mask it */
95 DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n",
96 tmp);
97 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK,
98 0xffffffff);
99
100 return 0;
101}
102
103#define QED_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1)
104#define ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1)
105#define ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0)
106#define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0xf)
107#define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1)
108#define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x1)
109#define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5)
110#define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0xff)
111#define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6)
112#define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0xf)
113#define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14)
114#define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0xff)
115#define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18)
116static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn)
117{
118 u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
119 PSWHST_REG_INCORRECT_ACCESS_VALID);
120
121 if (tmp & QED_PSWHST_ATTENTION_INCORRECT_ACCESS) {
122 u32 addr, data, length;
123
124 addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
125 PSWHST_REG_INCORRECT_ACCESS_ADDRESS);
126 data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
127 PSWHST_REG_INCORRECT_ACCESS_DATA);
128 length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
129 PSWHST_REG_INCORRECT_ACCESS_LENGTH);
130
131 DP_INFO(p_hwfn->cdev,
132 "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n",
133 addr, length,
134 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_PF_ID),
135 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_VF_ID),
136 (u8) GET_FIELD(data,
137 ATTENTION_INCORRECT_ACCESS_VF_VALID),
138 (u8) GET_FIELD(data,
139 ATTENTION_INCORRECT_ACCESS_CLIENT),
140 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_WR),
141 (u8) GET_FIELD(data,
142 ATTENTION_INCORRECT_ACCESS_BYTE_EN),
143 data);
144 }
145
146 return 0;
147}
148
149#define QED_GRC_ATTENTION_VALID_BIT (1 << 0)
150#define QED_GRC_ATTENTION_ADDRESS_MASK (0x7fffff)
151#define QED_GRC_ATTENTION_ADDRESS_SHIFT (0)
152#define QED_GRC_ATTENTION_RDWR_BIT (1 << 23)
153#define QED_GRC_ATTENTION_MASTER_MASK (0xf)
154#define QED_GRC_ATTENTION_MASTER_SHIFT (24)
155#define QED_GRC_ATTENTION_PF_MASK (0xf)
156#define QED_GRC_ATTENTION_PF_SHIFT (0)
157#define QED_GRC_ATTENTION_VF_MASK (0xff)
158#define QED_GRC_ATTENTION_VF_SHIFT (4)
159#define QED_GRC_ATTENTION_PRIV_MASK (0x3)
160#define QED_GRC_ATTENTION_PRIV_SHIFT (14)
161#define QED_GRC_ATTENTION_PRIV_VF (0)
162static const char *attn_master_to_str(u8 master)
163{
164 switch (master) {
165 case 1: return "PXP";
166 case 2: return "MCP";
167 case 3: return "MSDM";
168 case 4: return "PSDM";
169 case 5: return "YSDM";
170 case 6: return "USDM";
171 case 7: return "TSDM";
172 case 8: return "XSDM";
173 case 9: return "DBU";
174 case 10: return "DMAE";
175 default:
176 return "Unknown";
177 }
178}
179
180static int qed_grc_attn_cb(struct qed_hwfn *p_hwfn)
181{
182 u32 tmp, tmp2;
183
184 /* We've already cleared the timeout interrupt register, so we learn
185 * of interrupts via the validity register
186 */
187 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
188 GRC_REG_TIMEOUT_ATTN_ACCESS_VALID);
189 if (!(tmp & QED_GRC_ATTENTION_VALID_BIT))
190 goto out;
191
192 /* Read the GRC timeout information */
193 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
194 GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0);
195 tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
196 GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1);
197
198 DP_INFO(p_hwfn->cdev,
199 "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n",
200 tmp2, tmp,
201 (tmp & QED_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from",
202 GET_FIELD(tmp, QED_GRC_ATTENTION_ADDRESS) << 2,
203 attn_master_to_str(GET_FIELD(tmp, QED_GRC_ATTENTION_MASTER)),
204 GET_FIELD(tmp2, QED_GRC_ATTENTION_PF),
205 (GET_FIELD(tmp2, QED_GRC_ATTENTION_PRIV) ==
206 QED_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant)",
207 GET_FIELD(tmp2, QED_GRC_ATTENTION_VF));
208
209out:
210 /* Regardles of anything else, clean the validity bit */
211 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,
212 GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0);
213 return 0;
214}
215
216#define PGLUE_ATTENTION_VALID (1 << 29)
217#define PGLUE_ATTENTION_RD_VALID (1 << 26)
218#define PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf)
219#define PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20)
220#define PGLUE_ATTENTION_DETAILS_VF_VALID_MASK (0x1)
221#define PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT (19)
222#define PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff)
223#define PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24)
224#define PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK (0x1)
225#define PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT (21)
226#define PGLUE_ATTENTION_DETAILS2_BME_MASK (0x1)
227#define PGLUE_ATTENTION_DETAILS2_BME_SHIFT (22)
228#define PGLUE_ATTENTION_DETAILS2_FID_EN_MASK (0x1)
229#define PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT (23)
230#define PGLUE_ATTENTION_ICPL_VALID (1 << 23)
231#define PGLUE_ATTENTION_ZLR_VALID (1 << 25)
232#define PGLUE_ATTENTION_ILT_VALID (1 << 23)
233
234int qed_pglueb_rbc_attn_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
235 bool hw_init)
236{
237 char msg[256];
238 u32 tmp;
239
240 tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS2);
241 if (tmp & PGLUE_ATTENTION_VALID) {
242 u32 addr_lo, addr_hi, details;
243
244 addr_lo = qed_rd(p_hwfn, p_ptt,
245 PGLUE_B_REG_TX_ERR_WR_ADD_31_0);
246 addr_hi = qed_rd(p_hwfn, p_ptt,
247 PGLUE_B_REG_TX_ERR_WR_ADD_63_32);
248 details = qed_rd(p_hwfn, p_ptt,
249 PGLUE_B_REG_TX_ERR_WR_DETAILS);
250
251 snprintf(msg, sizeof(msg),
252 "Illegal write by chip to [%08x:%08x] blocked.\n"
253 "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n"
254 "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]",
255 addr_hi, addr_lo, details,
256 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID),
257 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID),
258 !!GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VF_VALID),
259 tmp,
260 !!GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_WAS_ERR),
261 !!GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_BME),
262 !!GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_FID_EN));
263
264 if (hw_init)
265 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "%s\n", msg);
266 else
267 DP_NOTICE(p_hwfn, "%s\n", msg);
268 }
269
270 tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS2);
271 if (tmp & PGLUE_ATTENTION_RD_VALID) {
272 u32 addr_lo, addr_hi, details;
273
274 addr_lo = qed_rd(p_hwfn, p_ptt,
275 PGLUE_B_REG_TX_ERR_RD_ADD_31_0);
276 addr_hi = qed_rd(p_hwfn, p_ptt,
277 PGLUE_B_REG_TX_ERR_RD_ADD_63_32);
278 details = qed_rd(p_hwfn, p_ptt,
279 PGLUE_B_REG_TX_ERR_RD_DETAILS);
280
281 DP_NOTICE(p_hwfn,
282 "Illegal read by chip from [%08x:%08x] blocked.\n"
283 "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n"
284 "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
285 addr_hi, addr_lo, details,
286 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID),
287 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID),
288 GET_FIELD(details,
289 PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0,
290 tmp,
291 GET_FIELD(tmp,
292 PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0,
293 GET_FIELD(tmp,
294 PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0,
295 GET_FIELD(tmp,
296 PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0);
297 }
298
299 tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL);
300 if (tmp & PGLUE_ATTENTION_ICPL_VALID) {
301 snprintf(msg, sizeof(msg), "ICPL error - %08x", tmp);
302
303 if (hw_init)
304 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "%s\n", msg);
305 else
306 DP_NOTICE(p_hwfn, "%s\n", msg);
307 }
308
309 tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS);
310 if (tmp & PGLUE_ATTENTION_ZLR_VALID) {
311 u32 addr_hi, addr_lo;
312
313 addr_lo = qed_rd(p_hwfn, p_ptt,
314 PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0);
315 addr_hi = qed_rd(p_hwfn, p_ptt,
316 PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32);
317
318 DP_NOTICE(p_hwfn, "ZLR error - %08x [Address %08x:%08x]\n",
319 tmp, addr_hi, addr_lo);
320 }
321
322 tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_DETAILS2);
323 if (tmp & PGLUE_ATTENTION_ILT_VALID) {
324 u32 addr_hi, addr_lo, details;
325
326 addr_lo = qed_rd(p_hwfn, p_ptt,
327 PGLUE_B_REG_VF_ILT_ERR_ADD_31_0);
328 addr_hi = qed_rd(p_hwfn, p_ptt,
329 PGLUE_B_REG_VF_ILT_ERR_ADD_63_32);
330 details = qed_rd(p_hwfn, p_ptt,
331 PGLUE_B_REG_VF_ILT_ERR_DETAILS);
332
333 DP_NOTICE(p_hwfn,
334 "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n",
335 details, tmp, addr_hi, addr_lo);
336 }
337
338 /* Clear the indications */
339 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_LATCHED_ERRORS_CLR, BIT(2));
340
341 return 0;
342}
343
344static int qed_pglueb_rbc_attn_cb(struct qed_hwfn *p_hwfn)
345{
346 return qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt, false);
347}
348
349static int qed_fw_assertion(struct qed_hwfn *p_hwfn)
350{
351 qed_hw_err_notify(p_hwfn, p_hwfn->p_dpc_ptt, QED_HW_ERR_FW_ASSERT,
352 "FW assertion!\n");
353
354 /* Clear assert indications */
355 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MISC_REG_AEU_GENERAL_ATTN_32, 0);
356
357 return -EINVAL;
358}
359
360static int qed_general_attention_35(struct qed_hwfn *p_hwfn)
361{
362 DP_INFO(p_hwfn, "General attention 35!\n");
363
364 return 0;
365}
366
367#define QED_DORQ_ATTENTION_REASON_MASK (0xfffff)
368#define QED_DORQ_ATTENTION_OPAQUE_MASK (0xffff)
369#define QED_DORQ_ATTENTION_OPAQUE_SHIFT (0x0)
370#define QED_DORQ_ATTENTION_SIZE_MASK (0x7f)
371#define QED_DORQ_ATTENTION_SIZE_SHIFT (16)
372
373#define QED_DB_REC_COUNT 1000
374#define QED_DB_REC_INTERVAL 100
375
376static int qed_db_rec_flush_queue(struct qed_hwfn *p_hwfn,
377 struct qed_ptt *p_ptt)
378{
379 u32 count = QED_DB_REC_COUNT;
380 u32 usage = 1;
381
382 /* Flush any pending (e)dpms as they may never arrive */
383 qed_wr(p_hwfn, p_ptt, DORQ_REG_DPM_FORCE_ABORT, 0x1);
384
385 /* wait for usage to zero or count to run out. This is necessary since
386 * EDPM doorbell transactions can take multiple 64b cycles, and as such
387 * can "split" over the pci. Possibly, the doorbell drop can happen with
388 * half an EDPM in the queue and other half dropped. Another EDPM
389 * doorbell to the same address (from doorbell recovery mechanism or
390 * from the doorbelling entity) could have first half dropped and second
391 * half interpreted as continuation of the first. To prevent such
392 * malformed doorbells from reaching the device, flush the queue before
393 * releasing the overflow sticky indication.
394 */
395 while (count-- && usage) {
396 usage = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_USAGE_CNT);
397 udelay(QED_DB_REC_INTERVAL);
398 }
399
400 /* should have been depleted by now */
401 if (usage) {
402 DP_NOTICE(p_hwfn->cdev,
403 "DB recovery: doorbell usage failed to zero after %d usec. usage was %x\n",
404 QED_DB_REC_INTERVAL * QED_DB_REC_COUNT, usage);
405 return -EBUSY;
406 }
407
408 return 0;
409}
410
411int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
412{
413 u32 attn_ovfl, cur_ovfl;
414 int rc;
415
416 attn_ovfl = test_and_clear_bit(QED_OVERFLOW_BIT,
417 &p_hwfn->db_recovery_info.overflow);
418 cur_ovfl = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY);
419 if (!cur_ovfl && !attn_ovfl)
420 return 0;
421
422 DP_NOTICE(p_hwfn, "PF Overflow sticky: attn %u current %u\n",
423 attn_ovfl, cur_ovfl);
424
425 if (cur_ovfl && !p_hwfn->db_bar_no_edpm) {
426 rc = qed_db_rec_flush_queue(p_hwfn, p_ptt);
427 if (rc)
428 return rc;
429 }
430
431 /* Release overflow sticky indication (stop silently dropping everything) */
432 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0);
433
434 /* Repeat all last doorbells (doorbell drop recovery) */
435 qed_db_recovery_execute(p_hwfn);
436
437 return 0;
438}
439
440static void qed_dorq_attn_overflow(struct qed_hwfn *p_hwfn)
441{
442 struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt;
443 u32 overflow;
444 int rc;
445
446 overflow = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY);
447 if (!overflow)
448 goto out;
449
450 /* Run PF doorbell recovery in next periodic handler */
451 set_bit(QED_OVERFLOW_BIT, &p_hwfn->db_recovery_info.overflow);
452
453 if (!p_hwfn->db_bar_no_edpm) {
454 rc = qed_db_rec_flush_queue(p_hwfn, p_ptt);
455 if (rc)
456 goto out;
457 }
458
459 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0);
460out:
461 /* Schedule the handler even if overflow was not detected */
462 qed_periodic_db_rec_start(p_hwfn);
463}
464
465static int qed_dorq_attn_int_sts(struct qed_hwfn *p_hwfn)
466{
467 u32 int_sts, first_drop_reason, details, address, all_drops_reason;
468 struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt;
469
470 int_sts = qed_rd(p_hwfn, p_ptt, DORQ_REG_INT_STS);
471 if (int_sts == 0xdeadbeaf) {
472 DP_NOTICE(p_hwfn->cdev,
473 "DORQ is being reset, skipping int_sts handler\n");
474
475 return 0;
476 }
477
478 /* int_sts may be zero since all PFs were interrupted for doorbell
479 * overflow but another one already handled it. Can abort here. If
480 * This PF also requires overflow recovery we will be interrupted again.
481 * The masked almost full indication may also be set. Ignoring.
482 */
483 if (!(int_sts & ~DORQ_REG_INT_STS_DORQ_FIFO_AFULL))
484 return 0;
485
486 DP_NOTICE(p_hwfn->cdev, "DORQ attention. int_sts was %x\n", int_sts);
487
488 /* check if db_drop or overflow happened */
489 if (int_sts & (DORQ_REG_INT_STS_DB_DROP |
490 DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR)) {
491 /* Obtain data about db drop/overflow */
492 first_drop_reason = qed_rd(p_hwfn, p_ptt,
493 DORQ_REG_DB_DROP_REASON) &
494 QED_DORQ_ATTENTION_REASON_MASK;
495 details = qed_rd(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS);
496 address = qed_rd(p_hwfn, p_ptt,
497 DORQ_REG_DB_DROP_DETAILS_ADDRESS);
498 all_drops_reason = qed_rd(p_hwfn, p_ptt,
499 DORQ_REG_DB_DROP_DETAILS_REASON);
500
501 /* Log info */
502 DP_NOTICE(p_hwfn->cdev,
503 "Doorbell drop occurred\n"
504 "Address\t\t0x%08x\t(second BAR address)\n"
505 "FID\t\t0x%04x\t\t(Opaque FID)\n"
506 "Size\t\t0x%04x\t\t(in bytes)\n"
507 "1st drop reason\t0x%08x\t(details on first drop since last handling)\n"
508 "Sticky reasons\t0x%08x\t(all drop reasons since last handling)\n",
509 address,
510 GET_FIELD(details, QED_DORQ_ATTENTION_OPAQUE),
511 GET_FIELD(details, QED_DORQ_ATTENTION_SIZE) * 4,
512 first_drop_reason, all_drops_reason);
513
514 /* Clear the doorbell drop details and prepare for next drop */
515 qed_wr(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS_REL, 0);
516
517 /* Mark interrupt as handled (note: even if drop was due to a different
518 * reason than overflow we mark as handled)
519 */
520 qed_wr(p_hwfn,
521 p_ptt,
522 DORQ_REG_INT_STS_WR,
523 DORQ_REG_INT_STS_DB_DROP |
524 DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR);
525
526 /* If there are no indications other than drop indications, success */
527 if ((int_sts & ~(DORQ_REG_INT_STS_DB_DROP |
528 DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR |
529 DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) == 0)
530 return 0;
531 }
532
533 /* Some other indication was present - non recoverable */
534 DP_INFO(p_hwfn, "DORQ fatal attention\n");
535
536 return -EINVAL;
537}
538
539static int qed_dorq_attn_cb(struct qed_hwfn *p_hwfn)
540{
541 if (p_hwfn->cdev->recov_in_prog)
542 return 0;
543
544 p_hwfn->db_recovery_info.dorq_attn = true;
545 qed_dorq_attn_overflow(p_hwfn);
546
547 return qed_dorq_attn_int_sts(p_hwfn);
548}
549
550static void qed_dorq_attn_handler(struct qed_hwfn *p_hwfn)
551{
552 if (p_hwfn->db_recovery_info.dorq_attn)
553 goto out;
554
555 /* Call DORQ callback if the attention was missed */
556 qed_dorq_attn_cb(p_hwfn);
557out:
558 p_hwfn->db_recovery_info.dorq_attn = false;
559}
560
561/* Instead of major changes to the data-structure, we have a some 'special'
562 * identifiers for sources that changed meaning between adapters.
563 */
564enum aeu_invert_reg_special_type {
565 AEU_INVERT_REG_SPECIAL_CNIG_0,
566 AEU_INVERT_REG_SPECIAL_CNIG_1,
567 AEU_INVERT_REG_SPECIAL_CNIG_2,
568 AEU_INVERT_REG_SPECIAL_CNIG_3,
569 AEU_INVERT_REG_SPECIAL_MAX,
570};
571
572static struct aeu_invert_reg_bit
573aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = {
574 {"CNIG port 0", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
575 {"CNIG port 1", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
576 {"CNIG port 2", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
577 {"CNIG port 3", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
578};
579
580/* Notice aeu_invert_reg must be defined in the same order of bits as HW; */
581static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = {
582 {
583 { /* After Invert 1 */
584 {"GPIO0 function%d",
585 (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID},
586 }
587 },
588
589 {
590 { /* After Invert 2 */
591 {"PGLUE config_space", ATTENTION_SINGLE,
592 NULL, MAX_BLOCK_ID},
593 {"PGLUE misc_flr", ATTENTION_SINGLE,
594 NULL, MAX_BLOCK_ID},
595 {"PGLUE B RBC", ATTENTION_PAR_INT,
596 qed_pglueb_rbc_attn_cb, BLOCK_PGLUE_B},
597 {"PGLUE misc_mctp", ATTENTION_SINGLE,
598 NULL, MAX_BLOCK_ID},
599 {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
600 {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
601 {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
602 {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) |
603 (1 << ATTENTION_OFFSET_SHIFT),
604 NULL, MAX_BLOCK_ID},
605 {"PCIE glue/PXP VPD %d",
606 (16 << ATTENTION_LENGTH_SHIFT), NULL, BLOCK_PGLCS},
607 }
608 },
609
610 {
611 { /* After Invert 3 */
612 {"General Attention %d",
613 (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID},
614 }
615 },
616
617 {
618 { /* After Invert 4 */
619 {"General Attention 32", ATTENTION_SINGLE |
620 ATTENTION_CLEAR_ENABLE, qed_fw_assertion,
621 MAX_BLOCK_ID},
622 {"General Attention %d",
623 (2 << ATTENTION_LENGTH_SHIFT) |
624 (33 << ATTENTION_OFFSET_SHIFT), NULL, MAX_BLOCK_ID},
625 {"General Attention 35", ATTENTION_SINGLE |
626 ATTENTION_CLEAR_ENABLE, qed_general_attention_35,
627 MAX_BLOCK_ID},
628 {"NWS Parity",
629 ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
630 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0),
631 NULL, BLOCK_NWS},
632 {"NWS Interrupt",
633 ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
634 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1),
635 NULL, BLOCK_NWS},
636 {"NWM Parity",
637 ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
638 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2),
639 NULL, BLOCK_NWM},
640 {"NWM Interrupt",
641 ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
642 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3),
643 NULL, BLOCK_NWM},
644 {"MCP CPU", ATTENTION_SINGLE,
645 qed_mcp_attn_cb, MAX_BLOCK_ID},
646 {"MCP Watchdog timer", ATTENTION_SINGLE,
647 NULL, MAX_BLOCK_ID},
648 {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
649 {"AVS stop status ready", ATTENTION_SINGLE,
650 NULL, MAX_BLOCK_ID},
651 {"MSTAT", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID},
652 {"MSTAT per-path", ATTENTION_PAR_INT,
653 NULL, MAX_BLOCK_ID},
654 {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT),
655 NULL, MAX_BLOCK_ID},
656 {"NIG", ATTENTION_PAR_INT, NULL, BLOCK_NIG},
657 {"BMB/OPTE/MCP", ATTENTION_PAR_INT, NULL, BLOCK_BMB},
658 {"BTB", ATTENTION_PAR_INT, NULL, BLOCK_BTB},
659 {"BRB", ATTENTION_PAR_INT, NULL, BLOCK_BRB},
660 {"PRS", ATTENTION_PAR_INT, NULL, BLOCK_PRS},
661 }
662 },
663
664 {
665 { /* After Invert 5 */
666 {"SRC", ATTENTION_PAR_INT, NULL, BLOCK_SRC},
667 {"PB Client1", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB1},
668 {"PB Client2", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB2},
669 {"RPB", ATTENTION_PAR_INT, NULL, BLOCK_RPB},
670 {"PBF", ATTENTION_PAR_INT, NULL, BLOCK_PBF},
671 {"QM", ATTENTION_PAR_INT, NULL, BLOCK_QM},
672 {"TM", ATTENTION_PAR_INT, NULL, BLOCK_TM},
673 {"MCM", ATTENTION_PAR_INT, NULL, BLOCK_MCM},
674 {"MSDM", ATTENTION_PAR_INT, NULL, BLOCK_MSDM},
675 {"MSEM", ATTENTION_PAR_INT, NULL, BLOCK_MSEM},
676 {"PCM", ATTENTION_PAR_INT, NULL, BLOCK_PCM},
677 {"PSDM", ATTENTION_PAR_INT, NULL, BLOCK_PSDM},
678 {"PSEM", ATTENTION_PAR_INT, NULL, BLOCK_PSEM},
679 {"TCM", ATTENTION_PAR_INT, NULL, BLOCK_TCM},
680 {"TSDM", ATTENTION_PAR_INT, NULL, BLOCK_TSDM},
681 {"TSEM", ATTENTION_PAR_INT, NULL, BLOCK_TSEM},
682 }
683 },
684
685 {
686 { /* After Invert 6 */
687 {"UCM", ATTENTION_PAR_INT, NULL, BLOCK_UCM},
688 {"USDM", ATTENTION_PAR_INT, NULL, BLOCK_USDM},
689 {"USEM", ATTENTION_PAR_INT, NULL, BLOCK_USEM},
690 {"XCM", ATTENTION_PAR_INT, NULL, BLOCK_XCM},
691 {"XSDM", ATTENTION_PAR_INT, NULL, BLOCK_XSDM},
692 {"XSEM", ATTENTION_PAR_INT, NULL, BLOCK_XSEM},
693 {"YCM", ATTENTION_PAR_INT, NULL, BLOCK_YCM},
694 {"YSDM", ATTENTION_PAR_INT, NULL, BLOCK_YSDM},
695 {"YSEM", ATTENTION_PAR_INT, NULL, BLOCK_YSEM},
696 {"XYLD", ATTENTION_PAR_INT, NULL, BLOCK_XYLD},
697 {"TMLD", ATTENTION_PAR_INT, NULL, BLOCK_TMLD},
698 {"MYLD", ATTENTION_PAR_INT, NULL, BLOCK_MULD},
699 {"YULD", ATTENTION_PAR_INT, NULL, BLOCK_YULD},
700 {"DORQ", ATTENTION_PAR_INT,
701 qed_dorq_attn_cb, BLOCK_DORQ},
702 {"DBG", ATTENTION_PAR_INT, NULL, BLOCK_DBG},
703 {"IPC", ATTENTION_PAR_INT, NULL, BLOCK_IPC},
704 }
705 },
706
707 {
708 { /* After Invert 7 */
709 {"CCFC", ATTENTION_PAR_INT, NULL, BLOCK_CCFC},
710 {"CDU", ATTENTION_PAR_INT, NULL, BLOCK_CDU},
711 {"DMAE", ATTENTION_PAR_INT, NULL, BLOCK_DMAE},
712 {"IGU", ATTENTION_PAR_INT, NULL, BLOCK_IGU},
713 {"ATC", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID},
714 {"CAU", ATTENTION_PAR_INT, NULL, BLOCK_CAU},
715 {"PTU", ATTENTION_PAR_INT, NULL, BLOCK_PTU},
716 {"PRM", ATTENTION_PAR_INT, NULL, BLOCK_PRM},
717 {"TCFC", ATTENTION_PAR_INT, NULL, BLOCK_TCFC},
718 {"RDIF", ATTENTION_PAR_INT, NULL, BLOCK_RDIF},
719 {"TDIF", ATTENTION_PAR_INT, NULL, BLOCK_TDIF},
720 {"RSS", ATTENTION_PAR_INT, NULL, BLOCK_RSS},
721 {"MISC", ATTENTION_PAR_INT, NULL, BLOCK_MISC},
722 {"MISCS", ATTENTION_PAR_INT, NULL, BLOCK_MISCS},
723 {"PCIE", ATTENTION_PAR, NULL, BLOCK_PCIE},
724 {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS},
725 {"PSWRQ", ATTENTION_PAR_INT, NULL, BLOCK_PSWRQ},
726 }
727 },
728
729 {
730 { /* After Invert 8 */
731 {"PSWRQ (pci_clk)", ATTENTION_PAR_INT,
732 NULL, BLOCK_PSWRQ2},
733 {"PSWWR", ATTENTION_PAR_INT, NULL, BLOCK_PSWWR},
734 {"PSWWR (pci_clk)", ATTENTION_PAR_INT,
735 NULL, BLOCK_PSWWR2},
736 {"PSWRD", ATTENTION_PAR_INT, NULL, BLOCK_PSWRD},
737 {"PSWRD (pci_clk)", ATTENTION_PAR_INT,
738 NULL, BLOCK_PSWRD2},
739 {"PSWHST", ATTENTION_PAR_INT,
740 qed_pswhst_attn_cb, BLOCK_PSWHST},
741 {"PSWHST (pci_clk)", ATTENTION_PAR_INT,
742 NULL, BLOCK_PSWHST2},
743 {"GRC", ATTENTION_PAR_INT,
744 qed_grc_attn_cb, BLOCK_GRC},
745 {"CPMU", ATTENTION_PAR_INT, NULL, BLOCK_CPMU},
746 {"NCSI", ATTENTION_PAR_INT, NULL, BLOCK_NCSI},
747 {"MSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
748 {"PSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
749 {"TSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
750 {"USEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
751 {"XSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
752 {"YSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
753 {"pxp_misc_mps", ATTENTION_PAR, NULL, BLOCK_PGLCS},
754 {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE,
755 NULL, BLOCK_PGLCS},
756 {"PERST_B assertion", ATTENTION_SINGLE,
757 NULL, MAX_BLOCK_ID},
758 {"PERST_B deassertion", ATTENTION_SINGLE,
759 NULL, MAX_BLOCK_ID},
760 {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT),
761 NULL, MAX_BLOCK_ID},
762 }
763 },
764
765 {
766 { /* After Invert 9 */
767 {"MCP Latched memory", ATTENTION_PAR,
768 NULL, MAX_BLOCK_ID},
769 {"MCP Latched scratchpad cache", ATTENTION_SINGLE,
770 NULL, MAX_BLOCK_ID},
771 {"MCP Latched ump_tx", ATTENTION_PAR,
772 NULL, MAX_BLOCK_ID},
773 {"MCP Latched scratchpad", ATTENTION_PAR,
774 NULL, MAX_BLOCK_ID},
775 {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT),
776 NULL, MAX_BLOCK_ID},
777 }
778 },
779};
780
781static struct aeu_invert_reg_bit *
782qed_int_aeu_translate(struct qed_hwfn *p_hwfn,
783 struct aeu_invert_reg_bit *p_bit)
784{
785 if (!QED_IS_BB(p_hwfn->cdev))
786 return p_bit;
787
788 if (!(p_bit->flags & ATTENTION_BB_DIFFERENT))
789 return p_bit;
790
791 return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >>
792 ATTENTION_BB_SHIFT];
793}
794
795static bool qed_int_is_parity_flag(struct qed_hwfn *p_hwfn,
796 struct aeu_invert_reg_bit *p_bit)
797{
798 return !!(qed_int_aeu_translate(p_hwfn, p_bit)->flags &
799 ATTENTION_PARITY);
800}
801
802#define ATTN_STATE_BITS (0xfff)
803#define ATTN_BITS_MASKABLE (0x3ff)
804struct qed_sb_attn_info {
805 /* Virtual & Physical address of the SB */
806 struct atten_status_block *sb_attn;
807 dma_addr_t sb_phys;
808
809 /* Last seen running index */
810 u16 index;
811
812 /* A mask of the AEU bits resulting in a parity error */
813 u32 parity_mask[NUM_ATTN_REGS];
814
815 /* A pointer to the attention description structure */
816 struct aeu_invert_reg *p_aeu_desc;
817
818 /* Previously asserted attentions, which are still unasserted */
819 u16 known_attn;
820
821 /* Cleanup address for the link's general hw attention */
822 u32 mfw_attn_addr;
823};
824
825static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn,
826 struct qed_sb_attn_info *p_sb_desc)
827{
828 u16 rc = 0, index;
829
830 index = le16_to_cpu(p_sb_desc->sb_attn->sb_index);
831 if (p_sb_desc->index != index) {
832 p_sb_desc->index = index;
833 rc = QED_SB_ATT_IDX;
834 }
835
836 return rc;
837}
838
839/**
840 * qed_int_assertion() - Handle asserted attention bits.
841 *
842 * @p_hwfn: HW device data.
843 * @asserted_bits: Newly asserted bits.
844 *
845 * Return: Zero value.
846 */
847static int qed_int_assertion(struct qed_hwfn *p_hwfn, u16 asserted_bits)
848{
849 struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
850 u32 igu_mask;
851
852 /* Mask the source of the attention in the IGU */
853 igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE);
854 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n",
855 igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE));
856 igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE);
857 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);
858
859 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
860 "inner known ATTN state: 0x%04x --> 0x%04x\n",
861 sb_attn_sw->known_attn,
862 sb_attn_sw->known_attn | asserted_bits);
863 sb_attn_sw->known_attn |= asserted_bits;
864
865 /* Handle MCP events */
866 if (asserted_bits & 0x100) {
867 qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt);
868 /* Clean the MCP attention */
869 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,
870 sb_attn_sw->mfw_attn_addr, 0);
871 }
872
873 DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview +
874 GTT_BAR0_MAP_REG_IGU_CMD +
875 ((IGU_CMD_ATTN_BIT_SET_UPPER -
876 IGU_CMD_INT_ACK_BASE) << 3),
877 (u32)asserted_bits);
878
879 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n",
880 asserted_bits);
881
882 return 0;
883}
884
885static void qed_int_attn_print(struct qed_hwfn *p_hwfn,
886 enum block_id id,
887 enum dbg_attn_type type, bool b_clear)
888{
889 struct dbg_attn_block_result attn_results;
890 enum dbg_status status;
891
892 memset(&attn_results, 0, sizeof(attn_results));
893
894 status = qed_dbg_read_attn(p_hwfn, p_hwfn->p_dpc_ptt, id, type,
895 b_clear, &attn_results);
896 if (status != DBG_STATUS_OK)
897 DP_NOTICE(p_hwfn,
898 "Failed to parse attention information [status: %s]\n",
899 qed_dbg_get_status_str(status));
900 else
901 qed_dbg_parse_attn(p_hwfn, &attn_results);
902}
903
904/**
905 * qed_int_deassertion_aeu_bit() - Handles the effects of a single
906 * cause of the attention.
907 *
908 * @p_hwfn: HW device data.
909 * @p_aeu: Descriptor of an AEU bit which caused the attention.
910 * @aeu_en_reg: Register offset of the AEU enable reg. which configured
911 * this bit to this group.
912 * @p_bit_name: AEU bit description for logging purposes.
913 * @bitmask: Index of this bit in the aeu_en_reg.
914 *
915 * Return: Zero on success, negative errno otherwise.
916 */
917static int
918qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn,
919 struct aeu_invert_reg_bit *p_aeu,
920 u32 aeu_en_reg,
921 const char *p_bit_name, u32 bitmask)
922{
923 bool b_fatal = false;
924 int rc = -EINVAL;
925 u32 val;
926
927 DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n",
928 p_bit_name, bitmask);
929
930 /* Call callback before clearing the interrupt status */
931 if (p_aeu->cb) {
932 DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n",
933 p_bit_name);
934 rc = p_aeu->cb(p_hwfn);
935 }
936
937 if (rc)
938 b_fatal = true;
939
940 /* Print HW block interrupt registers */
941 if (p_aeu->block_index != MAX_BLOCK_ID)
942 qed_int_attn_print(p_hwfn, p_aeu->block_index,
943 ATTN_TYPE_INTERRUPT, !b_fatal);
944
945 /* Reach assertion if attention is fatal */
946 if (b_fatal)
947 qed_hw_err_notify(p_hwfn, p_hwfn->p_dpc_ptt, QED_HW_ERR_HW_ATTN,
948 "`%s': Fatal attention\n",
949 p_bit_name);
950 else /* If the attention is benign, no need to prevent it */
951 goto out;
952
953 /* Prevent this Attention from being asserted in the future */
954 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
955 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask));
956 DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n",
957 p_bit_name);
958
959 /* Re-enable FW aassertion (Gen 32) interrupts */
960 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
961 MISC_REG_AEU_ENABLE4_IGU_OUT_0);
962 val |= MISC_REG_AEU_ENABLE4_IGU_OUT_0_GENERAL_ATTN32;
963 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,
964 MISC_REG_AEU_ENABLE4_IGU_OUT_0, val);
965
966out:
967 return rc;
968}
969
970/**
971 * qed_int_deassertion_parity() - Handle a single parity AEU source.
972 *
973 * @p_hwfn: HW device data.
974 * @p_aeu: Descriptor of an AEU bit which caused the parity.
975 * @aeu_en_reg: Address of the AEU enable register.
976 * @bit_index: Index (0-31) of an AEU bit.
977 */
978static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn,
979 struct aeu_invert_reg_bit *p_aeu,
980 u32 aeu_en_reg, u8 bit_index)
981{
982 u32 block_id = p_aeu->block_index, mask, val;
983
984 DP_NOTICE(p_hwfn->cdev,
985 "%s parity attention is set [address 0x%08x, bit %d]\n",
986 p_aeu->bit_name, aeu_en_reg, bit_index);
987
988 if (block_id != MAX_BLOCK_ID) {
989 qed_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false);
990
991 /* In BB, there's a single parity bit for several blocks */
992 if (block_id == BLOCK_BTB) {
993 qed_int_attn_print(p_hwfn, BLOCK_OPTE,
994 ATTN_TYPE_PARITY, false);
995 qed_int_attn_print(p_hwfn, BLOCK_MCP,
996 ATTN_TYPE_PARITY, false);
997 }
998 }
999
1000 /* Prevent this parity error from being re-asserted */
1001 mask = ~BIT(bit_index);
1002 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
1003 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask);
1004 DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n",
1005 p_aeu->bit_name);
1006}
1007
1008/**
1009 * qed_int_deassertion() - Handle deassertion of previously asserted
1010 * attentions.
1011 *
1012 * @p_hwfn: HW device data.
1013 * @deasserted_bits: newly deasserted bits.
1014 *
1015 * Return: Zero value.
1016 */
1017static int qed_int_deassertion(struct qed_hwfn *p_hwfn,
1018 u16 deasserted_bits)
1019{
1020 struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
1021 u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en;
1022 u8 i, j, k, bit_idx;
1023 int rc = 0;
1024
1025 /* Read the attention registers in the AEU */
1026 for (i = 0; i < NUM_ATTN_REGS; i++) {
1027 aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1028 MISC_REG_AEU_AFTER_INVERT_1_IGU +
1029 i * 0x4);
1030 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1031 "Deasserted bits [%d]: %08x\n",
1032 i, aeu_inv_arr[i]);
1033 }
1034
1035 /* Find parity attentions first */
1036 for (i = 0; i < NUM_ATTN_REGS; i++) {
1037 struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i];
1038 u32 parities;
1039
1040 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32);
1041 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
1042
1043 /* Skip register in which no parity bit is currently set */
1044 parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en;
1045 if (!parities)
1046 continue;
1047
1048 for (j = 0, bit_idx = 0; bit_idx < 32 && j < 32; j++) {
1049 struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j];
1050
1051 if (qed_int_is_parity_flag(p_hwfn, p_bit) &&
1052 !!(parities & BIT(bit_idx)))
1053 qed_int_deassertion_parity(p_hwfn, p_bit,
1054 aeu_en, bit_idx);
1055
1056 bit_idx += ATTENTION_LENGTH(p_bit->flags);
1057 }
1058 }
1059
1060 /* Find non-parity cause for attention and act */
1061 for (k = 0; k < MAX_ATTN_GRPS; k++) {
1062 struct aeu_invert_reg_bit *p_aeu;
1063
1064 /* Handle only groups whose attention is currently deasserted */
1065 if (!(deasserted_bits & (1 << k)))
1066 continue;
1067
1068 for (i = 0; i < NUM_ATTN_REGS; i++) {
1069 u32 bits;
1070
1071 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
1072 i * sizeof(u32) +
1073 k * sizeof(u32) * NUM_ATTN_REGS;
1074
1075 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
1076 bits = aeu_inv_arr[i] & en;
1077
1078 /* Skip if no bit from this group is currently set */
1079 if (!bits)
1080 continue;
1081
1082 /* Find all set bits from current register which belong
1083 * to current group, making them responsible for the
1084 * previous assertion.
1085 */
1086 for (j = 0, bit_idx = 0; bit_idx < 32 && j < 32; j++) {
1087 long unsigned int bitmask;
1088 u8 bit, bit_len;
1089
1090 p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j];
1091 p_aeu = qed_int_aeu_translate(p_hwfn, p_aeu);
1092
1093 bit = bit_idx;
1094 bit_len = ATTENTION_LENGTH(p_aeu->flags);
1095 if (qed_int_is_parity_flag(p_hwfn, p_aeu)) {
1096 /* Skip Parity */
1097 bit++;
1098 bit_len--;
1099 }
1100
1101 bitmask = bits & (((1 << bit_len) - 1) << bit);
1102 bitmask >>= bit;
1103
1104 if (bitmask) {
1105 u32 flags = p_aeu->flags;
1106 char bit_name[30];
1107 u8 num;
1108
1109 num = (u8)find_first_bit(&bitmask,
1110 bit_len);
1111
1112 /* Some bits represent more than a
1113 * single interrupt. Correctly print
1114 * their name.
1115 */
1116 if (ATTENTION_LENGTH(flags) > 2 ||
1117 ((flags & ATTENTION_PAR_INT) &&
1118 ATTENTION_LENGTH(flags) > 1))
1119 snprintf(bit_name, 30,
1120 p_aeu->bit_name, num);
1121 else
1122 strscpy(bit_name,
1123 p_aeu->bit_name, 30);
1124
1125 /* We now need to pass bitmask in its
1126 * correct position.
1127 */
1128 bitmask <<= bit;
1129
1130 /* Handle source of the attention */
1131 qed_int_deassertion_aeu_bit(p_hwfn,
1132 p_aeu,
1133 aeu_en,
1134 bit_name,
1135 bitmask);
1136 }
1137
1138 bit_idx += ATTENTION_LENGTH(p_aeu->flags);
1139 }
1140 }
1141 }
1142
1143 /* Handle missed DORQ attention */
1144 qed_dorq_attn_handler(p_hwfn);
1145
1146 /* Clear IGU indication for the deasserted bits */
1147 DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview +
1148 GTT_BAR0_MAP_REG_IGU_CMD +
1149 ((IGU_CMD_ATTN_BIT_CLR_UPPER -
1150 IGU_CMD_INT_ACK_BASE) << 3),
1151 ~((u32)deasserted_bits));
1152
1153 /* Unmask deasserted attentions in IGU */
1154 aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE);
1155 aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE);
1156 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);
1157
1158 /* Clear deassertion from inner state */
1159 sb_attn_sw->known_attn &= ~deasserted_bits;
1160
1161 return rc;
1162}
1163
1164static int qed_int_attentions(struct qed_hwfn *p_hwfn)
1165{
1166 struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn;
1167 struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn;
1168 u32 attn_bits = 0, attn_acks = 0;
1169 u16 asserted_bits, deasserted_bits;
1170 __le16 index;
1171 int rc = 0;
1172
1173 /* Read current attention bits/acks - safeguard against attentions
1174 * by guaranting work on a synchronized timeframe
1175 */
1176 do {
1177 index = p_sb_attn->sb_index;
1178 /* finish reading index before the loop condition */
1179 dma_rmb();
1180 attn_bits = le32_to_cpu(p_sb_attn->atten_bits);
1181 attn_acks = le32_to_cpu(p_sb_attn->atten_ack);
1182 } while (index != p_sb_attn->sb_index);
1183 p_sb_attn->sb_index = index;
1184
1185 /* Attention / Deassertion are meaningful (and in correct state)
1186 * only when they differ and consistent with known state - deassertion
1187 * when previous attention & current ack, and assertion when current
1188 * attention with no previous attention
1189 */
1190 asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) &
1191 ~p_sb_attn_sw->known_attn;
1192 deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) &
1193 p_sb_attn_sw->known_attn;
1194
1195 if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) {
1196 DP_INFO(p_hwfn,
1197 "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n",
1198 index, attn_bits, attn_acks, asserted_bits,
1199 deasserted_bits, p_sb_attn_sw->known_attn);
1200 } else if (asserted_bits == 0x100) {
1201 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1202 "MFW indication via attention\n");
1203 } else {
1204 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1205 "MFW indication [deassertion]\n");
1206 }
1207
1208 if (asserted_bits) {
1209 rc = qed_int_assertion(p_hwfn, asserted_bits);
1210 if (rc)
1211 return rc;
1212 }
1213
1214 if (deasserted_bits)
1215 rc = qed_int_deassertion(p_hwfn, deasserted_bits);
1216
1217 return rc;
1218}
1219
1220static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn,
1221 void __iomem *igu_addr, u32 ack_cons)
1222{
1223 u32 igu_ack;
1224
1225 igu_ack = ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1226 (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1227 (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1228 (IGU_SEG_ACCESS_ATTN <<
1229 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1230
1231 DIRECT_REG_WR(igu_addr, igu_ack);
1232
1233 /* Both segments (interrupts & acks) are written to same place address;
1234 * Need to guarantee all commands will be received (in-order) by HW.
1235 */
1236 barrier();
1237}
1238
1239void qed_int_sp_dpc(struct tasklet_struct *t)
1240{
1241 struct qed_hwfn *p_hwfn = from_tasklet(p_hwfn, t, sp_dpc);
1242 struct qed_pi_info *pi_info = NULL;
1243 struct qed_sb_attn_info *sb_attn;
1244 struct qed_sb_info *sb_info;
1245 int arr_size;
1246 u16 rc = 0;
1247
1248 if (!p_hwfn->p_sp_sb) {
1249 DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n");
1250 return;
1251 }
1252
1253 sb_info = &p_hwfn->p_sp_sb->sb_info;
1254 arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr);
1255 if (!sb_info) {
1256 DP_ERR(p_hwfn->cdev,
1257 "Status block is NULL - cannot ack interrupts\n");
1258 return;
1259 }
1260
1261 if (!p_hwfn->p_sb_attn) {
1262 DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn");
1263 return;
1264 }
1265 sb_attn = p_hwfn->p_sb_attn;
1266
1267 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n",
1268 p_hwfn, p_hwfn->my_id);
1269
1270 /* Disable ack for def status block. Required both for msix +
1271 * inta in non-mask mode, in inta does no harm.
1272 */
1273 qed_sb_ack(sb_info, IGU_INT_DISABLE, 0);
1274
1275 /* Gather Interrupts/Attentions information */
1276 if (!sb_info->sb_virt) {
1277 DP_ERR(p_hwfn->cdev,
1278 "Interrupt Status block is NULL - cannot check for new interrupts!\n");
1279 } else {
1280 u32 tmp_index = sb_info->sb_ack;
1281
1282 rc = qed_sb_update_sb_idx(sb_info);
1283 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR,
1284 "Interrupt indices: 0x%08x --> 0x%08x\n",
1285 tmp_index, sb_info->sb_ack);
1286 }
1287
1288 if (!sb_attn || !sb_attn->sb_attn) {
1289 DP_ERR(p_hwfn->cdev,
1290 "Attentions Status block is NULL - cannot check for new attentions!\n");
1291 } else {
1292 u16 tmp_index = sb_attn->index;
1293
1294 rc |= qed_attn_update_idx(p_hwfn, sb_attn);
1295 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR,
1296 "Attention indices: 0x%08x --> 0x%08x\n",
1297 tmp_index, sb_attn->index);
1298 }
1299
1300 /* Check if we expect interrupts at this time. if not just ack them */
1301 if (!(rc & QED_SB_EVENT_MASK)) {
1302 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1303 return;
1304 }
1305
1306 /* Check the validity of the DPC ptt. If not ack interrupts and fail */
1307 if (!p_hwfn->p_dpc_ptt) {
1308 DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n");
1309 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1310 return;
1311 }
1312
1313 if (rc & QED_SB_ATT_IDX)
1314 qed_int_attentions(p_hwfn);
1315
1316 if (rc & QED_SB_IDX) {
1317 int pi;
1318
1319 /* Look for a free index */
1320 for (pi = 0; pi < arr_size; pi++) {
1321 pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi];
1322 if (pi_info->comp_cb)
1323 pi_info->comp_cb(p_hwfn, pi_info->cookie);
1324 }
1325 }
1326
1327 if (sb_attn && (rc & QED_SB_ATT_IDX))
1328 /* This should be done before the interrupts are enabled,
1329 * since otherwise a new attention will be generated.
1330 */
1331 qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index);
1332
1333 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1334}
1335
1336static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn)
1337{
1338 struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn;
1339
1340 if (!p_sb)
1341 return;
1342
1343 if (p_sb->sb_attn)
1344 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1345 SB_ATTN_ALIGNED_SIZE(p_hwfn),
1346 p_sb->sb_attn, p_sb->sb_phys);
1347 kfree(p_sb);
1348 p_hwfn->p_sb_attn = NULL;
1349}
1350
1351static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn,
1352 struct qed_ptt *p_ptt)
1353{
1354 struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1355
1356 memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn));
1357
1358 sb_info->index = 0;
1359 sb_info->known_attn = 0;
1360
1361 /* Configure Attention Status Block in IGU */
1362 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,
1363 lower_32_bits(p_hwfn->p_sb_attn->sb_phys));
1364 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,
1365 upper_32_bits(p_hwfn->p_sb_attn->sb_phys));
1366}
1367
1368static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn,
1369 struct qed_ptt *p_ptt,
1370 void *sb_virt_addr, dma_addr_t sb_phy_addr)
1371{
1372 struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1373 int i, j, k;
1374
1375 sb_info->sb_attn = sb_virt_addr;
1376 sb_info->sb_phys = sb_phy_addr;
1377
1378 /* Set the pointer to the AEU descriptors */
1379 sb_info->p_aeu_desc = aeu_descs;
1380
1381 /* Calculate Parity Masks */
1382 memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS);
1383 for (i = 0; i < NUM_ATTN_REGS; i++) {
1384 /* j is array index, k is bit index */
1385 for (j = 0, k = 0; k < 32 && j < 32; j++) {
1386 struct aeu_invert_reg_bit *p_aeu;
1387
1388 p_aeu = &aeu_descs[i].bits[j];
1389 if (qed_int_is_parity_flag(p_hwfn, p_aeu))
1390 sb_info->parity_mask[i] |= 1 << k;
1391
1392 k += ATTENTION_LENGTH(p_aeu->flags);
1393 }
1394 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1395 "Attn Mask [Reg %d]: 0x%08x\n",
1396 i, sb_info->parity_mask[i]);
1397 }
1398
1399 /* Set the address of cleanup for the mcp attention */
1400 sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) +
1401 MISC_REG_AEU_GENERAL_ATTN_0;
1402
1403 qed_int_sb_attn_setup(p_hwfn, p_ptt);
1404}
1405
1406static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn,
1407 struct qed_ptt *p_ptt)
1408{
1409 struct qed_dev *cdev = p_hwfn->cdev;
1410 struct qed_sb_attn_info *p_sb;
1411 dma_addr_t p_phys = 0;
1412 void *p_virt;
1413
1414 /* SB struct */
1415 p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL);
1416 if (!p_sb)
1417 return -ENOMEM;
1418
1419 /* SB ring */
1420 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
1421 SB_ATTN_ALIGNED_SIZE(p_hwfn),
1422 &p_phys, GFP_KERNEL);
1423
1424 if (!p_virt) {
1425 kfree(p_sb);
1426 return -ENOMEM;
1427 }
1428
1429 /* Attention setup */
1430 p_hwfn->p_sb_attn = p_sb;
1431 qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys);
1432
1433 return 0;
1434}
1435
1436/* coalescing timeout = timeset << (timer_res + 1) */
1437#define QED_CAU_DEF_RX_USECS 24
1438#define QED_CAU_DEF_TX_USECS 48
1439
1440void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
1441 struct cau_sb_entry *p_sb_entry,
1442 u8 pf_id, u16 vf_number, u8 vf_valid)
1443{
1444 struct qed_dev *cdev = p_hwfn->cdev;
1445 u32 cau_state, params = 0, data = 0;
1446 u8 timer_res;
1447
1448 memset(p_sb_entry, 0, sizeof(*p_sb_entry));
1449
1450 SET_FIELD(params, CAU_SB_ENTRY_PF_NUMBER, pf_id);
1451 SET_FIELD(params, CAU_SB_ENTRY_VF_NUMBER, vf_number);
1452 SET_FIELD(params, CAU_SB_ENTRY_VF_VALID, vf_valid);
1453 SET_FIELD(params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F);
1454 SET_FIELD(params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F);
1455
1456 cau_state = CAU_HC_DISABLE_STATE;
1457
1458 if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
1459 cau_state = CAU_HC_ENABLE_STATE;
1460 if (!cdev->rx_coalesce_usecs)
1461 cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS;
1462 if (!cdev->tx_coalesce_usecs)
1463 cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS;
1464 }
1465
1466 /* Coalesce = (timeset << timer-res), timeset is 7bit wide */
1467 if (cdev->rx_coalesce_usecs <= 0x7F)
1468 timer_res = 0;
1469 else if (cdev->rx_coalesce_usecs <= 0xFF)
1470 timer_res = 1;
1471 else
1472 timer_res = 2;
1473
1474 SET_FIELD(params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
1475
1476 if (cdev->tx_coalesce_usecs <= 0x7F)
1477 timer_res = 0;
1478 else if (cdev->tx_coalesce_usecs <= 0xFF)
1479 timer_res = 1;
1480 else
1481 timer_res = 2;
1482
1483 SET_FIELD(params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
1484 p_sb_entry->params = cpu_to_le32(params);
1485
1486 SET_FIELD(data, CAU_SB_ENTRY_STATE0, cau_state);
1487 SET_FIELD(data, CAU_SB_ENTRY_STATE1, cau_state);
1488 p_sb_entry->data = cpu_to_le32(data);
1489}
1490
1491static void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,
1492 struct qed_ptt *p_ptt,
1493 u16 igu_sb_id,
1494 u32 pi_index,
1495 enum qed_coalescing_fsm coalescing_fsm,
1496 u8 timeset)
1497{
1498 u32 sb_offset, pi_offset;
1499 u32 prod = 0;
1500
1501 if (IS_VF(p_hwfn->cdev))
1502 return;
1503
1504 SET_FIELD(prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
1505 if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE)
1506 SET_FIELD(prod, CAU_PI_ENTRY_FSM_SEL, 0);
1507 else
1508 SET_FIELD(prod, CAU_PI_ENTRY_FSM_SEL, 1);
1509
1510 sb_offset = igu_sb_id * PIS_PER_SB;
1511 pi_offset = sb_offset + pi_index;
1512
1513 if (p_hwfn->hw_init_done)
1514 qed_wr(p_hwfn, p_ptt,
1515 CAU_REG_PI_MEMORY + pi_offset * sizeof(u32), prod);
1516 else
1517 STORE_RT_REG(p_hwfn, CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
1518 prod);
1519}
1520
1521void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
1522 struct qed_ptt *p_ptt,
1523 dma_addr_t sb_phys,
1524 u16 igu_sb_id, u16 vf_number, u8 vf_valid)
1525{
1526 struct cau_sb_entry sb_entry;
1527
1528 qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id,
1529 vf_number, vf_valid);
1530
1531 if (p_hwfn->hw_init_done) {
1532 /* Wide-bus, initialize via DMAE */
1533 u64 phys_addr = (u64)sb_phys;
1534
1535 qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr,
1536 CAU_REG_SB_ADDR_MEMORY +
1537 igu_sb_id * sizeof(u64), 2, NULL);
1538 qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry,
1539 CAU_REG_SB_VAR_MEMORY +
1540 igu_sb_id * sizeof(u64), 2, NULL);
1541 } else {
1542 /* Initialize Status Block Address */
1543 STORE_RT_REG_AGG(p_hwfn,
1544 CAU_REG_SB_ADDR_MEMORY_RT_OFFSET +
1545 igu_sb_id * 2,
1546 sb_phys);
1547
1548 STORE_RT_REG_AGG(p_hwfn,
1549 CAU_REG_SB_VAR_MEMORY_RT_OFFSET +
1550 igu_sb_id * 2,
1551 sb_entry);
1552 }
1553
1554 /* Configure pi coalescing if set */
1555 if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
1556 u8 num_tc = p_hwfn->hw_info.num_hw_tc;
1557 u8 timeset, timer_res;
1558 u8 i;
1559
1560 /* timeset = (coalesce >> timer-res), timeset is 7bit wide */
1561 if (p_hwfn->cdev->rx_coalesce_usecs <= 0x7F)
1562 timer_res = 0;
1563 else if (p_hwfn->cdev->rx_coalesce_usecs <= 0xFF)
1564 timer_res = 1;
1565 else
1566 timer_res = 2;
1567 timeset = (u8)(p_hwfn->cdev->rx_coalesce_usecs >> timer_res);
1568 qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
1569 QED_COAL_RX_STATE_MACHINE, timeset);
1570
1571 if (p_hwfn->cdev->tx_coalesce_usecs <= 0x7F)
1572 timer_res = 0;
1573 else if (p_hwfn->cdev->tx_coalesce_usecs <= 0xFF)
1574 timer_res = 1;
1575 else
1576 timer_res = 2;
1577 timeset = (u8)(p_hwfn->cdev->tx_coalesce_usecs >> timer_res);
1578 for (i = 0; i < num_tc; i++) {
1579 qed_int_cau_conf_pi(p_hwfn, p_ptt,
1580 igu_sb_id, TX_PI(i),
1581 QED_COAL_TX_STATE_MACHINE,
1582 timeset);
1583 }
1584 }
1585}
1586
1587void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
1588 struct qed_ptt *p_ptt, struct qed_sb_info *sb_info)
1589{
1590 /* zero status block and ack counter */
1591 sb_info->sb_ack = 0;
1592 memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1593
1594 if (IS_PF(p_hwfn->cdev))
1595 qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,
1596 sb_info->igu_sb_id, 0, 0);
1597}
1598
1599struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn, bool b_is_pf)
1600{
1601 struct qed_igu_block *p_block;
1602 u16 igu_id;
1603
1604 for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev);
1605 igu_id++) {
1606 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1607
1608 if (!(p_block->status & QED_IGU_STATUS_VALID) ||
1609 !(p_block->status & QED_IGU_STATUS_FREE))
1610 continue;
1611
1612 if (!!(p_block->status & QED_IGU_STATUS_PF) == b_is_pf)
1613 return p_block;
1614 }
1615
1616 return NULL;
1617}
1618
1619static u16 qed_get_pf_igu_sb_id(struct qed_hwfn *p_hwfn, u16 vector_id)
1620{
1621 struct qed_igu_block *p_block;
1622 u16 igu_id;
1623
1624 for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev);
1625 igu_id++) {
1626 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1627
1628 if (!(p_block->status & QED_IGU_STATUS_VALID) ||
1629 !p_block->is_pf ||
1630 p_block->vector_number != vector_id)
1631 continue;
1632
1633 return igu_id;
1634 }
1635
1636 return QED_SB_INVALID_IDX;
1637}
1638
1639u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id)
1640{
1641 u16 igu_sb_id;
1642
1643 /* Assuming continuous set of IGU SBs dedicated for given PF */
1644 if (sb_id == QED_SP_SB_ID)
1645 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
1646 else if (IS_PF(p_hwfn->cdev))
1647 igu_sb_id = qed_get_pf_igu_sb_id(p_hwfn, sb_id + 1);
1648 else
1649 igu_sb_id = qed_vf_get_igu_sb_id(p_hwfn, sb_id);
1650
1651 if (sb_id == QED_SP_SB_ID)
1652 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1653 "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id);
1654 else
1655 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1656 "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id);
1657
1658 return igu_sb_id;
1659}
1660
1661int qed_int_sb_init(struct qed_hwfn *p_hwfn,
1662 struct qed_ptt *p_ptt,
1663 struct qed_sb_info *sb_info,
1664 void *sb_virt_addr, dma_addr_t sb_phy_addr, u16 sb_id)
1665{
1666 sb_info->sb_virt = sb_virt_addr;
1667 sb_info->sb_phys = sb_phy_addr;
1668
1669 sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id);
1670
1671 if (sb_id != QED_SP_SB_ID) {
1672 if (IS_PF(p_hwfn->cdev)) {
1673 struct qed_igu_info *p_info;
1674 struct qed_igu_block *p_block;
1675
1676 p_info = p_hwfn->hw_info.p_igu_info;
1677 p_block = &p_info->entry[sb_info->igu_sb_id];
1678
1679 p_block->sb_info = sb_info;
1680 p_block->status &= ~QED_IGU_STATUS_FREE;
1681 p_info->usage.free_cnt--;
1682 } else {
1683 qed_vf_set_sb_info(p_hwfn, sb_id, sb_info);
1684 }
1685 }
1686
1687 sb_info->cdev = p_hwfn->cdev;
1688
1689 /* The igu address will hold the absolute address that needs to be
1690 * written to for a specific status block
1691 */
1692 if (IS_PF(p_hwfn->cdev)) {
1693 sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview +
1694 GTT_BAR0_MAP_REG_IGU_CMD +
1695 (sb_info->igu_sb_id << 3);
1696 } else {
1697 sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview +
1698 PXP_VF_BAR0_START_IGU +
1699 ((IGU_CMD_INT_ACK_BASE +
1700 sb_info->igu_sb_id) << 3);
1701 }
1702
1703 sb_info->flags |= QED_SB_INFO_INIT;
1704
1705 qed_int_sb_setup(p_hwfn, p_ptt, sb_info);
1706
1707 return 0;
1708}
1709
1710int qed_int_sb_release(struct qed_hwfn *p_hwfn,
1711 struct qed_sb_info *sb_info, u16 sb_id)
1712{
1713 struct qed_igu_block *p_block;
1714 struct qed_igu_info *p_info;
1715
1716 if (!sb_info)
1717 return 0;
1718
1719 /* zero status block and ack counter */
1720 sb_info->sb_ack = 0;
1721 memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1722
1723 if (IS_VF(p_hwfn->cdev)) {
1724 qed_vf_set_sb_info(p_hwfn, sb_id, NULL);
1725 return 0;
1726 }
1727
1728 p_info = p_hwfn->hw_info.p_igu_info;
1729 p_block = &p_info->entry[sb_info->igu_sb_id];
1730
1731 /* Vector 0 is reserved to Default SB */
1732 if (!p_block->vector_number) {
1733 DP_ERR(p_hwfn, "Do Not free sp sb using this function");
1734 return -EINVAL;
1735 }
1736
1737 /* Lose reference to client's SB info, and fix counters */
1738 p_block->sb_info = NULL;
1739 p_block->status |= QED_IGU_STATUS_FREE;
1740 p_info->usage.free_cnt++;
1741
1742 return 0;
1743}
1744
1745static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn)
1746{
1747 struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb;
1748
1749 if (!p_sb)
1750 return;
1751
1752 if (p_sb->sb_info.sb_virt)
1753 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1754 SB_ALIGNED_SIZE(p_hwfn),
1755 p_sb->sb_info.sb_virt,
1756 p_sb->sb_info.sb_phys);
1757 kfree(p_sb);
1758 p_hwfn->p_sp_sb = NULL;
1759}
1760
1761static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1762{
1763 struct qed_sb_sp_info *p_sb;
1764 dma_addr_t p_phys = 0;
1765 void *p_virt;
1766
1767 /* SB struct */
1768 p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL);
1769 if (!p_sb)
1770 return -ENOMEM;
1771
1772 /* SB ring */
1773 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1774 SB_ALIGNED_SIZE(p_hwfn),
1775 &p_phys, GFP_KERNEL);
1776 if (!p_virt) {
1777 kfree(p_sb);
1778 return -ENOMEM;
1779 }
1780
1781 /* Status Block setup */
1782 p_hwfn->p_sp_sb = p_sb;
1783 qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt,
1784 p_phys, QED_SP_SB_ID);
1785
1786 memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr));
1787
1788 return 0;
1789}
1790
1791int qed_int_register_cb(struct qed_hwfn *p_hwfn,
1792 qed_int_comp_cb_t comp_cb,
1793 void *cookie, u8 *sb_idx, __le16 **p_fw_cons)
1794{
1795 struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1796 int rc = -ENOMEM;
1797 u8 pi;
1798
1799 /* Look for a free index */
1800 for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) {
1801 if (p_sp_sb->pi_info_arr[pi].comp_cb)
1802 continue;
1803
1804 p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
1805 p_sp_sb->pi_info_arr[pi].cookie = cookie;
1806 *sb_idx = pi;
1807 *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi];
1808 rc = 0;
1809 break;
1810 }
1811
1812 return rc;
1813}
1814
1815int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi)
1816{
1817 struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1818
1819 if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL)
1820 return -ENOMEM;
1821
1822 p_sp_sb->pi_info_arr[pi].comp_cb = NULL;
1823 p_sp_sb->pi_info_arr[pi].cookie = NULL;
1824
1825 return 0;
1826}
1827
1828u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn)
1829{
1830 return p_hwfn->p_sp_sb->sb_info.igu_sb_id;
1831}
1832
1833void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,
1834 struct qed_ptt *p_ptt, enum qed_int_mode int_mode)
1835{
1836 u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN;
1837
1838 p_hwfn->cdev->int_mode = int_mode;
1839 switch (p_hwfn->cdev->int_mode) {
1840 case QED_INT_MODE_INTA:
1841 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN;
1842 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1843 break;
1844
1845 case QED_INT_MODE_MSI:
1846 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1847 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1848 break;
1849
1850 case QED_INT_MODE_MSIX:
1851 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1852 break;
1853 case QED_INT_MODE_POLL:
1854 break;
1855 }
1856
1857 qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);
1858}
1859
1860static void qed_int_igu_enable_attn(struct qed_hwfn *p_hwfn,
1861 struct qed_ptt *p_ptt)
1862{
1863
1864 /* Configure AEU signal change to produce attentions */
1865 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0);
1866 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);
1867 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);
1868 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff);
1869
1870 /* Unmask AEU signals toward IGU */
1871 qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);
1872}
1873
1874int
1875qed_int_igu_enable(struct qed_hwfn *p_hwfn,
1876 struct qed_ptt *p_ptt, enum qed_int_mode int_mode)
1877{
1878 int rc = 0;
1879
1880 qed_int_igu_enable_attn(p_hwfn, p_ptt);
1881
1882 if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {
1883 rc = qed_slowpath_irq_req(p_hwfn);
1884 if (rc) {
1885 DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n");
1886 return -EINVAL;
1887 }
1888 p_hwfn->b_int_requested = true;
1889 }
1890 /* Enable interrupt Generation */
1891 qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
1892 p_hwfn->b_int_enabled = 1;
1893
1894 return rc;
1895}
1896
1897void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1898{
1899 p_hwfn->b_int_enabled = 0;
1900
1901 if (IS_VF(p_hwfn->cdev))
1902 return;
1903
1904 qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
1905}
1906
1907#define IGU_CLEANUP_SLEEP_LENGTH (1000)
1908static void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn,
1909 struct qed_ptt *p_ptt,
1910 u16 igu_sb_id,
1911 bool cleanup_set, u16 opaque_fid)
1912{
1913 u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0;
1914 u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id;
1915 u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH;
1916
1917 /* Set the data field */
1918 SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0);
1919 SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0);
1920 SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET);
1921
1922 /* Set the control register */
1923 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr);
1924 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid);
1925 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR);
1926
1927 qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);
1928
1929 barrier();
1930
1931 qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);
1932
1933 /* calculate where to read the status bit from */
1934 sb_bit = 1 << (igu_sb_id % 32);
1935 sb_bit_addr = igu_sb_id / 32 * sizeof(u32);
1936
1937 sb_bit_addr += IGU_REG_CLEANUP_STATUS_0;
1938
1939 /* Now wait for the command to complete */
1940 do {
1941 val = qed_rd(p_hwfn, p_ptt, sb_bit_addr);
1942
1943 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0))
1944 break;
1945
1946 usleep_range(5000, 10000);
1947 } while (--sleep_cnt);
1948
1949 if (!sleep_cnt)
1950 DP_NOTICE(p_hwfn,
1951 "Timeout waiting for clear status 0x%08x [for sb %d]\n",
1952 val, igu_sb_id);
1953}
1954
1955void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
1956 struct qed_ptt *p_ptt,
1957 u16 igu_sb_id, u16 opaque, bool b_set)
1958{
1959 struct qed_igu_block *p_block;
1960 int pi, i;
1961
1962 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
1963 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1964 "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n",
1965 igu_sb_id,
1966 p_block->function_id,
1967 p_block->is_pf, p_block->vector_number);
1968
1969 /* Set */
1970 if (b_set)
1971 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque);
1972
1973 /* Clear */
1974 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque);
1975
1976 /* Wait for the IGU SB to cleanup */
1977 for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) {
1978 u32 val;
1979
1980 val = qed_rd(p_hwfn, p_ptt,
1981 IGU_REG_WRITE_DONE_PENDING +
1982 ((igu_sb_id / 32) * 4));
1983 if (val & BIT((igu_sb_id % 32)))
1984 usleep_range(10, 20);
1985 else
1986 break;
1987 }
1988 if (i == IGU_CLEANUP_SLEEP_LENGTH)
1989 DP_NOTICE(p_hwfn,
1990 "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n",
1991 igu_sb_id);
1992
1993 /* Clear the CAU for the SB */
1994 for (pi = 0; pi < 12; pi++)
1995 qed_wr(p_hwfn, p_ptt,
1996 CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0);
1997}
1998
1999void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
2000 struct qed_ptt *p_ptt,
2001 bool b_set, bool b_slowpath)
2002{
2003 struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2004 struct qed_igu_block *p_block;
2005 u16 igu_sb_id = 0;
2006 u32 val = 0;
2007
2008 val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
2009 val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN;
2010 val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN;
2011 qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);
2012
2013 for (igu_sb_id = 0;
2014 igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) {
2015 p_block = &p_info->entry[igu_sb_id];
2016
2017 if (!(p_block->status & QED_IGU_STATUS_VALID) ||
2018 !p_block->is_pf ||
2019 (p_block->status & QED_IGU_STATUS_DSB))
2020 continue;
2021
2022 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id,
2023 p_hwfn->hw_info.opaque_fid,
2024 b_set);
2025 }
2026
2027 if (b_slowpath)
2028 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt,
2029 p_info->igu_dsb_id,
2030 p_hwfn->hw_info.opaque_fid,
2031 b_set);
2032}
2033
2034int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2035{
2036 struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2037 struct qed_igu_block *p_block;
2038 int pf_sbs, vf_sbs;
2039 u16 igu_sb_id;
2040 u32 val, rval;
2041
2042 if (!RESC_NUM(p_hwfn, QED_SB)) {
2043 p_info->b_allow_pf_vf_change = false;
2044 } else {
2045 /* Use the numbers the MFW have provided -
2046 * don't forget MFW accounts for the default SB as well.
2047 */
2048 p_info->b_allow_pf_vf_change = true;
2049
2050 if (p_info->usage.cnt != RESC_NUM(p_hwfn, QED_SB) - 1) {
2051 DP_INFO(p_hwfn,
2052 "MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n",
2053 RESC_NUM(p_hwfn, QED_SB) - 1,
2054 p_info->usage.cnt);
2055 p_info->usage.cnt = RESC_NUM(p_hwfn, QED_SB) - 1;
2056 }
2057
2058 if (IS_PF_SRIOV(p_hwfn)) {
2059 u16 vfs = p_hwfn->cdev->p_iov_info->total_vfs;
2060
2061 if (vfs != p_info->usage.iov_cnt)
2062 DP_VERBOSE(p_hwfn,
2063 NETIF_MSG_INTR,
2064 "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n",
2065 p_info->usage.iov_cnt, vfs);
2066
2067 /* At this point we know how many SBs we have totally
2068 * in IGU + number of PF SBs. So we can validate that
2069 * we'd have sufficient for VF.
2070 */
2071 if (vfs > p_info->usage.free_cnt +
2072 p_info->usage.free_cnt_iov - p_info->usage.cnt) {
2073 DP_NOTICE(p_hwfn,
2074 "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n",
2075 p_info->usage.free_cnt +
2076 p_info->usage.free_cnt_iov,
2077 p_info->usage.cnt, vfs);
2078 return -EINVAL;
2079 }
2080
2081 /* Currently cap the number of VFs SBs by the
2082 * number of VFs.
2083 */
2084 p_info->usage.iov_cnt = vfs;
2085 }
2086 }
2087
2088 /* Mark all SBs as free, now in the right PF/VFs division */
2089 p_info->usage.free_cnt = p_info->usage.cnt;
2090 p_info->usage.free_cnt_iov = p_info->usage.iov_cnt;
2091 p_info->usage.orig = p_info->usage.cnt;
2092 p_info->usage.iov_orig = p_info->usage.iov_cnt;
2093
2094 /* We now proceed to re-configure the IGU cam to reflect the initial
2095 * configuration. We can start with the Default SB.
2096 */
2097 pf_sbs = p_info->usage.cnt;
2098 vf_sbs = p_info->usage.iov_cnt;
2099
2100 for (igu_sb_id = p_info->igu_dsb_id;
2101 igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) {
2102 p_block = &p_info->entry[igu_sb_id];
2103 val = 0;
2104
2105 if (!(p_block->status & QED_IGU_STATUS_VALID))
2106 continue;
2107
2108 if (p_block->status & QED_IGU_STATUS_DSB) {
2109 p_block->function_id = p_hwfn->rel_pf_id;
2110 p_block->is_pf = 1;
2111 p_block->vector_number = 0;
2112 p_block->status = QED_IGU_STATUS_VALID |
2113 QED_IGU_STATUS_PF |
2114 QED_IGU_STATUS_DSB;
2115 } else if (pf_sbs) {
2116 pf_sbs--;
2117 p_block->function_id = p_hwfn->rel_pf_id;
2118 p_block->is_pf = 1;
2119 p_block->vector_number = p_info->usage.cnt - pf_sbs;
2120 p_block->status = QED_IGU_STATUS_VALID |
2121 QED_IGU_STATUS_PF |
2122 QED_IGU_STATUS_FREE;
2123 } else if (vf_sbs) {
2124 p_block->function_id =
2125 p_hwfn->cdev->p_iov_info->first_vf_in_pf +
2126 p_info->usage.iov_cnt - vf_sbs;
2127 p_block->is_pf = 0;
2128 p_block->vector_number = 0;
2129 p_block->status = QED_IGU_STATUS_VALID |
2130 QED_IGU_STATUS_FREE;
2131 vf_sbs--;
2132 } else {
2133 p_block->function_id = 0;
2134 p_block->is_pf = 0;
2135 p_block->vector_number = 0;
2136 }
2137
2138 SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER,
2139 p_block->function_id);
2140 SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf);
2141 SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER,
2142 p_block->vector_number);
2143
2144 /* VF entries would be enabled when VF is initializaed */
2145 SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf);
2146
2147 rval = qed_rd(p_hwfn, p_ptt,
2148 IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id);
2149
2150 if (rval != val) {
2151 qed_wr(p_hwfn, p_ptt,
2152 IGU_REG_MAPPING_MEMORY +
2153 sizeof(u32) * igu_sb_id, val);
2154
2155 DP_VERBOSE(p_hwfn,
2156 NETIF_MSG_INTR,
2157 "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n",
2158 igu_sb_id,
2159 p_block->function_id,
2160 p_block->is_pf,
2161 p_block->vector_number, rval, val);
2162 }
2163 }
2164
2165 return 0;
2166}
2167
2168static void qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn,
2169 struct qed_ptt *p_ptt, u16 igu_sb_id)
2170{
2171 u32 val = qed_rd(p_hwfn, p_ptt,
2172 IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id);
2173 struct qed_igu_block *p_block;
2174
2175 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
2176
2177 /* Fill the block information */
2178 p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER);
2179 p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
2180 p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER);
2181 p_block->igu_sb_id = igu_sb_id;
2182}
2183
2184int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2185{
2186 struct qed_igu_info *p_igu_info;
2187 struct qed_igu_block *p_block;
2188 u32 min_vf = 0, max_vf = 0;
2189 u16 igu_sb_id;
2190
2191 p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL);
2192 if (!p_hwfn->hw_info.p_igu_info)
2193 return -ENOMEM;
2194
2195 p_igu_info = p_hwfn->hw_info.p_igu_info;
2196
2197 /* Distinguish between existent and non-existent default SB */
2198 p_igu_info->igu_dsb_id = QED_SB_INVALID_IDX;
2199
2200 /* Find the range of VF ids whose SB belong to this PF */
2201 if (p_hwfn->cdev->p_iov_info) {
2202 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
2203
2204 min_vf = p_iov->first_vf_in_pf;
2205 max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs;
2206 }
2207
2208 for (igu_sb_id = 0;
2209 igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) {
2210 /* Read current entry; Notice it might not belong to this PF */
2211 qed_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id);
2212 p_block = &p_igu_info->entry[igu_sb_id];
2213
2214 if ((p_block->is_pf) &&
2215 (p_block->function_id == p_hwfn->rel_pf_id)) {
2216 p_block->status = QED_IGU_STATUS_PF |
2217 QED_IGU_STATUS_VALID |
2218 QED_IGU_STATUS_FREE;
2219
2220 if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX)
2221 p_igu_info->usage.cnt++;
2222 } else if (!(p_block->is_pf) &&
2223 (p_block->function_id >= min_vf) &&
2224 (p_block->function_id < max_vf)) {
2225 /* Available for VFs of this PF */
2226 p_block->status = QED_IGU_STATUS_VALID |
2227 QED_IGU_STATUS_FREE;
2228
2229 if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX)
2230 p_igu_info->usage.iov_cnt++;
2231 }
2232
2233 /* Mark the First entry belonging to the PF or its VFs
2234 * as the default SB [we'll reset IGU prior to first usage].
2235 */
2236 if ((p_block->status & QED_IGU_STATUS_VALID) &&
2237 (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX)) {
2238 p_igu_info->igu_dsb_id = igu_sb_id;
2239 p_block->status |= QED_IGU_STATUS_DSB;
2240 }
2241
2242 /* limit number of prints by having each PF print only its
2243 * entries with the exception of PF0 which would print
2244 * everything.
2245 */
2246 if ((p_block->status & QED_IGU_STATUS_VALID) ||
2247 (p_hwfn->abs_pf_id == 0)) {
2248 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
2249 "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n",
2250 igu_sb_id, p_block->function_id,
2251 p_block->is_pf, p_block->vector_number);
2252 }
2253 }
2254
2255 if (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX) {
2256 DP_NOTICE(p_hwfn,
2257 "IGU CAM returned invalid values igu_dsb_id=0x%x\n",
2258 p_igu_info->igu_dsb_id);
2259 return -EINVAL;
2260 }
2261
2262 /* All non default SB are considered free at this point */
2263 p_igu_info->usage.free_cnt = p_igu_info->usage.cnt;
2264 p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt;
2265
2266 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
2267 "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n",
2268 p_igu_info->igu_dsb_id,
2269 p_igu_info->usage.cnt, p_igu_info->usage.iov_cnt);
2270
2271 return 0;
2272}
2273
2274/**
2275 * qed_int_igu_init_rt() - Initialize IGU runtime registers.
2276 *
2277 * @p_hwfn: HW device data.
2278 */
2279void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn)
2280{
2281 u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN;
2282
2283 STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);
2284}
2285
2286u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn)
2287{
2288 u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER -
2289 IGU_CMD_INT_ACK_BASE;
2290 u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER -
2291 IGU_CMD_INT_ACK_BASE;
2292 u32 intr_status_hi = 0, intr_status_lo = 0;
2293 u64 intr_status = 0;
2294
2295 intr_status_lo = REG_RD(p_hwfn,
2296 GTT_BAR0_MAP_REG_IGU_CMD +
2297 lsb_igu_cmd_addr * 8);
2298 intr_status_hi = REG_RD(p_hwfn,
2299 GTT_BAR0_MAP_REG_IGU_CMD +
2300 msb_igu_cmd_addr * 8);
2301 intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo;
2302
2303 return intr_status;
2304}
2305
2306static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn)
2307{
2308 tasklet_setup(&p_hwfn->sp_dpc, qed_int_sp_dpc);
2309 p_hwfn->b_sp_dpc_enabled = true;
2310}
2311
2312int qed_int_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2313{
2314 int rc = 0;
2315
2316 rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt);
2317 if (rc)
2318 return rc;
2319
2320 rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt);
2321
2322 return rc;
2323}
2324
2325void qed_int_free(struct qed_hwfn *p_hwfn)
2326{
2327 qed_int_sp_sb_free(p_hwfn);
2328 qed_int_sb_attn_free(p_hwfn);
2329}
2330
2331void qed_int_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2332{
2333 qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);
2334 qed_int_sb_attn_setup(p_hwfn, p_ptt);
2335 qed_int_sp_dpc_setup(p_hwfn);
2336}
2337
2338void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,
2339 struct qed_sb_cnt_info *p_sb_cnt_info)
2340{
2341 struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info;
2342
2343 if (!info || !p_sb_cnt_info)
2344 return;
2345
2346 memcpy(p_sb_cnt_info, &info->usage, sizeof(*p_sb_cnt_info));
2347}
2348
2349void qed_int_disable_post_isr_release(struct qed_dev *cdev)
2350{
2351 int i;
2352
2353 for_each_hwfn(cdev, i)
2354 cdev->hwfns[i].b_int_requested = false;
2355}
2356
2357void qed_int_attn_clr_enable(struct qed_dev *cdev, bool clr_enable)
2358{
2359 cdev->attn_clr_en = clr_enable;
2360}
2361
2362int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2363 u8 timer_res, u16 sb_id, bool tx)
2364{
2365 struct cau_sb_entry sb_entry;
2366 u32 params;
2367 int rc;
2368
2369 if (!p_hwfn->hw_init_done) {
2370 DP_ERR(p_hwfn, "hardware not initialized yet\n");
2371 return -EINVAL;
2372 }
2373
2374 rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2375 sb_id * sizeof(u64),
2376 (u64)(uintptr_t)&sb_entry, 2, NULL);
2377 if (rc) {
2378 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2379 return rc;
2380 }
2381
2382 params = le32_to_cpu(sb_entry.params);
2383
2384 if (tx)
2385 SET_FIELD(params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
2386 else
2387 SET_FIELD(params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
2388
2389 sb_entry.params = cpu_to_le32(params);
2390
2391 rc = qed_dmae_host2grc(p_hwfn, p_ptt,
2392 (u64)(uintptr_t)&sb_entry,
2393 CAU_REG_SB_VAR_MEMORY +
2394 sb_id * sizeof(u64), 2, NULL);
2395 if (rc) {
2396 DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc);
2397 return rc;
2398 }
2399
2400 return rc;
2401}
2402
2403int qed_int_get_sb_dbg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2404 struct qed_sb_info *p_sb, struct qed_sb_info_dbg *p_info)
2405{
2406 u16 sbid = p_sb->igu_sb_id;
2407 u32 i;
2408
2409 if (IS_VF(p_hwfn->cdev))
2410 return -EINVAL;
2411
2412 if (sbid >= NUM_OF_SBS(p_hwfn->cdev))
2413 return -EINVAL;
2414
2415 p_info->igu_prod = qed_rd(p_hwfn, p_ptt, IGU_REG_PRODUCER_MEMORY + sbid * 4);
2416 p_info->igu_cons = qed_rd(p_hwfn, p_ptt, IGU_REG_CONSUMER_MEM + sbid * 4);
2417
2418 for (i = 0; i < PIS_PER_SB; i++)
2419 p_info->pi[i] = (u16)qed_rd(p_hwfn, p_ptt,
2420 CAU_REG_PI_MEMORY + sbid * 4 * PIS_PER_SB + i * 4);
2421
2422 return 0;
2423}
1/* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
9#include <linux/types.h>
10#include <asm/byteorder.h>
11#include <linux/io.h>
12#include <linux/bitops.h>
13#include <linux/delay.h>
14#include <linux/dma-mapping.h>
15#include <linux/errno.h>
16#include <linux/interrupt.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/slab.h>
20#include <linux/string.h>
21#include "qed.h"
22#include "qed_hsi.h"
23#include "qed_hw.h"
24#include "qed_init_ops.h"
25#include "qed_int.h"
26#include "qed_mcp.h"
27#include "qed_reg_addr.h"
28#include "qed_sp.h"
29#include "qed_sriov.h"
30#include "qed_vf.h"
31
32struct qed_pi_info {
33 qed_int_comp_cb_t comp_cb;
34 void *cookie;
35};
36
37struct qed_sb_sp_info {
38 struct qed_sb_info sb_info;
39
40 /* per protocol index data */
41 struct qed_pi_info pi_info_arr[PIS_PER_SB];
42};
43
44enum qed_attention_type {
45 QED_ATTN_TYPE_ATTN,
46 QED_ATTN_TYPE_PARITY,
47};
48
49#define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
50 ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
51
52struct aeu_invert_reg_bit {
53 char bit_name[30];
54
55#define ATTENTION_PARITY (1 << 0)
56
57#define ATTENTION_LENGTH_MASK (0x00000ff0)
58#define ATTENTION_LENGTH_SHIFT (4)
59#define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \
60 ATTENTION_LENGTH_SHIFT)
61#define ATTENTION_SINGLE (1 << ATTENTION_LENGTH_SHIFT)
62#define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY)
63#define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \
64 ATTENTION_PARITY)
65
66/* Multiple bits start with this offset */
67#define ATTENTION_OFFSET_MASK (0x000ff000)
68#define ATTENTION_OFFSET_SHIFT (12)
69 unsigned int flags;
70
71 /* Callback to call if attention will be triggered */
72 int (*cb)(struct qed_hwfn *p_hwfn);
73
74 enum block_id block_index;
75};
76
77struct aeu_invert_reg {
78 struct aeu_invert_reg_bit bits[32];
79};
80
81#define MAX_ATTN_GRPS (8)
82#define NUM_ATTN_REGS (9)
83
84/* HW Attention register */
85struct attn_hw_reg {
86 u16 reg_idx; /* Index of this register in its block */
87 u16 num_of_bits; /* number of valid attention bits */
88 u32 sts_addr; /* Address of the STS register */
89 u32 sts_clr_addr; /* Address of the STS_CLR register */
90 u32 sts_wr_addr; /* Address of the STS_WR register */
91 u32 mask_addr; /* Address of the MASK register */
92};
93
94/* HW block attention registers */
95struct attn_hw_regs {
96 u16 num_of_int_regs; /* Number of interrupt regs */
97 u16 num_of_prty_regs; /* Number of parity regs */
98 struct attn_hw_reg **int_regs; /* interrupt regs */
99 struct attn_hw_reg **prty_regs; /* parity regs */
100};
101
102/* HW block attention registers */
103struct attn_hw_block {
104 const char *name; /* Block name */
105 struct attn_hw_regs chip_regs[1];
106};
107
108static struct attn_hw_reg grc_int0_bb_b0 = {
109 0, 4, 0x50180, 0x5018c, 0x50188, 0x50184};
110
111static struct attn_hw_reg *grc_int_bb_b0_regs[1] = {
112 &grc_int0_bb_b0};
113
114static struct attn_hw_reg grc_prty1_bb_b0 = {
115 0, 2, 0x50200, 0x5020c, 0x50208, 0x50204};
116
117static struct attn_hw_reg *grc_prty_bb_b0_regs[1] = {
118 &grc_prty1_bb_b0};
119
120static struct attn_hw_reg miscs_int0_bb_b0 = {
121 0, 3, 0x9180, 0x918c, 0x9188, 0x9184};
122
123static struct attn_hw_reg miscs_int1_bb_b0 = {
124 1, 11, 0x9190, 0x919c, 0x9198, 0x9194};
125
126static struct attn_hw_reg *miscs_int_bb_b0_regs[2] = {
127 &miscs_int0_bb_b0, &miscs_int1_bb_b0};
128
129static struct attn_hw_reg miscs_prty0_bb_b0 = {
130 0, 1, 0x91a0, 0x91ac, 0x91a8, 0x91a4};
131
132static struct attn_hw_reg *miscs_prty_bb_b0_regs[1] = {
133 &miscs_prty0_bb_b0};
134
135static struct attn_hw_reg misc_int0_bb_b0 = {
136 0, 1, 0x8180, 0x818c, 0x8188, 0x8184};
137
138static struct attn_hw_reg *misc_int_bb_b0_regs[1] = {
139 &misc_int0_bb_b0};
140
141static struct attn_hw_reg pglue_b_int0_bb_b0 = {
142 0, 23, 0x2a8180, 0x2a818c, 0x2a8188, 0x2a8184};
143
144static struct attn_hw_reg *pglue_b_int_bb_b0_regs[1] = {
145 &pglue_b_int0_bb_b0};
146
147static struct attn_hw_reg pglue_b_prty0_bb_b0 = {
148 0, 1, 0x2a8190, 0x2a819c, 0x2a8198, 0x2a8194};
149
150static struct attn_hw_reg pglue_b_prty1_bb_b0 = {
151 1, 22, 0x2a8200, 0x2a820c, 0x2a8208, 0x2a8204};
152
153static struct attn_hw_reg *pglue_b_prty_bb_b0_regs[2] = {
154 &pglue_b_prty0_bb_b0, &pglue_b_prty1_bb_b0};
155
156static struct attn_hw_reg cnig_int0_bb_b0 = {
157 0, 6, 0x2182e8, 0x2182f4, 0x2182f0, 0x2182ec};
158
159static struct attn_hw_reg *cnig_int_bb_b0_regs[1] = {
160 &cnig_int0_bb_b0};
161
162static struct attn_hw_reg cnig_prty0_bb_b0 = {
163 0, 2, 0x218348, 0x218354, 0x218350, 0x21834c};
164
165static struct attn_hw_reg *cnig_prty_bb_b0_regs[1] = {
166 &cnig_prty0_bb_b0};
167
168static struct attn_hw_reg cpmu_int0_bb_b0 = {
169 0, 1, 0x303e0, 0x303ec, 0x303e8, 0x303e4};
170
171static struct attn_hw_reg *cpmu_int_bb_b0_regs[1] = {
172 &cpmu_int0_bb_b0};
173
174static struct attn_hw_reg ncsi_int0_bb_b0 = {
175 0, 1, 0x404cc, 0x404d8, 0x404d4, 0x404d0};
176
177static struct attn_hw_reg *ncsi_int_bb_b0_regs[1] = {
178 &ncsi_int0_bb_b0};
179
180static struct attn_hw_reg ncsi_prty1_bb_b0 = {
181 0, 1, 0x40000, 0x4000c, 0x40008, 0x40004};
182
183static struct attn_hw_reg *ncsi_prty_bb_b0_regs[1] = {
184 &ncsi_prty1_bb_b0};
185
186static struct attn_hw_reg opte_prty1_bb_b0 = {
187 0, 11, 0x53000, 0x5300c, 0x53008, 0x53004};
188
189static struct attn_hw_reg opte_prty0_bb_b0 = {
190 1, 1, 0x53208, 0x53214, 0x53210, 0x5320c};
191
192static struct attn_hw_reg *opte_prty_bb_b0_regs[2] = {
193 &opte_prty1_bb_b0, &opte_prty0_bb_b0};
194
195static struct attn_hw_reg bmb_int0_bb_b0 = {
196 0, 16, 0x5400c0, 0x5400cc, 0x5400c8, 0x5400c4};
197
198static struct attn_hw_reg bmb_int1_bb_b0 = {
199 1, 28, 0x5400d8, 0x5400e4, 0x5400e0, 0x5400dc};
200
201static struct attn_hw_reg bmb_int2_bb_b0 = {
202 2, 26, 0x5400f0, 0x5400fc, 0x5400f8, 0x5400f4};
203
204static struct attn_hw_reg bmb_int3_bb_b0 = {
205 3, 31, 0x540108, 0x540114, 0x540110, 0x54010c};
206
207static struct attn_hw_reg bmb_int4_bb_b0 = {
208 4, 27, 0x540120, 0x54012c, 0x540128, 0x540124};
209
210static struct attn_hw_reg bmb_int5_bb_b0 = {
211 5, 29, 0x540138, 0x540144, 0x540140, 0x54013c};
212
213static struct attn_hw_reg bmb_int6_bb_b0 = {
214 6, 30, 0x540150, 0x54015c, 0x540158, 0x540154};
215
216static struct attn_hw_reg bmb_int7_bb_b0 = {
217 7, 32, 0x540168, 0x540174, 0x540170, 0x54016c};
218
219static struct attn_hw_reg bmb_int8_bb_b0 = {
220 8, 32, 0x540184, 0x540190, 0x54018c, 0x540188};
221
222static struct attn_hw_reg bmb_int9_bb_b0 = {
223 9, 32, 0x54019c, 0x5401a8, 0x5401a4, 0x5401a0};
224
225static struct attn_hw_reg bmb_int10_bb_b0 = {
226 10, 3, 0x5401b4, 0x5401c0, 0x5401bc, 0x5401b8};
227
228static struct attn_hw_reg bmb_int11_bb_b0 = {
229 11, 4, 0x5401cc, 0x5401d8, 0x5401d4, 0x5401d0};
230
231static struct attn_hw_reg *bmb_int_bb_b0_regs[12] = {
232 &bmb_int0_bb_b0, &bmb_int1_bb_b0, &bmb_int2_bb_b0, &bmb_int3_bb_b0,
233 &bmb_int4_bb_b0, &bmb_int5_bb_b0, &bmb_int6_bb_b0, &bmb_int7_bb_b0,
234 &bmb_int8_bb_b0, &bmb_int9_bb_b0, &bmb_int10_bb_b0, &bmb_int11_bb_b0};
235
236static struct attn_hw_reg bmb_prty0_bb_b0 = {
237 0, 5, 0x5401dc, 0x5401e8, 0x5401e4, 0x5401e0};
238
239static struct attn_hw_reg bmb_prty1_bb_b0 = {
240 1, 31, 0x540400, 0x54040c, 0x540408, 0x540404};
241
242static struct attn_hw_reg bmb_prty2_bb_b0 = {
243 2, 15, 0x540410, 0x54041c, 0x540418, 0x540414};
244
245static struct attn_hw_reg *bmb_prty_bb_b0_regs[3] = {
246 &bmb_prty0_bb_b0, &bmb_prty1_bb_b0, &bmb_prty2_bb_b0};
247
248static struct attn_hw_reg pcie_prty1_bb_b0 = {
249 0, 17, 0x54000, 0x5400c, 0x54008, 0x54004};
250
251static struct attn_hw_reg *pcie_prty_bb_b0_regs[1] = {
252 &pcie_prty1_bb_b0};
253
254static struct attn_hw_reg mcp2_prty0_bb_b0 = {
255 0, 1, 0x52040, 0x5204c, 0x52048, 0x52044};
256
257static struct attn_hw_reg mcp2_prty1_bb_b0 = {
258 1, 12, 0x52204, 0x52210, 0x5220c, 0x52208};
259
260static struct attn_hw_reg *mcp2_prty_bb_b0_regs[2] = {
261 &mcp2_prty0_bb_b0, &mcp2_prty1_bb_b0};
262
263static struct attn_hw_reg pswhst_int0_bb_b0 = {
264 0, 18, 0x2a0180, 0x2a018c, 0x2a0188, 0x2a0184};
265
266static struct attn_hw_reg *pswhst_int_bb_b0_regs[1] = {
267 &pswhst_int0_bb_b0};
268
269static struct attn_hw_reg pswhst_prty0_bb_b0 = {
270 0, 1, 0x2a0190, 0x2a019c, 0x2a0198, 0x2a0194};
271
272static struct attn_hw_reg pswhst_prty1_bb_b0 = {
273 1, 17, 0x2a0200, 0x2a020c, 0x2a0208, 0x2a0204};
274
275static struct attn_hw_reg *pswhst_prty_bb_b0_regs[2] = {
276 &pswhst_prty0_bb_b0, &pswhst_prty1_bb_b0};
277
278static struct attn_hw_reg pswhst2_int0_bb_b0 = {
279 0, 5, 0x29e180, 0x29e18c, 0x29e188, 0x29e184};
280
281static struct attn_hw_reg *pswhst2_int_bb_b0_regs[1] = {
282 &pswhst2_int0_bb_b0};
283
284static struct attn_hw_reg pswhst2_prty0_bb_b0 = {
285 0, 1, 0x29e190, 0x29e19c, 0x29e198, 0x29e194};
286
287static struct attn_hw_reg *pswhst2_prty_bb_b0_regs[1] = {
288 &pswhst2_prty0_bb_b0};
289
290static struct attn_hw_reg pswrd_int0_bb_b0 = {
291 0, 3, 0x29c180, 0x29c18c, 0x29c188, 0x29c184};
292
293static struct attn_hw_reg *pswrd_int_bb_b0_regs[1] = {
294 &pswrd_int0_bb_b0};
295
296static struct attn_hw_reg pswrd_prty0_bb_b0 = {
297 0, 1, 0x29c190, 0x29c19c, 0x29c198, 0x29c194};
298
299static struct attn_hw_reg *pswrd_prty_bb_b0_regs[1] = {
300 &pswrd_prty0_bb_b0};
301
302static struct attn_hw_reg pswrd2_int0_bb_b0 = {
303 0, 5, 0x29d180, 0x29d18c, 0x29d188, 0x29d184};
304
305static struct attn_hw_reg *pswrd2_int_bb_b0_regs[1] = {
306 &pswrd2_int0_bb_b0};
307
308static struct attn_hw_reg pswrd2_prty0_bb_b0 = {
309 0, 1, 0x29d190, 0x29d19c, 0x29d198, 0x29d194};
310
311static struct attn_hw_reg pswrd2_prty1_bb_b0 = {
312 1, 31, 0x29d200, 0x29d20c, 0x29d208, 0x29d204};
313
314static struct attn_hw_reg pswrd2_prty2_bb_b0 = {
315 2, 3, 0x29d210, 0x29d21c, 0x29d218, 0x29d214};
316
317static struct attn_hw_reg *pswrd2_prty_bb_b0_regs[3] = {
318 &pswrd2_prty0_bb_b0, &pswrd2_prty1_bb_b0, &pswrd2_prty2_bb_b0};
319
320static struct attn_hw_reg pswwr_int0_bb_b0 = {
321 0, 16, 0x29a180, 0x29a18c, 0x29a188, 0x29a184};
322
323static struct attn_hw_reg *pswwr_int_bb_b0_regs[1] = {
324 &pswwr_int0_bb_b0};
325
326static struct attn_hw_reg pswwr_prty0_bb_b0 = {
327 0, 1, 0x29a190, 0x29a19c, 0x29a198, 0x29a194};
328
329static struct attn_hw_reg *pswwr_prty_bb_b0_regs[1] = {
330 &pswwr_prty0_bb_b0};
331
332static struct attn_hw_reg pswwr2_int0_bb_b0 = {
333 0, 19, 0x29b180, 0x29b18c, 0x29b188, 0x29b184};
334
335static struct attn_hw_reg *pswwr2_int_bb_b0_regs[1] = {
336 &pswwr2_int0_bb_b0};
337
338static struct attn_hw_reg pswwr2_prty0_bb_b0 = {
339 0, 1, 0x29b190, 0x29b19c, 0x29b198, 0x29b194};
340
341static struct attn_hw_reg pswwr2_prty1_bb_b0 = {
342 1, 31, 0x29b200, 0x29b20c, 0x29b208, 0x29b204};
343
344static struct attn_hw_reg pswwr2_prty2_bb_b0 = {
345 2, 31, 0x29b210, 0x29b21c, 0x29b218, 0x29b214};
346
347static struct attn_hw_reg pswwr2_prty3_bb_b0 = {
348 3, 31, 0x29b220, 0x29b22c, 0x29b228, 0x29b224};
349
350static struct attn_hw_reg pswwr2_prty4_bb_b0 = {
351 4, 20, 0x29b230, 0x29b23c, 0x29b238, 0x29b234};
352
353static struct attn_hw_reg *pswwr2_prty_bb_b0_regs[5] = {
354 &pswwr2_prty0_bb_b0, &pswwr2_prty1_bb_b0, &pswwr2_prty2_bb_b0,
355 &pswwr2_prty3_bb_b0, &pswwr2_prty4_bb_b0};
356
357static struct attn_hw_reg pswrq_int0_bb_b0 = {
358 0, 21, 0x280180, 0x28018c, 0x280188, 0x280184};
359
360static struct attn_hw_reg *pswrq_int_bb_b0_regs[1] = {
361 &pswrq_int0_bb_b0};
362
363static struct attn_hw_reg pswrq_prty0_bb_b0 = {
364 0, 1, 0x280190, 0x28019c, 0x280198, 0x280194};
365
366static struct attn_hw_reg *pswrq_prty_bb_b0_regs[1] = {
367 &pswrq_prty0_bb_b0};
368
369static struct attn_hw_reg pswrq2_int0_bb_b0 = {
370 0, 15, 0x240180, 0x24018c, 0x240188, 0x240184};
371
372static struct attn_hw_reg *pswrq2_int_bb_b0_regs[1] = {
373 &pswrq2_int0_bb_b0};
374
375static struct attn_hw_reg pswrq2_prty1_bb_b0 = {
376 0, 9, 0x240200, 0x24020c, 0x240208, 0x240204};
377
378static struct attn_hw_reg *pswrq2_prty_bb_b0_regs[1] = {
379 &pswrq2_prty1_bb_b0};
380
381static struct attn_hw_reg pglcs_int0_bb_b0 = {
382 0, 1, 0x1d00, 0x1d0c, 0x1d08, 0x1d04};
383
384static struct attn_hw_reg *pglcs_int_bb_b0_regs[1] = {
385 &pglcs_int0_bb_b0};
386
387static struct attn_hw_reg dmae_int0_bb_b0 = {
388 0, 2, 0xc180, 0xc18c, 0xc188, 0xc184};
389
390static struct attn_hw_reg *dmae_int_bb_b0_regs[1] = {
391 &dmae_int0_bb_b0};
392
393static struct attn_hw_reg dmae_prty1_bb_b0 = {
394 0, 3, 0xc200, 0xc20c, 0xc208, 0xc204};
395
396static struct attn_hw_reg *dmae_prty_bb_b0_regs[1] = {
397 &dmae_prty1_bb_b0};
398
399static struct attn_hw_reg ptu_int0_bb_b0 = {
400 0, 8, 0x560180, 0x56018c, 0x560188, 0x560184};
401
402static struct attn_hw_reg *ptu_int_bb_b0_regs[1] = {
403 &ptu_int0_bb_b0};
404
405static struct attn_hw_reg ptu_prty1_bb_b0 = {
406 0, 18, 0x560200, 0x56020c, 0x560208, 0x560204};
407
408static struct attn_hw_reg *ptu_prty_bb_b0_regs[1] = {
409 &ptu_prty1_bb_b0};
410
411static struct attn_hw_reg tcm_int0_bb_b0 = {
412 0, 8, 0x1180180, 0x118018c, 0x1180188, 0x1180184};
413
414static struct attn_hw_reg tcm_int1_bb_b0 = {
415 1, 32, 0x1180190, 0x118019c, 0x1180198, 0x1180194};
416
417static struct attn_hw_reg tcm_int2_bb_b0 = {
418 2, 1, 0x11801a0, 0x11801ac, 0x11801a8, 0x11801a4};
419
420static struct attn_hw_reg *tcm_int_bb_b0_regs[3] = {
421 &tcm_int0_bb_b0, &tcm_int1_bb_b0, &tcm_int2_bb_b0};
422
423static struct attn_hw_reg tcm_prty1_bb_b0 = {
424 0, 31, 0x1180200, 0x118020c, 0x1180208, 0x1180204};
425
426static struct attn_hw_reg tcm_prty2_bb_b0 = {
427 1, 2, 0x1180210, 0x118021c, 0x1180218, 0x1180214};
428
429static struct attn_hw_reg *tcm_prty_bb_b0_regs[2] = {
430 &tcm_prty1_bb_b0, &tcm_prty2_bb_b0};
431
432static struct attn_hw_reg mcm_int0_bb_b0 = {
433 0, 14, 0x1200180, 0x120018c, 0x1200188, 0x1200184};
434
435static struct attn_hw_reg mcm_int1_bb_b0 = {
436 1, 26, 0x1200190, 0x120019c, 0x1200198, 0x1200194};
437
438static struct attn_hw_reg mcm_int2_bb_b0 = {
439 2, 1, 0x12001a0, 0x12001ac, 0x12001a8, 0x12001a4};
440
441static struct attn_hw_reg *mcm_int_bb_b0_regs[3] = {
442 &mcm_int0_bb_b0, &mcm_int1_bb_b0, &mcm_int2_bb_b0};
443
444static struct attn_hw_reg mcm_prty1_bb_b0 = {
445 0, 31, 0x1200200, 0x120020c, 0x1200208, 0x1200204};
446
447static struct attn_hw_reg mcm_prty2_bb_b0 = {
448 1, 4, 0x1200210, 0x120021c, 0x1200218, 0x1200214};
449
450static struct attn_hw_reg *mcm_prty_bb_b0_regs[2] = {
451 &mcm_prty1_bb_b0, &mcm_prty2_bb_b0};
452
453static struct attn_hw_reg ucm_int0_bb_b0 = {
454 0, 17, 0x1280180, 0x128018c, 0x1280188, 0x1280184};
455
456static struct attn_hw_reg ucm_int1_bb_b0 = {
457 1, 29, 0x1280190, 0x128019c, 0x1280198, 0x1280194};
458
459static struct attn_hw_reg ucm_int2_bb_b0 = {
460 2, 1, 0x12801a0, 0x12801ac, 0x12801a8, 0x12801a4};
461
462static struct attn_hw_reg *ucm_int_bb_b0_regs[3] = {
463 &ucm_int0_bb_b0, &ucm_int1_bb_b0, &ucm_int2_bb_b0};
464
465static struct attn_hw_reg ucm_prty1_bb_b0 = {
466 0, 31, 0x1280200, 0x128020c, 0x1280208, 0x1280204};
467
468static struct attn_hw_reg ucm_prty2_bb_b0 = {
469 1, 7, 0x1280210, 0x128021c, 0x1280218, 0x1280214};
470
471static struct attn_hw_reg *ucm_prty_bb_b0_regs[2] = {
472 &ucm_prty1_bb_b0, &ucm_prty2_bb_b0};
473
474static struct attn_hw_reg xcm_int0_bb_b0 = {
475 0, 16, 0x1000180, 0x100018c, 0x1000188, 0x1000184};
476
477static struct attn_hw_reg xcm_int1_bb_b0 = {
478 1, 25, 0x1000190, 0x100019c, 0x1000198, 0x1000194};
479
480static struct attn_hw_reg xcm_int2_bb_b0 = {
481 2, 8, 0x10001a0, 0x10001ac, 0x10001a8, 0x10001a4};
482
483static struct attn_hw_reg *xcm_int_bb_b0_regs[3] = {
484 &xcm_int0_bb_b0, &xcm_int1_bb_b0, &xcm_int2_bb_b0};
485
486static struct attn_hw_reg xcm_prty1_bb_b0 = {
487 0, 31, 0x1000200, 0x100020c, 0x1000208, 0x1000204};
488
489static struct attn_hw_reg xcm_prty2_bb_b0 = {
490 1, 11, 0x1000210, 0x100021c, 0x1000218, 0x1000214};
491
492static struct attn_hw_reg *xcm_prty_bb_b0_regs[2] = {
493 &xcm_prty1_bb_b0, &xcm_prty2_bb_b0};
494
495static struct attn_hw_reg ycm_int0_bb_b0 = {
496 0, 13, 0x1080180, 0x108018c, 0x1080188, 0x1080184};
497
498static struct attn_hw_reg ycm_int1_bb_b0 = {
499 1, 23, 0x1080190, 0x108019c, 0x1080198, 0x1080194};
500
501static struct attn_hw_reg ycm_int2_bb_b0 = {
502 2, 1, 0x10801a0, 0x10801ac, 0x10801a8, 0x10801a4};
503
504static struct attn_hw_reg *ycm_int_bb_b0_regs[3] = {
505 &ycm_int0_bb_b0, &ycm_int1_bb_b0, &ycm_int2_bb_b0};
506
507static struct attn_hw_reg ycm_prty1_bb_b0 = {
508 0, 31, 0x1080200, 0x108020c, 0x1080208, 0x1080204};
509
510static struct attn_hw_reg ycm_prty2_bb_b0 = {
511 1, 3, 0x1080210, 0x108021c, 0x1080218, 0x1080214};
512
513static struct attn_hw_reg *ycm_prty_bb_b0_regs[2] = {
514 &ycm_prty1_bb_b0, &ycm_prty2_bb_b0};
515
516static struct attn_hw_reg pcm_int0_bb_b0 = {
517 0, 5, 0x1100180, 0x110018c, 0x1100188, 0x1100184};
518
519static struct attn_hw_reg pcm_int1_bb_b0 = {
520 1, 14, 0x1100190, 0x110019c, 0x1100198, 0x1100194};
521
522static struct attn_hw_reg pcm_int2_bb_b0 = {
523 2, 1, 0x11001a0, 0x11001ac, 0x11001a8, 0x11001a4};
524
525static struct attn_hw_reg *pcm_int_bb_b0_regs[3] = {
526 &pcm_int0_bb_b0, &pcm_int1_bb_b0, &pcm_int2_bb_b0};
527
528static struct attn_hw_reg pcm_prty1_bb_b0 = {
529 0, 11, 0x1100200, 0x110020c, 0x1100208, 0x1100204};
530
531static struct attn_hw_reg *pcm_prty_bb_b0_regs[1] = {
532 &pcm_prty1_bb_b0};
533
534static struct attn_hw_reg qm_int0_bb_b0 = {
535 0, 22, 0x2f0180, 0x2f018c, 0x2f0188, 0x2f0184};
536
537static struct attn_hw_reg *qm_int_bb_b0_regs[1] = {
538 &qm_int0_bb_b0};
539
540static struct attn_hw_reg qm_prty0_bb_b0 = {
541 0, 11, 0x2f0190, 0x2f019c, 0x2f0198, 0x2f0194};
542
543static struct attn_hw_reg qm_prty1_bb_b0 = {
544 1, 31, 0x2f0200, 0x2f020c, 0x2f0208, 0x2f0204};
545
546static struct attn_hw_reg qm_prty2_bb_b0 = {
547 2, 31, 0x2f0210, 0x2f021c, 0x2f0218, 0x2f0214};
548
549static struct attn_hw_reg qm_prty3_bb_b0 = {
550 3, 11, 0x2f0220, 0x2f022c, 0x2f0228, 0x2f0224};
551
552static struct attn_hw_reg *qm_prty_bb_b0_regs[4] = {
553 &qm_prty0_bb_b0, &qm_prty1_bb_b0, &qm_prty2_bb_b0, &qm_prty3_bb_b0};
554
555static struct attn_hw_reg tm_int0_bb_b0 = {
556 0, 32, 0x2c0180, 0x2c018c, 0x2c0188, 0x2c0184};
557
558static struct attn_hw_reg tm_int1_bb_b0 = {
559 1, 11, 0x2c0190, 0x2c019c, 0x2c0198, 0x2c0194};
560
561static struct attn_hw_reg *tm_int_bb_b0_regs[2] = {
562 &tm_int0_bb_b0, &tm_int1_bb_b0};
563
564static struct attn_hw_reg tm_prty1_bb_b0 = {
565 0, 17, 0x2c0200, 0x2c020c, 0x2c0208, 0x2c0204};
566
567static struct attn_hw_reg *tm_prty_bb_b0_regs[1] = {
568 &tm_prty1_bb_b0};
569
570static struct attn_hw_reg dorq_int0_bb_b0 = {
571 0, 9, 0x100180, 0x10018c, 0x100188, 0x100184};
572
573static struct attn_hw_reg *dorq_int_bb_b0_regs[1] = {
574 &dorq_int0_bb_b0};
575
576static struct attn_hw_reg dorq_prty0_bb_b0 = {
577 0, 1, 0x100190, 0x10019c, 0x100198, 0x100194};
578
579static struct attn_hw_reg dorq_prty1_bb_b0 = {
580 1, 6, 0x100200, 0x10020c, 0x100208, 0x100204};
581
582static struct attn_hw_reg *dorq_prty_bb_b0_regs[2] = {
583 &dorq_prty0_bb_b0, &dorq_prty1_bb_b0};
584
585static struct attn_hw_reg brb_int0_bb_b0 = {
586 0, 32, 0x3400c0, 0x3400cc, 0x3400c8, 0x3400c4};
587
588static struct attn_hw_reg brb_int1_bb_b0 = {
589 1, 30, 0x3400d8, 0x3400e4, 0x3400e0, 0x3400dc};
590
591static struct attn_hw_reg brb_int2_bb_b0 = {
592 2, 28, 0x3400f0, 0x3400fc, 0x3400f8, 0x3400f4};
593
594static struct attn_hw_reg brb_int3_bb_b0 = {
595 3, 31, 0x340108, 0x340114, 0x340110, 0x34010c};
596
597static struct attn_hw_reg brb_int4_bb_b0 = {
598 4, 27, 0x340120, 0x34012c, 0x340128, 0x340124};
599
600static struct attn_hw_reg brb_int5_bb_b0 = {
601 5, 1, 0x340138, 0x340144, 0x340140, 0x34013c};
602
603static struct attn_hw_reg brb_int6_bb_b0 = {
604 6, 8, 0x340150, 0x34015c, 0x340158, 0x340154};
605
606static struct attn_hw_reg brb_int7_bb_b0 = {
607 7, 32, 0x340168, 0x340174, 0x340170, 0x34016c};
608
609static struct attn_hw_reg brb_int8_bb_b0 = {
610 8, 17, 0x340184, 0x340190, 0x34018c, 0x340188};
611
612static struct attn_hw_reg brb_int9_bb_b0 = {
613 9, 1, 0x34019c, 0x3401a8, 0x3401a4, 0x3401a0};
614
615static struct attn_hw_reg brb_int10_bb_b0 = {
616 10, 14, 0x3401b4, 0x3401c0, 0x3401bc, 0x3401b8};
617
618static struct attn_hw_reg brb_int11_bb_b0 = {
619 11, 8, 0x3401cc, 0x3401d8, 0x3401d4, 0x3401d0};
620
621static struct attn_hw_reg *brb_int_bb_b0_regs[12] = {
622 &brb_int0_bb_b0, &brb_int1_bb_b0, &brb_int2_bb_b0, &brb_int3_bb_b0,
623 &brb_int4_bb_b0, &brb_int5_bb_b0, &brb_int6_bb_b0, &brb_int7_bb_b0,
624 &brb_int8_bb_b0, &brb_int9_bb_b0, &brb_int10_bb_b0, &brb_int11_bb_b0};
625
626static struct attn_hw_reg brb_prty0_bb_b0 = {
627 0, 5, 0x3401dc, 0x3401e8, 0x3401e4, 0x3401e0};
628
629static struct attn_hw_reg brb_prty1_bb_b0 = {
630 1, 31, 0x340400, 0x34040c, 0x340408, 0x340404};
631
632static struct attn_hw_reg brb_prty2_bb_b0 = {
633 2, 14, 0x340410, 0x34041c, 0x340418, 0x340414};
634
635static struct attn_hw_reg *brb_prty_bb_b0_regs[3] = {
636 &brb_prty0_bb_b0, &brb_prty1_bb_b0, &brb_prty2_bb_b0};
637
638static struct attn_hw_reg src_int0_bb_b0 = {
639 0, 1, 0x2381d8, 0x2381dc, 0x2381e0, 0x2381e4};
640
641static struct attn_hw_reg *src_int_bb_b0_regs[1] = {
642 &src_int0_bb_b0};
643
644static struct attn_hw_reg prs_int0_bb_b0 = {
645 0, 2, 0x1f0040, 0x1f004c, 0x1f0048, 0x1f0044};
646
647static struct attn_hw_reg *prs_int_bb_b0_regs[1] = {
648 &prs_int0_bb_b0};
649
650static struct attn_hw_reg prs_prty0_bb_b0 = {
651 0, 2, 0x1f0050, 0x1f005c, 0x1f0058, 0x1f0054};
652
653static struct attn_hw_reg prs_prty1_bb_b0 = {
654 1, 31, 0x1f0204, 0x1f0210, 0x1f020c, 0x1f0208};
655
656static struct attn_hw_reg prs_prty2_bb_b0 = {
657 2, 5, 0x1f0214, 0x1f0220, 0x1f021c, 0x1f0218};
658
659static struct attn_hw_reg *prs_prty_bb_b0_regs[3] = {
660 &prs_prty0_bb_b0, &prs_prty1_bb_b0, &prs_prty2_bb_b0};
661
662static struct attn_hw_reg tsdm_int0_bb_b0 = {
663 0, 26, 0xfb0040, 0xfb004c, 0xfb0048, 0xfb0044};
664
665static struct attn_hw_reg *tsdm_int_bb_b0_regs[1] = {
666 &tsdm_int0_bb_b0};
667
668static struct attn_hw_reg tsdm_prty1_bb_b0 = {
669 0, 10, 0xfb0200, 0xfb020c, 0xfb0208, 0xfb0204};
670
671static struct attn_hw_reg *tsdm_prty_bb_b0_regs[1] = {
672 &tsdm_prty1_bb_b0};
673
674static struct attn_hw_reg msdm_int0_bb_b0 = {
675 0, 26, 0xfc0040, 0xfc004c, 0xfc0048, 0xfc0044};
676
677static struct attn_hw_reg *msdm_int_bb_b0_regs[1] = {
678 &msdm_int0_bb_b0};
679
680static struct attn_hw_reg msdm_prty1_bb_b0 = {
681 0, 11, 0xfc0200, 0xfc020c, 0xfc0208, 0xfc0204};
682
683static struct attn_hw_reg *msdm_prty_bb_b0_regs[1] = {
684 &msdm_prty1_bb_b0};
685
686static struct attn_hw_reg usdm_int0_bb_b0 = {
687 0, 26, 0xfd0040, 0xfd004c, 0xfd0048, 0xfd0044};
688
689static struct attn_hw_reg *usdm_int_bb_b0_regs[1] = {
690 &usdm_int0_bb_b0};
691
692static struct attn_hw_reg usdm_prty1_bb_b0 = {
693 0, 10, 0xfd0200, 0xfd020c, 0xfd0208, 0xfd0204};
694
695static struct attn_hw_reg *usdm_prty_bb_b0_regs[1] = {
696 &usdm_prty1_bb_b0};
697
698static struct attn_hw_reg xsdm_int0_bb_b0 = {
699 0, 26, 0xf80040, 0xf8004c, 0xf80048, 0xf80044};
700
701static struct attn_hw_reg *xsdm_int_bb_b0_regs[1] = {
702 &xsdm_int0_bb_b0};
703
704static struct attn_hw_reg xsdm_prty1_bb_b0 = {
705 0, 10, 0xf80200, 0xf8020c, 0xf80208, 0xf80204};
706
707static struct attn_hw_reg *xsdm_prty_bb_b0_regs[1] = {
708 &xsdm_prty1_bb_b0};
709
710static struct attn_hw_reg ysdm_int0_bb_b0 = {
711 0, 26, 0xf90040, 0xf9004c, 0xf90048, 0xf90044};
712
713static struct attn_hw_reg *ysdm_int_bb_b0_regs[1] = {
714 &ysdm_int0_bb_b0};
715
716static struct attn_hw_reg ysdm_prty1_bb_b0 = {
717 0, 9, 0xf90200, 0xf9020c, 0xf90208, 0xf90204};
718
719static struct attn_hw_reg *ysdm_prty_bb_b0_regs[1] = {
720 &ysdm_prty1_bb_b0};
721
722static struct attn_hw_reg psdm_int0_bb_b0 = {
723 0, 26, 0xfa0040, 0xfa004c, 0xfa0048, 0xfa0044};
724
725static struct attn_hw_reg *psdm_int_bb_b0_regs[1] = {
726 &psdm_int0_bb_b0};
727
728static struct attn_hw_reg psdm_prty1_bb_b0 = {
729 0, 9, 0xfa0200, 0xfa020c, 0xfa0208, 0xfa0204};
730
731static struct attn_hw_reg *psdm_prty_bb_b0_regs[1] = {
732 &psdm_prty1_bb_b0};
733
734static struct attn_hw_reg tsem_int0_bb_b0 = {
735 0, 32, 0x1700040, 0x170004c, 0x1700048, 0x1700044};
736
737static struct attn_hw_reg tsem_int1_bb_b0 = {
738 1, 13, 0x1700050, 0x170005c, 0x1700058, 0x1700054};
739
740static struct attn_hw_reg tsem_fast_memory_int0_bb_b0 = {
741 2, 1, 0x1740040, 0x174004c, 0x1740048, 0x1740044};
742
743static struct attn_hw_reg *tsem_int_bb_b0_regs[3] = {
744 &tsem_int0_bb_b0, &tsem_int1_bb_b0, &tsem_fast_memory_int0_bb_b0};
745
746static struct attn_hw_reg tsem_prty0_bb_b0 = {
747 0, 3, 0x17000c8, 0x17000d4, 0x17000d0, 0x17000cc};
748
749static struct attn_hw_reg tsem_prty1_bb_b0 = {
750 1, 6, 0x1700200, 0x170020c, 0x1700208, 0x1700204};
751
752static struct attn_hw_reg tsem_fast_memory_vfc_config_prty1_bb_b0 = {
753 2, 6, 0x174a200, 0x174a20c, 0x174a208, 0x174a204};
754
755static struct attn_hw_reg *tsem_prty_bb_b0_regs[3] = {
756 &tsem_prty0_bb_b0, &tsem_prty1_bb_b0,
757 &tsem_fast_memory_vfc_config_prty1_bb_b0};
758
759static struct attn_hw_reg msem_int0_bb_b0 = {
760 0, 32, 0x1800040, 0x180004c, 0x1800048, 0x1800044};
761
762static struct attn_hw_reg msem_int1_bb_b0 = {
763 1, 13, 0x1800050, 0x180005c, 0x1800058, 0x1800054};
764
765static struct attn_hw_reg msem_fast_memory_int0_bb_b0 = {
766 2, 1, 0x1840040, 0x184004c, 0x1840048, 0x1840044};
767
768static struct attn_hw_reg *msem_int_bb_b0_regs[3] = {
769 &msem_int0_bb_b0, &msem_int1_bb_b0, &msem_fast_memory_int0_bb_b0};
770
771static struct attn_hw_reg msem_prty0_bb_b0 = {
772 0, 3, 0x18000c8, 0x18000d4, 0x18000d0, 0x18000cc};
773
774static struct attn_hw_reg msem_prty1_bb_b0 = {
775 1, 6, 0x1800200, 0x180020c, 0x1800208, 0x1800204};
776
777static struct attn_hw_reg *msem_prty_bb_b0_regs[2] = {
778 &msem_prty0_bb_b0, &msem_prty1_bb_b0};
779
780static struct attn_hw_reg usem_int0_bb_b0 = {
781 0, 32, 0x1900040, 0x190004c, 0x1900048, 0x1900044};
782
783static struct attn_hw_reg usem_int1_bb_b0 = {
784 1, 13, 0x1900050, 0x190005c, 0x1900058, 0x1900054};
785
786static struct attn_hw_reg usem_fast_memory_int0_bb_b0 = {
787 2, 1, 0x1940040, 0x194004c, 0x1940048, 0x1940044};
788
789static struct attn_hw_reg *usem_int_bb_b0_regs[3] = {
790 &usem_int0_bb_b0, &usem_int1_bb_b0, &usem_fast_memory_int0_bb_b0};
791
792static struct attn_hw_reg usem_prty0_bb_b0 = {
793 0, 3, 0x19000c8, 0x19000d4, 0x19000d0, 0x19000cc};
794
795static struct attn_hw_reg usem_prty1_bb_b0 = {
796 1, 6, 0x1900200, 0x190020c, 0x1900208, 0x1900204};
797
798static struct attn_hw_reg *usem_prty_bb_b0_regs[2] = {
799 &usem_prty0_bb_b0, &usem_prty1_bb_b0};
800
801static struct attn_hw_reg xsem_int0_bb_b0 = {
802 0, 32, 0x1400040, 0x140004c, 0x1400048, 0x1400044};
803
804static struct attn_hw_reg xsem_int1_bb_b0 = {
805 1, 13, 0x1400050, 0x140005c, 0x1400058, 0x1400054};
806
807static struct attn_hw_reg xsem_fast_memory_int0_bb_b0 = {
808 2, 1, 0x1440040, 0x144004c, 0x1440048, 0x1440044};
809
810static struct attn_hw_reg *xsem_int_bb_b0_regs[3] = {
811 &xsem_int0_bb_b0, &xsem_int1_bb_b0, &xsem_fast_memory_int0_bb_b0};
812
813static struct attn_hw_reg xsem_prty0_bb_b0 = {
814 0, 3, 0x14000c8, 0x14000d4, 0x14000d0, 0x14000cc};
815
816static struct attn_hw_reg xsem_prty1_bb_b0 = {
817 1, 7, 0x1400200, 0x140020c, 0x1400208, 0x1400204};
818
819static struct attn_hw_reg *xsem_prty_bb_b0_regs[2] = {
820 &xsem_prty0_bb_b0, &xsem_prty1_bb_b0};
821
822static struct attn_hw_reg ysem_int0_bb_b0 = {
823 0, 32, 0x1500040, 0x150004c, 0x1500048, 0x1500044};
824
825static struct attn_hw_reg ysem_int1_bb_b0 = {
826 1, 13, 0x1500050, 0x150005c, 0x1500058, 0x1500054};
827
828static struct attn_hw_reg ysem_fast_memory_int0_bb_b0 = {
829 2, 1, 0x1540040, 0x154004c, 0x1540048, 0x1540044};
830
831static struct attn_hw_reg *ysem_int_bb_b0_regs[3] = {
832 &ysem_int0_bb_b0, &ysem_int1_bb_b0, &ysem_fast_memory_int0_bb_b0};
833
834static struct attn_hw_reg ysem_prty0_bb_b0 = {
835 0, 3, 0x15000c8, 0x15000d4, 0x15000d0, 0x15000cc};
836
837static struct attn_hw_reg ysem_prty1_bb_b0 = {
838 1, 7, 0x1500200, 0x150020c, 0x1500208, 0x1500204};
839
840static struct attn_hw_reg *ysem_prty_bb_b0_regs[2] = {
841 &ysem_prty0_bb_b0, &ysem_prty1_bb_b0};
842
843static struct attn_hw_reg psem_int0_bb_b0 = {
844 0, 32, 0x1600040, 0x160004c, 0x1600048, 0x1600044};
845
846static struct attn_hw_reg psem_int1_bb_b0 = {
847 1, 13, 0x1600050, 0x160005c, 0x1600058, 0x1600054};
848
849static struct attn_hw_reg psem_fast_memory_int0_bb_b0 = {
850 2, 1, 0x1640040, 0x164004c, 0x1640048, 0x1640044};
851
852static struct attn_hw_reg *psem_int_bb_b0_regs[3] = {
853 &psem_int0_bb_b0, &psem_int1_bb_b0, &psem_fast_memory_int0_bb_b0};
854
855static struct attn_hw_reg psem_prty0_bb_b0 = {
856 0, 3, 0x16000c8, 0x16000d4, 0x16000d0, 0x16000cc};
857
858static struct attn_hw_reg psem_prty1_bb_b0 = {
859 1, 6, 0x1600200, 0x160020c, 0x1600208, 0x1600204};
860
861static struct attn_hw_reg psem_fast_memory_vfc_config_prty1_bb_b0 = {
862 2, 6, 0x164a200, 0x164a20c, 0x164a208, 0x164a204};
863
864static struct attn_hw_reg *psem_prty_bb_b0_regs[3] = {
865 &psem_prty0_bb_b0, &psem_prty1_bb_b0,
866 &psem_fast_memory_vfc_config_prty1_bb_b0};
867
868static struct attn_hw_reg rss_int0_bb_b0 = {
869 0, 12, 0x238980, 0x23898c, 0x238988, 0x238984};
870
871static struct attn_hw_reg *rss_int_bb_b0_regs[1] = {
872 &rss_int0_bb_b0};
873
874static struct attn_hw_reg rss_prty1_bb_b0 = {
875 0, 4, 0x238a00, 0x238a0c, 0x238a08, 0x238a04};
876
877static struct attn_hw_reg *rss_prty_bb_b0_regs[1] = {
878 &rss_prty1_bb_b0};
879
880static struct attn_hw_reg tmld_int0_bb_b0 = {
881 0, 6, 0x4d0180, 0x4d018c, 0x4d0188, 0x4d0184};
882
883static struct attn_hw_reg *tmld_int_bb_b0_regs[1] = {
884 &tmld_int0_bb_b0};
885
886static struct attn_hw_reg tmld_prty1_bb_b0 = {
887 0, 8, 0x4d0200, 0x4d020c, 0x4d0208, 0x4d0204};
888
889static struct attn_hw_reg *tmld_prty_bb_b0_regs[1] = {
890 &tmld_prty1_bb_b0};
891
892static struct attn_hw_reg muld_int0_bb_b0 = {
893 0, 6, 0x4e0180, 0x4e018c, 0x4e0188, 0x4e0184};
894
895static struct attn_hw_reg *muld_int_bb_b0_regs[1] = {
896 &muld_int0_bb_b0};
897
898static struct attn_hw_reg muld_prty1_bb_b0 = {
899 0, 10, 0x4e0200, 0x4e020c, 0x4e0208, 0x4e0204};
900
901static struct attn_hw_reg *muld_prty_bb_b0_regs[1] = {
902 &muld_prty1_bb_b0};
903
904static struct attn_hw_reg yuld_int0_bb_b0 = {
905 0, 6, 0x4c8180, 0x4c818c, 0x4c8188, 0x4c8184};
906
907static struct attn_hw_reg *yuld_int_bb_b0_regs[1] = {
908 &yuld_int0_bb_b0};
909
910static struct attn_hw_reg yuld_prty1_bb_b0 = {
911 0, 6, 0x4c8200, 0x4c820c, 0x4c8208, 0x4c8204};
912
913static struct attn_hw_reg *yuld_prty_bb_b0_regs[1] = {
914 &yuld_prty1_bb_b0};
915
916static struct attn_hw_reg xyld_int0_bb_b0 = {
917 0, 6, 0x4c0180, 0x4c018c, 0x4c0188, 0x4c0184};
918
919static struct attn_hw_reg *xyld_int_bb_b0_regs[1] = {
920 &xyld_int0_bb_b0};
921
922static struct attn_hw_reg xyld_prty1_bb_b0 = {
923 0, 9, 0x4c0200, 0x4c020c, 0x4c0208, 0x4c0204};
924
925static struct attn_hw_reg *xyld_prty_bb_b0_regs[1] = {
926 &xyld_prty1_bb_b0};
927
928static struct attn_hw_reg prm_int0_bb_b0 = {
929 0, 11, 0x230040, 0x23004c, 0x230048, 0x230044};
930
931static struct attn_hw_reg *prm_int_bb_b0_regs[1] = {
932 &prm_int0_bb_b0};
933
934static struct attn_hw_reg prm_prty0_bb_b0 = {
935 0, 1, 0x230050, 0x23005c, 0x230058, 0x230054};
936
937static struct attn_hw_reg prm_prty1_bb_b0 = {
938 1, 24, 0x230200, 0x23020c, 0x230208, 0x230204};
939
940static struct attn_hw_reg *prm_prty_bb_b0_regs[2] = {
941 &prm_prty0_bb_b0, &prm_prty1_bb_b0};
942
943static struct attn_hw_reg pbf_pb1_int0_bb_b0 = {
944 0, 9, 0xda0040, 0xda004c, 0xda0048, 0xda0044};
945
946static struct attn_hw_reg *pbf_pb1_int_bb_b0_regs[1] = {
947 &pbf_pb1_int0_bb_b0};
948
949static struct attn_hw_reg pbf_pb1_prty0_bb_b0 = {
950 0, 1, 0xda0050, 0xda005c, 0xda0058, 0xda0054};
951
952static struct attn_hw_reg *pbf_pb1_prty_bb_b0_regs[1] = {
953 &pbf_pb1_prty0_bb_b0};
954
955static struct attn_hw_reg pbf_pb2_int0_bb_b0 = {
956 0, 9, 0xda4040, 0xda404c, 0xda4048, 0xda4044};
957
958static struct attn_hw_reg *pbf_pb2_int_bb_b0_regs[1] = {
959 &pbf_pb2_int0_bb_b0};
960
961static struct attn_hw_reg pbf_pb2_prty0_bb_b0 = {
962 0, 1, 0xda4050, 0xda405c, 0xda4058, 0xda4054};
963
964static struct attn_hw_reg *pbf_pb2_prty_bb_b0_regs[1] = {
965 &pbf_pb2_prty0_bb_b0};
966
967static struct attn_hw_reg rpb_int0_bb_b0 = {
968 0, 9, 0x23c040, 0x23c04c, 0x23c048, 0x23c044};
969
970static struct attn_hw_reg *rpb_int_bb_b0_regs[1] = {
971 &rpb_int0_bb_b0};
972
973static struct attn_hw_reg rpb_prty0_bb_b0 = {
974 0, 1, 0x23c050, 0x23c05c, 0x23c058, 0x23c054};
975
976static struct attn_hw_reg *rpb_prty_bb_b0_regs[1] = {
977 &rpb_prty0_bb_b0};
978
979static struct attn_hw_reg btb_int0_bb_b0 = {
980 0, 16, 0xdb00c0, 0xdb00cc, 0xdb00c8, 0xdb00c4};
981
982static struct attn_hw_reg btb_int1_bb_b0 = {
983 1, 16, 0xdb00d8, 0xdb00e4, 0xdb00e0, 0xdb00dc};
984
985static struct attn_hw_reg btb_int2_bb_b0 = {
986 2, 4, 0xdb00f0, 0xdb00fc, 0xdb00f8, 0xdb00f4};
987
988static struct attn_hw_reg btb_int3_bb_b0 = {
989 3, 32, 0xdb0108, 0xdb0114, 0xdb0110, 0xdb010c};
990
991static struct attn_hw_reg btb_int4_bb_b0 = {
992 4, 23, 0xdb0120, 0xdb012c, 0xdb0128, 0xdb0124};
993
994static struct attn_hw_reg btb_int5_bb_b0 = {
995 5, 32, 0xdb0138, 0xdb0144, 0xdb0140, 0xdb013c};
996
997static struct attn_hw_reg btb_int6_bb_b0 = {
998 6, 1, 0xdb0150, 0xdb015c, 0xdb0158, 0xdb0154};
999
1000static struct attn_hw_reg btb_int8_bb_b0 = {
1001 7, 1, 0xdb0184, 0xdb0190, 0xdb018c, 0xdb0188};
1002
1003static struct attn_hw_reg btb_int9_bb_b0 = {
1004 8, 1, 0xdb019c, 0xdb01a8, 0xdb01a4, 0xdb01a0};
1005
1006static struct attn_hw_reg btb_int10_bb_b0 = {
1007 9, 1, 0xdb01b4, 0xdb01c0, 0xdb01bc, 0xdb01b8};
1008
1009static struct attn_hw_reg btb_int11_bb_b0 = {
1010 10, 2, 0xdb01cc, 0xdb01d8, 0xdb01d4, 0xdb01d0};
1011
1012static struct attn_hw_reg *btb_int_bb_b0_regs[11] = {
1013 &btb_int0_bb_b0, &btb_int1_bb_b0, &btb_int2_bb_b0, &btb_int3_bb_b0,
1014 &btb_int4_bb_b0, &btb_int5_bb_b0, &btb_int6_bb_b0, &btb_int8_bb_b0,
1015 &btb_int9_bb_b0, &btb_int10_bb_b0, &btb_int11_bb_b0};
1016
1017static struct attn_hw_reg btb_prty0_bb_b0 = {
1018 0, 5, 0xdb01dc, 0xdb01e8, 0xdb01e4, 0xdb01e0};
1019
1020static struct attn_hw_reg btb_prty1_bb_b0 = {
1021 1, 23, 0xdb0400, 0xdb040c, 0xdb0408, 0xdb0404};
1022
1023static struct attn_hw_reg *btb_prty_bb_b0_regs[2] = {
1024 &btb_prty0_bb_b0, &btb_prty1_bb_b0};
1025
1026static struct attn_hw_reg pbf_int0_bb_b0 = {
1027 0, 1, 0xd80180, 0xd8018c, 0xd80188, 0xd80184};
1028
1029static struct attn_hw_reg *pbf_int_bb_b0_regs[1] = {
1030 &pbf_int0_bb_b0};
1031
1032static struct attn_hw_reg pbf_prty0_bb_b0 = {
1033 0, 1, 0xd80190, 0xd8019c, 0xd80198, 0xd80194};
1034
1035static struct attn_hw_reg pbf_prty1_bb_b0 = {
1036 1, 31, 0xd80200, 0xd8020c, 0xd80208, 0xd80204};
1037
1038static struct attn_hw_reg pbf_prty2_bb_b0 = {
1039 2, 27, 0xd80210, 0xd8021c, 0xd80218, 0xd80214};
1040
1041static struct attn_hw_reg *pbf_prty_bb_b0_regs[3] = {
1042 &pbf_prty0_bb_b0, &pbf_prty1_bb_b0, &pbf_prty2_bb_b0};
1043
1044static struct attn_hw_reg rdif_int0_bb_b0 = {
1045 0, 8, 0x300180, 0x30018c, 0x300188, 0x300184};
1046
1047static struct attn_hw_reg *rdif_int_bb_b0_regs[1] = {
1048 &rdif_int0_bb_b0};
1049
1050static struct attn_hw_reg rdif_prty0_bb_b0 = {
1051 0, 1, 0x300190, 0x30019c, 0x300198, 0x300194};
1052
1053static struct attn_hw_reg *rdif_prty_bb_b0_regs[1] = {
1054 &rdif_prty0_bb_b0};
1055
1056static struct attn_hw_reg tdif_int0_bb_b0 = {
1057 0, 8, 0x310180, 0x31018c, 0x310188, 0x310184};
1058
1059static struct attn_hw_reg *tdif_int_bb_b0_regs[1] = {
1060 &tdif_int0_bb_b0};
1061
1062static struct attn_hw_reg tdif_prty0_bb_b0 = {
1063 0, 1, 0x310190, 0x31019c, 0x310198, 0x310194};
1064
1065static struct attn_hw_reg tdif_prty1_bb_b0 = {
1066 1, 11, 0x310200, 0x31020c, 0x310208, 0x310204};
1067
1068static struct attn_hw_reg *tdif_prty_bb_b0_regs[2] = {
1069 &tdif_prty0_bb_b0, &tdif_prty1_bb_b0};
1070
1071static struct attn_hw_reg cdu_int0_bb_b0 = {
1072 0, 8, 0x5801c0, 0x5801c4, 0x5801c8, 0x5801cc};
1073
1074static struct attn_hw_reg *cdu_int_bb_b0_regs[1] = {
1075 &cdu_int0_bb_b0};
1076
1077static struct attn_hw_reg cdu_prty1_bb_b0 = {
1078 0, 5, 0x580200, 0x58020c, 0x580208, 0x580204};
1079
1080static struct attn_hw_reg *cdu_prty_bb_b0_regs[1] = {
1081 &cdu_prty1_bb_b0};
1082
1083static struct attn_hw_reg ccfc_int0_bb_b0 = {
1084 0, 2, 0x2e0180, 0x2e018c, 0x2e0188, 0x2e0184};
1085
1086static struct attn_hw_reg *ccfc_int_bb_b0_regs[1] = {
1087 &ccfc_int0_bb_b0};
1088
1089static struct attn_hw_reg ccfc_prty1_bb_b0 = {
1090 0, 2, 0x2e0200, 0x2e020c, 0x2e0208, 0x2e0204};
1091
1092static struct attn_hw_reg ccfc_prty0_bb_b0 = {
1093 1, 6, 0x2e05e4, 0x2e05f0, 0x2e05ec, 0x2e05e8};
1094
1095static struct attn_hw_reg *ccfc_prty_bb_b0_regs[2] = {
1096 &ccfc_prty1_bb_b0, &ccfc_prty0_bb_b0};
1097
1098static struct attn_hw_reg tcfc_int0_bb_b0 = {
1099 0, 2, 0x2d0180, 0x2d018c, 0x2d0188, 0x2d0184};
1100
1101static struct attn_hw_reg *tcfc_int_bb_b0_regs[1] = {
1102 &tcfc_int0_bb_b0};
1103
1104static struct attn_hw_reg tcfc_prty1_bb_b0 = {
1105 0, 2, 0x2d0200, 0x2d020c, 0x2d0208, 0x2d0204};
1106
1107static struct attn_hw_reg tcfc_prty0_bb_b0 = {
1108 1, 6, 0x2d05e4, 0x2d05f0, 0x2d05ec, 0x2d05e8};
1109
1110static struct attn_hw_reg *tcfc_prty_bb_b0_regs[2] = {
1111 &tcfc_prty1_bb_b0, &tcfc_prty0_bb_b0};
1112
1113static struct attn_hw_reg igu_int0_bb_b0 = {
1114 0, 11, 0x180180, 0x18018c, 0x180188, 0x180184};
1115
1116static struct attn_hw_reg *igu_int_bb_b0_regs[1] = {
1117 &igu_int0_bb_b0};
1118
1119static struct attn_hw_reg igu_prty0_bb_b0 = {
1120 0, 1, 0x180190, 0x18019c, 0x180198, 0x180194};
1121
1122static struct attn_hw_reg igu_prty1_bb_b0 = {
1123 1, 31, 0x180200, 0x18020c, 0x180208, 0x180204};
1124
1125static struct attn_hw_reg igu_prty2_bb_b0 = {
1126 2, 1, 0x180210, 0x18021c, 0x180218, 0x180214};
1127
1128static struct attn_hw_reg *igu_prty_bb_b0_regs[3] = {
1129 &igu_prty0_bb_b0, &igu_prty1_bb_b0, &igu_prty2_bb_b0};
1130
1131static struct attn_hw_reg cau_int0_bb_b0 = {
1132 0, 11, 0x1c00d4, 0x1c00d8, 0x1c00dc, 0x1c00e0};
1133
1134static struct attn_hw_reg *cau_int_bb_b0_regs[1] = {
1135 &cau_int0_bb_b0};
1136
1137static struct attn_hw_reg cau_prty1_bb_b0 = {
1138 0, 13, 0x1c0200, 0x1c020c, 0x1c0208, 0x1c0204};
1139
1140static struct attn_hw_reg *cau_prty_bb_b0_regs[1] = {
1141 &cau_prty1_bb_b0};
1142
1143static struct attn_hw_reg dbg_int0_bb_b0 = {
1144 0, 1, 0x10180, 0x1018c, 0x10188, 0x10184};
1145
1146static struct attn_hw_reg *dbg_int_bb_b0_regs[1] = {
1147 &dbg_int0_bb_b0};
1148
1149static struct attn_hw_reg dbg_prty1_bb_b0 = {
1150 0, 1, 0x10200, 0x1020c, 0x10208, 0x10204};
1151
1152static struct attn_hw_reg *dbg_prty_bb_b0_regs[1] = {
1153 &dbg_prty1_bb_b0};
1154
1155static struct attn_hw_reg nig_int0_bb_b0 = {
1156 0, 12, 0x500040, 0x50004c, 0x500048, 0x500044};
1157
1158static struct attn_hw_reg nig_int1_bb_b0 = {
1159 1, 32, 0x500050, 0x50005c, 0x500058, 0x500054};
1160
1161static struct attn_hw_reg nig_int2_bb_b0 = {
1162 2, 20, 0x500060, 0x50006c, 0x500068, 0x500064};
1163
1164static struct attn_hw_reg nig_int3_bb_b0 = {
1165 3, 18, 0x500070, 0x50007c, 0x500078, 0x500074};
1166
1167static struct attn_hw_reg nig_int4_bb_b0 = {
1168 4, 20, 0x500080, 0x50008c, 0x500088, 0x500084};
1169
1170static struct attn_hw_reg nig_int5_bb_b0 = {
1171 5, 18, 0x500090, 0x50009c, 0x500098, 0x500094};
1172
1173static struct attn_hw_reg *nig_int_bb_b0_regs[6] = {
1174 &nig_int0_bb_b0, &nig_int1_bb_b0, &nig_int2_bb_b0, &nig_int3_bb_b0,
1175 &nig_int4_bb_b0, &nig_int5_bb_b0};
1176
1177static struct attn_hw_reg nig_prty0_bb_b0 = {
1178 0, 1, 0x5000a0, 0x5000ac, 0x5000a8, 0x5000a4};
1179
1180static struct attn_hw_reg nig_prty1_bb_b0 = {
1181 1, 31, 0x500200, 0x50020c, 0x500208, 0x500204};
1182
1183static struct attn_hw_reg nig_prty2_bb_b0 = {
1184 2, 31, 0x500210, 0x50021c, 0x500218, 0x500214};
1185
1186static struct attn_hw_reg nig_prty3_bb_b0 = {
1187 3, 31, 0x500220, 0x50022c, 0x500228, 0x500224};
1188
1189static struct attn_hw_reg nig_prty4_bb_b0 = {
1190 4, 17, 0x500230, 0x50023c, 0x500238, 0x500234};
1191
1192static struct attn_hw_reg *nig_prty_bb_b0_regs[5] = {
1193 &nig_prty0_bb_b0, &nig_prty1_bb_b0, &nig_prty2_bb_b0,
1194 &nig_prty3_bb_b0, &nig_prty4_bb_b0};
1195
1196static struct attn_hw_reg ipc_int0_bb_b0 = {
1197 0, 13, 0x2050c, 0x20518, 0x20514, 0x20510};
1198
1199static struct attn_hw_reg *ipc_int_bb_b0_regs[1] = {
1200 &ipc_int0_bb_b0};
1201
1202static struct attn_hw_reg ipc_prty0_bb_b0 = {
1203 0, 1, 0x2051c, 0x20528, 0x20524, 0x20520};
1204
1205static struct attn_hw_reg *ipc_prty_bb_b0_regs[1] = {
1206 &ipc_prty0_bb_b0};
1207
1208static struct attn_hw_block attn_blocks[] = {
1209 {"grc", {{1, 1, grc_int_bb_b0_regs, grc_prty_bb_b0_regs} } },
1210 {"miscs", {{2, 1, miscs_int_bb_b0_regs, miscs_prty_bb_b0_regs} } },
1211 {"misc", {{1, 0, misc_int_bb_b0_regs, NULL} } },
1212 {"dbu", {{0, 0, NULL, NULL} } },
1213 {"pglue_b", {{1, 2, pglue_b_int_bb_b0_regs,
1214 pglue_b_prty_bb_b0_regs} } },
1215 {"cnig", {{1, 1, cnig_int_bb_b0_regs, cnig_prty_bb_b0_regs} } },
1216 {"cpmu", {{1, 0, cpmu_int_bb_b0_regs, NULL} } },
1217 {"ncsi", {{1, 1, ncsi_int_bb_b0_regs, ncsi_prty_bb_b0_regs} } },
1218 {"opte", {{0, 2, NULL, opte_prty_bb_b0_regs} } },
1219 {"bmb", {{12, 3, bmb_int_bb_b0_regs, bmb_prty_bb_b0_regs} } },
1220 {"pcie", {{0, 1, NULL, pcie_prty_bb_b0_regs} } },
1221 {"mcp", {{0, 0, NULL, NULL} } },
1222 {"mcp2", {{0, 2, NULL, mcp2_prty_bb_b0_regs} } },
1223 {"pswhst", {{1, 2, pswhst_int_bb_b0_regs, pswhst_prty_bb_b0_regs} } },
1224 {"pswhst2", {{1, 1, pswhst2_int_bb_b0_regs,
1225 pswhst2_prty_bb_b0_regs} } },
1226 {"pswrd", {{1, 1, pswrd_int_bb_b0_regs, pswrd_prty_bb_b0_regs} } },
1227 {"pswrd2", {{1, 3, pswrd2_int_bb_b0_regs, pswrd2_prty_bb_b0_regs} } },
1228 {"pswwr", {{1, 1, pswwr_int_bb_b0_regs, pswwr_prty_bb_b0_regs} } },
1229 {"pswwr2", {{1, 5, pswwr2_int_bb_b0_regs, pswwr2_prty_bb_b0_regs} } },
1230 {"pswrq", {{1, 1, pswrq_int_bb_b0_regs, pswrq_prty_bb_b0_regs} } },
1231 {"pswrq2", {{1, 1, pswrq2_int_bb_b0_regs, pswrq2_prty_bb_b0_regs} } },
1232 {"pglcs", {{1, 0, pglcs_int_bb_b0_regs, NULL} } },
1233 {"dmae", {{1, 1, dmae_int_bb_b0_regs, dmae_prty_bb_b0_regs} } },
1234 {"ptu", {{1, 1, ptu_int_bb_b0_regs, ptu_prty_bb_b0_regs} } },
1235 {"tcm", {{3, 2, tcm_int_bb_b0_regs, tcm_prty_bb_b0_regs} } },
1236 {"mcm", {{3, 2, mcm_int_bb_b0_regs, mcm_prty_bb_b0_regs} } },
1237 {"ucm", {{3, 2, ucm_int_bb_b0_regs, ucm_prty_bb_b0_regs} } },
1238 {"xcm", {{3, 2, xcm_int_bb_b0_regs, xcm_prty_bb_b0_regs} } },
1239 {"ycm", {{3, 2, ycm_int_bb_b0_regs, ycm_prty_bb_b0_regs} } },
1240 {"pcm", {{3, 1, pcm_int_bb_b0_regs, pcm_prty_bb_b0_regs} } },
1241 {"qm", {{1, 4, qm_int_bb_b0_regs, qm_prty_bb_b0_regs} } },
1242 {"tm", {{2, 1, tm_int_bb_b0_regs, tm_prty_bb_b0_regs} } },
1243 {"dorq", {{1, 2, dorq_int_bb_b0_regs, dorq_prty_bb_b0_regs} } },
1244 {"brb", {{12, 3, brb_int_bb_b0_regs, brb_prty_bb_b0_regs} } },
1245 {"src", {{1, 0, src_int_bb_b0_regs, NULL} } },
1246 {"prs", {{1, 3, prs_int_bb_b0_regs, prs_prty_bb_b0_regs} } },
1247 {"tsdm", {{1, 1, tsdm_int_bb_b0_regs, tsdm_prty_bb_b0_regs} } },
1248 {"msdm", {{1, 1, msdm_int_bb_b0_regs, msdm_prty_bb_b0_regs} } },
1249 {"usdm", {{1, 1, usdm_int_bb_b0_regs, usdm_prty_bb_b0_regs} } },
1250 {"xsdm", {{1, 1, xsdm_int_bb_b0_regs, xsdm_prty_bb_b0_regs} } },
1251 {"ysdm", {{1, 1, ysdm_int_bb_b0_regs, ysdm_prty_bb_b0_regs} } },
1252 {"psdm", {{1, 1, psdm_int_bb_b0_regs, psdm_prty_bb_b0_regs} } },
1253 {"tsem", {{3, 3, tsem_int_bb_b0_regs, tsem_prty_bb_b0_regs} } },
1254 {"msem", {{3, 2, msem_int_bb_b0_regs, msem_prty_bb_b0_regs} } },
1255 {"usem", {{3, 2, usem_int_bb_b0_regs, usem_prty_bb_b0_regs} } },
1256 {"xsem", {{3, 2, xsem_int_bb_b0_regs, xsem_prty_bb_b0_regs} } },
1257 {"ysem", {{3, 2, ysem_int_bb_b0_regs, ysem_prty_bb_b0_regs} } },
1258 {"psem", {{3, 3, psem_int_bb_b0_regs, psem_prty_bb_b0_regs} } },
1259 {"rss", {{1, 1, rss_int_bb_b0_regs, rss_prty_bb_b0_regs} } },
1260 {"tmld", {{1, 1, tmld_int_bb_b0_regs, tmld_prty_bb_b0_regs} } },
1261 {"muld", {{1, 1, muld_int_bb_b0_regs, muld_prty_bb_b0_regs} } },
1262 {"yuld", {{1, 1, yuld_int_bb_b0_regs, yuld_prty_bb_b0_regs} } },
1263 {"xyld", {{1, 1, xyld_int_bb_b0_regs, xyld_prty_bb_b0_regs} } },
1264 {"prm", {{1, 2, prm_int_bb_b0_regs, prm_prty_bb_b0_regs} } },
1265 {"pbf_pb1", {{1, 1, pbf_pb1_int_bb_b0_regs,
1266 pbf_pb1_prty_bb_b0_regs} } },
1267 {"pbf_pb2", {{1, 1, pbf_pb2_int_bb_b0_regs,
1268 pbf_pb2_prty_bb_b0_regs} } },
1269 {"rpb", { {1, 1, rpb_int_bb_b0_regs, rpb_prty_bb_b0_regs} } },
1270 {"btb", { {11, 2, btb_int_bb_b0_regs, btb_prty_bb_b0_regs} } },
1271 {"pbf", { {1, 3, pbf_int_bb_b0_regs, pbf_prty_bb_b0_regs} } },
1272 {"rdif", { {1, 1, rdif_int_bb_b0_regs, rdif_prty_bb_b0_regs} } },
1273 {"tdif", { {1, 2, tdif_int_bb_b0_regs, tdif_prty_bb_b0_regs} } },
1274 {"cdu", { {1, 1, cdu_int_bb_b0_regs, cdu_prty_bb_b0_regs} } },
1275 {"ccfc", { {1, 2, ccfc_int_bb_b0_regs, ccfc_prty_bb_b0_regs} } },
1276 {"tcfc", { {1, 2, tcfc_int_bb_b0_regs, tcfc_prty_bb_b0_regs} } },
1277 {"igu", { {1, 3, igu_int_bb_b0_regs, igu_prty_bb_b0_regs} } },
1278 {"cau", { {1, 1, cau_int_bb_b0_regs, cau_prty_bb_b0_regs} } },
1279 {"umac", { {0, 0, NULL, NULL} } },
1280 {"xmac", { {0, 0, NULL, NULL} } },
1281 {"dbg", { {1, 1, dbg_int_bb_b0_regs, dbg_prty_bb_b0_regs} } },
1282 {"nig", { {6, 5, nig_int_bb_b0_regs, nig_prty_bb_b0_regs} } },
1283 {"wol", { {0, 0, NULL, NULL} } },
1284 {"bmbn", { {0, 0, NULL, NULL} } },
1285 {"ipc", { {1, 1, ipc_int_bb_b0_regs, ipc_prty_bb_b0_regs} } },
1286 {"nwm", { {0, 0, NULL, NULL} } },
1287 {"nws", { {0, 0, NULL, NULL} } },
1288 {"ms", { {0, 0, NULL, NULL} } },
1289 {"phy_pcie", { {0, 0, NULL, NULL} } },
1290 {"misc_aeu", { {0, 0, NULL, NULL} } },
1291 {"bar0_map", { {0, 0, NULL, NULL} } },};
1292
1293/* Specific HW attention callbacks */
1294static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn)
1295{
1296 u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE);
1297
1298 /* This might occur on certain instances; Log it once then mask it */
1299 DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n",
1300 tmp);
1301 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK,
1302 0xffffffff);
1303
1304 return 0;
1305}
1306
1307#define QED_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1)
1308#define ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1)
1309#define ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0)
1310#define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0xf)
1311#define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1)
1312#define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x1)
1313#define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5)
1314#define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0xff)
1315#define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6)
1316#define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0xf)
1317#define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14)
1318#define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0xff)
1319#define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18)
1320static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn)
1321{
1322 u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1323 PSWHST_REG_INCORRECT_ACCESS_VALID);
1324
1325 if (tmp & QED_PSWHST_ATTENTION_INCORRECT_ACCESS) {
1326 u32 addr, data, length;
1327
1328 addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1329 PSWHST_REG_INCORRECT_ACCESS_ADDRESS);
1330 data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1331 PSWHST_REG_INCORRECT_ACCESS_DATA);
1332 length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1333 PSWHST_REG_INCORRECT_ACCESS_LENGTH);
1334
1335 DP_INFO(p_hwfn->cdev,
1336 "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n",
1337 addr, length,
1338 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_PF_ID),
1339 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_VF_ID),
1340 (u8) GET_FIELD(data,
1341 ATTENTION_INCORRECT_ACCESS_VF_VALID),
1342 (u8) GET_FIELD(data,
1343 ATTENTION_INCORRECT_ACCESS_CLIENT),
1344 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_WR),
1345 (u8) GET_FIELD(data,
1346 ATTENTION_INCORRECT_ACCESS_BYTE_EN),
1347 data);
1348 }
1349
1350 return 0;
1351}
1352
1353#define QED_GRC_ATTENTION_VALID_BIT (1 << 0)
1354#define QED_GRC_ATTENTION_ADDRESS_MASK (0x7fffff)
1355#define QED_GRC_ATTENTION_ADDRESS_SHIFT (0)
1356#define QED_GRC_ATTENTION_RDWR_BIT (1 << 23)
1357#define QED_GRC_ATTENTION_MASTER_MASK (0xf)
1358#define QED_GRC_ATTENTION_MASTER_SHIFT (24)
1359#define QED_GRC_ATTENTION_PF_MASK (0xf)
1360#define QED_GRC_ATTENTION_PF_SHIFT (0)
1361#define QED_GRC_ATTENTION_VF_MASK (0xff)
1362#define QED_GRC_ATTENTION_VF_SHIFT (4)
1363#define QED_GRC_ATTENTION_PRIV_MASK (0x3)
1364#define QED_GRC_ATTENTION_PRIV_SHIFT (14)
1365#define QED_GRC_ATTENTION_PRIV_VF (0)
1366static const char *attn_master_to_str(u8 master)
1367{
1368 switch (master) {
1369 case 1: return "PXP";
1370 case 2: return "MCP";
1371 case 3: return "MSDM";
1372 case 4: return "PSDM";
1373 case 5: return "YSDM";
1374 case 6: return "USDM";
1375 case 7: return "TSDM";
1376 case 8: return "XSDM";
1377 case 9: return "DBU";
1378 case 10: return "DMAE";
1379 default:
1380 return "Unknown";
1381 }
1382}
1383
1384static int qed_grc_attn_cb(struct qed_hwfn *p_hwfn)
1385{
1386 u32 tmp, tmp2;
1387
1388 /* We've already cleared the timeout interrupt register, so we learn
1389 * of interrupts via the validity register
1390 */
1391 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1392 GRC_REG_TIMEOUT_ATTN_ACCESS_VALID);
1393 if (!(tmp & QED_GRC_ATTENTION_VALID_BIT))
1394 goto out;
1395
1396 /* Read the GRC timeout information */
1397 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1398 GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0);
1399 tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1400 GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1);
1401
1402 DP_INFO(p_hwfn->cdev,
1403 "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n",
1404 tmp2, tmp,
1405 (tmp & QED_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from",
1406 GET_FIELD(tmp, QED_GRC_ATTENTION_ADDRESS) << 2,
1407 attn_master_to_str(GET_FIELD(tmp, QED_GRC_ATTENTION_MASTER)),
1408 GET_FIELD(tmp2, QED_GRC_ATTENTION_PF),
1409 (GET_FIELD(tmp2, QED_GRC_ATTENTION_PRIV) ==
1410 QED_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Ireelevant)",
1411 GET_FIELD(tmp2, QED_GRC_ATTENTION_VF));
1412
1413out:
1414 /* Regardles of anything else, clean the validity bit */
1415 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,
1416 GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0);
1417 return 0;
1418}
1419
1420#define PGLUE_ATTENTION_VALID (1 << 29)
1421#define PGLUE_ATTENTION_RD_VALID (1 << 26)
1422#define PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf)
1423#define PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20)
1424#define PGLUE_ATTENTION_DETAILS_VF_VALID_MASK (0x1)
1425#define PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT (19)
1426#define PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff)
1427#define PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24)
1428#define PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK (0x1)
1429#define PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT (21)
1430#define PGLUE_ATTENTION_DETAILS2_BME_MASK (0x1)
1431#define PGLUE_ATTENTION_DETAILS2_BME_SHIFT (22)
1432#define PGLUE_ATTENTION_DETAILS2_FID_EN_MASK (0x1)
1433#define PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT (23)
1434#define PGLUE_ATTENTION_ICPL_VALID (1 << 23)
1435#define PGLUE_ATTENTION_ZLR_VALID (1 << 25)
1436#define PGLUE_ATTENTION_ILT_VALID (1 << 23)
1437static int qed_pglub_rbc_attn_cb(struct qed_hwfn *p_hwfn)
1438{
1439 u32 tmp;
1440
1441 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1442 PGLUE_B_REG_TX_ERR_WR_DETAILS2);
1443 if (tmp & PGLUE_ATTENTION_VALID) {
1444 u32 addr_lo, addr_hi, details;
1445
1446 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1447 PGLUE_B_REG_TX_ERR_WR_ADD_31_0);
1448 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1449 PGLUE_B_REG_TX_ERR_WR_ADD_63_32);
1450 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1451 PGLUE_B_REG_TX_ERR_WR_DETAILS);
1452
1453 DP_INFO(p_hwfn,
1454 "Illegal write by chip to [%08x:%08x] blocked.\n"
1455 "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n"
1456 "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
1457 addr_hi, addr_lo, details,
1458 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID),
1459 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID),
1460 GET_FIELD(details,
1461 PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0,
1462 tmp,
1463 GET_FIELD(tmp,
1464 PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0,
1465 GET_FIELD(tmp,
1466 PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0,
1467 GET_FIELD(tmp,
1468 PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0);
1469 }
1470
1471 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1472 PGLUE_B_REG_TX_ERR_RD_DETAILS2);
1473 if (tmp & PGLUE_ATTENTION_RD_VALID) {
1474 u32 addr_lo, addr_hi, details;
1475
1476 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1477 PGLUE_B_REG_TX_ERR_RD_ADD_31_0);
1478 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1479 PGLUE_B_REG_TX_ERR_RD_ADD_63_32);
1480 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1481 PGLUE_B_REG_TX_ERR_RD_DETAILS);
1482
1483 DP_INFO(p_hwfn,
1484 "Illegal read by chip from [%08x:%08x] blocked.\n"
1485 " Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n"
1486 " Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
1487 addr_hi, addr_lo, details,
1488 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID),
1489 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID),
1490 GET_FIELD(details,
1491 PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0,
1492 tmp,
1493 GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1
1494 : 0,
1495 GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0,
1496 GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1
1497 : 0);
1498 }
1499
1500 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1501 PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL);
1502 if (tmp & PGLUE_ATTENTION_ICPL_VALID)
1503 DP_INFO(p_hwfn, "ICPL eror - %08x\n", tmp);
1504
1505 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1506 PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS);
1507 if (tmp & PGLUE_ATTENTION_ZLR_VALID) {
1508 u32 addr_hi, addr_lo;
1509
1510 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1511 PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0);
1512 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1513 PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32);
1514
1515 DP_INFO(p_hwfn, "ZLR eror - %08x [Address %08x:%08x]\n",
1516 tmp, addr_hi, addr_lo);
1517 }
1518
1519 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1520 PGLUE_B_REG_VF_ILT_ERR_DETAILS2);
1521 if (tmp & PGLUE_ATTENTION_ILT_VALID) {
1522 u32 addr_hi, addr_lo, details;
1523
1524 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1525 PGLUE_B_REG_VF_ILT_ERR_ADD_31_0);
1526 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1527 PGLUE_B_REG_VF_ILT_ERR_ADD_63_32);
1528 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1529 PGLUE_B_REG_VF_ILT_ERR_DETAILS);
1530
1531 DP_INFO(p_hwfn,
1532 "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n",
1533 details, tmp, addr_hi, addr_lo);
1534 }
1535
1536 /* Clear the indications */
1537 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,
1538 PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2));
1539
1540 return 0;
1541}
1542
1543#define QED_DORQ_ATTENTION_REASON_MASK (0xfffff)
1544#define QED_DORQ_ATTENTION_OPAQUE_MASK (0xffff)
1545#define QED_DORQ_ATTENTION_SIZE_MASK (0x7f)
1546#define QED_DORQ_ATTENTION_SIZE_SHIFT (16)
1547static int qed_dorq_attn_cb(struct qed_hwfn *p_hwfn)
1548{
1549 u32 reason;
1550
1551 reason = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, DORQ_REG_DB_DROP_REASON) &
1552 QED_DORQ_ATTENTION_REASON_MASK;
1553 if (reason) {
1554 u32 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1555 DORQ_REG_DB_DROP_DETAILS);
1556
1557 DP_INFO(p_hwfn->cdev,
1558 "DORQ db_drop: address 0x%08x Opaque FID 0x%04x Size [bytes] 0x%08x Reason: 0x%08x\n",
1559 qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1560 DORQ_REG_DB_DROP_DETAILS_ADDRESS),
1561 (u16)(details & QED_DORQ_ATTENTION_OPAQUE_MASK),
1562 GET_FIELD(details, QED_DORQ_ATTENTION_SIZE) * 4,
1563 reason);
1564 }
1565
1566 return -EINVAL;
1567}
1568
1569/* Notice aeu_invert_reg must be defined in the same order of bits as HW; */
1570static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = {
1571 {
1572 { /* After Invert 1 */
1573 {"GPIO0 function%d",
1574 (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID},
1575 }
1576 },
1577
1578 {
1579 { /* After Invert 2 */
1580 {"PGLUE config_space", ATTENTION_SINGLE,
1581 NULL, MAX_BLOCK_ID},
1582 {"PGLUE misc_flr", ATTENTION_SINGLE,
1583 NULL, MAX_BLOCK_ID},
1584 {"PGLUE B RBC", ATTENTION_PAR_INT,
1585 qed_pglub_rbc_attn_cb, BLOCK_PGLUE_B},
1586 {"PGLUE misc_mctp", ATTENTION_SINGLE,
1587 NULL, MAX_BLOCK_ID},
1588 {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
1589 {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
1590 {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
1591 {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) |
1592 (1 << ATTENTION_OFFSET_SHIFT),
1593 NULL, MAX_BLOCK_ID},
1594 {"PCIE glue/PXP VPD %d",
1595 (16 << ATTENTION_LENGTH_SHIFT), NULL, BLOCK_PGLCS},
1596 }
1597 },
1598
1599 {
1600 { /* After Invert 3 */
1601 {"General Attention %d",
1602 (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID},
1603 }
1604 },
1605
1606 {
1607 { /* After Invert 4 */
1608 {"General Attention 32", ATTENTION_SINGLE,
1609 NULL, MAX_BLOCK_ID},
1610 {"General Attention %d",
1611 (2 << ATTENTION_LENGTH_SHIFT) |
1612 (33 << ATTENTION_OFFSET_SHIFT), NULL, MAX_BLOCK_ID},
1613 {"General Attention 35", ATTENTION_SINGLE,
1614 NULL, MAX_BLOCK_ID},
1615 {"CNIG port %d", (4 << ATTENTION_LENGTH_SHIFT),
1616 NULL, BLOCK_CNIG},
1617 {"MCP CPU", ATTENTION_SINGLE,
1618 qed_mcp_attn_cb, MAX_BLOCK_ID},
1619 {"MCP Watchdog timer", ATTENTION_SINGLE,
1620 NULL, MAX_BLOCK_ID},
1621 {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
1622 {"AVS stop status ready", ATTENTION_SINGLE,
1623 NULL, MAX_BLOCK_ID},
1624 {"MSTAT", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID},
1625 {"MSTAT per-path", ATTENTION_PAR_INT,
1626 NULL, MAX_BLOCK_ID},
1627 {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT),
1628 NULL, MAX_BLOCK_ID},
1629 {"NIG", ATTENTION_PAR_INT, NULL, BLOCK_NIG},
1630 {"BMB/OPTE/MCP", ATTENTION_PAR_INT, NULL, BLOCK_BMB},
1631 {"BTB", ATTENTION_PAR_INT, NULL, BLOCK_BTB},
1632 {"BRB", ATTENTION_PAR_INT, NULL, BLOCK_BRB},
1633 {"PRS", ATTENTION_PAR_INT, NULL, BLOCK_PRS},
1634 }
1635 },
1636
1637 {
1638 { /* After Invert 5 */
1639 {"SRC", ATTENTION_PAR_INT, NULL, BLOCK_SRC},
1640 {"PB Client1", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB1},
1641 {"PB Client2", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB2},
1642 {"RPB", ATTENTION_PAR_INT, NULL, BLOCK_RPB},
1643 {"PBF", ATTENTION_PAR_INT, NULL, BLOCK_PBF},
1644 {"QM", ATTENTION_PAR_INT, NULL, BLOCK_QM},
1645 {"TM", ATTENTION_PAR_INT, NULL, BLOCK_TM},
1646 {"MCM", ATTENTION_PAR_INT, NULL, BLOCK_MCM},
1647 {"MSDM", ATTENTION_PAR_INT, NULL, BLOCK_MSDM},
1648 {"MSEM", ATTENTION_PAR_INT, NULL, BLOCK_MSEM},
1649 {"PCM", ATTENTION_PAR_INT, NULL, BLOCK_PCM},
1650 {"PSDM", ATTENTION_PAR_INT, NULL, BLOCK_PSDM},
1651 {"PSEM", ATTENTION_PAR_INT, NULL, BLOCK_PSEM},
1652 {"TCM", ATTENTION_PAR_INT, NULL, BLOCK_TCM},
1653 {"TSDM", ATTENTION_PAR_INT, NULL, BLOCK_TSDM},
1654 {"TSEM", ATTENTION_PAR_INT, NULL, BLOCK_TSEM},
1655 }
1656 },
1657
1658 {
1659 { /* After Invert 6 */
1660 {"UCM", ATTENTION_PAR_INT, NULL, BLOCK_UCM},
1661 {"USDM", ATTENTION_PAR_INT, NULL, BLOCK_USDM},
1662 {"USEM", ATTENTION_PAR_INT, NULL, BLOCK_USEM},
1663 {"XCM", ATTENTION_PAR_INT, NULL, BLOCK_XCM},
1664 {"XSDM", ATTENTION_PAR_INT, NULL, BLOCK_XSDM},
1665 {"XSEM", ATTENTION_PAR_INT, NULL, BLOCK_XSEM},
1666 {"YCM", ATTENTION_PAR_INT, NULL, BLOCK_YCM},
1667 {"YSDM", ATTENTION_PAR_INT, NULL, BLOCK_YSDM},
1668 {"YSEM", ATTENTION_PAR_INT, NULL, BLOCK_YSEM},
1669 {"XYLD", ATTENTION_PAR_INT, NULL, BLOCK_XYLD},
1670 {"TMLD", ATTENTION_PAR_INT, NULL, BLOCK_TMLD},
1671 {"MYLD", ATTENTION_PAR_INT, NULL, BLOCK_MULD},
1672 {"YULD", ATTENTION_PAR_INT, NULL, BLOCK_YULD},
1673 {"DORQ", ATTENTION_PAR_INT,
1674 qed_dorq_attn_cb, BLOCK_DORQ},
1675 {"DBG", ATTENTION_PAR_INT, NULL, BLOCK_DBG},
1676 {"IPC", ATTENTION_PAR_INT, NULL, BLOCK_IPC},
1677 }
1678 },
1679
1680 {
1681 { /* After Invert 7 */
1682 {"CCFC", ATTENTION_PAR_INT, NULL, BLOCK_CCFC},
1683 {"CDU", ATTENTION_PAR_INT, NULL, BLOCK_CDU},
1684 {"DMAE", ATTENTION_PAR_INT, NULL, BLOCK_DMAE},
1685 {"IGU", ATTENTION_PAR_INT, NULL, BLOCK_IGU},
1686 {"ATC", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID},
1687 {"CAU", ATTENTION_PAR_INT, NULL, BLOCK_CAU},
1688 {"PTU", ATTENTION_PAR_INT, NULL, BLOCK_PTU},
1689 {"PRM", ATTENTION_PAR_INT, NULL, BLOCK_PRM},
1690 {"TCFC", ATTENTION_PAR_INT, NULL, BLOCK_TCFC},
1691 {"RDIF", ATTENTION_PAR_INT, NULL, BLOCK_RDIF},
1692 {"TDIF", ATTENTION_PAR_INT, NULL, BLOCK_TDIF},
1693 {"RSS", ATTENTION_PAR_INT, NULL, BLOCK_RSS},
1694 {"MISC", ATTENTION_PAR_INT, NULL, BLOCK_MISC},
1695 {"MISCS", ATTENTION_PAR_INT, NULL, BLOCK_MISCS},
1696 {"PCIE", ATTENTION_PAR, NULL, BLOCK_PCIE},
1697 {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS},
1698 {"PSWRQ", ATTENTION_PAR_INT, NULL, BLOCK_PSWRQ},
1699 }
1700 },
1701
1702 {
1703 { /* After Invert 8 */
1704 {"PSWRQ (pci_clk)", ATTENTION_PAR_INT,
1705 NULL, BLOCK_PSWRQ2},
1706 {"PSWWR", ATTENTION_PAR_INT, NULL, BLOCK_PSWWR},
1707 {"PSWWR (pci_clk)", ATTENTION_PAR_INT,
1708 NULL, BLOCK_PSWWR2},
1709 {"PSWRD", ATTENTION_PAR_INT, NULL, BLOCK_PSWRD},
1710 {"PSWRD (pci_clk)", ATTENTION_PAR_INT,
1711 NULL, BLOCK_PSWRD2},
1712 {"PSWHST", ATTENTION_PAR_INT,
1713 qed_pswhst_attn_cb, BLOCK_PSWHST},
1714 {"PSWHST (pci_clk)", ATTENTION_PAR_INT,
1715 NULL, BLOCK_PSWHST2},
1716 {"GRC", ATTENTION_PAR_INT,
1717 qed_grc_attn_cb, BLOCK_GRC},
1718 {"CPMU", ATTENTION_PAR_INT, NULL, BLOCK_CPMU},
1719 {"NCSI", ATTENTION_PAR_INT, NULL, BLOCK_NCSI},
1720 {"MSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
1721 {"PSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
1722 {"TSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
1723 {"USEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
1724 {"XSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
1725 {"YSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
1726 {"pxp_misc_mps", ATTENTION_PAR, NULL, BLOCK_PGLCS},
1727 {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE,
1728 NULL, BLOCK_PGLCS},
1729 {"PERST_B assertion", ATTENTION_SINGLE,
1730 NULL, MAX_BLOCK_ID},
1731 {"PERST_B deassertion", ATTENTION_SINGLE,
1732 NULL, MAX_BLOCK_ID},
1733 {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT),
1734 NULL, MAX_BLOCK_ID},
1735 }
1736 },
1737
1738 {
1739 { /* After Invert 9 */
1740 {"MCP Latched memory", ATTENTION_PAR,
1741 NULL, MAX_BLOCK_ID},
1742 {"MCP Latched scratchpad cache", ATTENTION_SINGLE,
1743 NULL, MAX_BLOCK_ID},
1744 {"MCP Latched ump_tx", ATTENTION_PAR,
1745 NULL, MAX_BLOCK_ID},
1746 {"MCP Latched scratchpad", ATTENTION_PAR,
1747 NULL, MAX_BLOCK_ID},
1748 {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT),
1749 NULL, MAX_BLOCK_ID},
1750 }
1751 },
1752};
1753
1754#define ATTN_STATE_BITS (0xfff)
1755#define ATTN_BITS_MASKABLE (0x3ff)
1756struct qed_sb_attn_info {
1757 /* Virtual & Physical address of the SB */
1758 struct atten_status_block *sb_attn;
1759 dma_addr_t sb_phys;
1760
1761 /* Last seen running index */
1762 u16 index;
1763
1764 /* A mask of the AEU bits resulting in a parity error */
1765 u32 parity_mask[NUM_ATTN_REGS];
1766
1767 /* A pointer to the attention description structure */
1768 struct aeu_invert_reg *p_aeu_desc;
1769
1770 /* Previously asserted attentions, which are still unasserted */
1771 u16 known_attn;
1772
1773 /* Cleanup address for the link's general hw attention */
1774 u32 mfw_attn_addr;
1775};
1776
1777static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn,
1778 struct qed_sb_attn_info *p_sb_desc)
1779{
1780 u16 rc = 0, index;
1781
1782 /* Make certain HW write took affect */
1783 mmiowb();
1784
1785 index = le16_to_cpu(p_sb_desc->sb_attn->sb_index);
1786 if (p_sb_desc->index != index) {
1787 p_sb_desc->index = index;
1788 rc = QED_SB_ATT_IDX;
1789 }
1790
1791 /* Make certain we got a consistent view with HW */
1792 mmiowb();
1793
1794 return rc;
1795}
1796
1797/**
1798 * @brief qed_int_assertion - handles asserted attention bits
1799 *
1800 * @param p_hwfn
1801 * @param asserted_bits newly asserted bits
1802 * @return int
1803 */
1804static int qed_int_assertion(struct qed_hwfn *p_hwfn, u16 asserted_bits)
1805{
1806 struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
1807 u32 igu_mask;
1808
1809 /* Mask the source of the attention in the IGU */
1810 igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE);
1811 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n",
1812 igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE));
1813 igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE);
1814 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);
1815
1816 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1817 "inner known ATTN state: 0x%04x --> 0x%04x\n",
1818 sb_attn_sw->known_attn,
1819 sb_attn_sw->known_attn | asserted_bits);
1820 sb_attn_sw->known_attn |= asserted_bits;
1821
1822 /* Handle MCP events */
1823 if (asserted_bits & 0x100) {
1824 qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt);
1825 /* Clean the MCP attention */
1826 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,
1827 sb_attn_sw->mfw_attn_addr, 0);
1828 }
1829
1830 DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview +
1831 GTT_BAR0_MAP_REG_IGU_CMD +
1832 ((IGU_CMD_ATTN_BIT_SET_UPPER -
1833 IGU_CMD_INT_ACK_BASE) << 3),
1834 (u32)asserted_bits);
1835
1836 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n",
1837 asserted_bits);
1838
1839 return 0;
1840}
1841
1842static void qed_int_deassertion_print_bit(struct qed_hwfn *p_hwfn,
1843 struct attn_hw_reg *p_reg_desc,
1844 struct attn_hw_block *p_block,
1845 enum qed_attention_type type,
1846 u32 val, u32 mask)
1847{
1848 int j;
1849
1850 for (j = 0; j < p_reg_desc->num_of_bits; j++) {
1851 if (!(val & (1 << j)))
1852 continue;
1853
1854 DP_NOTICE(p_hwfn,
1855 "%s (%s): reg %d [0x%08x], bit %d [%s]\n",
1856 p_block->name,
1857 type == QED_ATTN_TYPE_ATTN ? "Interrupt" :
1858 "Parity",
1859 p_reg_desc->reg_idx, p_reg_desc->sts_addr,
1860 j, (mask & (1 << j)) ? " [MASKED]" : "");
1861 }
1862}
1863
1864/**
1865 * @brief qed_int_deassertion_aeu_bit - handles the effects of a single
1866 * cause of the attention
1867 *
1868 * @param p_hwfn
1869 * @param p_aeu - descriptor of an AEU bit which caused the attention
1870 * @param aeu_en_reg - register offset of the AEU enable reg. which configured
1871 * this bit to this group.
1872 * @param bit_index - index of this bit in the aeu_en_reg
1873 *
1874 * @return int
1875 */
1876static int
1877qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn,
1878 struct aeu_invert_reg_bit *p_aeu,
1879 u32 aeu_en_reg,
1880 u32 bitmask)
1881{
1882 int rc = -EINVAL;
1883 u32 val;
1884
1885 DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n",
1886 p_aeu->bit_name, bitmask);
1887
1888 /* Call callback before clearing the interrupt status */
1889 if (p_aeu->cb) {
1890 DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n",
1891 p_aeu->bit_name);
1892 rc = p_aeu->cb(p_hwfn);
1893 }
1894
1895 /* Handle HW block interrupt registers */
1896 if (p_aeu->block_index != MAX_BLOCK_ID) {
1897 struct attn_hw_block *p_block;
1898 u32 mask;
1899 int i;
1900
1901 p_block = &attn_blocks[p_aeu->block_index];
1902
1903 /* Handle each interrupt register */
1904 for (i = 0; i < p_block->chip_regs[0].num_of_int_regs; i++) {
1905 struct attn_hw_reg *p_reg_desc;
1906 u32 sts_addr;
1907
1908 p_reg_desc = p_block->chip_regs[0].int_regs[i];
1909
1910 /* In case of fatal attention, don't clear the status
1911 * so it would appear in following idle check.
1912 */
1913 if (rc == 0)
1914 sts_addr = p_reg_desc->sts_clr_addr;
1915 else
1916 sts_addr = p_reg_desc->sts_addr;
1917
1918 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, sts_addr);
1919 mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1920 p_reg_desc->mask_addr);
1921 qed_int_deassertion_print_bit(p_hwfn, p_reg_desc,
1922 p_block,
1923 QED_ATTN_TYPE_ATTN,
1924 val, mask);
1925 }
1926 }
1927
1928 /* If the attention is benign, no need to prevent it */
1929 if (!rc)
1930 goto out;
1931
1932 /* Prevent this Attention from being asserted in the future */
1933 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
1934 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask));
1935 DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n",
1936 p_aeu->bit_name);
1937
1938out:
1939 return rc;
1940}
1941
1942static void qed_int_parity_print(struct qed_hwfn *p_hwfn,
1943 struct aeu_invert_reg_bit *p_aeu,
1944 struct attn_hw_block *p_block,
1945 u8 bit_index)
1946{
1947 int i;
1948
1949 for (i = 0; i < p_block->chip_regs[0].num_of_prty_regs; i++) {
1950 struct attn_hw_reg *p_reg_desc;
1951 u32 val, mask;
1952
1953 p_reg_desc = p_block->chip_regs[0].prty_regs[i];
1954
1955 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1956 p_reg_desc->sts_clr_addr);
1957 mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1958 p_reg_desc->mask_addr);
1959 qed_int_deassertion_print_bit(p_hwfn, p_reg_desc,
1960 p_block,
1961 QED_ATTN_TYPE_PARITY,
1962 val, mask);
1963 }
1964}
1965
1966/**
1967 * @brief qed_int_deassertion_parity - handle a single parity AEU source
1968 *
1969 * @param p_hwfn
1970 * @param p_aeu - descriptor of an AEU bit which caused the parity
1971 * @param bit_index
1972 */
1973static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn,
1974 struct aeu_invert_reg_bit *p_aeu,
1975 u8 bit_index)
1976{
1977 u32 block_id = p_aeu->block_index;
1978
1979 DP_INFO(p_hwfn->cdev, "%s[%d] parity attention is set\n",
1980 p_aeu->bit_name, bit_index);
1981
1982 if (block_id != MAX_BLOCK_ID) {
1983 qed_int_parity_print(p_hwfn, p_aeu, &attn_blocks[block_id],
1984 bit_index);
1985
1986 /* In BB, there's a single parity bit for several blocks */
1987 if (block_id == BLOCK_BTB) {
1988 qed_int_parity_print(p_hwfn, p_aeu,
1989 &attn_blocks[BLOCK_OPTE],
1990 bit_index);
1991 qed_int_parity_print(p_hwfn, p_aeu,
1992 &attn_blocks[BLOCK_MCP],
1993 bit_index);
1994 }
1995 }
1996}
1997
1998/**
1999 * @brief - handles deassertion of previously asserted attentions.
2000 *
2001 * @param p_hwfn
2002 * @param deasserted_bits - newly deasserted bits
2003 * @return int
2004 *
2005 */
2006static int qed_int_deassertion(struct qed_hwfn *p_hwfn,
2007 u16 deasserted_bits)
2008{
2009 struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
2010 u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask;
2011 u8 i, j, k, bit_idx;
2012 int rc = 0;
2013
2014 /* Read the attention registers in the AEU */
2015 for (i = 0; i < NUM_ATTN_REGS; i++) {
2016 aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
2017 MISC_REG_AEU_AFTER_INVERT_1_IGU +
2018 i * 0x4);
2019 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
2020 "Deasserted bits [%d]: %08x\n",
2021 i, aeu_inv_arr[i]);
2022 }
2023
2024 /* Find parity attentions first */
2025 for (i = 0; i < NUM_ATTN_REGS; i++) {
2026 struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i];
2027 u32 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
2028 MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
2029 i * sizeof(u32));
2030 u32 parities;
2031
2032 /* Skip register in which no parity bit is currently set */
2033 parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en;
2034 if (!parities)
2035 continue;
2036
2037 for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
2038 struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j];
2039
2040 if ((p_bit->flags & ATTENTION_PARITY) &&
2041 !!(parities & BIT(bit_idx)))
2042 qed_int_deassertion_parity(p_hwfn, p_bit,
2043 bit_idx);
2044
2045 bit_idx += ATTENTION_LENGTH(p_bit->flags);
2046 }
2047 }
2048
2049 /* Find non-parity cause for attention and act */
2050 for (k = 0; k < MAX_ATTN_GRPS; k++) {
2051 struct aeu_invert_reg_bit *p_aeu;
2052
2053 /* Handle only groups whose attention is currently deasserted */
2054 if (!(deasserted_bits & (1 << k)))
2055 continue;
2056
2057 for (i = 0; i < NUM_ATTN_REGS; i++) {
2058 u32 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
2059 i * sizeof(u32) +
2060 k * sizeof(u32) * NUM_ATTN_REGS;
2061 u32 en, bits;
2062
2063 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
2064 bits = aeu_inv_arr[i] & en;
2065
2066 /* Skip if no bit from this group is currently set */
2067 if (!bits)
2068 continue;
2069
2070 /* Find all set bits from current register which belong
2071 * to current group, making them responsible for the
2072 * previous assertion.
2073 */
2074 for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
2075 u8 bit, bit_len;
2076 u32 bitmask;
2077
2078 p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j];
2079
2080 /* No need to handle parity-only bits */
2081 if (p_aeu->flags == ATTENTION_PAR)
2082 continue;
2083
2084 bit = bit_idx;
2085 bit_len = ATTENTION_LENGTH(p_aeu->flags);
2086 if (p_aeu->flags & ATTENTION_PAR_INT) {
2087 /* Skip Parity */
2088 bit++;
2089 bit_len--;
2090 }
2091
2092 bitmask = bits & (((1 << bit_len) - 1) << bit);
2093 if (bitmask) {
2094 /* Handle source of the attention */
2095 qed_int_deassertion_aeu_bit(p_hwfn,
2096 p_aeu,
2097 aeu_en,
2098 bitmask);
2099 }
2100
2101 bit_idx += ATTENTION_LENGTH(p_aeu->flags);
2102 }
2103 }
2104 }
2105
2106 /* Clear IGU indication for the deasserted bits */
2107 DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview +
2108 GTT_BAR0_MAP_REG_IGU_CMD +
2109 ((IGU_CMD_ATTN_BIT_CLR_UPPER -
2110 IGU_CMD_INT_ACK_BASE) << 3),
2111 ~((u32)deasserted_bits));
2112
2113 /* Unmask deasserted attentions in IGU */
2114 aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE);
2115 aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE);
2116 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);
2117
2118 /* Clear deassertion from inner state */
2119 sb_attn_sw->known_attn &= ~deasserted_bits;
2120
2121 return rc;
2122}
2123
2124static int qed_int_attentions(struct qed_hwfn *p_hwfn)
2125{
2126 struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn;
2127 struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn;
2128 u32 attn_bits = 0, attn_acks = 0;
2129 u16 asserted_bits, deasserted_bits;
2130 __le16 index;
2131 int rc = 0;
2132
2133 /* Read current attention bits/acks - safeguard against attentions
2134 * by guaranting work on a synchronized timeframe
2135 */
2136 do {
2137 index = p_sb_attn->sb_index;
2138 attn_bits = le32_to_cpu(p_sb_attn->atten_bits);
2139 attn_acks = le32_to_cpu(p_sb_attn->atten_ack);
2140 } while (index != p_sb_attn->sb_index);
2141 p_sb_attn->sb_index = index;
2142
2143 /* Attention / Deassertion are meaningful (and in correct state)
2144 * only when they differ and consistent with known state - deassertion
2145 * when previous attention & current ack, and assertion when current
2146 * attention with no previous attention
2147 */
2148 asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) &
2149 ~p_sb_attn_sw->known_attn;
2150 deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) &
2151 p_sb_attn_sw->known_attn;
2152
2153 if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) {
2154 DP_INFO(p_hwfn,
2155 "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n",
2156 index, attn_bits, attn_acks, asserted_bits,
2157 deasserted_bits, p_sb_attn_sw->known_attn);
2158 } else if (asserted_bits == 0x100) {
2159 DP_INFO(p_hwfn, "MFW indication via attention\n");
2160 } else {
2161 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
2162 "MFW indication [deassertion]\n");
2163 }
2164
2165 if (asserted_bits) {
2166 rc = qed_int_assertion(p_hwfn, asserted_bits);
2167 if (rc)
2168 return rc;
2169 }
2170
2171 if (deasserted_bits)
2172 rc = qed_int_deassertion(p_hwfn, deasserted_bits);
2173
2174 return rc;
2175}
2176
2177static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn,
2178 void __iomem *igu_addr, u32 ack_cons)
2179{
2180 struct igu_prod_cons_update igu_ack = { 0 };
2181
2182 igu_ack.sb_id_and_flags =
2183 ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
2184 (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
2185 (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
2186 (IGU_SEG_ACCESS_ATTN <<
2187 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
2188
2189 DIRECT_REG_WR(igu_addr, igu_ack.sb_id_and_flags);
2190
2191 /* Both segments (interrupts & acks) are written to same place address;
2192 * Need to guarantee all commands will be received (in-order) by HW.
2193 */
2194 mmiowb();
2195 barrier();
2196}
2197
2198void qed_int_sp_dpc(unsigned long hwfn_cookie)
2199{
2200 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)hwfn_cookie;
2201 struct qed_pi_info *pi_info = NULL;
2202 struct qed_sb_attn_info *sb_attn;
2203 struct qed_sb_info *sb_info;
2204 int arr_size;
2205 u16 rc = 0;
2206
2207 if (!p_hwfn->p_sp_sb) {
2208 DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n");
2209 return;
2210 }
2211
2212 sb_info = &p_hwfn->p_sp_sb->sb_info;
2213 arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr);
2214 if (!sb_info) {
2215 DP_ERR(p_hwfn->cdev,
2216 "Status block is NULL - cannot ack interrupts\n");
2217 return;
2218 }
2219
2220 if (!p_hwfn->p_sb_attn) {
2221 DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn");
2222 return;
2223 }
2224 sb_attn = p_hwfn->p_sb_attn;
2225
2226 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n",
2227 p_hwfn, p_hwfn->my_id);
2228
2229 /* Disable ack for def status block. Required both for msix +
2230 * inta in non-mask mode, in inta does no harm.
2231 */
2232 qed_sb_ack(sb_info, IGU_INT_DISABLE, 0);
2233
2234 /* Gather Interrupts/Attentions information */
2235 if (!sb_info->sb_virt) {
2236 DP_ERR(p_hwfn->cdev,
2237 "Interrupt Status block is NULL - cannot check for new interrupts!\n");
2238 } else {
2239 u32 tmp_index = sb_info->sb_ack;
2240
2241 rc = qed_sb_update_sb_idx(sb_info);
2242 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR,
2243 "Interrupt indices: 0x%08x --> 0x%08x\n",
2244 tmp_index, sb_info->sb_ack);
2245 }
2246
2247 if (!sb_attn || !sb_attn->sb_attn) {
2248 DP_ERR(p_hwfn->cdev,
2249 "Attentions Status block is NULL - cannot check for new attentions!\n");
2250 } else {
2251 u16 tmp_index = sb_attn->index;
2252
2253 rc |= qed_attn_update_idx(p_hwfn, sb_attn);
2254 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR,
2255 "Attention indices: 0x%08x --> 0x%08x\n",
2256 tmp_index, sb_attn->index);
2257 }
2258
2259 /* Check if we expect interrupts at this time. if not just ack them */
2260 if (!(rc & QED_SB_EVENT_MASK)) {
2261 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
2262 return;
2263 }
2264
2265 /* Check the validity of the DPC ptt. If not ack interrupts and fail */
2266 if (!p_hwfn->p_dpc_ptt) {
2267 DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n");
2268 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
2269 return;
2270 }
2271
2272 if (rc & QED_SB_ATT_IDX)
2273 qed_int_attentions(p_hwfn);
2274
2275 if (rc & QED_SB_IDX) {
2276 int pi;
2277
2278 /* Look for a free index */
2279 for (pi = 0; pi < arr_size; pi++) {
2280 pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi];
2281 if (pi_info->comp_cb)
2282 pi_info->comp_cb(p_hwfn, pi_info->cookie);
2283 }
2284 }
2285
2286 if (sb_attn && (rc & QED_SB_ATT_IDX))
2287 /* This should be done before the interrupts are enabled,
2288 * since otherwise a new attention will be generated.
2289 */
2290 qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index);
2291
2292 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
2293}
2294
2295static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn)
2296{
2297 struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn;
2298
2299 if (!p_sb)
2300 return;
2301
2302 if (p_sb->sb_attn)
2303 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
2304 SB_ATTN_ALIGNED_SIZE(p_hwfn),
2305 p_sb->sb_attn, p_sb->sb_phys);
2306 kfree(p_sb);
2307}
2308
2309static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn,
2310 struct qed_ptt *p_ptt)
2311{
2312 struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
2313
2314 memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn));
2315
2316 sb_info->index = 0;
2317 sb_info->known_attn = 0;
2318
2319 /* Configure Attention Status Block in IGU */
2320 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,
2321 lower_32_bits(p_hwfn->p_sb_attn->sb_phys));
2322 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,
2323 upper_32_bits(p_hwfn->p_sb_attn->sb_phys));
2324}
2325
2326static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn,
2327 struct qed_ptt *p_ptt,
2328 void *sb_virt_addr, dma_addr_t sb_phy_addr)
2329{
2330 struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
2331 int i, j, k;
2332
2333 sb_info->sb_attn = sb_virt_addr;
2334 sb_info->sb_phys = sb_phy_addr;
2335
2336 /* Set the pointer to the AEU descriptors */
2337 sb_info->p_aeu_desc = aeu_descs;
2338
2339 /* Calculate Parity Masks */
2340 memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS);
2341 for (i = 0; i < NUM_ATTN_REGS; i++) {
2342 /* j is array index, k is bit index */
2343 for (j = 0, k = 0; k < 32; j++) {
2344 unsigned int flags = aeu_descs[i].bits[j].flags;
2345
2346 if (flags & ATTENTION_PARITY)
2347 sb_info->parity_mask[i] |= 1 << k;
2348
2349 k += ATTENTION_LENGTH(flags);
2350 }
2351 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
2352 "Attn Mask [Reg %d]: 0x%08x\n",
2353 i, sb_info->parity_mask[i]);
2354 }
2355
2356 /* Set the address of cleanup for the mcp attention */
2357 sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) +
2358 MISC_REG_AEU_GENERAL_ATTN_0;
2359
2360 qed_int_sb_attn_setup(p_hwfn, p_ptt);
2361}
2362
2363static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn,
2364 struct qed_ptt *p_ptt)
2365{
2366 struct qed_dev *cdev = p_hwfn->cdev;
2367 struct qed_sb_attn_info *p_sb;
2368 dma_addr_t p_phys = 0;
2369 void *p_virt;
2370
2371 /* SB struct */
2372 p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL);
2373 if (!p_sb)
2374 return -ENOMEM;
2375
2376 /* SB ring */
2377 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
2378 SB_ATTN_ALIGNED_SIZE(p_hwfn),
2379 &p_phys, GFP_KERNEL);
2380
2381 if (!p_virt) {
2382 kfree(p_sb);
2383 return -ENOMEM;
2384 }
2385
2386 /* Attention setup */
2387 p_hwfn->p_sb_attn = p_sb;
2388 qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys);
2389
2390 return 0;
2391}
2392
2393/* coalescing timeout = timeset << (timer_res + 1) */
2394#define QED_CAU_DEF_RX_USECS 24
2395#define QED_CAU_DEF_TX_USECS 48
2396
2397void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
2398 struct cau_sb_entry *p_sb_entry,
2399 u8 pf_id, u16 vf_number, u8 vf_valid)
2400{
2401 struct qed_dev *cdev = p_hwfn->cdev;
2402 u32 cau_state;
2403 u8 timer_res;
2404
2405 memset(p_sb_entry, 0, sizeof(*p_sb_entry));
2406
2407 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id);
2408 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number);
2409 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid);
2410 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F);
2411 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F);
2412
2413 cau_state = CAU_HC_DISABLE_STATE;
2414
2415 if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
2416 cau_state = CAU_HC_ENABLE_STATE;
2417 if (!cdev->rx_coalesce_usecs)
2418 cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS;
2419 if (!cdev->tx_coalesce_usecs)
2420 cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS;
2421 }
2422
2423 /* Coalesce = (timeset << timer-res), timeset is 7bit wide */
2424 if (cdev->rx_coalesce_usecs <= 0x7F)
2425 timer_res = 0;
2426 else if (cdev->rx_coalesce_usecs <= 0xFF)
2427 timer_res = 1;
2428 else
2429 timer_res = 2;
2430 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
2431
2432 if (cdev->tx_coalesce_usecs <= 0x7F)
2433 timer_res = 0;
2434 else if (cdev->tx_coalesce_usecs <= 0xFF)
2435 timer_res = 1;
2436 else
2437 timer_res = 2;
2438 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
2439
2440 SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state);
2441 SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
2442}
2443
2444void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
2445 struct qed_ptt *p_ptt,
2446 dma_addr_t sb_phys,
2447 u16 igu_sb_id, u16 vf_number, u8 vf_valid)
2448{
2449 struct cau_sb_entry sb_entry;
2450
2451 qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id,
2452 vf_number, vf_valid);
2453
2454 if (p_hwfn->hw_init_done) {
2455 /* Wide-bus, initialize via DMAE */
2456 u64 phys_addr = (u64)sb_phys;
2457
2458 qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr,
2459 CAU_REG_SB_ADDR_MEMORY +
2460 igu_sb_id * sizeof(u64), 2, 0);
2461 qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry,
2462 CAU_REG_SB_VAR_MEMORY +
2463 igu_sb_id * sizeof(u64), 2, 0);
2464 } else {
2465 /* Initialize Status Block Address */
2466 STORE_RT_REG_AGG(p_hwfn,
2467 CAU_REG_SB_ADDR_MEMORY_RT_OFFSET +
2468 igu_sb_id * 2,
2469 sb_phys);
2470
2471 STORE_RT_REG_AGG(p_hwfn,
2472 CAU_REG_SB_VAR_MEMORY_RT_OFFSET +
2473 igu_sb_id * 2,
2474 sb_entry);
2475 }
2476
2477 /* Configure pi coalescing if set */
2478 if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
2479 u8 timeset, timer_res;
2480 u8 num_tc = 1, i;
2481
2482 /* timeset = (coalesce >> timer-res), timeset is 7bit wide */
2483 if (p_hwfn->cdev->rx_coalesce_usecs <= 0x7F)
2484 timer_res = 0;
2485 else if (p_hwfn->cdev->rx_coalesce_usecs <= 0xFF)
2486 timer_res = 1;
2487 else
2488 timer_res = 2;
2489 timeset = (u8)(p_hwfn->cdev->rx_coalesce_usecs >> timer_res);
2490 qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
2491 QED_COAL_RX_STATE_MACHINE, timeset);
2492
2493 if (p_hwfn->cdev->tx_coalesce_usecs <= 0x7F)
2494 timer_res = 0;
2495 else if (p_hwfn->cdev->tx_coalesce_usecs <= 0xFF)
2496 timer_res = 1;
2497 else
2498 timer_res = 2;
2499 timeset = (u8)(p_hwfn->cdev->tx_coalesce_usecs >> timer_res);
2500 for (i = 0; i < num_tc; i++) {
2501 qed_int_cau_conf_pi(p_hwfn, p_ptt,
2502 igu_sb_id, TX_PI(i),
2503 QED_COAL_TX_STATE_MACHINE,
2504 timeset);
2505 }
2506 }
2507}
2508
2509void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,
2510 struct qed_ptt *p_ptt,
2511 u16 igu_sb_id,
2512 u32 pi_index,
2513 enum qed_coalescing_fsm coalescing_fsm,
2514 u8 timeset)
2515{
2516 struct cau_pi_entry pi_entry;
2517 u32 sb_offset, pi_offset;
2518
2519 if (IS_VF(p_hwfn->cdev))
2520 return;
2521
2522 sb_offset = igu_sb_id * PIS_PER_SB;
2523 memset(&pi_entry, 0, sizeof(struct cau_pi_entry));
2524
2525 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
2526 if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE)
2527 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0);
2528 else
2529 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1);
2530
2531 pi_offset = sb_offset + pi_index;
2532 if (p_hwfn->hw_init_done) {
2533 qed_wr(p_hwfn, p_ptt,
2534 CAU_REG_PI_MEMORY + pi_offset * sizeof(u32),
2535 *((u32 *)&(pi_entry)));
2536 } else {
2537 STORE_RT_REG(p_hwfn,
2538 CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
2539 *((u32 *)&(pi_entry)));
2540 }
2541}
2542
2543void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
2544 struct qed_ptt *p_ptt, struct qed_sb_info *sb_info)
2545{
2546 /* zero status block and ack counter */
2547 sb_info->sb_ack = 0;
2548 memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
2549
2550 if (IS_PF(p_hwfn->cdev))
2551 qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,
2552 sb_info->igu_sb_id, 0, 0);
2553}
2554
2555/**
2556 * @brief qed_get_igu_sb_id - given a sw sb_id return the
2557 * igu_sb_id
2558 *
2559 * @param p_hwfn
2560 * @param sb_id
2561 *
2562 * @return u16
2563 */
2564static u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id)
2565{
2566 u16 igu_sb_id;
2567
2568 /* Assuming continuous set of IGU SBs dedicated for given PF */
2569 if (sb_id == QED_SP_SB_ID)
2570 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
2571 else if (IS_PF(p_hwfn->cdev))
2572 igu_sb_id = sb_id + p_hwfn->hw_info.p_igu_info->igu_base_sb;
2573 else
2574 igu_sb_id = qed_vf_get_igu_sb_id(p_hwfn, sb_id);
2575
2576 if (sb_id == QED_SP_SB_ID)
2577 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
2578 "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id);
2579 else
2580 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
2581 "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id);
2582
2583 return igu_sb_id;
2584}
2585
2586int qed_int_sb_init(struct qed_hwfn *p_hwfn,
2587 struct qed_ptt *p_ptt,
2588 struct qed_sb_info *sb_info,
2589 void *sb_virt_addr, dma_addr_t sb_phy_addr, u16 sb_id)
2590{
2591 sb_info->sb_virt = sb_virt_addr;
2592 sb_info->sb_phys = sb_phy_addr;
2593
2594 sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id);
2595
2596 if (sb_id != QED_SP_SB_ID) {
2597 p_hwfn->sbs_info[sb_id] = sb_info;
2598 p_hwfn->num_sbs++;
2599 }
2600
2601 sb_info->cdev = p_hwfn->cdev;
2602
2603 /* The igu address will hold the absolute address that needs to be
2604 * written to for a specific status block
2605 */
2606 if (IS_PF(p_hwfn->cdev)) {
2607 sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview +
2608 GTT_BAR0_MAP_REG_IGU_CMD +
2609 (sb_info->igu_sb_id << 3);
2610 } else {
2611 sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview +
2612 PXP_VF_BAR0_START_IGU +
2613 ((IGU_CMD_INT_ACK_BASE +
2614 sb_info->igu_sb_id) << 3);
2615 }
2616
2617 sb_info->flags |= QED_SB_INFO_INIT;
2618
2619 qed_int_sb_setup(p_hwfn, p_ptt, sb_info);
2620
2621 return 0;
2622}
2623
2624int qed_int_sb_release(struct qed_hwfn *p_hwfn,
2625 struct qed_sb_info *sb_info, u16 sb_id)
2626{
2627 if (sb_id == QED_SP_SB_ID) {
2628 DP_ERR(p_hwfn, "Do Not free sp sb using this function");
2629 return -EINVAL;
2630 }
2631
2632 /* zero status block and ack counter */
2633 sb_info->sb_ack = 0;
2634 memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
2635
2636 if (p_hwfn->sbs_info[sb_id] != NULL) {
2637 p_hwfn->sbs_info[sb_id] = NULL;
2638 p_hwfn->num_sbs--;
2639 }
2640
2641 return 0;
2642}
2643
2644static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn)
2645{
2646 struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb;
2647
2648 if (!p_sb)
2649 return;
2650
2651 if (p_sb->sb_info.sb_virt)
2652 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
2653 SB_ALIGNED_SIZE(p_hwfn),
2654 p_sb->sb_info.sb_virt,
2655 p_sb->sb_info.sb_phys);
2656 kfree(p_sb);
2657}
2658
2659static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2660{
2661 struct qed_sb_sp_info *p_sb;
2662 dma_addr_t p_phys = 0;
2663 void *p_virt;
2664
2665 /* SB struct */
2666 p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL);
2667 if (!p_sb)
2668 return -ENOMEM;
2669
2670 /* SB ring */
2671 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
2672 SB_ALIGNED_SIZE(p_hwfn),
2673 &p_phys, GFP_KERNEL);
2674 if (!p_virt) {
2675 kfree(p_sb);
2676 return -ENOMEM;
2677 }
2678
2679 /* Status Block setup */
2680 p_hwfn->p_sp_sb = p_sb;
2681 qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt,
2682 p_phys, QED_SP_SB_ID);
2683
2684 memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr));
2685
2686 return 0;
2687}
2688
2689int qed_int_register_cb(struct qed_hwfn *p_hwfn,
2690 qed_int_comp_cb_t comp_cb,
2691 void *cookie, u8 *sb_idx, __le16 **p_fw_cons)
2692{
2693 struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
2694 int rc = -ENOMEM;
2695 u8 pi;
2696
2697 /* Look for a free index */
2698 for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) {
2699 if (p_sp_sb->pi_info_arr[pi].comp_cb)
2700 continue;
2701
2702 p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
2703 p_sp_sb->pi_info_arr[pi].cookie = cookie;
2704 *sb_idx = pi;
2705 *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi];
2706 rc = 0;
2707 break;
2708 }
2709
2710 return rc;
2711}
2712
2713int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi)
2714{
2715 struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
2716
2717 if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL)
2718 return -ENOMEM;
2719
2720 p_sp_sb->pi_info_arr[pi].comp_cb = NULL;
2721 p_sp_sb->pi_info_arr[pi].cookie = NULL;
2722
2723 return 0;
2724}
2725
2726u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn)
2727{
2728 return p_hwfn->p_sp_sb->sb_info.igu_sb_id;
2729}
2730
2731void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,
2732 struct qed_ptt *p_ptt, enum qed_int_mode int_mode)
2733{
2734 u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN;
2735
2736 p_hwfn->cdev->int_mode = int_mode;
2737 switch (p_hwfn->cdev->int_mode) {
2738 case QED_INT_MODE_INTA:
2739 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN;
2740 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
2741 break;
2742
2743 case QED_INT_MODE_MSI:
2744 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
2745 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
2746 break;
2747
2748 case QED_INT_MODE_MSIX:
2749 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
2750 break;
2751 case QED_INT_MODE_POLL:
2752 break;
2753 }
2754
2755 qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);
2756}
2757
2758int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2759 enum qed_int_mode int_mode)
2760{
2761 int rc = 0;
2762
2763 /* Configure AEU signal change to produce attentions */
2764 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0);
2765 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);
2766 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);
2767 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff);
2768
2769 /* Flush the writes to IGU */
2770 mmiowb();
2771
2772 /* Unmask AEU signals toward IGU */
2773 qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);
2774 if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {
2775 rc = qed_slowpath_irq_req(p_hwfn);
2776 if (rc) {
2777 DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n");
2778 return -EINVAL;
2779 }
2780 p_hwfn->b_int_requested = true;
2781 }
2782 /* Enable interrupt Generation */
2783 qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
2784 p_hwfn->b_int_enabled = 1;
2785
2786 return rc;
2787}
2788
2789void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2790{
2791 p_hwfn->b_int_enabled = 0;
2792
2793 if (IS_VF(p_hwfn->cdev))
2794 return;
2795
2796 qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
2797}
2798
2799#define IGU_CLEANUP_SLEEP_LENGTH (1000)
2800static void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn,
2801 struct qed_ptt *p_ptt,
2802 u32 sb_id, bool cleanup_set, u16 opaque_fid)
2803{
2804 u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0;
2805 u32 pxp_addr = IGU_CMD_INT_ACK_BASE + sb_id;
2806 u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH;
2807
2808 /* Set the data field */
2809 SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0);
2810 SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0);
2811 SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET);
2812
2813 /* Set the control register */
2814 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr);
2815 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid);
2816 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR);
2817
2818 qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);
2819
2820 barrier();
2821
2822 qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);
2823
2824 /* Flush the write to IGU */
2825 mmiowb();
2826
2827 /* calculate where to read the status bit from */
2828 sb_bit = 1 << (sb_id % 32);
2829 sb_bit_addr = sb_id / 32 * sizeof(u32);
2830
2831 sb_bit_addr += IGU_REG_CLEANUP_STATUS_0;
2832
2833 /* Now wait for the command to complete */
2834 do {
2835 val = qed_rd(p_hwfn, p_ptt, sb_bit_addr);
2836
2837 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0))
2838 break;
2839
2840 usleep_range(5000, 10000);
2841 } while (--sleep_cnt);
2842
2843 if (!sleep_cnt)
2844 DP_NOTICE(p_hwfn,
2845 "Timeout waiting for clear status 0x%08x [for sb %d]\n",
2846 val, sb_id);
2847}
2848
2849void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
2850 struct qed_ptt *p_ptt,
2851 u32 sb_id, u16 opaque, bool b_set)
2852{
2853 int pi, i;
2854
2855 /* Set */
2856 if (b_set)
2857 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 1, opaque);
2858
2859 /* Clear */
2860 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 0, opaque);
2861
2862 /* Wait for the IGU SB to cleanup */
2863 for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) {
2864 u32 val;
2865
2866 val = qed_rd(p_hwfn, p_ptt,
2867 IGU_REG_WRITE_DONE_PENDING + ((sb_id / 32) * 4));
2868 if (val & (1 << (sb_id % 32)))
2869 usleep_range(10, 20);
2870 else
2871 break;
2872 }
2873 if (i == IGU_CLEANUP_SLEEP_LENGTH)
2874 DP_NOTICE(p_hwfn,
2875 "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n",
2876 sb_id);
2877
2878 /* Clear the CAU for the SB */
2879 for (pi = 0; pi < 12; pi++)
2880 qed_wr(p_hwfn, p_ptt,
2881 CAU_REG_PI_MEMORY + (sb_id * 12 + pi) * 4, 0);
2882}
2883
2884void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
2885 struct qed_ptt *p_ptt,
2886 bool b_set, bool b_slowpath)
2887{
2888 u32 igu_base_sb = p_hwfn->hw_info.p_igu_info->igu_base_sb;
2889 u32 igu_sb_cnt = p_hwfn->hw_info.p_igu_info->igu_sb_cnt;
2890 u32 sb_id = 0, val = 0;
2891
2892 val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
2893 val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN;
2894 val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN;
2895 qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);
2896
2897 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
2898 "IGU cleaning SBs [%d,...,%d]\n",
2899 igu_base_sb, igu_base_sb + igu_sb_cnt - 1);
2900
2901 for (sb_id = igu_base_sb; sb_id < igu_base_sb + igu_sb_cnt; sb_id++)
2902 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id,
2903 p_hwfn->hw_info.opaque_fid,
2904 b_set);
2905
2906 if (!b_slowpath)
2907 return;
2908
2909 sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
2910 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
2911 "IGU cleaning slowpath SB [%d]\n", sb_id);
2912 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id,
2913 p_hwfn->hw_info.opaque_fid, b_set);
2914}
2915
2916static u32 qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn,
2917 struct qed_ptt *p_ptt, u16 sb_id)
2918{
2919 u32 val = qed_rd(p_hwfn, p_ptt,
2920 IGU_REG_MAPPING_MEMORY + sizeof(u32) * sb_id);
2921 struct qed_igu_block *p_block;
2922
2923 p_block = &p_hwfn->hw_info.p_igu_info->igu_map.igu_blocks[sb_id];
2924
2925 /* stop scanning when hit first invalid PF entry */
2926 if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) &&
2927 GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID))
2928 goto out;
2929
2930 /* Fill the block information */
2931 p_block->status = QED_IGU_STATUS_VALID;
2932 p_block->function_id = GET_FIELD(val,
2933 IGU_MAPPING_LINE_FUNCTION_NUMBER);
2934 p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
2935 p_block->vector_number = GET_FIELD(val,
2936 IGU_MAPPING_LINE_VECTOR_NUMBER);
2937
2938 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
2939 "IGU_BLOCK: [SB 0x%04x, Value in CAM 0x%08x] func_id = %d is_pf = %d vector_num = 0x%x\n",
2940 sb_id, val, p_block->function_id,
2941 p_block->is_pf, p_block->vector_number);
2942
2943out:
2944 return val;
2945}
2946
2947int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2948{
2949 struct qed_igu_info *p_igu_info;
2950 u32 val, min_vf = 0, max_vf = 0;
2951 u16 sb_id, last_iov_sb_id = 0;
2952 struct qed_igu_block *blk;
2953 u16 prev_sb_id = 0xFF;
2954
2955 p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL);
2956 if (!p_hwfn->hw_info.p_igu_info)
2957 return -ENOMEM;
2958
2959 p_igu_info = p_hwfn->hw_info.p_igu_info;
2960
2961 /* Initialize base sb / sb cnt for PFs and VFs */
2962 p_igu_info->igu_base_sb = 0xffff;
2963 p_igu_info->igu_sb_cnt = 0;
2964 p_igu_info->igu_dsb_id = 0xffff;
2965 p_igu_info->igu_base_sb_iov = 0xffff;
2966
2967 if (p_hwfn->cdev->p_iov_info) {
2968 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
2969
2970 min_vf = p_iov->first_vf_in_pf;
2971 max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs;
2972 }
2973
2974 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev);
2975 sb_id++) {
2976 blk = &p_igu_info->igu_map.igu_blocks[sb_id];
2977
2978 val = qed_int_igu_read_cam_block(p_hwfn, p_ptt, sb_id);
2979
2980 /* stop scanning when hit first invalid PF entry */
2981 if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) &&
2982 GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID))
2983 break;
2984
2985 if (blk->is_pf) {
2986 if (blk->function_id == p_hwfn->rel_pf_id) {
2987 blk->status |= QED_IGU_STATUS_PF;
2988
2989 if (blk->vector_number == 0) {
2990 if (p_igu_info->igu_dsb_id == 0xffff)
2991 p_igu_info->igu_dsb_id = sb_id;
2992 } else {
2993 if (p_igu_info->igu_base_sb ==
2994 0xffff) {
2995 p_igu_info->igu_base_sb = sb_id;
2996 } else if (prev_sb_id != sb_id - 1) {
2997 DP_NOTICE(p_hwfn->cdev,
2998 "consecutive igu vectors for HWFN %x broken",
2999 p_hwfn->rel_pf_id);
3000 break;
3001 }
3002 prev_sb_id = sb_id;
3003 /* we don't count the default */
3004 (p_igu_info->igu_sb_cnt)++;
3005 }
3006 }
3007 } else {
3008 if ((blk->function_id >= min_vf) &&
3009 (blk->function_id < max_vf)) {
3010 /* Available for VFs of this PF */
3011 if (p_igu_info->igu_base_sb_iov == 0xffff) {
3012 p_igu_info->igu_base_sb_iov = sb_id;
3013 } else if (last_iov_sb_id != sb_id - 1) {
3014 if (!val) {
3015 DP_VERBOSE(p_hwfn->cdev,
3016 NETIF_MSG_INTR,
3017 "First uninitialized IGU CAM entry at index 0x%04x\n",
3018 sb_id);
3019 } else {
3020 DP_NOTICE(p_hwfn->cdev,
3021 "Consecutive igu vectors for HWFN %x vfs is broken [jumps from %04x to %04x]\n",
3022 p_hwfn->rel_pf_id,
3023 last_iov_sb_id,
3024 sb_id); }
3025 break;
3026 }
3027 blk->status |= QED_IGU_STATUS_FREE;
3028 p_hwfn->hw_info.p_igu_info->free_blks++;
3029 last_iov_sb_id = sb_id;
3030 }
3031 }
3032 }
3033
3034 /* There's a possibility the igu_sb_cnt_iov doesn't properly reflect
3035 * the number of VF SBs [especially for first VF on engine, as we can't
3036 * diffrentiate between empty entries and its entries].
3037 * Since we don't really support more SBs than VFs today, prevent any
3038 * such configuration by sanitizing the number of SBs to equal the
3039 * number of VFs.
3040 */
3041 if (IS_PF_SRIOV(p_hwfn)) {
3042 u16 total_vfs = p_hwfn->cdev->p_iov_info->total_vfs;
3043
3044 if (total_vfs < p_igu_info->free_blks) {
3045 DP_VERBOSE(p_hwfn,
3046 (NETIF_MSG_INTR | QED_MSG_IOV),
3047 "Limiting number of SBs for IOV - %04x --> %04x\n",
3048 p_igu_info->free_blks,
3049 p_hwfn->cdev->p_iov_info->total_vfs);
3050 p_igu_info->free_blks = total_vfs;
3051 } else if (total_vfs > p_igu_info->free_blks) {
3052 DP_NOTICE(p_hwfn,
3053 "IGU has only %04x SBs for VFs while the device has %04x VFs\n",
3054 p_igu_info->free_blks, total_vfs);
3055 return -EINVAL;
3056 }
3057 }
3058 p_igu_info->igu_sb_cnt_iov = p_igu_info->free_blks;
3059
3060 DP_VERBOSE(
3061 p_hwfn,
3062 NETIF_MSG_INTR,
3063 "IGU igu_base_sb=0x%x [IOV 0x%x] igu_sb_cnt=%d [IOV 0x%x] igu_dsb_id=0x%x\n",
3064 p_igu_info->igu_base_sb,
3065 p_igu_info->igu_base_sb_iov,
3066 p_igu_info->igu_sb_cnt,
3067 p_igu_info->igu_sb_cnt_iov,
3068 p_igu_info->igu_dsb_id);
3069
3070 if (p_igu_info->igu_base_sb == 0xffff ||
3071 p_igu_info->igu_dsb_id == 0xffff ||
3072 p_igu_info->igu_sb_cnt == 0) {
3073 DP_NOTICE(p_hwfn,
3074 "IGU CAM returned invalid values igu_base_sb=0x%x igu_sb_cnt=%d igu_dsb_id=0x%x\n",
3075 p_igu_info->igu_base_sb,
3076 p_igu_info->igu_sb_cnt,
3077 p_igu_info->igu_dsb_id);
3078 return -EINVAL;
3079 }
3080
3081 return 0;
3082}
3083
3084/**
3085 * @brief Initialize igu runtime registers
3086 *
3087 * @param p_hwfn
3088 */
3089void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn)
3090{
3091 u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN;
3092
3093 STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);
3094}
3095
3096u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn)
3097{
3098 u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER -
3099 IGU_CMD_INT_ACK_BASE;
3100 u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER -
3101 IGU_CMD_INT_ACK_BASE;
3102 u32 intr_status_hi = 0, intr_status_lo = 0;
3103 u64 intr_status = 0;
3104
3105 intr_status_lo = REG_RD(p_hwfn,
3106 GTT_BAR0_MAP_REG_IGU_CMD +
3107 lsb_igu_cmd_addr * 8);
3108 intr_status_hi = REG_RD(p_hwfn,
3109 GTT_BAR0_MAP_REG_IGU_CMD +
3110 msb_igu_cmd_addr * 8);
3111 intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo;
3112
3113 return intr_status;
3114}
3115
3116static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn)
3117{
3118 tasklet_init(p_hwfn->sp_dpc,
3119 qed_int_sp_dpc, (unsigned long)p_hwfn);
3120 p_hwfn->b_sp_dpc_enabled = true;
3121}
3122
3123static int qed_int_sp_dpc_alloc(struct qed_hwfn *p_hwfn)
3124{
3125 p_hwfn->sp_dpc = kmalloc(sizeof(*p_hwfn->sp_dpc), GFP_KERNEL);
3126 if (!p_hwfn->sp_dpc)
3127 return -ENOMEM;
3128
3129 return 0;
3130}
3131
3132static void qed_int_sp_dpc_free(struct qed_hwfn *p_hwfn)
3133{
3134 kfree(p_hwfn->sp_dpc);
3135}
3136
3137int qed_int_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3138{
3139 int rc = 0;
3140
3141 rc = qed_int_sp_dpc_alloc(p_hwfn);
3142 if (rc)
3143 return rc;
3144
3145 rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt);
3146 if (rc)
3147 return rc;
3148
3149 rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt);
3150
3151 return rc;
3152}
3153
3154void qed_int_free(struct qed_hwfn *p_hwfn)
3155{
3156 qed_int_sp_sb_free(p_hwfn);
3157 qed_int_sb_attn_free(p_hwfn);
3158 qed_int_sp_dpc_free(p_hwfn);
3159}
3160
3161void qed_int_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3162{
3163 qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);
3164 qed_int_sb_attn_setup(p_hwfn, p_ptt);
3165 qed_int_sp_dpc_setup(p_hwfn);
3166}
3167
3168void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,
3169 struct qed_sb_cnt_info *p_sb_cnt_info)
3170{
3171 struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info;
3172
3173 if (!info || !p_sb_cnt_info)
3174 return;
3175
3176 p_sb_cnt_info->sb_cnt = info->igu_sb_cnt;
3177 p_sb_cnt_info->sb_iov_cnt = info->igu_sb_cnt_iov;
3178 p_sb_cnt_info->sb_free_blk = info->free_blks;
3179}
3180
3181u16 qed_int_queue_id_from_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id)
3182{
3183 struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
3184
3185 /* Determine origin of SB id */
3186 if ((sb_id >= p_info->igu_base_sb) &&
3187 (sb_id < p_info->igu_base_sb + p_info->igu_sb_cnt)) {
3188 return sb_id - p_info->igu_base_sb;
3189 } else if ((sb_id >= p_info->igu_base_sb_iov) &&
3190 (sb_id < p_info->igu_base_sb_iov + p_info->igu_sb_cnt_iov)) {
3191 /* We want the first VF queue to be adjacent to the
3192 * last PF queue. Since L2 queues can be partial to
3193 * SBs, we'll use the feature instead.
3194 */
3195 return sb_id - p_info->igu_base_sb_iov +
3196 FEAT_NUM(p_hwfn, QED_PF_L2_QUE);
3197 } else {
3198 DP_NOTICE(p_hwfn, "SB %d not in range for function\n", sb_id);
3199 return 0;
3200 }
3201}
3202
3203void qed_int_disable_post_isr_release(struct qed_dev *cdev)
3204{
3205 int i;
3206
3207 for_each_hwfn(cdev, i)
3208 cdev->hwfns[i].b_int_requested = false;
3209}
3210
3211int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3212 u8 timer_res, u16 sb_id, bool tx)
3213{
3214 struct cau_sb_entry sb_entry;
3215 int rc;
3216
3217 if (!p_hwfn->hw_init_done) {
3218 DP_ERR(p_hwfn, "hardware not initialized yet\n");
3219 return -EINVAL;
3220 }
3221
3222 rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
3223 sb_id * sizeof(u64),
3224 (u64)(uintptr_t)&sb_entry, 2, 0);
3225 if (rc) {
3226 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
3227 return rc;
3228 }
3229
3230 if (tx)
3231 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
3232 else
3233 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
3234
3235 rc = qed_dmae_host2grc(p_hwfn, p_ptt,
3236 (u64)(uintptr_t)&sb_entry,
3237 CAU_REG_SB_VAR_MEMORY +
3238 sb_id * sizeof(u64), 2, 0);
3239 if (rc) {
3240 DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc);
3241 return rc;
3242 }
3243
3244 return rc;
3245}