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1/* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
9#ifndef REG_ADDR_H
10#define REG_ADDR_H
11
12#define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \
13 0
14
15#define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \
16 0xfff << 0)
17
18#define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \
19 12
20
21#define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \
22 0xfff << 12)
23
24#define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \
25 24
26
27#define CDU_REG_CID_ADDR_PARAMS_NCIB ( \
28 0xff << 24)
29
30#define CDU_REG_SEGMENT0_PARAMS \
31 0x580904UL
32#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK \
33 (0xfff << 0)
34#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT \
35 0
36#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE \
37 (0xff << 16)
38#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT \
39 16
40#define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE \
41 (0xff << 24)
42#define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT \
43 24
44#define CDU_REG_SEGMENT1_PARAMS \
45 0x580908UL
46#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK \
47 (0xfff << 0)
48#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT \
49 0
50#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE \
51 (0xff << 16)
52#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT \
53 16
54#define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE \
55 (0xff << 24)
56#define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT \
57 24
58
59#define XSDM_REG_OPERATION_GEN \
60 0xf80408UL
61#define NIG_REG_RX_BRB_OUT_EN \
62 0x500e18UL
63#define NIG_REG_STORM_OUT_EN \
64 0x500e08UL
65#define PSWRQ2_REG_L2P_VALIDATE_VFID \
66 0x240c50UL
67#define PGLUE_B_REG_USE_CLIENTID_IN_TAG \
68 0x2aae04UL
69#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \
70 0x2aa16cUL
71#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \
72 0x2aa118UL
73#define PSWHST_REG_ZONE_PERMISSION_TABLE \
74 0x2a0800UL
75#define BAR0_MAP_REG_MSDM_RAM \
76 0x1d00000UL
77#define BAR0_MAP_REG_USDM_RAM \
78 0x1d80000UL
79#define BAR0_MAP_REG_PSDM_RAM \
80 0x1f00000UL
81#define BAR0_MAP_REG_TSDM_RAM \
82 0x1c80000UL
83#define BAR0_MAP_REG_XSDM_RAM \
84 0x1e00000UL
85#define BAR0_MAP_REG_YSDM_RAM \
86 0x1e80000UL
87#define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \
88 0x5011f4UL
89#define PRS_REG_SEARCH_TCP \
90 0x1f0400UL
91#define PRS_REG_SEARCH_UDP \
92 0x1f0404UL
93#define PRS_REG_SEARCH_FCOE \
94 0x1f0408UL
95#define PRS_REG_SEARCH_ROCE \
96 0x1f040cUL
97#define PRS_REG_SEARCH_OPENFLOW \
98 0x1f0434UL
99#define TM_REG_PF_ENABLE_CONN \
100 0x2c043cUL
101#define TM_REG_PF_ENABLE_TASK \
102 0x2c0444UL
103#define TM_REG_PF_SCAN_ACTIVE_CONN \
104 0x2c04fcUL
105#define TM_REG_PF_SCAN_ACTIVE_TASK \
106 0x2c0500UL
107#define IGU_REG_LEADING_EDGE_LATCH \
108 0x18082cUL
109#define IGU_REG_TRAILING_EDGE_LATCH \
110 0x180830UL
111#define QM_REG_USG_CNT_PF_TX \
112 0x2f2eacUL
113#define QM_REG_USG_CNT_PF_OTHER \
114 0x2f2eb0UL
115#define DORQ_REG_PF_DB_ENABLE \
116 0x100508UL
117#define DORQ_REG_VF_USAGE_CNT \
118 0x1009c4UL
119#define QM_REG_PF_EN \
120 0x2f2ea4UL
121#define TCFC_REG_WEAK_ENABLE_VF \
122 0x2d0704UL
123#define TCFC_REG_STRONG_ENABLE_PF \
124 0x2d0708UL
125#define TCFC_REG_STRONG_ENABLE_VF \
126 0x2d070cUL
127#define CCFC_REG_WEAK_ENABLE_VF \
128 0x2e0704UL
129#define CCFC_REG_STRONG_ENABLE_PF \
130 0x2e0708UL
131#define PGLUE_B_REG_PGL_ADDR_88_F0 \
132 0x2aa404UL
133#define PGLUE_B_REG_PGL_ADDR_8C_F0 \
134 0x2aa408UL
135#define PGLUE_B_REG_PGL_ADDR_90_F0 \
136 0x2aa40cUL
137#define PGLUE_B_REG_PGL_ADDR_94_F0 \
138 0x2aa410UL
139#define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \
140 0x2aa138UL
141#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
142 0x2aa174UL
143#define MISC_REG_GEN_PURP_CR0 \
144 0x008c80UL
145#define MCP_REG_SCRATCH \
146 0xe20000UL
147#define CNIG_REG_NW_PORT_MODE_BB_B0 \
148 0x218200UL
149#define MISCS_REG_CHIP_NUM \
150 0x00976cUL
151#define MISCS_REG_CHIP_REV \
152 0x009770UL
153#define MISCS_REG_CMT_ENABLED_FOR_PAIR \
154 0x00971cUL
155#define MISCS_REG_CHIP_TEST_REG \
156 0x009778UL
157#define MISCS_REG_CHIP_METAL \
158 0x009774UL
159#define MISCS_REG_FUNCTION_HIDE \
160 0x0096f0UL
161#define BRB_REG_HEADER_SIZE \
162 0x340804UL
163#define BTB_REG_HEADER_SIZE \
164 0xdb0804UL
165#define CAU_REG_LONG_TIMEOUT_THRESHOLD \
166 0x1c0708UL
167#define CCFC_REG_ACTIVITY_COUNTER \
168 0x2e8800UL
169#define CCFC_REG_STRONG_ENABLE_VF \
170 0x2e070cUL
171#define CDU_REG_CID_ADDR_PARAMS \
172 0x580900UL
173#define DBG_REG_CLIENT_ENABLE \
174 0x010004UL
175#define DMAE_REG_INIT \
176 0x00c000UL
177#define DORQ_REG_IFEN \
178 0x100040UL
179#define DORQ_REG_DB_DROP_REASON \
180 0x100a2cUL
181#define DORQ_REG_DB_DROP_DETAILS \
182 0x100a24UL
183#define DORQ_REG_DB_DROP_DETAILS_ADDRESS \
184 0x100a1cUL
185#define GRC_REG_TIMEOUT_EN \
186 0x050404UL
187#define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \
188 0x050054UL
189#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \
190 0x05004cUL
191#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \
192 0x050050UL
193#define IGU_REG_BLOCK_CONFIGURATION \
194 0x180040UL
195#define MCM_REG_INIT \
196 0x1200000UL
197#define MCP2_REG_DBG_DWORD_ENABLE \
198 0x052404UL
199#define MISC_REG_PORT_MODE \
200 0x008c00UL
201#define MISCS_REG_CLK_100G_MODE \
202 0x009070UL
203#define MSDM_REG_ENABLE_IN1 \
204 0xfc0004UL
205#define MSEM_REG_ENABLE_IN \
206 0x1800004UL
207#define NIG_REG_CM_HDR \
208 0x500840UL
209#define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR \
210 0x50196cUL
211#define NIG_REG_LLH_CLS_TYPE_DUALMODE \
212 0x501964UL
213#define NIG_REG_LLH_FUNC_FILTER_VALUE \
214 0x501a00UL
215#define NIG_REG_LLH_FUNC_FILTER_VALUE_SIZE \
216 32
217#define NIG_REG_LLH_FUNC_FILTER_EN \
218 0x501a80UL
219#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE \
220 16
221#define NIG_REG_LLH_FUNC_FILTER_MODE \
222 0x501ac0UL
223#define NIG_REG_LLH_FUNC_FILTER_MODE_SIZE \
224 16
225#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE \
226 0x501b00UL
227#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_SIZE \
228 16
229#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL \
230 0x501b40UL
231#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_SIZE \
232 16
233#define NCSI_REG_CONFIG \
234 0x040200UL
235#define PBF_REG_INIT \
236 0xd80000UL
237#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 \
238 0xd806c8UL
239#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 \
240 0xd806ccUL
241#define PTU_REG_ATC_INIT_ARRAY \
242 0x560000UL
243#define PCM_REG_INIT \
244 0x1100000UL
245#define PGLUE_B_REG_ADMIN_PER_PF_REGION \
246 0x2a9000UL
247#define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \
248 0x2aa150UL
249#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \
250 0x2aa144UL
251#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \
252 0x2aa148UL
253#define PGLUE_B_REG_TX_ERR_WR_DETAILS \
254 0x2aa14cUL
255#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \
256 0x2aa154UL
257#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \
258 0x2aa158UL
259#define PGLUE_B_REG_TX_ERR_RD_DETAILS \
260 0x2aa15cUL
261#define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \
262 0x2aa160UL
263#define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \
264 0x2aa164UL
265#define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \
266 0x2aa54cUL
267#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \
268 0x2aa544UL
269#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \
270 0x2aa548UL
271#define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \
272 0x2aae74UL
273#define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \
274 0x2aae78UL
275#define PGLUE_B_REG_VF_ILT_ERR_DETAILS \
276 0x2aae7cUL
277#define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \
278 0x2aae80UL
279#define PGLUE_B_REG_LATCHED_ERRORS_CLR \
280 0x2aa3bcUL
281#define PRM_REG_DISABLE_PRM \
282 0x230000UL
283#define PRS_REG_SOFT_RST \
284 0x1f0000UL
285#define PRS_REG_MSG_INFO \
286 0x1f0a1cUL
287#define PRS_REG_ROCE_DEST_QP_MAX_PF \
288 0x1f0430UL
289#define PRS_REG_USE_LIGHT_L2 \
290 0x1f096cUL
291#define PSDM_REG_ENABLE_IN1 \
292 0xfa0004UL
293#define PSEM_REG_ENABLE_IN \
294 0x1600004UL
295#define PSWRQ_REG_DBG_SELECT \
296 0x280020UL
297#define PSWRQ2_REG_CDUT_P_SIZE \
298 0x24000cUL
299#define PSWRQ2_REG_ILT_MEMORY \
300 0x260000UL
301#define PSWHST_REG_DISCARD_INTERNAL_WRITES \
302 0x2a0040UL
303#define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
304 0x29e050UL
305#define PSWHST_REG_INCORRECT_ACCESS_VALID \
306 0x2a0070UL
307#define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \
308 0x2a0074UL
309#define PSWHST_REG_INCORRECT_ACCESS_DATA \
310 0x2a0068UL
311#define PSWHST_REG_INCORRECT_ACCESS_LENGTH \
312 0x2a006cUL
313#define PSWRD_REG_DBG_SELECT \
314 0x29c040UL
315#define PSWRD2_REG_CONF11 \
316 0x29d064UL
317#define PSWWR_REG_USDM_FULL_TH \
318 0x29a040UL
319#define PSWWR2_REG_CDU_FULL_TH2 \
320 0x29b040UL
321#define QM_REG_MAXPQSIZE_0 \
322 0x2f0434UL
323#define RSS_REG_RSS_INIT_EN \
324 0x238804UL
325#define RDIF_REG_STOP_ON_ERROR \
326 0x300040UL
327#define SRC_REG_SOFT_RST \
328 0x23874cUL
329#define TCFC_REG_ACTIVITY_COUNTER \
330 0x2d8800UL
331#define TCM_REG_INIT \
332 0x1180000UL
333#define TM_REG_PXP_READ_DATA_FIFO_INIT \
334 0x2c0014UL
335#define TSDM_REG_ENABLE_IN1 \
336 0xfb0004UL
337#define TSEM_REG_ENABLE_IN \
338 0x1700004UL
339#define TDIF_REG_STOP_ON_ERROR \
340 0x310040UL
341#define UCM_REG_INIT \
342 0x1280000UL
343#define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \
344 0x051004UL
345#define USDM_REG_ENABLE_IN1 \
346 0xfd0004UL
347#define USEM_REG_ENABLE_IN \
348 0x1900004UL
349#define XCM_REG_INIT \
350 0x1000000UL
351#define XSDM_REG_ENABLE_IN1 \
352 0xf80004UL
353#define XSEM_REG_ENABLE_IN \
354 0x1400004UL
355#define YCM_REG_INIT \
356 0x1080000UL
357#define YSDM_REG_ENABLE_IN1 \
358 0xf90004UL
359#define YSEM_REG_ENABLE_IN \
360 0x1500004UL
361#define XYLD_REG_SCBD_STRICT_PRIO \
362 0x4c0000UL
363#define TMLD_REG_SCBD_STRICT_PRIO \
364 0x4d0000UL
365#define MULD_REG_SCBD_STRICT_PRIO \
366 0x4e0000UL
367#define YULD_REG_SCBD_STRICT_PRIO \
368 0x4c8000UL
369#define MISC_REG_SHARED_MEM_ADDR \
370 0x008c20UL
371#define DMAE_REG_GO_C0 \
372 0x00c048UL
373#define DMAE_REG_GO_C1 \
374 0x00c04cUL
375#define DMAE_REG_GO_C2 \
376 0x00c050UL
377#define DMAE_REG_GO_C3 \
378 0x00c054UL
379#define DMAE_REG_GO_C4 \
380 0x00c058UL
381#define DMAE_REG_GO_C5 \
382 0x00c05cUL
383#define DMAE_REG_GO_C6 \
384 0x00c060UL
385#define DMAE_REG_GO_C7 \
386 0x00c064UL
387#define DMAE_REG_GO_C8 \
388 0x00c068UL
389#define DMAE_REG_GO_C9 \
390 0x00c06cUL
391#define DMAE_REG_GO_C10 \
392 0x00c070UL
393#define DMAE_REG_GO_C11 \
394 0x00c074UL
395#define DMAE_REG_GO_C12 \
396 0x00c078UL
397#define DMAE_REG_GO_C13 \
398 0x00c07cUL
399#define DMAE_REG_GO_C14 \
400 0x00c080UL
401#define DMAE_REG_GO_C15 \
402 0x00c084UL
403#define DMAE_REG_GO_C16 \
404 0x00c088UL
405#define DMAE_REG_GO_C17 \
406 0x00c08cUL
407#define DMAE_REG_GO_C18 \
408 0x00c090UL
409#define DMAE_REG_GO_C19 \
410 0x00c094UL
411#define DMAE_REG_GO_C20 \
412 0x00c098UL
413#define DMAE_REG_GO_C21 \
414 0x00c09cUL
415#define DMAE_REG_GO_C22 \
416 0x00c0a0UL
417#define DMAE_REG_GO_C23 \
418 0x00c0a4UL
419#define DMAE_REG_GO_C24 \
420 0x00c0a8UL
421#define DMAE_REG_GO_C25 \
422 0x00c0acUL
423#define DMAE_REG_GO_C26 \
424 0x00c0b0UL
425#define DMAE_REG_GO_C27 \
426 0x00c0b4UL
427#define DMAE_REG_GO_C28 \
428 0x00c0b8UL
429#define DMAE_REG_GO_C29 \
430 0x00c0bcUL
431#define DMAE_REG_GO_C30 \
432 0x00c0c0UL
433#define DMAE_REG_GO_C31 \
434 0x00c0c4UL
435#define DMAE_REG_CMD_MEM \
436 0x00c800UL
437#define QM_REG_MAXPQSIZETXSEL_0 \
438 0x2f0440UL
439#define QM_REG_SDMCMDREADY \
440 0x2f1e10UL
441#define QM_REG_SDMCMDADDR \
442 0x2f1e04UL
443#define QM_REG_SDMCMDDATALSB \
444 0x2f1e08UL
445#define QM_REG_SDMCMDDATAMSB \
446 0x2f1e0cUL
447#define QM_REG_SDMCMDGO \
448 0x2f1e14UL
449#define QM_REG_RLPFCRD \
450 0x2f4d80UL
451#define QM_REG_RLPFINCVAL \
452 0x2f4c80UL
453#define QM_REG_RLGLBLCRD \
454 0x2f4400UL
455#define QM_REG_RLGLBLINCVAL \
456 0x2f3400UL
457#define IGU_REG_ATTENTION_ENABLE \
458 0x18083cUL
459#define IGU_REG_ATTN_MSG_ADDR_L \
460 0x180820UL
461#define IGU_REG_ATTN_MSG_ADDR_H \
462 0x180824UL
463#define MISC_REG_AEU_GENERAL_ATTN_0 \
464 0x008400UL
465#define CAU_REG_SB_ADDR_MEMORY \
466 0x1c8000UL
467#define CAU_REG_SB_VAR_MEMORY \
468 0x1c6000UL
469#define CAU_REG_PI_MEMORY \
470 0x1d0000UL
471#define IGU_REG_PF_CONFIGURATION \
472 0x180800UL
473#define IGU_REG_VF_CONFIGURATION \
474 0x180804UL
475#define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \
476 0x00849cUL
477#define MISC_REG_AEU_AFTER_INVERT_1_IGU \
478 0x0087b4UL
479#define MISC_REG_AEU_MASK_ATTN_IGU \
480 0x008494UL
481#define IGU_REG_CLEANUP_STATUS_0 \
482 0x180980UL
483#define IGU_REG_CLEANUP_STATUS_1 \
484 0x180a00UL
485#define IGU_REG_CLEANUP_STATUS_2 \
486 0x180a80UL
487#define IGU_REG_CLEANUP_STATUS_3 \
488 0x180b00UL
489#define IGU_REG_CLEANUP_STATUS_4 \
490 0x180b80UL
491#define IGU_REG_COMMAND_REG_32LSB_DATA \
492 0x180840UL
493#define IGU_REG_COMMAND_REG_CTRL \
494 0x180848UL
495#define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \
496 0x1 << 1)
497#define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \
498 0x1 << 0)
499#define IGU_REG_MAPPING_MEMORY \
500 0x184000UL
501#define IGU_REG_STATISTIC_NUM_VF_MSG_SENT \
502 0x180408UL
503#define IGU_REG_WRITE_DONE_PENDING \
504 0x180900UL
505#define MISCS_REG_GENERIC_POR_0 \
506 0x0096d4UL
507#define MCP_REG_NVM_CFG4 \
508 0xe0642cUL
509#define MCP_REG_NVM_CFG4_FLASH_SIZE ( \
510 0x7 << 0)
511#define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \
512 0
513#define MCP_REG_CPU_STATE \
514 0xe05004UL
515#define MCP_REG_CPU_EVENT_MASK \
516 0xe05008UL
517#define PGLUE_B_REG_PF_BAR0_SIZE \
518 0x2aae60UL
519#define PGLUE_B_REG_PF_BAR1_SIZE \
520 0x2aae64UL
521#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL
522#define PRS_REG_GRE_PROTOCOL 0x1f0734UL
523#define PRS_REG_VXLAN_PORT 0x1f0738UL
524#define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL
525#define NIG_REG_ENC_TYPE_ENABLE 0x501058UL
526
527#define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0)
528#define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0
529#define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE (0x1 << 1)
530#define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1
531#define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE (0x1 << 2)
532#define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2
533
534#define NIG_REG_VXLAN_CTRL 0x50105cUL
535#define PBF_REG_VXLAN_PORT 0xd80518UL
536#define PBF_REG_NGE_PORT 0xd8051cUL
537#define PRS_REG_NGE_PORT 0x1f086cUL
538#define NIG_REG_NGE_PORT 0x508b38UL
539
540#define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL
541#define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL
542#define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL
543#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN 0x10092cUL
544#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN 0x100930UL
545
546#define NIG_REG_NGE_IP_ENABLE 0x508b28UL
547#define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL
548#define NIG_REG_NGE_COMP_VER 0x508b30UL
549#define PBF_REG_NGE_COMP_VER 0xd80524UL
550#define PRS_REG_NGE_COMP_VER 0x1f0878UL
551
552#define QM_REG_WFQPFWEIGHT 0x2f4e80UL
553#define QM_REG_WFQVPWEIGHT 0x2fa000UL
554
555#define PGLCS_REG_DBG_SELECT \
556 0x001d14UL
557#define PGLCS_REG_DBG_DWORD_ENABLE \
558 0x001d18UL
559#define PGLCS_REG_DBG_SHIFT \
560 0x001d1cUL
561#define PGLCS_REG_DBG_FORCE_VALID \
562 0x001d20UL
563#define PGLCS_REG_DBG_FORCE_FRAME \
564 0x001d24UL
565#define MISC_REG_RESET_PL_PDA_VMAIN_1 \
566 0x008070UL
567#define MISC_REG_RESET_PL_PDA_VMAIN_2 \
568 0x008080UL
569#define MISC_REG_RESET_PL_PDA_VAUX \
570 0x008090UL
571#define MISCS_REG_RESET_PL_UA \
572 0x009050UL
573#define MISCS_REG_RESET_PL_HV \
574 0x009060UL
575#define MISCS_REG_RESET_PL_HV_2 \
576 0x009150UL
577#define DMAE_REG_DBG_SELECT \
578 0x00c510UL
579#define DMAE_REG_DBG_DWORD_ENABLE \
580 0x00c514UL
581#define DMAE_REG_DBG_SHIFT \
582 0x00c518UL
583#define DMAE_REG_DBG_FORCE_VALID \
584 0x00c51cUL
585#define DMAE_REG_DBG_FORCE_FRAME \
586 0x00c520UL
587#define NCSI_REG_DBG_SELECT \
588 0x040474UL
589#define NCSI_REG_DBG_DWORD_ENABLE \
590 0x040478UL
591#define NCSI_REG_DBG_SHIFT \
592 0x04047cUL
593#define NCSI_REG_DBG_FORCE_VALID \
594 0x040480UL
595#define NCSI_REG_DBG_FORCE_FRAME \
596 0x040484UL
597#define GRC_REG_DBG_SELECT \
598 0x0500a4UL
599#define GRC_REG_DBG_DWORD_ENABLE \
600 0x0500a8UL
601#define GRC_REG_DBG_SHIFT \
602 0x0500acUL
603#define GRC_REG_DBG_FORCE_VALID \
604 0x0500b0UL
605#define GRC_REG_DBG_FORCE_FRAME \
606 0x0500b4UL
607#define UMAC_REG_DBG_SELECT \
608 0x051094UL
609#define UMAC_REG_DBG_DWORD_ENABLE \
610 0x051098UL
611#define UMAC_REG_DBG_SHIFT \
612 0x05109cUL
613#define UMAC_REG_DBG_FORCE_VALID \
614 0x0510a0UL
615#define UMAC_REG_DBG_FORCE_FRAME \
616 0x0510a4UL
617#define MCP2_REG_DBG_SELECT \
618 0x052400UL
619#define MCP2_REG_DBG_DWORD_ENABLE \
620 0x052404UL
621#define MCP2_REG_DBG_SHIFT \
622 0x052408UL
623#define MCP2_REG_DBG_FORCE_VALID \
624 0x052440UL
625#define MCP2_REG_DBG_FORCE_FRAME \
626 0x052444UL
627#define PCIE_REG_DBG_SELECT \
628 0x0547e8UL
629#define PCIE_REG_DBG_DWORD_ENABLE \
630 0x0547ecUL
631#define PCIE_REG_DBG_SHIFT \
632 0x0547f0UL
633#define PCIE_REG_DBG_FORCE_VALID \
634 0x0547f4UL
635#define PCIE_REG_DBG_FORCE_FRAME \
636 0x0547f8UL
637#define DORQ_REG_DBG_SELECT \
638 0x100ad0UL
639#define DORQ_REG_DBG_DWORD_ENABLE \
640 0x100ad4UL
641#define DORQ_REG_DBG_SHIFT \
642 0x100ad8UL
643#define DORQ_REG_DBG_FORCE_VALID \
644 0x100adcUL
645#define DORQ_REG_DBG_FORCE_FRAME \
646 0x100ae0UL
647#define IGU_REG_DBG_SELECT \
648 0x181578UL
649#define IGU_REG_DBG_DWORD_ENABLE \
650 0x18157cUL
651#define IGU_REG_DBG_SHIFT \
652 0x181580UL
653#define IGU_REG_DBG_FORCE_VALID \
654 0x181584UL
655#define IGU_REG_DBG_FORCE_FRAME \
656 0x181588UL
657#define CAU_REG_DBG_SELECT \
658 0x1c0ea8UL
659#define CAU_REG_DBG_DWORD_ENABLE \
660 0x1c0eacUL
661#define CAU_REG_DBG_SHIFT \
662 0x1c0eb0UL
663#define CAU_REG_DBG_FORCE_VALID \
664 0x1c0eb4UL
665#define CAU_REG_DBG_FORCE_FRAME \
666 0x1c0eb8UL
667#define PRS_REG_DBG_SELECT \
668 0x1f0b6cUL
669#define PRS_REG_DBG_DWORD_ENABLE \
670 0x1f0b70UL
671#define PRS_REG_DBG_SHIFT \
672 0x1f0b74UL
673#define PRS_REG_DBG_FORCE_VALID \
674 0x1f0ba0UL
675#define PRS_REG_DBG_FORCE_FRAME \
676 0x1f0ba4UL
677#define CNIG_REG_DBG_SELECT_K2 \
678 0x218254UL
679#define CNIG_REG_DBG_DWORD_ENABLE_K2 \
680 0x218258UL
681#define CNIG_REG_DBG_SHIFT_K2 \
682 0x21825cUL
683#define CNIG_REG_DBG_FORCE_VALID_K2 \
684 0x218260UL
685#define CNIG_REG_DBG_FORCE_FRAME_K2 \
686 0x218264UL
687#define PRM_REG_DBG_SELECT \
688 0x2306a8UL
689#define PRM_REG_DBG_DWORD_ENABLE \
690 0x2306acUL
691#define PRM_REG_DBG_SHIFT \
692 0x2306b0UL
693#define PRM_REG_DBG_FORCE_VALID \
694 0x2306b4UL
695#define PRM_REG_DBG_FORCE_FRAME \
696 0x2306b8UL
697#define SRC_REG_DBG_SELECT \
698 0x238700UL
699#define SRC_REG_DBG_DWORD_ENABLE \
700 0x238704UL
701#define SRC_REG_DBG_SHIFT \
702 0x238708UL
703#define SRC_REG_DBG_FORCE_VALID \
704 0x23870cUL
705#define SRC_REG_DBG_FORCE_FRAME \
706 0x238710UL
707#define RSS_REG_DBG_SELECT \
708 0x238c4cUL
709#define RSS_REG_DBG_DWORD_ENABLE \
710 0x238c50UL
711#define RSS_REG_DBG_SHIFT \
712 0x238c54UL
713#define RSS_REG_DBG_FORCE_VALID \
714 0x238c58UL
715#define RSS_REG_DBG_FORCE_FRAME \
716 0x238c5cUL
717#define RPB_REG_DBG_SELECT \
718 0x23c728UL
719#define RPB_REG_DBG_DWORD_ENABLE \
720 0x23c72cUL
721#define RPB_REG_DBG_SHIFT \
722 0x23c730UL
723#define RPB_REG_DBG_FORCE_VALID \
724 0x23c734UL
725#define RPB_REG_DBG_FORCE_FRAME \
726 0x23c738UL
727#define PSWRQ2_REG_DBG_SELECT \
728 0x240100UL
729#define PSWRQ2_REG_DBG_DWORD_ENABLE \
730 0x240104UL
731#define PSWRQ2_REG_DBG_SHIFT \
732 0x240108UL
733#define PSWRQ2_REG_DBG_FORCE_VALID \
734 0x24010cUL
735#define PSWRQ2_REG_DBG_FORCE_FRAME \
736 0x240110UL
737#define PSWRQ_REG_DBG_SELECT \
738 0x280020UL
739#define PSWRQ_REG_DBG_DWORD_ENABLE \
740 0x280024UL
741#define PSWRQ_REG_DBG_SHIFT \
742 0x280028UL
743#define PSWRQ_REG_DBG_FORCE_VALID \
744 0x28002cUL
745#define PSWRQ_REG_DBG_FORCE_FRAME \
746 0x280030UL
747#define PSWWR_REG_DBG_SELECT \
748 0x29a084UL
749#define PSWWR_REG_DBG_DWORD_ENABLE \
750 0x29a088UL
751#define PSWWR_REG_DBG_SHIFT \
752 0x29a08cUL
753#define PSWWR_REG_DBG_FORCE_VALID \
754 0x29a090UL
755#define PSWWR_REG_DBG_FORCE_FRAME \
756 0x29a094UL
757#define PSWRD_REG_DBG_SELECT \
758 0x29c040UL
759#define PSWRD_REG_DBG_DWORD_ENABLE \
760 0x29c044UL
761#define PSWRD_REG_DBG_SHIFT \
762 0x29c048UL
763#define PSWRD_REG_DBG_FORCE_VALID \
764 0x29c04cUL
765#define PSWRD_REG_DBG_FORCE_FRAME \
766 0x29c050UL
767#define PSWRD2_REG_DBG_SELECT \
768 0x29d400UL
769#define PSWRD2_REG_DBG_DWORD_ENABLE \
770 0x29d404UL
771#define PSWRD2_REG_DBG_SHIFT \
772 0x29d408UL
773#define PSWRD2_REG_DBG_FORCE_VALID \
774 0x29d40cUL
775#define PSWRD2_REG_DBG_FORCE_FRAME \
776 0x29d410UL
777#define PSWHST2_REG_DBG_SELECT \
778 0x29e058UL
779#define PSWHST2_REG_DBG_DWORD_ENABLE \
780 0x29e05cUL
781#define PSWHST2_REG_DBG_SHIFT \
782 0x29e060UL
783#define PSWHST2_REG_DBG_FORCE_VALID \
784 0x29e064UL
785#define PSWHST2_REG_DBG_FORCE_FRAME \
786 0x29e068UL
787#define PSWHST_REG_DBG_SELECT \
788 0x2a0100UL
789#define PSWHST_REG_DBG_DWORD_ENABLE \
790 0x2a0104UL
791#define PSWHST_REG_DBG_SHIFT \
792 0x2a0108UL
793#define PSWHST_REG_DBG_FORCE_VALID \
794 0x2a010cUL
795#define PSWHST_REG_DBG_FORCE_FRAME \
796 0x2a0110UL
797#define PGLUE_B_REG_DBG_SELECT \
798 0x2a8400UL
799#define PGLUE_B_REG_DBG_DWORD_ENABLE \
800 0x2a8404UL
801#define PGLUE_B_REG_DBG_SHIFT \
802 0x2a8408UL
803#define PGLUE_B_REG_DBG_FORCE_VALID \
804 0x2a840cUL
805#define PGLUE_B_REG_DBG_FORCE_FRAME \
806 0x2a8410UL
807#define TM_REG_DBG_SELECT \
808 0x2c07a8UL
809#define TM_REG_DBG_DWORD_ENABLE \
810 0x2c07acUL
811#define TM_REG_DBG_SHIFT \
812 0x2c07b0UL
813#define TM_REG_DBG_FORCE_VALID \
814 0x2c07b4UL
815#define TM_REG_DBG_FORCE_FRAME \
816 0x2c07b8UL
817#define TCFC_REG_DBG_SELECT \
818 0x2d0500UL
819#define TCFC_REG_DBG_DWORD_ENABLE \
820 0x2d0504UL
821#define TCFC_REG_DBG_SHIFT \
822 0x2d0508UL
823#define TCFC_REG_DBG_FORCE_VALID \
824 0x2d050cUL
825#define TCFC_REG_DBG_FORCE_FRAME \
826 0x2d0510UL
827#define CCFC_REG_DBG_SELECT \
828 0x2e0500UL
829#define CCFC_REG_DBG_DWORD_ENABLE \
830 0x2e0504UL
831#define CCFC_REG_DBG_SHIFT \
832 0x2e0508UL
833#define CCFC_REG_DBG_FORCE_VALID \
834 0x2e050cUL
835#define CCFC_REG_DBG_FORCE_FRAME \
836 0x2e0510UL
837#define QM_REG_DBG_SELECT \
838 0x2f2e74UL
839#define QM_REG_DBG_DWORD_ENABLE \
840 0x2f2e78UL
841#define QM_REG_DBG_SHIFT \
842 0x2f2e7cUL
843#define QM_REG_DBG_FORCE_VALID \
844 0x2f2e80UL
845#define QM_REG_DBG_FORCE_FRAME \
846 0x2f2e84UL
847#define RDIF_REG_DBG_SELECT \
848 0x300500UL
849#define RDIF_REG_DBG_DWORD_ENABLE \
850 0x300504UL
851#define RDIF_REG_DBG_SHIFT \
852 0x300508UL
853#define RDIF_REG_DBG_FORCE_VALID \
854 0x30050cUL
855#define RDIF_REG_DBG_FORCE_FRAME \
856 0x300510UL
857#define TDIF_REG_DBG_SELECT \
858 0x310500UL
859#define TDIF_REG_DBG_DWORD_ENABLE \
860 0x310504UL
861#define TDIF_REG_DBG_SHIFT \
862 0x310508UL
863#define TDIF_REG_DBG_FORCE_VALID \
864 0x31050cUL
865#define TDIF_REG_DBG_FORCE_FRAME \
866 0x310510UL
867#define BRB_REG_DBG_SELECT \
868 0x340ed0UL
869#define BRB_REG_DBG_DWORD_ENABLE \
870 0x340ed4UL
871#define BRB_REG_DBG_SHIFT \
872 0x340ed8UL
873#define BRB_REG_DBG_FORCE_VALID \
874 0x340edcUL
875#define BRB_REG_DBG_FORCE_FRAME \
876 0x340ee0UL
877#define XYLD_REG_DBG_SELECT \
878 0x4c1600UL
879#define XYLD_REG_DBG_DWORD_ENABLE \
880 0x4c1604UL
881#define XYLD_REG_DBG_SHIFT \
882 0x4c1608UL
883#define XYLD_REG_DBG_FORCE_VALID \
884 0x4c160cUL
885#define XYLD_REG_DBG_FORCE_FRAME \
886 0x4c1610UL
887#define YULD_REG_DBG_SELECT \
888 0x4c9600UL
889#define YULD_REG_DBG_DWORD_ENABLE \
890 0x4c9604UL
891#define YULD_REG_DBG_SHIFT \
892 0x4c9608UL
893#define YULD_REG_DBG_FORCE_VALID \
894 0x4c960cUL
895#define YULD_REG_DBG_FORCE_FRAME \
896 0x4c9610UL
897#define TMLD_REG_DBG_SELECT \
898 0x4d1600UL
899#define TMLD_REG_DBG_DWORD_ENABLE \
900 0x4d1604UL
901#define TMLD_REG_DBG_SHIFT \
902 0x4d1608UL
903#define TMLD_REG_DBG_FORCE_VALID \
904 0x4d160cUL
905#define TMLD_REG_DBG_FORCE_FRAME \
906 0x4d1610UL
907#define MULD_REG_DBG_SELECT \
908 0x4e1600UL
909#define MULD_REG_DBG_DWORD_ENABLE \
910 0x4e1604UL
911#define MULD_REG_DBG_SHIFT \
912 0x4e1608UL
913#define MULD_REG_DBG_FORCE_VALID \
914 0x4e160cUL
915#define MULD_REG_DBG_FORCE_FRAME \
916 0x4e1610UL
917#define NIG_REG_DBG_SELECT \
918 0x502140UL
919#define NIG_REG_DBG_DWORD_ENABLE \
920 0x502144UL
921#define NIG_REG_DBG_SHIFT \
922 0x502148UL
923#define NIG_REG_DBG_FORCE_VALID \
924 0x50214cUL
925#define NIG_REG_DBG_FORCE_FRAME \
926 0x502150UL
927#define BMB_REG_DBG_SELECT \
928 0x540a7cUL
929#define BMB_REG_DBG_DWORD_ENABLE \
930 0x540a80UL
931#define BMB_REG_DBG_SHIFT \
932 0x540a84UL
933#define BMB_REG_DBG_FORCE_VALID \
934 0x540a88UL
935#define BMB_REG_DBG_FORCE_FRAME \
936 0x540a8cUL
937#define PTU_REG_DBG_SELECT \
938 0x560100UL
939#define PTU_REG_DBG_DWORD_ENABLE \
940 0x560104UL
941#define PTU_REG_DBG_SHIFT \
942 0x560108UL
943#define PTU_REG_DBG_FORCE_VALID \
944 0x56010cUL
945#define PTU_REG_DBG_FORCE_FRAME \
946 0x560110UL
947#define CDU_REG_DBG_SELECT \
948 0x580704UL
949#define CDU_REG_DBG_DWORD_ENABLE \
950 0x580708UL
951#define CDU_REG_DBG_SHIFT \
952 0x58070cUL
953#define CDU_REG_DBG_FORCE_VALID \
954 0x580710UL
955#define CDU_REG_DBG_FORCE_FRAME \
956 0x580714UL
957#define WOL_REG_DBG_SELECT \
958 0x600140UL
959#define WOL_REG_DBG_DWORD_ENABLE \
960 0x600144UL
961#define WOL_REG_DBG_SHIFT \
962 0x600148UL
963#define WOL_REG_DBG_FORCE_VALID \
964 0x60014cUL
965#define WOL_REG_DBG_FORCE_FRAME \
966 0x600150UL
967#define BMBN_REG_DBG_SELECT \
968 0x610140UL
969#define BMBN_REG_DBG_DWORD_ENABLE \
970 0x610144UL
971#define BMBN_REG_DBG_SHIFT \
972 0x610148UL
973#define BMBN_REG_DBG_FORCE_VALID \
974 0x61014cUL
975#define BMBN_REG_DBG_FORCE_FRAME \
976 0x610150UL
977#define NWM_REG_DBG_SELECT \
978 0x8000ecUL
979#define NWM_REG_DBG_DWORD_ENABLE \
980 0x8000f0UL
981#define NWM_REG_DBG_SHIFT \
982 0x8000f4UL
983#define NWM_REG_DBG_FORCE_VALID \
984 0x8000f8UL
985#define NWM_REG_DBG_FORCE_FRAME \
986 0x8000fcUL
987#define PBF_REG_DBG_SELECT \
988 0xd80060UL
989#define PBF_REG_DBG_DWORD_ENABLE \
990 0xd80064UL
991#define PBF_REG_DBG_SHIFT \
992 0xd80068UL
993#define PBF_REG_DBG_FORCE_VALID \
994 0xd8006cUL
995#define PBF_REG_DBG_FORCE_FRAME \
996 0xd80070UL
997#define PBF_PB1_REG_DBG_SELECT \
998 0xda0728UL
999#define PBF_PB1_REG_DBG_DWORD_ENABLE \
1000 0xda072cUL
1001#define PBF_PB1_REG_DBG_SHIFT \
1002 0xda0730UL
1003#define PBF_PB1_REG_DBG_FORCE_VALID \
1004 0xda0734UL
1005#define PBF_PB1_REG_DBG_FORCE_FRAME \
1006 0xda0738UL
1007#define PBF_PB2_REG_DBG_SELECT \
1008 0xda4728UL
1009#define PBF_PB2_REG_DBG_DWORD_ENABLE \
1010 0xda472cUL
1011#define PBF_PB2_REG_DBG_SHIFT \
1012 0xda4730UL
1013#define PBF_PB2_REG_DBG_FORCE_VALID \
1014 0xda4734UL
1015#define PBF_PB2_REG_DBG_FORCE_FRAME \
1016 0xda4738UL
1017#define BTB_REG_DBG_SELECT \
1018 0xdb08c8UL
1019#define BTB_REG_DBG_DWORD_ENABLE \
1020 0xdb08ccUL
1021#define BTB_REG_DBG_SHIFT \
1022 0xdb08d0UL
1023#define BTB_REG_DBG_FORCE_VALID \
1024 0xdb08d4UL
1025#define BTB_REG_DBG_FORCE_FRAME \
1026 0xdb08d8UL
1027#define XSDM_REG_DBG_SELECT \
1028 0xf80e28UL
1029#define XSDM_REG_DBG_DWORD_ENABLE \
1030 0xf80e2cUL
1031#define XSDM_REG_DBG_SHIFT \
1032 0xf80e30UL
1033#define XSDM_REG_DBG_FORCE_VALID \
1034 0xf80e34UL
1035#define XSDM_REG_DBG_FORCE_FRAME \
1036 0xf80e38UL
1037#define YSDM_REG_DBG_SELECT \
1038 0xf90e28UL
1039#define YSDM_REG_DBG_DWORD_ENABLE \
1040 0xf90e2cUL
1041#define YSDM_REG_DBG_SHIFT \
1042 0xf90e30UL
1043#define YSDM_REG_DBG_FORCE_VALID \
1044 0xf90e34UL
1045#define YSDM_REG_DBG_FORCE_FRAME \
1046 0xf90e38UL
1047#define PSDM_REG_DBG_SELECT \
1048 0xfa0e28UL
1049#define PSDM_REG_DBG_DWORD_ENABLE \
1050 0xfa0e2cUL
1051#define PSDM_REG_DBG_SHIFT \
1052 0xfa0e30UL
1053#define PSDM_REG_DBG_FORCE_VALID \
1054 0xfa0e34UL
1055#define PSDM_REG_DBG_FORCE_FRAME \
1056 0xfa0e38UL
1057#define TSDM_REG_DBG_SELECT \
1058 0xfb0e28UL
1059#define TSDM_REG_DBG_DWORD_ENABLE \
1060 0xfb0e2cUL
1061#define TSDM_REG_DBG_SHIFT \
1062 0xfb0e30UL
1063#define TSDM_REG_DBG_FORCE_VALID \
1064 0xfb0e34UL
1065#define TSDM_REG_DBG_FORCE_FRAME \
1066 0xfb0e38UL
1067#define MSDM_REG_DBG_SELECT \
1068 0xfc0e28UL
1069#define MSDM_REG_DBG_DWORD_ENABLE \
1070 0xfc0e2cUL
1071#define MSDM_REG_DBG_SHIFT \
1072 0xfc0e30UL
1073#define MSDM_REG_DBG_FORCE_VALID \
1074 0xfc0e34UL
1075#define MSDM_REG_DBG_FORCE_FRAME \
1076 0xfc0e38UL
1077#define USDM_REG_DBG_SELECT \
1078 0xfd0e28UL
1079#define USDM_REG_DBG_DWORD_ENABLE \
1080 0xfd0e2cUL
1081#define USDM_REG_DBG_SHIFT \
1082 0xfd0e30UL
1083#define USDM_REG_DBG_FORCE_VALID \
1084 0xfd0e34UL
1085#define USDM_REG_DBG_FORCE_FRAME \
1086 0xfd0e38UL
1087#define XCM_REG_DBG_SELECT \
1088 0x1000040UL
1089#define XCM_REG_DBG_DWORD_ENABLE \
1090 0x1000044UL
1091#define XCM_REG_DBG_SHIFT \
1092 0x1000048UL
1093#define XCM_REG_DBG_FORCE_VALID \
1094 0x100004cUL
1095#define XCM_REG_DBG_FORCE_FRAME \
1096 0x1000050UL
1097#define YCM_REG_DBG_SELECT \
1098 0x1080040UL
1099#define YCM_REG_DBG_DWORD_ENABLE \
1100 0x1080044UL
1101#define YCM_REG_DBG_SHIFT \
1102 0x1080048UL
1103#define YCM_REG_DBG_FORCE_VALID \
1104 0x108004cUL
1105#define YCM_REG_DBG_FORCE_FRAME \
1106 0x1080050UL
1107#define PCM_REG_DBG_SELECT \
1108 0x1100040UL
1109#define PCM_REG_DBG_DWORD_ENABLE \
1110 0x1100044UL
1111#define PCM_REG_DBG_SHIFT \
1112 0x1100048UL
1113#define PCM_REG_DBG_FORCE_VALID \
1114 0x110004cUL
1115#define PCM_REG_DBG_FORCE_FRAME \
1116 0x1100050UL
1117#define TCM_REG_DBG_SELECT \
1118 0x1180040UL
1119#define TCM_REG_DBG_DWORD_ENABLE \
1120 0x1180044UL
1121#define TCM_REG_DBG_SHIFT \
1122 0x1180048UL
1123#define TCM_REG_DBG_FORCE_VALID \
1124 0x118004cUL
1125#define TCM_REG_DBG_FORCE_FRAME \
1126 0x1180050UL
1127#define MCM_REG_DBG_SELECT \
1128 0x1200040UL
1129#define MCM_REG_DBG_DWORD_ENABLE \
1130 0x1200044UL
1131#define MCM_REG_DBG_SHIFT \
1132 0x1200048UL
1133#define MCM_REG_DBG_FORCE_VALID \
1134 0x120004cUL
1135#define MCM_REG_DBG_FORCE_FRAME \
1136 0x1200050UL
1137#define UCM_REG_DBG_SELECT \
1138 0x1280050UL
1139#define UCM_REG_DBG_DWORD_ENABLE \
1140 0x1280054UL
1141#define UCM_REG_DBG_SHIFT \
1142 0x1280058UL
1143#define UCM_REG_DBG_FORCE_VALID \
1144 0x128005cUL
1145#define UCM_REG_DBG_FORCE_FRAME \
1146 0x1280060UL
1147#define XSEM_REG_DBG_SELECT \
1148 0x1401528UL
1149#define XSEM_REG_DBG_DWORD_ENABLE \
1150 0x140152cUL
1151#define XSEM_REG_DBG_SHIFT \
1152 0x1401530UL
1153#define XSEM_REG_DBG_FORCE_VALID \
1154 0x1401534UL
1155#define XSEM_REG_DBG_FORCE_FRAME \
1156 0x1401538UL
1157#define YSEM_REG_DBG_SELECT \
1158 0x1501528UL
1159#define YSEM_REG_DBG_DWORD_ENABLE \
1160 0x150152cUL
1161#define YSEM_REG_DBG_SHIFT \
1162 0x1501530UL
1163#define YSEM_REG_DBG_FORCE_VALID \
1164 0x1501534UL
1165#define YSEM_REG_DBG_FORCE_FRAME \
1166 0x1501538UL
1167#define PSEM_REG_DBG_SELECT \
1168 0x1601528UL
1169#define PSEM_REG_DBG_DWORD_ENABLE \
1170 0x160152cUL
1171#define PSEM_REG_DBG_SHIFT \
1172 0x1601530UL
1173#define PSEM_REG_DBG_FORCE_VALID \
1174 0x1601534UL
1175#define PSEM_REG_DBG_FORCE_FRAME \
1176 0x1601538UL
1177#define TSEM_REG_DBG_SELECT \
1178 0x1701528UL
1179#define TSEM_REG_DBG_DWORD_ENABLE \
1180 0x170152cUL
1181#define TSEM_REG_DBG_SHIFT \
1182 0x1701530UL
1183#define TSEM_REG_DBG_FORCE_VALID \
1184 0x1701534UL
1185#define TSEM_REG_DBG_FORCE_FRAME \
1186 0x1701538UL
1187#define MSEM_REG_DBG_SELECT \
1188 0x1801528UL
1189#define MSEM_REG_DBG_DWORD_ENABLE \
1190 0x180152cUL
1191#define MSEM_REG_DBG_SHIFT \
1192 0x1801530UL
1193#define MSEM_REG_DBG_FORCE_VALID \
1194 0x1801534UL
1195#define MSEM_REG_DBG_FORCE_FRAME \
1196 0x1801538UL
1197#define USEM_REG_DBG_SELECT \
1198 0x1901528UL
1199#define USEM_REG_DBG_DWORD_ENABLE \
1200 0x190152cUL
1201#define USEM_REG_DBG_SHIFT \
1202 0x1901530UL
1203#define USEM_REG_DBG_FORCE_VALID \
1204 0x1901534UL
1205#define USEM_REG_DBG_FORCE_FRAME \
1206 0x1901538UL
1207#define PCIE_REG_DBG_COMMON_SELECT \
1208 0x054398UL
1209#define PCIE_REG_DBG_COMMON_DWORD_ENABLE \
1210 0x05439cUL
1211#define PCIE_REG_DBG_COMMON_SHIFT \
1212 0x0543a0UL
1213#define PCIE_REG_DBG_COMMON_FORCE_VALID \
1214 0x0543a4UL
1215#define PCIE_REG_DBG_COMMON_FORCE_FRAME \
1216 0x0543a8UL
1217#define MISC_REG_RESET_PL_UA \
1218 0x008050UL
1219#define MISC_REG_RESET_PL_HV \
1220 0x008060UL
1221#define XCM_REG_CTX_RBC_ACCS \
1222 0x1001800UL
1223#define XCM_REG_AGG_CON_CTX \
1224 0x1001804UL
1225#define XCM_REG_SM_CON_CTX \
1226 0x1001808UL
1227#define YCM_REG_CTX_RBC_ACCS \
1228 0x1081800UL
1229#define YCM_REG_AGG_CON_CTX \
1230 0x1081804UL
1231#define YCM_REG_AGG_TASK_CTX \
1232 0x1081808UL
1233#define YCM_REG_SM_CON_CTX \
1234 0x108180cUL
1235#define YCM_REG_SM_TASK_CTX \
1236 0x1081810UL
1237#define PCM_REG_CTX_RBC_ACCS \
1238 0x1101440UL
1239#define PCM_REG_SM_CON_CTX \
1240 0x1101444UL
1241#define TCM_REG_CTX_RBC_ACCS \
1242 0x11814c0UL
1243#define TCM_REG_AGG_CON_CTX \
1244 0x11814c4UL
1245#define TCM_REG_AGG_TASK_CTX \
1246 0x11814c8UL
1247#define TCM_REG_SM_CON_CTX \
1248 0x11814ccUL
1249#define TCM_REG_SM_TASK_CTX \
1250 0x11814d0UL
1251#define MCM_REG_CTX_RBC_ACCS \
1252 0x1201800UL
1253#define MCM_REG_AGG_CON_CTX \
1254 0x1201804UL
1255#define MCM_REG_AGG_TASK_CTX \
1256 0x1201808UL
1257#define MCM_REG_SM_CON_CTX \
1258 0x120180cUL
1259#define MCM_REG_SM_TASK_CTX \
1260 0x1201810UL
1261#define UCM_REG_CTX_RBC_ACCS \
1262 0x1281700UL
1263#define UCM_REG_AGG_CON_CTX \
1264 0x1281704UL
1265#define UCM_REG_AGG_TASK_CTX \
1266 0x1281708UL
1267#define UCM_REG_SM_CON_CTX \
1268 0x128170cUL
1269#define UCM_REG_SM_TASK_CTX \
1270 0x1281710UL
1271#define XSEM_REG_SLOW_DBG_EMPTY \
1272 0x1401140UL
1273#define XSEM_REG_SYNC_DBG_EMPTY \
1274 0x1401160UL
1275#define XSEM_REG_SLOW_DBG_ACTIVE \
1276 0x1401400UL
1277#define XSEM_REG_SLOW_DBG_MODE \
1278 0x1401404UL
1279#define XSEM_REG_DBG_FRAME_MODE \
1280 0x1401408UL
1281#define XSEM_REG_DBG_MODE1_CFG \
1282 0x1401420UL
1283#define XSEM_REG_FAST_MEMORY \
1284 0x1440000UL
1285#define YSEM_REG_SYNC_DBG_EMPTY \
1286 0x1501160UL
1287#define YSEM_REG_SLOW_DBG_ACTIVE \
1288 0x1501400UL
1289#define YSEM_REG_SLOW_DBG_MODE \
1290 0x1501404UL
1291#define YSEM_REG_DBG_FRAME_MODE \
1292 0x1501408UL
1293#define YSEM_REG_DBG_MODE1_CFG \
1294 0x1501420UL
1295#define YSEM_REG_FAST_MEMORY \
1296 0x1540000UL
1297#define PSEM_REG_SLOW_DBG_EMPTY \
1298 0x1601140UL
1299#define PSEM_REG_SYNC_DBG_EMPTY \
1300 0x1601160UL
1301#define PSEM_REG_SLOW_DBG_ACTIVE \
1302 0x1601400UL
1303#define PSEM_REG_SLOW_DBG_MODE \
1304 0x1601404UL
1305#define PSEM_REG_DBG_FRAME_MODE \
1306 0x1601408UL
1307#define PSEM_REG_DBG_MODE1_CFG \
1308 0x1601420UL
1309#define PSEM_REG_FAST_MEMORY \
1310 0x1640000UL
1311#define TSEM_REG_SLOW_DBG_EMPTY \
1312 0x1701140UL
1313#define TSEM_REG_SYNC_DBG_EMPTY \
1314 0x1701160UL
1315#define TSEM_REG_SLOW_DBG_ACTIVE \
1316 0x1701400UL
1317#define TSEM_REG_SLOW_DBG_MODE \
1318 0x1701404UL
1319#define TSEM_REG_DBG_FRAME_MODE \
1320 0x1701408UL
1321#define TSEM_REG_DBG_MODE1_CFG \
1322 0x1701420UL
1323#define TSEM_REG_FAST_MEMORY \
1324 0x1740000UL
1325#define MSEM_REG_SLOW_DBG_EMPTY \
1326 0x1801140UL
1327#define MSEM_REG_SYNC_DBG_EMPTY \
1328 0x1801160UL
1329#define MSEM_REG_SLOW_DBG_ACTIVE \
1330 0x1801400UL
1331#define MSEM_REG_SLOW_DBG_MODE \
1332 0x1801404UL
1333#define MSEM_REG_DBG_FRAME_MODE \
1334 0x1801408UL
1335#define MSEM_REG_DBG_MODE1_CFG \
1336 0x1801420UL
1337#define MSEM_REG_FAST_MEMORY \
1338 0x1840000UL
1339#define USEM_REG_SLOW_DBG_EMPTY \
1340 0x1901140UL
1341#define USEM_REG_SYNC_DBG_EMPTY \
1342 0x1901160UL
1343#define USEM_REG_SLOW_DBG_ACTIVE \
1344 0x1901400UL
1345#define USEM_REG_SLOW_DBG_MODE \
1346 0x1901404UL
1347#define USEM_REG_DBG_FRAME_MODE \
1348 0x1901408UL
1349#define USEM_REG_DBG_MODE1_CFG \
1350 0x1901420UL
1351#define USEM_REG_FAST_MEMORY \
1352 0x1940000UL
1353#define SEM_FAST_REG_INT_RAM \
1354 0x020000UL
1355#define SEM_FAST_REG_INT_RAM_SIZE \
1356 20480
1357#define GRC_REG_TRACE_FIFO_VALID_DATA \
1358 0x050064UL
1359#define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW \
1360 0x05040cUL
1361#define GRC_REG_PROTECTION_OVERRIDE_WINDOW \
1362 0x050500UL
1363#define IGU_REG_ERROR_HANDLING_MEMORY \
1364 0x181520UL
1365#define MCP_REG_CPU_MODE \
1366 0xe05000UL
1367#define MCP_REG_CPU_MODE_SOFT_HALT \
1368 (0x1 << 10)
1369#define BRB_REG_BIG_RAM_ADDRESS \
1370 0x340800UL
1371#define BRB_REG_BIG_RAM_DATA \
1372 0x341500UL
1373#define SEM_FAST_REG_STALL_0 \
1374 0x000488UL
1375#define SEM_FAST_REG_STALLED \
1376 0x000494UL
1377#define BTB_REG_BIG_RAM_ADDRESS \
1378 0xdb0800UL
1379#define BTB_REG_BIG_RAM_DATA \
1380 0xdb0c00UL
1381#define BMB_REG_BIG_RAM_ADDRESS \
1382 0x540800UL
1383#define BMB_REG_BIG_RAM_DATA \
1384 0x540f00UL
1385#define SEM_FAST_REG_STORM_REG_FILE \
1386 0x008000UL
1387#define RSS_REG_RSS_RAM_ADDR \
1388 0x238c30UL
1389#define MISCS_REG_BLOCK_256B_EN \
1390 0x009074UL
1391#define MCP_REG_SCRATCH_SIZE \
1392 57344
1393#define MCP_REG_CPU_REG_FILE \
1394 0xe05200UL
1395#define MCP_REG_CPU_REG_FILE_SIZE \
1396 32
1397#define DBG_REG_DEBUG_TARGET \
1398 0x01005cUL
1399#define DBG_REG_FULL_MODE \
1400 0x010060UL
1401#define DBG_REG_CALENDAR_OUT_DATA \
1402 0x010480UL
1403#define GRC_REG_TRACE_FIFO \
1404 0x050068UL
1405#define IGU_REG_ERROR_HANDLING_DATA_VALID \
1406 0x181530UL
1407#define DBG_REG_DBG_BLOCK_ON \
1408 0x010454UL
1409#define DBG_REG_FRAMING_MODE \
1410 0x010058UL
1411#define SEM_FAST_REG_VFC_DATA_WR \
1412 0x000b40UL
1413#define SEM_FAST_REG_VFC_ADDR \
1414 0x000b44UL
1415#define SEM_FAST_REG_VFC_DATA_RD \
1416 0x000b48UL
1417#define RSS_REG_RSS_RAM_DATA \
1418 0x238c20UL
1419#define MISC_REG_BLOCK_256B_EN \
1420 0x008c14UL
1421#define NWS_REG_NWS_CMU \
1422 0x720000UL
1423#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0 \
1424 0x000680UL
1425#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8 \
1426 0x000684UL
1427#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0 \
1428 0x0006c0UL
1429#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8 \
1430 0x0006c4UL
1431#define MS_REG_MS_CMU \
1432 0x6a4000UL
1433#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130 \
1434 0x000208UL
1435#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132 \
1436 0x000210UL
1437#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131 \
1438 0x00020cUL
1439#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133 \
1440 0x000214UL
1441#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130 \
1442 0x000208UL
1443#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131 \
1444 0x00020cUL
1445#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132 \
1446 0x000210UL
1447#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133 \
1448 0x000214UL
1449#define PHY_PCIE_REG_PHY0 \
1450 0x620000UL
1451#define PHY_PCIE_REG_PHY1 \
1452 0x624000UL
1453#define NIG_REG_ROCE_DUPLICATE_TO_HOST 0x5088f0UL
1454#define PRS_REG_LIGHT_L2_ETHERTYPE_EN 0x1f0968UL
1455#define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL
1456#define DORQ_REG_PF_DPM_ENABLE 0x100510UL
1457#define DORQ_REG_PF_ICID_BIT_SHIFT_NORM 0x100448UL
1458#define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL
1459#define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL
1460#endif