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1/* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef REG_ADDR_H
34#define REG_ADDR_H
35
36#define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \
37 0
38
39#define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \
40 0xfff << 0)
41
42#define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \
43 12
44
45#define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \
46 0xfff << 12)
47
48#define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \
49 24
50
51#define CDU_REG_CID_ADDR_PARAMS_NCIB ( \
52 0xff << 24)
53
54#define CDU_REG_SEGMENT0_PARAMS \
55 0x580904UL
56#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK \
57 (0xfff << 0)
58#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT \
59 0
60#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE \
61 (0xff << 16)
62#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT \
63 16
64#define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE \
65 (0xff << 24)
66#define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT \
67 24
68#define CDU_REG_SEGMENT1_PARAMS \
69 0x580908UL
70#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK \
71 (0xfff << 0)
72#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT \
73 0
74#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE \
75 (0xff << 16)
76#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT \
77 16
78#define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE \
79 (0xff << 24)
80#define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT \
81 24
82
83#define XSDM_REG_OPERATION_GEN \
84 0xf80408UL
85#define NIG_REG_RX_BRB_OUT_EN \
86 0x500e18UL
87#define NIG_REG_STORM_OUT_EN \
88 0x500e08UL
89#define PSWRQ2_REG_L2P_VALIDATE_VFID \
90 0x240c50UL
91#define PGLUE_B_REG_USE_CLIENTID_IN_TAG \
92 0x2aae04UL
93#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \
94 0x2aa16cUL
95#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \
96 0x2aa118UL
97#define PSWHST_REG_ZONE_PERMISSION_TABLE \
98 0x2a0800UL
99#define BAR0_MAP_REG_MSDM_RAM \
100 0x1d00000UL
101#define BAR0_MAP_REG_USDM_RAM \
102 0x1d80000UL
103#define BAR0_MAP_REG_PSDM_RAM \
104 0x1f00000UL
105#define BAR0_MAP_REG_TSDM_RAM \
106 0x1c80000UL
107#define BAR0_MAP_REG_XSDM_RAM \
108 0x1e00000UL
109#define BAR0_MAP_REG_YSDM_RAM \
110 0x1e80000UL
111#define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \
112 0x5011f4UL
113#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE \
114 0x1f0164UL
115#define PRS_REG_SEARCH_TCP \
116 0x1f0400UL
117#define PRS_REG_SEARCH_UDP \
118 0x1f0404UL
119#define PRS_REG_SEARCH_FCOE \
120 0x1f0408UL
121#define PRS_REG_SEARCH_ROCE \
122 0x1f040cUL
123#define PRS_REG_SEARCH_OPENFLOW \
124 0x1f0434UL
125#define PRS_REG_SEARCH_TAG1 \
126 0x1f0444UL
127#define PRS_REG_SEARCH_TENANT_ID \
128 0x1f044cUL
129#define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST \
130 0x1f0a0cUL
131#define PRS_REG_SEARCH_TCP_FIRST_FRAG \
132 0x1f0410UL
133#define TM_REG_PF_ENABLE_CONN \
134 0x2c043cUL
135#define TM_REG_PF_ENABLE_TASK \
136 0x2c0444UL
137#define TM_REG_PF_SCAN_ACTIVE_CONN \
138 0x2c04fcUL
139#define TM_REG_PF_SCAN_ACTIVE_TASK \
140 0x2c0500UL
141#define IGU_REG_LEADING_EDGE_LATCH \
142 0x18082cUL
143#define IGU_REG_TRAILING_EDGE_LATCH \
144 0x180830UL
145#define QM_REG_USG_CNT_PF_TX \
146 0x2f2eacUL
147#define QM_REG_USG_CNT_PF_OTHER \
148 0x2f2eb0UL
149#define DORQ_REG_PF_DB_ENABLE \
150 0x100508UL
151#define DORQ_REG_VF_USAGE_CNT \
152 0x1009c4UL
153#define QM_REG_PF_EN \
154 0x2f2ea4UL
155#define TCFC_REG_WEAK_ENABLE_VF \
156 0x2d0704UL
157#define TCFC_REG_STRONG_ENABLE_PF \
158 0x2d0708UL
159#define TCFC_REG_STRONG_ENABLE_VF \
160 0x2d070cUL
161#define CCFC_REG_WEAK_ENABLE_VF \
162 0x2e0704UL
163#define CCFC_REG_STRONG_ENABLE_PF \
164 0x2e0708UL
165#define PGLUE_B_REG_PGL_ADDR_88_F0_BB \
166 0x2aa404UL
167#define PGLUE_B_REG_PGL_ADDR_8C_F0_BB \
168 0x2aa408UL
169#define PGLUE_B_REG_PGL_ADDR_90_F0_BB \
170 0x2aa40cUL
171#define PGLUE_B_REG_PGL_ADDR_94_F0_BB \
172 0x2aa410UL
173#define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \
174 0x2aa138UL
175#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
176 0x2aa174UL
177#define MISC_REG_GEN_PURP_CR0 \
178 0x008c80UL
179#define MCP_REG_SCRATCH \
180 0xe20000UL
181#define CNIG_REG_NW_PORT_MODE_BB \
182 0x218200UL
183#define MISCS_REG_CHIP_NUM \
184 0x00976cUL
185#define MISCS_REG_CHIP_REV \
186 0x009770UL
187#define MISCS_REG_CMT_ENABLED_FOR_PAIR \
188 0x00971cUL
189#define MISCS_REG_CHIP_TEST_REG \
190 0x009778UL
191#define MISCS_REG_CHIP_METAL \
192 0x009774UL
193#define MISCS_REG_FUNCTION_HIDE \
194 0x0096f0UL
195#define BRB_REG_HEADER_SIZE \
196 0x340804UL
197#define BTB_REG_HEADER_SIZE \
198 0xdb0804UL
199#define CAU_REG_LONG_TIMEOUT_THRESHOLD \
200 0x1c0708UL
201#define CCFC_REG_ACTIVITY_COUNTER \
202 0x2e8800UL
203#define CCFC_REG_STRONG_ENABLE_VF \
204 0x2e070cUL
205#define CDU_REG_CCFC_CTX_VALID0 \
206 0x580400UL
207#define CDU_REG_CCFC_CTX_VALID1 \
208 0x580404UL
209#define CDU_REG_TCFC_CTX_VALID0 \
210 0x580408UL
211#define CDU_REG_CID_ADDR_PARAMS \
212 0x580900UL
213#define DBG_REG_CLIENT_ENABLE \
214 0x010004UL
215#define DMAE_REG_INIT \
216 0x00c000UL
217#define DORQ_REG_IFEN \
218 0x100040UL
219#define DORQ_REG_TAG1_OVRD_MODE \
220 0x1008b4UL
221#define DORQ_REG_PF_PCP_BB_K2 \
222 0x1008c4UL
223#define DORQ_REG_PF_EXT_VID_BB_K2 \
224 0x1008c8UL
225#define DORQ_REG_DB_DROP_REASON \
226 0x100a2cUL
227#define DORQ_REG_DB_DROP_DETAILS \
228 0x100a24UL
229#define DORQ_REG_DB_DROP_DETAILS_ADDRESS \
230 0x100a1cUL
231#define GRC_REG_TIMEOUT_EN \
232 0x050404UL
233#define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \
234 0x050054UL
235#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \
236 0x05004cUL
237#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \
238 0x050050UL
239#define IGU_REG_BLOCK_CONFIGURATION \
240 0x180040UL
241#define MCM_REG_INIT \
242 0x1200000UL
243#define MCP2_REG_DBG_DWORD_ENABLE \
244 0x052404UL
245#define MISC_REG_PORT_MODE \
246 0x008c00UL
247#define MISCS_REG_CLK_100G_MODE \
248 0x009070UL
249#define MSDM_REG_ENABLE_IN1 \
250 0xfc0004UL
251#define MSEM_REG_ENABLE_IN \
252 0x1800004UL
253#define NIG_REG_CM_HDR \
254 0x500840UL
255#define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR \
256 0x50196cUL
257#define NIG_REG_LLH_PPFID2PFID_TBL_0 \
258 0x501970UL
259#define NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL \
260 0x50
261#define NIG_REG_LLH_CLS_TYPE_DUALMODE \
262 0x501964UL
263#define NIG_REG_LLH_FUNC_TAG_EN 0x5019b0UL
264#define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL
265#define NIG_REG_LLH_FUNC_FILTER_VALUE \
266 0x501a00UL
267#define NIG_REG_LLH_FUNC_FILTER_VALUE_SIZE \
268 32
269#define NIG_REG_LLH_FUNC_FILTER_EN \
270 0x501a80UL
271#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE \
272 16
273#define NIG_REG_LLH_FUNC_FILTER_MODE \
274 0x501ac0UL
275#define NIG_REG_LLH_FUNC_FILTER_MODE_SIZE \
276 16
277#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE \
278 0x501b00UL
279#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_SIZE \
280 16
281#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL \
282 0x501b40UL
283#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_SIZE \
284 16
285#define NCSI_REG_CONFIG \
286 0x040200UL
287#define PBF_REG_INIT \
288 0xd80000UL
289#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 \
290 0xd806c8UL
291#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 \
292 0xd806ccUL
293#define PTU_REG_ATC_INIT_ARRAY \
294 0x560000UL
295#define PCM_REG_INIT \
296 0x1100000UL
297#define PGLUE_B_REG_ADMIN_PER_PF_REGION \
298 0x2a9000UL
299#define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \
300 0x2aa150UL
301#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \
302 0x2aa144UL
303#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \
304 0x2aa148UL
305#define PGLUE_B_REG_TX_ERR_WR_DETAILS \
306 0x2aa14cUL
307#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \
308 0x2aa154UL
309#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \
310 0x2aa158UL
311#define PGLUE_B_REG_TX_ERR_RD_DETAILS \
312 0x2aa15cUL
313#define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \
314 0x2aa160UL
315#define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \
316 0x2aa164UL
317#define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \
318 0x2aa54cUL
319#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \
320 0x2aa544UL
321#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \
322 0x2aa548UL
323#define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \
324 0x2aae74UL
325#define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \
326 0x2aae78UL
327#define PGLUE_B_REG_VF_ILT_ERR_DETAILS \
328 0x2aae7cUL
329#define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \
330 0x2aae80UL
331#define PGLUE_B_REG_LATCHED_ERRORS_CLR \
332 0x2aa3bcUL
333#define PRM_REG_DISABLE_PRM \
334 0x230000UL
335#define PRS_REG_SOFT_RST \
336 0x1f0000UL
337#define PRS_REG_MSG_INFO \
338 0x1f0a1cUL
339#define PRS_REG_ROCE_DEST_QP_MAX_PF \
340 0x1f0430UL
341#define PRS_REG_USE_LIGHT_L2 \
342 0x1f096cUL
343#define PSDM_REG_ENABLE_IN1 \
344 0xfa0004UL
345#define PSEM_REG_ENABLE_IN \
346 0x1600004UL
347#define PSWRQ_REG_DBG_SELECT \
348 0x280020UL
349#define PSWRQ2_REG_CDUT_P_SIZE \
350 0x24000cUL
351#define PSWRQ2_REG_ILT_MEMORY \
352 0x260000UL
353#define PSWHST_REG_DISCARD_INTERNAL_WRITES \
354 0x2a0040UL
355#define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
356 0x29e050UL
357#define PSWHST_REG_INCORRECT_ACCESS_VALID \
358 0x2a0070UL
359#define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \
360 0x2a0074UL
361#define PSWHST_REG_INCORRECT_ACCESS_DATA \
362 0x2a0068UL
363#define PSWHST_REG_INCORRECT_ACCESS_LENGTH \
364 0x2a006cUL
365#define PSWRD_REG_DBG_SELECT \
366 0x29c040UL
367#define PSWRD2_REG_CONF11 \
368 0x29d064UL
369#define PSWWR_REG_USDM_FULL_TH \
370 0x29a040UL
371#define PSWWR2_REG_CDU_FULL_TH2 \
372 0x29b040UL
373#define QM_REG_MAXPQSIZE_0 \
374 0x2f0434UL
375#define RSS_REG_RSS_INIT_EN \
376 0x238804UL
377#define RDIF_REG_STOP_ON_ERROR \
378 0x300040UL
379#define RDIF_REG_DEBUG_ERROR_INFO \
380 0x300400UL
381#define RDIF_REG_DEBUG_ERROR_INFO_SIZE \
382 64
383#define SRC_REG_SOFT_RST \
384 0x23874cUL
385#define TCFC_REG_ACTIVITY_COUNTER \
386 0x2d8800UL
387#define TCM_REG_INIT \
388 0x1180000UL
389#define TM_REG_PXP_READ_DATA_FIFO_INIT \
390 0x2c0014UL
391#define TSDM_REG_ENABLE_IN1 \
392 0xfb0004UL
393#define TSEM_REG_ENABLE_IN \
394 0x1700004UL
395#define TDIF_REG_STOP_ON_ERROR \
396 0x310040UL
397#define TDIF_REG_DEBUG_ERROR_INFO \
398 0x310400UL
399#define TDIF_REG_DEBUG_ERROR_INFO_SIZE \
400 64
401#define UCM_REG_INIT \
402 0x1280000UL
403#define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \
404 0x051004UL
405#define USDM_REG_ENABLE_IN1 \
406 0xfd0004UL
407#define USEM_REG_ENABLE_IN \
408 0x1900004UL
409#define XCM_REG_INIT \
410 0x1000000UL
411#define XSDM_REG_ENABLE_IN1 \
412 0xf80004UL
413#define XSEM_REG_ENABLE_IN \
414 0x1400004UL
415#define YCM_REG_INIT \
416 0x1080000UL
417#define YSDM_REG_ENABLE_IN1 \
418 0xf90004UL
419#define YSEM_REG_ENABLE_IN \
420 0x1500004UL
421#define XYLD_REG_SCBD_STRICT_PRIO \
422 0x4c0000UL
423#define TMLD_REG_SCBD_STRICT_PRIO \
424 0x4d0000UL
425#define MULD_REG_SCBD_STRICT_PRIO \
426 0x4e0000UL
427#define YULD_REG_SCBD_STRICT_PRIO \
428 0x4c8000UL
429#define MISC_REG_SHARED_MEM_ADDR \
430 0x008c20UL
431#define DMAE_REG_GO_C0 \
432 0x00c048UL
433#define DMAE_REG_GO_C1 \
434 0x00c04cUL
435#define DMAE_REG_GO_C2 \
436 0x00c050UL
437#define DMAE_REG_GO_C3 \
438 0x00c054UL
439#define DMAE_REG_GO_C4 \
440 0x00c058UL
441#define DMAE_REG_GO_C5 \
442 0x00c05cUL
443#define DMAE_REG_GO_C6 \
444 0x00c060UL
445#define DMAE_REG_GO_C7 \
446 0x00c064UL
447#define DMAE_REG_GO_C8 \
448 0x00c068UL
449#define DMAE_REG_GO_C9 \
450 0x00c06cUL
451#define DMAE_REG_GO_C10 \
452 0x00c070UL
453#define DMAE_REG_GO_C11 \
454 0x00c074UL
455#define DMAE_REG_GO_C12 \
456 0x00c078UL
457#define DMAE_REG_GO_C13 \
458 0x00c07cUL
459#define DMAE_REG_GO_C14 \
460 0x00c080UL
461#define DMAE_REG_GO_C15 \
462 0x00c084UL
463#define DMAE_REG_GO_C16 \
464 0x00c088UL
465#define DMAE_REG_GO_C17 \
466 0x00c08cUL
467#define DMAE_REG_GO_C18 \
468 0x00c090UL
469#define DMAE_REG_GO_C19 \
470 0x00c094UL
471#define DMAE_REG_GO_C20 \
472 0x00c098UL
473#define DMAE_REG_GO_C21 \
474 0x00c09cUL
475#define DMAE_REG_GO_C22 \
476 0x00c0a0UL
477#define DMAE_REG_GO_C23 \
478 0x00c0a4UL
479#define DMAE_REG_GO_C24 \
480 0x00c0a8UL
481#define DMAE_REG_GO_C25 \
482 0x00c0acUL
483#define DMAE_REG_GO_C26 \
484 0x00c0b0UL
485#define DMAE_REG_GO_C27 \
486 0x00c0b4UL
487#define DMAE_REG_GO_C28 \
488 0x00c0b8UL
489#define DMAE_REG_GO_C29 \
490 0x00c0bcUL
491#define DMAE_REG_GO_C30 \
492 0x00c0c0UL
493#define DMAE_REG_GO_C31 \
494 0x00c0c4UL
495#define DMAE_REG_CMD_MEM \
496 0x00c800UL
497#define QM_REG_MAXPQSIZETXSEL_0 \
498 0x2f0440UL
499#define QM_REG_SDMCMDREADY \
500 0x2f1e10UL
501#define QM_REG_SDMCMDADDR \
502 0x2f1e04UL
503#define QM_REG_SDMCMDDATALSB \
504 0x2f1e08UL
505#define QM_REG_SDMCMDDATAMSB \
506 0x2f1e0cUL
507#define QM_REG_SDMCMDGO \
508 0x2f1e14UL
509#define QM_REG_RLPFCRD \
510 0x2f4d80UL
511#define QM_REG_RLPFINCVAL \
512 0x2f4c80UL
513#define QM_REG_RLGLBLCRD \
514 0x2f4400UL
515#define QM_REG_RLGLBLINCVAL \
516 0x2f3400UL
517#define IGU_REG_ATTENTION_ENABLE \
518 0x18083cUL
519#define IGU_REG_ATTN_MSG_ADDR_L \
520 0x180820UL
521#define IGU_REG_ATTN_MSG_ADDR_H \
522 0x180824UL
523#define MISC_REG_AEU_GENERAL_ATTN_0 \
524 0x008400UL
525#define MISC_REG_AEU_GENERAL_ATTN_35 \
526 0x00848cUL
527#define CAU_REG_SB_ADDR_MEMORY \
528 0x1c8000UL
529#define CAU_REG_SB_VAR_MEMORY \
530 0x1c6000UL
531#define CAU_REG_PI_MEMORY \
532 0x1d0000UL
533#define IGU_REG_PF_CONFIGURATION \
534 0x180800UL
535#define IGU_REG_VF_CONFIGURATION \
536 0x180804UL
537#define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \
538 0x00849cUL
539#define MISC_REG_AEU_AFTER_INVERT_1_IGU \
540 0x0087b4UL
541#define MISC_REG_AEU_MASK_ATTN_IGU \
542 0x008494UL
543#define IGU_REG_CLEANUP_STATUS_0 \
544 0x180980UL
545#define IGU_REG_CLEANUP_STATUS_1 \
546 0x180a00UL
547#define IGU_REG_CLEANUP_STATUS_2 \
548 0x180a80UL
549#define IGU_REG_CLEANUP_STATUS_3 \
550 0x180b00UL
551#define IGU_REG_CLEANUP_STATUS_4 \
552 0x180b80UL
553#define IGU_REG_COMMAND_REG_32LSB_DATA \
554 0x180840UL
555#define IGU_REG_COMMAND_REG_CTRL \
556 0x180848UL
557#define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \
558 0x1 << 1)
559#define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \
560 0x1 << 0)
561#define IGU_REG_MAPPING_MEMORY \
562 0x184000UL
563#define IGU_REG_STATISTIC_NUM_VF_MSG_SENT \
564 0x180408UL
565#define IGU_REG_WRITE_DONE_PENDING \
566 0x180900UL
567#define MISCS_REG_GENERIC_POR_0 \
568 0x0096d4UL
569#define MCP_REG_NVM_CFG4 \
570 0xe0642cUL
571#define MCP_REG_NVM_CFG4_FLASH_SIZE ( \
572 0x7 << 0)
573#define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \
574 0
575#define MCP_REG_CPU_STATE \
576 0xe05004UL
577#define MCP_REG_CPU_STATE_SOFT_HALTED (0x1UL << 10)
578#define MCP_REG_CPU_EVENT_MASK \
579 0xe05008UL
580#define MCP_REG_CPU_PROGRAM_COUNTER 0xe0501cUL
581#define PGLUE_B_REG_PF_BAR0_SIZE \
582 0x2aae60UL
583#define PGLUE_B_REG_PF_BAR1_SIZE \
584 0x2aae64UL
585#define PGLUE_B_REG_VF_BAR1_SIZE 0x2aae68UL
586#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL
587#define PRS_REG_GRE_PROTOCOL 0x1f0734UL
588#define PRS_REG_VXLAN_PORT 0x1f0738UL
589#define PRS_REG_OUTPUT_FORMAT_4_0_BB_K2 0x1f099cUL
590#define NIG_REG_ENC_TYPE_ENABLE 0x501058UL
591
592#define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0)
593#define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0
594#define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE (0x1 << 1)
595#define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1
596#define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE (0x1 << 2)
597#define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2
598
599#define NIG_REG_VXLAN_CTRL 0x50105cUL
600#define PBF_REG_VXLAN_PORT 0xd80518UL
601#define PBF_REG_NGE_PORT 0xd8051cUL
602#define PRS_REG_NGE_PORT 0x1f086cUL
603#define NIG_REG_NGE_PORT 0x508b38UL
604
605#define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL
606#define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL
607#define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL
608#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5 0x10092cUL
609#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5 0x100930UL
610
611#define NIG_REG_NGE_IP_ENABLE 0x508b28UL
612#define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL
613#define NIG_REG_NGE_COMP_VER 0x508b30UL
614#define PBF_REG_NGE_COMP_VER 0xd80524UL
615#define PRS_REG_NGE_COMP_VER 0x1f0878UL
616
617#define QM_REG_WFQPFWEIGHT 0x2f4e80UL
618#define QM_REG_WFQVPWEIGHT 0x2fa000UL
619
620#define PGLCS_REG_DBG_SELECT_K2_E5 \
621 0x001d14UL
622#define PGLCS_REG_DBG_DWORD_ENABLE_K2_E5 \
623 0x001d18UL
624#define PGLCS_REG_DBG_SHIFT_K2_E5 \
625 0x001d1cUL
626#define PGLCS_REG_DBG_FORCE_VALID_K2_E5 \
627 0x001d20UL
628#define PGLCS_REG_DBG_FORCE_FRAME_K2_E5 \
629 0x001d24UL
630#define MISC_REG_RESET_PL_PDA_VMAIN_1 \
631 0x008070UL
632#define MISC_REG_RESET_PL_PDA_VMAIN_2 \
633 0x008080UL
634#define MISC_REG_RESET_PL_PDA_VAUX \
635 0x008090UL
636#define MISCS_REG_RESET_PL_UA \
637 0x009050UL
638#define MISCS_REG_RESET_PL_HV \
639 0x009060UL
640#define MISCS_REG_RESET_PL_HV_2_K2_E5 \
641 0x009150UL
642#define DMAE_REG_DBG_SELECT \
643 0x00c510UL
644#define DMAE_REG_DBG_DWORD_ENABLE \
645 0x00c514UL
646#define DMAE_REG_DBG_SHIFT \
647 0x00c518UL
648#define DMAE_REG_DBG_FORCE_VALID \
649 0x00c51cUL
650#define DMAE_REG_DBG_FORCE_FRAME \
651 0x00c520UL
652#define NCSI_REG_DBG_SELECT \
653 0x040474UL
654#define NCSI_REG_DBG_DWORD_ENABLE \
655 0x040478UL
656#define NCSI_REG_DBG_SHIFT \
657 0x04047cUL
658#define NCSI_REG_DBG_FORCE_VALID \
659 0x040480UL
660#define NCSI_REG_DBG_FORCE_FRAME \
661 0x040484UL
662#define GRC_REG_DBG_SELECT \
663 0x0500a4UL
664#define GRC_REG_DBG_DWORD_ENABLE \
665 0x0500a8UL
666#define GRC_REG_DBG_SHIFT \
667 0x0500acUL
668#define GRC_REG_DBG_FORCE_VALID \
669 0x0500b0UL
670#define GRC_REG_DBG_FORCE_FRAME \
671 0x0500b4UL
672#define UMAC_REG_DBG_SELECT_K2_E5 \
673 0x051094UL
674#define UMAC_REG_DBG_DWORD_ENABLE_K2_E5 \
675 0x051098UL
676#define UMAC_REG_DBG_SHIFT_K2_E5 \
677 0x05109cUL
678#define UMAC_REG_DBG_FORCE_VALID_K2_E5 \
679 0x0510a0UL
680#define UMAC_REG_DBG_FORCE_FRAME_K2_E5 \
681 0x0510a4UL
682#define MCP2_REG_DBG_SELECT \
683 0x052400UL
684#define MCP2_REG_DBG_DWORD_ENABLE \
685 0x052404UL
686#define MCP2_REG_DBG_SHIFT \
687 0x052408UL
688#define MCP2_REG_DBG_FORCE_VALID \
689 0x052440UL
690#define MCP2_REG_DBG_FORCE_FRAME \
691 0x052444UL
692#define PCIE_REG_DBG_SELECT \
693 0x0547e8UL
694#define PCIE_REG_DBG_DWORD_ENABLE \
695 0x0547ecUL
696#define PCIE_REG_DBG_SHIFT \
697 0x0547f0UL
698#define PCIE_REG_DBG_FORCE_VALID \
699 0x0547f4UL
700#define PCIE_REG_DBG_FORCE_FRAME \
701 0x0547f8UL
702#define DORQ_REG_DBG_SELECT \
703 0x100ad0UL
704#define DORQ_REG_DBG_DWORD_ENABLE \
705 0x100ad4UL
706#define DORQ_REG_DBG_SHIFT \
707 0x100ad8UL
708#define DORQ_REG_DBG_FORCE_VALID \
709 0x100adcUL
710#define DORQ_REG_DBG_FORCE_FRAME \
711 0x100ae0UL
712#define IGU_REG_DBG_SELECT \
713 0x181578UL
714#define IGU_REG_DBG_DWORD_ENABLE \
715 0x18157cUL
716#define IGU_REG_DBG_SHIFT \
717 0x181580UL
718#define IGU_REG_DBG_FORCE_VALID \
719 0x181584UL
720#define IGU_REG_DBG_FORCE_FRAME \
721 0x181588UL
722#define CAU_REG_DBG_SELECT \
723 0x1c0ea8UL
724#define CAU_REG_DBG_DWORD_ENABLE \
725 0x1c0eacUL
726#define CAU_REG_DBG_SHIFT \
727 0x1c0eb0UL
728#define CAU_REG_DBG_FORCE_VALID \
729 0x1c0eb4UL
730#define CAU_REG_DBG_FORCE_FRAME \
731 0x1c0eb8UL
732#define PRS_REG_DBG_SELECT \
733 0x1f0b6cUL
734#define PRS_REG_DBG_DWORD_ENABLE \
735 0x1f0b70UL
736#define PRS_REG_DBG_SHIFT \
737 0x1f0b74UL
738#define PRS_REG_DBG_FORCE_VALID \
739 0x1f0ba0UL
740#define PRS_REG_DBG_FORCE_FRAME \
741 0x1f0ba4UL
742#define CNIG_REG_DBG_SELECT_K2_E5 \
743 0x218254UL
744#define CNIG_REG_DBG_DWORD_ENABLE_K2_E5 \
745 0x218258UL
746#define CNIG_REG_DBG_SHIFT_K2_E5 \
747 0x21825cUL
748#define CNIG_REG_DBG_FORCE_VALID_K2_E5 \
749 0x218260UL
750#define CNIG_REG_DBG_FORCE_FRAME_K2_E5 \
751 0x218264UL
752#define PRM_REG_DBG_SELECT \
753 0x2306a8UL
754#define PRM_REG_DBG_DWORD_ENABLE \
755 0x2306acUL
756#define PRM_REG_DBG_SHIFT \
757 0x2306b0UL
758#define PRM_REG_DBG_FORCE_VALID \
759 0x2306b4UL
760#define PRM_REG_DBG_FORCE_FRAME \
761 0x2306b8UL
762#define SRC_REG_DBG_SELECT \
763 0x238700UL
764#define SRC_REG_DBG_DWORD_ENABLE \
765 0x238704UL
766#define SRC_REG_DBG_SHIFT \
767 0x238708UL
768#define SRC_REG_DBG_FORCE_VALID \
769 0x23870cUL
770#define SRC_REG_DBG_FORCE_FRAME \
771 0x238710UL
772#define RSS_REG_DBG_SELECT \
773 0x238c4cUL
774#define RSS_REG_DBG_DWORD_ENABLE \
775 0x238c50UL
776#define RSS_REG_DBG_SHIFT \
777 0x238c54UL
778#define RSS_REG_DBG_FORCE_VALID \
779 0x238c58UL
780#define RSS_REG_DBG_FORCE_FRAME \
781 0x238c5cUL
782#define RPB_REG_DBG_SELECT \
783 0x23c728UL
784#define RPB_REG_DBG_DWORD_ENABLE \
785 0x23c72cUL
786#define RPB_REG_DBG_SHIFT \
787 0x23c730UL
788#define RPB_REG_DBG_FORCE_VALID \
789 0x23c734UL
790#define RPB_REG_DBG_FORCE_FRAME \
791 0x23c738UL
792#define PSWRQ2_REG_DBG_SELECT \
793 0x240100UL
794#define PSWRQ2_REG_DBG_DWORD_ENABLE \
795 0x240104UL
796#define PSWRQ2_REG_DBG_SHIFT \
797 0x240108UL
798#define PSWRQ2_REG_DBG_FORCE_VALID \
799 0x24010cUL
800#define PSWRQ2_REG_DBG_FORCE_FRAME \
801 0x240110UL
802#define PSWRQ_REG_DBG_SELECT \
803 0x280020UL
804#define PSWRQ_REG_DBG_DWORD_ENABLE \
805 0x280024UL
806#define PSWRQ_REG_DBG_SHIFT \
807 0x280028UL
808#define PSWRQ_REG_DBG_FORCE_VALID \
809 0x28002cUL
810#define PSWRQ_REG_DBG_FORCE_FRAME \
811 0x280030UL
812#define PSWWR_REG_DBG_SELECT \
813 0x29a084UL
814#define PSWWR_REG_DBG_DWORD_ENABLE \
815 0x29a088UL
816#define PSWWR_REG_DBG_SHIFT \
817 0x29a08cUL
818#define PSWWR_REG_DBG_FORCE_VALID \
819 0x29a090UL
820#define PSWWR_REG_DBG_FORCE_FRAME \
821 0x29a094UL
822#define PSWRD_REG_DBG_SELECT \
823 0x29c040UL
824#define PSWRD_REG_DBG_DWORD_ENABLE \
825 0x29c044UL
826#define PSWRD_REG_DBG_SHIFT \
827 0x29c048UL
828#define PSWRD_REG_DBG_FORCE_VALID \
829 0x29c04cUL
830#define PSWRD_REG_DBG_FORCE_FRAME \
831 0x29c050UL
832#define PSWRD2_REG_DBG_SELECT \
833 0x29d400UL
834#define PSWRD2_REG_DBG_DWORD_ENABLE \
835 0x29d404UL
836#define PSWRD2_REG_DBG_SHIFT \
837 0x29d408UL
838#define PSWRD2_REG_DBG_FORCE_VALID \
839 0x29d40cUL
840#define PSWRD2_REG_DBG_FORCE_FRAME \
841 0x29d410UL
842#define PSWHST2_REG_DBG_SELECT \
843 0x29e058UL
844#define PSWHST2_REG_DBG_DWORD_ENABLE \
845 0x29e05cUL
846#define PSWHST2_REG_DBG_SHIFT \
847 0x29e060UL
848#define PSWHST2_REG_DBG_FORCE_VALID \
849 0x29e064UL
850#define PSWHST2_REG_DBG_FORCE_FRAME \
851 0x29e068UL
852#define PSWHST_REG_DBG_SELECT \
853 0x2a0100UL
854#define PSWHST_REG_DBG_DWORD_ENABLE \
855 0x2a0104UL
856#define PSWHST_REG_DBG_SHIFT \
857 0x2a0108UL
858#define PSWHST_REG_DBG_FORCE_VALID \
859 0x2a010cUL
860#define PSWHST_REG_DBG_FORCE_FRAME \
861 0x2a0110UL
862#define PGLUE_B_REG_DBG_SELECT \
863 0x2a8400UL
864#define PGLUE_B_REG_DBG_DWORD_ENABLE \
865 0x2a8404UL
866#define PGLUE_B_REG_DBG_SHIFT \
867 0x2a8408UL
868#define PGLUE_B_REG_DBG_FORCE_VALID \
869 0x2a840cUL
870#define PGLUE_B_REG_DBG_FORCE_FRAME \
871 0x2a8410UL
872#define TM_REG_DBG_SELECT \
873 0x2c07a8UL
874#define TM_REG_DBG_DWORD_ENABLE \
875 0x2c07acUL
876#define TM_REG_DBG_SHIFT \
877 0x2c07b0UL
878#define TM_REG_DBG_FORCE_VALID \
879 0x2c07b4UL
880#define TM_REG_DBG_FORCE_FRAME \
881 0x2c07b8UL
882#define TCFC_REG_DBG_SELECT \
883 0x2d0500UL
884#define TCFC_REG_DBG_DWORD_ENABLE \
885 0x2d0504UL
886#define TCFC_REG_DBG_SHIFT \
887 0x2d0508UL
888#define TCFC_REG_DBG_FORCE_VALID \
889 0x2d050cUL
890#define TCFC_REG_DBG_FORCE_FRAME \
891 0x2d0510UL
892#define CCFC_REG_DBG_SELECT \
893 0x2e0500UL
894#define CCFC_REG_DBG_DWORD_ENABLE \
895 0x2e0504UL
896#define CCFC_REG_DBG_SHIFT \
897 0x2e0508UL
898#define CCFC_REG_DBG_FORCE_VALID \
899 0x2e050cUL
900#define CCFC_REG_DBG_FORCE_FRAME \
901 0x2e0510UL
902#define QM_REG_DBG_SELECT \
903 0x2f2e74UL
904#define QM_REG_DBG_DWORD_ENABLE \
905 0x2f2e78UL
906#define QM_REG_DBG_SHIFT \
907 0x2f2e7cUL
908#define QM_REG_DBG_FORCE_VALID \
909 0x2f2e80UL
910#define QM_REG_DBG_FORCE_FRAME \
911 0x2f2e84UL
912#define RDIF_REG_DBG_SELECT \
913 0x300500UL
914#define RDIF_REG_DBG_DWORD_ENABLE \
915 0x300504UL
916#define RDIF_REG_DBG_SHIFT \
917 0x300508UL
918#define RDIF_REG_DBG_FORCE_VALID \
919 0x30050cUL
920#define RDIF_REG_DBG_FORCE_FRAME \
921 0x300510UL
922#define TDIF_REG_DBG_SELECT \
923 0x310500UL
924#define TDIF_REG_DBG_DWORD_ENABLE \
925 0x310504UL
926#define TDIF_REG_DBG_SHIFT \
927 0x310508UL
928#define TDIF_REG_DBG_FORCE_VALID \
929 0x31050cUL
930#define TDIF_REG_DBG_FORCE_FRAME \
931 0x310510UL
932#define BRB_REG_DBG_SELECT \
933 0x340ed0UL
934#define BRB_REG_DBG_DWORD_ENABLE \
935 0x340ed4UL
936#define BRB_REG_DBG_SHIFT \
937 0x340ed8UL
938#define BRB_REG_DBG_FORCE_VALID \
939 0x340edcUL
940#define BRB_REG_DBG_FORCE_FRAME \
941 0x340ee0UL
942#define XYLD_REG_DBG_SELECT \
943 0x4c1600UL
944#define XYLD_REG_DBG_DWORD_ENABLE \
945 0x4c1604UL
946#define XYLD_REG_DBG_SHIFT \
947 0x4c1608UL
948#define XYLD_REG_DBG_FORCE_VALID \
949 0x4c160cUL
950#define XYLD_REG_DBG_FORCE_FRAME \
951 0x4c1610UL
952#define YULD_REG_DBG_SELECT_BB_K2 \
953 0x4c9600UL
954#define YULD_REG_DBG_DWORD_ENABLE_BB_K2 \
955 0x4c9604UL
956#define YULD_REG_DBG_SHIFT_BB_K2 \
957 0x4c9608UL
958#define YULD_REG_DBG_FORCE_VALID_BB_K2 \
959 0x4c960cUL
960#define YULD_REG_DBG_FORCE_FRAME_BB_K2 \
961 0x4c9610UL
962#define TMLD_REG_DBG_SELECT \
963 0x4d1600UL
964#define TMLD_REG_DBG_DWORD_ENABLE \
965 0x4d1604UL
966#define TMLD_REG_DBG_SHIFT \
967 0x4d1608UL
968#define TMLD_REG_DBG_FORCE_VALID \
969 0x4d160cUL
970#define TMLD_REG_DBG_FORCE_FRAME \
971 0x4d1610UL
972#define MULD_REG_DBG_SELECT \
973 0x4e1600UL
974#define MULD_REG_DBG_DWORD_ENABLE \
975 0x4e1604UL
976#define MULD_REG_DBG_SHIFT \
977 0x4e1608UL
978#define MULD_REG_DBG_FORCE_VALID \
979 0x4e160cUL
980#define MULD_REG_DBG_FORCE_FRAME \
981 0x4e1610UL
982#define NIG_REG_DBG_SELECT \
983 0x502140UL
984#define NIG_REG_DBG_DWORD_ENABLE \
985 0x502144UL
986#define NIG_REG_DBG_SHIFT \
987 0x502148UL
988#define NIG_REG_DBG_FORCE_VALID \
989 0x50214cUL
990#define NIG_REG_DBG_FORCE_FRAME \
991 0x502150UL
992#define BMB_REG_DBG_SELECT \
993 0x540a7cUL
994#define BMB_REG_DBG_DWORD_ENABLE \
995 0x540a80UL
996#define BMB_REG_DBG_SHIFT \
997 0x540a84UL
998#define BMB_REG_DBG_FORCE_VALID \
999 0x540a88UL
1000#define BMB_REG_DBG_FORCE_FRAME \
1001 0x540a8cUL
1002#define PTU_REG_DBG_SELECT \
1003 0x560100UL
1004#define PTU_REG_DBG_DWORD_ENABLE \
1005 0x560104UL
1006#define PTU_REG_DBG_SHIFT \
1007 0x560108UL
1008#define PTU_REG_DBG_FORCE_VALID \
1009 0x56010cUL
1010#define PTU_REG_DBG_FORCE_FRAME \
1011 0x560110UL
1012#define CDU_REG_DBG_SELECT \
1013 0x580704UL
1014#define CDU_REG_DBG_DWORD_ENABLE \
1015 0x580708UL
1016#define CDU_REG_DBG_SHIFT \
1017 0x58070cUL
1018#define CDU_REG_DBG_FORCE_VALID \
1019 0x580710UL
1020#define CDU_REG_DBG_FORCE_FRAME \
1021 0x580714UL
1022#define WOL_REG_DBG_SELECT_K2_E5 \
1023 0x600140UL
1024#define WOL_REG_DBG_DWORD_ENABLE_K2_E5 \
1025 0x600144UL
1026#define WOL_REG_DBG_SHIFT_K2_E5 \
1027 0x600148UL
1028#define WOL_REG_DBG_FORCE_VALID_K2_E5 \
1029 0x60014cUL
1030#define WOL_REG_DBG_FORCE_FRAME_K2_E5 \
1031 0x600150UL
1032#define BMBN_REG_DBG_SELECT_K2_E5 \
1033 0x610140UL
1034#define BMBN_REG_DBG_DWORD_ENABLE_K2_E5 \
1035 0x610144UL
1036#define BMBN_REG_DBG_SHIFT_K2_E5 \
1037 0x610148UL
1038#define BMBN_REG_DBG_FORCE_VALID_K2_E5 \
1039 0x61014cUL
1040#define BMBN_REG_DBG_FORCE_FRAME_K2_E5 \
1041 0x610150UL
1042#define NWM_REG_DBG_SELECT_K2_E5 \
1043 0x8000ecUL
1044#define NWM_REG_DBG_DWORD_ENABLE_K2_E5 \
1045 0x8000f0UL
1046#define NWM_REG_DBG_SHIFT_K2_E5 \
1047 0x8000f4UL
1048#define NWM_REG_DBG_FORCE_VALID_K2_E5 \
1049 0x8000f8UL
1050#define NWM_REG_DBG_FORCE_FRAME_K2_E5 \
1051 0x8000fcUL
1052#define PBF_REG_DBG_SELECT \
1053 0xd80060UL
1054#define PBF_REG_DBG_DWORD_ENABLE \
1055 0xd80064UL
1056#define PBF_REG_DBG_SHIFT \
1057 0xd80068UL
1058#define PBF_REG_DBG_FORCE_VALID \
1059 0xd8006cUL
1060#define PBF_REG_DBG_FORCE_FRAME \
1061 0xd80070UL
1062#define PBF_PB1_REG_DBG_SELECT \
1063 0xda0728UL
1064#define PBF_PB1_REG_DBG_DWORD_ENABLE \
1065 0xda072cUL
1066#define PBF_PB1_REG_DBG_SHIFT \
1067 0xda0730UL
1068#define PBF_PB1_REG_DBG_FORCE_VALID \
1069 0xda0734UL
1070#define PBF_PB1_REG_DBG_FORCE_FRAME \
1071 0xda0738UL
1072#define PBF_PB2_REG_DBG_SELECT \
1073 0xda4728UL
1074#define PBF_PB2_REG_DBG_DWORD_ENABLE \
1075 0xda472cUL
1076#define PBF_PB2_REG_DBG_SHIFT \
1077 0xda4730UL
1078#define PBF_PB2_REG_DBG_FORCE_VALID \
1079 0xda4734UL
1080#define PBF_PB2_REG_DBG_FORCE_FRAME \
1081 0xda4738UL
1082#define BTB_REG_DBG_SELECT \
1083 0xdb08c8UL
1084#define BTB_REG_DBG_DWORD_ENABLE \
1085 0xdb08ccUL
1086#define BTB_REG_DBG_SHIFT \
1087 0xdb08d0UL
1088#define BTB_REG_DBG_FORCE_VALID \
1089 0xdb08d4UL
1090#define BTB_REG_DBG_FORCE_FRAME \
1091 0xdb08d8UL
1092#define XSDM_REG_DBG_SELECT \
1093 0xf80e28UL
1094#define XSDM_REG_DBG_DWORD_ENABLE \
1095 0xf80e2cUL
1096#define XSDM_REG_DBG_SHIFT \
1097 0xf80e30UL
1098#define XSDM_REG_DBG_FORCE_VALID \
1099 0xf80e34UL
1100#define XSDM_REG_DBG_FORCE_FRAME \
1101 0xf80e38UL
1102#define YSDM_REG_DBG_SELECT \
1103 0xf90e28UL
1104#define YSDM_REG_DBG_DWORD_ENABLE \
1105 0xf90e2cUL
1106#define YSDM_REG_DBG_SHIFT \
1107 0xf90e30UL
1108#define YSDM_REG_DBG_FORCE_VALID \
1109 0xf90e34UL
1110#define YSDM_REG_DBG_FORCE_FRAME \
1111 0xf90e38UL
1112#define PSDM_REG_DBG_SELECT \
1113 0xfa0e28UL
1114#define PSDM_REG_DBG_DWORD_ENABLE \
1115 0xfa0e2cUL
1116#define PSDM_REG_DBG_SHIFT \
1117 0xfa0e30UL
1118#define PSDM_REG_DBG_FORCE_VALID \
1119 0xfa0e34UL
1120#define PSDM_REG_DBG_FORCE_FRAME \
1121 0xfa0e38UL
1122#define TSDM_REG_DBG_SELECT \
1123 0xfb0e28UL
1124#define TSDM_REG_DBG_DWORD_ENABLE \
1125 0xfb0e2cUL
1126#define TSDM_REG_DBG_SHIFT \
1127 0xfb0e30UL
1128#define TSDM_REG_DBG_FORCE_VALID \
1129 0xfb0e34UL
1130#define TSDM_REG_DBG_FORCE_FRAME \
1131 0xfb0e38UL
1132#define MSDM_REG_DBG_SELECT \
1133 0xfc0e28UL
1134#define MSDM_REG_DBG_DWORD_ENABLE \
1135 0xfc0e2cUL
1136#define MSDM_REG_DBG_SHIFT \
1137 0xfc0e30UL
1138#define MSDM_REG_DBG_FORCE_VALID \
1139 0xfc0e34UL
1140#define MSDM_REG_DBG_FORCE_FRAME \
1141 0xfc0e38UL
1142#define USDM_REG_DBG_SELECT \
1143 0xfd0e28UL
1144#define USDM_REG_DBG_DWORD_ENABLE \
1145 0xfd0e2cUL
1146#define USDM_REG_DBG_SHIFT \
1147 0xfd0e30UL
1148#define USDM_REG_DBG_FORCE_VALID \
1149 0xfd0e34UL
1150#define USDM_REG_DBG_FORCE_FRAME \
1151 0xfd0e38UL
1152#define XCM_REG_DBG_SELECT \
1153 0x1000040UL
1154#define XCM_REG_DBG_DWORD_ENABLE \
1155 0x1000044UL
1156#define XCM_REG_DBG_SHIFT \
1157 0x1000048UL
1158#define XCM_REG_DBG_FORCE_VALID \
1159 0x100004cUL
1160#define XCM_REG_DBG_FORCE_FRAME \
1161 0x1000050UL
1162#define YCM_REG_DBG_SELECT \
1163 0x1080040UL
1164#define YCM_REG_DBG_DWORD_ENABLE \
1165 0x1080044UL
1166#define YCM_REG_DBG_SHIFT \
1167 0x1080048UL
1168#define YCM_REG_DBG_FORCE_VALID \
1169 0x108004cUL
1170#define YCM_REG_DBG_FORCE_FRAME \
1171 0x1080050UL
1172#define PCM_REG_DBG_SELECT \
1173 0x1100040UL
1174#define PCM_REG_DBG_DWORD_ENABLE \
1175 0x1100044UL
1176#define PCM_REG_DBG_SHIFT \
1177 0x1100048UL
1178#define PCM_REG_DBG_FORCE_VALID \
1179 0x110004cUL
1180#define PCM_REG_DBG_FORCE_FRAME \
1181 0x1100050UL
1182#define TCM_REG_DBG_SELECT \
1183 0x1180040UL
1184#define TCM_REG_DBG_DWORD_ENABLE \
1185 0x1180044UL
1186#define TCM_REG_DBG_SHIFT \
1187 0x1180048UL
1188#define TCM_REG_DBG_FORCE_VALID \
1189 0x118004cUL
1190#define TCM_REG_DBG_FORCE_FRAME \
1191 0x1180050UL
1192#define MCM_REG_DBG_SELECT \
1193 0x1200040UL
1194#define MCM_REG_DBG_DWORD_ENABLE \
1195 0x1200044UL
1196#define MCM_REG_DBG_SHIFT \
1197 0x1200048UL
1198#define MCM_REG_DBG_FORCE_VALID \
1199 0x120004cUL
1200#define MCM_REG_DBG_FORCE_FRAME \
1201 0x1200050UL
1202#define UCM_REG_DBG_SELECT \
1203 0x1280050UL
1204#define UCM_REG_DBG_DWORD_ENABLE \
1205 0x1280054UL
1206#define UCM_REG_DBG_SHIFT \
1207 0x1280058UL
1208#define UCM_REG_DBG_FORCE_VALID \
1209 0x128005cUL
1210#define UCM_REG_DBG_FORCE_FRAME \
1211 0x1280060UL
1212#define XSEM_REG_DBG_SELECT \
1213 0x1401528UL
1214#define XSEM_REG_DBG_DWORD_ENABLE \
1215 0x140152cUL
1216#define XSEM_REG_DBG_SHIFT \
1217 0x1401530UL
1218#define XSEM_REG_DBG_FORCE_VALID \
1219 0x1401534UL
1220#define XSEM_REG_DBG_FORCE_FRAME \
1221 0x1401538UL
1222#define YSEM_REG_DBG_SELECT \
1223 0x1501528UL
1224#define YSEM_REG_DBG_DWORD_ENABLE \
1225 0x150152cUL
1226#define YSEM_REG_DBG_SHIFT \
1227 0x1501530UL
1228#define YSEM_REG_DBG_FORCE_VALID \
1229 0x1501534UL
1230#define YSEM_REG_DBG_FORCE_FRAME \
1231 0x1501538UL
1232#define PSEM_REG_DBG_SELECT \
1233 0x1601528UL
1234#define PSEM_REG_DBG_DWORD_ENABLE \
1235 0x160152cUL
1236#define PSEM_REG_DBG_SHIFT \
1237 0x1601530UL
1238#define PSEM_REG_DBG_FORCE_VALID \
1239 0x1601534UL
1240#define PSEM_REG_DBG_FORCE_FRAME \
1241 0x1601538UL
1242#define TSEM_REG_DBG_SELECT \
1243 0x1701528UL
1244#define TSEM_REG_DBG_DWORD_ENABLE \
1245 0x170152cUL
1246#define TSEM_REG_DBG_SHIFT \
1247 0x1701530UL
1248#define TSEM_REG_DBG_FORCE_VALID \
1249 0x1701534UL
1250#define TSEM_REG_DBG_FORCE_FRAME \
1251 0x1701538UL
1252#define DORQ_REG_PF_USAGE_CNT \
1253 0x1009c0UL
1254#define DORQ_REG_PF_OVFL_STICKY \
1255 0x1009d0UL
1256#define DORQ_REG_DPM_FORCE_ABORT \
1257 0x1009d8UL
1258#define DORQ_REG_INT_STS \
1259 0x100180UL
1260#define DORQ_REG_INT_STS_ADDRESS_ERROR \
1261 (0x1UL << 0)
1262#define DORQ_REG_INT_STS_WR \
1263 0x100188UL
1264#define DORQ_REG_DB_DROP_DETAILS_REL \
1265 0x100a28UL
1266#define DORQ_REG_INT_STS_ADDRESS_ERROR_SHIFT \
1267 0
1268#define DORQ_REG_INT_STS_DB_DROP \
1269 (0x1UL << 1)
1270#define DORQ_REG_INT_STS_DB_DROP_SHIFT \
1271 1
1272#define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR \
1273 (0x1UL << 2)
1274#define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR_SHIFT \
1275 2
1276#define DORQ_REG_INT_STS_DORQ_FIFO_AFULL\
1277 (0x1UL << 3)
1278#define DORQ_REG_INT_STS_DORQ_FIFO_AFULL_SHIFT \
1279 3
1280#define DORQ_REG_INT_STS_CFC_BYP_VALIDATION_ERR \
1281 (0x1UL << 4)
1282#define DORQ_REG_INT_STS_CFC_BYP_VALIDATION_ERR_SHIFT \
1283 4
1284#define DORQ_REG_INT_STS_CFC_LD_RESP_ERR \
1285 (0x1UL << 5)
1286#define DORQ_REG_INT_STS_CFC_LD_RESP_ERR_SHIFT \
1287 5
1288#define DORQ_REG_INT_STS_XCM_DONE_CNT_ERR \
1289 (0x1UL << 6)
1290#define DORQ_REG_INT_STS_XCM_DONE_CNT_ERR_SHIFT \
1291 6
1292#define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_OVFL_ERR \
1293 (0x1UL << 7)
1294#define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_OVFL_ERR_SHIFT \
1295 7
1296#define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_UNDER_ERR \
1297 (0x1UL << 8)
1298#define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_UNDER_ERR_SHIFT \
1299 8
1300#define DORQ_REG_DB_DROP_DETAILS_REASON \
1301 0x100a20UL
1302#define MSEM_REG_DBG_SELECT \
1303 0x1801528UL
1304#define MSEM_REG_DBG_DWORD_ENABLE \
1305 0x180152cUL
1306#define MSEM_REG_DBG_SHIFT \
1307 0x1801530UL
1308#define MSEM_REG_DBG_FORCE_VALID \
1309 0x1801534UL
1310#define MSEM_REG_DBG_FORCE_FRAME \
1311 0x1801538UL
1312#define USEM_REG_DBG_SELECT \
1313 0x1901528UL
1314#define USEM_REG_DBG_DWORD_ENABLE \
1315 0x190152cUL
1316#define USEM_REG_DBG_SHIFT \
1317 0x1901530UL
1318#define USEM_REG_DBG_FORCE_VALID \
1319 0x1901534UL
1320#define USEM_REG_DBG_FORCE_FRAME \
1321 0x1901538UL
1322#define NWS_REG_DBG_SELECT_K2_E5 \
1323 0x700128UL
1324#define NWS_REG_DBG_DWORD_ENABLE_K2_E5 \
1325 0x70012cUL
1326#define NWS_REG_DBG_SHIFT_K2_E5 \
1327 0x700130UL
1328#define NWS_REG_DBG_FORCE_VALID_K2_E5 \
1329 0x700134UL
1330#define NWS_REG_DBG_FORCE_FRAME_K2_E5 \
1331 0x700138UL
1332#define MS_REG_DBG_SELECT_K2_E5 \
1333 0x6a0228UL
1334#define MS_REG_DBG_DWORD_ENABLE_K2_E5 \
1335 0x6a022cUL
1336#define MS_REG_DBG_SHIFT_K2_E5 \
1337 0x6a0230UL
1338#define MS_REG_DBG_FORCE_VALID_K2_E5 \
1339 0x6a0234UL
1340#define MS_REG_DBG_FORCE_FRAME_K2_E5 \
1341 0x6a0238UL
1342#define PCIE_REG_DBG_COMMON_SELECT_K2_E5 \
1343 0x054398UL
1344#define PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5 \
1345 0x05439cUL
1346#define PCIE_REG_DBG_COMMON_SHIFT_K2_E5 \
1347 0x0543a0UL
1348#define PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5 \
1349 0x0543a4UL
1350#define PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5 \
1351 0x0543a8UL
1352#define PTLD_REG_DBG_SELECT_E5 \
1353 0x5a1600UL
1354#define PTLD_REG_DBG_DWORD_ENABLE_E5 \
1355 0x5a1604UL
1356#define PTLD_REG_DBG_SHIFT_E5 \
1357 0x5a1608UL
1358#define PTLD_REG_DBG_FORCE_VALID_E5 \
1359 0x5a160cUL
1360#define PTLD_REG_DBG_FORCE_FRAME_E5 \
1361 0x5a1610UL
1362#define YPLD_REG_DBG_SELECT_E5 \
1363 0x5c1600UL
1364#define YPLD_REG_DBG_DWORD_ENABLE_E5 \
1365 0x5c1604UL
1366#define YPLD_REG_DBG_SHIFT_E5 \
1367 0x5c1608UL
1368#define YPLD_REG_DBG_FORCE_VALID_E5 \
1369 0x5c160cUL
1370#define YPLD_REG_DBG_FORCE_FRAME_E5 \
1371 0x5c1610UL
1372#define RGSRC_REG_DBG_SELECT_E5 \
1373 0x320040UL
1374#define RGSRC_REG_DBG_DWORD_ENABLE_E5 \
1375 0x320044UL
1376#define RGSRC_REG_DBG_SHIFT_E5 \
1377 0x320048UL
1378#define RGSRC_REG_DBG_FORCE_VALID_E5 \
1379 0x32004cUL
1380#define RGSRC_REG_DBG_FORCE_FRAME_E5 \
1381 0x320050UL
1382#define TGSRC_REG_DBG_SELECT_E5 \
1383 0x322040UL
1384#define TGSRC_REG_DBG_DWORD_ENABLE_E5 \
1385 0x322044UL
1386#define TGSRC_REG_DBG_SHIFT_E5 \
1387 0x322048UL
1388#define TGSRC_REG_DBG_FORCE_VALID_E5 \
1389 0x32204cUL
1390#define TGSRC_REG_DBG_FORCE_FRAME_E5 \
1391 0x322050UL
1392#define MISC_REG_RESET_PL_UA \
1393 0x008050UL
1394#define MISC_REG_RESET_PL_HV \
1395 0x008060UL
1396#define XCM_REG_CTX_RBC_ACCS \
1397 0x1001800UL
1398#define XCM_REG_AGG_CON_CTX \
1399 0x1001804UL
1400#define XCM_REG_SM_CON_CTX \
1401 0x1001808UL
1402#define YCM_REG_CTX_RBC_ACCS \
1403 0x1081800UL
1404#define YCM_REG_AGG_CON_CTX \
1405 0x1081804UL
1406#define YCM_REG_AGG_TASK_CTX \
1407 0x1081808UL
1408#define YCM_REG_SM_CON_CTX \
1409 0x108180cUL
1410#define YCM_REG_SM_TASK_CTX \
1411 0x1081810UL
1412#define PCM_REG_CTX_RBC_ACCS \
1413 0x1101440UL
1414#define PCM_REG_SM_CON_CTX \
1415 0x1101444UL
1416#define TCM_REG_CTX_RBC_ACCS \
1417 0x11814c0UL
1418#define TCM_REG_AGG_CON_CTX \
1419 0x11814c4UL
1420#define TCM_REG_AGG_TASK_CTX \
1421 0x11814c8UL
1422#define TCM_REG_SM_CON_CTX \
1423 0x11814ccUL
1424#define TCM_REG_SM_TASK_CTX \
1425 0x11814d0UL
1426#define MCM_REG_CTX_RBC_ACCS \
1427 0x1201800UL
1428#define MCM_REG_AGG_CON_CTX \
1429 0x1201804UL
1430#define MCM_REG_AGG_TASK_CTX \
1431 0x1201808UL
1432#define MCM_REG_SM_CON_CTX \
1433 0x120180cUL
1434#define MCM_REG_SM_TASK_CTX \
1435 0x1201810UL
1436#define UCM_REG_CTX_RBC_ACCS \
1437 0x1281700UL
1438#define UCM_REG_AGG_CON_CTX \
1439 0x1281704UL
1440#define UCM_REG_AGG_TASK_CTX \
1441 0x1281708UL
1442#define UCM_REG_SM_CON_CTX \
1443 0x128170cUL
1444#define UCM_REG_SM_TASK_CTX \
1445 0x1281710UL
1446#define XSEM_REG_SLOW_DBG_EMPTY_BB_K2 \
1447 0x1401140UL
1448#define XSEM_REG_SYNC_DBG_EMPTY \
1449 0x1401160UL
1450#define XSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
1451 0x1401400UL
1452#define XSEM_REG_SLOW_DBG_MODE_BB_K2 \
1453 0x1401404UL
1454#define XSEM_REG_DBG_FRAME_MODE_BB_K2 \
1455 0x1401408UL
1456#define XSEM_REG_DBG_MODE1_CFG_BB_K2 \
1457 0x1401420UL
1458#define XSEM_REG_FAST_MEMORY \
1459 0x1440000UL
1460#define YSEM_REG_SYNC_DBG_EMPTY \
1461 0x1501160UL
1462#define YSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
1463 0x1501400UL
1464#define YSEM_REG_SLOW_DBG_MODE_BB_K2 \
1465 0x1501404UL
1466#define YSEM_REG_DBG_FRAME_MODE_BB_K2 \
1467 0x1501408UL
1468#define YSEM_REG_DBG_MODE1_CFG_BB_K2 \
1469 0x1501420UL
1470#define YSEM_REG_FAST_MEMORY \
1471 0x1540000UL
1472#define PSEM_REG_SLOW_DBG_EMPTY_BB_K2 \
1473 0x1601140UL
1474#define PSEM_REG_SYNC_DBG_EMPTY \
1475 0x1601160UL
1476#define PSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
1477 0x1601400UL
1478#define PSEM_REG_SLOW_DBG_MODE_BB_K2 \
1479 0x1601404UL
1480#define PSEM_REG_DBG_FRAME_MODE_BB_K2 \
1481 0x1601408UL
1482#define PSEM_REG_DBG_MODE1_CFG_BB_K2 \
1483 0x1601420UL
1484#define PSEM_REG_FAST_MEMORY \
1485 0x1640000UL
1486#define TSEM_REG_SLOW_DBG_EMPTY_BB_K2 \
1487 0x1701140UL
1488#define TSEM_REG_SYNC_DBG_EMPTY \
1489 0x1701160UL
1490#define TSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
1491 0x1701400UL
1492#define TSEM_REG_SLOW_DBG_MODE_BB_K2 \
1493 0x1701404UL
1494#define TSEM_REG_DBG_FRAME_MODE_BB_K2 \
1495 0x1701408UL
1496#define TSEM_REG_DBG_MODE1_CFG_BB_K2 \
1497 0x1701420UL
1498#define TSEM_REG_FAST_MEMORY \
1499 0x1740000UL
1500#define MSEM_REG_SLOW_DBG_EMPTY_BB_K2 \
1501 0x1801140UL
1502#define MSEM_REG_SYNC_DBG_EMPTY \
1503 0x1801160UL
1504#define MSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
1505 0x1801400UL
1506#define MSEM_REG_SLOW_DBG_MODE_BB_K2 \
1507 0x1801404UL
1508#define MSEM_REG_DBG_FRAME_MODE_BB_K2 \
1509 0x1801408UL
1510#define MSEM_REG_DBG_MODE1_CFG_BB_K2 \
1511 0x1801420UL
1512#define MSEM_REG_FAST_MEMORY \
1513 0x1840000UL
1514#define USEM_REG_SLOW_DBG_EMPTY_BB_K2 \
1515 0x1901140UL
1516#define USEM_REG_SYNC_DBG_EMPTY \
1517 0x1901160UL
1518#define USEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
1519 0x1901400UL
1520#define USEM_REG_SLOW_DBG_MODE_BB_K2 \
1521 0x1901404UL
1522#define USEM_REG_DBG_FRAME_MODE_BB_K2 \
1523 0x1901408UL
1524#define USEM_REG_DBG_MODE1_CFG_BB_K2 \
1525 0x1901420UL
1526#define USEM_REG_FAST_MEMORY \
1527 0x1940000UL
1528#define SEM_FAST_REG_INT_RAM \
1529 0x020000UL
1530#define SEM_FAST_REG_INT_RAM_SIZE_BB_K2 \
1531 20480
1532#define GRC_REG_TRACE_FIFO_VALID_DATA \
1533 0x050064UL
1534#define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW \
1535 0x05040cUL
1536#define GRC_REG_PROTECTION_OVERRIDE_WINDOW \
1537 0x050500UL
1538#define IGU_REG_ERROR_HANDLING_MEMORY \
1539 0x181520UL
1540#define MCP_REG_CPU_MODE \
1541 0xe05000UL
1542#define MCP_REG_CPU_MODE_SOFT_HALT \
1543 (0x1 << 10)
1544#define BRB_REG_BIG_RAM_ADDRESS \
1545 0x340800UL
1546#define BRB_REG_BIG_RAM_DATA \
1547 0x341500UL
1548#define BRB_REG_BIG_RAM_DATA_SIZE \
1549 64
1550#define SEM_FAST_REG_STALL_0_BB_K2 \
1551 0x000488UL
1552#define SEM_FAST_REG_STALLED \
1553 0x000494UL
1554#define BTB_REG_BIG_RAM_ADDRESS \
1555 0xdb0800UL
1556#define BTB_REG_BIG_RAM_DATA \
1557 0xdb0c00UL
1558#define BMB_REG_BIG_RAM_ADDRESS \
1559 0x540800UL
1560#define BMB_REG_BIG_RAM_DATA \
1561 0x540f00UL
1562#define SEM_FAST_REG_STORM_REG_FILE \
1563 0x008000UL
1564#define RSS_REG_RSS_RAM_ADDR \
1565 0x238c30UL
1566#define MISCS_REG_BLOCK_256B_EN \
1567 0x009074UL
1568#define MCP_REG_SCRATCH_SIZE_BB_K2 \
1569 57344
1570#define MCP_REG_CPU_REG_FILE \
1571 0xe05200UL
1572#define MCP_REG_CPU_REG_FILE_SIZE \
1573 32
1574#define DBG_REG_DEBUG_TARGET \
1575 0x01005cUL
1576#define DBG_REG_FULL_MODE \
1577 0x010060UL
1578#define DBG_REG_CALENDAR_OUT_DATA \
1579 0x010480UL
1580#define GRC_REG_TRACE_FIFO \
1581 0x050068UL
1582#define IGU_REG_ERROR_HANDLING_DATA_VALID \
1583 0x181530UL
1584#define DBG_REG_DBG_BLOCK_ON \
1585 0x010454UL
1586#define DBG_REG_FRAMING_MODE \
1587 0x010058UL
1588#define SEM_FAST_REG_VFC_DATA_WR \
1589 0x000b40UL
1590#define SEM_FAST_REG_VFC_ADDR \
1591 0x000b44UL
1592#define SEM_FAST_REG_VFC_DATA_RD \
1593 0x000b48UL
1594#define RSS_REG_RSS_RAM_DATA \
1595 0x238c20UL
1596#define RSS_REG_RSS_RAM_DATA_SIZE \
1597 4
1598#define MISC_REG_BLOCK_256B_EN \
1599 0x008c14UL
1600#define NWS_REG_NWS_CMU_K2 \
1601 0x720000UL
1602#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2_E5 \
1603 0x000680UL
1604#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2_E5 \
1605 0x000684UL
1606#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2_E5 \
1607 0x0006c0UL
1608#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2_E5 \
1609 0x0006c4UL
1610#define MS_REG_MS_CMU_K2_E5 \
1611 0x6a4000UL
1612#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2_E5 \
1613 0x000208UL
1614#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 \
1615 0x00020cUL
1616#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2_E5 \
1617 0x000210UL
1618#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2_E5 \
1619 0x000214UL
1620#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5 \
1621 0x000208UL
1622#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 \
1623 0x00020cUL
1624#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5 \
1625 0x000210UL
1626#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5 \
1627 0x000214UL
1628#define PHY_PCIE_REG_PHY0_K2_E5 \
1629 0x620000UL
1630#define PHY_PCIE_REG_PHY1_K2_E5 \
1631 0x624000UL
1632#define NIG_REG_ROCE_DUPLICATE_TO_HOST 0x5088f0UL
1633#define NIG_REG_PPF_TO_ENGINE_SEL 0x508900UL
1634#define NIG_REG_PPF_TO_ENGINE_SEL_SIZE 8
1635#define PRS_REG_LIGHT_L2_ETHERTYPE_EN 0x1f0968UL
1636#define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL
1637#define DORQ_REG_PF_DPM_ENABLE 0x100510UL
1638#define DORQ_REG_PF_ICID_BIT_SHIFT_NORM 0x100448UL
1639#define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL
1640#define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL
1641#define NIG_REG_RX_PTP_EN 0x501900UL
1642#define NIG_REG_TX_PTP_EN 0x501904UL
1643#define NIG_REG_LLH_PTP_TO_HOST 0x501908UL
1644#define NIG_REG_LLH_PTP_TO_MCP 0x50190cUL
1645#define NIG_REG_PTP_SW_TXTSEN 0x501910UL
1646#define NIG_REG_LLH_PTP_ETHERTYPE_1 0x501914UL
1647#define NIG_REG_LLH_PTP_MAC_DA_2_LSB 0x501918UL
1648#define NIG_REG_LLH_PTP_MAC_DA_2_MSB 0x50191cUL
1649#define NIG_REG_LLH_PTP_PARAM_MASK 0x501920UL
1650#define NIG_REG_LLH_PTP_RULE_MASK 0x501924UL
1651#define NIG_REG_TX_LLH_PTP_PARAM_MASK 0x501928UL
1652#define NIG_REG_TX_LLH_PTP_RULE_MASK 0x50192cUL
1653#define NIG_REG_LLH_PTP_HOST_BUF_SEQID 0x501930UL
1654#define NIG_REG_LLH_PTP_HOST_BUF_TS_LSB 0x501934UL
1655#define NIG_REG_LLH_PTP_HOST_BUF_TS_MSB 0x501938UL
1656#define NIG_REG_LLH_PTP_MCP_BUF_SEQID 0x50193cUL
1657#define NIG_REG_LLH_PTP_MCP_BUF_TS_LSB 0x501940UL
1658#define NIG_REG_LLH_PTP_MCP_BUF_TS_MSB 0x501944UL
1659#define NIG_REG_TX_LLH_PTP_BUF_SEQID 0x501948UL
1660#define NIG_REG_TX_LLH_PTP_BUF_TS_LSB 0x50194cUL
1661#define NIG_REG_TX_LLH_PTP_BUF_TS_MSB 0x501950UL
1662#define NIG_REG_RX_PTP_TS_MSB_ERR 0x501954UL
1663#define NIG_REG_TX_PTP_TS_MSB_ERR 0x501958UL
1664#define NIG_REG_TSGEN_SYNC_TIME_LSB 0x5088c0UL
1665#define NIG_REG_TSGEN_SYNC_TIME_MSB 0x5088c4UL
1666#define NIG_REG_TSGEN_RST_DRIFT_CNTR 0x5088d8UL
1667#define NIG_REG_TSGEN_DRIFT_CNTR_CONF 0x5088dcUL
1668#define NIG_REG_TS_OUTPUT_ENABLE_PDA 0x508870UL
1669#define NIG_REG_TIMESYNC_GEN_REG_BB 0x500d00UL
1670#define NIG_REG_TSGEN_FREE_CNT_VALUE_LSB 0x5088a8UL
1671#define NIG_REG_TSGEN_FREE_CNT_VALUE_MSB 0x5088acUL
1672#define NIG_REG_PTP_LATCH_OSTS_PKT_TIME 0x509040UL
1673#define PSWRQ2_REG_WR_MBS0 0x240400UL
1674
1675#define PGLUE_B_REG_PGL_ADDR_E8_F0_K2 0x2aaf98UL
1676#define PGLUE_B_REG_PGL_ADDR_EC_F0_K2 0x2aaf9cUL
1677#define PGLUE_B_REG_PGL_ADDR_F0_F0_K2 0x2aafa0UL
1678#define PGLUE_B_REG_PGL_ADDR_F4_F0_K2 0x2aafa4UL
1679#define PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE 0x2aae30UL
1680#define NIG_REG_TSGEN_FREECNT_UPDATE_K2 0x509008UL
1681#define CNIG_REG_NIG_PORT0_CONF_K2 0x218200UL
1682
1683#define NIG_REG_TX_EDPM_CTRL 0x501f0cUL
1684#define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN (0x1 << 0)
1685#define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN_SHIFT 0
1686#define NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN (0xff << 1)
1687#define NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN_SHIFT 1
1688
1689#define PRS_REG_SEARCH_GFT 0x1f11bcUL
1690#define PRS_REG_SEARCH_NON_IP_AS_GFT 0x1f11c0UL
1691#define PRS_REG_CM_HDR_GFT 0x1f11c8UL
1692#define PRS_REG_GFT_CAM 0x1f1100UL
1693#define PRS_REG_GFT_PROFILE_MASK_RAM 0x1f1000UL
1694#define PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT 0
1695#define PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT 8
1696#define PRS_REG_LOAD_L2_FILTER 0x1f0198UL
1697
1698#endif