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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <drm/drm_edid.h>
25#include <drm/drm_fourcc.h>
26#include <drm/drm_modeset_helper.h>
27#include <drm/drm_modeset_helper_vtables.h>
28#include <drm/drm_vblank.h>
29
30#include "amdgpu.h"
31#include "amdgpu_pm.h"
32#include "amdgpu_i2c.h"
33#include "vid.h"
34#include "atom.h"
35#include "amdgpu_atombios.h"
36#include "atombios_crtc.h"
37#include "atombios_encoders.h"
38#include "amdgpu_pll.h"
39#include "amdgpu_connectors.h"
40#include "amdgpu_display.h"
41#include "dce_v10_0.h"
42
43#include "dce/dce_10_0_d.h"
44#include "dce/dce_10_0_sh_mask.h"
45#include "dce/dce_10_0_enum.h"
46#include "oss/oss_3_0_d.h"
47#include "oss/oss_3_0_sh_mask.h"
48#include "gmc/gmc_8_1_d.h"
49#include "gmc/gmc_8_1_sh_mask.h"
50
51#include "ivsrcid/ivsrcid_vislands30.h"
52
53static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
54static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
55static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, int hpd);
56
57static const u32 crtc_offsets[] = {
58 CRTC0_REGISTER_OFFSET,
59 CRTC1_REGISTER_OFFSET,
60 CRTC2_REGISTER_OFFSET,
61 CRTC3_REGISTER_OFFSET,
62 CRTC4_REGISTER_OFFSET,
63 CRTC5_REGISTER_OFFSET,
64 CRTC6_REGISTER_OFFSET
65};
66
67static const u32 hpd_offsets[] = {
68 HPD0_REGISTER_OFFSET,
69 HPD1_REGISTER_OFFSET,
70 HPD2_REGISTER_OFFSET,
71 HPD3_REGISTER_OFFSET,
72 HPD4_REGISTER_OFFSET,
73 HPD5_REGISTER_OFFSET
74};
75
76static const uint32_t dig_offsets[] = {
77 DIG0_REGISTER_OFFSET,
78 DIG1_REGISTER_OFFSET,
79 DIG2_REGISTER_OFFSET,
80 DIG3_REGISTER_OFFSET,
81 DIG4_REGISTER_OFFSET,
82 DIG5_REGISTER_OFFSET,
83 DIG6_REGISTER_OFFSET
84};
85
86static const struct {
87 uint32_t reg;
88 uint32_t vblank;
89 uint32_t vline;
90 uint32_t hpd;
91
92} interrupt_status_offsets[] = { {
93 .reg = mmDISP_INTERRUPT_STATUS,
94 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
95 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
96 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
97}, {
98 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
99 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
100 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
101 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
102}, {
103 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
104 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
105 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
106 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
107}, {
108 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
109 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
110 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
111 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
112}, {
113 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
114 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
115 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
116 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
117}, {
118 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
119 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
120 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
121 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
122} };
123
124static const u32 golden_settings_tonga_a11[] = {
125 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
126 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
127 mmFBC_MISC, 0x1f311fff, 0x12300000,
128 mmHDMI_CONTROL, 0x31000111, 0x00000011,
129};
130
131static const u32 tonga_mgcg_cgcg_init[] = {
132 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
133 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
134};
135
136static const u32 golden_settings_fiji_a10[] = {
137 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
138 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
139 mmFBC_MISC, 0x1f311fff, 0x12300000,
140 mmHDMI_CONTROL, 0x31000111, 0x00000011,
141};
142
143static const u32 fiji_mgcg_cgcg_init[] = {
144 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
145 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
146};
147
148static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
149{
150 switch (adev->asic_type) {
151 case CHIP_FIJI:
152 amdgpu_device_program_register_sequence(adev,
153 fiji_mgcg_cgcg_init,
154 ARRAY_SIZE(fiji_mgcg_cgcg_init));
155 amdgpu_device_program_register_sequence(adev,
156 golden_settings_fiji_a10,
157 ARRAY_SIZE(golden_settings_fiji_a10));
158 break;
159 case CHIP_TONGA:
160 amdgpu_device_program_register_sequence(adev,
161 tonga_mgcg_cgcg_init,
162 ARRAY_SIZE(tonga_mgcg_cgcg_init));
163 amdgpu_device_program_register_sequence(adev,
164 golden_settings_tonga_a11,
165 ARRAY_SIZE(golden_settings_tonga_a11));
166 break;
167 default:
168 break;
169 }
170}
171
172static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
173 u32 block_offset, u32 reg)
174{
175 unsigned long flags;
176 u32 r;
177
178 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
179 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
180 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
181 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
182
183 return r;
184}
185
186static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
187 u32 block_offset, u32 reg, u32 v)
188{
189 unsigned long flags;
190
191 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
192 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
193 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
194 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
195}
196
197static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
198{
199 if (crtc >= adev->mode_info.num_crtc)
200 return 0;
201 else
202 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
203}
204
205static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
206{
207 unsigned i;
208
209 /* Enable pflip interrupts */
210 for (i = 0; i < adev->mode_info.num_crtc; i++)
211 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
212}
213
214static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
215{
216 unsigned i;
217
218 /* Disable pflip interrupts */
219 for (i = 0; i < adev->mode_info.num_crtc; i++)
220 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
221}
222
223/**
224 * dce_v10_0_page_flip - pageflip callback.
225 *
226 * @adev: amdgpu_device pointer
227 * @crtc_id: crtc to cleanup pageflip on
228 * @crtc_base: new address of the crtc (GPU MC address)
229 * @async: asynchronous flip
230 *
231 * Triggers the actual pageflip by updating the primary
232 * surface base address.
233 */
234static void dce_v10_0_page_flip(struct amdgpu_device *adev,
235 int crtc_id, u64 crtc_base, bool async)
236{
237 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
238 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
239 u32 tmp;
240
241 /* flip at hsync for async, default is vsync */
242 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
243 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
244 GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
245 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
246 /* update pitch */
247 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
248 fb->pitches[0] / fb->format->cpp[0]);
249 /* update the primary scanout address */
250 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
251 upper_32_bits(crtc_base));
252 /* writing to the low address triggers the update */
253 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
254 lower_32_bits(crtc_base));
255 /* post the write */
256 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
257}
258
259static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
260 u32 *vbl, u32 *position)
261{
262 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
263 return -EINVAL;
264
265 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
266 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
267
268 return 0;
269}
270
271/**
272 * dce_v10_0_hpd_sense - hpd sense callback.
273 *
274 * @adev: amdgpu_device pointer
275 * @hpd: hpd (hotplug detect) pin
276 *
277 * Checks if a digital monitor is connected (evergreen+).
278 * Returns true if connected, false if not connected.
279 */
280static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
281 enum amdgpu_hpd_id hpd)
282{
283 bool connected = false;
284
285 if (hpd >= adev->mode_info.num_hpd)
286 return connected;
287
288 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
289 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
290 connected = true;
291
292 return connected;
293}
294
295/**
296 * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
297 *
298 * @adev: amdgpu_device pointer
299 * @hpd: hpd (hotplug detect) pin
300 *
301 * Set the polarity of the hpd pin (evergreen+).
302 */
303static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
304 enum amdgpu_hpd_id hpd)
305{
306 u32 tmp;
307 bool connected = dce_v10_0_hpd_sense(adev, hpd);
308
309 if (hpd >= adev->mode_info.num_hpd)
310 return;
311
312 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
313 if (connected)
314 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
315 else
316 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
317 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
318}
319
320/**
321 * dce_v10_0_hpd_init - hpd setup callback.
322 *
323 * @adev: amdgpu_device pointer
324 *
325 * Setup the hpd pins used by the card (evergreen+).
326 * Enable the pin, set the polarity, and enable the hpd interrupts.
327 */
328static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
329{
330 struct drm_device *dev = adev_to_drm(adev);
331 struct drm_connector *connector;
332 struct drm_connector_list_iter iter;
333 u32 tmp;
334
335 drm_connector_list_iter_begin(dev, &iter);
336 drm_for_each_connector_iter(connector, &iter) {
337 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
338
339 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
340 continue;
341
342 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
343 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
344 /* don't try to enable hpd on eDP or LVDS avoid breaking the
345 * aux dp channel on imac and help (but not completely fix)
346 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
347 * also avoid interrupt storms during dpms.
348 */
349 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
350 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
351 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
352 continue;
353 }
354
355 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
356 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
357 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
358
359 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
360 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
361 DC_HPD_CONNECT_INT_DELAY,
362 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
363 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
364 DC_HPD_DISCONNECT_INT_DELAY,
365 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
366 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
367
368 dce_v10_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd);
369 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
370 amdgpu_irq_get(adev, &adev->hpd_irq,
371 amdgpu_connector->hpd.hpd);
372 }
373 drm_connector_list_iter_end(&iter);
374}
375
376/**
377 * dce_v10_0_hpd_fini - hpd tear down callback.
378 *
379 * @adev: amdgpu_device pointer
380 *
381 * Tear down the hpd pins used by the card (evergreen+).
382 * Disable the hpd interrupts.
383 */
384static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
385{
386 struct drm_device *dev = adev_to_drm(adev);
387 struct drm_connector *connector;
388 struct drm_connector_list_iter iter;
389 u32 tmp;
390
391 drm_connector_list_iter_begin(dev, &iter);
392 drm_for_each_connector_iter(connector, &iter) {
393 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
394
395 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
396 continue;
397
398 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
399 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
400 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
401
402 amdgpu_irq_put(adev, &adev->hpd_irq,
403 amdgpu_connector->hpd.hpd);
404 }
405 drm_connector_list_iter_end(&iter);
406}
407
408static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
409{
410 return mmDC_GPIO_HPD_A;
411}
412
413static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
414{
415 u32 crtc_hung = 0;
416 u32 crtc_status[6];
417 u32 i, j, tmp;
418
419 for (i = 0; i < adev->mode_info.num_crtc; i++) {
420 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
421 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
422 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
423 crtc_hung |= (1 << i);
424 }
425 }
426
427 for (j = 0; j < 10; j++) {
428 for (i = 0; i < adev->mode_info.num_crtc; i++) {
429 if (crtc_hung & (1 << i)) {
430 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
431 if (tmp != crtc_status[i])
432 crtc_hung &= ~(1 << i);
433 }
434 }
435 if (crtc_hung == 0)
436 return false;
437 udelay(100);
438 }
439
440 return true;
441}
442
443static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
444 bool render)
445{
446 u32 tmp;
447
448 /* Lockout access through VGA aperture*/
449 tmp = RREG32(mmVGA_HDP_CONTROL);
450 if (render)
451 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
452 else
453 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
454 WREG32(mmVGA_HDP_CONTROL, tmp);
455
456 /* disable VGA render */
457 tmp = RREG32(mmVGA_RENDER_CONTROL);
458 if (render)
459 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
460 else
461 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
462 WREG32(mmVGA_RENDER_CONTROL, tmp);
463}
464
465static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev)
466{
467 int num_crtc = 0;
468
469 switch (adev->asic_type) {
470 case CHIP_FIJI:
471 case CHIP_TONGA:
472 num_crtc = 6;
473 break;
474 default:
475 num_crtc = 0;
476 }
477 return num_crtc;
478}
479
480void dce_v10_0_disable_dce(struct amdgpu_device *adev)
481{
482 /*Disable VGA render and enabled crtc, if has DCE engine*/
483 if (amdgpu_atombios_has_dce_engine_info(adev)) {
484 u32 tmp;
485 int crtc_enabled, i;
486
487 dce_v10_0_set_vga_render_state(adev, false);
488
489 /*Disable crtc*/
490 for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) {
491 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
492 CRTC_CONTROL, CRTC_MASTER_EN);
493 if (crtc_enabled) {
494 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
495 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
496 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
497 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
498 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
499 }
500 }
501 }
502}
503
504static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
505{
506 struct drm_device *dev = encoder->dev;
507 struct amdgpu_device *adev = drm_to_adev(dev);
508 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
509 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
510 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
511 int bpc = 0;
512 u32 tmp = 0;
513 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
514
515 if (connector) {
516 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
517 bpc = amdgpu_connector_get_monitor_bpc(connector);
518 dither = amdgpu_connector->dither;
519 }
520
521 /* LVDS/eDP FMT is set up by atom */
522 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
523 return;
524
525 /* not needed for analog */
526 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
527 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
528 return;
529
530 if (bpc == 0)
531 return;
532
533 switch (bpc) {
534 case 6:
535 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
536 /* XXX sort out optimal dither settings */
537 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
538 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
539 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
540 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
541 } else {
542 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
543 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
544 }
545 break;
546 case 8:
547 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
548 /* XXX sort out optimal dither settings */
549 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
550 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
551 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
552 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
553 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
554 } else {
555 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
556 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
557 }
558 break;
559 case 10:
560 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
561 /* XXX sort out optimal dither settings */
562 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
563 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
564 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
565 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
566 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
567 } else {
568 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
569 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
570 }
571 break;
572 default:
573 /* not needed */
574 break;
575 }
576
577 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
578}
579
580
581/* display watermark setup */
582/**
583 * dce_v10_0_line_buffer_adjust - Set up the line buffer
584 *
585 * @adev: amdgpu_device pointer
586 * @amdgpu_crtc: the selected display controller
587 * @mode: the current display mode on the selected display
588 * controller
589 *
590 * Setup up the line buffer allocation for
591 * the selected display controller (CIK).
592 * Returns the line buffer size in pixels.
593 */
594static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
595 struct amdgpu_crtc *amdgpu_crtc,
596 struct drm_display_mode *mode)
597{
598 u32 tmp, buffer_alloc, i, mem_cfg;
599 u32 pipe_offset = amdgpu_crtc->crtc_id;
600 /*
601 * Line Buffer Setup
602 * There are 6 line buffers, one for each display controllers.
603 * There are 3 partitions per LB. Select the number of partitions
604 * to enable based on the display width. For display widths larger
605 * than 4096, you need use to use 2 display controllers and combine
606 * them using the stereo blender.
607 */
608 if (amdgpu_crtc->base.enabled && mode) {
609 if (mode->crtc_hdisplay < 1920) {
610 mem_cfg = 1;
611 buffer_alloc = 2;
612 } else if (mode->crtc_hdisplay < 2560) {
613 mem_cfg = 2;
614 buffer_alloc = 2;
615 } else if (mode->crtc_hdisplay < 4096) {
616 mem_cfg = 0;
617 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
618 } else {
619 DRM_DEBUG_KMS("Mode too big for LB!\n");
620 mem_cfg = 0;
621 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
622 }
623 } else {
624 mem_cfg = 1;
625 buffer_alloc = 0;
626 }
627
628 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
629 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
630 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
631
632 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
633 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
634 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
635
636 for (i = 0; i < adev->usec_timeout; i++) {
637 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
638 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
639 break;
640 udelay(1);
641 }
642
643 if (amdgpu_crtc->base.enabled && mode) {
644 switch (mem_cfg) {
645 case 0:
646 default:
647 return 4096 * 2;
648 case 1:
649 return 1920 * 2;
650 case 2:
651 return 2560 * 2;
652 }
653 }
654
655 /* controller not enabled, so no lb used */
656 return 0;
657}
658
659/**
660 * cik_get_number_of_dram_channels - get the number of dram channels
661 *
662 * @adev: amdgpu_device pointer
663 *
664 * Look up the number of video ram channels (CIK).
665 * Used for display watermark bandwidth calculations
666 * Returns the number of dram channels
667 */
668static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
669{
670 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
671
672 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
673 case 0:
674 default:
675 return 1;
676 case 1:
677 return 2;
678 case 2:
679 return 4;
680 case 3:
681 return 8;
682 case 4:
683 return 3;
684 case 5:
685 return 6;
686 case 6:
687 return 10;
688 case 7:
689 return 12;
690 case 8:
691 return 16;
692 }
693}
694
695struct dce10_wm_params {
696 u32 dram_channels; /* number of dram channels */
697 u32 yclk; /* bandwidth per dram data pin in kHz */
698 u32 sclk; /* engine clock in kHz */
699 u32 disp_clk; /* display clock in kHz */
700 u32 src_width; /* viewport width */
701 u32 active_time; /* active display time in ns */
702 u32 blank_time; /* blank time in ns */
703 bool interlaced; /* mode is interlaced */
704 fixed20_12 vsc; /* vertical scale ratio */
705 u32 num_heads; /* number of active crtcs */
706 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
707 u32 lb_size; /* line buffer allocated to pipe */
708 u32 vtaps; /* vertical scaler taps */
709};
710
711/**
712 * dce_v10_0_dram_bandwidth - get the dram bandwidth
713 *
714 * @wm: watermark calculation data
715 *
716 * Calculate the raw dram bandwidth (CIK).
717 * Used for display watermark bandwidth calculations
718 * Returns the dram bandwidth in MBytes/s
719 */
720static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
721{
722 /* Calculate raw DRAM Bandwidth */
723 fixed20_12 dram_efficiency; /* 0.7 */
724 fixed20_12 yclk, dram_channels, bandwidth;
725 fixed20_12 a;
726
727 a.full = dfixed_const(1000);
728 yclk.full = dfixed_const(wm->yclk);
729 yclk.full = dfixed_div(yclk, a);
730 dram_channels.full = dfixed_const(wm->dram_channels * 4);
731 a.full = dfixed_const(10);
732 dram_efficiency.full = dfixed_const(7);
733 dram_efficiency.full = dfixed_div(dram_efficiency, a);
734 bandwidth.full = dfixed_mul(dram_channels, yclk);
735 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
736
737 return dfixed_trunc(bandwidth);
738}
739
740/**
741 * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
742 *
743 * @wm: watermark calculation data
744 *
745 * Calculate the dram bandwidth used for display (CIK).
746 * Used for display watermark bandwidth calculations
747 * Returns the dram bandwidth for display in MBytes/s
748 */
749static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
750{
751 /* Calculate DRAM Bandwidth and the part allocated to display. */
752 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
753 fixed20_12 yclk, dram_channels, bandwidth;
754 fixed20_12 a;
755
756 a.full = dfixed_const(1000);
757 yclk.full = dfixed_const(wm->yclk);
758 yclk.full = dfixed_div(yclk, a);
759 dram_channels.full = dfixed_const(wm->dram_channels * 4);
760 a.full = dfixed_const(10);
761 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
762 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
763 bandwidth.full = dfixed_mul(dram_channels, yclk);
764 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
765
766 return dfixed_trunc(bandwidth);
767}
768
769/**
770 * dce_v10_0_data_return_bandwidth - get the data return bandwidth
771 *
772 * @wm: watermark calculation data
773 *
774 * Calculate the data return bandwidth used for display (CIK).
775 * Used for display watermark bandwidth calculations
776 * Returns the data return bandwidth in MBytes/s
777 */
778static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
779{
780 /* Calculate the display Data return Bandwidth */
781 fixed20_12 return_efficiency; /* 0.8 */
782 fixed20_12 sclk, bandwidth;
783 fixed20_12 a;
784
785 a.full = dfixed_const(1000);
786 sclk.full = dfixed_const(wm->sclk);
787 sclk.full = dfixed_div(sclk, a);
788 a.full = dfixed_const(10);
789 return_efficiency.full = dfixed_const(8);
790 return_efficiency.full = dfixed_div(return_efficiency, a);
791 a.full = dfixed_const(32);
792 bandwidth.full = dfixed_mul(a, sclk);
793 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
794
795 return dfixed_trunc(bandwidth);
796}
797
798/**
799 * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
800 *
801 * @wm: watermark calculation data
802 *
803 * Calculate the dmif bandwidth used for display (CIK).
804 * Used for display watermark bandwidth calculations
805 * Returns the dmif bandwidth in MBytes/s
806 */
807static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
808{
809 /* Calculate the DMIF Request Bandwidth */
810 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
811 fixed20_12 disp_clk, bandwidth;
812 fixed20_12 a, b;
813
814 a.full = dfixed_const(1000);
815 disp_clk.full = dfixed_const(wm->disp_clk);
816 disp_clk.full = dfixed_div(disp_clk, a);
817 a.full = dfixed_const(32);
818 b.full = dfixed_mul(a, disp_clk);
819
820 a.full = dfixed_const(10);
821 disp_clk_request_efficiency.full = dfixed_const(8);
822 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
823
824 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
825
826 return dfixed_trunc(bandwidth);
827}
828
829/**
830 * dce_v10_0_available_bandwidth - get the min available bandwidth
831 *
832 * @wm: watermark calculation data
833 *
834 * Calculate the min available bandwidth used for display (CIK).
835 * Used for display watermark bandwidth calculations
836 * Returns the min available bandwidth in MBytes/s
837 */
838static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
839{
840 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
841 u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
842 u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
843 u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
844
845 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
846}
847
848/**
849 * dce_v10_0_average_bandwidth - get the average available bandwidth
850 *
851 * @wm: watermark calculation data
852 *
853 * Calculate the average available bandwidth used for display (CIK).
854 * Used for display watermark bandwidth calculations
855 * Returns the average available bandwidth in MBytes/s
856 */
857static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
858{
859 /* Calculate the display mode Average Bandwidth
860 * DisplayMode should contain the source and destination dimensions,
861 * timing, etc.
862 */
863 fixed20_12 bpp;
864 fixed20_12 line_time;
865 fixed20_12 src_width;
866 fixed20_12 bandwidth;
867 fixed20_12 a;
868
869 a.full = dfixed_const(1000);
870 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
871 line_time.full = dfixed_div(line_time, a);
872 bpp.full = dfixed_const(wm->bytes_per_pixel);
873 src_width.full = dfixed_const(wm->src_width);
874 bandwidth.full = dfixed_mul(src_width, bpp);
875 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
876 bandwidth.full = dfixed_div(bandwidth, line_time);
877
878 return dfixed_trunc(bandwidth);
879}
880
881/**
882 * dce_v10_0_latency_watermark - get the latency watermark
883 *
884 * @wm: watermark calculation data
885 *
886 * Calculate the latency watermark (CIK).
887 * Used for display watermark bandwidth calculations
888 * Returns the latency watermark in ns
889 */
890static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
891{
892 /* First calculate the latency in ns */
893 u32 mc_latency = 2000; /* 2000 ns. */
894 u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
895 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
896 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
897 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
898 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
899 (wm->num_heads * cursor_line_pair_return_time);
900 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
901 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
902 u32 tmp, dmif_size = 12288;
903 fixed20_12 a, b, c;
904
905 if (wm->num_heads == 0)
906 return 0;
907
908 a.full = dfixed_const(2);
909 b.full = dfixed_const(1);
910 if ((wm->vsc.full > a.full) ||
911 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
912 (wm->vtaps >= 5) ||
913 ((wm->vsc.full >= a.full) && wm->interlaced))
914 max_src_lines_per_dst_line = 4;
915 else
916 max_src_lines_per_dst_line = 2;
917
918 a.full = dfixed_const(available_bandwidth);
919 b.full = dfixed_const(wm->num_heads);
920 a.full = dfixed_div(a, b);
921 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
922 tmp = min(dfixed_trunc(a), tmp);
923
924 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
925
926 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
927 b.full = dfixed_const(1000);
928 c.full = dfixed_const(lb_fill_bw);
929 b.full = dfixed_div(c, b);
930 a.full = dfixed_div(a, b);
931 line_fill_time = dfixed_trunc(a);
932
933 if (line_fill_time < wm->active_time)
934 return latency;
935 else
936 return latency + (line_fill_time - wm->active_time);
937
938}
939
940/**
941 * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
942 * average and available dram bandwidth
943 *
944 * @wm: watermark calculation data
945 *
946 * Check if the display average bandwidth fits in the display
947 * dram bandwidth (CIK).
948 * Used for display watermark bandwidth calculations
949 * Returns true if the display fits, false if not.
950 */
951static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
952{
953 if (dce_v10_0_average_bandwidth(wm) <=
954 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
955 return true;
956 else
957 return false;
958}
959
960/**
961 * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
962 * average and available bandwidth
963 *
964 * @wm: watermark calculation data
965 *
966 * Check if the display average bandwidth fits in the display
967 * available bandwidth (CIK).
968 * Used for display watermark bandwidth calculations
969 * Returns true if the display fits, false if not.
970 */
971static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
972{
973 if (dce_v10_0_average_bandwidth(wm) <=
974 (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
975 return true;
976 else
977 return false;
978}
979
980/**
981 * dce_v10_0_check_latency_hiding - check latency hiding
982 *
983 * @wm: watermark calculation data
984 *
985 * Check latency hiding (CIK).
986 * Used for display watermark bandwidth calculations
987 * Returns true if the display fits, false if not.
988 */
989static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
990{
991 u32 lb_partitions = wm->lb_size / wm->src_width;
992 u32 line_time = wm->active_time + wm->blank_time;
993 u32 latency_tolerant_lines;
994 u32 latency_hiding;
995 fixed20_12 a;
996
997 a.full = dfixed_const(1);
998 if (wm->vsc.full > a.full)
999 latency_tolerant_lines = 1;
1000 else {
1001 if (lb_partitions <= (wm->vtaps + 1))
1002 latency_tolerant_lines = 1;
1003 else
1004 latency_tolerant_lines = 2;
1005 }
1006
1007 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1008
1009 if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1010 return true;
1011 else
1012 return false;
1013}
1014
1015/**
1016 * dce_v10_0_program_watermarks - program display watermarks
1017 *
1018 * @adev: amdgpu_device pointer
1019 * @amdgpu_crtc: the selected display controller
1020 * @lb_size: line buffer size
1021 * @num_heads: number of display controllers in use
1022 *
1023 * Calculate and program the display watermarks for the
1024 * selected display controller (CIK).
1025 */
1026static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1027 struct amdgpu_crtc *amdgpu_crtc,
1028 u32 lb_size, u32 num_heads)
1029{
1030 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1031 struct dce10_wm_params wm_low, wm_high;
1032 u32 active_time;
1033 u32 line_time = 0;
1034 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1035 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1036
1037 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1038 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1039 (u32)mode->clock);
1040 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1041 (u32)mode->clock);
1042 line_time = min_t(u32, line_time, 65535);
1043
1044 /* watermark for high clocks */
1045 if (adev->pm.dpm_enabled) {
1046 wm_high.yclk =
1047 amdgpu_dpm_get_mclk(adev, false) * 10;
1048 wm_high.sclk =
1049 amdgpu_dpm_get_sclk(adev, false) * 10;
1050 } else {
1051 wm_high.yclk = adev->pm.current_mclk * 10;
1052 wm_high.sclk = adev->pm.current_sclk * 10;
1053 }
1054
1055 wm_high.disp_clk = mode->clock;
1056 wm_high.src_width = mode->crtc_hdisplay;
1057 wm_high.active_time = active_time;
1058 wm_high.blank_time = line_time - wm_high.active_time;
1059 wm_high.interlaced = false;
1060 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1061 wm_high.interlaced = true;
1062 wm_high.vsc = amdgpu_crtc->vsc;
1063 wm_high.vtaps = 1;
1064 if (amdgpu_crtc->rmx_type != RMX_OFF)
1065 wm_high.vtaps = 2;
1066 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1067 wm_high.lb_size = lb_size;
1068 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1069 wm_high.num_heads = num_heads;
1070
1071 /* set for high clocks */
1072 latency_watermark_a = min_t(u32, dce_v10_0_latency_watermark(&wm_high), 65535);
1073
1074 /* possibly force display priority to high */
1075 /* should really do this at mode validation time... */
1076 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1077 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1078 !dce_v10_0_check_latency_hiding(&wm_high) ||
1079 (adev->mode_info.disp_priority == 2)) {
1080 DRM_DEBUG_KMS("force priority to high\n");
1081 }
1082
1083 /* watermark for low clocks */
1084 if (adev->pm.dpm_enabled) {
1085 wm_low.yclk =
1086 amdgpu_dpm_get_mclk(adev, true) * 10;
1087 wm_low.sclk =
1088 amdgpu_dpm_get_sclk(adev, true) * 10;
1089 } else {
1090 wm_low.yclk = adev->pm.current_mclk * 10;
1091 wm_low.sclk = adev->pm.current_sclk * 10;
1092 }
1093
1094 wm_low.disp_clk = mode->clock;
1095 wm_low.src_width = mode->crtc_hdisplay;
1096 wm_low.active_time = active_time;
1097 wm_low.blank_time = line_time - wm_low.active_time;
1098 wm_low.interlaced = false;
1099 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1100 wm_low.interlaced = true;
1101 wm_low.vsc = amdgpu_crtc->vsc;
1102 wm_low.vtaps = 1;
1103 if (amdgpu_crtc->rmx_type != RMX_OFF)
1104 wm_low.vtaps = 2;
1105 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1106 wm_low.lb_size = lb_size;
1107 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1108 wm_low.num_heads = num_heads;
1109
1110 /* set for low clocks */
1111 latency_watermark_b = min_t(u32, dce_v10_0_latency_watermark(&wm_low), 65535);
1112
1113 /* possibly force display priority to high */
1114 /* should really do this at mode validation time... */
1115 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1116 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1117 !dce_v10_0_check_latency_hiding(&wm_low) ||
1118 (adev->mode_info.disp_priority == 2)) {
1119 DRM_DEBUG_KMS("force priority to high\n");
1120 }
1121 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1122 }
1123
1124 /* select wm A */
1125 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1126 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1127 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1128 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1129 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1130 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1131 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1132 /* select wm B */
1133 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1134 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1135 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1136 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1137 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1138 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1139 /* restore original selection */
1140 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1141
1142 /* save values for DPM */
1143 amdgpu_crtc->line_time = line_time;
1144 amdgpu_crtc->wm_high = latency_watermark_a;
1145 amdgpu_crtc->wm_low = latency_watermark_b;
1146 /* Save number of lines the linebuffer leads before the scanout */
1147 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1148}
1149
1150/**
1151 * dce_v10_0_bandwidth_update - program display watermarks
1152 *
1153 * @adev: amdgpu_device pointer
1154 *
1155 * Calculate and program the display watermarks and line
1156 * buffer allocation (CIK).
1157 */
1158static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1159{
1160 struct drm_display_mode *mode = NULL;
1161 u32 num_heads = 0, lb_size;
1162 int i;
1163
1164 amdgpu_display_update_priority(adev);
1165
1166 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1167 if (adev->mode_info.crtcs[i]->base.enabled)
1168 num_heads++;
1169 }
1170 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1171 mode = &adev->mode_info.crtcs[i]->base.mode;
1172 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1173 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1174 lb_size, num_heads);
1175 }
1176}
1177
1178static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1179{
1180 int i;
1181 u32 offset, tmp;
1182
1183 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1184 offset = adev->mode_info.audio.pin[i].offset;
1185 tmp = RREG32_AUDIO_ENDPT(offset,
1186 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1187 if (((tmp &
1188 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1189 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1190 adev->mode_info.audio.pin[i].connected = false;
1191 else
1192 adev->mode_info.audio.pin[i].connected = true;
1193 }
1194}
1195
1196static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1197{
1198 int i;
1199
1200 dce_v10_0_audio_get_connected_pins(adev);
1201
1202 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1203 if (adev->mode_info.audio.pin[i].connected)
1204 return &adev->mode_info.audio.pin[i];
1205 }
1206 DRM_ERROR("No connected audio pins found!\n");
1207 return NULL;
1208}
1209
1210static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1211{
1212 struct amdgpu_device *adev = drm_to_adev(encoder->dev);
1213 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1214 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1215 u32 tmp;
1216
1217 if (!dig || !dig->afmt || !dig->afmt->pin)
1218 return;
1219
1220 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1221 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1222 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1223}
1224
1225static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1226 struct drm_display_mode *mode)
1227{
1228 struct drm_device *dev = encoder->dev;
1229 struct amdgpu_device *adev = drm_to_adev(dev);
1230 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1231 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1232 struct drm_connector *connector;
1233 struct drm_connector_list_iter iter;
1234 struct amdgpu_connector *amdgpu_connector = NULL;
1235 u32 tmp;
1236 int interlace = 0;
1237
1238 if (!dig || !dig->afmt || !dig->afmt->pin)
1239 return;
1240
1241 drm_connector_list_iter_begin(dev, &iter);
1242 drm_for_each_connector_iter(connector, &iter) {
1243 if (connector->encoder == encoder) {
1244 amdgpu_connector = to_amdgpu_connector(connector);
1245 break;
1246 }
1247 }
1248 drm_connector_list_iter_end(&iter);
1249
1250 if (!amdgpu_connector) {
1251 DRM_ERROR("Couldn't find encoder's connector\n");
1252 return;
1253 }
1254
1255 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1256 interlace = 1;
1257 if (connector->latency_present[interlace]) {
1258 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1259 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1260 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1261 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1262 } else {
1263 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1264 VIDEO_LIPSYNC, 0);
1265 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1266 AUDIO_LIPSYNC, 0);
1267 }
1268 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1269 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1270}
1271
1272static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1273{
1274 struct drm_device *dev = encoder->dev;
1275 struct amdgpu_device *adev = drm_to_adev(dev);
1276 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1277 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1278 struct drm_connector *connector;
1279 struct drm_connector_list_iter iter;
1280 struct amdgpu_connector *amdgpu_connector = NULL;
1281 u32 tmp;
1282 u8 *sadb = NULL;
1283 int sad_count;
1284
1285 if (!dig || !dig->afmt || !dig->afmt->pin)
1286 return;
1287
1288 drm_connector_list_iter_begin(dev, &iter);
1289 drm_for_each_connector_iter(connector, &iter) {
1290 if (connector->encoder == encoder) {
1291 amdgpu_connector = to_amdgpu_connector(connector);
1292 break;
1293 }
1294 }
1295 drm_connector_list_iter_end(&iter);
1296
1297 if (!amdgpu_connector) {
1298 DRM_ERROR("Couldn't find encoder's connector\n");
1299 return;
1300 }
1301
1302 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb);
1303 if (sad_count < 0) {
1304 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1305 sad_count = 0;
1306 }
1307
1308 /* program the speaker allocation */
1309 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1310 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1311 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1312 DP_CONNECTION, 0);
1313 /* set HDMI mode */
1314 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1315 HDMI_CONNECTION, 1);
1316 if (sad_count)
1317 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1318 SPEAKER_ALLOCATION, sadb[0]);
1319 else
1320 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1321 SPEAKER_ALLOCATION, 5); /* stereo */
1322 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1323 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1324
1325 kfree(sadb);
1326}
1327
1328static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1329{
1330 struct drm_device *dev = encoder->dev;
1331 struct amdgpu_device *adev = drm_to_adev(dev);
1332 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1333 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1334 struct drm_connector *connector;
1335 struct drm_connector_list_iter iter;
1336 struct amdgpu_connector *amdgpu_connector = NULL;
1337 struct cea_sad *sads;
1338 int i, sad_count;
1339
1340 static const u16 eld_reg_to_type[][2] = {
1341 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1342 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1343 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1344 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1345 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1346 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1347 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1348 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1349 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1350 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1351 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1352 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1353 };
1354
1355 if (!dig || !dig->afmt || !dig->afmt->pin)
1356 return;
1357
1358 drm_connector_list_iter_begin(dev, &iter);
1359 drm_for_each_connector_iter(connector, &iter) {
1360 if (connector->encoder == encoder) {
1361 amdgpu_connector = to_amdgpu_connector(connector);
1362 break;
1363 }
1364 }
1365 drm_connector_list_iter_end(&iter);
1366
1367 if (!amdgpu_connector) {
1368 DRM_ERROR("Couldn't find encoder's connector\n");
1369 return;
1370 }
1371
1372 sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads);
1373 if (sad_count < 0)
1374 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1375 if (sad_count <= 0)
1376 return;
1377 BUG_ON(!sads);
1378
1379 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1380 u32 tmp = 0;
1381 u8 stereo_freqs = 0;
1382 int max_channels = -1;
1383 int j;
1384
1385 for (j = 0; j < sad_count; j++) {
1386 struct cea_sad *sad = &sads[j];
1387
1388 if (sad->format == eld_reg_to_type[i][1]) {
1389 if (sad->channels > max_channels) {
1390 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1391 MAX_CHANNELS, sad->channels);
1392 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1393 DESCRIPTOR_BYTE_2, sad->byte2);
1394 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1395 SUPPORTED_FREQUENCIES, sad->freq);
1396 max_channels = sad->channels;
1397 }
1398
1399 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1400 stereo_freqs |= sad->freq;
1401 else
1402 break;
1403 }
1404 }
1405
1406 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1407 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1408 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1409 }
1410
1411 kfree(sads);
1412}
1413
1414static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1415 struct amdgpu_audio_pin *pin,
1416 bool enable)
1417{
1418 if (!pin)
1419 return;
1420
1421 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1422 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1423}
1424
1425static const u32 pin_offsets[] = {
1426 AUD0_REGISTER_OFFSET,
1427 AUD1_REGISTER_OFFSET,
1428 AUD2_REGISTER_OFFSET,
1429 AUD3_REGISTER_OFFSET,
1430 AUD4_REGISTER_OFFSET,
1431 AUD5_REGISTER_OFFSET,
1432 AUD6_REGISTER_OFFSET,
1433};
1434
1435static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1436{
1437 int i;
1438
1439 if (!amdgpu_audio)
1440 return 0;
1441
1442 adev->mode_info.audio.enabled = true;
1443
1444 adev->mode_info.audio.num_pins = 7;
1445
1446 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1447 adev->mode_info.audio.pin[i].channels = -1;
1448 adev->mode_info.audio.pin[i].rate = -1;
1449 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1450 adev->mode_info.audio.pin[i].status_bits = 0;
1451 adev->mode_info.audio.pin[i].category_code = 0;
1452 adev->mode_info.audio.pin[i].connected = false;
1453 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1454 adev->mode_info.audio.pin[i].id = i;
1455 /* disable audio. it will be set up later */
1456 /* XXX remove once we switch to ip funcs */
1457 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1458 }
1459
1460 return 0;
1461}
1462
1463static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1464{
1465 int i;
1466
1467 if (!amdgpu_audio)
1468 return;
1469
1470 if (!adev->mode_info.audio.enabled)
1471 return;
1472
1473 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1474 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1475
1476 adev->mode_info.audio.enabled = false;
1477}
1478
1479/*
1480 * update the N and CTS parameters for a given pixel clock rate
1481 */
1482static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1483{
1484 struct drm_device *dev = encoder->dev;
1485 struct amdgpu_device *adev = drm_to_adev(dev);
1486 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1487 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1488 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1489 u32 tmp;
1490
1491 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1492 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1493 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1494 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1495 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1496 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1497
1498 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1499 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1500 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1501 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1502 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1503 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1504
1505 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1506 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1507 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1508 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1509 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1510 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1511
1512}
1513
1514/*
1515 * build a HDMI Video Info Frame
1516 */
1517static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1518 void *buffer, size_t size)
1519{
1520 struct drm_device *dev = encoder->dev;
1521 struct amdgpu_device *adev = drm_to_adev(dev);
1522 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1523 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1524 uint8_t *frame = buffer + 3;
1525 uint8_t *header = buffer;
1526
1527 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1528 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1529 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1530 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1531 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1532 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1533 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1534 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1535}
1536
1537static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1538{
1539 struct drm_device *dev = encoder->dev;
1540 struct amdgpu_device *adev = drm_to_adev(dev);
1541 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1542 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1543 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1544 u32 dto_phase = 24 * 1000;
1545 u32 dto_modulo = clock;
1546 u32 tmp;
1547
1548 if (!dig || !dig->afmt)
1549 return;
1550
1551 /* XXX two dtos; generally use dto0 for hdmi */
1552 /* Express [24MHz / target pixel clock] as an exact rational
1553 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1554 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1555 */
1556 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1557 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1558 amdgpu_crtc->crtc_id);
1559 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1560 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1561 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1562}
1563
1564/*
1565 * update the info frames with the data from the current display mode
1566 */
1567static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1568 struct drm_display_mode *mode)
1569{
1570 struct drm_device *dev = encoder->dev;
1571 struct amdgpu_device *adev = drm_to_adev(dev);
1572 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1573 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1574 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1575 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1576 struct hdmi_avi_infoframe frame;
1577 ssize_t err;
1578 u32 tmp;
1579 int bpc = 8;
1580
1581 if (!dig || !dig->afmt)
1582 return;
1583
1584 /* Silent, r600_hdmi_enable will raise WARN for us */
1585 if (!dig->afmt->enabled)
1586 return;
1587
1588 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1589 if (encoder->crtc) {
1590 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1591 bpc = amdgpu_crtc->bpc;
1592 }
1593
1594 /* disable audio prior to setting up hw */
1595 dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1596 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1597
1598 dce_v10_0_audio_set_dto(encoder, mode->clock);
1599
1600 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1601 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1602 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1603
1604 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1605
1606 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1607 switch (bpc) {
1608 case 0:
1609 case 6:
1610 case 8:
1611 case 16:
1612 default:
1613 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1614 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1615 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1616 connector->name, bpc);
1617 break;
1618 case 10:
1619 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1620 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1621 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1622 connector->name);
1623 break;
1624 case 12:
1625 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1626 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1627 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1628 connector->name);
1629 break;
1630 }
1631 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1632
1633 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1634 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1635 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1636 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1637 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1638
1639 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1640 /* enable audio info frames (frames won't be set until audio is enabled) */
1641 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1642 /* required for audio info values to be updated */
1643 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1644 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1645
1646 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1647 /* required for audio info values to be updated */
1648 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1649 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1650
1651 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1652 /* anything other than 0 */
1653 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1654 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1655
1656 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1657
1658 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1659 /* set the default audio delay */
1660 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1661 /* should be suffient for all audio modes and small enough for all hblanks */
1662 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1663 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1664
1665 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1666 /* allow 60958 channel status fields to be updated */
1667 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1668 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1669
1670 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1671 if (bpc > 8)
1672 /* clear SW CTS value */
1673 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1674 else
1675 /* select SW CTS value */
1676 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1677 /* allow hw to sent ACR packets when required */
1678 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1679 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1680
1681 dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1682
1683 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1684 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1685 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1686
1687 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1688 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1689 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1690
1691 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1692 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1693 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1694 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1695 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1696 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1697 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1698 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1699
1700 dce_v10_0_audio_write_speaker_allocation(encoder);
1701
1702 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1703 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1704
1705 dce_v10_0_afmt_audio_select_pin(encoder);
1706 dce_v10_0_audio_write_sad_regs(encoder);
1707 dce_v10_0_audio_write_latency_fields(encoder, mode);
1708
1709 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1710 if (err < 0) {
1711 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1712 return;
1713 }
1714
1715 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1716 if (err < 0) {
1717 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1718 return;
1719 }
1720
1721 dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1722
1723 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1724 /* enable AVI info frames */
1725 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1726 /* required for audio info values to be updated */
1727 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1728 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1729
1730 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1731 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1732 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1733
1734 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1735 /* send audio packets */
1736 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1737 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1738
1739 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1740 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1741 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1742 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1743
1744 /* enable audio after to setting up hw */
1745 dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1746}
1747
1748static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1749{
1750 struct drm_device *dev = encoder->dev;
1751 struct amdgpu_device *adev = drm_to_adev(dev);
1752 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1753 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1754
1755 if (!dig || !dig->afmt)
1756 return;
1757
1758 /* Silent, r600_hdmi_enable will raise WARN for us */
1759 if (enable && dig->afmt->enabled)
1760 return;
1761 if (!enable && !dig->afmt->enabled)
1762 return;
1763
1764 if (!enable && dig->afmt->pin) {
1765 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1766 dig->afmt->pin = NULL;
1767 }
1768
1769 dig->afmt->enabled = enable;
1770
1771 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1772 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1773}
1774
1775static int dce_v10_0_afmt_init(struct amdgpu_device *adev)
1776{
1777 int i;
1778
1779 for (i = 0; i < adev->mode_info.num_dig; i++)
1780 adev->mode_info.afmt[i] = NULL;
1781
1782 /* DCE10 has audio blocks tied to DIG encoders */
1783 for (i = 0; i < adev->mode_info.num_dig; i++) {
1784 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1785 if (adev->mode_info.afmt[i]) {
1786 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1787 adev->mode_info.afmt[i]->id = i;
1788 } else {
1789 int j;
1790 for (j = 0; j < i; j++) {
1791 kfree(adev->mode_info.afmt[j]);
1792 adev->mode_info.afmt[j] = NULL;
1793 }
1794 return -ENOMEM;
1795 }
1796 }
1797 return 0;
1798}
1799
1800static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
1801{
1802 int i;
1803
1804 for (i = 0; i < adev->mode_info.num_dig; i++) {
1805 kfree(adev->mode_info.afmt[i]);
1806 adev->mode_info.afmt[i] = NULL;
1807 }
1808}
1809
1810static const u32 vga_control_regs[6] = {
1811 mmD1VGA_CONTROL,
1812 mmD2VGA_CONTROL,
1813 mmD3VGA_CONTROL,
1814 mmD4VGA_CONTROL,
1815 mmD5VGA_CONTROL,
1816 mmD6VGA_CONTROL,
1817};
1818
1819static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
1820{
1821 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1822 struct drm_device *dev = crtc->dev;
1823 struct amdgpu_device *adev = drm_to_adev(dev);
1824 u32 vga_control;
1825
1826 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1827 if (enable)
1828 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1829 else
1830 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1831}
1832
1833static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
1834{
1835 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1836 struct drm_device *dev = crtc->dev;
1837 struct amdgpu_device *adev = drm_to_adev(dev);
1838
1839 if (enable)
1840 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1841 else
1842 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1843}
1844
1845static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
1846 struct drm_framebuffer *fb,
1847 int x, int y, int atomic)
1848{
1849 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1850 struct drm_device *dev = crtc->dev;
1851 struct amdgpu_device *adev = drm_to_adev(dev);
1852 struct drm_framebuffer *target_fb;
1853 struct drm_gem_object *obj;
1854 struct amdgpu_bo *abo;
1855 uint64_t fb_location, tiling_flags;
1856 uint32_t fb_format, fb_pitch_pixels;
1857 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
1858 u32 pipe_config;
1859 u32 tmp, viewport_w, viewport_h;
1860 int r;
1861 bool bypass_lut = false;
1862
1863 /* no fb bound */
1864 if (!atomic && !crtc->primary->fb) {
1865 DRM_DEBUG_KMS("No FB bound\n");
1866 return 0;
1867 }
1868
1869 if (atomic)
1870 target_fb = fb;
1871 else
1872 target_fb = crtc->primary->fb;
1873
1874 /* If atomic, assume fb object is pinned & idle & fenced and
1875 * just update base pointers
1876 */
1877 obj = target_fb->obj[0];
1878 abo = gem_to_amdgpu_bo(obj);
1879 r = amdgpu_bo_reserve(abo, false);
1880 if (unlikely(r != 0))
1881 return r;
1882
1883 if (!atomic) {
1884 abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1885 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1886 if (unlikely(r != 0)) {
1887 amdgpu_bo_unreserve(abo);
1888 return -EINVAL;
1889 }
1890 }
1891 fb_location = amdgpu_bo_gpu_offset(abo);
1892
1893 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1894 amdgpu_bo_unreserve(abo);
1895
1896 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1897
1898 switch (target_fb->format->format) {
1899 case DRM_FORMAT_C8:
1900 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
1901 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1902 break;
1903 case DRM_FORMAT_XRGB4444:
1904 case DRM_FORMAT_ARGB4444:
1905 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1906 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
1907#ifdef __BIG_ENDIAN
1908 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1909 ENDIAN_8IN16);
1910#endif
1911 break;
1912 case DRM_FORMAT_XRGB1555:
1913 case DRM_FORMAT_ARGB1555:
1914 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1915 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1916#ifdef __BIG_ENDIAN
1917 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1918 ENDIAN_8IN16);
1919#endif
1920 break;
1921 case DRM_FORMAT_BGRX5551:
1922 case DRM_FORMAT_BGRA5551:
1923 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1924 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
1925#ifdef __BIG_ENDIAN
1926 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1927 ENDIAN_8IN16);
1928#endif
1929 break;
1930 case DRM_FORMAT_RGB565:
1931 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1932 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1933#ifdef __BIG_ENDIAN
1934 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1935 ENDIAN_8IN16);
1936#endif
1937 break;
1938 case DRM_FORMAT_XRGB8888:
1939 case DRM_FORMAT_ARGB8888:
1940 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1941 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1942#ifdef __BIG_ENDIAN
1943 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1944 ENDIAN_8IN32);
1945#endif
1946 break;
1947 case DRM_FORMAT_XRGB2101010:
1948 case DRM_FORMAT_ARGB2101010:
1949 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1950 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1951#ifdef __BIG_ENDIAN
1952 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1953 ENDIAN_8IN32);
1954#endif
1955 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1956 bypass_lut = true;
1957 break;
1958 case DRM_FORMAT_BGRX1010102:
1959 case DRM_FORMAT_BGRA1010102:
1960 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1961 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
1962#ifdef __BIG_ENDIAN
1963 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1964 ENDIAN_8IN32);
1965#endif
1966 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1967 bypass_lut = true;
1968 break;
1969 case DRM_FORMAT_XBGR8888:
1970 case DRM_FORMAT_ABGR8888:
1971 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1972 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1973 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);
1974 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);
1975#ifdef __BIG_ENDIAN
1976 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1977 ENDIAN_8IN32);
1978#endif
1979 break;
1980 default:
1981 DRM_ERROR("Unsupported screen format %p4cc\n",
1982 &target_fb->format->format);
1983 return -EINVAL;
1984 }
1985
1986 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1987 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1988
1989 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1990 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1991 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1992 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1993 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1994
1995 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
1996 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
1997 ARRAY_2D_TILED_THIN1);
1998 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
1999 tile_split);
2000 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2001 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2002 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2003 mtaspect);
2004 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2005 ADDR_SURF_MICRO_TILING_DISPLAY);
2006 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2007 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2008 ARRAY_1D_TILED_THIN1);
2009 }
2010
2011 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2012 pipe_config);
2013
2014 dce_v10_0_vga_enable(crtc, false);
2015
2016 /* Make sure surface address is updated at vertical blank rather than
2017 * horizontal blank
2018 */
2019 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2020 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2021 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2022 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2023
2024 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2025 upper_32_bits(fb_location));
2026 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2027 upper_32_bits(fb_location));
2028 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2029 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2030 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2031 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2032 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2033 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2034
2035 /*
2036 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2037 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2038 * retain the full precision throughout the pipeline.
2039 */
2040 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2041 if (bypass_lut)
2042 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2043 else
2044 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2045 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2046
2047 if (bypass_lut)
2048 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2049
2050 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2051 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2052 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2053 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2054 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2055 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2056
2057 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2058 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2059
2060 dce_v10_0_grph_enable(crtc, true);
2061
2062 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2063 target_fb->height);
2064
2065 x &= ~3;
2066 y &= ~1;
2067 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2068 (x << 16) | y);
2069 viewport_w = crtc->mode.hdisplay;
2070 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2071 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2072 (viewport_w << 16) | viewport_h);
2073
2074 /* set pageflip to happen anywhere in vblank interval */
2075 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2076
2077 if (!atomic && fb && fb != crtc->primary->fb) {
2078 abo = gem_to_amdgpu_bo(fb->obj[0]);
2079 r = amdgpu_bo_reserve(abo, true);
2080 if (unlikely(r != 0))
2081 return r;
2082 amdgpu_bo_unpin(abo);
2083 amdgpu_bo_unreserve(abo);
2084 }
2085
2086 /* Bytes per pixel may have changed */
2087 dce_v10_0_bandwidth_update(adev);
2088
2089 return 0;
2090}
2091
2092static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2093 struct drm_display_mode *mode)
2094{
2095 struct drm_device *dev = crtc->dev;
2096 struct amdgpu_device *adev = drm_to_adev(dev);
2097 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2098 u32 tmp;
2099
2100 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2101 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2102 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2103 else
2104 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2105 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2106}
2107
2108static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2109{
2110 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2111 struct drm_device *dev = crtc->dev;
2112 struct amdgpu_device *adev = drm_to_adev(dev);
2113 u16 *r, *g, *b;
2114 int i;
2115 u32 tmp;
2116
2117 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2118
2119 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2120 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2121 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2122 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2123
2124 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2125 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2126 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2127
2128 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2129 tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2130 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2131
2132 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2133 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2134 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2135 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2136
2137 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2138
2139 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2140 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2141 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2142
2143 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2144 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2145 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2146
2147 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2148 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2149
2150 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2151 r = crtc->gamma_store;
2152 g = r + crtc->gamma_size;
2153 b = g + crtc->gamma_size;
2154 for (i = 0; i < 256; i++) {
2155 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2156 ((*r++ & 0xffc0) << 14) |
2157 ((*g++ & 0xffc0) << 4) |
2158 (*b++ >> 6));
2159 }
2160
2161 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2162 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2163 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2164 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2165 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2166
2167 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2168 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2169 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2170 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2171
2172 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2173 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2174 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2175 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2176
2177 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2178 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2179 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2180 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2181
2182 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2183 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2184 /* XXX this only needs to be programmed once per crtc at startup,
2185 * not sure where the best place for it is
2186 */
2187 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2188 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2189 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2190}
2191
2192static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2193{
2194 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2195 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2196
2197 switch (amdgpu_encoder->encoder_id) {
2198 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2199 if (dig->linkb)
2200 return 1;
2201 else
2202 return 0;
2203 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2204 if (dig->linkb)
2205 return 3;
2206 else
2207 return 2;
2208 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2209 if (dig->linkb)
2210 return 5;
2211 else
2212 return 4;
2213 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2214 return 6;
2215 default:
2216 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2217 return 0;
2218 }
2219}
2220
2221/**
2222 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2223 *
2224 * @crtc: drm crtc
2225 *
2226 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2227 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2228 * monitors a dedicated PPLL must be used. If a particular board has
2229 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2230 * as there is no need to program the PLL itself. If we are not able to
2231 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2232 * avoid messing up an existing monitor.
2233 *
2234 * Asic specific PLL information
2235 *
2236 * DCE 10.x
2237 * Tonga
2238 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2239 * CI
2240 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2241 *
2242 */
2243static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2244{
2245 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2246 struct drm_device *dev = crtc->dev;
2247 struct amdgpu_device *adev = drm_to_adev(dev);
2248 u32 pll_in_use;
2249 int pll;
2250
2251 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2252 if (adev->clock.dp_extclk)
2253 /* skip PPLL programming if using ext clock */
2254 return ATOM_PPLL_INVALID;
2255 else {
2256 /* use the same PPLL for all DP monitors */
2257 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2258 if (pll != ATOM_PPLL_INVALID)
2259 return pll;
2260 }
2261 } else {
2262 /* use the same PPLL for all monitors with the same clock */
2263 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2264 if (pll != ATOM_PPLL_INVALID)
2265 return pll;
2266 }
2267
2268 /* DCE10 has PPLL0, PPLL1, and PPLL2 */
2269 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2270 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2271 return ATOM_PPLL2;
2272 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2273 return ATOM_PPLL1;
2274 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2275 return ATOM_PPLL0;
2276 DRM_ERROR("unable to allocate a PPLL\n");
2277 return ATOM_PPLL_INVALID;
2278}
2279
2280static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2281{
2282 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2283 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2284 uint32_t cur_lock;
2285
2286 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2287 if (lock)
2288 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2289 else
2290 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2291 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2292}
2293
2294static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2295{
2296 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2297 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2298 u32 tmp;
2299
2300 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2301 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2302 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2303}
2304
2305static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2306{
2307 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2308 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2309 u32 tmp;
2310
2311 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2312 upper_32_bits(amdgpu_crtc->cursor_addr));
2313 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2314 lower_32_bits(amdgpu_crtc->cursor_addr));
2315
2316 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2317 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2318 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2319 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2320}
2321
2322static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2323 int x, int y)
2324{
2325 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2326 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2327 int xorigin = 0, yorigin = 0;
2328
2329 amdgpu_crtc->cursor_x = x;
2330 amdgpu_crtc->cursor_y = y;
2331
2332 /* avivo cursor are offset into the total surface */
2333 x += crtc->x;
2334 y += crtc->y;
2335 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2336
2337 if (x < 0) {
2338 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2339 x = 0;
2340 }
2341 if (y < 0) {
2342 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2343 y = 0;
2344 }
2345
2346 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2347 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2348 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2349 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2350
2351 return 0;
2352}
2353
2354static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2355 int x, int y)
2356{
2357 int ret;
2358
2359 dce_v10_0_lock_cursor(crtc, true);
2360 ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2361 dce_v10_0_lock_cursor(crtc, false);
2362
2363 return ret;
2364}
2365
2366static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2367 struct drm_file *file_priv,
2368 uint32_t handle,
2369 uint32_t width,
2370 uint32_t height,
2371 int32_t hot_x,
2372 int32_t hot_y)
2373{
2374 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2375 struct drm_gem_object *obj;
2376 struct amdgpu_bo *aobj;
2377 int ret;
2378
2379 if (!handle) {
2380 /* turn off cursor */
2381 dce_v10_0_hide_cursor(crtc);
2382 obj = NULL;
2383 goto unpin;
2384 }
2385
2386 if ((width > amdgpu_crtc->max_cursor_width) ||
2387 (height > amdgpu_crtc->max_cursor_height)) {
2388 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2389 return -EINVAL;
2390 }
2391
2392 obj = drm_gem_object_lookup(file_priv, handle);
2393 if (!obj) {
2394 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2395 return -ENOENT;
2396 }
2397
2398 aobj = gem_to_amdgpu_bo(obj);
2399 ret = amdgpu_bo_reserve(aobj, false);
2400 if (ret != 0) {
2401 drm_gem_object_put(obj);
2402 return ret;
2403 }
2404
2405 aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
2406 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2407 amdgpu_bo_unreserve(aobj);
2408 if (ret) {
2409 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2410 drm_gem_object_put(obj);
2411 return ret;
2412 }
2413 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2414
2415 dce_v10_0_lock_cursor(crtc, true);
2416
2417 if (width != amdgpu_crtc->cursor_width ||
2418 height != amdgpu_crtc->cursor_height ||
2419 hot_x != amdgpu_crtc->cursor_hot_x ||
2420 hot_y != amdgpu_crtc->cursor_hot_y) {
2421 int x, y;
2422
2423 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2424 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2425
2426 dce_v10_0_cursor_move_locked(crtc, x, y);
2427
2428 amdgpu_crtc->cursor_width = width;
2429 amdgpu_crtc->cursor_height = height;
2430 amdgpu_crtc->cursor_hot_x = hot_x;
2431 amdgpu_crtc->cursor_hot_y = hot_y;
2432 }
2433
2434 dce_v10_0_show_cursor(crtc);
2435 dce_v10_0_lock_cursor(crtc, false);
2436
2437unpin:
2438 if (amdgpu_crtc->cursor_bo) {
2439 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2440 ret = amdgpu_bo_reserve(aobj, true);
2441 if (likely(ret == 0)) {
2442 amdgpu_bo_unpin(aobj);
2443 amdgpu_bo_unreserve(aobj);
2444 }
2445 drm_gem_object_put(amdgpu_crtc->cursor_bo);
2446 }
2447
2448 amdgpu_crtc->cursor_bo = obj;
2449 return 0;
2450}
2451
2452static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2453{
2454 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2455
2456 if (amdgpu_crtc->cursor_bo) {
2457 dce_v10_0_lock_cursor(crtc, true);
2458
2459 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2460 amdgpu_crtc->cursor_y);
2461
2462 dce_v10_0_show_cursor(crtc);
2463
2464 dce_v10_0_lock_cursor(crtc, false);
2465 }
2466}
2467
2468static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2469 u16 *blue, uint32_t size,
2470 struct drm_modeset_acquire_ctx *ctx)
2471{
2472 dce_v10_0_crtc_load_lut(crtc);
2473
2474 return 0;
2475}
2476
2477static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2478{
2479 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2480
2481 drm_crtc_cleanup(crtc);
2482 kfree(amdgpu_crtc);
2483}
2484
2485static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
2486 .cursor_set2 = dce_v10_0_crtc_cursor_set2,
2487 .cursor_move = dce_v10_0_crtc_cursor_move,
2488 .gamma_set = dce_v10_0_crtc_gamma_set,
2489 .set_config = amdgpu_display_crtc_set_config,
2490 .destroy = dce_v10_0_crtc_destroy,
2491 .page_flip_target = amdgpu_display_crtc_page_flip_target,
2492 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
2493 .enable_vblank = amdgpu_enable_vblank_kms,
2494 .disable_vblank = amdgpu_disable_vblank_kms,
2495 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
2496};
2497
2498static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2499{
2500 struct drm_device *dev = crtc->dev;
2501 struct amdgpu_device *adev = drm_to_adev(dev);
2502 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2503 unsigned type;
2504
2505 switch (mode) {
2506 case DRM_MODE_DPMS_ON:
2507 amdgpu_crtc->enabled = true;
2508 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2509 dce_v10_0_vga_enable(crtc, true);
2510 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2511 dce_v10_0_vga_enable(crtc, false);
2512 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2513 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2514 amdgpu_crtc->crtc_id);
2515 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2516 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2517 drm_crtc_vblank_on(crtc);
2518 dce_v10_0_crtc_load_lut(crtc);
2519 break;
2520 case DRM_MODE_DPMS_STANDBY:
2521 case DRM_MODE_DPMS_SUSPEND:
2522 case DRM_MODE_DPMS_OFF:
2523 drm_crtc_vblank_off(crtc);
2524 if (amdgpu_crtc->enabled) {
2525 dce_v10_0_vga_enable(crtc, true);
2526 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2527 dce_v10_0_vga_enable(crtc, false);
2528 }
2529 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2530 amdgpu_crtc->enabled = false;
2531 break;
2532 }
2533 /* adjust pm to dpms */
2534 amdgpu_dpm_compute_clocks(adev);
2535}
2536
2537static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2538{
2539 /* disable crtc pair power gating before programming */
2540 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2541 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2542 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2543}
2544
2545static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2546{
2547 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2548 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2549}
2550
2551static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2552{
2553 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2554 struct drm_device *dev = crtc->dev;
2555 struct amdgpu_device *adev = drm_to_adev(dev);
2556 struct amdgpu_atom_ss ss;
2557 int i;
2558
2559 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2560 if (crtc->primary->fb) {
2561 int r;
2562 struct amdgpu_bo *abo;
2563
2564 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2565 r = amdgpu_bo_reserve(abo, true);
2566 if (unlikely(r))
2567 DRM_ERROR("failed to reserve abo before unpin\n");
2568 else {
2569 amdgpu_bo_unpin(abo);
2570 amdgpu_bo_unreserve(abo);
2571 }
2572 }
2573 /* disable the GRPH */
2574 dce_v10_0_grph_enable(crtc, false);
2575
2576 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2577
2578 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2579 if (adev->mode_info.crtcs[i] &&
2580 adev->mode_info.crtcs[i]->enabled &&
2581 i != amdgpu_crtc->crtc_id &&
2582 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2583 /* one other crtc is using this pll don't turn
2584 * off the pll
2585 */
2586 goto done;
2587 }
2588 }
2589
2590 switch (amdgpu_crtc->pll_id) {
2591 case ATOM_PPLL0:
2592 case ATOM_PPLL1:
2593 case ATOM_PPLL2:
2594 /* disable the ppll */
2595 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2596 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2597 break;
2598 default:
2599 break;
2600 }
2601done:
2602 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2603 amdgpu_crtc->adjusted_clock = 0;
2604 amdgpu_crtc->encoder = NULL;
2605 amdgpu_crtc->connector = NULL;
2606}
2607
2608static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2609 struct drm_display_mode *mode,
2610 struct drm_display_mode *adjusted_mode,
2611 int x, int y, struct drm_framebuffer *old_fb)
2612{
2613 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2614
2615 if (!amdgpu_crtc->adjusted_clock)
2616 return -EINVAL;
2617
2618 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2619 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2620 dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2621 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2622 amdgpu_atombios_crtc_scaler_setup(crtc);
2623 dce_v10_0_cursor_reset(crtc);
2624 /* update the hw version fpr dpm */
2625 amdgpu_crtc->hw_mode = *adjusted_mode;
2626
2627 return 0;
2628}
2629
2630static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2631 const struct drm_display_mode *mode,
2632 struct drm_display_mode *adjusted_mode)
2633{
2634 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2635 struct drm_device *dev = crtc->dev;
2636 struct drm_encoder *encoder;
2637
2638 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2639 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2640 if (encoder->crtc == crtc) {
2641 amdgpu_crtc->encoder = encoder;
2642 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2643 break;
2644 }
2645 }
2646 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2647 amdgpu_crtc->encoder = NULL;
2648 amdgpu_crtc->connector = NULL;
2649 return false;
2650 }
2651 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2652 return false;
2653 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2654 return false;
2655 /* pick pll */
2656 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2657 /* if we can't get a PPLL for a non-DP encoder, fail */
2658 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2659 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2660 return false;
2661
2662 return true;
2663}
2664
2665static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2666 struct drm_framebuffer *old_fb)
2667{
2668 return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2669}
2670
2671static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2672 struct drm_framebuffer *fb,
2673 int x, int y, enum mode_set_atomic state)
2674{
2675 return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
2676}
2677
2678static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2679 .dpms = dce_v10_0_crtc_dpms,
2680 .mode_fixup = dce_v10_0_crtc_mode_fixup,
2681 .mode_set = dce_v10_0_crtc_mode_set,
2682 .mode_set_base = dce_v10_0_crtc_set_base,
2683 .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2684 .prepare = dce_v10_0_crtc_prepare,
2685 .commit = dce_v10_0_crtc_commit,
2686 .disable = dce_v10_0_crtc_disable,
2687 .get_scanout_position = amdgpu_crtc_get_scanout_position,
2688};
2689
2690static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2691{
2692 struct amdgpu_crtc *amdgpu_crtc;
2693
2694 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2695 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2696 if (amdgpu_crtc == NULL)
2697 return -ENOMEM;
2698
2699 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2700
2701 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2702 amdgpu_crtc->crtc_id = index;
2703 adev->mode_info.crtcs[index] = amdgpu_crtc;
2704
2705 amdgpu_crtc->max_cursor_width = 128;
2706 amdgpu_crtc->max_cursor_height = 128;
2707 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2708 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2709
2710 switch (amdgpu_crtc->crtc_id) {
2711 case 0:
2712 default:
2713 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2714 break;
2715 case 1:
2716 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2717 break;
2718 case 2:
2719 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2720 break;
2721 case 3:
2722 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2723 break;
2724 case 4:
2725 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2726 break;
2727 case 5:
2728 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2729 break;
2730 }
2731
2732 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2733 amdgpu_crtc->adjusted_clock = 0;
2734 amdgpu_crtc->encoder = NULL;
2735 amdgpu_crtc->connector = NULL;
2736 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2737
2738 return 0;
2739}
2740
2741static int dce_v10_0_early_init(struct amdgpu_ip_block *ip_block)
2742{
2743 struct amdgpu_device *adev = ip_block->adev;
2744
2745 adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2746 adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2747
2748 dce_v10_0_set_display_funcs(adev);
2749
2750 adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
2751
2752 switch (adev->asic_type) {
2753 case CHIP_FIJI:
2754 case CHIP_TONGA:
2755 adev->mode_info.num_hpd = 6;
2756 adev->mode_info.num_dig = 7;
2757 break;
2758 default:
2759 /* FIXME: not supported yet */
2760 return -EINVAL;
2761 }
2762
2763 dce_v10_0_set_irq_funcs(adev);
2764
2765 return 0;
2766}
2767
2768static int dce_v10_0_sw_init(struct amdgpu_ip_block *ip_block)
2769{
2770 int r, i;
2771 struct amdgpu_device *adev = ip_block->adev;
2772
2773 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2774 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2775 if (r)
2776 return r;
2777 }
2778
2779 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
2780 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2781 if (r)
2782 return r;
2783 }
2784
2785 /* HPD hotplug */
2786 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2787 if (r)
2788 return r;
2789
2790 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
2791
2792 adev_to_drm(adev)->mode_config.async_page_flip = true;
2793
2794 adev_to_drm(adev)->mode_config.max_width = 16384;
2795 adev_to_drm(adev)->mode_config.max_height = 16384;
2796
2797 adev_to_drm(adev)->mode_config.preferred_depth = 24;
2798 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
2799
2800 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
2801
2802 r = amdgpu_display_modeset_create_props(adev);
2803 if (r)
2804 return r;
2805
2806 adev_to_drm(adev)->mode_config.max_width = 16384;
2807 adev_to_drm(adev)->mode_config.max_height = 16384;
2808
2809 /* allocate crtcs */
2810 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2811 r = dce_v10_0_crtc_init(adev, i);
2812 if (r)
2813 return r;
2814 }
2815
2816 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2817 amdgpu_display_print_display_setup(adev_to_drm(adev));
2818 else
2819 return -EINVAL;
2820
2821 /* setup afmt */
2822 r = dce_v10_0_afmt_init(adev);
2823 if (r)
2824 return r;
2825
2826 r = dce_v10_0_audio_init(adev);
2827 if (r)
2828 return r;
2829
2830 /* Disable vblank IRQs aggressively for power-saving */
2831 /* XXX: can this be enabled for DC? */
2832 adev_to_drm(adev)->vblank_disable_immediate = true;
2833
2834 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc);
2835 if (r)
2836 return r;
2837
2838 INIT_DELAYED_WORK(&adev->hotplug_work,
2839 amdgpu_display_hotplug_work_func);
2840
2841 drm_kms_helper_poll_init(adev_to_drm(adev));
2842
2843 adev->mode_info.mode_config_initialized = true;
2844 return 0;
2845}
2846
2847static int dce_v10_0_sw_fini(struct amdgpu_ip_block *ip_block)
2848{
2849 struct amdgpu_device *adev = ip_block->adev;
2850
2851 drm_edid_free(adev->mode_info.bios_hardcoded_edid);
2852
2853 drm_kms_helper_poll_fini(adev_to_drm(adev));
2854
2855 dce_v10_0_audio_fini(adev);
2856
2857 dce_v10_0_afmt_fini(adev);
2858
2859 drm_mode_config_cleanup(adev_to_drm(adev));
2860 adev->mode_info.mode_config_initialized = false;
2861
2862 return 0;
2863}
2864
2865static int dce_v10_0_hw_init(struct amdgpu_ip_block *ip_block)
2866{
2867 int i;
2868 struct amdgpu_device *adev = ip_block->adev;
2869
2870 dce_v10_0_init_golden_registers(adev);
2871
2872 /* disable vga render */
2873 dce_v10_0_set_vga_render_state(adev, false);
2874 /* init dig PHYs, disp eng pll */
2875 amdgpu_atombios_encoder_init_dig(adev);
2876 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2877
2878 /* initialize hpd */
2879 dce_v10_0_hpd_init(adev);
2880
2881 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2882 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2883 }
2884
2885 dce_v10_0_pageflip_interrupt_init(adev);
2886
2887 return 0;
2888}
2889
2890static int dce_v10_0_hw_fini(struct amdgpu_ip_block *ip_block)
2891{
2892 int i;
2893 struct amdgpu_device *adev = ip_block->adev;
2894
2895 dce_v10_0_hpd_fini(adev);
2896
2897 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2898 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2899 }
2900
2901 dce_v10_0_pageflip_interrupt_fini(adev);
2902
2903 flush_delayed_work(&adev->hotplug_work);
2904
2905 return 0;
2906}
2907
2908static int dce_v10_0_suspend(struct amdgpu_ip_block *ip_block)
2909{
2910 struct amdgpu_device *adev = ip_block->adev;
2911 int r;
2912
2913 r = amdgpu_display_suspend_helper(adev);
2914 if (r)
2915 return r;
2916
2917 adev->mode_info.bl_level =
2918 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2919
2920 return dce_v10_0_hw_fini(ip_block);
2921}
2922
2923static int dce_v10_0_resume(struct amdgpu_ip_block *ip_block)
2924{
2925 struct amdgpu_device *adev = ip_block->adev;
2926 int ret;
2927
2928 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2929 adev->mode_info.bl_level);
2930
2931 ret = dce_v10_0_hw_init(ip_block);
2932
2933 /* turn on the BL */
2934 if (adev->mode_info.bl_encoder) {
2935 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2936 adev->mode_info.bl_encoder);
2937 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2938 bl_level);
2939 }
2940 if (ret)
2941 return ret;
2942
2943 return amdgpu_display_resume_helper(adev);
2944}
2945
2946static bool dce_v10_0_is_idle(void *handle)
2947{
2948 return true;
2949}
2950
2951static bool dce_v10_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
2952{
2953 struct amdgpu_device *adev = ip_block->adev;
2954
2955 return dce_v10_0_is_display_hung(adev);
2956}
2957
2958static int dce_v10_0_soft_reset(struct amdgpu_ip_block *ip_block)
2959{
2960 u32 srbm_soft_reset = 0, tmp;
2961 struct amdgpu_device *adev = ip_block->adev;
2962
2963 if (dce_v10_0_is_display_hung(adev))
2964 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2965
2966 if (srbm_soft_reset) {
2967 tmp = RREG32(mmSRBM_SOFT_RESET);
2968 tmp |= srbm_soft_reset;
2969 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2970 WREG32(mmSRBM_SOFT_RESET, tmp);
2971 tmp = RREG32(mmSRBM_SOFT_RESET);
2972
2973 udelay(50);
2974
2975 tmp &= ~srbm_soft_reset;
2976 WREG32(mmSRBM_SOFT_RESET, tmp);
2977 tmp = RREG32(mmSRBM_SOFT_RESET);
2978
2979 /* Wait a little for things to settle down */
2980 udelay(50);
2981 }
2982 return 0;
2983}
2984
2985static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2986 int crtc,
2987 enum amdgpu_interrupt_state state)
2988{
2989 u32 lb_interrupt_mask;
2990
2991 if (crtc >= adev->mode_info.num_crtc) {
2992 DRM_DEBUG("invalid crtc %d\n", crtc);
2993 return;
2994 }
2995
2996 switch (state) {
2997 case AMDGPU_IRQ_STATE_DISABLE:
2998 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
2999 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3000 VBLANK_INTERRUPT_MASK, 0);
3001 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3002 break;
3003 case AMDGPU_IRQ_STATE_ENABLE:
3004 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3005 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3006 VBLANK_INTERRUPT_MASK, 1);
3007 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3008 break;
3009 default:
3010 break;
3011 }
3012}
3013
3014static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3015 int crtc,
3016 enum amdgpu_interrupt_state state)
3017{
3018 u32 lb_interrupt_mask;
3019
3020 if (crtc >= adev->mode_info.num_crtc) {
3021 DRM_DEBUG("invalid crtc %d\n", crtc);
3022 return;
3023 }
3024
3025 switch (state) {
3026 case AMDGPU_IRQ_STATE_DISABLE:
3027 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3028 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3029 VLINE_INTERRUPT_MASK, 0);
3030 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3031 break;
3032 case AMDGPU_IRQ_STATE_ENABLE:
3033 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3034 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3035 VLINE_INTERRUPT_MASK, 1);
3036 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3037 break;
3038 default:
3039 break;
3040 }
3041}
3042
3043static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
3044 struct amdgpu_irq_src *source,
3045 unsigned hpd,
3046 enum amdgpu_interrupt_state state)
3047{
3048 u32 tmp;
3049
3050 if (hpd >= adev->mode_info.num_hpd) {
3051 DRM_DEBUG("invalid hdp %d\n", hpd);
3052 return 0;
3053 }
3054
3055 switch (state) {
3056 case AMDGPU_IRQ_STATE_DISABLE:
3057 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3058 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3059 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3060 break;
3061 case AMDGPU_IRQ_STATE_ENABLE:
3062 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3063 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3064 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3065 break;
3066 default:
3067 break;
3068 }
3069
3070 return 0;
3071}
3072
3073static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3074 struct amdgpu_irq_src *source,
3075 unsigned type,
3076 enum amdgpu_interrupt_state state)
3077{
3078 switch (type) {
3079 case AMDGPU_CRTC_IRQ_VBLANK1:
3080 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3081 break;
3082 case AMDGPU_CRTC_IRQ_VBLANK2:
3083 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3084 break;
3085 case AMDGPU_CRTC_IRQ_VBLANK3:
3086 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3087 break;
3088 case AMDGPU_CRTC_IRQ_VBLANK4:
3089 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3090 break;
3091 case AMDGPU_CRTC_IRQ_VBLANK5:
3092 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3093 break;
3094 case AMDGPU_CRTC_IRQ_VBLANK6:
3095 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3096 break;
3097 case AMDGPU_CRTC_IRQ_VLINE1:
3098 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
3099 break;
3100 case AMDGPU_CRTC_IRQ_VLINE2:
3101 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
3102 break;
3103 case AMDGPU_CRTC_IRQ_VLINE3:
3104 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
3105 break;
3106 case AMDGPU_CRTC_IRQ_VLINE4:
3107 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
3108 break;
3109 case AMDGPU_CRTC_IRQ_VLINE5:
3110 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
3111 break;
3112 case AMDGPU_CRTC_IRQ_VLINE6:
3113 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
3114 break;
3115 default:
3116 break;
3117 }
3118 return 0;
3119}
3120
3121static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3122 struct amdgpu_irq_src *src,
3123 unsigned type,
3124 enum amdgpu_interrupt_state state)
3125{
3126 u32 reg;
3127
3128 if (type >= adev->mode_info.num_crtc) {
3129 DRM_ERROR("invalid pageflip crtc %d\n", type);
3130 return -EINVAL;
3131 }
3132
3133 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3134 if (state == AMDGPU_IRQ_STATE_DISABLE)
3135 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3136 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3137 else
3138 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3139 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3140
3141 return 0;
3142}
3143
3144static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3145 struct amdgpu_irq_src *source,
3146 struct amdgpu_iv_entry *entry)
3147{
3148 unsigned long flags;
3149 unsigned crtc_id;
3150 struct amdgpu_crtc *amdgpu_crtc;
3151 struct amdgpu_flip_work *works;
3152
3153 crtc_id = (entry->src_id - 8) >> 1;
3154 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3155
3156 if (crtc_id >= adev->mode_info.num_crtc) {
3157 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3158 return -EINVAL;
3159 }
3160
3161 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3162 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3163 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3164 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3165
3166 /* IRQ could occur when in initial stage */
3167 if (amdgpu_crtc == NULL)
3168 return 0;
3169
3170 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
3171 works = amdgpu_crtc->pflip_works;
3172 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3173 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3174 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3175 amdgpu_crtc->pflip_status,
3176 AMDGPU_FLIP_SUBMITTED);
3177 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3178 return 0;
3179 }
3180
3181 /* page flip completed. clean up */
3182 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3183 amdgpu_crtc->pflip_works = NULL;
3184
3185 /* wakeup usersapce */
3186 if (works->event)
3187 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3188
3189 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3190
3191 drm_crtc_vblank_put(&amdgpu_crtc->base);
3192 schedule_work(&works->unpin_work);
3193
3194 return 0;
3195}
3196
3197static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3198 int hpd)
3199{
3200 u32 tmp;
3201
3202 if (hpd >= adev->mode_info.num_hpd) {
3203 DRM_DEBUG("invalid hdp %d\n", hpd);
3204 return;
3205 }
3206
3207 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3208 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3209 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3210}
3211
3212static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3213 int crtc)
3214{
3215 u32 tmp;
3216
3217 if (crtc >= adev->mode_info.num_crtc) {
3218 DRM_DEBUG("invalid crtc %d\n", crtc);
3219 return;
3220 }
3221
3222 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3223 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3224 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3225}
3226
3227static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3228 int crtc)
3229{
3230 u32 tmp;
3231
3232 if (crtc >= adev->mode_info.num_crtc) {
3233 DRM_DEBUG("invalid crtc %d\n", crtc);
3234 return;
3235 }
3236
3237 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3238 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3239 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3240}
3241
3242static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3243 struct amdgpu_irq_src *source,
3244 struct amdgpu_iv_entry *entry)
3245{
3246 unsigned crtc = entry->src_id - 1;
3247 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3248 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, crtc);
3249
3250 switch (entry->src_data[0]) {
3251 case 0: /* vblank */
3252 if (disp_int & interrupt_status_offsets[crtc].vblank)
3253 dce_v10_0_crtc_vblank_int_ack(adev, crtc);
3254 else
3255 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3256
3257 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3258 drm_handle_vblank(adev_to_drm(adev), crtc);
3259 }
3260 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3261
3262 break;
3263 case 1: /* vline */
3264 if (disp_int & interrupt_status_offsets[crtc].vline)
3265 dce_v10_0_crtc_vline_int_ack(adev, crtc);
3266 else
3267 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3268
3269 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3270
3271 break;
3272 default:
3273 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3274 break;
3275 }
3276
3277 return 0;
3278}
3279
3280static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3281 struct amdgpu_irq_src *source,
3282 struct amdgpu_iv_entry *entry)
3283{
3284 uint32_t disp_int, mask;
3285 unsigned hpd;
3286
3287 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3288 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3289 return 0;
3290 }
3291
3292 hpd = entry->src_data[0];
3293 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3294 mask = interrupt_status_offsets[hpd].hpd;
3295
3296 if (disp_int & mask) {
3297 dce_v10_0_hpd_int_ack(adev, hpd);
3298 schedule_delayed_work(&adev->hotplug_work, 0);
3299 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3300 }
3301
3302 return 0;
3303}
3304
3305static int dce_v10_0_set_clockgating_state(void *handle,
3306 enum amd_clockgating_state state)
3307{
3308 return 0;
3309}
3310
3311static int dce_v10_0_set_powergating_state(void *handle,
3312 enum amd_powergating_state state)
3313{
3314 return 0;
3315}
3316
3317static const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3318 .name = "dce_v10_0",
3319 .early_init = dce_v10_0_early_init,
3320 .sw_init = dce_v10_0_sw_init,
3321 .sw_fini = dce_v10_0_sw_fini,
3322 .hw_init = dce_v10_0_hw_init,
3323 .hw_fini = dce_v10_0_hw_fini,
3324 .suspend = dce_v10_0_suspend,
3325 .resume = dce_v10_0_resume,
3326 .is_idle = dce_v10_0_is_idle,
3327 .check_soft_reset = dce_v10_0_check_soft_reset,
3328 .soft_reset = dce_v10_0_soft_reset,
3329 .set_clockgating_state = dce_v10_0_set_clockgating_state,
3330 .set_powergating_state = dce_v10_0_set_powergating_state,
3331};
3332
3333static void
3334dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3335 struct drm_display_mode *mode,
3336 struct drm_display_mode *adjusted_mode)
3337{
3338 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3339
3340 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3341
3342 /* need to call this here rather than in prepare() since we need some crtc info */
3343 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3344
3345 /* set scaler clears this on some chips */
3346 dce_v10_0_set_interleave(encoder->crtc, mode);
3347
3348 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3349 dce_v10_0_afmt_enable(encoder, true);
3350 dce_v10_0_afmt_setmode(encoder, adjusted_mode);
3351 }
3352}
3353
3354static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3355{
3356 struct amdgpu_device *adev = drm_to_adev(encoder->dev);
3357 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3358 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3359
3360 if ((amdgpu_encoder->active_device &
3361 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3362 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3363 ENCODER_OBJECT_ID_NONE)) {
3364 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3365 if (dig) {
3366 dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3367 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3368 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3369 }
3370 }
3371
3372 amdgpu_atombios_scratch_regs_lock(adev, true);
3373
3374 if (connector) {
3375 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3376
3377 /* select the clock/data port if it uses a router */
3378 if (amdgpu_connector->router.cd_valid)
3379 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3380
3381 /* turn eDP panel on for mode set */
3382 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3383 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3384 ATOM_TRANSMITTER_ACTION_POWER_ON);
3385 }
3386
3387 /* this is needed for the pll/ss setup to work correctly in some cases */
3388 amdgpu_atombios_encoder_set_crtc_source(encoder);
3389 /* set up the FMT blocks */
3390 dce_v10_0_program_fmt(encoder);
3391}
3392
3393static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3394{
3395 struct drm_device *dev = encoder->dev;
3396 struct amdgpu_device *adev = drm_to_adev(dev);
3397
3398 /* need to call this here as we need the crtc set up */
3399 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3400 amdgpu_atombios_scratch_regs_lock(adev, false);
3401}
3402
3403static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3404{
3405 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3406 struct amdgpu_encoder_atom_dig *dig;
3407
3408 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3409
3410 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3411 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3412 dce_v10_0_afmt_enable(encoder, false);
3413 dig = amdgpu_encoder->enc_priv;
3414 dig->dig_encoder = -1;
3415 }
3416 amdgpu_encoder->active_device = 0;
3417}
3418
3419/* these are handled by the primary encoders */
3420static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3421{
3422
3423}
3424
3425static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3426{
3427
3428}
3429
3430static void
3431dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3432 struct drm_display_mode *mode,
3433 struct drm_display_mode *adjusted_mode)
3434{
3435
3436}
3437
3438static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3439{
3440
3441}
3442
3443static void
3444dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3445{
3446
3447}
3448
3449static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3450 .dpms = dce_v10_0_ext_dpms,
3451 .prepare = dce_v10_0_ext_prepare,
3452 .mode_set = dce_v10_0_ext_mode_set,
3453 .commit = dce_v10_0_ext_commit,
3454 .disable = dce_v10_0_ext_disable,
3455 /* no detect for TMDS/LVDS yet */
3456};
3457
3458static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3459 .dpms = amdgpu_atombios_encoder_dpms,
3460 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3461 .prepare = dce_v10_0_encoder_prepare,
3462 .mode_set = dce_v10_0_encoder_mode_set,
3463 .commit = dce_v10_0_encoder_commit,
3464 .disable = dce_v10_0_encoder_disable,
3465 .detect = amdgpu_atombios_encoder_dig_detect,
3466};
3467
3468static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3469 .dpms = amdgpu_atombios_encoder_dpms,
3470 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3471 .prepare = dce_v10_0_encoder_prepare,
3472 .mode_set = dce_v10_0_encoder_mode_set,
3473 .commit = dce_v10_0_encoder_commit,
3474 .detect = amdgpu_atombios_encoder_dac_detect,
3475};
3476
3477static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3478{
3479 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3480 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3481 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3482 kfree(amdgpu_encoder->enc_priv);
3483 drm_encoder_cleanup(encoder);
3484 kfree(amdgpu_encoder);
3485}
3486
3487static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3488 .destroy = dce_v10_0_encoder_destroy,
3489};
3490
3491static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3492 uint32_t encoder_enum,
3493 uint32_t supported_device,
3494 u16 caps)
3495{
3496 struct drm_device *dev = adev_to_drm(adev);
3497 struct drm_encoder *encoder;
3498 struct amdgpu_encoder *amdgpu_encoder;
3499
3500 /* see if we already added it */
3501 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3502 amdgpu_encoder = to_amdgpu_encoder(encoder);
3503 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3504 amdgpu_encoder->devices |= supported_device;
3505 return;
3506 }
3507
3508 }
3509
3510 /* add a new one */
3511 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3512 if (!amdgpu_encoder)
3513 return;
3514
3515 encoder = &amdgpu_encoder->base;
3516 switch (adev->mode_info.num_crtc) {
3517 case 1:
3518 encoder->possible_crtcs = 0x1;
3519 break;
3520 case 2:
3521 default:
3522 encoder->possible_crtcs = 0x3;
3523 break;
3524 case 4:
3525 encoder->possible_crtcs = 0xf;
3526 break;
3527 case 6:
3528 encoder->possible_crtcs = 0x3f;
3529 break;
3530 }
3531
3532 amdgpu_encoder->enc_priv = NULL;
3533
3534 amdgpu_encoder->encoder_enum = encoder_enum;
3535 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3536 amdgpu_encoder->devices = supported_device;
3537 amdgpu_encoder->rmx_type = RMX_OFF;
3538 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3539 amdgpu_encoder->is_ext_encoder = false;
3540 amdgpu_encoder->caps = caps;
3541
3542 switch (amdgpu_encoder->encoder_id) {
3543 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3544 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3545 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3546 DRM_MODE_ENCODER_DAC, NULL);
3547 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
3548 break;
3549 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3550 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3551 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3552 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3553 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3554 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3555 amdgpu_encoder->rmx_type = RMX_FULL;
3556 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3557 DRM_MODE_ENCODER_LVDS, NULL);
3558 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3559 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3560 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3561 DRM_MODE_ENCODER_DAC, NULL);
3562 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3563 } else {
3564 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3565 DRM_MODE_ENCODER_TMDS, NULL);
3566 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3567 }
3568 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
3569 break;
3570 case ENCODER_OBJECT_ID_SI170B:
3571 case ENCODER_OBJECT_ID_CH7303:
3572 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3573 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3574 case ENCODER_OBJECT_ID_TITFP513:
3575 case ENCODER_OBJECT_ID_VT1623:
3576 case ENCODER_OBJECT_ID_HDMI_SI1930:
3577 case ENCODER_OBJECT_ID_TRAVIS:
3578 case ENCODER_OBJECT_ID_NUTMEG:
3579 /* these are handled by the primary encoders */
3580 amdgpu_encoder->is_ext_encoder = true;
3581 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3582 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3583 DRM_MODE_ENCODER_LVDS, NULL);
3584 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3585 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3586 DRM_MODE_ENCODER_DAC, NULL);
3587 else
3588 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3589 DRM_MODE_ENCODER_TMDS, NULL);
3590 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
3591 break;
3592 }
3593}
3594
3595static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3596 .bandwidth_update = &dce_v10_0_bandwidth_update,
3597 .vblank_get_counter = &dce_v10_0_vblank_get_counter,
3598 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3599 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3600 .hpd_sense = &dce_v10_0_hpd_sense,
3601 .hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3602 .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3603 .page_flip = &dce_v10_0_page_flip,
3604 .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3605 .add_encoder = &dce_v10_0_encoder_add,
3606 .add_connector = &amdgpu_connector_add,
3607};
3608
3609static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3610{
3611 adev->mode_info.funcs = &dce_v10_0_display_funcs;
3612}
3613
3614static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3615 .set = dce_v10_0_set_crtc_irq_state,
3616 .process = dce_v10_0_crtc_irq,
3617};
3618
3619static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3620 .set = dce_v10_0_set_pageflip_irq_state,
3621 .process = dce_v10_0_pageflip_irq,
3622};
3623
3624static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3625 .set = dce_v10_0_set_hpd_irq_state,
3626 .process = dce_v10_0_hpd_irq,
3627};
3628
3629static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3630{
3631 if (adev->mode_info.num_crtc > 0)
3632 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3633 else
3634 adev->crtc_irq.num_types = 0;
3635 adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3636
3637 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3638 adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3639
3640 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3641 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3642}
3643
3644const struct amdgpu_ip_block_version dce_v10_0_ip_block = {
3645 .type = AMD_IP_BLOCK_TYPE_DCE,
3646 .major = 10,
3647 .minor = 0,
3648 .rev = 0,
3649 .funcs = &dce_v10_0_ip_funcs,
3650};
3651
3652const struct amdgpu_ip_block_version dce_v10_1_ip_block = {
3653 .type = AMD_IP_BLOCK_TYPE_DCE,
3654 .major = 10,
3655 .minor = 1,
3656 .rev = 0,
3657 .funcs = &dce_v10_0_ip_funcs,
3658};
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "drmP.h"
24#include "amdgpu.h"
25#include "amdgpu_pm.h"
26#include "amdgpu_i2c.h"
27#include "vid.h"
28#include "atom.h"
29#include "amdgpu_atombios.h"
30#include "atombios_crtc.h"
31#include "atombios_encoders.h"
32#include "amdgpu_pll.h"
33#include "amdgpu_connectors.h"
34#include "dce_v10_0.h"
35
36#include "dce/dce_10_0_d.h"
37#include "dce/dce_10_0_sh_mask.h"
38#include "dce/dce_10_0_enum.h"
39#include "oss/oss_3_0_d.h"
40#include "oss/oss_3_0_sh_mask.h"
41#include "gmc/gmc_8_1_d.h"
42#include "gmc/gmc_8_1_sh_mask.h"
43
44static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
45static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
46
47static const u32 crtc_offsets[] =
48{
49 CRTC0_REGISTER_OFFSET,
50 CRTC1_REGISTER_OFFSET,
51 CRTC2_REGISTER_OFFSET,
52 CRTC3_REGISTER_OFFSET,
53 CRTC4_REGISTER_OFFSET,
54 CRTC5_REGISTER_OFFSET,
55 CRTC6_REGISTER_OFFSET
56};
57
58static const u32 hpd_offsets[] =
59{
60 HPD0_REGISTER_OFFSET,
61 HPD1_REGISTER_OFFSET,
62 HPD2_REGISTER_OFFSET,
63 HPD3_REGISTER_OFFSET,
64 HPD4_REGISTER_OFFSET,
65 HPD5_REGISTER_OFFSET
66};
67
68static const uint32_t dig_offsets[] = {
69 DIG0_REGISTER_OFFSET,
70 DIG1_REGISTER_OFFSET,
71 DIG2_REGISTER_OFFSET,
72 DIG3_REGISTER_OFFSET,
73 DIG4_REGISTER_OFFSET,
74 DIG5_REGISTER_OFFSET,
75 DIG6_REGISTER_OFFSET
76};
77
78static const struct {
79 uint32_t reg;
80 uint32_t vblank;
81 uint32_t vline;
82 uint32_t hpd;
83
84} interrupt_status_offsets[] = { {
85 .reg = mmDISP_INTERRUPT_STATUS,
86 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
87 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
88 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
89}, {
90 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
91 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
92 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
93 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
94}, {
95 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
96 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
97 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
98 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
99}, {
100 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
101 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
102 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
103 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
104}, {
105 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
106 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
107 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
108 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
109}, {
110 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
111 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
112 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
113 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
114} };
115
116static const u32 golden_settings_tonga_a11[] =
117{
118 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
119 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
120 mmFBC_MISC, 0x1f311fff, 0x12300000,
121 mmHDMI_CONTROL, 0x31000111, 0x00000011,
122};
123
124static const u32 tonga_mgcg_cgcg_init[] =
125{
126 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
127 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
128};
129
130static const u32 golden_settings_fiji_a10[] =
131{
132 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
133 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
134 mmFBC_MISC, 0x1f311fff, 0x12300000,
135 mmHDMI_CONTROL, 0x31000111, 0x00000011,
136};
137
138static const u32 fiji_mgcg_cgcg_init[] =
139{
140 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
141 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
142};
143
144static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
145{
146 switch (adev->asic_type) {
147 case CHIP_FIJI:
148 amdgpu_program_register_sequence(adev,
149 fiji_mgcg_cgcg_init,
150 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
151 amdgpu_program_register_sequence(adev,
152 golden_settings_fiji_a10,
153 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
154 break;
155 case CHIP_TONGA:
156 amdgpu_program_register_sequence(adev,
157 tonga_mgcg_cgcg_init,
158 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
159 amdgpu_program_register_sequence(adev,
160 golden_settings_tonga_a11,
161 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
162 break;
163 default:
164 break;
165 }
166}
167
168static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
169 u32 block_offset, u32 reg)
170{
171 unsigned long flags;
172 u32 r;
173
174 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
175 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
176 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
177 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
178
179 return r;
180}
181
182static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
183 u32 block_offset, u32 reg, u32 v)
184{
185 unsigned long flags;
186
187 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
188 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
189 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
190 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
191}
192
193static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
194{
195 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
196 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
197 return true;
198 else
199 return false;
200}
201
202static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
203{
204 u32 pos1, pos2;
205
206 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
207 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
208
209 if (pos1 != pos2)
210 return true;
211 else
212 return false;
213}
214
215/**
216 * dce_v10_0_vblank_wait - vblank wait asic callback.
217 *
218 * @adev: amdgpu_device pointer
219 * @crtc: crtc to wait for vblank on
220 *
221 * Wait for vblank on the requested crtc (evergreen+).
222 */
223static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc)
224{
225 unsigned i = 100;
226
227 if (crtc >= adev->mode_info.num_crtc)
228 return;
229
230 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
231 return;
232
233 /* depending on when we hit vblank, we may be close to active; if so,
234 * wait for another frame.
235 */
236 while (dce_v10_0_is_in_vblank(adev, crtc)) {
237 if (i++ == 100) {
238 i = 0;
239 if (!dce_v10_0_is_counter_moving(adev, crtc))
240 break;
241 }
242 }
243
244 while (!dce_v10_0_is_in_vblank(adev, crtc)) {
245 if (i++ == 100) {
246 i = 0;
247 if (!dce_v10_0_is_counter_moving(adev, crtc))
248 break;
249 }
250 }
251}
252
253static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
254{
255 if (crtc >= adev->mode_info.num_crtc)
256 return 0;
257 else
258 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
259}
260
261static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
262{
263 unsigned i;
264
265 /* Enable pflip interrupts */
266 for (i = 0; i < adev->mode_info.num_crtc; i++)
267 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
268}
269
270static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
271{
272 unsigned i;
273
274 /* Disable pflip interrupts */
275 for (i = 0; i < adev->mode_info.num_crtc; i++)
276 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
277}
278
279/**
280 * dce_v10_0_page_flip - pageflip callback.
281 *
282 * @adev: amdgpu_device pointer
283 * @crtc_id: crtc to cleanup pageflip on
284 * @crtc_base: new address of the crtc (GPU MC address)
285 *
286 * Triggers the actual pageflip by updating the primary
287 * surface base address.
288 */
289static void dce_v10_0_page_flip(struct amdgpu_device *adev,
290 int crtc_id, u64 crtc_base, bool async)
291{
292 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
293 u32 tmp;
294
295 /* flip at hsync for async, default is vsync */
296 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
297 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
298 GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
299 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
300 /* update the primary scanout address */
301 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
302 upper_32_bits(crtc_base));
303 /* writing to the low address triggers the update */
304 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
305 lower_32_bits(crtc_base));
306 /* post the write */
307 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
308}
309
310static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
311 u32 *vbl, u32 *position)
312{
313 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
314 return -EINVAL;
315
316 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
317 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
318
319 return 0;
320}
321
322/**
323 * dce_v10_0_hpd_sense - hpd sense callback.
324 *
325 * @adev: amdgpu_device pointer
326 * @hpd: hpd (hotplug detect) pin
327 *
328 * Checks if a digital monitor is connected (evergreen+).
329 * Returns true if connected, false if not connected.
330 */
331static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
332 enum amdgpu_hpd_id hpd)
333{
334 bool connected = false;
335
336 if (hpd >= adev->mode_info.num_hpd)
337 return connected;
338
339 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
340 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
341 connected = true;
342
343 return connected;
344}
345
346/**
347 * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
348 *
349 * @adev: amdgpu_device pointer
350 * @hpd: hpd (hotplug detect) pin
351 *
352 * Set the polarity of the hpd pin (evergreen+).
353 */
354static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
355 enum amdgpu_hpd_id hpd)
356{
357 u32 tmp;
358 bool connected = dce_v10_0_hpd_sense(adev, hpd);
359
360 if (hpd >= adev->mode_info.num_hpd)
361 return;
362
363 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
364 if (connected)
365 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
366 else
367 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
368 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
369}
370
371/**
372 * dce_v10_0_hpd_init - hpd setup callback.
373 *
374 * @adev: amdgpu_device pointer
375 *
376 * Setup the hpd pins used by the card (evergreen+).
377 * Enable the pin, set the polarity, and enable the hpd interrupts.
378 */
379static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
380{
381 struct drm_device *dev = adev->ddev;
382 struct drm_connector *connector;
383 u32 tmp;
384
385 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
386 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
387
388 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
389 continue;
390
391 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
392 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
393 /* don't try to enable hpd on eDP or LVDS avoid breaking the
394 * aux dp channel on imac and help (but not completely fix)
395 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
396 * also avoid interrupt storms during dpms.
397 */
398 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
399 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
400 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
401 continue;
402 }
403
404 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
405 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
406 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
407
408 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
409 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
410 DC_HPD_CONNECT_INT_DELAY,
411 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
412 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
413 DC_HPD_DISCONNECT_INT_DELAY,
414 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
415 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
416
417 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
418 amdgpu_irq_get(adev, &adev->hpd_irq,
419 amdgpu_connector->hpd.hpd);
420 }
421}
422
423/**
424 * dce_v10_0_hpd_fini - hpd tear down callback.
425 *
426 * @adev: amdgpu_device pointer
427 *
428 * Tear down the hpd pins used by the card (evergreen+).
429 * Disable the hpd interrupts.
430 */
431static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
432{
433 struct drm_device *dev = adev->ddev;
434 struct drm_connector *connector;
435 u32 tmp;
436
437 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
438 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
439
440 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
441 continue;
442
443 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
444 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
445 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
446
447 amdgpu_irq_put(adev, &adev->hpd_irq,
448 amdgpu_connector->hpd.hpd);
449 }
450}
451
452static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
453{
454 return mmDC_GPIO_HPD_A;
455}
456
457static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
458{
459 u32 crtc_hung = 0;
460 u32 crtc_status[6];
461 u32 i, j, tmp;
462
463 for (i = 0; i < adev->mode_info.num_crtc; i++) {
464 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
465 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
466 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
467 crtc_hung |= (1 << i);
468 }
469 }
470
471 for (j = 0; j < 10; j++) {
472 for (i = 0; i < adev->mode_info.num_crtc; i++) {
473 if (crtc_hung & (1 << i)) {
474 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
475 if (tmp != crtc_status[i])
476 crtc_hung &= ~(1 << i);
477 }
478 }
479 if (crtc_hung == 0)
480 return false;
481 udelay(100);
482 }
483
484 return true;
485}
486
487static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev,
488 struct amdgpu_mode_mc_save *save)
489{
490 u32 crtc_enabled, tmp;
491 int i;
492
493 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
494 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
495
496 /* disable VGA render */
497 tmp = RREG32(mmVGA_RENDER_CONTROL);
498 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
499 WREG32(mmVGA_RENDER_CONTROL, tmp);
500
501 /* blank the display controllers */
502 for (i = 0; i < adev->mode_info.num_crtc; i++) {
503 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
504 CRTC_CONTROL, CRTC_MASTER_EN);
505 if (crtc_enabled) {
506#if 0
507 u32 frame_count;
508 int j;
509
510 save->crtc_enabled[i] = true;
511 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
512 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
513 amdgpu_display_vblank_wait(adev, i);
514 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
515 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
516 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
517 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
518 }
519 /* wait for the next frame */
520 frame_count = amdgpu_display_vblank_get_counter(adev, i);
521 for (j = 0; j < adev->usec_timeout; j++) {
522 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
523 break;
524 udelay(1);
525 }
526 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
527 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
528 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
529 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
530 }
531 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
532 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
533 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
534 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
535 }
536#else
537 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
538 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
539 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
540 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
541 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
542 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
543 save->crtc_enabled[i] = false;
544 /* ***** */
545#endif
546 } else {
547 save->crtc_enabled[i] = false;
548 }
549 }
550}
551
552static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
553 struct amdgpu_mode_mc_save *save)
554{
555 u32 tmp, frame_count;
556 int i, j;
557
558 /* update crtc base addresses */
559 for (i = 0; i < adev->mode_info.num_crtc; i++) {
560 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
561 upper_32_bits(adev->mc.vram_start));
562 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
563 upper_32_bits(adev->mc.vram_start));
564 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
565 (u32)adev->mc.vram_start);
566 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
567 (u32)adev->mc.vram_start);
568
569 if (save->crtc_enabled[i]) {
570 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
571 if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 0) {
572 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 0);
573 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
574 }
575 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
576 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
577 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
578 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
579 }
580 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
581 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
582 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
583 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
584 }
585 for (j = 0; j < adev->usec_timeout; j++) {
586 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
587 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
588 break;
589 udelay(1);
590 }
591 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
592 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
593 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
594 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
595 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
596 /* wait for the next frame */
597 frame_count = amdgpu_display_vblank_get_counter(adev, i);
598 for (j = 0; j < adev->usec_timeout; j++) {
599 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
600 break;
601 udelay(1);
602 }
603 }
604 }
605
606 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
607 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
608
609 /* Unlock vga access */
610 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
611 mdelay(1);
612 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
613}
614
615static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
616 bool render)
617{
618 u32 tmp;
619
620 /* Lockout access through VGA aperture*/
621 tmp = RREG32(mmVGA_HDP_CONTROL);
622 if (render)
623 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
624 else
625 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
626 WREG32(mmVGA_HDP_CONTROL, tmp);
627
628 /* disable VGA render */
629 tmp = RREG32(mmVGA_RENDER_CONTROL);
630 if (render)
631 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
632 else
633 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
634 WREG32(mmVGA_RENDER_CONTROL, tmp);
635}
636
637static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev)
638{
639 int num_crtc = 0;
640
641 switch (adev->asic_type) {
642 case CHIP_FIJI:
643 case CHIP_TONGA:
644 num_crtc = 6;
645 break;
646 default:
647 num_crtc = 0;
648 }
649 return num_crtc;
650}
651
652void dce_v10_0_disable_dce(struct amdgpu_device *adev)
653{
654 /*Disable VGA render and enabled crtc, if has DCE engine*/
655 if (amdgpu_atombios_has_dce_engine_info(adev)) {
656 u32 tmp;
657 int crtc_enabled, i;
658
659 dce_v10_0_set_vga_render_state(adev, false);
660
661 /*Disable crtc*/
662 for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) {
663 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
664 CRTC_CONTROL, CRTC_MASTER_EN);
665 if (crtc_enabled) {
666 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
667 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
668 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
669 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
670 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
671 }
672 }
673 }
674}
675
676static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
677{
678 struct drm_device *dev = encoder->dev;
679 struct amdgpu_device *adev = dev->dev_private;
680 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
681 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
682 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
683 int bpc = 0;
684 u32 tmp = 0;
685 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
686
687 if (connector) {
688 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
689 bpc = amdgpu_connector_get_monitor_bpc(connector);
690 dither = amdgpu_connector->dither;
691 }
692
693 /* LVDS/eDP FMT is set up by atom */
694 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
695 return;
696
697 /* not needed for analog */
698 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
699 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
700 return;
701
702 if (bpc == 0)
703 return;
704
705 switch (bpc) {
706 case 6:
707 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
708 /* XXX sort out optimal dither settings */
709 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
710 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
711 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
712 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
713 } else {
714 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
715 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
716 }
717 break;
718 case 8:
719 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
720 /* XXX sort out optimal dither settings */
721 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
722 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
723 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
724 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
725 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
726 } else {
727 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
728 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
729 }
730 break;
731 case 10:
732 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
733 /* XXX sort out optimal dither settings */
734 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
735 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
736 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
737 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
738 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
739 } else {
740 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
741 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
742 }
743 break;
744 default:
745 /* not needed */
746 break;
747 }
748
749 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
750}
751
752
753/* display watermark setup */
754/**
755 * dce_v10_0_line_buffer_adjust - Set up the line buffer
756 *
757 * @adev: amdgpu_device pointer
758 * @amdgpu_crtc: the selected display controller
759 * @mode: the current display mode on the selected display
760 * controller
761 *
762 * Setup up the line buffer allocation for
763 * the selected display controller (CIK).
764 * Returns the line buffer size in pixels.
765 */
766static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
767 struct amdgpu_crtc *amdgpu_crtc,
768 struct drm_display_mode *mode)
769{
770 u32 tmp, buffer_alloc, i, mem_cfg;
771 u32 pipe_offset = amdgpu_crtc->crtc_id;
772 /*
773 * Line Buffer Setup
774 * There are 6 line buffers, one for each display controllers.
775 * There are 3 partitions per LB. Select the number of partitions
776 * to enable based on the display width. For display widths larger
777 * than 4096, you need use to use 2 display controllers and combine
778 * them using the stereo blender.
779 */
780 if (amdgpu_crtc->base.enabled && mode) {
781 if (mode->crtc_hdisplay < 1920) {
782 mem_cfg = 1;
783 buffer_alloc = 2;
784 } else if (mode->crtc_hdisplay < 2560) {
785 mem_cfg = 2;
786 buffer_alloc = 2;
787 } else if (mode->crtc_hdisplay < 4096) {
788 mem_cfg = 0;
789 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
790 } else {
791 DRM_DEBUG_KMS("Mode too big for LB!\n");
792 mem_cfg = 0;
793 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
794 }
795 } else {
796 mem_cfg = 1;
797 buffer_alloc = 0;
798 }
799
800 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
801 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
802 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
803
804 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
805 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
806 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
807
808 for (i = 0; i < adev->usec_timeout; i++) {
809 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
810 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
811 break;
812 udelay(1);
813 }
814
815 if (amdgpu_crtc->base.enabled && mode) {
816 switch (mem_cfg) {
817 case 0:
818 default:
819 return 4096 * 2;
820 case 1:
821 return 1920 * 2;
822 case 2:
823 return 2560 * 2;
824 }
825 }
826
827 /* controller not enabled, so no lb used */
828 return 0;
829}
830
831/**
832 * cik_get_number_of_dram_channels - get the number of dram channels
833 *
834 * @adev: amdgpu_device pointer
835 *
836 * Look up the number of video ram channels (CIK).
837 * Used for display watermark bandwidth calculations
838 * Returns the number of dram channels
839 */
840static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
841{
842 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
843
844 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
845 case 0:
846 default:
847 return 1;
848 case 1:
849 return 2;
850 case 2:
851 return 4;
852 case 3:
853 return 8;
854 case 4:
855 return 3;
856 case 5:
857 return 6;
858 case 6:
859 return 10;
860 case 7:
861 return 12;
862 case 8:
863 return 16;
864 }
865}
866
867struct dce10_wm_params {
868 u32 dram_channels; /* number of dram channels */
869 u32 yclk; /* bandwidth per dram data pin in kHz */
870 u32 sclk; /* engine clock in kHz */
871 u32 disp_clk; /* display clock in kHz */
872 u32 src_width; /* viewport width */
873 u32 active_time; /* active display time in ns */
874 u32 blank_time; /* blank time in ns */
875 bool interlaced; /* mode is interlaced */
876 fixed20_12 vsc; /* vertical scale ratio */
877 u32 num_heads; /* number of active crtcs */
878 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
879 u32 lb_size; /* line buffer allocated to pipe */
880 u32 vtaps; /* vertical scaler taps */
881};
882
883/**
884 * dce_v10_0_dram_bandwidth - get the dram bandwidth
885 *
886 * @wm: watermark calculation data
887 *
888 * Calculate the raw dram bandwidth (CIK).
889 * Used for display watermark bandwidth calculations
890 * Returns the dram bandwidth in MBytes/s
891 */
892static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
893{
894 /* Calculate raw DRAM Bandwidth */
895 fixed20_12 dram_efficiency; /* 0.7 */
896 fixed20_12 yclk, dram_channels, bandwidth;
897 fixed20_12 a;
898
899 a.full = dfixed_const(1000);
900 yclk.full = dfixed_const(wm->yclk);
901 yclk.full = dfixed_div(yclk, a);
902 dram_channels.full = dfixed_const(wm->dram_channels * 4);
903 a.full = dfixed_const(10);
904 dram_efficiency.full = dfixed_const(7);
905 dram_efficiency.full = dfixed_div(dram_efficiency, a);
906 bandwidth.full = dfixed_mul(dram_channels, yclk);
907 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
908
909 return dfixed_trunc(bandwidth);
910}
911
912/**
913 * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
914 *
915 * @wm: watermark calculation data
916 *
917 * Calculate the dram bandwidth used for display (CIK).
918 * Used for display watermark bandwidth calculations
919 * Returns the dram bandwidth for display in MBytes/s
920 */
921static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
922{
923 /* Calculate DRAM Bandwidth and the part allocated to display. */
924 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
925 fixed20_12 yclk, dram_channels, bandwidth;
926 fixed20_12 a;
927
928 a.full = dfixed_const(1000);
929 yclk.full = dfixed_const(wm->yclk);
930 yclk.full = dfixed_div(yclk, a);
931 dram_channels.full = dfixed_const(wm->dram_channels * 4);
932 a.full = dfixed_const(10);
933 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
934 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
935 bandwidth.full = dfixed_mul(dram_channels, yclk);
936 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
937
938 return dfixed_trunc(bandwidth);
939}
940
941/**
942 * dce_v10_0_data_return_bandwidth - get the data return bandwidth
943 *
944 * @wm: watermark calculation data
945 *
946 * Calculate the data return bandwidth used for display (CIK).
947 * Used for display watermark bandwidth calculations
948 * Returns the data return bandwidth in MBytes/s
949 */
950static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
951{
952 /* Calculate the display Data return Bandwidth */
953 fixed20_12 return_efficiency; /* 0.8 */
954 fixed20_12 sclk, bandwidth;
955 fixed20_12 a;
956
957 a.full = dfixed_const(1000);
958 sclk.full = dfixed_const(wm->sclk);
959 sclk.full = dfixed_div(sclk, a);
960 a.full = dfixed_const(10);
961 return_efficiency.full = dfixed_const(8);
962 return_efficiency.full = dfixed_div(return_efficiency, a);
963 a.full = dfixed_const(32);
964 bandwidth.full = dfixed_mul(a, sclk);
965 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
966
967 return dfixed_trunc(bandwidth);
968}
969
970/**
971 * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
972 *
973 * @wm: watermark calculation data
974 *
975 * Calculate the dmif bandwidth used for display (CIK).
976 * Used for display watermark bandwidth calculations
977 * Returns the dmif bandwidth in MBytes/s
978 */
979static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
980{
981 /* Calculate the DMIF Request Bandwidth */
982 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
983 fixed20_12 disp_clk, bandwidth;
984 fixed20_12 a, b;
985
986 a.full = dfixed_const(1000);
987 disp_clk.full = dfixed_const(wm->disp_clk);
988 disp_clk.full = dfixed_div(disp_clk, a);
989 a.full = dfixed_const(32);
990 b.full = dfixed_mul(a, disp_clk);
991
992 a.full = dfixed_const(10);
993 disp_clk_request_efficiency.full = dfixed_const(8);
994 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
995
996 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
997
998 return dfixed_trunc(bandwidth);
999}
1000
1001/**
1002 * dce_v10_0_available_bandwidth - get the min available bandwidth
1003 *
1004 * @wm: watermark calculation data
1005 *
1006 * Calculate the min available bandwidth used for display (CIK).
1007 * Used for display watermark bandwidth calculations
1008 * Returns the min available bandwidth in MBytes/s
1009 */
1010static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
1011{
1012 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1013 u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
1014 u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
1015 u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
1016
1017 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1018}
1019
1020/**
1021 * dce_v10_0_average_bandwidth - get the average available bandwidth
1022 *
1023 * @wm: watermark calculation data
1024 *
1025 * Calculate the average available bandwidth used for display (CIK).
1026 * Used for display watermark bandwidth calculations
1027 * Returns the average available bandwidth in MBytes/s
1028 */
1029static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
1030{
1031 /* Calculate the display mode Average Bandwidth
1032 * DisplayMode should contain the source and destination dimensions,
1033 * timing, etc.
1034 */
1035 fixed20_12 bpp;
1036 fixed20_12 line_time;
1037 fixed20_12 src_width;
1038 fixed20_12 bandwidth;
1039 fixed20_12 a;
1040
1041 a.full = dfixed_const(1000);
1042 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1043 line_time.full = dfixed_div(line_time, a);
1044 bpp.full = dfixed_const(wm->bytes_per_pixel);
1045 src_width.full = dfixed_const(wm->src_width);
1046 bandwidth.full = dfixed_mul(src_width, bpp);
1047 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1048 bandwidth.full = dfixed_div(bandwidth, line_time);
1049
1050 return dfixed_trunc(bandwidth);
1051}
1052
1053/**
1054 * dce_v10_0_latency_watermark - get the latency watermark
1055 *
1056 * @wm: watermark calculation data
1057 *
1058 * Calculate the latency watermark (CIK).
1059 * Used for display watermark bandwidth calculations
1060 * Returns the latency watermark in ns
1061 */
1062static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
1063{
1064 /* First calculate the latency in ns */
1065 u32 mc_latency = 2000; /* 2000 ns. */
1066 u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
1067 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1068 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1069 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1070 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1071 (wm->num_heads * cursor_line_pair_return_time);
1072 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1073 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1074 u32 tmp, dmif_size = 12288;
1075 fixed20_12 a, b, c;
1076
1077 if (wm->num_heads == 0)
1078 return 0;
1079
1080 a.full = dfixed_const(2);
1081 b.full = dfixed_const(1);
1082 if ((wm->vsc.full > a.full) ||
1083 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1084 (wm->vtaps >= 5) ||
1085 ((wm->vsc.full >= a.full) && wm->interlaced))
1086 max_src_lines_per_dst_line = 4;
1087 else
1088 max_src_lines_per_dst_line = 2;
1089
1090 a.full = dfixed_const(available_bandwidth);
1091 b.full = dfixed_const(wm->num_heads);
1092 a.full = dfixed_div(a, b);
1093
1094 b.full = dfixed_const(mc_latency + 512);
1095 c.full = dfixed_const(wm->disp_clk);
1096 b.full = dfixed_div(b, c);
1097
1098 c.full = dfixed_const(dmif_size);
1099 b.full = dfixed_div(c, b);
1100
1101 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1102
1103 b.full = dfixed_const(1000);
1104 c.full = dfixed_const(wm->disp_clk);
1105 b.full = dfixed_div(c, b);
1106 c.full = dfixed_const(wm->bytes_per_pixel);
1107 b.full = dfixed_mul(b, c);
1108
1109 lb_fill_bw = min(tmp, dfixed_trunc(b));
1110
1111 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1112 b.full = dfixed_const(1000);
1113 c.full = dfixed_const(lb_fill_bw);
1114 b.full = dfixed_div(c, b);
1115 a.full = dfixed_div(a, b);
1116 line_fill_time = dfixed_trunc(a);
1117
1118 if (line_fill_time < wm->active_time)
1119 return latency;
1120 else
1121 return latency + (line_fill_time - wm->active_time);
1122
1123}
1124
1125/**
1126 * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1127 * average and available dram bandwidth
1128 *
1129 * @wm: watermark calculation data
1130 *
1131 * Check if the display average bandwidth fits in the display
1132 * dram bandwidth (CIK).
1133 * Used for display watermark bandwidth calculations
1134 * Returns true if the display fits, false if not.
1135 */
1136static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1137{
1138 if (dce_v10_0_average_bandwidth(wm) <=
1139 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1140 return true;
1141 else
1142 return false;
1143}
1144
1145/**
1146 * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
1147 * average and available bandwidth
1148 *
1149 * @wm: watermark calculation data
1150 *
1151 * Check if the display average bandwidth fits in the display
1152 * available bandwidth (CIK).
1153 * Used for display watermark bandwidth calculations
1154 * Returns true if the display fits, false if not.
1155 */
1156static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1157{
1158 if (dce_v10_0_average_bandwidth(wm) <=
1159 (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
1160 return true;
1161 else
1162 return false;
1163}
1164
1165/**
1166 * dce_v10_0_check_latency_hiding - check latency hiding
1167 *
1168 * @wm: watermark calculation data
1169 *
1170 * Check latency hiding (CIK).
1171 * Used for display watermark bandwidth calculations
1172 * Returns true if the display fits, false if not.
1173 */
1174static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
1175{
1176 u32 lb_partitions = wm->lb_size / wm->src_width;
1177 u32 line_time = wm->active_time + wm->blank_time;
1178 u32 latency_tolerant_lines;
1179 u32 latency_hiding;
1180 fixed20_12 a;
1181
1182 a.full = dfixed_const(1);
1183 if (wm->vsc.full > a.full)
1184 latency_tolerant_lines = 1;
1185 else {
1186 if (lb_partitions <= (wm->vtaps + 1))
1187 latency_tolerant_lines = 1;
1188 else
1189 latency_tolerant_lines = 2;
1190 }
1191
1192 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1193
1194 if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1195 return true;
1196 else
1197 return false;
1198}
1199
1200/**
1201 * dce_v10_0_program_watermarks - program display watermarks
1202 *
1203 * @adev: amdgpu_device pointer
1204 * @amdgpu_crtc: the selected display controller
1205 * @lb_size: line buffer size
1206 * @num_heads: number of display controllers in use
1207 *
1208 * Calculate and program the display watermarks for the
1209 * selected display controller (CIK).
1210 */
1211static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1212 struct amdgpu_crtc *amdgpu_crtc,
1213 u32 lb_size, u32 num_heads)
1214{
1215 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1216 struct dce10_wm_params wm_low, wm_high;
1217 u32 pixel_period;
1218 u32 line_time = 0;
1219 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1220 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1221
1222 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1223 pixel_period = 1000000 / (u32)mode->clock;
1224 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1225
1226 /* watermark for high clocks */
1227 if (adev->pm.dpm_enabled) {
1228 wm_high.yclk =
1229 amdgpu_dpm_get_mclk(adev, false) * 10;
1230 wm_high.sclk =
1231 amdgpu_dpm_get_sclk(adev, false) * 10;
1232 } else {
1233 wm_high.yclk = adev->pm.current_mclk * 10;
1234 wm_high.sclk = adev->pm.current_sclk * 10;
1235 }
1236
1237 wm_high.disp_clk = mode->clock;
1238 wm_high.src_width = mode->crtc_hdisplay;
1239 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1240 wm_high.blank_time = line_time - wm_high.active_time;
1241 wm_high.interlaced = false;
1242 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1243 wm_high.interlaced = true;
1244 wm_high.vsc = amdgpu_crtc->vsc;
1245 wm_high.vtaps = 1;
1246 if (amdgpu_crtc->rmx_type != RMX_OFF)
1247 wm_high.vtaps = 2;
1248 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1249 wm_high.lb_size = lb_size;
1250 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1251 wm_high.num_heads = num_heads;
1252
1253 /* set for high clocks */
1254 latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);
1255
1256 /* possibly force display priority to high */
1257 /* should really do this at mode validation time... */
1258 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1259 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1260 !dce_v10_0_check_latency_hiding(&wm_high) ||
1261 (adev->mode_info.disp_priority == 2)) {
1262 DRM_DEBUG_KMS("force priority to high\n");
1263 }
1264
1265 /* watermark for low clocks */
1266 if (adev->pm.dpm_enabled) {
1267 wm_low.yclk =
1268 amdgpu_dpm_get_mclk(adev, true) * 10;
1269 wm_low.sclk =
1270 amdgpu_dpm_get_sclk(adev, true) * 10;
1271 } else {
1272 wm_low.yclk = adev->pm.current_mclk * 10;
1273 wm_low.sclk = adev->pm.current_sclk * 10;
1274 }
1275
1276 wm_low.disp_clk = mode->clock;
1277 wm_low.src_width = mode->crtc_hdisplay;
1278 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1279 wm_low.blank_time = line_time - wm_low.active_time;
1280 wm_low.interlaced = false;
1281 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1282 wm_low.interlaced = true;
1283 wm_low.vsc = amdgpu_crtc->vsc;
1284 wm_low.vtaps = 1;
1285 if (amdgpu_crtc->rmx_type != RMX_OFF)
1286 wm_low.vtaps = 2;
1287 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1288 wm_low.lb_size = lb_size;
1289 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1290 wm_low.num_heads = num_heads;
1291
1292 /* set for low clocks */
1293 latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);
1294
1295 /* possibly force display priority to high */
1296 /* should really do this at mode validation time... */
1297 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1298 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1299 !dce_v10_0_check_latency_hiding(&wm_low) ||
1300 (adev->mode_info.disp_priority == 2)) {
1301 DRM_DEBUG_KMS("force priority to high\n");
1302 }
1303 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1304 }
1305
1306 /* select wm A */
1307 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1308 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1309 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1310 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1311 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1312 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1313 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1314 /* select wm B */
1315 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1316 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1317 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1318 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1319 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1320 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1321 /* restore original selection */
1322 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1323
1324 /* save values for DPM */
1325 amdgpu_crtc->line_time = line_time;
1326 amdgpu_crtc->wm_high = latency_watermark_a;
1327 amdgpu_crtc->wm_low = latency_watermark_b;
1328 /* Save number of lines the linebuffer leads before the scanout */
1329 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1330}
1331
1332/**
1333 * dce_v10_0_bandwidth_update - program display watermarks
1334 *
1335 * @adev: amdgpu_device pointer
1336 *
1337 * Calculate and program the display watermarks and line
1338 * buffer allocation (CIK).
1339 */
1340static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1341{
1342 struct drm_display_mode *mode = NULL;
1343 u32 num_heads = 0, lb_size;
1344 int i;
1345
1346 amdgpu_update_display_priority(adev);
1347
1348 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1349 if (adev->mode_info.crtcs[i]->base.enabled)
1350 num_heads++;
1351 }
1352 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1353 mode = &adev->mode_info.crtcs[i]->base.mode;
1354 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1355 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1356 lb_size, num_heads);
1357 }
1358}
1359
1360static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1361{
1362 int i;
1363 u32 offset, tmp;
1364
1365 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1366 offset = adev->mode_info.audio.pin[i].offset;
1367 tmp = RREG32_AUDIO_ENDPT(offset,
1368 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1369 if (((tmp &
1370 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1371 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1372 adev->mode_info.audio.pin[i].connected = false;
1373 else
1374 adev->mode_info.audio.pin[i].connected = true;
1375 }
1376}
1377
1378static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1379{
1380 int i;
1381
1382 dce_v10_0_audio_get_connected_pins(adev);
1383
1384 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1385 if (adev->mode_info.audio.pin[i].connected)
1386 return &adev->mode_info.audio.pin[i];
1387 }
1388 DRM_ERROR("No connected audio pins found!\n");
1389 return NULL;
1390}
1391
1392static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1393{
1394 struct amdgpu_device *adev = encoder->dev->dev_private;
1395 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1396 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1397 u32 tmp;
1398
1399 if (!dig || !dig->afmt || !dig->afmt->pin)
1400 return;
1401
1402 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1403 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1404 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1405}
1406
1407static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1408 struct drm_display_mode *mode)
1409{
1410 struct amdgpu_device *adev = encoder->dev->dev_private;
1411 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1412 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1413 struct drm_connector *connector;
1414 struct amdgpu_connector *amdgpu_connector = NULL;
1415 u32 tmp;
1416 int interlace = 0;
1417
1418 if (!dig || !dig->afmt || !dig->afmt->pin)
1419 return;
1420
1421 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1422 if (connector->encoder == encoder) {
1423 amdgpu_connector = to_amdgpu_connector(connector);
1424 break;
1425 }
1426 }
1427
1428 if (!amdgpu_connector) {
1429 DRM_ERROR("Couldn't find encoder's connector\n");
1430 return;
1431 }
1432
1433 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1434 interlace = 1;
1435 if (connector->latency_present[interlace]) {
1436 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1437 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1438 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1439 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1440 } else {
1441 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1442 VIDEO_LIPSYNC, 0);
1443 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1444 AUDIO_LIPSYNC, 0);
1445 }
1446 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1447 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1448}
1449
1450static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1451{
1452 struct amdgpu_device *adev = encoder->dev->dev_private;
1453 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1454 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1455 struct drm_connector *connector;
1456 struct amdgpu_connector *amdgpu_connector = NULL;
1457 u32 tmp;
1458 u8 *sadb = NULL;
1459 int sad_count;
1460
1461 if (!dig || !dig->afmt || !dig->afmt->pin)
1462 return;
1463
1464 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1465 if (connector->encoder == encoder) {
1466 amdgpu_connector = to_amdgpu_connector(connector);
1467 break;
1468 }
1469 }
1470
1471 if (!amdgpu_connector) {
1472 DRM_ERROR("Couldn't find encoder's connector\n");
1473 return;
1474 }
1475
1476 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1477 if (sad_count < 0) {
1478 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1479 sad_count = 0;
1480 }
1481
1482 /* program the speaker allocation */
1483 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1484 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1485 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1486 DP_CONNECTION, 0);
1487 /* set HDMI mode */
1488 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1489 HDMI_CONNECTION, 1);
1490 if (sad_count)
1491 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1492 SPEAKER_ALLOCATION, sadb[0]);
1493 else
1494 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1495 SPEAKER_ALLOCATION, 5); /* stereo */
1496 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1497 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1498
1499 kfree(sadb);
1500}
1501
1502static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1503{
1504 struct amdgpu_device *adev = encoder->dev->dev_private;
1505 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1506 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1507 struct drm_connector *connector;
1508 struct amdgpu_connector *amdgpu_connector = NULL;
1509 struct cea_sad *sads;
1510 int i, sad_count;
1511
1512 static const u16 eld_reg_to_type[][2] = {
1513 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1514 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1515 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1516 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1517 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1518 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1519 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1520 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1521 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1522 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1523 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1524 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1525 };
1526
1527 if (!dig || !dig->afmt || !dig->afmt->pin)
1528 return;
1529
1530 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1531 if (connector->encoder == encoder) {
1532 amdgpu_connector = to_amdgpu_connector(connector);
1533 break;
1534 }
1535 }
1536
1537 if (!amdgpu_connector) {
1538 DRM_ERROR("Couldn't find encoder's connector\n");
1539 return;
1540 }
1541
1542 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1543 if (sad_count <= 0) {
1544 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1545 return;
1546 }
1547 BUG_ON(!sads);
1548
1549 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1550 u32 tmp = 0;
1551 u8 stereo_freqs = 0;
1552 int max_channels = -1;
1553 int j;
1554
1555 for (j = 0; j < sad_count; j++) {
1556 struct cea_sad *sad = &sads[j];
1557
1558 if (sad->format == eld_reg_to_type[i][1]) {
1559 if (sad->channels > max_channels) {
1560 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1561 MAX_CHANNELS, sad->channels);
1562 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1563 DESCRIPTOR_BYTE_2, sad->byte2);
1564 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1565 SUPPORTED_FREQUENCIES, sad->freq);
1566 max_channels = sad->channels;
1567 }
1568
1569 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1570 stereo_freqs |= sad->freq;
1571 else
1572 break;
1573 }
1574 }
1575
1576 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1577 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1578 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1579 }
1580
1581 kfree(sads);
1582}
1583
1584static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1585 struct amdgpu_audio_pin *pin,
1586 bool enable)
1587{
1588 if (!pin)
1589 return;
1590
1591 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1592 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1593}
1594
1595static const u32 pin_offsets[] =
1596{
1597 AUD0_REGISTER_OFFSET,
1598 AUD1_REGISTER_OFFSET,
1599 AUD2_REGISTER_OFFSET,
1600 AUD3_REGISTER_OFFSET,
1601 AUD4_REGISTER_OFFSET,
1602 AUD5_REGISTER_OFFSET,
1603 AUD6_REGISTER_OFFSET,
1604};
1605
1606static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1607{
1608 int i;
1609
1610 if (!amdgpu_audio)
1611 return 0;
1612
1613 adev->mode_info.audio.enabled = true;
1614
1615 adev->mode_info.audio.num_pins = 7;
1616
1617 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1618 adev->mode_info.audio.pin[i].channels = -1;
1619 adev->mode_info.audio.pin[i].rate = -1;
1620 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1621 adev->mode_info.audio.pin[i].status_bits = 0;
1622 adev->mode_info.audio.pin[i].category_code = 0;
1623 adev->mode_info.audio.pin[i].connected = false;
1624 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1625 adev->mode_info.audio.pin[i].id = i;
1626 /* disable audio. it will be set up later */
1627 /* XXX remove once we switch to ip funcs */
1628 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1629 }
1630
1631 return 0;
1632}
1633
1634static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1635{
1636 int i;
1637
1638 if (!amdgpu_audio)
1639 return;
1640
1641 if (!adev->mode_info.audio.enabled)
1642 return;
1643
1644 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1645 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1646
1647 adev->mode_info.audio.enabled = false;
1648}
1649
1650/*
1651 * update the N and CTS parameters for a given pixel clock rate
1652 */
1653static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1654{
1655 struct drm_device *dev = encoder->dev;
1656 struct amdgpu_device *adev = dev->dev_private;
1657 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1658 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1659 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1660 u32 tmp;
1661
1662 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1663 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1664 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1665 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1666 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1667 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1668
1669 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1670 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1671 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1672 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1673 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1674 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1675
1676 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1677 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1678 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1679 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1680 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1681 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1682
1683}
1684
1685/*
1686 * build a HDMI Video Info Frame
1687 */
1688static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1689 void *buffer, size_t size)
1690{
1691 struct drm_device *dev = encoder->dev;
1692 struct amdgpu_device *adev = dev->dev_private;
1693 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1694 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1695 uint8_t *frame = buffer + 3;
1696 uint8_t *header = buffer;
1697
1698 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1699 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1700 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1701 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1702 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1703 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1704 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1705 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1706}
1707
1708static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1709{
1710 struct drm_device *dev = encoder->dev;
1711 struct amdgpu_device *adev = dev->dev_private;
1712 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1713 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1714 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1715 u32 dto_phase = 24 * 1000;
1716 u32 dto_modulo = clock;
1717 u32 tmp;
1718
1719 if (!dig || !dig->afmt)
1720 return;
1721
1722 /* XXX two dtos; generally use dto0 for hdmi */
1723 /* Express [24MHz / target pixel clock] as an exact rational
1724 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1725 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1726 */
1727 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1728 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1729 amdgpu_crtc->crtc_id);
1730 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1731 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1732 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1733}
1734
1735/*
1736 * update the info frames with the data from the current display mode
1737 */
1738static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1739 struct drm_display_mode *mode)
1740{
1741 struct drm_device *dev = encoder->dev;
1742 struct amdgpu_device *adev = dev->dev_private;
1743 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1744 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1745 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1746 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1747 struct hdmi_avi_infoframe frame;
1748 ssize_t err;
1749 u32 tmp;
1750 int bpc = 8;
1751
1752 if (!dig || !dig->afmt)
1753 return;
1754
1755 /* Silent, r600_hdmi_enable will raise WARN for us */
1756 if (!dig->afmt->enabled)
1757 return;
1758
1759 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1760 if (encoder->crtc) {
1761 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1762 bpc = amdgpu_crtc->bpc;
1763 }
1764
1765 /* disable audio prior to setting up hw */
1766 dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1767 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1768
1769 dce_v10_0_audio_set_dto(encoder, mode->clock);
1770
1771 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1772 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1773 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1774
1775 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1776
1777 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1778 switch (bpc) {
1779 case 0:
1780 case 6:
1781 case 8:
1782 case 16:
1783 default:
1784 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1785 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1786 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1787 connector->name, bpc);
1788 break;
1789 case 10:
1790 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1791 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1792 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1793 connector->name);
1794 break;
1795 case 12:
1796 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1797 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1798 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1799 connector->name);
1800 break;
1801 }
1802 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1803
1804 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1805 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1806 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1807 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1808 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1809
1810 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1811 /* enable audio info frames (frames won't be set until audio is enabled) */
1812 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1813 /* required for audio info values to be updated */
1814 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1815 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1816
1817 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1818 /* required for audio info values to be updated */
1819 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1820 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1821
1822 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1823 /* anything other than 0 */
1824 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1825 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1826
1827 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1828
1829 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1830 /* set the default audio delay */
1831 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1832 /* should be suffient for all audio modes and small enough for all hblanks */
1833 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1834 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1835
1836 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1837 /* allow 60958 channel status fields to be updated */
1838 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1839 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1840
1841 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1842 if (bpc > 8)
1843 /* clear SW CTS value */
1844 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1845 else
1846 /* select SW CTS value */
1847 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1848 /* allow hw to sent ACR packets when required */
1849 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1850 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1851
1852 dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1853
1854 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1855 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1856 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1857
1858 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1859 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1860 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1861
1862 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1863 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1864 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1865 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1866 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1867 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1868 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1869 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1870
1871 dce_v10_0_audio_write_speaker_allocation(encoder);
1872
1873 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1874 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1875
1876 dce_v10_0_afmt_audio_select_pin(encoder);
1877 dce_v10_0_audio_write_sad_regs(encoder);
1878 dce_v10_0_audio_write_latency_fields(encoder, mode);
1879
1880 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1881 if (err < 0) {
1882 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1883 return;
1884 }
1885
1886 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1887 if (err < 0) {
1888 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1889 return;
1890 }
1891
1892 dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1893
1894 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1895 /* enable AVI info frames */
1896 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1897 /* required for audio info values to be updated */
1898 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1899 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1900
1901 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1902 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1903 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1904
1905 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1906 /* send audio packets */
1907 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1908 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1909
1910 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1911 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1912 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1913 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1914
1915 /* enable audio after to setting up hw */
1916 dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1917}
1918
1919static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1920{
1921 struct drm_device *dev = encoder->dev;
1922 struct amdgpu_device *adev = dev->dev_private;
1923 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1924 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1925
1926 if (!dig || !dig->afmt)
1927 return;
1928
1929 /* Silent, r600_hdmi_enable will raise WARN for us */
1930 if (enable && dig->afmt->enabled)
1931 return;
1932 if (!enable && !dig->afmt->enabled)
1933 return;
1934
1935 if (!enable && dig->afmt->pin) {
1936 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1937 dig->afmt->pin = NULL;
1938 }
1939
1940 dig->afmt->enabled = enable;
1941
1942 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1943 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1944}
1945
1946static int dce_v10_0_afmt_init(struct amdgpu_device *adev)
1947{
1948 int i;
1949
1950 for (i = 0; i < adev->mode_info.num_dig; i++)
1951 adev->mode_info.afmt[i] = NULL;
1952
1953 /* DCE10 has audio blocks tied to DIG encoders */
1954 for (i = 0; i < adev->mode_info.num_dig; i++) {
1955 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1956 if (adev->mode_info.afmt[i]) {
1957 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1958 adev->mode_info.afmt[i]->id = i;
1959 } else {
1960 int j;
1961 for (j = 0; j < i; j++) {
1962 kfree(adev->mode_info.afmt[j]);
1963 adev->mode_info.afmt[j] = NULL;
1964 }
1965 return -ENOMEM;
1966 }
1967 }
1968 return 0;
1969}
1970
1971static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
1972{
1973 int i;
1974
1975 for (i = 0; i < adev->mode_info.num_dig; i++) {
1976 kfree(adev->mode_info.afmt[i]);
1977 adev->mode_info.afmt[i] = NULL;
1978 }
1979}
1980
1981static const u32 vga_control_regs[6] =
1982{
1983 mmD1VGA_CONTROL,
1984 mmD2VGA_CONTROL,
1985 mmD3VGA_CONTROL,
1986 mmD4VGA_CONTROL,
1987 mmD5VGA_CONTROL,
1988 mmD6VGA_CONTROL,
1989};
1990
1991static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
1992{
1993 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1994 struct drm_device *dev = crtc->dev;
1995 struct amdgpu_device *adev = dev->dev_private;
1996 u32 vga_control;
1997
1998 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1999 if (enable)
2000 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2001 else
2002 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2003}
2004
2005static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
2006{
2007 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2008 struct drm_device *dev = crtc->dev;
2009 struct amdgpu_device *adev = dev->dev_private;
2010
2011 if (enable)
2012 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2013 else
2014 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2015}
2016
2017static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
2018 struct drm_framebuffer *fb,
2019 int x, int y, int atomic)
2020{
2021 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2022 struct drm_device *dev = crtc->dev;
2023 struct amdgpu_device *adev = dev->dev_private;
2024 struct amdgpu_framebuffer *amdgpu_fb;
2025 struct drm_framebuffer *target_fb;
2026 struct drm_gem_object *obj;
2027 struct amdgpu_bo *abo;
2028 uint64_t fb_location, tiling_flags;
2029 uint32_t fb_format, fb_pitch_pixels;
2030 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2031 u32 pipe_config;
2032 u32 tmp, viewport_w, viewport_h;
2033 int r;
2034 bool bypass_lut = false;
2035 struct drm_format_name_buf format_name;
2036
2037 /* no fb bound */
2038 if (!atomic && !crtc->primary->fb) {
2039 DRM_DEBUG_KMS("No FB bound\n");
2040 return 0;
2041 }
2042
2043 if (atomic) {
2044 amdgpu_fb = to_amdgpu_framebuffer(fb);
2045 target_fb = fb;
2046 } else {
2047 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2048 target_fb = crtc->primary->fb;
2049 }
2050
2051 /* If atomic, assume fb object is pinned & idle & fenced and
2052 * just update base pointers
2053 */
2054 obj = amdgpu_fb->obj;
2055 abo = gem_to_amdgpu_bo(obj);
2056 r = amdgpu_bo_reserve(abo, false);
2057 if (unlikely(r != 0))
2058 return r;
2059
2060 if (atomic) {
2061 fb_location = amdgpu_bo_gpu_offset(abo);
2062 } else {
2063 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2064 if (unlikely(r != 0)) {
2065 amdgpu_bo_unreserve(abo);
2066 return -EINVAL;
2067 }
2068 }
2069
2070 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
2071 amdgpu_bo_unreserve(abo);
2072
2073 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2074
2075 switch (target_fb->pixel_format) {
2076 case DRM_FORMAT_C8:
2077 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2078 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2079 break;
2080 case DRM_FORMAT_XRGB4444:
2081 case DRM_FORMAT_ARGB4444:
2082 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2083 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2084#ifdef __BIG_ENDIAN
2085 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2086 ENDIAN_8IN16);
2087#endif
2088 break;
2089 case DRM_FORMAT_XRGB1555:
2090 case DRM_FORMAT_ARGB1555:
2091 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2092 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2093#ifdef __BIG_ENDIAN
2094 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2095 ENDIAN_8IN16);
2096#endif
2097 break;
2098 case DRM_FORMAT_BGRX5551:
2099 case DRM_FORMAT_BGRA5551:
2100 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2101 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2102#ifdef __BIG_ENDIAN
2103 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2104 ENDIAN_8IN16);
2105#endif
2106 break;
2107 case DRM_FORMAT_RGB565:
2108 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2109 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2110#ifdef __BIG_ENDIAN
2111 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2112 ENDIAN_8IN16);
2113#endif
2114 break;
2115 case DRM_FORMAT_XRGB8888:
2116 case DRM_FORMAT_ARGB8888:
2117 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2118 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2119#ifdef __BIG_ENDIAN
2120 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2121 ENDIAN_8IN32);
2122#endif
2123 break;
2124 case DRM_FORMAT_XRGB2101010:
2125 case DRM_FORMAT_ARGB2101010:
2126 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2127 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2128#ifdef __BIG_ENDIAN
2129 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2130 ENDIAN_8IN32);
2131#endif
2132 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2133 bypass_lut = true;
2134 break;
2135 case DRM_FORMAT_BGRX1010102:
2136 case DRM_FORMAT_BGRA1010102:
2137 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2138 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2139#ifdef __BIG_ENDIAN
2140 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2141 ENDIAN_8IN32);
2142#endif
2143 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2144 bypass_lut = true;
2145 break;
2146 default:
2147 DRM_ERROR("Unsupported screen format %s\n",
2148 drm_get_format_name(target_fb->pixel_format, &format_name));
2149 return -EINVAL;
2150 }
2151
2152 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2153 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2154
2155 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2156 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2157 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2158 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2159 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2160
2161 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2162 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2163 ARRAY_2D_TILED_THIN1);
2164 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2165 tile_split);
2166 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2167 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2168 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2169 mtaspect);
2170 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2171 ADDR_SURF_MICRO_TILING_DISPLAY);
2172 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2173 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2174 ARRAY_1D_TILED_THIN1);
2175 }
2176
2177 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2178 pipe_config);
2179
2180 dce_v10_0_vga_enable(crtc, false);
2181
2182 /* Make sure surface address is updated at vertical blank rather than
2183 * horizontal blank
2184 */
2185 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2186 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2187 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2188 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2189
2190 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2191 upper_32_bits(fb_location));
2192 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2193 upper_32_bits(fb_location));
2194 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2195 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2196 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2197 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2198 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2199 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2200
2201 /*
2202 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2203 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2204 * retain the full precision throughout the pipeline.
2205 */
2206 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2207 if (bypass_lut)
2208 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2209 else
2210 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2211 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2212
2213 if (bypass_lut)
2214 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2215
2216 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2217 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2218 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2219 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2220 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2221 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2222
2223 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2224 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2225
2226 dce_v10_0_grph_enable(crtc, true);
2227
2228 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2229 target_fb->height);
2230
2231 x &= ~3;
2232 y &= ~1;
2233 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2234 (x << 16) | y);
2235 viewport_w = crtc->mode.hdisplay;
2236 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2237 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2238 (viewport_w << 16) | viewport_h);
2239
2240 /* set pageflip to happen anywhere in vblank interval */
2241 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2242
2243 if (!atomic && fb && fb != crtc->primary->fb) {
2244 amdgpu_fb = to_amdgpu_framebuffer(fb);
2245 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2246 r = amdgpu_bo_reserve(abo, false);
2247 if (unlikely(r != 0))
2248 return r;
2249 amdgpu_bo_unpin(abo);
2250 amdgpu_bo_unreserve(abo);
2251 }
2252
2253 /* Bytes per pixel may have changed */
2254 dce_v10_0_bandwidth_update(adev);
2255
2256 return 0;
2257}
2258
2259static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2260 struct drm_display_mode *mode)
2261{
2262 struct drm_device *dev = crtc->dev;
2263 struct amdgpu_device *adev = dev->dev_private;
2264 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2265 u32 tmp;
2266
2267 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2268 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2269 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2270 else
2271 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2272 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2273}
2274
2275static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2276{
2277 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2278 struct drm_device *dev = crtc->dev;
2279 struct amdgpu_device *adev = dev->dev_private;
2280 int i;
2281 u32 tmp;
2282
2283 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2284
2285 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2286 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2287 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2288 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2289
2290 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2291 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2292 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2293
2294 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2295 tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2296 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2297
2298 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2299 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2300 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2301 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2302
2303 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2304
2305 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2306 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2307 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2308
2309 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2310 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2311 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2312
2313 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2314 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2315
2316 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2317 for (i = 0; i < 256; i++) {
2318 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2319 (amdgpu_crtc->lut_r[i] << 20) |
2320 (amdgpu_crtc->lut_g[i] << 10) |
2321 (amdgpu_crtc->lut_b[i] << 0));
2322 }
2323
2324 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2325 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2326 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2327 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2328 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2329
2330 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2331 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2332 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2333 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2334
2335 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2336 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2337 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2338 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2339
2340 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2341 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2342 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2343 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2344
2345 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2346 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2347 /* XXX this only needs to be programmed once per crtc at startup,
2348 * not sure where the best place for it is
2349 */
2350 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2351 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2352 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2353}
2354
2355static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2356{
2357 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2358 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2359
2360 switch (amdgpu_encoder->encoder_id) {
2361 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2362 if (dig->linkb)
2363 return 1;
2364 else
2365 return 0;
2366 break;
2367 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2368 if (dig->linkb)
2369 return 3;
2370 else
2371 return 2;
2372 break;
2373 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2374 if (dig->linkb)
2375 return 5;
2376 else
2377 return 4;
2378 break;
2379 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2380 return 6;
2381 break;
2382 default:
2383 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2384 return 0;
2385 }
2386}
2387
2388/**
2389 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2390 *
2391 * @crtc: drm crtc
2392 *
2393 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2394 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2395 * monitors a dedicated PPLL must be used. If a particular board has
2396 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2397 * as there is no need to program the PLL itself. If we are not able to
2398 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2399 * avoid messing up an existing monitor.
2400 *
2401 * Asic specific PLL information
2402 *
2403 * DCE 10.x
2404 * Tonga
2405 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2406 * CI
2407 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2408 *
2409 */
2410static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2411{
2412 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2413 struct drm_device *dev = crtc->dev;
2414 struct amdgpu_device *adev = dev->dev_private;
2415 u32 pll_in_use;
2416 int pll;
2417
2418 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2419 if (adev->clock.dp_extclk)
2420 /* skip PPLL programming if using ext clock */
2421 return ATOM_PPLL_INVALID;
2422 else {
2423 /* use the same PPLL for all DP monitors */
2424 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2425 if (pll != ATOM_PPLL_INVALID)
2426 return pll;
2427 }
2428 } else {
2429 /* use the same PPLL for all monitors with the same clock */
2430 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2431 if (pll != ATOM_PPLL_INVALID)
2432 return pll;
2433 }
2434
2435 /* DCE10 has PPLL0, PPLL1, and PPLL2 */
2436 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2437 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2438 return ATOM_PPLL2;
2439 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2440 return ATOM_PPLL1;
2441 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2442 return ATOM_PPLL0;
2443 DRM_ERROR("unable to allocate a PPLL\n");
2444 return ATOM_PPLL_INVALID;
2445}
2446
2447static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2448{
2449 struct amdgpu_device *adev = crtc->dev->dev_private;
2450 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2451 uint32_t cur_lock;
2452
2453 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2454 if (lock)
2455 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2456 else
2457 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2458 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2459}
2460
2461static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2462{
2463 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2464 struct amdgpu_device *adev = crtc->dev->dev_private;
2465 u32 tmp;
2466
2467 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2468 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2469 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2470}
2471
2472static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2473{
2474 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2475 struct amdgpu_device *adev = crtc->dev->dev_private;
2476 u32 tmp;
2477
2478 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2479 upper_32_bits(amdgpu_crtc->cursor_addr));
2480 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2481 lower_32_bits(amdgpu_crtc->cursor_addr));
2482
2483 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2484 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2485 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2486 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2487}
2488
2489static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2490 int x, int y)
2491{
2492 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2493 struct amdgpu_device *adev = crtc->dev->dev_private;
2494 int xorigin = 0, yorigin = 0;
2495
2496 amdgpu_crtc->cursor_x = x;
2497 amdgpu_crtc->cursor_y = y;
2498
2499 /* avivo cursor are offset into the total surface */
2500 x += crtc->x;
2501 y += crtc->y;
2502 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2503
2504 if (x < 0) {
2505 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2506 x = 0;
2507 }
2508 if (y < 0) {
2509 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2510 y = 0;
2511 }
2512
2513 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2514 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2515 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2516 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2517
2518 return 0;
2519}
2520
2521static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2522 int x, int y)
2523{
2524 int ret;
2525
2526 dce_v10_0_lock_cursor(crtc, true);
2527 ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2528 dce_v10_0_lock_cursor(crtc, false);
2529
2530 return ret;
2531}
2532
2533static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2534 struct drm_file *file_priv,
2535 uint32_t handle,
2536 uint32_t width,
2537 uint32_t height,
2538 int32_t hot_x,
2539 int32_t hot_y)
2540{
2541 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2542 struct drm_gem_object *obj;
2543 struct amdgpu_bo *aobj;
2544 int ret;
2545
2546 if (!handle) {
2547 /* turn off cursor */
2548 dce_v10_0_hide_cursor(crtc);
2549 obj = NULL;
2550 goto unpin;
2551 }
2552
2553 if ((width > amdgpu_crtc->max_cursor_width) ||
2554 (height > amdgpu_crtc->max_cursor_height)) {
2555 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2556 return -EINVAL;
2557 }
2558
2559 obj = drm_gem_object_lookup(file_priv, handle);
2560 if (!obj) {
2561 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2562 return -ENOENT;
2563 }
2564
2565 aobj = gem_to_amdgpu_bo(obj);
2566 ret = amdgpu_bo_reserve(aobj, false);
2567 if (ret != 0) {
2568 drm_gem_object_unreference_unlocked(obj);
2569 return ret;
2570 }
2571
2572 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2573 amdgpu_bo_unreserve(aobj);
2574 if (ret) {
2575 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2576 drm_gem_object_unreference_unlocked(obj);
2577 return ret;
2578 }
2579
2580 dce_v10_0_lock_cursor(crtc, true);
2581
2582 if (width != amdgpu_crtc->cursor_width ||
2583 height != amdgpu_crtc->cursor_height ||
2584 hot_x != amdgpu_crtc->cursor_hot_x ||
2585 hot_y != amdgpu_crtc->cursor_hot_y) {
2586 int x, y;
2587
2588 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2589 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2590
2591 dce_v10_0_cursor_move_locked(crtc, x, y);
2592
2593 amdgpu_crtc->cursor_width = width;
2594 amdgpu_crtc->cursor_height = height;
2595 amdgpu_crtc->cursor_hot_x = hot_x;
2596 amdgpu_crtc->cursor_hot_y = hot_y;
2597 }
2598
2599 dce_v10_0_show_cursor(crtc);
2600 dce_v10_0_lock_cursor(crtc, false);
2601
2602unpin:
2603 if (amdgpu_crtc->cursor_bo) {
2604 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2605 ret = amdgpu_bo_reserve(aobj, false);
2606 if (likely(ret == 0)) {
2607 amdgpu_bo_unpin(aobj);
2608 amdgpu_bo_unreserve(aobj);
2609 }
2610 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2611 }
2612
2613 amdgpu_crtc->cursor_bo = obj;
2614 return 0;
2615}
2616
2617static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2618{
2619 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2620
2621 if (amdgpu_crtc->cursor_bo) {
2622 dce_v10_0_lock_cursor(crtc, true);
2623
2624 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2625 amdgpu_crtc->cursor_y);
2626
2627 dce_v10_0_show_cursor(crtc);
2628
2629 dce_v10_0_lock_cursor(crtc, false);
2630 }
2631}
2632
2633static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2634 u16 *blue, uint32_t size)
2635{
2636 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2637 int i;
2638
2639 /* userspace palettes are always correct as is */
2640 for (i = 0; i < size; i++) {
2641 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2642 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2643 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2644 }
2645 dce_v10_0_crtc_load_lut(crtc);
2646
2647 return 0;
2648}
2649
2650static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2651{
2652 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2653
2654 drm_crtc_cleanup(crtc);
2655 kfree(amdgpu_crtc);
2656}
2657
2658static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
2659 .cursor_set2 = dce_v10_0_crtc_cursor_set2,
2660 .cursor_move = dce_v10_0_crtc_cursor_move,
2661 .gamma_set = dce_v10_0_crtc_gamma_set,
2662 .set_config = amdgpu_crtc_set_config,
2663 .destroy = dce_v10_0_crtc_destroy,
2664 .page_flip_target = amdgpu_crtc_page_flip_target,
2665};
2666
2667static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2668{
2669 struct drm_device *dev = crtc->dev;
2670 struct amdgpu_device *adev = dev->dev_private;
2671 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2672 unsigned type;
2673
2674 switch (mode) {
2675 case DRM_MODE_DPMS_ON:
2676 amdgpu_crtc->enabled = true;
2677 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2678 dce_v10_0_vga_enable(crtc, true);
2679 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2680 dce_v10_0_vga_enable(crtc, false);
2681 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2682 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2683 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2684 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2685 drm_crtc_vblank_on(crtc);
2686 dce_v10_0_crtc_load_lut(crtc);
2687 break;
2688 case DRM_MODE_DPMS_STANDBY:
2689 case DRM_MODE_DPMS_SUSPEND:
2690 case DRM_MODE_DPMS_OFF:
2691 drm_crtc_vblank_off(crtc);
2692 if (amdgpu_crtc->enabled) {
2693 dce_v10_0_vga_enable(crtc, true);
2694 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2695 dce_v10_0_vga_enable(crtc, false);
2696 }
2697 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2698 amdgpu_crtc->enabled = false;
2699 break;
2700 }
2701 /* adjust pm to dpms */
2702 amdgpu_pm_compute_clocks(adev);
2703}
2704
2705static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2706{
2707 /* disable crtc pair power gating before programming */
2708 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2709 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2710 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2711}
2712
2713static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2714{
2715 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2716 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2717}
2718
2719static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2720{
2721 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2722 struct drm_device *dev = crtc->dev;
2723 struct amdgpu_device *adev = dev->dev_private;
2724 struct amdgpu_atom_ss ss;
2725 int i;
2726
2727 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2728 if (crtc->primary->fb) {
2729 int r;
2730 struct amdgpu_framebuffer *amdgpu_fb;
2731 struct amdgpu_bo *abo;
2732
2733 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2734 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2735 r = amdgpu_bo_reserve(abo, false);
2736 if (unlikely(r))
2737 DRM_ERROR("failed to reserve abo before unpin\n");
2738 else {
2739 amdgpu_bo_unpin(abo);
2740 amdgpu_bo_unreserve(abo);
2741 }
2742 }
2743 /* disable the GRPH */
2744 dce_v10_0_grph_enable(crtc, false);
2745
2746 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2747
2748 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2749 if (adev->mode_info.crtcs[i] &&
2750 adev->mode_info.crtcs[i]->enabled &&
2751 i != amdgpu_crtc->crtc_id &&
2752 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2753 /* one other crtc is using this pll don't turn
2754 * off the pll
2755 */
2756 goto done;
2757 }
2758 }
2759
2760 switch (amdgpu_crtc->pll_id) {
2761 case ATOM_PPLL0:
2762 case ATOM_PPLL1:
2763 case ATOM_PPLL2:
2764 /* disable the ppll */
2765 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2766 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2767 break;
2768 default:
2769 break;
2770 }
2771done:
2772 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2773 amdgpu_crtc->adjusted_clock = 0;
2774 amdgpu_crtc->encoder = NULL;
2775 amdgpu_crtc->connector = NULL;
2776}
2777
2778static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2779 struct drm_display_mode *mode,
2780 struct drm_display_mode *adjusted_mode,
2781 int x, int y, struct drm_framebuffer *old_fb)
2782{
2783 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2784
2785 if (!amdgpu_crtc->adjusted_clock)
2786 return -EINVAL;
2787
2788 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2789 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2790 dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2791 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2792 amdgpu_atombios_crtc_scaler_setup(crtc);
2793 dce_v10_0_cursor_reset(crtc);
2794 /* update the hw version fpr dpm */
2795 amdgpu_crtc->hw_mode = *adjusted_mode;
2796
2797 return 0;
2798}
2799
2800static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2801 const struct drm_display_mode *mode,
2802 struct drm_display_mode *adjusted_mode)
2803{
2804 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2805 struct drm_device *dev = crtc->dev;
2806 struct drm_encoder *encoder;
2807
2808 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2809 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2810 if (encoder->crtc == crtc) {
2811 amdgpu_crtc->encoder = encoder;
2812 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2813 break;
2814 }
2815 }
2816 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2817 amdgpu_crtc->encoder = NULL;
2818 amdgpu_crtc->connector = NULL;
2819 return false;
2820 }
2821 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2822 return false;
2823 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2824 return false;
2825 /* pick pll */
2826 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2827 /* if we can't get a PPLL for a non-DP encoder, fail */
2828 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2829 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2830 return false;
2831
2832 return true;
2833}
2834
2835static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2836 struct drm_framebuffer *old_fb)
2837{
2838 return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2839}
2840
2841static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2842 struct drm_framebuffer *fb,
2843 int x, int y, enum mode_set_atomic state)
2844{
2845 return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
2846}
2847
2848static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2849 .dpms = dce_v10_0_crtc_dpms,
2850 .mode_fixup = dce_v10_0_crtc_mode_fixup,
2851 .mode_set = dce_v10_0_crtc_mode_set,
2852 .mode_set_base = dce_v10_0_crtc_set_base,
2853 .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2854 .prepare = dce_v10_0_crtc_prepare,
2855 .commit = dce_v10_0_crtc_commit,
2856 .load_lut = dce_v10_0_crtc_load_lut,
2857 .disable = dce_v10_0_crtc_disable,
2858};
2859
2860static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2861{
2862 struct amdgpu_crtc *amdgpu_crtc;
2863 int i;
2864
2865 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2866 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2867 if (amdgpu_crtc == NULL)
2868 return -ENOMEM;
2869
2870 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2871
2872 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2873 amdgpu_crtc->crtc_id = index;
2874 adev->mode_info.crtcs[index] = amdgpu_crtc;
2875
2876 amdgpu_crtc->max_cursor_width = 128;
2877 amdgpu_crtc->max_cursor_height = 128;
2878 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2879 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2880
2881 for (i = 0; i < 256; i++) {
2882 amdgpu_crtc->lut_r[i] = i << 2;
2883 amdgpu_crtc->lut_g[i] = i << 2;
2884 amdgpu_crtc->lut_b[i] = i << 2;
2885 }
2886
2887 switch (amdgpu_crtc->crtc_id) {
2888 case 0:
2889 default:
2890 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2891 break;
2892 case 1:
2893 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2894 break;
2895 case 2:
2896 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2897 break;
2898 case 3:
2899 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2900 break;
2901 case 4:
2902 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2903 break;
2904 case 5:
2905 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2906 break;
2907 }
2908
2909 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2910 amdgpu_crtc->adjusted_clock = 0;
2911 amdgpu_crtc->encoder = NULL;
2912 amdgpu_crtc->connector = NULL;
2913 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2914
2915 return 0;
2916}
2917
2918static int dce_v10_0_early_init(void *handle)
2919{
2920 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2921
2922 adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2923 adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2924
2925 dce_v10_0_set_display_funcs(adev);
2926 dce_v10_0_set_irq_funcs(adev);
2927
2928 adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
2929
2930 switch (adev->asic_type) {
2931 case CHIP_FIJI:
2932 case CHIP_TONGA:
2933 adev->mode_info.num_hpd = 6;
2934 adev->mode_info.num_dig = 7;
2935 break;
2936 default:
2937 /* FIXME: not supported yet */
2938 return -EINVAL;
2939 }
2940
2941 return 0;
2942}
2943
2944static int dce_v10_0_sw_init(void *handle)
2945{
2946 int r, i;
2947 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2948
2949 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2950 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2951 if (r)
2952 return r;
2953 }
2954
2955 for (i = 8; i < 20; i += 2) {
2956 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2957 if (r)
2958 return r;
2959 }
2960
2961 /* HPD hotplug */
2962 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2963 if (r)
2964 return r;
2965
2966 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2967
2968 adev->ddev->mode_config.async_page_flip = true;
2969
2970 adev->ddev->mode_config.max_width = 16384;
2971 adev->ddev->mode_config.max_height = 16384;
2972
2973 adev->ddev->mode_config.preferred_depth = 24;
2974 adev->ddev->mode_config.prefer_shadow = 1;
2975
2976 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2977
2978 r = amdgpu_modeset_create_props(adev);
2979 if (r)
2980 return r;
2981
2982 adev->ddev->mode_config.max_width = 16384;
2983 adev->ddev->mode_config.max_height = 16384;
2984
2985 /* allocate crtcs */
2986 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2987 r = dce_v10_0_crtc_init(adev, i);
2988 if (r)
2989 return r;
2990 }
2991
2992 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2993 amdgpu_print_display_setup(adev->ddev);
2994 else
2995 return -EINVAL;
2996
2997 /* setup afmt */
2998 r = dce_v10_0_afmt_init(adev);
2999 if (r)
3000 return r;
3001
3002 r = dce_v10_0_audio_init(adev);
3003 if (r)
3004 return r;
3005
3006 drm_kms_helper_poll_init(adev->ddev);
3007
3008 adev->mode_info.mode_config_initialized = true;
3009 return 0;
3010}
3011
3012static int dce_v10_0_sw_fini(void *handle)
3013{
3014 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3015
3016 kfree(adev->mode_info.bios_hardcoded_edid);
3017
3018 drm_kms_helper_poll_fini(adev->ddev);
3019
3020 dce_v10_0_audio_fini(adev);
3021
3022 dce_v10_0_afmt_fini(adev);
3023
3024 drm_mode_config_cleanup(adev->ddev);
3025 adev->mode_info.mode_config_initialized = false;
3026
3027 return 0;
3028}
3029
3030static int dce_v10_0_hw_init(void *handle)
3031{
3032 int i;
3033 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3034
3035 dce_v10_0_init_golden_registers(adev);
3036
3037 /* init dig PHYs, disp eng pll */
3038 amdgpu_atombios_encoder_init_dig(adev);
3039 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3040
3041 /* initialize hpd */
3042 dce_v10_0_hpd_init(adev);
3043
3044 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3045 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3046 }
3047
3048 dce_v10_0_pageflip_interrupt_init(adev);
3049
3050 return 0;
3051}
3052
3053static int dce_v10_0_hw_fini(void *handle)
3054{
3055 int i;
3056 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3057
3058 dce_v10_0_hpd_fini(adev);
3059
3060 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3061 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3062 }
3063
3064 dce_v10_0_pageflip_interrupt_fini(adev);
3065
3066 return 0;
3067}
3068
3069static int dce_v10_0_suspend(void *handle)
3070{
3071 return dce_v10_0_hw_fini(handle);
3072}
3073
3074static int dce_v10_0_resume(void *handle)
3075{
3076 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3077 int ret;
3078
3079 ret = dce_v10_0_hw_init(handle);
3080
3081 /* turn on the BL */
3082 if (adev->mode_info.bl_encoder) {
3083 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3084 adev->mode_info.bl_encoder);
3085 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3086 bl_level);
3087 }
3088
3089 return ret;
3090}
3091
3092static bool dce_v10_0_is_idle(void *handle)
3093{
3094 return true;
3095}
3096
3097static int dce_v10_0_wait_for_idle(void *handle)
3098{
3099 return 0;
3100}
3101
3102static bool dce_v10_0_check_soft_reset(void *handle)
3103{
3104 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3105
3106 return dce_v10_0_is_display_hung(adev);
3107}
3108
3109static int dce_v10_0_soft_reset(void *handle)
3110{
3111 u32 srbm_soft_reset = 0, tmp;
3112 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3113
3114 if (dce_v10_0_is_display_hung(adev))
3115 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3116
3117 if (srbm_soft_reset) {
3118 tmp = RREG32(mmSRBM_SOFT_RESET);
3119 tmp |= srbm_soft_reset;
3120 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3121 WREG32(mmSRBM_SOFT_RESET, tmp);
3122 tmp = RREG32(mmSRBM_SOFT_RESET);
3123
3124 udelay(50);
3125
3126 tmp &= ~srbm_soft_reset;
3127 WREG32(mmSRBM_SOFT_RESET, tmp);
3128 tmp = RREG32(mmSRBM_SOFT_RESET);
3129
3130 /* Wait a little for things to settle down */
3131 udelay(50);
3132 }
3133 return 0;
3134}
3135
3136static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3137 int crtc,
3138 enum amdgpu_interrupt_state state)
3139{
3140 u32 lb_interrupt_mask;
3141
3142 if (crtc >= adev->mode_info.num_crtc) {
3143 DRM_DEBUG("invalid crtc %d\n", crtc);
3144 return;
3145 }
3146
3147 switch (state) {
3148 case AMDGPU_IRQ_STATE_DISABLE:
3149 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3150 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3151 VBLANK_INTERRUPT_MASK, 0);
3152 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3153 break;
3154 case AMDGPU_IRQ_STATE_ENABLE:
3155 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3156 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3157 VBLANK_INTERRUPT_MASK, 1);
3158 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3159 break;
3160 default:
3161 break;
3162 }
3163}
3164
3165static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3166 int crtc,
3167 enum amdgpu_interrupt_state state)
3168{
3169 u32 lb_interrupt_mask;
3170
3171 if (crtc >= adev->mode_info.num_crtc) {
3172 DRM_DEBUG("invalid crtc %d\n", crtc);
3173 return;
3174 }
3175
3176 switch (state) {
3177 case AMDGPU_IRQ_STATE_DISABLE:
3178 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3179 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3180 VLINE_INTERRUPT_MASK, 0);
3181 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3182 break;
3183 case AMDGPU_IRQ_STATE_ENABLE:
3184 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3185 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3186 VLINE_INTERRUPT_MASK, 1);
3187 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3188 break;
3189 default:
3190 break;
3191 }
3192}
3193
3194static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
3195 struct amdgpu_irq_src *source,
3196 unsigned hpd,
3197 enum amdgpu_interrupt_state state)
3198{
3199 u32 tmp;
3200
3201 if (hpd >= adev->mode_info.num_hpd) {
3202 DRM_DEBUG("invalid hdp %d\n", hpd);
3203 return 0;
3204 }
3205
3206 switch (state) {
3207 case AMDGPU_IRQ_STATE_DISABLE:
3208 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3209 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3210 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3211 break;
3212 case AMDGPU_IRQ_STATE_ENABLE:
3213 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3214 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3215 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3216 break;
3217 default:
3218 break;
3219 }
3220
3221 return 0;
3222}
3223
3224static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3225 struct amdgpu_irq_src *source,
3226 unsigned type,
3227 enum amdgpu_interrupt_state state)
3228{
3229 switch (type) {
3230 case AMDGPU_CRTC_IRQ_VBLANK1:
3231 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3232 break;
3233 case AMDGPU_CRTC_IRQ_VBLANK2:
3234 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3235 break;
3236 case AMDGPU_CRTC_IRQ_VBLANK3:
3237 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3238 break;
3239 case AMDGPU_CRTC_IRQ_VBLANK4:
3240 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3241 break;
3242 case AMDGPU_CRTC_IRQ_VBLANK5:
3243 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3244 break;
3245 case AMDGPU_CRTC_IRQ_VBLANK6:
3246 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3247 break;
3248 case AMDGPU_CRTC_IRQ_VLINE1:
3249 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
3250 break;
3251 case AMDGPU_CRTC_IRQ_VLINE2:
3252 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
3253 break;
3254 case AMDGPU_CRTC_IRQ_VLINE3:
3255 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
3256 break;
3257 case AMDGPU_CRTC_IRQ_VLINE4:
3258 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
3259 break;
3260 case AMDGPU_CRTC_IRQ_VLINE5:
3261 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
3262 break;
3263 case AMDGPU_CRTC_IRQ_VLINE6:
3264 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
3265 break;
3266 default:
3267 break;
3268 }
3269 return 0;
3270}
3271
3272static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3273 struct amdgpu_irq_src *src,
3274 unsigned type,
3275 enum amdgpu_interrupt_state state)
3276{
3277 u32 reg;
3278
3279 if (type >= adev->mode_info.num_crtc) {
3280 DRM_ERROR("invalid pageflip crtc %d\n", type);
3281 return -EINVAL;
3282 }
3283
3284 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3285 if (state == AMDGPU_IRQ_STATE_DISABLE)
3286 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3287 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3288 else
3289 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3290 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3291
3292 return 0;
3293}
3294
3295static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3296 struct amdgpu_irq_src *source,
3297 struct amdgpu_iv_entry *entry)
3298{
3299 unsigned long flags;
3300 unsigned crtc_id;
3301 struct amdgpu_crtc *amdgpu_crtc;
3302 struct amdgpu_flip_work *works;
3303
3304 crtc_id = (entry->src_id - 8) >> 1;
3305 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3306
3307 if (crtc_id >= adev->mode_info.num_crtc) {
3308 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3309 return -EINVAL;
3310 }
3311
3312 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3313 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3314 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3315 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3316
3317 /* IRQ could occur when in initial stage */
3318 if (amdgpu_crtc == NULL)
3319 return 0;
3320
3321 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3322 works = amdgpu_crtc->pflip_works;
3323 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3324 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3325 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3326 amdgpu_crtc->pflip_status,
3327 AMDGPU_FLIP_SUBMITTED);
3328 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3329 return 0;
3330 }
3331
3332 /* page flip completed. clean up */
3333 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3334 amdgpu_crtc->pflip_works = NULL;
3335
3336 /* wakeup usersapce */
3337 if (works->event)
3338 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3339
3340 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3341
3342 drm_crtc_vblank_put(&amdgpu_crtc->base);
3343 schedule_work(&works->unpin_work);
3344
3345 return 0;
3346}
3347
3348static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3349 int hpd)
3350{
3351 u32 tmp;
3352
3353 if (hpd >= adev->mode_info.num_hpd) {
3354 DRM_DEBUG("invalid hdp %d\n", hpd);
3355 return;
3356 }
3357
3358 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3359 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3360 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3361}
3362
3363static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3364 int crtc)
3365{
3366 u32 tmp;
3367
3368 if (crtc >= adev->mode_info.num_crtc) {
3369 DRM_DEBUG("invalid crtc %d\n", crtc);
3370 return;
3371 }
3372
3373 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3374 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3375 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3376}
3377
3378static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3379 int crtc)
3380{
3381 u32 tmp;
3382
3383 if (crtc >= adev->mode_info.num_crtc) {
3384 DRM_DEBUG("invalid crtc %d\n", crtc);
3385 return;
3386 }
3387
3388 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3389 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3390 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3391}
3392
3393static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3394 struct amdgpu_irq_src *source,
3395 struct amdgpu_iv_entry *entry)
3396{
3397 unsigned crtc = entry->src_id - 1;
3398 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3399 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3400
3401 switch (entry->src_data) {
3402 case 0: /* vblank */
3403 if (disp_int & interrupt_status_offsets[crtc].vblank)
3404 dce_v10_0_crtc_vblank_int_ack(adev, crtc);
3405 else
3406 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3407
3408 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3409 drm_handle_vblank(adev->ddev, crtc);
3410 }
3411 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3412
3413 break;
3414 case 1: /* vline */
3415 if (disp_int & interrupt_status_offsets[crtc].vline)
3416 dce_v10_0_crtc_vline_int_ack(adev, crtc);
3417 else
3418 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3419
3420 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3421
3422 break;
3423 default:
3424 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3425 break;
3426 }
3427
3428 return 0;
3429}
3430
3431static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3432 struct amdgpu_irq_src *source,
3433 struct amdgpu_iv_entry *entry)
3434{
3435 uint32_t disp_int, mask;
3436 unsigned hpd;
3437
3438 if (entry->src_data >= adev->mode_info.num_hpd) {
3439 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3440 return 0;
3441 }
3442
3443 hpd = entry->src_data;
3444 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3445 mask = interrupt_status_offsets[hpd].hpd;
3446
3447 if (disp_int & mask) {
3448 dce_v10_0_hpd_int_ack(adev, hpd);
3449 schedule_work(&adev->hotplug_work);
3450 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3451 }
3452
3453 return 0;
3454}
3455
3456static int dce_v10_0_set_clockgating_state(void *handle,
3457 enum amd_clockgating_state state)
3458{
3459 return 0;
3460}
3461
3462static int dce_v10_0_set_powergating_state(void *handle,
3463 enum amd_powergating_state state)
3464{
3465 return 0;
3466}
3467
3468static const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3469 .name = "dce_v10_0",
3470 .early_init = dce_v10_0_early_init,
3471 .late_init = NULL,
3472 .sw_init = dce_v10_0_sw_init,
3473 .sw_fini = dce_v10_0_sw_fini,
3474 .hw_init = dce_v10_0_hw_init,
3475 .hw_fini = dce_v10_0_hw_fini,
3476 .suspend = dce_v10_0_suspend,
3477 .resume = dce_v10_0_resume,
3478 .is_idle = dce_v10_0_is_idle,
3479 .wait_for_idle = dce_v10_0_wait_for_idle,
3480 .check_soft_reset = dce_v10_0_check_soft_reset,
3481 .soft_reset = dce_v10_0_soft_reset,
3482 .set_clockgating_state = dce_v10_0_set_clockgating_state,
3483 .set_powergating_state = dce_v10_0_set_powergating_state,
3484};
3485
3486static void
3487dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3488 struct drm_display_mode *mode,
3489 struct drm_display_mode *adjusted_mode)
3490{
3491 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3492
3493 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3494
3495 /* need to call this here rather than in prepare() since we need some crtc info */
3496 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3497
3498 /* set scaler clears this on some chips */
3499 dce_v10_0_set_interleave(encoder->crtc, mode);
3500
3501 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3502 dce_v10_0_afmt_enable(encoder, true);
3503 dce_v10_0_afmt_setmode(encoder, adjusted_mode);
3504 }
3505}
3506
3507static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3508{
3509 struct amdgpu_device *adev = encoder->dev->dev_private;
3510 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3511 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3512
3513 if ((amdgpu_encoder->active_device &
3514 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3515 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3516 ENCODER_OBJECT_ID_NONE)) {
3517 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3518 if (dig) {
3519 dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3520 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3521 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3522 }
3523 }
3524
3525 amdgpu_atombios_scratch_regs_lock(adev, true);
3526
3527 if (connector) {
3528 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3529
3530 /* select the clock/data port if it uses a router */
3531 if (amdgpu_connector->router.cd_valid)
3532 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3533
3534 /* turn eDP panel on for mode set */
3535 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3536 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3537 ATOM_TRANSMITTER_ACTION_POWER_ON);
3538 }
3539
3540 /* this is needed for the pll/ss setup to work correctly in some cases */
3541 amdgpu_atombios_encoder_set_crtc_source(encoder);
3542 /* set up the FMT blocks */
3543 dce_v10_0_program_fmt(encoder);
3544}
3545
3546static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3547{
3548 struct drm_device *dev = encoder->dev;
3549 struct amdgpu_device *adev = dev->dev_private;
3550
3551 /* need to call this here as we need the crtc set up */
3552 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3553 amdgpu_atombios_scratch_regs_lock(adev, false);
3554}
3555
3556static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3557{
3558 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3559 struct amdgpu_encoder_atom_dig *dig;
3560
3561 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3562
3563 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3564 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3565 dce_v10_0_afmt_enable(encoder, false);
3566 dig = amdgpu_encoder->enc_priv;
3567 dig->dig_encoder = -1;
3568 }
3569 amdgpu_encoder->active_device = 0;
3570}
3571
3572/* these are handled by the primary encoders */
3573static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3574{
3575
3576}
3577
3578static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3579{
3580
3581}
3582
3583static void
3584dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3585 struct drm_display_mode *mode,
3586 struct drm_display_mode *adjusted_mode)
3587{
3588
3589}
3590
3591static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3592{
3593
3594}
3595
3596static void
3597dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3598{
3599
3600}
3601
3602static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3603 .dpms = dce_v10_0_ext_dpms,
3604 .prepare = dce_v10_0_ext_prepare,
3605 .mode_set = dce_v10_0_ext_mode_set,
3606 .commit = dce_v10_0_ext_commit,
3607 .disable = dce_v10_0_ext_disable,
3608 /* no detect for TMDS/LVDS yet */
3609};
3610
3611static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3612 .dpms = amdgpu_atombios_encoder_dpms,
3613 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3614 .prepare = dce_v10_0_encoder_prepare,
3615 .mode_set = dce_v10_0_encoder_mode_set,
3616 .commit = dce_v10_0_encoder_commit,
3617 .disable = dce_v10_0_encoder_disable,
3618 .detect = amdgpu_atombios_encoder_dig_detect,
3619};
3620
3621static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3622 .dpms = amdgpu_atombios_encoder_dpms,
3623 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3624 .prepare = dce_v10_0_encoder_prepare,
3625 .mode_set = dce_v10_0_encoder_mode_set,
3626 .commit = dce_v10_0_encoder_commit,
3627 .detect = amdgpu_atombios_encoder_dac_detect,
3628};
3629
3630static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3631{
3632 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3633 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3634 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3635 kfree(amdgpu_encoder->enc_priv);
3636 drm_encoder_cleanup(encoder);
3637 kfree(amdgpu_encoder);
3638}
3639
3640static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3641 .destroy = dce_v10_0_encoder_destroy,
3642};
3643
3644static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3645 uint32_t encoder_enum,
3646 uint32_t supported_device,
3647 u16 caps)
3648{
3649 struct drm_device *dev = adev->ddev;
3650 struct drm_encoder *encoder;
3651 struct amdgpu_encoder *amdgpu_encoder;
3652
3653 /* see if we already added it */
3654 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3655 amdgpu_encoder = to_amdgpu_encoder(encoder);
3656 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3657 amdgpu_encoder->devices |= supported_device;
3658 return;
3659 }
3660
3661 }
3662
3663 /* add a new one */
3664 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3665 if (!amdgpu_encoder)
3666 return;
3667
3668 encoder = &amdgpu_encoder->base;
3669 switch (adev->mode_info.num_crtc) {
3670 case 1:
3671 encoder->possible_crtcs = 0x1;
3672 break;
3673 case 2:
3674 default:
3675 encoder->possible_crtcs = 0x3;
3676 break;
3677 case 4:
3678 encoder->possible_crtcs = 0xf;
3679 break;
3680 case 6:
3681 encoder->possible_crtcs = 0x3f;
3682 break;
3683 }
3684
3685 amdgpu_encoder->enc_priv = NULL;
3686
3687 amdgpu_encoder->encoder_enum = encoder_enum;
3688 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3689 amdgpu_encoder->devices = supported_device;
3690 amdgpu_encoder->rmx_type = RMX_OFF;
3691 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3692 amdgpu_encoder->is_ext_encoder = false;
3693 amdgpu_encoder->caps = caps;
3694
3695 switch (amdgpu_encoder->encoder_id) {
3696 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3697 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3698 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3699 DRM_MODE_ENCODER_DAC, NULL);
3700 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
3701 break;
3702 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3703 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3704 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3705 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3706 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3707 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3708 amdgpu_encoder->rmx_type = RMX_FULL;
3709 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3710 DRM_MODE_ENCODER_LVDS, NULL);
3711 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3712 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3713 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3714 DRM_MODE_ENCODER_DAC, NULL);
3715 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3716 } else {
3717 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3718 DRM_MODE_ENCODER_TMDS, NULL);
3719 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3720 }
3721 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
3722 break;
3723 case ENCODER_OBJECT_ID_SI170B:
3724 case ENCODER_OBJECT_ID_CH7303:
3725 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3726 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3727 case ENCODER_OBJECT_ID_TITFP513:
3728 case ENCODER_OBJECT_ID_VT1623:
3729 case ENCODER_OBJECT_ID_HDMI_SI1930:
3730 case ENCODER_OBJECT_ID_TRAVIS:
3731 case ENCODER_OBJECT_ID_NUTMEG:
3732 /* these are handled by the primary encoders */
3733 amdgpu_encoder->is_ext_encoder = true;
3734 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3735 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3736 DRM_MODE_ENCODER_LVDS, NULL);
3737 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3738 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3739 DRM_MODE_ENCODER_DAC, NULL);
3740 else
3741 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3742 DRM_MODE_ENCODER_TMDS, NULL);
3743 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
3744 break;
3745 }
3746}
3747
3748static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3749 .set_vga_render_state = &dce_v10_0_set_vga_render_state,
3750 .bandwidth_update = &dce_v10_0_bandwidth_update,
3751 .vblank_get_counter = &dce_v10_0_vblank_get_counter,
3752 .vblank_wait = &dce_v10_0_vblank_wait,
3753 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3754 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3755 .hpd_sense = &dce_v10_0_hpd_sense,
3756 .hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3757 .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3758 .page_flip = &dce_v10_0_page_flip,
3759 .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3760 .add_encoder = &dce_v10_0_encoder_add,
3761 .add_connector = &amdgpu_connector_add,
3762 .stop_mc_access = &dce_v10_0_stop_mc_access,
3763 .resume_mc_access = &dce_v10_0_resume_mc_access,
3764};
3765
3766static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3767{
3768 if (adev->mode_info.funcs == NULL)
3769 adev->mode_info.funcs = &dce_v10_0_display_funcs;
3770}
3771
3772static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3773 .set = dce_v10_0_set_crtc_irq_state,
3774 .process = dce_v10_0_crtc_irq,
3775};
3776
3777static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3778 .set = dce_v10_0_set_pageflip_irq_state,
3779 .process = dce_v10_0_pageflip_irq,
3780};
3781
3782static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3783 .set = dce_v10_0_set_hpd_irq_state,
3784 .process = dce_v10_0_hpd_irq,
3785};
3786
3787static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3788{
3789 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3790 adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3791
3792 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3793 adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3794
3795 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3796 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3797}
3798
3799const struct amdgpu_ip_block_version dce_v10_0_ip_block =
3800{
3801 .type = AMD_IP_BLOCK_TYPE_DCE,
3802 .major = 10,
3803 .minor = 0,
3804 .rev = 0,
3805 .funcs = &dce_v10_0_ip_funcs,
3806};
3807
3808const struct amdgpu_ip_block_version dce_v10_1_ip_block =
3809{
3810 .type = AMD_IP_BLOCK_TYPE_DCE,
3811 .major = 10,
3812 .minor = 1,
3813 .rev = 0,
3814 .funcs = &dce_v10_0_ip_funcs,
3815};