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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Generic EP93xx GPIO handling
4 *
5 * Copyright (c) 2008 Ryan Mallon
6 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
7 *
8 * Based on code originally from:
9 * linux/arch/arm/mach-ep93xx/core.c
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/irq.h>
18#include <linux/slab.h>
19#include <linux/gpio/driver.h>
20#include <linux/bitops.h>
21#include <linux/seq_file.h>
22
23struct ep93xx_gpio_irq_chip {
24 void __iomem *base;
25 u8 int_unmasked;
26 u8 int_enabled;
27 u8 int_type1;
28 u8 int_type2;
29 u8 int_debounce;
30};
31
32struct ep93xx_gpio_chip {
33 void __iomem *base;
34 struct gpio_chip gc;
35 struct ep93xx_gpio_irq_chip *eic;
36};
37
38#define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc)
39
40static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_chip *gc)
41{
42 struct ep93xx_gpio_chip *egc = to_ep93xx_gpio_chip(gc);
43
44 return egc->eic;
45}
46
47/*************************************************************************
48 * Interrupt handling for EP93xx on-chip GPIOs
49 *************************************************************************/
50#define EP93XX_INT_TYPE1_OFFSET 0x00
51#define EP93XX_INT_TYPE2_OFFSET 0x04
52#define EP93XX_INT_EOI_OFFSET 0x08
53#define EP93XX_INT_EN_OFFSET 0x0c
54#define EP93XX_INT_STATUS_OFFSET 0x10
55#define EP93XX_INT_RAW_STATUS_OFFSET 0x14
56#define EP93XX_INT_DEBOUNCE_OFFSET 0x18
57
58static void ep93xx_gpio_update_int_params(struct ep93xx_gpio_irq_chip *eic)
59{
60 writeb_relaxed(0, eic->base + EP93XX_INT_EN_OFFSET);
61
62 writeb_relaxed(eic->int_type2,
63 eic->base + EP93XX_INT_TYPE2_OFFSET);
64
65 writeb_relaxed(eic->int_type1,
66 eic->base + EP93XX_INT_TYPE1_OFFSET);
67
68 writeb_relaxed(eic->int_unmasked & eic->int_enabled,
69 eic->base + EP93XX_INT_EN_OFFSET);
70}
71
72static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
73 unsigned int offset, bool enable)
74{
75 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
76 int port_mask = BIT(offset);
77
78 if (enable)
79 eic->int_debounce |= port_mask;
80 else
81 eic->int_debounce &= ~port_mask;
82
83 writeb(eic->int_debounce, eic->base + EP93XX_INT_DEBOUNCE_OFFSET);
84}
85
86static u32 ep93xx_gpio_ab_irq_handler(struct gpio_chip *gc)
87{
88 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
89 unsigned long stat;
90 int offset;
91
92 stat = readb(eic->base + EP93XX_INT_STATUS_OFFSET);
93 for_each_set_bit(offset, &stat, 8)
94 generic_handle_domain_irq(gc->irq.domain, offset);
95
96 return stat;
97}
98
99static irqreturn_t ep93xx_ab_irq_handler(int irq, void *dev_id)
100{
101 return IRQ_RETVAL(ep93xx_gpio_ab_irq_handler(dev_id));
102}
103
104static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
105{
106 struct irq_chip *irqchip = irq_desc_get_chip(desc);
107 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
108 struct gpio_irq_chip *gic = &gc->irq;
109 unsigned int parent = irq_desc_get_irq(desc);
110 unsigned int i;
111
112 chained_irq_enter(irqchip, desc);
113 for (i = 0; i < gic->num_parents; i++)
114 if (gic->parents[i] == parent)
115 break;
116
117 if (i < gic->num_parents)
118 generic_handle_domain_irq(gc->irq.domain, i);
119
120 chained_irq_exit(irqchip, desc);
121}
122
123static void ep93xx_gpio_irq_ack(struct irq_data *d)
124{
125 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
126 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
127 int port_mask = BIT(irqd_to_hwirq(d));
128
129 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
130 eic->int_type2 ^= port_mask; /* switch edge direction */
131 ep93xx_gpio_update_int_params(eic);
132 }
133
134 writeb(port_mask, eic->base + EP93XX_INT_EOI_OFFSET);
135}
136
137static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
138{
139 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
140 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
141 irq_hw_number_t hwirq = irqd_to_hwirq(d);
142 int port_mask = BIT(hwirq);
143
144 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
145 eic->int_type2 ^= port_mask; /* switch edge direction */
146
147 eic->int_unmasked &= ~port_mask;
148 ep93xx_gpio_update_int_params(eic);
149
150 writeb(port_mask, eic->base + EP93XX_INT_EOI_OFFSET);
151 gpiochip_disable_irq(gc, hwirq);
152}
153
154static void ep93xx_gpio_irq_mask(struct irq_data *d)
155{
156 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
157 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
158 irq_hw_number_t hwirq = irqd_to_hwirq(d);
159
160 eic->int_unmasked &= ~BIT(hwirq);
161 ep93xx_gpio_update_int_params(eic);
162 gpiochip_disable_irq(gc, hwirq);
163}
164
165static void ep93xx_gpio_irq_unmask(struct irq_data *d)
166{
167 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
168 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
169 irq_hw_number_t hwirq = irqd_to_hwirq(d);
170
171 gpiochip_enable_irq(gc, hwirq);
172 eic->int_unmasked |= BIT(hwirq);
173 ep93xx_gpio_update_int_params(eic);
174}
175
176/*
177 * gpio_int_type1 controls whether the interrupt is level (0) or
178 * edge (1) triggered, while gpio_int_type2 controls whether it
179 * triggers on low/falling (0) or high/rising (1).
180 */
181static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
182{
183 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
184 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
185 irq_hw_number_t hwirq = irqd_to_hwirq(d);
186 int port_mask = BIT(hwirq);
187 irq_flow_handler_t handler;
188
189 gc->direction_input(gc, hwirq);
190
191 switch (type) {
192 case IRQ_TYPE_EDGE_RISING:
193 eic->int_type1 |= port_mask;
194 eic->int_type2 |= port_mask;
195 handler = handle_edge_irq;
196 break;
197 case IRQ_TYPE_EDGE_FALLING:
198 eic->int_type1 |= port_mask;
199 eic->int_type2 &= ~port_mask;
200 handler = handle_edge_irq;
201 break;
202 case IRQ_TYPE_LEVEL_HIGH:
203 eic->int_type1 &= ~port_mask;
204 eic->int_type2 |= port_mask;
205 handler = handle_level_irq;
206 break;
207 case IRQ_TYPE_LEVEL_LOW:
208 eic->int_type1 &= ~port_mask;
209 eic->int_type2 &= ~port_mask;
210 handler = handle_level_irq;
211 break;
212 case IRQ_TYPE_EDGE_BOTH:
213 eic->int_type1 |= port_mask;
214 /* set initial polarity based on current input level */
215 if (gc->get(gc, hwirq))
216 eic->int_type2 &= ~port_mask; /* falling */
217 else
218 eic->int_type2 |= port_mask; /* rising */
219 handler = handle_edge_irq;
220 break;
221 default:
222 return -EINVAL;
223 }
224
225 irq_set_handler_locked(d, handler);
226
227 eic->int_enabled |= port_mask;
228
229 ep93xx_gpio_update_int_params(eic);
230
231 return 0;
232}
233
234static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
235 unsigned long config)
236{
237 u32 debounce;
238
239 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
240 return -ENOTSUPP;
241
242 debounce = pinconf_to_config_argument(config);
243 ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false);
244
245 return 0;
246}
247
248static void ep93xx_irq_print_chip(struct irq_data *data, struct seq_file *p)
249{
250 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
251
252 seq_puts(p, dev_name(gc->parent));
253}
254
255static const struct irq_chip gpio_eic_irq_chip = {
256 .name = "ep93xx-gpio-eic",
257 .irq_ack = ep93xx_gpio_irq_ack,
258 .irq_mask = ep93xx_gpio_irq_mask,
259 .irq_unmask = ep93xx_gpio_irq_unmask,
260 .irq_mask_ack = ep93xx_gpio_irq_mask_ack,
261 .irq_set_type = ep93xx_gpio_irq_type,
262 .irq_print_chip = ep93xx_irq_print_chip,
263 .flags = IRQCHIP_IMMUTABLE,
264 GPIOCHIP_IRQ_RESOURCE_HELPERS,
265};
266
267static int ep93xx_setup_irqs(struct platform_device *pdev,
268 struct ep93xx_gpio_chip *egc)
269{
270 struct gpio_chip *gc = &egc->gc;
271 struct device *dev = &pdev->dev;
272 struct gpio_irq_chip *girq = &gc->irq;
273 int ret, irq, i;
274 void __iomem *intr;
275
276 intr = devm_platform_ioremap_resource_byname(pdev, "intr");
277 if (IS_ERR(intr))
278 return PTR_ERR(intr);
279
280 gc->set_config = ep93xx_gpio_set_config;
281 egc->eic = devm_kzalloc(dev, sizeof(*egc->eic), GFP_KERNEL);
282 if (!egc->eic)
283 return -ENOMEM;
284
285 egc->eic->base = intr;
286 gpio_irq_chip_set_chip(girq, &gpio_eic_irq_chip);
287 girq->num_parents = platform_irq_count(pdev);
288 if (girq->num_parents == 0)
289 return -EINVAL;
290
291 girq->parents = devm_kcalloc(dev, girq->num_parents, sizeof(*girq->parents),
292 GFP_KERNEL);
293 if (!girq->parents)
294 return -ENOMEM;
295
296 if (girq->num_parents == 1) { /* A/B irqchips */
297 irq = platform_get_irq(pdev, 0);
298 if (irq < 0)
299 return irq;
300
301 ret = devm_request_irq(dev, irq, ep93xx_ab_irq_handler,
302 IRQF_SHARED, gc->label, gc);
303 if (ret)
304 return dev_err_probe(dev, ret, "requesting IRQ: %d\n", irq);
305
306 girq->parents[0] = irq;
307 } else { /* F irqchip */
308 girq->parent_handler = ep93xx_gpio_f_irq_handler;
309
310 for (i = 0; i < girq->num_parents; i++) {
311 irq = platform_get_irq_optional(pdev, i);
312 if (irq < 0)
313 continue;
314
315 girq->parents[i] = irq;
316 }
317
318 girq->map = girq->parents;
319 }
320
321 girq->default_type = IRQ_TYPE_NONE;
322 /* TODO: replace with handle_bad_irq() once we are fully hierarchical */
323 girq->handler = handle_simple_irq;
324
325 return 0;
326}
327
328static int ep93xx_gpio_probe(struct platform_device *pdev)
329{
330 struct ep93xx_gpio_chip *egc;
331 struct gpio_chip *gc;
332 void __iomem *data;
333 void __iomem *dir;
334 int ret;
335
336 egc = devm_kzalloc(&pdev->dev, sizeof(*egc), GFP_KERNEL);
337 if (!egc)
338 return -ENOMEM;
339
340 data = devm_platform_ioremap_resource_byname(pdev, "data");
341 if (IS_ERR(data))
342 return PTR_ERR(data);
343
344 dir = devm_platform_ioremap_resource_byname(pdev, "dir");
345 if (IS_ERR(dir))
346 return PTR_ERR(dir);
347
348 gc = &egc->gc;
349 ret = bgpio_init(gc, &pdev->dev, 1, data, NULL, NULL, dir, NULL, 0);
350 if (ret)
351 return dev_err_probe(&pdev->dev, ret, "unable to init generic GPIO\n");
352
353 gc->label = dev_name(&pdev->dev);
354 if (platform_irq_count(pdev) > 0) {
355 dev_dbg(&pdev->dev, "setting up irqs for %s\n", dev_name(&pdev->dev));
356 ret = ep93xx_setup_irqs(pdev, egc);
357 if (ret)
358 dev_err_probe(&pdev->dev, ret, "setup irqs failed");
359 }
360
361 return devm_gpiochip_add_data(&pdev->dev, gc, egc);
362}
363
364static const struct of_device_id ep93xx_gpio_match[] = {
365 { .compatible = "cirrus,ep9301-gpio" },
366 { /* sentinel */ }
367};
368
369static struct platform_driver ep93xx_gpio_driver = {
370 .driver = {
371 .name = "gpio-ep93xx",
372 .of_match_table = ep93xx_gpio_match,
373 },
374 .probe = ep93xx_gpio_probe,
375};
376
377static int __init ep93xx_gpio_init(void)
378{
379 return platform_driver_register(&ep93xx_gpio_driver);
380}
381postcore_initcall(ep93xx_gpio_init);
382
383MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
384 "H Hartley Sweeten <hsweeten@visionengravers.com>");
385MODULE_DESCRIPTION("EP93XX GPIO driver");
386MODULE_LICENSE("GPL");
1/*
2 * Generic EP93xx GPIO handling
3 *
4 * Copyright (c) 2008 Ryan Mallon
5 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
6 *
7 * Based on code originally from:
8 * linux/arch/arm/mach-ep93xx/core.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/io.h>
19#include <linux/irq.h>
20#include <linux/slab.h>
21#include <linux/gpio/driver.h>
22/* FIXME: this is here for gpio_to_irq() - get rid of this! */
23#include <linux/gpio.h>
24
25#include <mach/hardware.h>
26#include <mach/gpio-ep93xx.h>
27
28#define irq_to_gpio(irq) ((irq) - gpio_to_irq(0))
29
30struct ep93xx_gpio {
31 void __iomem *mmio_base;
32 struct gpio_chip gc[8];
33};
34
35/*************************************************************************
36 * Interrupt handling for EP93xx on-chip GPIOs
37 *************************************************************************/
38static unsigned char gpio_int_unmasked[3];
39static unsigned char gpio_int_enabled[3];
40static unsigned char gpio_int_type1[3];
41static unsigned char gpio_int_type2[3];
42static unsigned char gpio_int_debounce[3];
43
44/* Port ordering is: A B F */
45static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
46static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
47static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
48static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
49static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
50
51static void ep93xx_gpio_update_int_params(unsigned port)
52{
53 BUG_ON(port > 2);
54
55 writeb_relaxed(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
56
57 writeb_relaxed(gpio_int_type2[port],
58 EP93XX_GPIO_REG(int_type2_register_offset[port]));
59
60 writeb_relaxed(gpio_int_type1[port],
61 EP93XX_GPIO_REG(int_type1_register_offset[port]));
62
63 writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
64 EP93XX_GPIO_REG(int_en_register_offset[port]));
65}
66
67static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
68{
69 int line = irq_to_gpio(irq);
70 int port = line >> 3;
71 int port_mask = 1 << (line & 7);
72
73 if (enable)
74 gpio_int_debounce[port] |= port_mask;
75 else
76 gpio_int_debounce[port] &= ~port_mask;
77
78 writeb(gpio_int_debounce[port],
79 EP93XX_GPIO_REG(int_debounce_register_offset[port]));
80}
81
82static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
83{
84 unsigned char status;
85 int i;
86
87 status = readb(EP93XX_GPIO_A_INT_STATUS);
88 for (i = 0; i < 8; i++) {
89 if (status & (1 << i)) {
90 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
91 generic_handle_irq(gpio_irq);
92 }
93 }
94
95 status = readb(EP93XX_GPIO_B_INT_STATUS);
96 for (i = 0; i < 8; i++) {
97 if (status & (1 << i)) {
98 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
99 generic_handle_irq(gpio_irq);
100 }
101 }
102}
103
104static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
105{
106 /*
107 * map discontiguous hw irq range to continuous sw irq range:
108 *
109 * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
110 */
111 unsigned int irq = irq_desc_get_irq(desc);
112 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
113 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
114
115 generic_handle_irq(gpio_irq);
116}
117
118static void ep93xx_gpio_irq_ack(struct irq_data *d)
119{
120 int line = irq_to_gpio(d->irq);
121 int port = line >> 3;
122 int port_mask = 1 << (line & 7);
123
124 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
125 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
126 ep93xx_gpio_update_int_params(port);
127 }
128
129 writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
130}
131
132static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
133{
134 int line = irq_to_gpio(d->irq);
135 int port = line >> 3;
136 int port_mask = 1 << (line & 7);
137
138 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
139 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
140
141 gpio_int_unmasked[port] &= ~port_mask;
142 ep93xx_gpio_update_int_params(port);
143
144 writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
145}
146
147static void ep93xx_gpio_irq_mask(struct irq_data *d)
148{
149 int line = irq_to_gpio(d->irq);
150 int port = line >> 3;
151
152 gpio_int_unmasked[port] &= ~(1 << (line & 7));
153 ep93xx_gpio_update_int_params(port);
154}
155
156static void ep93xx_gpio_irq_unmask(struct irq_data *d)
157{
158 int line = irq_to_gpio(d->irq);
159 int port = line >> 3;
160
161 gpio_int_unmasked[port] |= 1 << (line & 7);
162 ep93xx_gpio_update_int_params(port);
163}
164
165/*
166 * gpio_int_type1 controls whether the interrupt is level (0) or
167 * edge (1) triggered, while gpio_int_type2 controls whether it
168 * triggers on low/falling (0) or high/rising (1).
169 */
170static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
171{
172 const int gpio = irq_to_gpio(d->irq);
173 const int port = gpio >> 3;
174 const int port_mask = 1 << (gpio & 7);
175 irq_flow_handler_t handler;
176
177 gpio_direction_input(gpio);
178
179 switch (type) {
180 case IRQ_TYPE_EDGE_RISING:
181 gpio_int_type1[port] |= port_mask;
182 gpio_int_type2[port] |= port_mask;
183 handler = handle_edge_irq;
184 break;
185 case IRQ_TYPE_EDGE_FALLING:
186 gpio_int_type1[port] |= port_mask;
187 gpio_int_type2[port] &= ~port_mask;
188 handler = handle_edge_irq;
189 break;
190 case IRQ_TYPE_LEVEL_HIGH:
191 gpio_int_type1[port] &= ~port_mask;
192 gpio_int_type2[port] |= port_mask;
193 handler = handle_level_irq;
194 break;
195 case IRQ_TYPE_LEVEL_LOW:
196 gpio_int_type1[port] &= ~port_mask;
197 gpio_int_type2[port] &= ~port_mask;
198 handler = handle_level_irq;
199 break;
200 case IRQ_TYPE_EDGE_BOTH:
201 gpio_int_type1[port] |= port_mask;
202 /* set initial polarity based on current input level */
203 if (gpio_get_value(gpio))
204 gpio_int_type2[port] &= ~port_mask; /* falling */
205 else
206 gpio_int_type2[port] |= port_mask; /* rising */
207 handler = handle_edge_irq;
208 break;
209 default:
210 return -EINVAL;
211 }
212
213 irq_set_handler_locked(d, handler);
214
215 gpio_int_enabled[port] |= port_mask;
216
217 ep93xx_gpio_update_int_params(port);
218
219 return 0;
220}
221
222static struct irq_chip ep93xx_gpio_irq_chip = {
223 .name = "GPIO",
224 .irq_ack = ep93xx_gpio_irq_ack,
225 .irq_mask_ack = ep93xx_gpio_irq_mask_ack,
226 .irq_mask = ep93xx_gpio_irq_mask,
227 .irq_unmask = ep93xx_gpio_irq_unmask,
228 .irq_set_type = ep93xx_gpio_irq_type,
229};
230
231static void ep93xx_gpio_init_irq(void)
232{
233 int gpio_irq;
234
235 for (gpio_irq = gpio_to_irq(0);
236 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
237 irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
238 handle_level_irq);
239 irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
240 }
241
242 irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
243 ep93xx_gpio_ab_irq_handler);
244 irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
245 ep93xx_gpio_f_irq_handler);
246 irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
247 ep93xx_gpio_f_irq_handler);
248 irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
249 ep93xx_gpio_f_irq_handler);
250 irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
251 ep93xx_gpio_f_irq_handler);
252 irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
253 ep93xx_gpio_f_irq_handler);
254 irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
255 ep93xx_gpio_f_irq_handler);
256 irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
257 ep93xx_gpio_f_irq_handler);
258 irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
259 ep93xx_gpio_f_irq_handler);
260}
261
262
263/*************************************************************************
264 * gpiolib interface for EP93xx on-chip GPIOs
265 *************************************************************************/
266struct ep93xx_gpio_bank {
267 const char *label;
268 int data;
269 int dir;
270 int base;
271 bool has_debounce;
272};
273
274#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _debounce) \
275 { \
276 .label = _label, \
277 .data = _data, \
278 .dir = _dir, \
279 .base = _base, \
280 .has_debounce = _debounce, \
281 }
282
283static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
284 EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true),
285 EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true),
286 EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
287 EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
288 EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
289 EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true),
290 EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
291 EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
292};
293
294static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
295 unsigned offset, unsigned debounce)
296{
297 int gpio = chip->base + offset;
298 int irq = gpio_to_irq(gpio);
299
300 if (irq < 0)
301 return -EINVAL;
302
303 ep93xx_gpio_int_debounce(irq, debounce ? true : false);
304
305 return 0;
306}
307
308/*
309 * Map GPIO A0..A7 (0..7) to irq 64..71,
310 * B0..B7 (7..15) to irq 72..79, and
311 * F0..F7 (16..24) to irq 80..87.
312 */
313static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
314{
315 int gpio = chip->base + offset;
316
317 if (gpio > EP93XX_GPIO_LINE_MAX_IRQ)
318 return -EINVAL;
319
320 return 64 + gpio;
321}
322
323static int ep93xx_gpio_add_bank(struct gpio_chip *gc, struct device *dev,
324 void __iomem *mmio_base, struct ep93xx_gpio_bank *bank)
325{
326 void __iomem *data = mmio_base + bank->data;
327 void __iomem *dir = mmio_base + bank->dir;
328 int err;
329
330 err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
331 if (err)
332 return err;
333
334 gc->label = bank->label;
335 gc->base = bank->base;
336
337 if (bank->has_debounce) {
338 gc->set_debounce = ep93xx_gpio_set_debounce;
339 gc->to_irq = ep93xx_gpio_to_irq;
340 }
341
342 return devm_gpiochip_add_data(dev, gc, NULL);
343}
344
345static int ep93xx_gpio_probe(struct platform_device *pdev)
346{
347 struct ep93xx_gpio *ep93xx_gpio;
348 struct resource *res;
349 int i;
350 struct device *dev = &pdev->dev;
351
352 ep93xx_gpio = devm_kzalloc(dev, sizeof(struct ep93xx_gpio), GFP_KERNEL);
353 if (!ep93xx_gpio)
354 return -ENOMEM;
355
356 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
357 ep93xx_gpio->mmio_base = devm_ioremap_resource(dev, res);
358 if (IS_ERR(ep93xx_gpio->mmio_base))
359 return PTR_ERR(ep93xx_gpio->mmio_base);
360
361 for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
362 struct gpio_chip *gc = &ep93xx_gpio->gc[i];
363 struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
364
365 if (ep93xx_gpio_add_bank(gc, &pdev->dev,
366 ep93xx_gpio->mmio_base, bank))
367 dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
368 bank->label);
369 }
370
371 ep93xx_gpio_init_irq();
372
373 return 0;
374}
375
376static struct platform_driver ep93xx_gpio_driver = {
377 .driver = {
378 .name = "gpio-ep93xx",
379 },
380 .probe = ep93xx_gpio_probe,
381};
382
383static int __init ep93xx_gpio_init(void)
384{
385 return platform_driver_register(&ep93xx_gpio_driver);
386}
387postcore_initcall(ep93xx_gpio_init);
388
389MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
390 "H Hartley Sweeten <hsweeten@visionengravers.com>");
391MODULE_DESCRIPTION("EP93XX GPIO driver");
392MODULE_LICENSE("GPL");