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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */
13#ifndef _ASM_MIPSREGS_H
14#define _ASM_MIPSREGS_H
15
16#include <linux/linkage.h>
17#include <linux/types.h>
18#include <asm/hazards.h>
19#include <asm/isa-rev.h>
20
21/*
22 * The following macros are especially useful for __asm__
23 * inline assembler.
24 */
25#ifndef __STR
26#define __STR(x) #x
27#endif
28#ifndef STR
29#define STR(x) __STR(x)
30#endif
31
32/*
33 * Configure language
34 */
35#ifdef __ASSEMBLY__
36#define _ULCAST_
37#define _U64CAST_
38#else
39#define _ULCAST_ (unsigned long)
40#define _U64CAST_ (u64)
41#endif
42
43/*
44 * Coprocessor 0 register names
45 *
46 * CP0_REGISTER variant is meant to be used in assembly code, C0_REGISTER
47 * variant is meant to be used in C (uasm) code.
48 */
49#define CP0_INDEX $0
50#define C0_INDEX 0, 0
51
52#define CP0_RANDOM $1
53#define C0_RANDOM 1, 0
54
55#define CP0_ENTRYLO0 $2
56#define C0_ENTRYLO0 2, 0
57
58#define CP0_ENTRYLO1 $3
59#define C0_ENTRYLO1 3, 0
60
61#define CP0_CONF $3
62#define C0_CONF 3, 0
63
64#define CP0_GLOBALNUMBER $3, 1
65#define C0_GLOBALNUMBER 3, 1
66
67#define CP0_CONTEXT $4
68#define C0_CONTEXT 4, 0
69
70#define CP0_PAGEMASK $5
71#define C0_PAGEMASK 5, 0
72
73#define CP0_PAGEGRAIN $5, 1
74#define C0_PAGEGRAIN 5, 1
75
76#define CP0_SEGCTL0 $5, 2
77#define C0_SEGCTL0 5, 2
78
79#define CP0_SEGCTL1 $5, 3
80#define C0_SEGCTL1 5, 3
81
82#define CP0_SEGCTL2 $5, 4
83#define C0_SEGCTL2 5, 4
84
85#define CP0_PWBASE $5, 5
86#define C0_PWBASE 5, 5
87
88#define CP0_PWFIELD $5, 6
89#define C0_PWFIELD 5, 6
90
91#define CP0_PWCTL $5, 7
92#define C0_PWCTL 5, 7
93
94#define CP0_WIRED $6
95#define C0_WIRED 6, 0
96
97#define CP0_INFO $7
98#define C0_INFO 7, 0
99
100#define CP0_HWRENA $7
101#define C0_HWRENA 7, 0
102
103#define CP0_BADVADDR $8
104#define C0_BADVADDR 8, 0
105
106#define CP0_BADINSTR $8, 1
107#define C0_BADINSTR 8, 1
108
109#define CP0_BADINSTRP $8, 2
110#define C0_BADINSTRP 8, 2
111
112#define CP0_COUNT $9
113#define C0_COUNT 9, 0
114
115#define CP0_PGD $9, 7
116#define C0_PGD 9, 7
117
118#define CP0_ENTRYHI $10
119#define C0_ENTRYHI 10, 0
120
121#define CP0_GUESTCTL1 $10, 4
122#define C0_GUESTCTL1 10, 5
123
124#define CP0_GUESTCTL2 $10, 5
125#define C0_GUESTCTL2 10, 5
126
127#define CP0_GUESTCTL3 $10, 6
128#define C0_GUESTCTL3 10, 6
129
130#define CP0_COMPARE $11
131#define C0_COMPARE 11, 0
132
133#define CP0_GUESTCTL0EXT $11, 4
134#define C0_GUESTCTL0EXT 11, 4
135
136#define CP0_STATUS $12
137#define C0_STATUS 12, 0
138
139#define CP0_GUESTCTL0 $12, 6
140#define C0_GUESTCTL0 12, 6
141
142#define CP0_GTOFFSET $12, 7
143#define C0_GTOFFSET 12, 7
144
145#define CP0_CAUSE $13
146#define C0_CAUSE 13, 0
147
148#define CP0_EPC $14
149#define C0_EPC 14, 0
150
151#define CP0_PRID $15
152#define C0_PRID 15, 0
153
154#define CP0_EBASE $15, 1
155#define C0_EBASE 15, 1
156
157#define CP0_CMGCRBASE $15, 3
158#define C0_CMGCRBASE 15, 3
159
160#define CP0_CONFIG $16
161#define C0_CONFIG 16, 0
162
163#define CP0_CONFIG1 $16, 1
164#define C0_CONFIG1 16, 1
165
166#define CP0_CONFIG2 $16, 2
167#define C0_CONFIG2 16, 2
168
169#define CP0_CONFIG3 $16, 3
170#define C0_CONFIG3 16, 3
171
172#define CP0_CONFIG4 $16, 4
173#define C0_CONFIG4 16, 4
174
175#define CP0_CONFIG5 $16, 5
176#define C0_CONFIG5 16, 5
177
178#define CP0_CONFIG6 $16, 6
179#define C0_CONFIG6 16, 6
180
181#define CP0_LLADDR $17
182#define C0_LLADDR 17, 0
183
184#define CP0_WATCHLO $18
185#define C0_WATCHLO 18, 0
186
187#define CP0_WATCHHI $19
188#define C0_WATCHHI 19, 0
189
190#define CP0_XCONTEXT $20
191#define C0_XCONTEXT 20, 0
192
193#define CP0_FRAMEMASK $21
194#define C0_FRAMEMASK 21, 0
195
196#define CP0_DIAGNOSTIC $22
197#define C0_DIAGNOSTIC 22, 0
198
199#define CP0_DIAGNOSTIC1 $22, 1
200#define C0_DIAGNOSTIC1 22, 1
201
202#define CP0_DEBUG $23
203#define C0_DEBUG 23, 0
204
205#define CP0_DEPC $24
206#define C0_DEPC 24, 0
207
208#define CP0_PERFORMANCE $25
209#define C0_PERFORMANCE 25, 0
210
211#define CP0_ECC $26
212#define C0_ECC 26, 0
213
214#define CP0_CACHEERR $27
215#define C0_CACHEERR 27, 0
216
217#define CP0_TAGLO $28
218#define C0_TAGLO 28, 0
219
220#define CP0_DTAGLO $28, 2
221#define C0_DTAGLO 28, 2
222
223#define CP0_DDATALO $28, 3
224#define C0_DDATALO 28, 3
225
226#define CP0_STAGLO $28, 4
227#define C0_STAGLO 28, 4
228
229#define CP0_TAGHI $29
230#define C0_TAGHI 29, 0
231
232#define CP0_ERROREPC $30
233#define C0_ERROREPC 30, 0
234
235#define CP0_DESAVE $31
236#define C0_DESAVE 31, 0
237
238/*
239 * R4640/R4650 cp0 register names. These registers are listed
240 * here only for completeness; without MMU these CPUs are not usable
241 * by Linux. A future ELKS port might take make Linux run on them
242 * though ...
243 */
244#define CP0_IBASE $0
245#define CP0_IBOUND $1
246#define CP0_DBASE $2
247#define CP0_DBOUND $3
248#define CP0_CALG $17
249#define CP0_IWATCH $18
250#define CP0_DWATCH $19
251
252/*
253 * Coprocessor 0 Set 1 register names
254 */
255#define CP0_S1_DERRADDR0 $26
256#define CP0_S1_DERRADDR1 $27
257#define CP0_S1_INTCONTROL $20
258
259/*
260 * Coprocessor 0 Set 2 register names
261 */
262#define CP0_S2_SRSCTL $12 /* MIPSR2 */
263
264/*
265 * Coprocessor 0 Set 3 register names
266 */
267#define CP0_S3_SRSMAP $12 /* MIPSR2 */
268
269/*
270 * TX39 Series
271 */
272#define CP0_TX39_CACHE $7
273
274
275/* Generic EntryLo bit definitions */
276#define ENTRYLO_G (_ULCAST_(1) << 0)
277#define ENTRYLO_V (_ULCAST_(1) << 1)
278#define ENTRYLO_D (_ULCAST_(1) << 2)
279#define ENTRYLO_C_SHIFT 3
280#define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
281
282/* R3000 EntryLo bit definitions */
283#define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
284#define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
285#define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
286#define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
287
288/* MIPS32/64 EntryLo bit definitions */
289#define MIPS_ENTRYLO_PFN_SHIFT 6
290#define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
291#define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
292
293/*
294 * MIPSr6+ GlobalNumber register definitions
295 */
296#define MIPS_GLOBALNUMBER_VP_SHF 0
297#define MIPS_GLOBALNUMBER_VP (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
298#define MIPS_GLOBALNUMBER_CORE_SHF 8
299#define MIPS_GLOBALNUMBER_CORE (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
300#define MIPS_GLOBALNUMBER_CLUSTER_SHF 16
301#define MIPS_GLOBALNUMBER_CLUSTER (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
302
303/*
304 * Values for PageMask register
305 */
306#define PM_4K 0x00000000
307#define PM_8K 0x00002000
308#define PM_16K 0x00006000
309#define PM_32K 0x0000e000
310#define PM_64K 0x0001e000
311#define PM_128K 0x0003e000
312#define PM_256K 0x0007e000
313#define PM_512K 0x000fe000
314#define PM_1M 0x001fe000
315#define PM_2M 0x003fe000
316#define PM_4M 0x007fe000
317#define PM_8M 0x00ffe000
318#define PM_16M 0x01ffe000
319#define PM_32M 0x03ffe000
320#define PM_64M 0x07ffe000
321#define PM_256M 0x1fffe000
322#define PM_1G 0x7fffe000
323
324/*
325 * Default page size for a given kernel configuration
326 */
327#ifdef CONFIG_PAGE_SIZE_4KB
328#define PM_DEFAULT_MASK PM_4K
329#elif defined(CONFIG_PAGE_SIZE_8KB)
330#define PM_DEFAULT_MASK PM_8K
331#elif defined(CONFIG_PAGE_SIZE_16KB)
332#define PM_DEFAULT_MASK PM_16K
333#elif defined(CONFIG_PAGE_SIZE_32KB)
334#define PM_DEFAULT_MASK PM_32K
335#elif defined(CONFIG_PAGE_SIZE_64KB)
336#define PM_DEFAULT_MASK PM_64K
337#else
338#error Bad page size configuration!
339#endif
340
341/*
342 * Default huge tlb size for a given kernel configuration
343 */
344#ifdef CONFIG_PAGE_SIZE_4KB
345#define PM_HUGE_MASK PM_1M
346#elif defined(CONFIG_PAGE_SIZE_8KB)
347#define PM_HUGE_MASK PM_4M
348#elif defined(CONFIG_PAGE_SIZE_16KB)
349#define PM_HUGE_MASK PM_16M
350#elif defined(CONFIG_PAGE_SIZE_32KB)
351#define PM_HUGE_MASK PM_64M
352#elif defined(CONFIG_PAGE_SIZE_64KB)
353#define PM_HUGE_MASK PM_256M
354#elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
355#error Bad page size configuration for hugetlbfs!
356#endif
357
358/*
359 * Wired register bits
360 */
361#define MIPSR6_WIRED_LIMIT_SHIFT 16
362#define MIPSR6_WIRED_LIMIT (_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
363#define MIPSR6_WIRED_WIRED_SHIFT 0
364#define MIPSR6_WIRED_WIRED (_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
365
366/*
367 * Values used for computation of new tlb entries
368 */
369#define PL_4K 12
370#define PL_16K 14
371#define PL_64K 16
372#define PL_256K 18
373#define PL_1M 20
374#define PL_4M 22
375#define PL_16M 24
376#define PL_64M 26
377#define PL_256M 28
378
379/*
380 * PageGrain bits
381 */
382#define PG_RIE (_ULCAST_(1) << 31)
383#define PG_XIE (_ULCAST_(1) << 30)
384#define PG_ELPA (_ULCAST_(1) << 29)
385#define PG_ESP (_ULCAST_(1) << 28)
386#define PG_IEC (_ULCAST_(1) << 27)
387
388/* MIPS32/64 EntryHI bit definitions */
389#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
390#define MIPS_ENTRYHI_ASIDX (_ULCAST_(0x3) << 8)
391#define MIPS_ENTRYHI_ASID (_ULCAST_(0xff) << 0)
392
393/*
394 * R4x00 interrupt enable / cause bits
395 */
396#define IE_SW0 (_ULCAST_(1) << 8)
397#define IE_SW1 (_ULCAST_(1) << 9)
398#define IE_IRQ0 (_ULCAST_(1) << 10)
399#define IE_IRQ1 (_ULCAST_(1) << 11)
400#define IE_IRQ2 (_ULCAST_(1) << 12)
401#define IE_IRQ3 (_ULCAST_(1) << 13)
402#define IE_IRQ4 (_ULCAST_(1) << 14)
403#define IE_IRQ5 (_ULCAST_(1) << 15)
404
405/*
406 * R4x00 interrupt cause bits
407 */
408#define C_SW0 (_ULCAST_(1) << 8)
409#define C_SW1 (_ULCAST_(1) << 9)
410#define C_IRQ0 (_ULCAST_(1) << 10)
411#define C_IRQ1 (_ULCAST_(1) << 11)
412#define C_IRQ2 (_ULCAST_(1) << 12)
413#define C_IRQ3 (_ULCAST_(1) << 13)
414#define C_IRQ4 (_ULCAST_(1) << 14)
415#define C_IRQ5 (_ULCAST_(1) << 15)
416
417/*
418 * Bitfields in the R4xx0 cp0 status register
419 */
420#define ST0_IE 0x00000001
421#define ST0_EXL 0x00000002
422#define ST0_ERL 0x00000004
423#define ST0_KSU 0x00000018
424# define KSU_USER 0x00000010
425# define KSU_SUPERVISOR 0x00000008
426# define KSU_KERNEL 0x00000000
427#define ST0_UX 0x00000020
428#define ST0_SX 0x00000040
429#define ST0_KX 0x00000080
430#define ST0_DE 0x00010000
431#define ST0_CE 0x00020000
432
433#ifdef CONFIG_64BIT
434#define ST0_KX_IF_64 ST0_KX
435#else
436#define ST0_KX_IF_64 0
437#endif
438
439/*
440 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
441 * cacheops in userspace. This bit exists only on RM7000 and RM9000
442 * processors.
443 */
444#define ST0_CO 0x08000000
445
446/*
447 * Bitfields in the R[23]000 cp0 status register.
448 */
449#define ST0_IEC 0x00000001
450#define ST0_KUC 0x00000002
451#define ST0_IEP 0x00000004
452#define ST0_KUP 0x00000008
453#define ST0_IEO 0x00000010
454#define ST0_KUO 0x00000020
455/* bits 6 & 7 are reserved on R[23]000 */
456#define ST0_ISC 0x00010000
457#define ST0_SWC 0x00020000
458#define ST0_CM 0x00080000
459
460/*
461 * Bits specific to the R4640/R4650
462 */
463#define ST0_UM (_ULCAST_(1) << 4)
464#define ST0_IL (_ULCAST_(1) << 23)
465#define ST0_DL (_ULCAST_(1) << 24)
466
467/*
468 * Enable the MIPS MDMX and DSP ASEs
469 */
470#define ST0_MX 0x01000000
471
472/*
473 * Status register bits available in all MIPS CPUs.
474 */
475#define ST0_IM 0x0000ff00
476#define STATUSB_IP0 8
477#define STATUSF_IP0 (_ULCAST_(1) << 8)
478#define STATUSB_IP1 9
479#define STATUSF_IP1 (_ULCAST_(1) << 9)
480#define STATUSB_IP2 10
481#define STATUSF_IP2 (_ULCAST_(1) << 10)
482#define STATUSB_IP3 11
483#define STATUSF_IP3 (_ULCAST_(1) << 11)
484#define STATUSB_IP4 12
485#define STATUSF_IP4 (_ULCAST_(1) << 12)
486#define STATUSB_IP5 13
487#define STATUSF_IP5 (_ULCAST_(1) << 13)
488#define STATUSB_IP6 14
489#define STATUSF_IP6 (_ULCAST_(1) << 14)
490#define STATUSB_IP7 15
491#define STATUSF_IP7 (_ULCAST_(1) << 15)
492#define STATUSB_IP8 0
493#define STATUSF_IP8 (_ULCAST_(1) << 0)
494#define STATUSB_IP9 1
495#define STATUSF_IP9 (_ULCAST_(1) << 1)
496#define STATUSB_IP10 2
497#define STATUSF_IP10 (_ULCAST_(1) << 2)
498#define STATUSB_IP11 3
499#define STATUSF_IP11 (_ULCAST_(1) << 3)
500#define STATUSB_IP12 4
501#define STATUSF_IP12 (_ULCAST_(1) << 4)
502#define STATUSB_IP13 5
503#define STATUSF_IP13 (_ULCAST_(1) << 5)
504#define STATUSB_IP14 6
505#define STATUSF_IP14 (_ULCAST_(1) << 6)
506#define STATUSB_IP15 7
507#define STATUSF_IP15 (_ULCAST_(1) << 7)
508#define ST0_CH 0x00040000
509#define ST0_NMI 0x00080000
510#define ST0_SR 0x00100000
511#define ST0_TS 0x00200000
512#define ST0_BEV 0x00400000
513#define ST0_RE 0x02000000
514#define ST0_FR 0x04000000
515#define ST0_CU 0xf0000000
516#define ST0_CU0 0x10000000
517#define ST0_CU1 0x20000000
518#define ST0_CU2 0x40000000
519#define ST0_CU3 0x80000000
520#define ST0_XX 0x80000000 /* MIPS IV naming */
521
522/* in-kernel enabled CUs */
523#ifdef CONFIG_CPU_LOONGSON64
524#define ST0_KERNEL_CUMASK (ST0_CU0 | ST0_CU2)
525#else
526#define ST0_KERNEL_CUMASK ST0_CU0
527#endif
528
529/*
530 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
531 */
532#define INTCTLB_IPFDC 23
533#define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
534#define INTCTLB_IPPCI 26
535#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
536#define INTCTLB_IPTI 29
537#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
538
539/*
540 * Bitfields and bit numbers in the coprocessor 0 cause register.
541 *
542 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
543 */
544#define CAUSEB_EXCCODE 2
545#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
546#define CAUSEB_IP 8
547#define CAUSEF_IP (_ULCAST_(255) << 8)
548#define CAUSEB_IP0 8
549#define CAUSEF_IP0 (_ULCAST_(1) << 8)
550#define CAUSEB_IP1 9
551#define CAUSEF_IP1 (_ULCAST_(1) << 9)
552#define CAUSEB_IP2 10
553#define CAUSEF_IP2 (_ULCAST_(1) << 10)
554#define CAUSEB_IP3 11
555#define CAUSEF_IP3 (_ULCAST_(1) << 11)
556#define CAUSEB_IP4 12
557#define CAUSEF_IP4 (_ULCAST_(1) << 12)
558#define CAUSEB_IP5 13
559#define CAUSEF_IP5 (_ULCAST_(1) << 13)
560#define CAUSEB_IP6 14
561#define CAUSEF_IP6 (_ULCAST_(1) << 14)
562#define CAUSEB_IP7 15
563#define CAUSEF_IP7 (_ULCAST_(1) << 15)
564#define CAUSEB_FDCI 21
565#define CAUSEF_FDCI (_ULCAST_(1) << 21)
566#define CAUSEB_WP 22
567#define CAUSEF_WP (_ULCAST_(1) << 22)
568#define CAUSEB_IV 23
569#define CAUSEF_IV (_ULCAST_(1) << 23)
570#define CAUSEB_PCI 26
571#define CAUSEF_PCI (_ULCAST_(1) << 26)
572#define CAUSEB_DC 27
573#define CAUSEF_DC (_ULCAST_(1) << 27)
574#define CAUSEB_CE 28
575#define CAUSEF_CE (_ULCAST_(3) << 28)
576#define CAUSEB_TI 30
577#define CAUSEF_TI (_ULCAST_(1) << 30)
578#define CAUSEB_BD 31
579#define CAUSEF_BD (_ULCAST_(1) << 31)
580
581/*
582 * Cause.ExcCode trap codes.
583 */
584#define EXCCODE_INT 0 /* Interrupt pending */
585#define EXCCODE_MOD 1 /* TLB modified fault */
586#define EXCCODE_TLBL 2 /* TLB miss on load or ifetch */
587#define EXCCODE_TLBS 3 /* TLB miss on a store */
588#define EXCCODE_ADEL 4 /* Address error on a load or ifetch */
589#define EXCCODE_ADES 5 /* Address error on a store */
590#define EXCCODE_IBE 6 /* Bus error on an ifetch */
591#define EXCCODE_DBE 7 /* Bus error on a load or store */
592#define EXCCODE_SYS 8 /* System call */
593#define EXCCODE_BP 9 /* Breakpoint */
594#define EXCCODE_RI 10 /* Reserved instruction exception */
595#define EXCCODE_CPU 11 /* Coprocessor unusable */
596#define EXCCODE_OV 12 /* Arithmetic overflow */
597#define EXCCODE_TR 13 /* Trap instruction */
598#define EXCCODE_MSAFPE 14 /* MSA floating point exception */
599#define EXCCODE_FPE 15 /* Floating point exception */
600#define EXCCODE_TLBRI 19 /* TLB Read-Inhibit exception */
601#define EXCCODE_TLBXI 20 /* TLB Execution-Inhibit exception */
602#define EXCCODE_MSADIS 21 /* MSA disabled exception */
603#define EXCCODE_MDMX 22 /* MDMX unusable exception */
604#define EXCCODE_WATCH 23 /* Watch address reference */
605#define EXCCODE_MCHECK 24 /* Machine check */
606#define EXCCODE_THREAD 25 /* Thread exceptions (MT) */
607#define EXCCODE_DSPDIS 26 /* DSP disabled exception */
608#define EXCCODE_GE 27 /* Virtualized guest exception (VZ) */
609#define EXCCODE_CACHEERR 30 /* Parity/ECC occurred on a core */
610
611/* Implementation specific trap codes used by MIPS cores */
612#define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */
613
614/* Implementation specific trap codes used by Loongson cores */
615#define LOONGSON_EXCCODE_GSEXC 16 /* Loongson-specific exception */
616
617/*
618 * Bits in the coprocessor 0 config register.
619 */
620/* Generic bits. */
621#define CONF_CM_CACHABLE_NO_WA 0
622#define CONF_CM_CACHABLE_WA 1
623#define CONF_CM_UNCACHED 2
624#define CONF_CM_CACHABLE_NONCOHERENT 3
625#define CONF_CM_CACHABLE_CE 4
626#define CONF_CM_CACHABLE_COW 5
627#define CONF_CM_CACHABLE_CUW 6
628#define CONF_CM_CACHABLE_ACCELERATED 7
629#define CONF_CM_CMASK 7
630#define CONF_BE (_ULCAST_(1) << 15)
631
632/* Bits common to various processors. */
633#define CONF_CU (_ULCAST_(1) << 3)
634#define CONF_DB (_ULCAST_(1) << 4)
635#define CONF_IB (_ULCAST_(1) << 5)
636#define CONF_DC (_ULCAST_(7) << 6)
637#define CONF_IC (_ULCAST_(7) << 9)
638#define CONF_EB (_ULCAST_(1) << 13)
639#define CONF_EM (_ULCAST_(1) << 14)
640#define CONF_SM (_ULCAST_(1) << 16)
641#define CONF_SC (_ULCAST_(1) << 17)
642#define CONF_EW (_ULCAST_(3) << 18)
643#define CONF_EP (_ULCAST_(15)<< 24)
644#define CONF_EC (_ULCAST_(7) << 28)
645#define CONF_CM (_ULCAST_(1) << 31)
646
647/* Bits specific to the R4xx0. */
648#define R4K_CONF_SW (_ULCAST_(1) << 20)
649#define R4K_CONF_SS (_ULCAST_(1) << 21)
650#define R4K_CONF_SB (_ULCAST_(3) << 22)
651
652/* Bits specific to the R5000. */
653#define R5K_CONF_SE (_ULCAST_(1) << 12)
654#define R5K_CONF_SS (_ULCAST_(3) << 20)
655
656/* Bits specific to the RM7000. */
657#define RM7K_CONF_SE (_ULCAST_(1) << 3)
658#define RM7K_CONF_TE (_ULCAST_(1) << 12)
659#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
660#define RM7K_CONF_TC (_ULCAST_(1) << 17)
661#define RM7K_CONF_SI (_ULCAST_(3) << 20)
662#define RM7K_CONF_SC (_ULCAST_(1) << 31)
663
664/* Bits specific to the R10000. */
665#define R10K_CONF_DN (_ULCAST_(3) << 3)
666#define R10K_CONF_CT (_ULCAST_(1) << 5)
667#define R10K_CONF_PE (_ULCAST_(1) << 6)
668#define R10K_CONF_PM (_ULCAST_(3) << 7)
669#define R10K_CONF_EC (_ULCAST_(15)<< 9)
670#define R10K_CONF_SB (_ULCAST_(1) << 13)
671#define R10K_CONF_SK (_ULCAST_(1) << 14)
672#define R10K_CONF_SS (_ULCAST_(7) << 16)
673#define R10K_CONF_SC (_ULCAST_(7) << 19)
674#define R10K_CONF_DC (_ULCAST_(7) << 26)
675#define R10K_CONF_IC (_ULCAST_(7) << 29)
676
677/* Bits specific to the VR41xx. */
678#define VR41_CONF_CS (_ULCAST_(1) << 12)
679#define VR41_CONF_P4K (_ULCAST_(1) << 13)
680#define VR41_CONF_BP (_ULCAST_(1) << 16)
681#define VR41_CONF_M16 (_ULCAST_(1) << 20)
682#define VR41_CONF_AD (_ULCAST_(1) << 23)
683
684/* Bits specific to the R30xx. */
685#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
686#define R30XX_CONF_REV (_ULCAST_(1) << 22)
687#define R30XX_CONF_AC (_ULCAST_(1) << 23)
688#define R30XX_CONF_RF (_ULCAST_(1) << 24)
689#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
690#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
691#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
692#define R30XX_CONF_SB (_ULCAST_(1) << 30)
693#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
694
695/* Bits specific to the TX49. */
696#define TX49_CONF_DC (_ULCAST_(1) << 16)
697#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
698#define TX49_CONF_HALT (_ULCAST_(1) << 18)
699#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
700
701/* Bits specific to the MIPS32/64 PRA. */
702#define MIPS_CONF_VI (_ULCAST_(1) << 3)
703#define MIPS_CONF_MT (_ULCAST_(7) << 7)
704#define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
705#define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
706#define MIPS_CONF_AR (_ULCAST_(7) << 10)
707#define MIPS_CONF_AT (_ULCAST_(3) << 13)
708#define MIPS_CONF_BE (_ULCAST_(1) << 15)
709#define MIPS_CONF_BM (_ULCAST_(1) << 16)
710#define MIPS_CONF_MM (_ULCAST_(3) << 17)
711#define MIPS_CONF_MM_SYSAD (_ULCAST_(1) << 17)
712#define MIPS_CONF_MM_FULL (_ULCAST_(2) << 17)
713#define MIPS_CONF_SB (_ULCAST_(1) << 21)
714#define MIPS_CONF_UDI (_ULCAST_(1) << 22)
715#define MIPS_CONF_DSP (_ULCAST_(1) << 23)
716#define MIPS_CONF_ISP (_ULCAST_(1) << 24)
717#define MIPS_CONF_KU (_ULCAST_(3) << 25)
718#define MIPS_CONF_K23 (_ULCAST_(3) << 28)
719#define MIPS_CONF_M (_ULCAST_(1) << 31)
720
721/*
722 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
723 */
724#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
725#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
726#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
727#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
728#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
729#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
730#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
731#define MIPS_CONF1_DA_SHF 7
732#define MIPS_CONF1_DA_SZ 3
733#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
734#define MIPS_CONF1_DL_SHF 10
735#define MIPS_CONF1_DL_SZ 3
736#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
737#define MIPS_CONF1_DS_SHF 13
738#define MIPS_CONF1_DS_SZ 3
739#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
740#define MIPS_CONF1_IA_SHF 16
741#define MIPS_CONF1_IA_SZ 3
742#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
743#define MIPS_CONF1_IL_SHF 19
744#define MIPS_CONF1_IL_SZ 3
745#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
746#define MIPS_CONF1_IS_SHF 22
747#define MIPS_CONF1_IS_SZ 3
748#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
749#define MIPS_CONF1_TLBS_SHIFT (25)
750#define MIPS_CONF1_TLBS_SIZE (6)
751#define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
752
753#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
754#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
755#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
756#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
757#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
758#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
759#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
760#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
761
762#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
763#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
764#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
765#define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
766#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
767#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
768#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
769#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
770#define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
771#define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
772#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
773#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
774#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
775#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
776#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
777#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
778#define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
779#define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
780#define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
781#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
782#define MIPS_CONF3_PW (_ULCAST_(1) << 24)
783#define MIPS_CONF3_SC (_ULCAST_(1) << 25)
784#define MIPS_CONF3_BI (_ULCAST_(1) << 26)
785#define MIPS_CONF3_BP (_ULCAST_(1) << 27)
786#define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
787#define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
788#define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
789
790#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
791#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
792#define MIPS_CONF4_FTLBSETS_SHIFT (0)
793#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
794#define MIPS_CONF4_FTLBWAYS_SHIFT (4)
795#define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
796#define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
797/* bits 10:8 in FTLB-only configurations */
798#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
799/* bits 12:8 in VTLB-FTLB only configurations */
800#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
801#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
802#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
803#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
804#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
805#define MIPS_CONF4_KSCREXIST_SHIFT (16)
806#define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
807#define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
808#define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
809#define MIPS_CONF4_AE (_ULCAST_(1) << 28)
810#define MIPS_CONF4_IE (_ULCAST_(3) << 29)
811#define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
812
813#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
814#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
815#define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
816#define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
817#define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
818#define MIPS_CONF5_VP (_ULCAST_(1) << 7)
819#define MIPS_CONF5_SBRI (_ULCAST_(1) << 6)
820#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
821#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
822#define MIPS_CONF5_CA2 (_ULCAST_(1) << 14)
823#define MIPS_CONF5_MI (_ULCAST_(1) << 17)
824#define MIPS_CONF5_CRCP (_ULCAST_(1) << 18)
825#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
826#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
827#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
828#define MIPS_CONF5_K (_ULCAST_(1) << 30)
829
830/* Config6 feature bits for proAptiv/P5600 */
831
832/* Jump register cache prediction disable */
833#define MTI_CONF6_JRCD (_ULCAST_(1) << 0)
834/* MIPSr6 extensions enable */
835#define MTI_CONF6_R6 (_ULCAST_(1) << 2)
836/* IFU Performance Control */
837#define MTI_CONF6_IFUPERFCTL (_ULCAST_(3) << 10)
838#define MTI_CONF6_SYND (_ULCAST_(1) << 13)
839/* Sleep state performance counter disable */
840#define MTI_CONF6_SPCD (_ULCAST_(1) << 14)
841/* proAptiv FTLB on/off bit */
842#define MTI_CONF6_FTLBEN (_ULCAST_(1) << 15)
843/* Disable load/store bonding */
844#define MTI_CONF6_DLSB (_ULCAST_(1) << 21)
845/* FTLB probability bits */
846#define MTI_CONF6_FTLBP_SHIFT (16)
847
848/* Config6 feature bits for Loongson-3 */
849
850/* Loongson-3 internal timer bit */
851#define LOONGSON_CONF6_INTIMER (_ULCAST_(1) << 6)
852/* Loongson-3 external timer bit */
853#define LOONGSON_CONF6_EXTIMER (_ULCAST_(1) << 7)
854/* Loongson-3 SFB on/off bit, STFill in manual */
855#define LOONGSON_CONF6_SFBEN (_ULCAST_(1) << 8)
856/* Loongson-3's LL on exclusive cacheline */
857#define LOONGSON_CONF6_LLEXC (_ULCAST_(1) << 16)
858/* Loongson-3's SC has a random delay */
859#define LOONGSON_CONF6_SCRAND (_ULCAST_(1) << 17)
860/* Loongson-3 FTLB on/off bit, VTLBOnly in manual */
861#define LOONGSON_CONF6_FTLBDIS (_ULCAST_(1) << 22)
862
863#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
864
865#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
866
867#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
868#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
869
870/* Ingenic HPTLB off bits */
871#define XBURST_PAGECTRL_HPTLB_DIS 0xa9000000
872
873/* Ingenic Config7 bits */
874#define MIPS_CONF7_BTB_LOOP_EN (_ULCAST_(1) << 4)
875
876/* Config7 Bits specific to MIPS Technologies. */
877
878/* Performance counters implemented Per TC */
879#define MTI_CONF7_PTC (_ULCAST_(1) << 19)
880
881/* WatchLo* register definitions */
882#define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0)
883
884/* WatchHi* register definitions */
885#define MIPS_WATCHHI_M (_ULCAST_(1) << 31)
886#define MIPS_WATCHHI_G (_ULCAST_(1) << 30)
887#define MIPS_WATCHHI_WM (_ULCAST_(0x3) << 28)
888#define MIPS_WATCHHI_WM_R_RVA (_ULCAST_(0) << 28)
889#define MIPS_WATCHHI_WM_R_GPA (_ULCAST_(1) << 28)
890#define MIPS_WATCHHI_WM_G_GVA (_ULCAST_(2) << 28)
891#define MIPS_WATCHHI_EAS (_ULCAST_(0x3) << 24)
892#define MIPS_WATCHHI_ASID (_ULCAST_(0xff) << 16)
893#define MIPS_WATCHHI_MASK (_ULCAST_(0x1ff) << 3)
894#define MIPS_WATCHHI_I (_ULCAST_(1) << 2)
895#define MIPS_WATCHHI_R (_ULCAST_(1) << 1)
896#define MIPS_WATCHHI_W (_ULCAST_(1) << 0)
897#define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0)
898
899/* PerfCnt control register definitions */
900#define MIPS_PERFCTRL_EXL (_ULCAST_(1) << 0)
901#define MIPS_PERFCTRL_K (_ULCAST_(1) << 1)
902#define MIPS_PERFCTRL_S (_ULCAST_(1) << 2)
903#define MIPS_PERFCTRL_U (_ULCAST_(1) << 3)
904#define MIPS_PERFCTRL_IE (_ULCAST_(1) << 4)
905#define MIPS_PERFCTRL_EVENT_S 5
906#define MIPS_PERFCTRL_EVENT (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
907#define MIPS_PERFCTRL_PCTD (_ULCAST_(1) << 15)
908#define MIPS_PERFCTRL_EC (_ULCAST_(0x3) << 23)
909#define MIPS_PERFCTRL_EC_R (_ULCAST_(0) << 23)
910#define MIPS_PERFCTRL_EC_RI (_ULCAST_(1) << 23)
911#define MIPS_PERFCTRL_EC_G (_ULCAST_(2) << 23)
912#define MIPS_PERFCTRL_EC_GRI (_ULCAST_(3) << 23)
913#define MIPS_PERFCTRL_W (_ULCAST_(1) << 30)
914#define MIPS_PERFCTRL_M (_ULCAST_(1) << 31)
915
916/* PerfCnt control register MT extensions used by MIPS cores */
917#define MIPS_PERFCTRL_VPEID_S 16
918#define MIPS_PERFCTRL_VPEID (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
919#define MIPS_PERFCTRL_TCID_S 22
920#define MIPS_PERFCTRL_TCID (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
921#define MIPS_PERFCTRL_MT_EN (_ULCAST_(0x3) << 20)
922#define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
923#define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20)
924#define MIPS_PERFCTRL_MT_EN_TC (_ULCAST_(2) << 20)
925
926/* PerfCnt control register MT extensions used by BMIPS5000 */
927#define BRCM_PERFCTRL_TC (_ULCAST_(1) << 30)
928
929/* PerfCnt control register MT extensions used by Netlogic XLR */
930#define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13)
931
932/* MAAR bit definitions */
933#define MIPS_MAAR_VH (_U64CAST_(1) << 63)
934#define MIPS_MAAR_ADDR GENMASK_ULL(55, 12)
935#define MIPS_MAAR_ADDR_SHIFT 12
936#define MIPS_MAAR_S (_ULCAST_(1) << 1)
937#define MIPS_MAAR_VL (_ULCAST_(1) << 0)
938#ifdef CONFIG_XPA
939#define MIPS_MAAR_V (MIPS_MAAR_VH | MIPS_MAAR_VL)
940#else
941#define MIPS_MAAR_V MIPS_MAAR_VL
942#endif
943#define MIPS_MAARX_VH (_ULCAST_(1) << 31)
944#define MIPS_MAARX_ADDR 0xF
945#define MIPS_MAARX_ADDR_SHIFT 32
946
947/* MAARI bit definitions */
948#define MIPS_MAARI_INDEX (_ULCAST_(0x3f) << 0)
949
950/* EBase bit definitions */
951#define MIPS_EBASE_CPUNUM_SHIFT 0
952#define MIPS_EBASE_CPUNUM (_ULCAST_(0x3ff) << 0)
953#define MIPS_EBASE_WG_SHIFT 11
954#define MIPS_EBASE_WG (_ULCAST_(1) << 11)
955#define MIPS_EBASE_BASE_SHIFT 12
956#define MIPS_EBASE_BASE (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
957
958/* CMGCRBase bit definitions */
959#define MIPS_CMGCRB_BASE 11
960#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
961
962/* LLAddr bit definitions */
963#define MIPS_LLADDR_LLB_SHIFT 0
964#define MIPS_LLADDR_LLB (_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
965
966/*
967 * Bits in the MIPS32 Memory Segmentation registers.
968 */
969#define MIPS_SEGCFG_PA_SHIFT 9
970#define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
971#define MIPS_SEGCFG_AM_SHIFT 4
972#define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
973#define MIPS_SEGCFG_EU_SHIFT 3
974#define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
975#define MIPS_SEGCFG_C_SHIFT 0
976#define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
977
978#define MIPS_SEGCFG_UUSK _ULCAST_(7)
979#define MIPS_SEGCFG_USK _ULCAST_(5)
980#define MIPS_SEGCFG_MUSUK _ULCAST_(4)
981#define MIPS_SEGCFG_MUSK _ULCAST_(3)
982#define MIPS_SEGCFG_MSK _ULCAST_(2)
983#define MIPS_SEGCFG_MK _ULCAST_(1)
984#define MIPS_SEGCFG_UK _ULCAST_(0)
985
986#define MIPS_PWFIELD_GDI_SHIFT 24
987#define MIPS_PWFIELD_GDI_MASK 0x3f000000
988#define MIPS_PWFIELD_UDI_SHIFT 18
989#define MIPS_PWFIELD_UDI_MASK 0x00fc0000
990#define MIPS_PWFIELD_MDI_SHIFT 12
991#define MIPS_PWFIELD_MDI_MASK 0x0003f000
992#define MIPS_PWFIELD_PTI_SHIFT 6
993#define MIPS_PWFIELD_PTI_MASK 0x00000fc0
994#define MIPS_PWFIELD_PTEI_SHIFT 0
995#define MIPS_PWFIELD_PTEI_MASK 0x0000003f
996
997#define MIPS_PWSIZE_PS_SHIFT 30
998#define MIPS_PWSIZE_PS_MASK 0x40000000
999#define MIPS_PWSIZE_GDW_SHIFT 24
1000#define MIPS_PWSIZE_GDW_MASK 0x3f000000
1001#define MIPS_PWSIZE_UDW_SHIFT 18
1002#define MIPS_PWSIZE_UDW_MASK 0x00fc0000
1003#define MIPS_PWSIZE_MDW_SHIFT 12
1004#define MIPS_PWSIZE_MDW_MASK 0x0003f000
1005#define MIPS_PWSIZE_PTW_SHIFT 6
1006#define MIPS_PWSIZE_PTW_MASK 0x00000fc0
1007#define MIPS_PWSIZE_PTEW_SHIFT 0
1008#define MIPS_PWSIZE_PTEW_MASK 0x0000003f
1009
1010#define MIPS_PWCTL_PWEN_SHIFT 31
1011#define MIPS_PWCTL_PWEN_MASK 0x80000000
1012#define MIPS_PWCTL_XK_SHIFT 28
1013#define MIPS_PWCTL_XK_MASK 0x10000000
1014#define MIPS_PWCTL_XS_SHIFT 27
1015#define MIPS_PWCTL_XS_MASK 0x08000000
1016#define MIPS_PWCTL_XU_SHIFT 26
1017#define MIPS_PWCTL_XU_MASK 0x04000000
1018#define MIPS_PWCTL_DPH_SHIFT 7
1019#define MIPS_PWCTL_DPH_MASK 0x00000080
1020#define MIPS_PWCTL_HUGEPG_SHIFT 6
1021#define MIPS_PWCTL_HUGEPG_MASK 0x00000060
1022#define MIPS_PWCTL_PSN_SHIFT 0
1023#define MIPS_PWCTL_PSN_MASK 0x0000003f
1024
1025/* GuestCtl0 fields */
1026#define MIPS_GCTL0_GM_SHIFT 31
1027#define MIPS_GCTL0_GM (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
1028#define MIPS_GCTL0_RI_SHIFT 30
1029#define MIPS_GCTL0_RI (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
1030#define MIPS_GCTL0_MC_SHIFT 29
1031#define MIPS_GCTL0_MC (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
1032#define MIPS_GCTL0_CP0_SHIFT 28
1033#define MIPS_GCTL0_CP0 (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
1034#define MIPS_GCTL0_AT_SHIFT 26
1035#define MIPS_GCTL0_AT (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
1036#define MIPS_GCTL0_GT_SHIFT 25
1037#define MIPS_GCTL0_GT (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
1038#define MIPS_GCTL0_CG_SHIFT 24
1039#define MIPS_GCTL0_CG (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
1040#define MIPS_GCTL0_CF_SHIFT 23
1041#define MIPS_GCTL0_CF (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
1042#define MIPS_GCTL0_G1_SHIFT 22
1043#define MIPS_GCTL0_G1 (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
1044#define MIPS_GCTL0_G0E_SHIFT 19
1045#define MIPS_GCTL0_G0E (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
1046#define MIPS_GCTL0_PT_SHIFT 18
1047#define MIPS_GCTL0_PT (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
1048#define MIPS_GCTL0_RAD_SHIFT 9
1049#define MIPS_GCTL0_RAD (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
1050#define MIPS_GCTL0_DRG_SHIFT 8
1051#define MIPS_GCTL0_DRG (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
1052#define MIPS_GCTL0_G2_SHIFT 7
1053#define MIPS_GCTL0_G2 (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
1054#define MIPS_GCTL0_GEXC_SHIFT 2
1055#define MIPS_GCTL0_GEXC (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
1056#define MIPS_GCTL0_SFC2_SHIFT 1
1057#define MIPS_GCTL0_SFC2 (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
1058#define MIPS_GCTL0_SFC1_SHIFT 0
1059#define MIPS_GCTL0_SFC1 (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
1060
1061/* GuestCtl0.AT Guest address translation control */
1062#define MIPS_GCTL0_AT_ROOT 1 /* Guest MMU under Root control */
1063#define MIPS_GCTL0_AT_GUEST 3 /* Guest MMU under Guest control */
1064
1065/* GuestCtl0.GExcCode Hypervisor exception cause codes */
1066#define MIPS_GCTL0_GEXC_GPSI 0 /* Guest Privileged Sensitive Instruction */
1067#define MIPS_GCTL0_GEXC_GSFC 1 /* Guest Software Field Change */
1068#define MIPS_GCTL0_GEXC_HC 2 /* Hypercall */
1069#define MIPS_GCTL0_GEXC_GRR 3 /* Guest Reserved Instruction Redirect */
1070#define MIPS_GCTL0_GEXC_GVA 8 /* Guest Virtual Address available */
1071#define MIPS_GCTL0_GEXC_GHFC 9 /* Guest Hardware Field Change */
1072#define MIPS_GCTL0_GEXC_GPA 10 /* Guest Physical Address available */
1073
1074/* GuestCtl0Ext fields */
1075#define MIPS_GCTL0EXT_RPW_SHIFT 8
1076#define MIPS_GCTL0EXT_RPW (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
1077#define MIPS_GCTL0EXT_NCC_SHIFT 6
1078#define MIPS_GCTL0EXT_NCC (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
1079#define MIPS_GCTL0EXT_CGI_SHIFT 4
1080#define MIPS_GCTL0EXT_CGI (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
1081#define MIPS_GCTL0EXT_FCD_SHIFT 3
1082#define MIPS_GCTL0EXT_FCD (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
1083#define MIPS_GCTL0EXT_OG_SHIFT 2
1084#define MIPS_GCTL0EXT_OG (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
1085#define MIPS_GCTL0EXT_BG_SHIFT 1
1086#define MIPS_GCTL0EXT_BG (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
1087#define MIPS_GCTL0EXT_MG_SHIFT 0
1088#define MIPS_GCTL0EXT_MG (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
1089
1090/* GuestCtl0Ext.RPW Root page walk configuration */
1091#define MIPS_GCTL0EXT_RPW_BOTH 0 /* Root PW for GPA->RPA and RVA->RPA */
1092#define MIPS_GCTL0EXT_RPW_GPA 2 /* Root PW for GPA->RPA */
1093#define MIPS_GCTL0EXT_RPW_RVA 3 /* Root PW for RVA->RPA */
1094
1095/* GuestCtl0Ext.NCC Nested cache coherency attributes */
1096#define MIPS_GCTL0EXT_NCC_IND 0 /* Guest CCA independent of Root CCA */
1097#define MIPS_GCTL0EXT_NCC_MOD 1 /* Guest CCA modified by Root CCA */
1098
1099/* GuestCtl1 fields */
1100#define MIPS_GCTL1_ID_SHIFT 0
1101#define MIPS_GCTL1_ID_WIDTH 8
1102#define MIPS_GCTL1_ID (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
1103#define MIPS_GCTL1_RID_SHIFT 16
1104#define MIPS_GCTL1_RID_WIDTH 8
1105#define MIPS_GCTL1_RID (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
1106#define MIPS_GCTL1_EID_SHIFT 24
1107#define MIPS_GCTL1_EID_WIDTH 8
1108#define MIPS_GCTL1_EID (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
1109
1110/* GuestID reserved for root context */
1111#define MIPS_GCTL1_ROOT_GUESTID 0
1112
1113/* CDMMBase register bit definitions */
1114#define MIPS_CDMMBASE_SIZE_SHIFT 0
1115#define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
1116#define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
1117#define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
1118#define MIPS_CDMMBASE_ADDR_SHIFT 11
1119#define MIPS_CDMMBASE_ADDR_START 15
1120
1121/* RDHWR register numbers */
1122#define MIPS_HWR_CPUNUM 0 /* CPU number */
1123#define MIPS_HWR_SYNCISTEP 1 /* SYNCI step size */
1124#define MIPS_HWR_CC 2 /* Cycle counter */
1125#define MIPS_HWR_CCRES 3 /* Cycle counter resolution */
1126#define MIPS_HWR_ULR 29 /* UserLocal */
1127#define MIPS_HWR_IMPL1 30 /* Implementation dependent */
1128#define MIPS_HWR_IMPL2 31 /* Implementation dependent */
1129
1130/* Bits in HWREna register */
1131#define MIPS_HWRENA_CPUNUM (_ULCAST_(1) << MIPS_HWR_CPUNUM)
1132#define MIPS_HWRENA_SYNCISTEP (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
1133#define MIPS_HWRENA_CC (_ULCAST_(1) << MIPS_HWR_CC)
1134#define MIPS_HWRENA_CCRES (_ULCAST_(1) << MIPS_HWR_CCRES)
1135#define MIPS_HWRENA_ULR (_ULCAST_(1) << MIPS_HWR_ULR)
1136#define MIPS_HWRENA_IMPL1 (_ULCAST_(1) << MIPS_HWR_IMPL1)
1137#define MIPS_HWRENA_IMPL2 (_ULCAST_(1) << MIPS_HWR_IMPL2)
1138
1139/*
1140 * Bitfields in the TX39 family CP0 Configuration Register 3
1141 */
1142#define TX39_CONF_ICS_SHIFT 19
1143#define TX39_CONF_ICS_MASK 0x00380000
1144#define TX39_CONF_ICS_1KB 0x00000000
1145#define TX39_CONF_ICS_2KB 0x00080000
1146#define TX39_CONF_ICS_4KB 0x00100000
1147#define TX39_CONF_ICS_8KB 0x00180000
1148#define TX39_CONF_ICS_16KB 0x00200000
1149
1150#define TX39_CONF_DCS_SHIFT 16
1151#define TX39_CONF_DCS_MASK 0x00070000
1152#define TX39_CONF_DCS_1KB 0x00000000
1153#define TX39_CONF_DCS_2KB 0x00010000
1154#define TX39_CONF_DCS_4KB 0x00020000
1155#define TX39_CONF_DCS_8KB 0x00030000
1156#define TX39_CONF_DCS_16KB 0x00040000
1157
1158#define TX39_CONF_CWFON 0x00004000
1159#define TX39_CONF_WBON 0x00002000
1160#define TX39_CONF_RF_SHIFT 10
1161#define TX39_CONF_RF_MASK 0x00000c00
1162#define TX39_CONF_DOZE 0x00000200
1163#define TX39_CONF_HALT 0x00000100
1164#define TX39_CONF_LOCK 0x00000080
1165#define TX39_CONF_ICE 0x00000020
1166#define TX39_CONF_DCE 0x00000010
1167#define TX39_CONF_IRSIZE_SHIFT 2
1168#define TX39_CONF_IRSIZE_MASK 0x0000000c
1169#define TX39_CONF_DRSIZE_SHIFT 0
1170#define TX39_CONF_DRSIZE_MASK 0x00000003
1171
1172/*
1173 * Interesting Bits in the R10K CP0 Branch Diagnostic Register
1174 */
1175/* Disable Branch Target Address Cache */
1176#define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
1177/* Enable Branch Prediction Global History */
1178#define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
1179/* Disable Branch Return Cache */
1180#define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
1181
1182/* Flush BTB */
1183#define LOONGSON_DIAG_BTB (_ULCAST_(1) << 1)
1184/* Flush ITLB */
1185#define LOONGSON_DIAG_ITLB (_ULCAST_(1) << 2)
1186/* Flush DTLB */
1187#define LOONGSON_DIAG_DTLB (_ULCAST_(1) << 3)
1188/* Allow some CACHE instructions (CACHE0, 1, 3, 21 and 23) in user mode */
1189#define LOONGSON_DIAG_UCAC (_ULCAST_(1) << 8)
1190/* Flush VTLB */
1191#define LOONGSON_DIAG_VTLB (_ULCAST_(1) << 12)
1192/* Flush FTLB */
1193#define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13)
1194
1195/*
1196 * Diag1 (GSCause in Loongson-speak) fields
1197 */
1198/* Loongson-specific exception code (GSExcCode) */
1199#define LOONGSON_DIAG1_EXCCODE_SHIFT 2
1200#define LOONGSON_DIAG1_EXCCODE GENMASK(6, 2)
1201
1202/* CvmCtl register field definitions */
1203#define CVMCTL_IPPCI_SHIFT 7
1204#define CVMCTL_IPPCI (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
1205#define CVMCTL_IPTI_SHIFT 4
1206#define CVMCTL_IPTI (_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
1207
1208/* CvmMemCtl2 register field definitions */
1209#define CVMMEMCTL2_INHIBITTS (_U64CAST_(1) << 17)
1210
1211/* CvmVMConfig register field definitions */
1212#define CVMVMCONF_DGHT (_U64CAST_(1) << 60)
1213#define CVMVMCONF_MMUSIZEM1_S 12
1214#define CVMVMCONF_MMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
1215#define CVMVMCONF_RMMUSIZEM1_S 0
1216#define CVMVMCONF_RMMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
1217
1218/* Debug register field definitions */
1219#define MIPS_DEBUG_DBP_SHIFT 1
1220#define MIPS_DEBUG_DBP (_ULCAST_(1) << MIPS_DEBUG_DBP_SHIFT)
1221
1222/*
1223 * Coprocessor 1 (FPU) register names
1224 */
1225#define CP1_REVISION $0
1226#define CP1_UFR $1
1227#define CP1_UNFR $4
1228#define CP1_FCCR $25
1229#define CP1_FEXR $26
1230#define CP1_FENR $28
1231#define CP1_STATUS $31
1232
1233
1234/*
1235 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
1236 */
1237#define MIPS_FPIR_S (_ULCAST_(1) << 16)
1238#define MIPS_FPIR_D (_ULCAST_(1) << 17)
1239#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
1240#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
1241#define MIPS_FPIR_W (_ULCAST_(1) << 20)
1242#define MIPS_FPIR_L (_ULCAST_(1) << 21)
1243#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
1244#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
1245#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
1246#define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
1247
1248/*
1249 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
1250 */
1251#define MIPS_FCCR_CONDX_S 0
1252#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
1253#define MIPS_FCCR_COND0_S 0
1254#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
1255#define MIPS_FCCR_COND1_S 1
1256#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
1257#define MIPS_FCCR_COND2_S 2
1258#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
1259#define MIPS_FCCR_COND3_S 3
1260#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
1261#define MIPS_FCCR_COND4_S 4
1262#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
1263#define MIPS_FCCR_COND5_S 5
1264#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
1265#define MIPS_FCCR_COND6_S 6
1266#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
1267#define MIPS_FCCR_COND7_S 7
1268#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
1269
1270/*
1271 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
1272 */
1273#define MIPS_FENR_FS_S 2
1274#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
1275
1276/*
1277 * FPU Status Register Values
1278 */
1279#define FPU_CSR_COND_S 23 /* $fcc0 */
1280#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
1281
1282#define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
1283#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
1284
1285#define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
1286#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
1287#define FPU_CSR_COND1_S 25 /* $fcc1 */
1288#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
1289#define FPU_CSR_COND2_S 26 /* $fcc2 */
1290#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
1291#define FPU_CSR_COND3_S 27 /* $fcc3 */
1292#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
1293#define FPU_CSR_COND4_S 28 /* $fcc4 */
1294#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
1295#define FPU_CSR_COND5_S 29 /* $fcc5 */
1296#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
1297#define FPU_CSR_COND6_S 30 /* $fcc6 */
1298#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
1299#define FPU_CSR_COND7_S 31 /* $fcc7 */
1300#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
1301
1302/*
1303 * Bits 22:20 of the FPU Status Register will be read as 0,
1304 * and should be written as zero.
1305 * MAC2008 was removed in Release 5 so we still treat it as
1306 * reserved.
1307 */
1308#define FPU_CSR_RSVD (_ULCAST_(7) << 20)
1309
1310#define FPU_CSR_MAC2008 (_ULCAST_(1) << 20)
1311#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
1312#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1313
1314/*
1315 * X the exception cause indicator
1316 * E the exception enable
1317 * S the sticky/flag bit
1318*/
1319#define FPU_CSR_ALL_X 0x0003f000
1320#define FPU_CSR_UNI_X 0x00020000
1321#define FPU_CSR_INV_X 0x00010000
1322#define FPU_CSR_DIV_X 0x00008000
1323#define FPU_CSR_OVF_X 0x00004000
1324#define FPU_CSR_UDF_X 0x00002000
1325#define FPU_CSR_INE_X 0x00001000
1326
1327#define FPU_CSR_ALL_E 0x00000f80
1328#define FPU_CSR_INV_E 0x00000800
1329#define FPU_CSR_DIV_E 0x00000400
1330#define FPU_CSR_OVF_E 0x00000200
1331#define FPU_CSR_UDF_E 0x00000100
1332#define FPU_CSR_INE_E 0x00000080
1333
1334#define FPU_CSR_ALL_S 0x0000007c
1335#define FPU_CSR_INV_S 0x00000040
1336#define FPU_CSR_DIV_S 0x00000020
1337#define FPU_CSR_OVF_S 0x00000010
1338#define FPU_CSR_UDF_S 0x00000008
1339#define FPU_CSR_INE_S 0x00000004
1340
1341/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1342#define FPU_CSR_RM 0x00000003
1343#define FPU_CSR_RN 0x0 /* nearest */
1344#define FPU_CSR_RZ 0x1 /* towards zero */
1345#define FPU_CSR_RU 0x2 /* towards +Infinity */
1346#define FPU_CSR_RD 0x3 /* towards -Infinity */
1347
1348
1349#ifndef __ASSEMBLY__
1350
1351/*
1352 * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1353 */
1354#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1355 defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1356#define get_isa16_mode(x) ((x) & 0x1)
1357#define msk_isa16_mode(x) ((x) & ~0x1)
1358#define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
1359#else
1360#define get_isa16_mode(x) 0
1361#define msk_isa16_mode(x) (x)
1362#define set_isa16_mode(x) do { } while(0)
1363#endif
1364
1365/*
1366 * microMIPS instructions can be 16-bit or 32-bit in length. This
1367 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1368 */
1369static inline int mm_insn_16bit(u16 insn)
1370{
1371 u16 opcode = (insn >> 10) & 0x7;
1372
1373 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1374}
1375
1376/*
1377 * Helper macros for generating raw instruction encodings in inline asm.
1378 */
1379#ifdef CONFIG_CPU_MICROMIPS
1380#define _ASM_INSN16_IF_MM(_enc) \
1381 ".insn\n\t" \
1382 ".hword (" #_enc ")\n\t"
1383#define _ASM_INSN32_IF_MM(_enc) \
1384 ".insn\n\t" \
1385 ".hword ((" #_enc ") >> 16)\n\t" \
1386 ".hword ((" #_enc ") & 0xffff)\n\t"
1387#else
1388#define _ASM_INSN_IF_MIPS(_enc) \
1389 ".insn\n\t" \
1390 ".word (" #_enc ")\n\t"
1391#endif
1392
1393#ifndef _ASM_INSN16_IF_MM
1394#define _ASM_INSN16_IF_MM(_enc)
1395#endif
1396#ifndef _ASM_INSN32_IF_MM
1397#define _ASM_INSN32_IF_MM(_enc)
1398#endif
1399#ifndef _ASM_INSN_IF_MIPS
1400#define _ASM_INSN_IF_MIPS(_enc)
1401#endif
1402
1403/*
1404 * parse_r var, r - Helper assembler macro for parsing register names.
1405 *
1406 * This converts the register name in $n form provided in \r to the
1407 * corresponding register number, which is assigned to the variable \var. It is
1408 * needed to allow explicit encoding of instructions in inline assembly where
1409 * registers are chosen by the compiler in $n form, allowing us to avoid using
1410 * fixed register numbers.
1411 *
1412 * It also allows newer instructions (not implemented by the assembler) to be
1413 * transparently implemented using assembler macros, instead of needing separate
1414 * cases depending on toolchain support.
1415 *
1416 * Simple usage example:
1417 * __asm__ __volatile__("parse_r __rt, %0\n\t"
1418 * ".insn\n\t"
1419 * "# di %0\n\t"
1420 * ".word (0x41606000 | (__rt << 16))"
1421 * : "=r" (status);
1422 */
1423
1424/* Match an individual register number and assign to \var */
1425#define _IFC_REG_NAME(name, n) \
1426 ".ifc \\r, $" #name "\n\t" \
1427 "\\var = " #n "\n\t" \
1428 ".endif\n\t"
1429
1430#define _IFC_REG(n) _IFC_REG_NAME(n, n)
1431
1432#define _ASM_SET_PARSE_R \
1433 ".macro parse_r var r\n\t" \
1434 "\\var = -1\n\t" \
1435 _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3) \
1436 _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7) \
1437 _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11) \
1438 _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15) \
1439 _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19) \
1440 _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23) \
1441 _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27) \
1442 _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31) \
1443 _IFC_REG_NAME(sp, 29) _IFC_REG_NAME(fp, 30) \
1444 ".iflt \\var\n\t" \
1445 ".error \"Unable to parse register name \\r\"\n\t" \
1446 ".endif\n\t" \
1447 ".endm\n\t"
1448#define _ASM_UNSET_PARSE_R ".purgem parse_r\n\t"
1449
1450/*
1451 * C macros for generating assembler macros for common instruction formats.
1452 *
1453 * The names of the operands can be chosen by the caller, and the encoding of
1454 * register operand \<Rn> is assigned to __<Rn> where it can be accessed from
1455 * the ENC encodings.
1456 */
1457
1458/* Instructions with 1 register operand */
1459#define _ASM_MACRO_1R(OP, R1, ENC) \
1460 ".macro " #OP " " #R1 "\n\t" \
1461 _ASM_SET_PARSE_R \
1462 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1463 ENC \
1464 _ASM_UNSET_PARSE_R \
1465 ".endm\n\t"
1466
1467/* Instructions with 1 register operand & 1 immediate operand */
1468#define _ASM_MACRO_1R1I(OP, R1, I2, ENC) \
1469 ".macro " #OP " " #R1 ", " #I2 "\n\t" \
1470 _ASM_SET_PARSE_R \
1471 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1472 ENC \
1473 _ASM_UNSET_PARSE_R \
1474 ".endm\n\t"
1475
1476/* Instructions with 2 register operands */
1477#define _ASM_MACRO_2R(OP, R1, R2, ENC) \
1478 ".macro " #OP " " #R1 ", " #R2 "\n\t" \
1479 _ASM_SET_PARSE_R \
1480 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1481 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1482 ENC \
1483 _ASM_UNSET_PARSE_R \
1484 ".endm\n\t"
1485
1486/* Instructions with 3 register operands */
1487#define _ASM_MACRO_3R(OP, R1, R2, R3, ENC) \
1488 ".macro " #OP " " #R1 ", " #R2 ", " #R3 "\n\t" \
1489 _ASM_SET_PARSE_R \
1490 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1491 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1492 "parse_r __" #R3 ", \\" #R3 "\n\t" \
1493 ENC \
1494 _ASM_UNSET_PARSE_R \
1495 ".endm\n\t"
1496
1497/* Instructions with 2 register operands and 1 optional select operand */
1498#define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC) \
1499 ".macro " #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t" \
1500 _ASM_SET_PARSE_R \
1501 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1502 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1503 ENC \
1504 _ASM_UNSET_PARSE_R \
1505 ".endm\n\t"
1506
1507/*
1508 * TLB Invalidate Flush
1509 */
1510static inline void tlbinvf(void)
1511{
1512 __asm__ __volatile__(
1513 ".set push\n\t"
1514 ".set noreorder\n\t"
1515 "# tlbinvf\n\t"
1516 _ASM_INSN_IF_MIPS(0x42000004)
1517 _ASM_INSN32_IF_MM(0x0000537c)
1518 ".set pop");
1519}
1520
1521
1522/*
1523 * Functions to access the R10000 performance counters. These are basically
1524 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1525 * performance counter number encoded into bits 1 ... 5 of the instruction.
1526 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1527 * disassembler these will look like an access to sel 0 or 1.
1528 */
1529#define read_r10k_perf_cntr(counter) \
1530({ \
1531 unsigned int __res; \
1532 __asm__ __volatile__( \
1533 "mfpc\t%0, %1" \
1534 : "=r" (__res) \
1535 : "i" (counter)); \
1536 \
1537 __res; \
1538})
1539
1540#define write_r10k_perf_cntr(counter,val) \
1541do { \
1542 __asm__ __volatile__( \
1543 "mtpc\t%0, %1" \
1544 : \
1545 : "r" (val), "i" (counter)); \
1546} while (0)
1547
1548#define read_r10k_perf_event(counter) \
1549({ \
1550 unsigned int __res; \
1551 __asm__ __volatile__( \
1552 "mfps\t%0, %1" \
1553 : "=r" (__res) \
1554 : "i" (counter)); \
1555 \
1556 __res; \
1557})
1558
1559#define write_r10k_perf_cntl(counter,val) \
1560do { \
1561 __asm__ __volatile__( \
1562 "mtps\t%0, %1" \
1563 : \
1564 : "r" (val), "i" (counter)); \
1565} while (0)
1566
1567
1568/*
1569 * Macros to access the system control coprocessor
1570 */
1571
1572#define ___read_32bit_c0_register(source, sel, vol) \
1573({ unsigned int __res; \
1574 if (sel == 0) \
1575 __asm__ vol( \
1576 "mfc0\t%0, " #source "\n\t" \
1577 : "=r" (__res)); \
1578 else \
1579 __asm__ vol( \
1580 ".set\tpush\n\t" \
1581 ".set\tmips32\n\t" \
1582 "mfc0\t%0, " #source ", " #sel "\n\t" \
1583 ".set\tpop\n\t" \
1584 : "=r" (__res)); \
1585 __res; \
1586})
1587
1588#define ___read_64bit_c0_register(source, sel, vol) \
1589({ unsigned long long __res; \
1590 if (sizeof(unsigned long) == 4) \
1591 __res = __read_64bit_c0_split(source, sel, vol); \
1592 else if (sel == 0) \
1593 __asm__ vol( \
1594 ".set\tpush\n\t" \
1595 ".set\tmips3\n\t" \
1596 "dmfc0\t%0, " #source "\n\t" \
1597 ".set\tpop" \
1598 : "=r" (__res)); \
1599 else \
1600 __asm__ vol( \
1601 ".set\tpush\n\t" \
1602 ".set\tmips64\n\t" \
1603 "dmfc0\t%0, " #source ", " #sel "\n\t" \
1604 ".set\tpop" \
1605 : "=r" (__res)); \
1606 __res; \
1607})
1608
1609#define __read_32bit_c0_register(source, sel) \
1610 ___read_32bit_c0_register(source, sel, __volatile__)
1611
1612#define __read_const_32bit_c0_register(source, sel) \
1613 ___read_32bit_c0_register(source, sel,)
1614
1615#define __read_64bit_c0_register(source, sel) \
1616 ___read_64bit_c0_register(source, sel, __volatile__)
1617
1618#define __read_const_64bit_c0_register(source, sel) \
1619 ___read_64bit_c0_register(source, sel,)
1620
1621#define __write_32bit_c0_register(register, sel, value) \
1622do { \
1623 if (sel == 0) \
1624 __asm__ __volatile__( \
1625 "mtc0\t%z0, " #register "\n\t" \
1626 : : "Jr" ((unsigned int)(value))); \
1627 else \
1628 __asm__ __volatile__( \
1629 ".set\tpush\n\t" \
1630 ".set\tmips32\n\t" \
1631 "mtc0\t%z0, " #register ", " #sel "\n\t" \
1632 ".set\tpop" \
1633 : : "Jr" ((unsigned int)(value))); \
1634} while (0)
1635
1636#define __write_64bit_c0_register(register, sel, value) \
1637do { \
1638 if (sizeof(unsigned long) == 4) \
1639 __write_64bit_c0_split(register, sel, value); \
1640 else if (sel == 0) \
1641 __asm__ __volatile__( \
1642 ".set\tpush\n\t" \
1643 ".set\tmips3\n\t" \
1644 "dmtc0\t%z0, " #register "\n\t" \
1645 ".set\tpop" \
1646 : : "Jr" (value)); \
1647 else \
1648 __asm__ __volatile__( \
1649 ".set\tpush\n\t" \
1650 ".set\tmips64\n\t" \
1651 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
1652 ".set\tpop" \
1653 : : "Jr" (value)); \
1654} while (0)
1655
1656#define __read_ulong_c0_register(reg, sel) \
1657 ((sizeof(unsigned long) == 4) ? \
1658 (unsigned long) __read_32bit_c0_register(reg, sel) : \
1659 (unsigned long) __read_64bit_c0_register(reg, sel))
1660
1661#define __read_const_ulong_c0_register(reg, sel) \
1662 ((sizeof(unsigned long) == 4) ? \
1663 (unsigned long) __read_const_32bit_c0_register(reg, sel) : \
1664 (unsigned long) __read_const_64bit_c0_register(reg, sel))
1665
1666#define __write_ulong_c0_register(reg, sel, val) \
1667do { \
1668 if (sizeof(unsigned long) == 4) \
1669 __write_32bit_c0_register(reg, sel, val); \
1670 else \
1671 __write_64bit_c0_register(reg, sel, val); \
1672} while (0)
1673
1674/*
1675 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1676 */
1677#define __read_32bit_c0_ctrl_register(source) \
1678({ unsigned int __res; \
1679 __asm__ __volatile__( \
1680 "cfc0\t%0, " #source "\n\t" \
1681 : "=r" (__res)); \
1682 __res; \
1683})
1684
1685#define __write_32bit_c0_ctrl_register(register, value) \
1686do { \
1687 __asm__ __volatile__( \
1688 "ctc0\t%z0, " #register "\n\t" \
1689 : : "Jr" ((unsigned int)(value))); \
1690} while (0)
1691
1692/*
1693 * These versions are only needed for systems with more than 38 bits of
1694 * physical address space running the 32-bit kernel. That's none atm :-)
1695 */
1696#define __read_64bit_c0_split(source, sel, vol) \
1697({ \
1698 unsigned long long __val; \
1699 unsigned long __flags; \
1700 \
1701 local_irq_save(__flags); \
1702 if (sel == 0) \
1703 __asm__ vol( \
1704 ".set\tpush\n\t" \
1705 ".set\tmips64\n\t" \
1706 "dmfc0\t%L0, " #source "\n\t" \
1707 "dsra\t%M0, %L0, 32\n\t" \
1708 "sll\t%L0, %L0, 0\n\t" \
1709 ".set\tpop" \
1710 : "=r" (__val)); \
1711 else \
1712 __asm__ vol( \
1713 ".set\tpush\n\t" \
1714 ".set\tmips64\n\t" \
1715 "dmfc0\t%L0, " #source ", " #sel "\n\t" \
1716 "dsra\t%M0, %L0, 32\n\t" \
1717 "sll\t%L0, %L0, 0\n\t" \
1718 ".set\tpop" \
1719 : "=r" (__val)); \
1720 local_irq_restore(__flags); \
1721 \
1722 __val; \
1723})
1724
1725#define __write_64bit_c0_split(source, sel, val) \
1726do { \
1727 unsigned long long __tmp = (val); \
1728 unsigned long __flags; \
1729 \
1730 local_irq_save(__flags); \
1731 if (MIPS_ISA_REV >= 2) \
1732 __asm__ __volatile__( \
1733 ".set\tpush\n\t" \
1734 ".set\t" MIPS_ISA_LEVEL "\n\t" \
1735 "dins\t%L0, %M0, 32, 32\n\t" \
1736 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1737 ".set\tpop" \
1738 : "+r" (__tmp)); \
1739 else if (sel == 0) \
1740 __asm__ __volatile__( \
1741 ".set\tpush\n\t" \
1742 ".set\tmips64\n\t" \
1743 "dsll\t%L0, %L0, 32\n\t" \
1744 "dsrl\t%L0, %L0, 32\n\t" \
1745 "dsll\t%M0, %M0, 32\n\t" \
1746 "or\t%L0, %L0, %M0\n\t" \
1747 "dmtc0\t%L0, " #source "\n\t" \
1748 ".set\tpop" \
1749 : "+r" (__tmp)); \
1750 else \
1751 __asm__ __volatile__( \
1752 ".set\tpush\n\t" \
1753 ".set\tmips64\n\t" \
1754 "dsll\t%L0, %L0, 32\n\t" \
1755 "dsrl\t%L0, %L0, 32\n\t" \
1756 "dsll\t%M0, %M0, 32\n\t" \
1757 "or\t%L0, %L0, %M0\n\t" \
1758 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1759 ".set\tpop" \
1760 : "+r" (__tmp)); \
1761 local_irq_restore(__flags); \
1762} while (0)
1763
1764#ifndef TOOLCHAIN_SUPPORTS_XPA
1765#define _ASM_SET_MFHC0 \
1766 _ASM_MACRO_2R_1S(mfhc0, rt, rs, sel, \
1767 _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel) \
1768 _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11))
1769#define _ASM_UNSET_MFHC0 ".purgem mfhc0\n\t"
1770#define _ASM_SET_MTHC0 \
1771 _ASM_MACRO_2R_1S(mthc0, rt, rd, sel, \
1772 _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel) \
1773 _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11))
1774#define _ASM_UNSET_MTHC0 ".purgem mthc0\n\t"
1775#else /* !TOOLCHAIN_SUPPORTS_XPA */
1776#define _ASM_SET_MFHC0 ".set\txpa\n\t"
1777#define _ASM_SET_MTHC0 ".set\txpa\n\t"
1778#define _ASM_UNSET_MFHC0
1779#define _ASM_UNSET_MTHC0
1780#endif
1781
1782#define __readx_32bit_c0_register(source, sel) \
1783({ \
1784 unsigned int __res; \
1785 \
1786 __asm__ __volatile__( \
1787 " .set push \n" \
1788 " .set mips32r2 \n" \
1789 _ASM_SET_MFHC0 \
1790 " mfhc0 %0, " #source ", %1 \n" \
1791 _ASM_UNSET_MFHC0 \
1792 " .set pop \n" \
1793 : "=r" (__res) \
1794 : "i" (sel)); \
1795 __res; \
1796})
1797
1798#define __writex_32bit_c0_register(register, sel, value) \
1799do { \
1800 __asm__ __volatile__( \
1801 " .set push \n" \
1802 " .set mips32r2 \n" \
1803 _ASM_SET_MTHC0 \
1804 " mthc0 %z0, " #register ", %1 \n" \
1805 _ASM_UNSET_MTHC0 \
1806 " .set pop \n" \
1807 : \
1808 : "Jr" (value), "i" (sel)); \
1809} while (0)
1810
1811#define read_c0_index() __read_32bit_c0_register($0, 0)
1812#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1813
1814#define read_c0_random() __read_32bit_c0_register($1, 0)
1815#define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1816
1817#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1818#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1819
1820#define readx_c0_entrylo0() __readx_32bit_c0_register($2, 0)
1821#define writex_c0_entrylo0(val) __writex_32bit_c0_register($2, 0, val)
1822
1823#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1824#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1825
1826#define readx_c0_entrylo1() __readx_32bit_c0_register($3, 0)
1827#define writex_c0_entrylo1(val) __writex_32bit_c0_register($3, 0, val)
1828
1829#define read_c0_conf() __read_32bit_c0_register($3, 0)
1830#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1831
1832#define read_c0_globalnumber() __read_32bit_c0_register($3, 1)
1833
1834#define read_c0_context() __read_ulong_c0_register($4, 0)
1835#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1836
1837#define read_c0_contextconfig() __read_32bit_c0_register($4, 1)
1838#define write_c0_contextconfig(val) __write_32bit_c0_register($4, 1, val)
1839
1840#define read_c0_userlocal() __read_ulong_c0_register($4, 2)
1841#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1842
1843#define read_c0_xcontextconfig() __read_ulong_c0_register($4, 3)
1844#define write_c0_xcontextconfig(val) __write_ulong_c0_register($4, 3, val)
1845
1846#define read_c0_memorymapid() __read_32bit_c0_register($4, 5)
1847#define write_c0_memorymapid(val) __write_32bit_c0_register($4, 5, val)
1848
1849#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1850#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1851
1852#define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
1853#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1854
1855#define read_c0_wired() __read_32bit_c0_register($6, 0)
1856#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1857
1858#define read_c0_info() __read_32bit_c0_register($7, 0)
1859
1860#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
1861#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1862
1863#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1864#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1865
1866#define read_c0_badinstr() __read_32bit_c0_register($8, 1)
1867#define read_c0_badinstrp() __read_32bit_c0_register($8, 2)
1868
1869#define read_c0_count() __read_32bit_c0_register($9, 0)
1870#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1871
1872#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1873#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1874
1875#define read_c0_guestctl1() __read_32bit_c0_register($10, 4)
1876#define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1877
1878#define read_c0_guestctl2() __read_32bit_c0_register($10, 5)
1879#define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1880
1881#define read_c0_guestctl3() __read_32bit_c0_register($10, 6)
1882#define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1883
1884#define read_c0_compare() __read_32bit_c0_register($11, 0)
1885#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1886
1887#define read_c0_guestctl0ext() __read_32bit_c0_register($11, 4)
1888#define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1889
1890#define read_c0_status() __read_32bit_c0_register($12, 0)
1891
1892#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1893
1894#define read_c0_guestctl0() __read_32bit_c0_register($12, 6)
1895#define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1896
1897#define read_c0_gtoffset() __read_32bit_c0_register($12, 7)
1898#define write_c0_gtoffset(val) __write_32bit_c0_register($12, 7, val)
1899
1900#define read_c0_cause() __read_32bit_c0_register($13, 0)
1901#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1902
1903#define read_c0_epc() __read_ulong_c0_register($14, 0)
1904#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1905
1906#define read_c0_prid() __read_const_32bit_c0_register($15, 0)
1907
1908#define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
1909
1910#define read_c0_config() __read_32bit_c0_register($16, 0)
1911#define read_c0_config1() __read_32bit_c0_register($16, 1)
1912#define read_c0_config2() __read_32bit_c0_register($16, 2)
1913#define read_c0_config3() __read_32bit_c0_register($16, 3)
1914#define read_c0_config4() __read_32bit_c0_register($16, 4)
1915#define read_c0_config5() __read_32bit_c0_register($16, 5)
1916#define read_c0_config6() __read_32bit_c0_register($16, 6)
1917#define read_c0_config7() __read_32bit_c0_register($16, 7)
1918#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1919#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1920#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1921#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1922#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1923#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1924#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1925#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1926
1927#define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1928#define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1929#define read_c0_maar() __read_ulong_c0_register($17, 1)
1930#define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1931#define readx_c0_maar() __readx_32bit_c0_register($17, 1)
1932#define writex_c0_maar(val) __writex_32bit_c0_register($17, 1, val)
1933#define read_c0_maari() __read_32bit_c0_register($17, 2)
1934#define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1935
1936/*
1937 * The WatchLo register. There may be up to 8 of them.
1938 */
1939#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1940#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1941#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1942#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1943#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1944#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1945#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1946#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1947#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1948#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1949#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1950#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1951#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1952#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1953#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1954#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1955
1956/*
1957 * The WatchHi register. There may be up to 8 of them.
1958 */
1959#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1960#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
1961#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
1962#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
1963#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
1964#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
1965#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
1966#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
1967
1968#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1969#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1970#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1971#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1972#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1973#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1974#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1975#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1976
1977#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1978#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1979
1980#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
1981#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1982
1983#define read_c0_framemask() __read_32bit_c0_register($21, 0)
1984#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1985
1986#define read_c0_diag() __read_32bit_c0_register($22, 0)
1987#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1988
1989/* R10K CP0 Branch Diagnostic register is 64bits wide */
1990#define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1991#define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1992
1993#define read_c0_diag1() __read_32bit_c0_register($22, 1)
1994#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1995
1996#define read_c0_diag2() __read_32bit_c0_register($22, 2)
1997#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1998
1999#define read_c0_diag3() __read_32bit_c0_register($22, 3)
2000#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
2001
2002#define read_c0_diag4() __read_32bit_c0_register($22, 4)
2003#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
2004
2005#define read_c0_diag5() __read_32bit_c0_register($22, 5)
2006#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
2007
2008#define read_c0_debug() __read_32bit_c0_register($23, 0)
2009#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
2010
2011#define read_c0_depc() __read_ulong_c0_register($24, 0)
2012#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
2013
2014/*
2015 * MIPS32 / MIPS64 performance counters
2016 */
2017#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
2018#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
2019#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
2020#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
2021#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
2022#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
2023#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
2024#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
2025#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
2026#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
2027#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
2028#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
2029#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
2030#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
2031#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
2032#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
2033#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
2034#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
2035#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
2036#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
2037#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
2038#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
2039#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
2040#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
2041
2042#define read_c0_ecc() __read_32bit_c0_register($26, 0)
2043#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
2044
2045#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
2046#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
2047
2048#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
2049
2050#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
2051#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
2052
2053#define read_c0_taglo() __read_32bit_c0_register($28, 0)
2054#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
2055
2056#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
2057#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
2058
2059#define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
2060#define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
2061
2062#define read_c0_staglo() __read_32bit_c0_register($28, 4)
2063#define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
2064
2065#define read_c0_taghi() __read_32bit_c0_register($29, 0)
2066#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
2067
2068#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
2069#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
2070
2071/* MIPSR2 */
2072#define read_c0_hwrena() __read_32bit_c0_register($7, 0)
2073#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
2074
2075#define read_c0_intctl() __read_32bit_c0_register($12, 1)
2076#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
2077
2078#define read_c0_srsctl() __read_32bit_c0_register($12, 2)
2079#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
2080
2081#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
2082#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
2083
2084#define read_c0_ebase() __read_32bit_c0_register($15, 1)
2085#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
2086
2087#define read_c0_ebase_64() __read_64bit_c0_register($15, 1)
2088#define write_c0_ebase_64(val) __write_64bit_c0_register($15, 1, val)
2089
2090#define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
2091#define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
2092
2093/* MIPSR3 */
2094#define read_c0_segctl0() __read_32bit_c0_register($5, 2)
2095#define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
2096
2097#define read_c0_segctl1() __read_32bit_c0_register($5, 3)
2098#define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
2099
2100#define read_c0_segctl2() __read_32bit_c0_register($5, 4)
2101#define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
2102
2103/* Hardware Page Table Walker */
2104#define read_c0_pwbase() __read_ulong_c0_register($5, 5)
2105#define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
2106
2107#define read_c0_pwfield() __read_ulong_c0_register($5, 6)
2108#define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
2109
2110#define read_c0_pwsize() __read_ulong_c0_register($5, 7)
2111#define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
2112
2113#define read_c0_pwctl() __read_32bit_c0_register($6, 6)
2114#define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
2115
2116#define read_c0_pgd() __read_64bit_c0_register($9, 7)
2117#define write_c0_pgd(val) __write_64bit_c0_register($9, 7, val)
2118
2119#define read_c0_kpgd() __read_64bit_c0_register($31, 7)
2120#define write_c0_kpgd(val) __write_64bit_c0_register($31, 7, val)
2121
2122/* Cavium OCTEON (cnMIPS) */
2123#define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
2124#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
2125
2126#define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
2127#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
2128
2129#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
2130#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
2131
2132#define read_c0_cvmmemctl2() __read_64bit_c0_register($16, 6)
2133#define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val)
2134
2135#define read_c0_cvmvmconfig() __read_64bit_c0_register($16, 7)
2136#define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val)
2137
2138/*
2139 * The cacheerr registers are not standardized. On OCTEON, they are
2140 * 64 bits wide.
2141 */
2142#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
2143#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
2144
2145#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
2146#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
2147
2148/* BMIPS3300 */
2149#define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
2150#define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
2151
2152#define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
2153#define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
2154
2155#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
2156#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
2157
2158/* BMIPS43xx */
2159#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
2160#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
2161
2162#define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
2163#define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
2164
2165#define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
2166#define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
2167
2168#define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
2169#define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
2170
2171#define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
2172#define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
2173
2174/* BMIPS5000 */
2175#define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
2176#define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
2177
2178#define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
2179#define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
2180
2181#define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
2182#define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
2183
2184#define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
2185#define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
2186
2187#define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
2188#define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
2189
2190#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
2191#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
2192
2193/* Ingenic page ctrl register */
2194#define write_c0_page_ctrl(val) __write_32bit_c0_register($5, 4, val)
2195
2196/*
2197 * Macros to access the guest system control coprocessor
2198 */
2199
2200#ifndef TOOLCHAIN_SUPPORTS_VIRT
2201#define _ASM_SET_MFGC0 \
2202 _ASM_MACRO_2R_1S(mfgc0, rt, rs, sel, \
2203 _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel) \
2204 _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11))
2205#define _ASM_UNSET_MFGC0 ".purgem mfgc0\n\t"
2206#define _ASM_SET_DMFGC0 \
2207 _ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel, \
2208 _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel) \
2209 _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11))
2210#define _ASM_UNSET_DMFGC0 ".purgem dmfgc0\n\t"
2211#define _ASM_SET_MTGC0 \
2212 _ASM_MACRO_2R_1S(mtgc0, rt, rd, sel, \
2213 _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel) \
2214 _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11))
2215#define _ASM_UNSET_MTGC0 ".purgem mtgc0\n\t"
2216#define _ASM_SET_DMTGC0 \
2217 _ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel, \
2218 _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel) \
2219 _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11))
2220#define _ASM_UNSET_DMTGC0 ".purgem dmtgc0\n\t"
2221
2222#define __tlbgp() \
2223 _ASM_INSN_IF_MIPS(0x42000010) \
2224 _ASM_INSN32_IF_MM(0x0000017c)
2225#define __tlbgr() \
2226 _ASM_INSN_IF_MIPS(0x42000009) \
2227 _ASM_INSN32_IF_MM(0x0000117c)
2228#define __tlbgwi() \
2229 _ASM_INSN_IF_MIPS(0x4200000a) \
2230 _ASM_INSN32_IF_MM(0x0000217c)
2231#define __tlbgwr() \
2232 _ASM_INSN_IF_MIPS(0x4200000e) \
2233 _ASM_INSN32_IF_MM(0x0000317c)
2234#define __tlbginvf() \
2235 _ASM_INSN_IF_MIPS(0x4200000c) \
2236 _ASM_INSN32_IF_MM(0x0000517c)
2237#else /* !TOOLCHAIN_SUPPORTS_VIRT */
2238#if MIPS_ISA_REV >= 5
2239#define _ASM_SET_VIRT_ISA
2240#elif defined(CONFIG_64BIT)
2241#define _ASM_SET_VIRT_ISA ".set\tmips64r5\n\t"
2242#else
2243#define _ASM_SET_VIRT_ISA ".set\tmips32r5\n\t"
2244#endif
2245#define _ASM_SET_VIRT _ASM_SET_VIRT_ISA ".set\tvirt\n\t"
2246#define _ASM_SET_MFGC0 _ASM_SET_VIRT
2247#define _ASM_SET_DMFGC0 _ASM_SET_VIRT
2248#define _ASM_SET_MTGC0 _ASM_SET_VIRT
2249#define _ASM_SET_DMTGC0 _ASM_SET_VIRT
2250#define _ASM_UNSET_MFGC0
2251#define _ASM_UNSET_DMFGC0
2252#define _ASM_UNSET_MTGC0
2253#define _ASM_UNSET_DMTGC0
2254
2255#define __tlbgp() _ASM_SET_VIRT "tlbgp\n\t"
2256#define __tlbgr() _ASM_SET_VIRT "tlbgr\n\t"
2257#define __tlbgwi() _ASM_SET_VIRT "tlbgwi\n\t"
2258#define __tlbgwr() _ASM_SET_VIRT "tlbgwr\n\t"
2259#define __tlbginvf() _ASM_SET_VIRT "tlbginvf\n\t"
2260#endif
2261
2262#define __read_32bit_gc0_register(source, sel) \
2263({ int __res; \
2264 __asm__ __volatile__( \
2265 ".set\tpush\n\t" \
2266 _ASM_SET_MFGC0 \
2267 "mfgc0\t%0, " #source ", %1\n\t" \
2268 _ASM_UNSET_MFGC0 \
2269 ".set\tpop" \
2270 : "=r" (__res) \
2271 : "i" (sel)); \
2272 __res; \
2273})
2274
2275#define __read_64bit_gc0_register(source, sel) \
2276({ unsigned long long __res; \
2277 __asm__ __volatile__( \
2278 ".set\tpush\n\t" \
2279 _ASM_SET_DMFGC0 \
2280 "dmfgc0\t%0, " #source ", %1\n\t" \
2281 _ASM_UNSET_DMFGC0 \
2282 ".set\tpop" \
2283 : "=r" (__res) \
2284 : "i" (sel)); \
2285 __res; \
2286})
2287
2288#define __write_32bit_gc0_register(register, sel, value) \
2289do { \
2290 __asm__ __volatile__( \
2291 ".set\tpush\n\t" \
2292 _ASM_SET_MTGC0 \
2293 "mtgc0\t%z0, " #register ", %1\n\t" \
2294 _ASM_UNSET_MTGC0 \
2295 ".set\tpop" \
2296 : : "Jr" ((unsigned int)(value)), \
2297 "i" (sel)); \
2298} while (0)
2299
2300#define __write_64bit_gc0_register(register, sel, value) \
2301do { \
2302 __asm__ __volatile__( \
2303 ".set\tpush\n\t" \
2304 _ASM_SET_DMTGC0 \
2305 "dmtgc0\t%z0, " #register ", %1\n\t" \
2306 _ASM_UNSET_DMTGC0 \
2307 ".set\tpop" \
2308 : : "Jr" (value), \
2309 "i" (sel)); \
2310} while (0)
2311
2312#define __read_ulong_gc0_register(reg, sel) \
2313 ((sizeof(unsigned long) == 4) ? \
2314 (unsigned long) __read_32bit_gc0_register(reg, sel) : \
2315 (unsigned long) __read_64bit_gc0_register(reg, sel))
2316
2317#define __write_ulong_gc0_register(reg, sel, val) \
2318do { \
2319 if (sizeof(unsigned long) == 4) \
2320 __write_32bit_gc0_register(reg, sel, val); \
2321 else \
2322 __write_64bit_gc0_register(reg, sel, val); \
2323} while (0)
2324
2325#define read_gc0_index() __read_32bit_gc0_register($0, 0)
2326#define write_gc0_index(val) __write_32bit_gc0_register($0, 0, val)
2327
2328#define read_gc0_entrylo0() __read_ulong_gc0_register($2, 0)
2329#define write_gc0_entrylo0(val) __write_ulong_gc0_register($2, 0, val)
2330
2331#define read_gc0_entrylo1() __read_ulong_gc0_register($3, 0)
2332#define write_gc0_entrylo1(val) __write_ulong_gc0_register($3, 0, val)
2333
2334#define read_gc0_context() __read_ulong_gc0_register($4, 0)
2335#define write_gc0_context(val) __write_ulong_gc0_register($4, 0, val)
2336
2337#define read_gc0_contextconfig() __read_32bit_gc0_register($4, 1)
2338#define write_gc0_contextconfig(val) __write_32bit_gc0_register($4, 1, val)
2339
2340#define read_gc0_userlocal() __read_ulong_gc0_register($4, 2)
2341#define write_gc0_userlocal(val) __write_ulong_gc0_register($4, 2, val)
2342
2343#define read_gc0_xcontextconfig() __read_ulong_gc0_register($4, 3)
2344#define write_gc0_xcontextconfig(val) __write_ulong_gc0_register($4, 3, val)
2345
2346#define read_gc0_pagemask() __read_32bit_gc0_register($5, 0)
2347#define write_gc0_pagemask(val) __write_32bit_gc0_register($5, 0, val)
2348
2349#define read_gc0_pagegrain() __read_32bit_gc0_register($5, 1)
2350#define write_gc0_pagegrain(val) __write_32bit_gc0_register($5, 1, val)
2351
2352#define read_gc0_segctl0() __read_ulong_gc0_register($5, 2)
2353#define write_gc0_segctl0(val) __write_ulong_gc0_register($5, 2, val)
2354
2355#define read_gc0_segctl1() __read_ulong_gc0_register($5, 3)
2356#define write_gc0_segctl1(val) __write_ulong_gc0_register($5, 3, val)
2357
2358#define read_gc0_segctl2() __read_ulong_gc0_register($5, 4)
2359#define write_gc0_segctl2(val) __write_ulong_gc0_register($5, 4, val)
2360
2361#define read_gc0_pwbase() __read_ulong_gc0_register($5, 5)
2362#define write_gc0_pwbase(val) __write_ulong_gc0_register($5, 5, val)
2363
2364#define read_gc0_pwfield() __read_ulong_gc0_register($5, 6)
2365#define write_gc0_pwfield(val) __write_ulong_gc0_register($5, 6, val)
2366
2367#define read_gc0_pwsize() __read_ulong_gc0_register($5, 7)
2368#define write_gc0_pwsize(val) __write_ulong_gc0_register($5, 7, val)
2369
2370#define read_gc0_wired() __read_32bit_gc0_register($6, 0)
2371#define write_gc0_wired(val) __write_32bit_gc0_register($6, 0, val)
2372
2373#define read_gc0_pwctl() __read_32bit_gc0_register($6, 6)
2374#define write_gc0_pwctl(val) __write_32bit_gc0_register($6, 6, val)
2375
2376#define read_gc0_hwrena() __read_32bit_gc0_register($7, 0)
2377#define write_gc0_hwrena(val) __write_32bit_gc0_register($7, 0, val)
2378
2379#define read_gc0_badvaddr() __read_ulong_gc0_register($8, 0)
2380#define write_gc0_badvaddr(val) __write_ulong_gc0_register($8, 0, val)
2381
2382#define read_gc0_badinstr() __read_32bit_gc0_register($8, 1)
2383#define write_gc0_badinstr(val) __write_32bit_gc0_register($8, 1, val)
2384
2385#define read_gc0_badinstrp() __read_32bit_gc0_register($8, 2)
2386#define write_gc0_badinstrp(val) __write_32bit_gc0_register($8, 2, val)
2387
2388#define read_gc0_count() __read_32bit_gc0_register($9, 0)
2389
2390#define read_gc0_entryhi() __read_ulong_gc0_register($10, 0)
2391#define write_gc0_entryhi(val) __write_ulong_gc0_register($10, 0, val)
2392
2393#define read_gc0_compare() __read_32bit_gc0_register($11, 0)
2394#define write_gc0_compare(val) __write_32bit_gc0_register($11, 0, val)
2395
2396#define read_gc0_status() __read_32bit_gc0_register($12, 0)
2397#define write_gc0_status(val) __write_32bit_gc0_register($12, 0, val)
2398
2399#define read_gc0_intctl() __read_32bit_gc0_register($12, 1)
2400#define write_gc0_intctl(val) __write_32bit_gc0_register($12, 1, val)
2401
2402#define read_gc0_cause() __read_32bit_gc0_register($13, 0)
2403#define write_gc0_cause(val) __write_32bit_gc0_register($13, 0, val)
2404
2405#define read_gc0_epc() __read_ulong_gc0_register($14, 0)
2406#define write_gc0_epc(val) __write_ulong_gc0_register($14, 0, val)
2407
2408#define read_gc0_prid() __read_32bit_gc0_register($15, 0)
2409
2410#define read_gc0_ebase() __read_32bit_gc0_register($15, 1)
2411#define write_gc0_ebase(val) __write_32bit_gc0_register($15, 1, val)
2412
2413#define read_gc0_ebase_64() __read_64bit_gc0_register($15, 1)
2414#define write_gc0_ebase_64(val) __write_64bit_gc0_register($15, 1, val)
2415
2416#define read_gc0_config() __read_32bit_gc0_register($16, 0)
2417#define read_gc0_config1() __read_32bit_gc0_register($16, 1)
2418#define read_gc0_config2() __read_32bit_gc0_register($16, 2)
2419#define read_gc0_config3() __read_32bit_gc0_register($16, 3)
2420#define read_gc0_config4() __read_32bit_gc0_register($16, 4)
2421#define read_gc0_config5() __read_32bit_gc0_register($16, 5)
2422#define read_gc0_config6() __read_32bit_gc0_register($16, 6)
2423#define read_gc0_config7() __read_32bit_gc0_register($16, 7)
2424#define write_gc0_config(val) __write_32bit_gc0_register($16, 0, val)
2425#define write_gc0_config1(val) __write_32bit_gc0_register($16, 1, val)
2426#define write_gc0_config2(val) __write_32bit_gc0_register($16, 2, val)
2427#define write_gc0_config3(val) __write_32bit_gc0_register($16, 3, val)
2428#define write_gc0_config4(val) __write_32bit_gc0_register($16, 4, val)
2429#define write_gc0_config5(val) __write_32bit_gc0_register($16, 5, val)
2430#define write_gc0_config6(val) __write_32bit_gc0_register($16, 6, val)
2431#define write_gc0_config7(val) __write_32bit_gc0_register($16, 7, val)
2432
2433#define read_gc0_lladdr() __read_ulong_gc0_register($17, 0)
2434#define write_gc0_lladdr(val) __write_ulong_gc0_register($17, 0, val)
2435
2436#define read_gc0_watchlo0() __read_ulong_gc0_register($18, 0)
2437#define read_gc0_watchlo1() __read_ulong_gc0_register($18, 1)
2438#define read_gc0_watchlo2() __read_ulong_gc0_register($18, 2)
2439#define read_gc0_watchlo3() __read_ulong_gc0_register($18, 3)
2440#define read_gc0_watchlo4() __read_ulong_gc0_register($18, 4)
2441#define read_gc0_watchlo5() __read_ulong_gc0_register($18, 5)
2442#define read_gc0_watchlo6() __read_ulong_gc0_register($18, 6)
2443#define read_gc0_watchlo7() __read_ulong_gc0_register($18, 7)
2444#define write_gc0_watchlo0(val) __write_ulong_gc0_register($18, 0, val)
2445#define write_gc0_watchlo1(val) __write_ulong_gc0_register($18, 1, val)
2446#define write_gc0_watchlo2(val) __write_ulong_gc0_register($18, 2, val)
2447#define write_gc0_watchlo3(val) __write_ulong_gc0_register($18, 3, val)
2448#define write_gc0_watchlo4(val) __write_ulong_gc0_register($18, 4, val)
2449#define write_gc0_watchlo5(val) __write_ulong_gc0_register($18, 5, val)
2450#define write_gc0_watchlo6(val) __write_ulong_gc0_register($18, 6, val)
2451#define write_gc0_watchlo7(val) __write_ulong_gc0_register($18, 7, val)
2452
2453#define read_gc0_watchhi0() __read_32bit_gc0_register($19, 0)
2454#define read_gc0_watchhi1() __read_32bit_gc0_register($19, 1)
2455#define read_gc0_watchhi2() __read_32bit_gc0_register($19, 2)
2456#define read_gc0_watchhi3() __read_32bit_gc0_register($19, 3)
2457#define read_gc0_watchhi4() __read_32bit_gc0_register($19, 4)
2458#define read_gc0_watchhi5() __read_32bit_gc0_register($19, 5)
2459#define read_gc0_watchhi6() __read_32bit_gc0_register($19, 6)
2460#define read_gc0_watchhi7() __read_32bit_gc0_register($19, 7)
2461#define write_gc0_watchhi0(val) __write_32bit_gc0_register($19, 0, val)
2462#define write_gc0_watchhi1(val) __write_32bit_gc0_register($19, 1, val)
2463#define write_gc0_watchhi2(val) __write_32bit_gc0_register($19, 2, val)
2464#define write_gc0_watchhi3(val) __write_32bit_gc0_register($19, 3, val)
2465#define write_gc0_watchhi4(val) __write_32bit_gc0_register($19, 4, val)
2466#define write_gc0_watchhi5(val) __write_32bit_gc0_register($19, 5, val)
2467#define write_gc0_watchhi6(val) __write_32bit_gc0_register($19, 6, val)
2468#define write_gc0_watchhi7(val) __write_32bit_gc0_register($19, 7, val)
2469
2470#define read_gc0_xcontext() __read_ulong_gc0_register($20, 0)
2471#define write_gc0_xcontext(val) __write_ulong_gc0_register($20, 0, val)
2472
2473#define read_gc0_perfctrl0() __read_32bit_gc0_register($25, 0)
2474#define write_gc0_perfctrl0(val) __write_32bit_gc0_register($25, 0, val)
2475#define read_gc0_perfcntr0() __read_32bit_gc0_register($25, 1)
2476#define write_gc0_perfcntr0(val) __write_32bit_gc0_register($25, 1, val)
2477#define read_gc0_perfcntr0_64() __read_64bit_gc0_register($25, 1)
2478#define write_gc0_perfcntr0_64(val) __write_64bit_gc0_register($25, 1, val)
2479#define read_gc0_perfctrl1() __read_32bit_gc0_register($25, 2)
2480#define write_gc0_perfctrl1(val) __write_32bit_gc0_register($25, 2, val)
2481#define read_gc0_perfcntr1() __read_32bit_gc0_register($25, 3)
2482#define write_gc0_perfcntr1(val) __write_32bit_gc0_register($25, 3, val)
2483#define read_gc0_perfcntr1_64() __read_64bit_gc0_register($25, 3)
2484#define write_gc0_perfcntr1_64(val) __write_64bit_gc0_register($25, 3, val)
2485#define read_gc0_perfctrl2() __read_32bit_gc0_register($25, 4)
2486#define write_gc0_perfctrl2(val) __write_32bit_gc0_register($25, 4, val)
2487#define read_gc0_perfcntr2() __read_32bit_gc0_register($25, 5)
2488#define write_gc0_perfcntr2(val) __write_32bit_gc0_register($25, 5, val)
2489#define read_gc0_perfcntr2_64() __read_64bit_gc0_register($25, 5)
2490#define write_gc0_perfcntr2_64(val) __write_64bit_gc0_register($25, 5, val)
2491#define read_gc0_perfctrl3() __read_32bit_gc0_register($25, 6)
2492#define write_gc0_perfctrl3(val) __write_32bit_gc0_register($25, 6, val)
2493#define read_gc0_perfcntr3() __read_32bit_gc0_register($25, 7)
2494#define write_gc0_perfcntr3(val) __write_32bit_gc0_register($25, 7, val)
2495#define read_gc0_perfcntr3_64() __read_64bit_gc0_register($25, 7)
2496#define write_gc0_perfcntr3_64(val) __write_64bit_gc0_register($25, 7, val)
2497
2498#define read_gc0_errorepc() __read_ulong_gc0_register($30, 0)
2499#define write_gc0_errorepc(val) __write_ulong_gc0_register($30, 0, val)
2500
2501#define read_gc0_kscratch1() __read_ulong_gc0_register($31, 2)
2502#define read_gc0_kscratch2() __read_ulong_gc0_register($31, 3)
2503#define read_gc0_kscratch3() __read_ulong_gc0_register($31, 4)
2504#define read_gc0_kscratch4() __read_ulong_gc0_register($31, 5)
2505#define read_gc0_kscratch5() __read_ulong_gc0_register($31, 6)
2506#define read_gc0_kscratch6() __read_ulong_gc0_register($31, 7)
2507#define write_gc0_kscratch1(val) __write_ulong_gc0_register($31, 2, val)
2508#define write_gc0_kscratch2(val) __write_ulong_gc0_register($31, 3, val)
2509#define write_gc0_kscratch3(val) __write_ulong_gc0_register($31, 4, val)
2510#define write_gc0_kscratch4(val) __write_ulong_gc0_register($31, 5, val)
2511#define write_gc0_kscratch5(val) __write_ulong_gc0_register($31, 6, val)
2512#define write_gc0_kscratch6(val) __write_ulong_gc0_register($31, 7, val)
2513
2514/* Cavium OCTEON (cnMIPS) */
2515#define read_gc0_cvmcount() __read_ulong_gc0_register($9, 6)
2516#define write_gc0_cvmcount(val) __write_ulong_gc0_register($9, 6, val)
2517
2518#define read_gc0_cvmctl() __read_64bit_gc0_register($9, 7)
2519#define write_gc0_cvmctl(val) __write_64bit_gc0_register($9, 7, val)
2520
2521#define read_gc0_cvmmemctl() __read_64bit_gc0_register($11, 7)
2522#define write_gc0_cvmmemctl(val) __write_64bit_gc0_register($11, 7, val)
2523
2524#define read_gc0_cvmmemctl2() __read_64bit_gc0_register($16, 6)
2525#define write_gc0_cvmmemctl2(val) __write_64bit_gc0_register($16, 6, val)
2526
2527/*
2528 * Macros to access the floating point coprocessor control registers
2529 */
2530#define read_32bit_cp1_register(source) \
2531({ \
2532 unsigned int __res; \
2533 \
2534 __asm__ __volatile__( \
2535 " .set push \n" \
2536 " .set reorder \n" \
2537 " # gas fails to assemble cfc1 for some archs, \n" \
2538 " # like Octeon. \n" \
2539 " .set mips1 \n" \
2540 " .set hardfloat \n" \
2541 " cfc1 %0,"STR(source)" \n" \
2542 " .set pop \n" \
2543 : "=r" (__res)); \
2544 __res; \
2545})
2546
2547#define write_32bit_cp1_register(dest, val) \
2548do { \
2549 __asm__ __volatile__( \
2550 " .set push \n" \
2551 " .set reorder \n" \
2552 " .set hardfloat \n" \
2553 " ctc1 %0,"STR(dest)" \n" \
2554 " .set pop \n" \
2555 : : "r" (val)); \
2556} while (0)
2557
2558#ifdef TOOLCHAIN_SUPPORTS_DSP
2559#define rddsp(mask) \
2560({ \
2561 unsigned int __dspctl; \
2562 \
2563 __asm__ __volatile__( \
2564 " .set push \n" \
2565 " .set " MIPS_ISA_LEVEL " \n" \
2566 " .set dsp \n" \
2567 " rddsp %0, %x1 \n" \
2568 " .set pop \n" \
2569 : "=r" (__dspctl) \
2570 : "i" (mask)); \
2571 __dspctl; \
2572})
2573
2574#define wrdsp(val, mask) \
2575do { \
2576 __asm__ __volatile__( \
2577 " .set push \n" \
2578 " .set " MIPS_ISA_LEVEL " \n" \
2579 " .set dsp \n" \
2580 " wrdsp %0, %x1 \n" \
2581 " .set pop \n" \
2582 : \
2583 : "r" (val), "i" (mask)); \
2584} while (0)
2585
2586#define mflo0() \
2587({ \
2588 long mflo0; \
2589 __asm__( \
2590 " .set push \n" \
2591 " .set " MIPS_ISA_LEVEL " \n" \
2592 " .set dsp \n" \
2593 " mflo %0, $ac0 \n" \
2594 " .set pop \n" \
2595 : "=r" (mflo0)); \
2596 mflo0; \
2597})
2598
2599#define mflo1() \
2600({ \
2601 long mflo1; \
2602 __asm__( \
2603 " .set push \n" \
2604 " .set " MIPS_ISA_LEVEL " \n" \
2605 " .set dsp \n" \
2606 " mflo %0, $ac1 \n" \
2607 " .set pop \n" \
2608 : "=r" (mflo1)); \
2609 mflo1; \
2610})
2611
2612#define mflo2() \
2613({ \
2614 long mflo2; \
2615 __asm__( \
2616 " .set push \n" \
2617 " .set " MIPS_ISA_LEVEL " \n" \
2618 " .set dsp \n" \
2619 " mflo %0, $ac2 \n" \
2620 " .set pop \n" \
2621 : "=r" (mflo2)); \
2622 mflo2; \
2623})
2624
2625#define mflo3() \
2626({ \
2627 long mflo3; \
2628 __asm__( \
2629 " .set push \n" \
2630 " .set " MIPS_ISA_LEVEL " \n" \
2631 " .set dsp \n" \
2632 " mflo %0, $ac3 \n" \
2633 " .set pop \n" \
2634 : "=r" (mflo3)); \
2635 mflo3; \
2636})
2637
2638#define mfhi0() \
2639({ \
2640 long mfhi0; \
2641 __asm__( \
2642 " .set push \n" \
2643 " .set " MIPS_ISA_LEVEL " \n" \
2644 " .set dsp \n" \
2645 " mfhi %0, $ac0 \n" \
2646 " .set pop \n" \
2647 : "=r" (mfhi0)); \
2648 mfhi0; \
2649})
2650
2651#define mfhi1() \
2652({ \
2653 long mfhi1; \
2654 __asm__( \
2655 " .set push \n" \
2656 " .set " MIPS_ISA_LEVEL " \n" \
2657 " .set dsp \n" \
2658 " mfhi %0, $ac1 \n" \
2659 " .set pop \n" \
2660 : "=r" (mfhi1)); \
2661 mfhi1; \
2662})
2663
2664#define mfhi2() \
2665({ \
2666 long mfhi2; \
2667 __asm__( \
2668 " .set push \n" \
2669 " .set " MIPS_ISA_LEVEL " \n" \
2670 " .set dsp \n" \
2671 " mfhi %0, $ac2 \n" \
2672 " .set pop \n" \
2673 : "=r" (mfhi2)); \
2674 mfhi2; \
2675})
2676
2677#define mfhi3() \
2678({ \
2679 long mfhi3; \
2680 __asm__( \
2681 " .set push \n" \
2682 " .set " MIPS_ISA_LEVEL " \n" \
2683 " .set dsp \n" \
2684 " mfhi %0, $ac3 \n" \
2685 " .set pop \n" \
2686 : "=r" (mfhi3)); \
2687 mfhi3; \
2688})
2689
2690
2691#define mtlo0(x) \
2692({ \
2693 __asm__( \
2694 " .set push \n" \
2695 " .set " MIPS_ISA_LEVEL " \n" \
2696 " .set dsp \n" \
2697 " mtlo %0, $ac0 \n" \
2698 " .set pop \n" \
2699 : \
2700 : "r" (x)); \
2701})
2702
2703#define mtlo1(x) \
2704({ \
2705 __asm__( \
2706 " .set push \n" \
2707 " .set " MIPS_ISA_LEVEL " \n" \
2708 " .set dsp \n" \
2709 " mtlo %0, $ac1 \n" \
2710 " .set pop \n" \
2711 : \
2712 : "r" (x)); \
2713})
2714
2715#define mtlo2(x) \
2716({ \
2717 __asm__( \
2718 " .set push \n" \
2719 " .set " MIPS_ISA_LEVEL " \n" \
2720 " .set dsp \n" \
2721 " mtlo %0, $ac2 \n" \
2722 " .set pop \n" \
2723 : \
2724 : "r" (x)); \
2725})
2726
2727#define mtlo3(x) \
2728({ \
2729 __asm__( \
2730 " .set push \n" \
2731 " .set " MIPS_ISA_LEVEL " \n" \
2732 " .set dsp \n" \
2733 " mtlo %0, $ac3 \n" \
2734 " .set pop \n" \
2735 : \
2736 : "r" (x)); \
2737})
2738
2739#define mthi0(x) \
2740({ \
2741 __asm__( \
2742 " .set push \n" \
2743 " .set " MIPS_ISA_LEVEL " \n" \
2744 " .set dsp \n" \
2745 " mthi %0, $ac0 \n" \
2746 " .set pop \n" \
2747 : \
2748 : "r" (x)); \
2749})
2750
2751#define mthi1(x) \
2752({ \
2753 __asm__( \
2754 " .set push \n" \
2755 " .set " MIPS_ISA_LEVEL " \n" \
2756 " .set dsp \n" \
2757 " mthi %0, $ac1 \n" \
2758 " .set pop \n" \
2759 : \
2760 : "r" (x)); \
2761})
2762
2763#define mthi2(x) \
2764({ \
2765 __asm__( \
2766 " .set push \n" \
2767 " .set " MIPS_ISA_LEVEL " \n" \
2768 " .set dsp \n" \
2769 " mthi %0, $ac2 \n" \
2770 " .set pop \n" \
2771 : \
2772 : "r" (x)); \
2773})
2774
2775#define mthi3(x) \
2776({ \
2777 __asm__( \
2778 " .set push \n" \
2779 " .set " MIPS_ISA_LEVEL " \n" \
2780 " .set dsp \n" \
2781 " mthi %0, $ac3 \n" \
2782 " .set pop \n" \
2783 : \
2784 : "r" (x)); \
2785})
2786
2787#else
2788
2789#define rddsp(mask) \
2790({ \
2791 unsigned int __res; \
2792 \
2793 __asm__ __volatile__( \
2794 " .set push \n" \
2795 " .set noat \n" \
2796 " # rddsp $1, %x1 \n" \
2797 _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16)) \
2798 _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14)) \
2799 " move %0, $1 \n" \
2800 " .set pop \n" \
2801 : "=r" (__res) \
2802 : "i" (mask)); \
2803 __res; \
2804})
2805
2806#define wrdsp(val, mask) \
2807do { \
2808 __asm__ __volatile__( \
2809 " .set push \n" \
2810 " .set noat \n" \
2811 " move $1, %0 \n" \
2812 " # wrdsp $1, %x1 \n" \
2813 _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11)) \
2814 _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14)) \
2815 " .set pop \n" \
2816 : \
2817 : "r" (val), "i" (mask)); \
2818} while (0)
2819
2820#define _dsp_mfxxx(ins) \
2821({ \
2822 unsigned long __treg; \
2823 \
2824 __asm__ __volatile__( \
2825 " .set push \n" \
2826 " .set noat \n" \
2827 _ASM_INSN_IF_MIPS(0x00000810 | %X1) \
2828 _ASM_INSN32_IF_MM(0x0001007c | %x1) \
2829 " move %0, $1 \n" \
2830 " .set pop \n" \
2831 : "=r" (__treg) \
2832 : "i" (ins)); \
2833 __treg; \
2834})
2835
2836#define _dsp_mtxxx(val, ins) \
2837do { \
2838 __asm__ __volatile__( \
2839 " .set push \n" \
2840 " .set noat \n" \
2841 " move $1, %0 \n" \
2842 _ASM_INSN_IF_MIPS(0x00200011 | %X1) \
2843 _ASM_INSN32_IF_MM(0x0001207c | %x1) \
2844 " .set pop \n" \
2845 : \
2846 : "r" (val), "i" (ins)); \
2847} while (0)
2848
2849#ifdef CONFIG_CPU_MICROMIPS
2850
2851#define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2852#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2853
2854#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2855#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2856
2857#else /* !CONFIG_CPU_MICROMIPS */
2858
2859#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2860#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2861
2862#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2863#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2864
2865#endif /* CONFIG_CPU_MICROMIPS */
2866
2867#define mflo0() _dsp_mflo(0)
2868#define mflo1() _dsp_mflo(1)
2869#define mflo2() _dsp_mflo(2)
2870#define mflo3() _dsp_mflo(3)
2871
2872#define mfhi0() _dsp_mfhi(0)
2873#define mfhi1() _dsp_mfhi(1)
2874#define mfhi2() _dsp_mfhi(2)
2875#define mfhi3() _dsp_mfhi(3)
2876
2877#define mtlo0(x) _dsp_mtlo(x, 0)
2878#define mtlo1(x) _dsp_mtlo(x, 1)
2879#define mtlo2(x) _dsp_mtlo(x, 2)
2880#define mtlo3(x) _dsp_mtlo(x, 3)
2881
2882#define mthi0(x) _dsp_mthi(x, 0)
2883#define mthi1(x) _dsp_mthi(x, 1)
2884#define mthi2(x) _dsp_mthi(x, 2)
2885#define mthi3(x) _dsp_mthi(x, 3)
2886
2887#endif
2888
2889/*
2890 * TLB operations.
2891 *
2892 * It is responsibility of the caller to take care of any TLB hazards.
2893 */
2894static inline void tlb_probe(void)
2895{
2896 __asm__ __volatile__(
2897 ".set noreorder\n\t"
2898 "tlbp\n\t"
2899 ".set reorder");
2900}
2901
2902static inline void tlb_read(void)
2903{
2904#ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
2905 int res = 0;
2906
2907 __asm__ __volatile__(
2908 " .set push \n"
2909 " .set noreorder \n"
2910 " .set noat \n"
2911 " .set mips32r2 \n"
2912 " .word 0x41610001 # dvpe $1 \n"
2913 " move %0, $1 \n"
2914 " ehb \n"
2915 " .set pop \n"
2916 : "=r" (res));
2917
2918 instruction_hazard();
2919#endif
2920
2921 __asm__ __volatile__(
2922 ".set noreorder\n\t"
2923 "tlbr\n\t"
2924 ".set reorder");
2925
2926#ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
2927 if ((res & _ULCAST_(1)))
2928 __asm__ __volatile__(
2929 " .set push \n"
2930 " .set noreorder \n"
2931 " .set noat \n"
2932 " .set mips32r2 \n"
2933 " .word 0x41600021 # evpe \n"
2934 " ehb \n"
2935 " .set pop \n");
2936#endif
2937}
2938
2939static inline void tlb_write_indexed(void)
2940{
2941 __asm__ __volatile__(
2942 ".set noreorder\n\t"
2943 "tlbwi\n\t"
2944 ".set reorder");
2945}
2946
2947static inline void tlb_write_random(void)
2948{
2949 __asm__ __volatile__(
2950 ".set noreorder\n\t"
2951 "tlbwr\n\t"
2952 ".set reorder");
2953}
2954
2955/*
2956 * Guest TLB operations.
2957 *
2958 * It is responsibility of the caller to take care of any TLB hazards.
2959 */
2960static inline void guest_tlb_probe(void)
2961{
2962 __asm__ __volatile__(
2963 ".set push\n\t"
2964 ".set noreorder\n\t"
2965 __tlbgp()
2966 ".set pop");
2967}
2968
2969static inline void guest_tlb_read(void)
2970{
2971 __asm__ __volatile__(
2972 ".set push\n\t"
2973 ".set noreorder\n\t"
2974 __tlbgr()
2975 ".set pop");
2976}
2977
2978static inline void guest_tlb_write_indexed(void)
2979{
2980 __asm__ __volatile__(
2981 ".set push\n\t"
2982 ".set noreorder\n\t"
2983 __tlbgwi()
2984 ".set pop");
2985}
2986
2987static inline void guest_tlb_write_random(void)
2988{
2989 __asm__ __volatile__(
2990 ".set push\n\t"
2991 ".set noreorder\n\t"
2992 __tlbgwr()
2993 ".set pop");
2994}
2995
2996/*
2997 * Guest TLB Invalidate Flush
2998 */
2999static inline void guest_tlbinvf(void)
3000{
3001 __asm__ __volatile__(
3002 ".set push\n\t"
3003 ".set noreorder\n\t"
3004 __tlbginvf()
3005 ".set pop");
3006}
3007
3008/*
3009 * Manipulate bits in a register.
3010 */
3011#define __BUILD_SET_COMMON(name) \
3012static inline unsigned int \
3013set_##name(unsigned int set) \
3014{ \
3015 unsigned int res, new; \
3016 \
3017 res = read_##name(); \
3018 new = res | set; \
3019 write_##name(new); \
3020 \
3021 return res; \
3022} \
3023 \
3024static inline unsigned int \
3025clear_##name(unsigned int clear) \
3026{ \
3027 unsigned int res, new; \
3028 \
3029 res = read_##name(); \
3030 new = res & ~clear; \
3031 write_##name(new); \
3032 \
3033 return res; \
3034} \
3035 \
3036static inline unsigned int \
3037change_##name(unsigned int change, unsigned int val) \
3038{ \
3039 unsigned int res, new; \
3040 \
3041 res = read_##name(); \
3042 new = res & ~change; \
3043 new |= (val & change); \
3044 write_##name(new); \
3045 \
3046 return res; \
3047}
3048
3049/*
3050 * Manipulate bits in a c0 register.
3051 */
3052#define __BUILD_SET_C0(name) __BUILD_SET_COMMON(c0_##name)
3053
3054__BUILD_SET_C0(status)
3055__BUILD_SET_C0(cause)
3056__BUILD_SET_C0(config)
3057__BUILD_SET_C0(config5)
3058__BUILD_SET_C0(config6)
3059__BUILD_SET_C0(config7)
3060__BUILD_SET_C0(diag)
3061__BUILD_SET_C0(intcontrol)
3062__BUILD_SET_C0(intctl)
3063__BUILD_SET_C0(srsmap)
3064__BUILD_SET_C0(pagegrain)
3065__BUILD_SET_C0(guestctl0)
3066__BUILD_SET_C0(guestctl0ext)
3067__BUILD_SET_C0(guestctl1)
3068__BUILD_SET_C0(guestctl2)
3069__BUILD_SET_C0(guestctl3)
3070__BUILD_SET_C0(brcm_config_0)
3071__BUILD_SET_C0(brcm_bus_pll)
3072__BUILD_SET_C0(brcm_reset)
3073__BUILD_SET_C0(brcm_cmt_intr)
3074__BUILD_SET_C0(brcm_cmt_ctrl)
3075__BUILD_SET_C0(brcm_config)
3076__BUILD_SET_C0(brcm_mode)
3077
3078/*
3079 * Manipulate bits in a guest c0 register.
3080 */
3081#define __BUILD_SET_GC0(name) __BUILD_SET_COMMON(gc0_##name)
3082
3083__BUILD_SET_GC0(wired)
3084__BUILD_SET_GC0(status)
3085__BUILD_SET_GC0(cause)
3086__BUILD_SET_GC0(ebase)
3087__BUILD_SET_GC0(config1)
3088
3089/*
3090 * Return low 10 bits of ebase.
3091 * Note that under KVM (MIPSVZ) this returns vcpu id.
3092 */
3093static inline unsigned int get_ebase_cpunum(void)
3094{
3095 return read_c0_ebase() & MIPS_EBASE_CPUNUM;
3096}
3097
3098#endif /* !__ASSEMBLY__ */
3099
3100#endif /* _ASM_MIPSREGS_H */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */
13#ifndef _ASM_MIPSREGS_H
14#define _ASM_MIPSREGS_H
15
16#include <linux/linkage.h>
17#include <linux/types.h>
18#include <asm/hazards.h>
19#include <asm/war.h>
20
21/*
22 * The following macros are especially useful for __asm__
23 * inline assembler.
24 */
25#ifndef __STR
26#define __STR(x) #x
27#endif
28#ifndef STR
29#define STR(x) __STR(x)
30#endif
31
32/*
33 * Configure language
34 */
35#ifdef __ASSEMBLY__
36#define _ULCAST_
37#else
38#define _ULCAST_ (unsigned long)
39#endif
40
41/*
42 * Coprocessor 0 register names
43 */
44#define CP0_INDEX $0
45#define CP0_RANDOM $1
46#define CP0_ENTRYLO0 $2
47#define CP0_ENTRYLO1 $3
48#define CP0_CONF $3
49#define CP0_CONTEXT $4
50#define CP0_PAGEMASK $5
51#define CP0_SEGCTL0 $5, 2
52#define CP0_SEGCTL1 $5, 3
53#define CP0_SEGCTL2 $5, 4
54#define CP0_WIRED $6
55#define CP0_INFO $7
56#define CP0_HWRENA $7
57#define CP0_BADVADDR $8
58#define CP0_BADINSTR $8, 1
59#define CP0_COUNT $9
60#define CP0_ENTRYHI $10
61#define CP0_GUESTCTL1 $10, 4
62#define CP0_GUESTCTL2 $10, 5
63#define CP0_GUESTCTL3 $10, 6
64#define CP0_COMPARE $11
65#define CP0_GUESTCTL0EXT $11, 4
66#define CP0_STATUS $12
67#define CP0_GUESTCTL0 $12, 6
68#define CP0_GTOFFSET $12, 7
69#define CP0_CAUSE $13
70#define CP0_EPC $14
71#define CP0_PRID $15
72#define CP0_EBASE $15, 1
73#define CP0_CMGCRBASE $15, 3
74#define CP0_CONFIG $16
75#define CP0_CONFIG3 $16, 3
76#define CP0_CONFIG5 $16, 5
77#define CP0_LLADDR $17
78#define CP0_WATCHLO $18
79#define CP0_WATCHHI $19
80#define CP0_XCONTEXT $20
81#define CP0_FRAMEMASK $21
82#define CP0_DIAGNOSTIC $22
83#define CP0_DEBUG $23
84#define CP0_DEPC $24
85#define CP0_PERFORMANCE $25
86#define CP0_ECC $26
87#define CP0_CACHEERR $27
88#define CP0_TAGLO $28
89#define CP0_TAGHI $29
90#define CP0_ERROREPC $30
91#define CP0_DESAVE $31
92
93/*
94 * R4640/R4650 cp0 register names. These registers are listed
95 * here only for completeness; without MMU these CPUs are not useable
96 * by Linux. A future ELKS port might take make Linux run on them
97 * though ...
98 */
99#define CP0_IBASE $0
100#define CP0_IBOUND $1
101#define CP0_DBASE $2
102#define CP0_DBOUND $3
103#define CP0_CALG $17
104#define CP0_IWATCH $18
105#define CP0_DWATCH $19
106
107/*
108 * Coprocessor 0 Set 1 register names
109 */
110#define CP0_S1_DERRADDR0 $26
111#define CP0_S1_DERRADDR1 $27
112#define CP0_S1_INTCONTROL $20
113
114/*
115 * Coprocessor 0 Set 2 register names
116 */
117#define CP0_S2_SRSCTL $12 /* MIPSR2 */
118
119/*
120 * Coprocessor 0 Set 3 register names
121 */
122#define CP0_S3_SRSMAP $12 /* MIPSR2 */
123
124/*
125 * TX39 Series
126 */
127#define CP0_TX39_CACHE $7
128
129
130/* Generic EntryLo bit definitions */
131#define ENTRYLO_G (_ULCAST_(1) << 0)
132#define ENTRYLO_V (_ULCAST_(1) << 1)
133#define ENTRYLO_D (_ULCAST_(1) << 2)
134#define ENTRYLO_C_SHIFT 3
135#define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
136
137/* R3000 EntryLo bit definitions */
138#define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
139#define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
140#define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
141#define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
142
143/* MIPS32/64 EntryLo bit definitions */
144#define MIPS_ENTRYLO_PFN_SHIFT 6
145#define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
146#define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
147
148/*
149 * Values for PageMask register
150 */
151#ifdef CONFIG_CPU_VR41XX
152
153/* Why doesn't stupidity hurt ... */
154
155#define PM_1K 0x00000000
156#define PM_4K 0x00001800
157#define PM_16K 0x00007800
158#define PM_64K 0x0001f800
159#define PM_256K 0x0007f800
160
161#else
162
163#define PM_4K 0x00000000
164#define PM_8K 0x00002000
165#define PM_16K 0x00006000
166#define PM_32K 0x0000e000
167#define PM_64K 0x0001e000
168#define PM_128K 0x0003e000
169#define PM_256K 0x0007e000
170#define PM_512K 0x000fe000
171#define PM_1M 0x001fe000
172#define PM_2M 0x003fe000
173#define PM_4M 0x007fe000
174#define PM_8M 0x00ffe000
175#define PM_16M 0x01ffe000
176#define PM_32M 0x03ffe000
177#define PM_64M 0x07ffe000
178#define PM_256M 0x1fffe000
179#define PM_1G 0x7fffe000
180
181#endif
182
183/*
184 * Default page size for a given kernel configuration
185 */
186#ifdef CONFIG_PAGE_SIZE_4KB
187#define PM_DEFAULT_MASK PM_4K
188#elif defined(CONFIG_PAGE_SIZE_8KB)
189#define PM_DEFAULT_MASK PM_8K
190#elif defined(CONFIG_PAGE_SIZE_16KB)
191#define PM_DEFAULT_MASK PM_16K
192#elif defined(CONFIG_PAGE_SIZE_32KB)
193#define PM_DEFAULT_MASK PM_32K
194#elif defined(CONFIG_PAGE_SIZE_64KB)
195#define PM_DEFAULT_MASK PM_64K
196#else
197#error Bad page size configuration!
198#endif
199
200/*
201 * Default huge tlb size for a given kernel configuration
202 */
203#ifdef CONFIG_PAGE_SIZE_4KB
204#define PM_HUGE_MASK PM_1M
205#elif defined(CONFIG_PAGE_SIZE_8KB)
206#define PM_HUGE_MASK PM_4M
207#elif defined(CONFIG_PAGE_SIZE_16KB)
208#define PM_HUGE_MASK PM_16M
209#elif defined(CONFIG_PAGE_SIZE_32KB)
210#define PM_HUGE_MASK PM_64M
211#elif defined(CONFIG_PAGE_SIZE_64KB)
212#define PM_HUGE_MASK PM_256M
213#elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
214#error Bad page size configuration for hugetlbfs!
215#endif
216
217/*
218 * Wired register bits
219 */
220#define MIPSR6_WIRED_LIMIT (_ULCAST_(0xffff) << 16)
221#define MIPSR6_WIRED_WIRED (_ULCAST_(0xffff) << 0)
222
223/*
224 * Values used for computation of new tlb entries
225 */
226#define PL_4K 12
227#define PL_16K 14
228#define PL_64K 16
229#define PL_256K 18
230#define PL_1M 20
231#define PL_4M 22
232#define PL_16M 24
233#define PL_64M 26
234#define PL_256M 28
235
236/*
237 * PageGrain bits
238 */
239#define PG_RIE (_ULCAST_(1) << 31)
240#define PG_XIE (_ULCAST_(1) << 30)
241#define PG_ELPA (_ULCAST_(1) << 29)
242#define PG_ESP (_ULCAST_(1) << 28)
243#define PG_IEC (_ULCAST_(1) << 27)
244
245/* MIPS32/64 EntryHI bit definitions */
246#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
247#define MIPS_ENTRYHI_ASIDX (_ULCAST_(0x3) << 8)
248#define MIPS_ENTRYHI_ASID (_ULCAST_(0xff) << 0)
249
250/*
251 * R4x00 interrupt enable / cause bits
252 */
253#define IE_SW0 (_ULCAST_(1) << 8)
254#define IE_SW1 (_ULCAST_(1) << 9)
255#define IE_IRQ0 (_ULCAST_(1) << 10)
256#define IE_IRQ1 (_ULCAST_(1) << 11)
257#define IE_IRQ2 (_ULCAST_(1) << 12)
258#define IE_IRQ3 (_ULCAST_(1) << 13)
259#define IE_IRQ4 (_ULCAST_(1) << 14)
260#define IE_IRQ5 (_ULCAST_(1) << 15)
261
262/*
263 * R4x00 interrupt cause bits
264 */
265#define C_SW0 (_ULCAST_(1) << 8)
266#define C_SW1 (_ULCAST_(1) << 9)
267#define C_IRQ0 (_ULCAST_(1) << 10)
268#define C_IRQ1 (_ULCAST_(1) << 11)
269#define C_IRQ2 (_ULCAST_(1) << 12)
270#define C_IRQ3 (_ULCAST_(1) << 13)
271#define C_IRQ4 (_ULCAST_(1) << 14)
272#define C_IRQ5 (_ULCAST_(1) << 15)
273
274/*
275 * Bitfields in the R4xx0 cp0 status register
276 */
277#define ST0_IE 0x00000001
278#define ST0_EXL 0x00000002
279#define ST0_ERL 0x00000004
280#define ST0_KSU 0x00000018
281# define KSU_USER 0x00000010
282# define KSU_SUPERVISOR 0x00000008
283# define KSU_KERNEL 0x00000000
284#define ST0_UX 0x00000020
285#define ST0_SX 0x00000040
286#define ST0_KX 0x00000080
287#define ST0_DE 0x00010000
288#define ST0_CE 0x00020000
289
290/*
291 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
292 * cacheops in userspace. This bit exists only on RM7000 and RM9000
293 * processors.
294 */
295#define ST0_CO 0x08000000
296
297/*
298 * Bitfields in the R[23]000 cp0 status register.
299 */
300#define ST0_IEC 0x00000001
301#define ST0_KUC 0x00000002
302#define ST0_IEP 0x00000004
303#define ST0_KUP 0x00000008
304#define ST0_IEO 0x00000010
305#define ST0_KUO 0x00000020
306/* bits 6 & 7 are reserved on R[23]000 */
307#define ST0_ISC 0x00010000
308#define ST0_SWC 0x00020000
309#define ST0_CM 0x00080000
310
311/*
312 * Bits specific to the R4640/R4650
313 */
314#define ST0_UM (_ULCAST_(1) << 4)
315#define ST0_IL (_ULCAST_(1) << 23)
316#define ST0_DL (_ULCAST_(1) << 24)
317
318/*
319 * Enable the MIPS MDMX and DSP ASEs
320 */
321#define ST0_MX 0x01000000
322
323/*
324 * Status register bits available in all MIPS CPUs.
325 */
326#define ST0_IM 0x0000ff00
327#define STATUSB_IP0 8
328#define STATUSF_IP0 (_ULCAST_(1) << 8)
329#define STATUSB_IP1 9
330#define STATUSF_IP1 (_ULCAST_(1) << 9)
331#define STATUSB_IP2 10
332#define STATUSF_IP2 (_ULCAST_(1) << 10)
333#define STATUSB_IP3 11
334#define STATUSF_IP3 (_ULCAST_(1) << 11)
335#define STATUSB_IP4 12
336#define STATUSF_IP4 (_ULCAST_(1) << 12)
337#define STATUSB_IP5 13
338#define STATUSF_IP5 (_ULCAST_(1) << 13)
339#define STATUSB_IP6 14
340#define STATUSF_IP6 (_ULCAST_(1) << 14)
341#define STATUSB_IP7 15
342#define STATUSF_IP7 (_ULCAST_(1) << 15)
343#define STATUSB_IP8 0
344#define STATUSF_IP8 (_ULCAST_(1) << 0)
345#define STATUSB_IP9 1
346#define STATUSF_IP9 (_ULCAST_(1) << 1)
347#define STATUSB_IP10 2
348#define STATUSF_IP10 (_ULCAST_(1) << 2)
349#define STATUSB_IP11 3
350#define STATUSF_IP11 (_ULCAST_(1) << 3)
351#define STATUSB_IP12 4
352#define STATUSF_IP12 (_ULCAST_(1) << 4)
353#define STATUSB_IP13 5
354#define STATUSF_IP13 (_ULCAST_(1) << 5)
355#define STATUSB_IP14 6
356#define STATUSF_IP14 (_ULCAST_(1) << 6)
357#define STATUSB_IP15 7
358#define STATUSF_IP15 (_ULCAST_(1) << 7)
359#define ST0_CH 0x00040000
360#define ST0_NMI 0x00080000
361#define ST0_SR 0x00100000
362#define ST0_TS 0x00200000
363#define ST0_BEV 0x00400000
364#define ST0_RE 0x02000000
365#define ST0_FR 0x04000000
366#define ST0_CU 0xf0000000
367#define ST0_CU0 0x10000000
368#define ST0_CU1 0x20000000
369#define ST0_CU2 0x40000000
370#define ST0_CU3 0x80000000
371#define ST0_XX 0x80000000 /* MIPS IV naming */
372
373/*
374 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
375 */
376#define INTCTLB_IPFDC 23
377#define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
378#define INTCTLB_IPPCI 26
379#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
380#define INTCTLB_IPTI 29
381#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
382
383/*
384 * Bitfields and bit numbers in the coprocessor 0 cause register.
385 *
386 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
387 */
388#define CAUSEB_EXCCODE 2
389#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
390#define CAUSEB_IP 8
391#define CAUSEF_IP (_ULCAST_(255) << 8)
392#define CAUSEB_IP0 8
393#define CAUSEF_IP0 (_ULCAST_(1) << 8)
394#define CAUSEB_IP1 9
395#define CAUSEF_IP1 (_ULCAST_(1) << 9)
396#define CAUSEB_IP2 10
397#define CAUSEF_IP2 (_ULCAST_(1) << 10)
398#define CAUSEB_IP3 11
399#define CAUSEF_IP3 (_ULCAST_(1) << 11)
400#define CAUSEB_IP4 12
401#define CAUSEF_IP4 (_ULCAST_(1) << 12)
402#define CAUSEB_IP5 13
403#define CAUSEF_IP5 (_ULCAST_(1) << 13)
404#define CAUSEB_IP6 14
405#define CAUSEF_IP6 (_ULCAST_(1) << 14)
406#define CAUSEB_IP7 15
407#define CAUSEF_IP7 (_ULCAST_(1) << 15)
408#define CAUSEB_FDCI 21
409#define CAUSEF_FDCI (_ULCAST_(1) << 21)
410#define CAUSEB_WP 22
411#define CAUSEF_WP (_ULCAST_(1) << 22)
412#define CAUSEB_IV 23
413#define CAUSEF_IV (_ULCAST_(1) << 23)
414#define CAUSEB_PCI 26
415#define CAUSEF_PCI (_ULCAST_(1) << 26)
416#define CAUSEB_DC 27
417#define CAUSEF_DC (_ULCAST_(1) << 27)
418#define CAUSEB_CE 28
419#define CAUSEF_CE (_ULCAST_(3) << 28)
420#define CAUSEB_TI 30
421#define CAUSEF_TI (_ULCAST_(1) << 30)
422#define CAUSEB_BD 31
423#define CAUSEF_BD (_ULCAST_(1) << 31)
424
425/*
426 * Cause.ExcCode trap codes.
427 */
428#define EXCCODE_INT 0 /* Interrupt pending */
429#define EXCCODE_MOD 1 /* TLB modified fault */
430#define EXCCODE_TLBL 2 /* TLB miss on load or ifetch */
431#define EXCCODE_TLBS 3 /* TLB miss on a store */
432#define EXCCODE_ADEL 4 /* Address error on a load or ifetch */
433#define EXCCODE_ADES 5 /* Address error on a store */
434#define EXCCODE_IBE 6 /* Bus error on an ifetch */
435#define EXCCODE_DBE 7 /* Bus error on a load or store */
436#define EXCCODE_SYS 8 /* System call */
437#define EXCCODE_BP 9 /* Breakpoint */
438#define EXCCODE_RI 10 /* Reserved instruction exception */
439#define EXCCODE_CPU 11 /* Coprocessor unusable */
440#define EXCCODE_OV 12 /* Arithmetic overflow */
441#define EXCCODE_TR 13 /* Trap instruction */
442#define EXCCODE_MSAFPE 14 /* MSA floating point exception */
443#define EXCCODE_FPE 15 /* Floating point exception */
444#define EXCCODE_TLBRI 19 /* TLB Read-Inhibit exception */
445#define EXCCODE_TLBXI 20 /* TLB Execution-Inhibit exception */
446#define EXCCODE_MSADIS 21 /* MSA disabled exception */
447#define EXCCODE_MDMX 22 /* MDMX unusable exception */
448#define EXCCODE_WATCH 23 /* Watch address reference */
449#define EXCCODE_MCHECK 24 /* Machine check */
450#define EXCCODE_THREAD 25 /* Thread exceptions (MT) */
451#define EXCCODE_DSPDIS 26 /* DSP disabled exception */
452#define EXCCODE_GE 27 /* Virtualized guest exception (VZ) */
453
454/* Implementation specific trap codes used by MIPS cores */
455#define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */
456
457/*
458 * Bits in the coprocessor 0 config register.
459 */
460/* Generic bits. */
461#define CONF_CM_CACHABLE_NO_WA 0
462#define CONF_CM_CACHABLE_WA 1
463#define CONF_CM_UNCACHED 2
464#define CONF_CM_CACHABLE_NONCOHERENT 3
465#define CONF_CM_CACHABLE_CE 4
466#define CONF_CM_CACHABLE_COW 5
467#define CONF_CM_CACHABLE_CUW 6
468#define CONF_CM_CACHABLE_ACCELERATED 7
469#define CONF_CM_CMASK 7
470#define CONF_BE (_ULCAST_(1) << 15)
471
472/* Bits common to various processors. */
473#define CONF_CU (_ULCAST_(1) << 3)
474#define CONF_DB (_ULCAST_(1) << 4)
475#define CONF_IB (_ULCAST_(1) << 5)
476#define CONF_DC (_ULCAST_(7) << 6)
477#define CONF_IC (_ULCAST_(7) << 9)
478#define CONF_EB (_ULCAST_(1) << 13)
479#define CONF_EM (_ULCAST_(1) << 14)
480#define CONF_SM (_ULCAST_(1) << 16)
481#define CONF_SC (_ULCAST_(1) << 17)
482#define CONF_EW (_ULCAST_(3) << 18)
483#define CONF_EP (_ULCAST_(15)<< 24)
484#define CONF_EC (_ULCAST_(7) << 28)
485#define CONF_CM (_ULCAST_(1) << 31)
486
487/* Bits specific to the R4xx0. */
488#define R4K_CONF_SW (_ULCAST_(1) << 20)
489#define R4K_CONF_SS (_ULCAST_(1) << 21)
490#define R4K_CONF_SB (_ULCAST_(3) << 22)
491
492/* Bits specific to the R5000. */
493#define R5K_CONF_SE (_ULCAST_(1) << 12)
494#define R5K_CONF_SS (_ULCAST_(3) << 20)
495
496/* Bits specific to the RM7000. */
497#define RM7K_CONF_SE (_ULCAST_(1) << 3)
498#define RM7K_CONF_TE (_ULCAST_(1) << 12)
499#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
500#define RM7K_CONF_TC (_ULCAST_(1) << 17)
501#define RM7K_CONF_SI (_ULCAST_(3) << 20)
502#define RM7K_CONF_SC (_ULCAST_(1) << 31)
503
504/* Bits specific to the R10000. */
505#define R10K_CONF_DN (_ULCAST_(3) << 3)
506#define R10K_CONF_CT (_ULCAST_(1) << 5)
507#define R10K_CONF_PE (_ULCAST_(1) << 6)
508#define R10K_CONF_PM (_ULCAST_(3) << 7)
509#define R10K_CONF_EC (_ULCAST_(15)<< 9)
510#define R10K_CONF_SB (_ULCAST_(1) << 13)
511#define R10K_CONF_SK (_ULCAST_(1) << 14)
512#define R10K_CONF_SS (_ULCAST_(7) << 16)
513#define R10K_CONF_SC (_ULCAST_(7) << 19)
514#define R10K_CONF_DC (_ULCAST_(7) << 26)
515#define R10K_CONF_IC (_ULCAST_(7) << 29)
516
517/* Bits specific to the VR41xx. */
518#define VR41_CONF_CS (_ULCAST_(1) << 12)
519#define VR41_CONF_P4K (_ULCAST_(1) << 13)
520#define VR41_CONF_BP (_ULCAST_(1) << 16)
521#define VR41_CONF_M16 (_ULCAST_(1) << 20)
522#define VR41_CONF_AD (_ULCAST_(1) << 23)
523
524/* Bits specific to the R30xx. */
525#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
526#define R30XX_CONF_REV (_ULCAST_(1) << 22)
527#define R30XX_CONF_AC (_ULCAST_(1) << 23)
528#define R30XX_CONF_RF (_ULCAST_(1) << 24)
529#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
530#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
531#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
532#define R30XX_CONF_SB (_ULCAST_(1) << 30)
533#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
534
535/* Bits specific to the TX49. */
536#define TX49_CONF_DC (_ULCAST_(1) << 16)
537#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
538#define TX49_CONF_HALT (_ULCAST_(1) << 18)
539#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
540
541/* Bits specific to the MIPS32/64 PRA. */
542#define MIPS_CONF_VI (_ULCAST_(1) << 3)
543#define MIPS_CONF_MT (_ULCAST_(7) << 7)
544#define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
545#define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
546#define MIPS_CONF_AR (_ULCAST_(7) << 10)
547#define MIPS_CONF_AT (_ULCAST_(3) << 13)
548#define MIPS_CONF_M (_ULCAST_(1) << 31)
549
550/*
551 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
552 */
553#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
554#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
555#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
556#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
557#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
558#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
559#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
560#define MIPS_CONF1_DA_SHF 7
561#define MIPS_CONF1_DA_SZ 3
562#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
563#define MIPS_CONF1_DL_SHF 10
564#define MIPS_CONF1_DL_SZ 3
565#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
566#define MIPS_CONF1_DS_SHF 13
567#define MIPS_CONF1_DS_SZ 3
568#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
569#define MIPS_CONF1_IA_SHF 16
570#define MIPS_CONF1_IA_SZ 3
571#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
572#define MIPS_CONF1_IL_SHF 19
573#define MIPS_CONF1_IL_SZ 3
574#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
575#define MIPS_CONF1_IS_SHF 22
576#define MIPS_CONF1_IS_SZ 3
577#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
578#define MIPS_CONF1_TLBS_SHIFT (25)
579#define MIPS_CONF1_TLBS_SIZE (6)
580#define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
581
582#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
583#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
584#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
585#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
586#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
587#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
588#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
589#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
590
591#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
592#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
593#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
594#define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
595#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
596#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
597#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
598#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
599#define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
600#define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
601#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
602#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
603#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
604#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
605#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
606#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
607#define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
608#define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
609#define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
610#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
611#define MIPS_CONF3_PW (_ULCAST_(1) << 24)
612#define MIPS_CONF3_SC (_ULCAST_(1) << 25)
613#define MIPS_CONF3_BI (_ULCAST_(1) << 26)
614#define MIPS_CONF3_BP (_ULCAST_(1) << 27)
615#define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
616#define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
617#define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
618
619#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
620#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
621#define MIPS_CONF4_FTLBSETS_SHIFT (0)
622#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
623#define MIPS_CONF4_FTLBWAYS_SHIFT (4)
624#define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
625#define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
626/* bits 10:8 in FTLB-only configurations */
627#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
628/* bits 12:8 in VTLB-FTLB only configurations */
629#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
630#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
631#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
632#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
633#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
634#define MIPS_CONF4_KSCREXIST_SHIFT (16)
635#define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
636#define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
637#define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
638#define MIPS_CONF4_AE (_ULCAST_(1) << 28)
639#define MIPS_CONF4_IE (_ULCAST_(3) << 29)
640#define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
641
642#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
643#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
644#define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
645#define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
646#define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
647#define MIPS_CONF5_VP (_ULCAST_(1) << 7)
648#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
649#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
650#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
651#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
652#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
653#define MIPS_CONF5_K (_ULCAST_(1) << 30)
654
655#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
656/* proAptiv FTLB on/off bit */
657#define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
658/* Loongson-3 FTLB on/off bit */
659#define MIPS_CONF6_FTLBDIS (_ULCAST_(1) << 22)
660/* FTLB probability bits */
661#define MIPS_CONF6_FTLBP_SHIFT (16)
662
663#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
664
665#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
666
667#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
668#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
669
670/* WatchLo* register definitions */
671#define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0)
672
673/* WatchHi* register definitions */
674#define MIPS_WATCHHI_M (_ULCAST_(1) << 31)
675#define MIPS_WATCHHI_G (_ULCAST_(1) << 30)
676#define MIPS_WATCHHI_WM (_ULCAST_(0x3) << 28)
677#define MIPS_WATCHHI_WM_R_RVA (_ULCAST_(0) << 28)
678#define MIPS_WATCHHI_WM_R_GPA (_ULCAST_(1) << 28)
679#define MIPS_WATCHHI_WM_G_GVA (_ULCAST_(2) << 28)
680#define MIPS_WATCHHI_EAS (_ULCAST_(0x3) << 24)
681#define MIPS_WATCHHI_ASID (_ULCAST_(0xff) << 16)
682#define MIPS_WATCHHI_MASK (_ULCAST_(0x1ff) << 3)
683#define MIPS_WATCHHI_I (_ULCAST_(1) << 2)
684#define MIPS_WATCHHI_R (_ULCAST_(1) << 1)
685#define MIPS_WATCHHI_W (_ULCAST_(1) << 0)
686#define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0)
687
688/* MAAR bit definitions */
689#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
690#define MIPS_MAAR_ADDR_SHIFT 12
691#define MIPS_MAAR_S (_ULCAST_(1) << 1)
692#define MIPS_MAAR_V (_ULCAST_(1) << 0)
693
694/* EBase bit definitions */
695#define MIPS_EBASE_CPUNUM_SHIFT 0
696#define MIPS_EBASE_CPUNUM (_ULCAST_(0x3ff) << 0)
697#define MIPS_EBASE_WG_SHIFT 11
698#define MIPS_EBASE_WG (_ULCAST_(1) << 11)
699#define MIPS_EBASE_BASE_SHIFT 12
700#define MIPS_EBASE_BASE (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
701
702/* CMGCRBase bit definitions */
703#define MIPS_CMGCRB_BASE 11
704#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
705
706/*
707 * Bits in the MIPS32 Memory Segmentation registers.
708 */
709#define MIPS_SEGCFG_PA_SHIFT 9
710#define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
711#define MIPS_SEGCFG_AM_SHIFT 4
712#define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
713#define MIPS_SEGCFG_EU_SHIFT 3
714#define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
715#define MIPS_SEGCFG_C_SHIFT 0
716#define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
717
718#define MIPS_SEGCFG_UUSK _ULCAST_(7)
719#define MIPS_SEGCFG_USK _ULCAST_(5)
720#define MIPS_SEGCFG_MUSUK _ULCAST_(4)
721#define MIPS_SEGCFG_MUSK _ULCAST_(3)
722#define MIPS_SEGCFG_MSK _ULCAST_(2)
723#define MIPS_SEGCFG_MK _ULCAST_(1)
724#define MIPS_SEGCFG_UK _ULCAST_(0)
725
726#define MIPS_PWFIELD_GDI_SHIFT 24
727#define MIPS_PWFIELD_GDI_MASK 0x3f000000
728#define MIPS_PWFIELD_UDI_SHIFT 18
729#define MIPS_PWFIELD_UDI_MASK 0x00fc0000
730#define MIPS_PWFIELD_MDI_SHIFT 12
731#define MIPS_PWFIELD_MDI_MASK 0x0003f000
732#define MIPS_PWFIELD_PTI_SHIFT 6
733#define MIPS_PWFIELD_PTI_MASK 0x00000fc0
734#define MIPS_PWFIELD_PTEI_SHIFT 0
735#define MIPS_PWFIELD_PTEI_MASK 0x0000003f
736
737#define MIPS_PWSIZE_PS_SHIFT 30
738#define MIPS_PWSIZE_PS_MASK 0x40000000
739#define MIPS_PWSIZE_GDW_SHIFT 24
740#define MIPS_PWSIZE_GDW_MASK 0x3f000000
741#define MIPS_PWSIZE_UDW_SHIFT 18
742#define MIPS_PWSIZE_UDW_MASK 0x00fc0000
743#define MIPS_PWSIZE_MDW_SHIFT 12
744#define MIPS_PWSIZE_MDW_MASK 0x0003f000
745#define MIPS_PWSIZE_PTW_SHIFT 6
746#define MIPS_PWSIZE_PTW_MASK 0x00000fc0
747#define MIPS_PWSIZE_PTEW_SHIFT 0
748#define MIPS_PWSIZE_PTEW_MASK 0x0000003f
749
750#define MIPS_PWCTL_PWEN_SHIFT 31
751#define MIPS_PWCTL_PWEN_MASK 0x80000000
752#define MIPS_PWCTL_XK_SHIFT 28
753#define MIPS_PWCTL_XK_MASK 0x10000000
754#define MIPS_PWCTL_XS_SHIFT 27
755#define MIPS_PWCTL_XS_MASK 0x08000000
756#define MIPS_PWCTL_XU_SHIFT 26
757#define MIPS_PWCTL_XU_MASK 0x04000000
758#define MIPS_PWCTL_DPH_SHIFT 7
759#define MIPS_PWCTL_DPH_MASK 0x00000080
760#define MIPS_PWCTL_HUGEPG_SHIFT 6
761#define MIPS_PWCTL_HUGEPG_MASK 0x00000060
762#define MIPS_PWCTL_PSN_SHIFT 0
763#define MIPS_PWCTL_PSN_MASK 0x0000003f
764
765/* GuestCtl0 fields */
766#define MIPS_GCTL0_GM_SHIFT 31
767#define MIPS_GCTL0_GM (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
768#define MIPS_GCTL0_RI_SHIFT 30
769#define MIPS_GCTL0_RI (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
770#define MIPS_GCTL0_MC_SHIFT 29
771#define MIPS_GCTL0_MC (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
772#define MIPS_GCTL0_CP0_SHIFT 28
773#define MIPS_GCTL0_CP0 (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
774#define MIPS_GCTL0_AT_SHIFT 26
775#define MIPS_GCTL0_AT (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
776#define MIPS_GCTL0_GT_SHIFT 25
777#define MIPS_GCTL0_GT (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
778#define MIPS_GCTL0_CG_SHIFT 24
779#define MIPS_GCTL0_CG (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
780#define MIPS_GCTL0_CF_SHIFT 23
781#define MIPS_GCTL0_CF (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
782#define MIPS_GCTL0_G1_SHIFT 22
783#define MIPS_GCTL0_G1 (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
784#define MIPS_GCTL0_G0E_SHIFT 19
785#define MIPS_GCTL0_G0E (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
786#define MIPS_GCTL0_PT_SHIFT 18
787#define MIPS_GCTL0_PT (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
788#define MIPS_GCTL0_RAD_SHIFT 9
789#define MIPS_GCTL0_RAD (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
790#define MIPS_GCTL0_DRG_SHIFT 8
791#define MIPS_GCTL0_DRG (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
792#define MIPS_GCTL0_G2_SHIFT 7
793#define MIPS_GCTL0_G2 (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
794#define MIPS_GCTL0_GEXC_SHIFT 2
795#define MIPS_GCTL0_GEXC (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
796#define MIPS_GCTL0_SFC2_SHIFT 1
797#define MIPS_GCTL0_SFC2 (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
798#define MIPS_GCTL0_SFC1_SHIFT 0
799#define MIPS_GCTL0_SFC1 (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
800
801/* GuestCtl0.AT Guest address translation control */
802#define MIPS_GCTL0_AT_ROOT 1 /* Guest MMU under Root control */
803#define MIPS_GCTL0_AT_GUEST 3 /* Guest MMU under Guest control */
804
805/* GuestCtl0.GExcCode Hypervisor exception cause codes */
806#define MIPS_GCTL0_GEXC_GPSI 0 /* Guest Privileged Sensitive Instruction */
807#define MIPS_GCTL0_GEXC_GSFC 1 /* Guest Software Field Change */
808#define MIPS_GCTL0_GEXC_HC 2 /* Hypercall */
809#define MIPS_GCTL0_GEXC_GRR 3 /* Guest Reserved Instruction Redirect */
810#define MIPS_GCTL0_GEXC_GVA 8 /* Guest Virtual Address available */
811#define MIPS_GCTL0_GEXC_GHFC 9 /* Guest Hardware Field Change */
812#define MIPS_GCTL0_GEXC_GPA 10 /* Guest Physical Address available */
813
814/* GuestCtl0Ext fields */
815#define MIPS_GCTL0EXT_RPW_SHIFT 8
816#define MIPS_GCTL0EXT_RPW (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
817#define MIPS_GCTL0EXT_NCC_SHIFT 6
818#define MIPS_GCTL0EXT_NCC (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
819#define MIPS_GCTL0EXT_CGI_SHIFT 4
820#define MIPS_GCTL0EXT_CGI (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
821#define MIPS_GCTL0EXT_FCD_SHIFT 3
822#define MIPS_GCTL0EXT_FCD (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
823#define MIPS_GCTL0EXT_OG_SHIFT 2
824#define MIPS_GCTL0EXT_OG (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
825#define MIPS_GCTL0EXT_BG_SHIFT 1
826#define MIPS_GCTL0EXT_BG (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
827#define MIPS_GCTL0EXT_MG_SHIFT 0
828#define MIPS_GCTL0EXT_MG (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
829
830/* GuestCtl0Ext.RPW Root page walk configuration */
831#define MIPS_GCTL0EXT_RPW_BOTH 0 /* Root PW for GPA->RPA and RVA->RPA */
832#define MIPS_GCTL0EXT_RPW_GPA 2 /* Root PW for GPA->RPA */
833#define MIPS_GCTL0EXT_RPW_RVA 3 /* Root PW for RVA->RPA */
834
835/* GuestCtl0Ext.NCC Nested cache coherency attributes */
836#define MIPS_GCTL0EXT_NCC_IND 0 /* Guest CCA independent of Root CCA */
837#define MIPS_GCTL0EXT_NCC_MOD 1 /* Guest CCA modified by Root CCA */
838
839/* GuestCtl1 fields */
840#define MIPS_GCTL1_ID_SHIFT 0
841#define MIPS_GCTL1_ID_WIDTH 8
842#define MIPS_GCTL1_ID (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
843#define MIPS_GCTL1_RID_SHIFT 16
844#define MIPS_GCTL1_RID_WIDTH 8
845#define MIPS_GCTL1_RID (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
846#define MIPS_GCTL1_EID_SHIFT 24
847#define MIPS_GCTL1_EID_WIDTH 8
848#define MIPS_GCTL1_EID (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
849
850/* GuestID reserved for root context */
851#define MIPS_GCTL1_ROOT_GUESTID 0
852
853/* CDMMBase register bit definitions */
854#define MIPS_CDMMBASE_SIZE_SHIFT 0
855#define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
856#define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
857#define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
858#define MIPS_CDMMBASE_ADDR_SHIFT 11
859#define MIPS_CDMMBASE_ADDR_START 15
860
861/* RDHWR register numbers */
862#define MIPS_HWR_CPUNUM 0 /* CPU number */
863#define MIPS_HWR_SYNCISTEP 1 /* SYNCI step size */
864#define MIPS_HWR_CC 2 /* Cycle counter */
865#define MIPS_HWR_CCRES 3 /* Cycle counter resolution */
866#define MIPS_HWR_ULR 29 /* UserLocal */
867#define MIPS_HWR_IMPL1 30 /* Implementation dependent */
868#define MIPS_HWR_IMPL2 31 /* Implementation dependent */
869
870/* Bits in HWREna register */
871#define MIPS_HWRENA_CPUNUM (_ULCAST_(1) << MIPS_HWR_CPUNUM)
872#define MIPS_HWRENA_SYNCISTEP (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
873#define MIPS_HWRENA_CC (_ULCAST_(1) << MIPS_HWR_CC)
874#define MIPS_HWRENA_CCRES (_ULCAST_(1) << MIPS_HWR_CCRES)
875#define MIPS_HWRENA_ULR (_ULCAST_(1) << MIPS_HWR_ULR)
876#define MIPS_HWRENA_IMPL1 (_ULCAST_(1) << MIPS_HWR_IMPL1)
877#define MIPS_HWRENA_IMPL2 (_ULCAST_(1) << MIPS_HWR_IMPL2)
878
879/*
880 * Bitfields in the TX39 family CP0 Configuration Register 3
881 */
882#define TX39_CONF_ICS_SHIFT 19
883#define TX39_CONF_ICS_MASK 0x00380000
884#define TX39_CONF_ICS_1KB 0x00000000
885#define TX39_CONF_ICS_2KB 0x00080000
886#define TX39_CONF_ICS_4KB 0x00100000
887#define TX39_CONF_ICS_8KB 0x00180000
888#define TX39_CONF_ICS_16KB 0x00200000
889
890#define TX39_CONF_DCS_SHIFT 16
891#define TX39_CONF_DCS_MASK 0x00070000
892#define TX39_CONF_DCS_1KB 0x00000000
893#define TX39_CONF_DCS_2KB 0x00010000
894#define TX39_CONF_DCS_4KB 0x00020000
895#define TX39_CONF_DCS_8KB 0x00030000
896#define TX39_CONF_DCS_16KB 0x00040000
897
898#define TX39_CONF_CWFON 0x00004000
899#define TX39_CONF_WBON 0x00002000
900#define TX39_CONF_RF_SHIFT 10
901#define TX39_CONF_RF_MASK 0x00000c00
902#define TX39_CONF_DOZE 0x00000200
903#define TX39_CONF_HALT 0x00000100
904#define TX39_CONF_LOCK 0x00000080
905#define TX39_CONF_ICE 0x00000020
906#define TX39_CONF_DCE 0x00000010
907#define TX39_CONF_IRSIZE_SHIFT 2
908#define TX39_CONF_IRSIZE_MASK 0x0000000c
909#define TX39_CONF_DRSIZE_SHIFT 0
910#define TX39_CONF_DRSIZE_MASK 0x00000003
911
912/*
913 * Interesting Bits in the R10K CP0 Branch Diagnostic Register
914 */
915/* Disable Branch Target Address Cache */
916#define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
917/* Enable Branch Prediction Global History */
918#define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
919/* Disable Branch Return Cache */
920#define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
921
922/* Flush ITLB */
923#define LOONGSON_DIAG_ITLB (_ULCAST_(1) << 2)
924/* Flush DTLB */
925#define LOONGSON_DIAG_DTLB (_ULCAST_(1) << 3)
926/* Flush VTLB */
927#define LOONGSON_DIAG_VTLB (_ULCAST_(1) << 12)
928/* Flush FTLB */
929#define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13)
930
931/*
932 * Coprocessor 1 (FPU) register names
933 */
934#define CP1_REVISION $0
935#define CP1_UFR $1
936#define CP1_UNFR $4
937#define CP1_FCCR $25
938#define CP1_FEXR $26
939#define CP1_FENR $28
940#define CP1_STATUS $31
941
942
943/*
944 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
945 */
946#define MIPS_FPIR_S (_ULCAST_(1) << 16)
947#define MIPS_FPIR_D (_ULCAST_(1) << 17)
948#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
949#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
950#define MIPS_FPIR_W (_ULCAST_(1) << 20)
951#define MIPS_FPIR_L (_ULCAST_(1) << 21)
952#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
953#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
954#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
955#define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
956
957/*
958 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
959 */
960#define MIPS_FCCR_CONDX_S 0
961#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
962#define MIPS_FCCR_COND0_S 0
963#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
964#define MIPS_FCCR_COND1_S 1
965#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
966#define MIPS_FCCR_COND2_S 2
967#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
968#define MIPS_FCCR_COND3_S 3
969#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
970#define MIPS_FCCR_COND4_S 4
971#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
972#define MIPS_FCCR_COND5_S 5
973#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
974#define MIPS_FCCR_COND6_S 6
975#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
976#define MIPS_FCCR_COND7_S 7
977#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
978
979/*
980 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
981 */
982#define MIPS_FENR_FS_S 2
983#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
984
985/*
986 * FPU Status Register Values
987 */
988#define FPU_CSR_COND_S 23 /* $fcc0 */
989#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
990
991#define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
992#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
993
994#define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
995#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
996#define FPU_CSR_COND1_S 25 /* $fcc1 */
997#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
998#define FPU_CSR_COND2_S 26 /* $fcc2 */
999#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
1000#define FPU_CSR_COND3_S 27 /* $fcc3 */
1001#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
1002#define FPU_CSR_COND4_S 28 /* $fcc4 */
1003#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
1004#define FPU_CSR_COND5_S 29 /* $fcc5 */
1005#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
1006#define FPU_CSR_COND6_S 30 /* $fcc6 */
1007#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
1008#define FPU_CSR_COND7_S 31 /* $fcc7 */
1009#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
1010
1011/*
1012 * Bits 22:20 of the FPU Status Register will be read as 0,
1013 * and should be written as zero.
1014 */
1015#define FPU_CSR_RSVD (_ULCAST_(7) << 20)
1016
1017#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
1018#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1019
1020/*
1021 * X the exception cause indicator
1022 * E the exception enable
1023 * S the sticky/flag bit
1024*/
1025#define FPU_CSR_ALL_X 0x0003f000
1026#define FPU_CSR_UNI_X 0x00020000
1027#define FPU_CSR_INV_X 0x00010000
1028#define FPU_CSR_DIV_X 0x00008000
1029#define FPU_CSR_OVF_X 0x00004000
1030#define FPU_CSR_UDF_X 0x00002000
1031#define FPU_CSR_INE_X 0x00001000
1032
1033#define FPU_CSR_ALL_E 0x00000f80
1034#define FPU_CSR_INV_E 0x00000800
1035#define FPU_CSR_DIV_E 0x00000400
1036#define FPU_CSR_OVF_E 0x00000200
1037#define FPU_CSR_UDF_E 0x00000100
1038#define FPU_CSR_INE_E 0x00000080
1039
1040#define FPU_CSR_ALL_S 0x0000007c
1041#define FPU_CSR_INV_S 0x00000040
1042#define FPU_CSR_DIV_S 0x00000020
1043#define FPU_CSR_OVF_S 0x00000010
1044#define FPU_CSR_UDF_S 0x00000008
1045#define FPU_CSR_INE_S 0x00000004
1046
1047/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1048#define FPU_CSR_RM 0x00000003
1049#define FPU_CSR_RN 0x0 /* nearest */
1050#define FPU_CSR_RZ 0x1 /* towards zero */
1051#define FPU_CSR_RU 0x2 /* towards +Infinity */
1052#define FPU_CSR_RD 0x3 /* towards -Infinity */
1053
1054
1055#ifndef __ASSEMBLY__
1056
1057/*
1058 * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1059 */
1060#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1061 defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1062#define get_isa16_mode(x) ((x) & 0x1)
1063#define msk_isa16_mode(x) ((x) & ~0x1)
1064#define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
1065#else
1066#define get_isa16_mode(x) 0
1067#define msk_isa16_mode(x) (x)
1068#define set_isa16_mode(x) do { } while(0)
1069#endif
1070
1071/*
1072 * microMIPS instructions can be 16-bit or 32-bit in length. This
1073 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1074 */
1075static inline int mm_insn_16bit(u16 insn)
1076{
1077 u16 opcode = (insn >> 10) & 0x7;
1078
1079 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1080}
1081
1082/*
1083 * Helper macros for generating raw instruction encodings in inline asm.
1084 */
1085#ifdef CONFIG_CPU_MICROMIPS
1086#define _ASM_INSN16_IF_MM(_enc) \
1087 ".insn\n\t" \
1088 ".hword (" #_enc ")\n\t"
1089#define _ASM_INSN32_IF_MM(_enc) \
1090 ".insn\n\t" \
1091 ".hword ((" #_enc ") >> 16)\n\t" \
1092 ".hword ((" #_enc ") & 0xffff)\n\t"
1093#else
1094#define _ASM_INSN_IF_MIPS(_enc) \
1095 ".insn\n\t" \
1096 ".word (" #_enc ")\n\t"
1097#endif
1098
1099#ifndef _ASM_INSN16_IF_MM
1100#define _ASM_INSN16_IF_MM(_enc)
1101#endif
1102#ifndef _ASM_INSN32_IF_MM
1103#define _ASM_INSN32_IF_MM(_enc)
1104#endif
1105#ifndef _ASM_INSN_IF_MIPS
1106#define _ASM_INSN_IF_MIPS(_enc)
1107#endif
1108
1109/*
1110 * TLB Invalidate Flush
1111 */
1112static inline void tlbinvf(void)
1113{
1114 __asm__ __volatile__(
1115 ".set push\n\t"
1116 ".set noreorder\n\t"
1117 "# tlbinvf\n\t"
1118 _ASM_INSN_IF_MIPS(0x42000004)
1119 _ASM_INSN32_IF_MM(0x0000537c)
1120 ".set pop");
1121}
1122
1123
1124/*
1125 * Functions to access the R10000 performance counters. These are basically
1126 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1127 * performance counter number encoded into bits 1 ... 5 of the instruction.
1128 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1129 * disassembler these will look like an access to sel 0 or 1.
1130 */
1131#define read_r10k_perf_cntr(counter) \
1132({ \
1133 unsigned int __res; \
1134 __asm__ __volatile__( \
1135 "mfpc\t%0, %1" \
1136 : "=r" (__res) \
1137 : "i" (counter)); \
1138 \
1139 __res; \
1140})
1141
1142#define write_r10k_perf_cntr(counter,val) \
1143do { \
1144 __asm__ __volatile__( \
1145 "mtpc\t%0, %1" \
1146 : \
1147 : "r" (val), "i" (counter)); \
1148} while (0)
1149
1150#define read_r10k_perf_event(counter) \
1151({ \
1152 unsigned int __res; \
1153 __asm__ __volatile__( \
1154 "mfps\t%0, %1" \
1155 : "=r" (__res) \
1156 : "i" (counter)); \
1157 \
1158 __res; \
1159})
1160
1161#define write_r10k_perf_cntl(counter,val) \
1162do { \
1163 __asm__ __volatile__( \
1164 "mtps\t%0, %1" \
1165 : \
1166 : "r" (val), "i" (counter)); \
1167} while (0)
1168
1169
1170/*
1171 * Macros to access the system control coprocessor
1172 */
1173
1174#define __read_32bit_c0_register(source, sel) \
1175({ unsigned int __res; \
1176 if (sel == 0) \
1177 __asm__ __volatile__( \
1178 "mfc0\t%0, " #source "\n\t" \
1179 : "=r" (__res)); \
1180 else \
1181 __asm__ __volatile__( \
1182 ".set\tmips32\n\t" \
1183 "mfc0\t%0, " #source ", " #sel "\n\t" \
1184 ".set\tmips0\n\t" \
1185 : "=r" (__res)); \
1186 __res; \
1187})
1188
1189#define __read_64bit_c0_register(source, sel) \
1190({ unsigned long long __res; \
1191 if (sizeof(unsigned long) == 4) \
1192 __res = __read_64bit_c0_split(source, sel); \
1193 else if (sel == 0) \
1194 __asm__ __volatile__( \
1195 ".set\tmips3\n\t" \
1196 "dmfc0\t%0, " #source "\n\t" \
1197 ".set\tmips0" \
1198 : "=r" (__res)); \
1199 else \
1200 __asm__ __volatile__( \
1201 ".set\tmips64\n\t" \
1202 "dmfc0\t%0, " #source ", " #sel "\n\t" \
1203 ".set\tmips0" \
1204 : "=r" (__res)); \
1205 __res; \
1206})
1207
1208#define __write_32bit_c0_register(register, sel, value) \
1209do { \
1210 if (sel == 0) \
1211 __asm__ __volatile__( \
1212 "mtc0\t%z0, " #register "\n\t" \
1213 : : "Jr" ((unsigned int)(value))); \
1214 else \
1215 __asm__ __volatile__( \
1216 ".set\tmips32\n\t" \
1217 "mtc0\t%z0, " #register ", " #sel "\n\t" \
1218 ".set\tmips0" \
1219 : : "Jr" ((unsigned int)(value))); \
1220} while (0)
1221
1222#define __write_64bit_c0_register(register, sel, value) \
1223do { \
1224 if (sizeof(unsigned long) == 4) \
1225 __write_64bit_c0_split(register, sel, value); \
1226 else if (sel == 0) \
1227 __asm__ __volatile__( \
1228 ".set\tmips3\n\t" \
1229 "dmtc0\t%z0, " #register "\n\t" \
1230 ".set\tmips0" \
1231 : : "Jr" (value)); \
1232 else \
1233 __asm__ __volatile__( \
1234 ".set\tmips64\n\t" \
1235 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
1236 ".set\tmips0" \
1237 : : "Jr" (value)); \
1238} while (0)
1239
1240#define __read_ulong_c0_register(reg, sel) \
1241 ((sizeof(unsigned long) == 4) ? \
1242 (unsigned long) __read_32bit_c0_register(reg, sel) : \
1243 (unsigned long) __read_64bit_c0_register(reg, sel))
1244
1245#define __write_ulong_c0_register(reg, sel, val) \
1246do { \
1247 if (sizeof(unsigned long) == 4) \
1248 __write_32bit_c0_register(reg, sel, val); \
1249 else \
1250 __write_64bit_c0_register(reg, sel, val); \
1251} while (0)
1252
1253/*
1254 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1255 */
1256#define __read_32bit_c0_ctrl_register(source) \
1257({ unsigned int __res; \
1258 __asm__ __volatile__( \
1259 "cfc0\t%0, " #source "\n\t" \
1260 : "=r" (__res)); \
1261 __res; \
1262})
1263
1264#define __write_32bit_c0_ctrl_register(register, value) \
1265do { \
1266 __asm__ __volatile__( \
1267 "ctc0\t%z0, " #register "\n\t" \
1268 : : "Jr" ((unsigned int)(value))); \
1269} while (0)
1270
1271/*
1272 * These versions are only needed for systems with more than 38 bits of
1273 * physical address space running the 32-bit kernel. That's none atm :-)
1274 */
1275#define __read_64bit_c0_split(source, sel) \
1276({ \
1277 unsigned long long __val; \
1278 unsigned long __flags; \
1279 \
1280 local_irq_save(__flags); \
1281 if (sel == 0) \
1282 __asm__ __volatile__( \
1283 ".set\tmips64\n\t" \
1284 "dmfc0\t%M0, " #source "\n\t" \
1285 "dsll\t%L0, %M0, 32\n\t" \
1286 "dsra\t%M0, %M0, 32\n\t" \
1287 "dsra\t%L0, %L0, 32\n\t" \
1288 ".set\tmips0" \
1289 : "=r" (__val)); \
1290 else \
1291 __asm__ __volatile__( \
1292 ".set\tmips64\n\t" \
1293 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
1294 "dsll\t%L0, %M0, 32\n\t" \
1295 "dsra\t%M0, %M0, 32\n\t" \
1296 "dsra\t%L0, %L0, 32\n\t" \
1297 ".set\tmips0" \
1298 : "=r" (__val)); \
1299 local_irq_restore(__flags); \
1300 \
1301 __val; \
1302})
1303
1304#define __write_64bit_c0_split(source, sel, val) \
1305do { \
1306 unsigned long __flags; \
1307 \
1308 local_irq_save(__flags); \
1309 if (sel == 0) \
1310 __asm__ __volatile__( \
1311 ".set\tmips64\n\t" \
1312 "dsll\t%L0, %L0, 32\n\t" \
1313 "dsrl\t%L0, %L0, 32\n\t" \
1314 "dsll\t%M0, %M0, 32\n\t" \
1315 "or\t%L0, %L0, %M0\n\t" \
1316 "dmtc0\t%L0, " #source "\n\t" \
1317 ".set\tmips0" \
1318 : : "r" (val)); \
1319 else \
1320 __asm__ __volatile__( \
1321 ".set\tmips64\n\t" \
1322 "dsll\t%L0, %L0, 32\n\t" \
1323 "dsrl\t%L0, %L0, 32\n\t" \
1324 "dsll\t%M0, %M0, 32\n\t" \
1325 "or\t%L0, %L0, %M0\n\t" \
1326 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1327 ".set\tmips0" \
1328 : : "r" (val)); \
1329 local_irq_restore(__flags); \
1330} while (0)
1331
1332#define __readx_32bit_c0_register(source) \
1333({ \
1334 unsigned int __res; \
1335 \
1336 __asm__ __volatile__( \
1337 " .set push \n" \
1338 " .set noat \n" \
1339 " .set mips32r2 \n" \
1340 " # mfhc0 $1, %1 \n" \
1341 _ASM_INSN_IF_MIPS(0x40410000 | ((%1 & 0x1f) << 11)) \
1342 _ASM_INSN32_IF_MM(0x002000f4 | ((%1 & 0x1f) << 16)) \
1343 " move %0, $1 \n" \
1344 " .set pop \n" \
1345 : "=r" (__res) \
1346 : "i" (source)); \
1347 __res; \
1348})
1349
1350#define __writex_32bit_c0_register(register, value) \
1351do { \
1352 __asm__ __volatile__( \
1353 " .set push \n" \
1354 " .set noat \n" \
1355 " .set mips32r2 \n" \
1356 " move $1, %0 \n" \
1357 " # mthc0 $1, %1 \n" \
1358 _ASM_INSN_IF_MIPS(0x40c10000 | ((%1 & 0x1f) << 11)) \
1359 _ASM_INSN32_IF_MM(0x002002f4 | ((%1 & 0x1f) << 16)) \
1360 " .set pop \n" \
1361 : \
1362 : "r" (value), "i" (register)); \
1363} while (0)
1364
1365#define read_c0_index() __read_32bit_c0_register($0, 0)
1366#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1367
1368#define read_c0_random() __read_32bit_c0_register($1, 0)
1369#define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1370
1371#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1372#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1373
1374#define readx_c0_entrylo0() __readx_32bit_c0_register(2)
1375#define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1376
1377#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1378#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1379
1380#define readx_c0_entrylo1() __readx_32bit_c0_register(3)
1381#define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1382
1383#define read_c0_conf() __read_32bit_c0_register($3, 0)
1384#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1385
1386#define read_c0_context() __read_ulong_c0_register($4, 0)
1387#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1388
1389#define read_c0_contextconfig() __read_32bit_c0_register($4, 1)
1390#define write_c0_contextconfig(val) __write_32bit_c0_register($4, 1, val)
1391
1392#define read_c0_userlocal() __read_ulong_c0_register($4, 2)
1393#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1394
1395#define read_c0_xcontextconfig() __read_ulong_c0_register($4, 3)
1396#define write_c0_xcontextconfig(val) __write_ulong_c0_register($4, 3, val)
1397
1398#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1399#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1400
1401#define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
1402#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1403
1404#define read_c0_wired() __read_32bit_c0_register($6, 0)
1405#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1406
1407#define read_c0_info() __read_32bit_c0_register($7, 0)
1408
1409#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
1410#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1411
1412#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1413#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1414
1415#define read_c0_badinstr() __read_32bit_c0_register($8, 1)
1416#define read_c0_badinstrp() __read_32bit_c0_register($8, 2)
1417
1418#define read_c0_count() __read_32bit_c0_register($9, 0)
1419#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1420
1421#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
1422#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
1423
1424#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
1425#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
1426
1427#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1428#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1429
1430#define read_c0_guestctl1() __read_32bit_c0_register($10, 4)
1431#define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1432
1433#define read_c0_guestctl2() __read_32bit_c0_register($10, 5)
1434#define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1435
1436#define read_c0_guestctl3() __read_32bit_c0_register($10, 6)
1437#define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1438
1439#define read_c0_compare() __read_32bit_c0_register($11, 0)
1440#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1441
1442#define read_c0_guestctl0ext() __read_32bit_c0_register($11, 4)
1443#define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1444
1445#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
1446#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
1447
1448#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
1449#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
1450
1451#define read_c0_status() __read_32bit_c0_register($12, 0)
1452
1453#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1454
1455#define read_c0_guestctl0() __read_32bit_c0_register($12, 6)
1456#define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1457
1458#define read_c0_gtoffset() __read_32bit_c0_register($12, 7)
1459#define write_c0_gtoffset(val) __write_32bit_c0_register($12, 7, val)
1460
1461#define read_c0_cause() __read_32bit_c0_register($13, 0)
1462#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1463
1464#define read_c0_epc() __read_ulong_c0_register($14, 0)
1465#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1466
1467#define read_c0_prid() __read_32bit_c0_register($15, 0)
1468
1469#define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
1470
1471#define read_c0_config() __read_32bit_c0_register($16, 0)
1472#define read_c0_config1() __read_32bit_c0_register($16, 1)
1473#define read_c0_config2() __read_32bit_c0_register($16, 2)
1474#define read_c0_config3() __read_32bit_c0_register($16, 3)
1475#define read_c0_config4() __read_32bit_c0_register($16, 4)
1476#define read_c0_config5() __read_32bit_c0_register($16, 5)
1477#define read_c0_config6() __read_32bit_c0_register($16, 6)
1478#define read_c0_config7() __read_32bit_c0_register($16, 7)
1479#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1480#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1481#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1482#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1483#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1484#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1485#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1486#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1487
1488#define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1489#define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1490#define read_c0_maar() __read_ulong_c0_register($17, 1)
1491#define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1492#define read_c0_maari() __read_32bit_c0_register($17, 2)
1493#define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1494
1495/*
1496 * The WatchLo register. There may be up to 8 of them.
1497 */
1498#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1499#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1500#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1501#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1502#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1503#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1504#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1505#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1506#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1507#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1508#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1509#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1510#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1511#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1512#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1513#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1514
1515/*
1516 * The WatchHi register. There may be up to 8 of them.
1517 */
1518#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1519#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
1520#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
1521#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
1522#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
1523#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
1524#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
1525#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
1526
1527#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1528#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1529#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1530#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1531#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1532#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1533#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1534#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1535
1536#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1537#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1538
1539#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
1540#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1541
1542#define read_c0_framemask() __read_32bit_c0_register($21, 0)
1543#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1544
1545#define read_c0_diag() __read_32bit_c0_register($22, 0)
1546#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1547
1548/* R10K CP0 Branch Diagnostic register is 64bits wide */
1549#define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1550#define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1551
1552#define read_c0_diag1() __read_32bit_c0_register($22, 1)
1553#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1554
1555#define read_c0_diag2() __read_32bit_c0_register($22, 2)
1556#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1557
1558#define read_c0_diag3() __read_32bit_c0_register($22, 3)
1559#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1560
1561#define read_c0_diag4() __read_32bit_c0_register($22, 4)
1562#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1563
1564#define read_c0_diag5() __read_32bit_c0_register($22, 5)
1565#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1566
1567#define read_c0_debug() __read_32bit_c0_register($23, 0)
1568#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1569
1570#define read_c0_depc() __read_ulong_c0_register($24, 0)
1571#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1572
1573/*
1574 * MIPS32 / MIPS64 performance counters
1575 */
1576#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1577#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1578#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1579#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1580#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1581#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1582#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1583#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1584#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1585#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1586#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1587#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1588#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1589#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1590#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1591#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1592#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1593#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1594#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1595#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1596#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1597#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1598#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1599#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1600
1601#define read_c0_ecc() __read_32bit_c0_register($26, 0)
1602#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1603
1604#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1605#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1606
1607#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1608
1609#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1610#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1611
1612#define read_c0_taglo() __read_32bit_c0_register($28, 0)
1613#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1614
1615#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1616#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1617
1618#define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1619#define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1620
1621#define read_c0_staglo() __read_32bit_c0_register($28, 4)
1622#define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1623
1624#define read_c0_taghi() __read_32bit_c0_register($29, 0)
1625#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1626
1627#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1628#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1629
1630/* MIPSR2 */
1631#define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1632#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1633
1634#define read_c0_intctl() __read_32bit_c0_register($12, 1)
1635#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1636
1637#define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1638#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1639
1640#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1641#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1642
1643#define read_c0_ebase() __read_32bit_c0_register($15, 1)
1644#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1645
1646#define read_c0_ebase_64() __read_64bit_c0_register($15, 1)
1647#define write_c0_ebase_64(val) __write_64bit_c0_register($15, 1, val)
1648
1649#define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
1650#define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
1651
1652/* MIPSR3 */
1653#define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1654#define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1655
1656#define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1657#define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1658
1659#define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1660#define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1661
1662/* Hardware Page Table Walker */
1663#define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1664#define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1665
1666#define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1667#define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1668
1669#define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1670#define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1671
1672#define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1673#define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1674
1675#define read_c0_pgd() __read_64bit_c0_register($9, 7)
1676#define write_c0_pgd(val) __write_64bit_c0_register($9, 7, val)
1677
1678#define read_c0_kpgd() __read_64bit_c0_register($31, 7)
1679#define write_c0_kpgd(val) __write_64bit_c0_register($31, 7, val)
1680
1681/* Cavium OCTEON (cnMIPS) */
1682#define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1683#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1684
1685#define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1686#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1687
1688#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1689#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1690/*
1691 * The cacheerr registers are not standardized. On OCTEON, they are
1692 * 64 bits wide.
1693 */
1694#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1695#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1696
1697#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1698#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1699
1700/* BMIPS3300 */
1701#define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1702#define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1703
1704#define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
1705#define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
1706
1707#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1708#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1709
1710/* BMIPS43xx */
1711#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1712#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1713
1714#define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
1715#define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
1716
1717#define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
1718#define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
1719
1720#define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
1721#define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
1722
1723#define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
1724#define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
1725
1726/* BMIPS5000 */
1727#define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
1728#define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
1729
1730#define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
1731#define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
1732
1733#define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
1734#define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
1735
1736#define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
1737#define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
1738
1739#define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
1740#define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
1741
1742#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
1743#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
1744
1745/*
1746 * Macros to access the guest system control coprocessor
1747 */
1748
1749#ifdef TOOLCHAIN_SUPPORTS_VIRT
1750
1751#define __read_32bit_gc0_register(source, sel) \
1752({ int __res; \
1753 __asm__ __volatile__( \
1754 ".set\tpush\n\t" \
1755 ".set\tmips32r2\n\t" \
1756 ".set\tvirt\n\t" \
1757 "mfgc0\t%0, $%1, %2\n\t" \
1758 ".set\tpop" \
1759 : "=r" (__res) \
1760 : "i" (source), "i" (sel)); \
1761 __res; \
1762})
1763
1764#define __read_64bit_gc0_register(source, sel) \
1765({ unsigned long long __res; \
1766 __asm__ __volatile__( \
1767 ".set\tpush\n\t" \
1768 ".set\tmips64r2\n\t" \
1769 ".set\tvirt\n\t" \
1770 "dmfgc0\t%0, $%1, %2\n\t" \
1771 ".set\tpop" \
1772 : "=r" (__res) \
1773 : "i" (source), "i" (sel)); \
1774 __res; \
1775})
1776
1777#define __write_32bit_gc0_register(register, sel, value) \
1778do { \
1779 __asm__ __volatile__( \
1780 ".set\tpush\n\t" \
1781 ".set\tmips32r2\n\t" \
1782 ".set\tvirt\n\t" \
1783 "mtgc0\t%z0, $%1, %2\n\t" \
1784 ".set\tpop" \
1785 : : "Jr" ((unsigned int)(value)), \
1786 "i" (register), "i" (sel)); \
1787} while (0)
1788
1789#define __write_64bit_gc0_register(register, sel, value) \
1790do { \
1791 __asm__ __volatile__( \
1792 ".set\tpush\n\t" \
1793 ".set\tmips64r2\n\t" \
1794 ".set\tvirt\n\t" \
1795 "dmtgc0\t%z0, $%1, %2\n\t" \
1796 ".set\tpop" \
1797 : : "Jr" (value), \
1798 "i" (register), "i" (sel)); \
1799} while (0)
1800
1801#else /* TOOLCHAIN_SUPPORTS_VIRT */
1802
1803#define __read_32bit_gc0_register(source, sel) \
1804({ int __res; \
1805 __asm__ __volatile__( \
1806 ".set\tpush\n\t" \
1807 ".set\tnoat\n\t" \
1808 "# mfgc0\t$1, $%1, %2\n\t" \
1809 _ASM_INSN_IF_MIPS(0x40610000 | %1 << 11 | %2) \
1810 _ASM_INSN32_IF_MM(0x002004fc | %1 << 16 | %2 << 11) \
1811 "move\t%0, $1\n\t" \
1812 ".set\tpop" \
1813 : "=r" (__res) \
1814 : "i" (source), "i" (sel)); \
1815 __res; \
1816})
1817
1818#define __read_64bit_gc0_register(source, sel) \
1819({ unsigned long long __res; \
1820 __asm__ __volatile__( \
1821 ".set\tpush\n\t" \
1822 ".set\tnoat\n\t" \
1823 "# dmfgc0\t$1, $%1, %2\n\t" \
1824 _ASM_INSN_IF_MIPS(0x40610100 | %1 << 11 | %2) \
1825 _ASM_INSN32_IF_MM(0x582004fc | %1 << 16 | %2 << 11) \
1826 "move\t%0, $1\n\t" \
1827 ".set\tpop" \
1828 : "=r" (__res) \
1829 : "i" (source), "i" (sel)); \
1830 __res; \
1831})
1832
1833#define __write_32bit_gc0_register(register, sel, value) \
1834do { \
1835 __asm__ __volatile__( \
1836 ".set\tpush\n\t" \
1837 ".set\tnoat\n\t" \
1838 "move\t$1, %z0\n\t" \
1839 "# mtgc0\t$1, $%1, %2\n\t" \
1840 _ASM_INSN_IF_MIPS(0x40610200 | %1 << 11 | %2) \
1841 _ASM_INSN32_IF_MM(0x002006fc | %1 << 16 | %2 << 11) \
1842 ".set\tpop" \
1843 : : "Jr" ((unsigned int)(value)), \
1844 "i" (register), "i" (sel)); \
1845} while (0)
1846
1847#define __write_64bit_gc0_register(register, sel, value) \
1848do { \
1849 __asm__ __volatile__( \
1850 ".set\tpush\n\t" \
1851 ".set\tnoat\n\t" \
1852 "move\t$1, %z0\n\t" \
1853 "# dmtgc0\t$1, $%1, %2\n\t" \
1854 _ASM_INSN_IF_MIPS(0x40610300 | %1 << 11 | %2) \
1855 _ASM_INSN32_IF_MM(0x582006fc | %1 << 16 | %2 << 11) \
1856 ".set\tpop" \
1857 : : "Jr" (value), \
1858 "i" (register), "i" (sel)); \
1859} while (0)
1860
1861#endif /* !TOOLCHAIN_SUPPORTS_VIRT */
1862
1863#define __read_ulong_gc0_register(reg, sel) \
1864 ((sizeof(unsigned long) == 4) ? \
1865 (unsigned long) __read_32bit_gc0_register(reg, sel) : \
1866 (unsigned long) __read_64bit_gc0_register(reg, sel))
1867
1868#define __write_ulong_gc0_register(reg, sel, val) \
1869do { \
1870 if (sizeof(unsigned long) == 4) \
1871 __write_32bit_gc0_register(reg, sel, val); \
1872 else \
1873 __write_64bit_gc0_register(reg, sel, val); \
1874} while (0)
1875
1876#define read_gc0_index() __read_32bit_gc0_register(0, 0)
1877#define write_gc0_index(val) __write_32bit_gc0_register(0, 0, val)
1878
1879#define read_gc0_entrylo0() __read_ulong_gc0_register(2, 0)
1880#define write_gc0_entrylo0(val) __write_ulong_gc0_register(2, 0, val)
1881
1882#define read_gc0_entrylo1() __read_ulong_gc0_register(3, 0)
1883#define write_gc0_entrylo1(val) __write_ulong_gc0_register(3, 0, val)
1884
1885#define read_gc0_context() __read_ulong_gc0_register(4, 0)
1886#define write_gc0_context(val) __write_ulong_gc0_register(4, 0, val)
1887
1888#define read_gc0_contextconfig() __read_32bit_gc0_register(4, 1)
1889#define write_gc0_contextconfig(val) __write_32bit_gc0_register(4, 1, val)
1890
1891#define read_gc0_userlocal() __read_ulong_gc0_register(4, 2)
1892#define write_gc0_userlocal(val) __write_ulong_gc0_register(4, 2, val)
1893
1894#define read_gc0_xcontextconfig() __read_ulong_gc0_register(4, 3)
1895#define write_gc0_xcontextconfig(val) __write_ulong_gc0_register(4, 3, val)
1896
1897#define read_gc0_pagemask() __read_32bit_gc0_register(5, 0)
1898#define write_gc0_pagemask(val) __write_32bit_gc0_register(5, 0, val)
1899
1900#define read_gc0_pagegrain() __read_32bit_gc0_register(5, 1)
1901#define write_gc0_pagegrain(val) __write_32bit_gc0_register(5, 1, val)
1902
1903#define read_gc0_segctl0() __read_ulong_gc0_register(5, 2)
1904#define write_gc0_segctl0(val) __write_ulong_gc0_register(5, 2, val)
1905
1906#define read_gc0_segctl1() __read_ulong_gc0_register(5, 3)
1907#define write_gc0_segctl1(val) __write_ulong_gc0_register(5, 3, val)
1908
1909#define read_gc0_segctl2() __read_ulong_gc0_register(5, 4)
1910#define write_gc0_segctl2(val) __write_ulong_gc0_register(5, 4, val)
1911
1912#define read_gc0_pwbase() __read_ulong_gc0_register(5, 5)
1913#define write_gc0_pwbase(val) __write_ulong_gc0_register(5, 5, val)
1914
1915#define read_gc0_pwfield() __read_ulong_gc0_register(5, 6)
1916#define write_gc0_pwfield(val) __write_ulong_gc0_register(5, 6, val)
1917
1918#define read_gc0_pwsize() __read_ulong_gc0_register(5, 7)
1919#define write_gc0_pwsize(val) __write_ulong_gc0_register(5, 7, val)
1920
1921#define read_gc0_wired() __read_32bit_gc0_register(6, 0)
1922#define write_gc0_wired(val) __write_32bit_gc0_register(6, 0, val)
1923
1924#define read_gc0_pwctl() __read_32bit_gc0_register(6, 6)
1925#define write_gc0_pwctl(val) __write_32bit_gc0_register(6, 6, val)
1926
1927#define read_gc0_hwrena() __read_32bit_gc0_register(7, 0)
1928#define write_gc0_hwrena(val) __write_32bit_gc0_register(7, 0, val)
1929
1930#define read_gc0_badvaddr() __read_ulong_gc0_register(8, 0)
1931#define write_gc0_badvaddr(val) __write_ulong_gc0_register(8, 0, val)
1932
1933#define read_gc0_badinstr() __read_32bit_gc0_register(8, 1)
1934#define write_gc0_badinstr(val) __write_32bit_gc0_register(8, 1, val)
1935
1936#define read_gc0_badinstrp() __read_32bit_gc0_register(8, 2)
1937#define write_gc0_badinstrp(val) __write_32bit_gc0_register(8, 2, val)
1938
1939#define read_gc0_count() __read_32bit_gc0_register(9, 0)
1940
1941#define read_gc0_entryhi() __read_ulong_gc0_register(10, 0)
1942#define write_gc0_entryhi(val) __write_ulong_gc0_register(10, 0, val)
1943
1944#define read_gc0_compare() __read_32bit_gc0_register(11, 0)
1945#define write_gc0_compare(val) __write_32bit_gc0_register(11, 0, val)
1946
1947#define read_gc0_status() __read_32bit_gc0_register(12, 0)
1948#define write_gc0_status(val) __write_32bit_gc0_register(12, 0, val)
1949
1950#define read_gc0_intctl() __read_32bit_gc0_register(12, 1)
1951#define write_gc0_intctl(val) __write_32bit_gc0_register(12, 1, val)
1952
1953#define read_gc0_cause() __read_32bit_gc0_register(13, 0)
1954#define write_gc0_cause(val) __write_32bit_gc0_register(13, 0, val)
1955
1956#define read_gc0_epc() __read_ulong_gc0_register(14, 0)
1957#define write_gc0_epc(val) __write_ulong_gc0_register(14, 0, val)
1958
1959#define read_gc0_ebase() __read_32bit_gc0_register(15, 1)
1960#define write_gc0_ebase(val) __write_32bit_gc0_register(15, 1, val)
1961
1962#define read_gc0_ebase_64() __read_64bit_gc0_register(15, 1)
1963#define write_gc0_ebase_64(val) __write_64bit_gc0_register(15, 1, val)
1964
1965#define read_gc0_config() __read_32bit_gc0_register(16, 0)
1966#define read_gc0_config1() __read_32bit_gc0_register(16, 1)
1967#define read_gc0_config2() __read_32bit_gc0_register(16, 2)
1968#define read_gc0_config3() __read_32bit_gc0_register(16, 3)
1969#define read_gc0_config4() __read_32bit_gc0_register(16, 4)
1970#define read_gc0_config5() __read_32bit_gc0_register(16, 5)
1971#define read_gc0_config6() __read_32bit_gc0_register(16, 6)
1972#define read_gc0_config7() __read_32bit_gc0_register(16, 7)
1973#define write_gc0_config(val) __write_32bit_gc0_register(16, 0, val)
1974#define write_gc0_config1(val) __write_32bit_gc0_register(16, 1, val)
1975#define write_gc0_config2(val) __write_32bit_gc0_register(16, 2, val)
1976#define write_gc0_config3(val) __write_32bit_gc0_register(16, 3, val)
1977#define write_gc0_config4(val) __write_32bit_gc0_register(16, 4, val)
1978#define write_gc0_config5(val) __write_32bit_gc0_register(16, 5, val)
1979#define write_gc0_config6(val) __write_32bit_gc0_register(16, 6, val)
1980#define write_gc0_config7(val) __write_32bit_gc0_register(16, 7, val)
1981
1982#define read_gc0_watchlo0() __read_ulong_gc0_register(18, 0)
1983#define read_gc0_watchlo1() __read_ulong_gc0_register(18, 1)
1984#define read_gc0_watchlo2() __read_ulong_gc0_register(18, 2)
1985#define read_gc0_watchlo3() __read_ulong_gc0_register(18, 3)
1986#define read_gc0_watchlo4() __read_ulong_gc0_register(18, 4)
1987#define read_gc0_watchlo5() __read_ulong_gc0_register(18, 5)
1988#define read_gc0_watchlo6() __read_ulong_gc0_register(18, 6)
1989#define read_gc0_watchlo7() __read_ulong_gc0_register(18, 7)
1990#define write_gc0_watchlo0(val) __write_ulong_gc0_register(18, 0, val)
1991#define write_gc0_watchlo1(val) __write_ulong_gc0_register(18, 1, val)
1992#define write_gc0_watchlo2(val) __write_ulong_gc0_register(18, 2, val)
1993#define write_gc0_watchlo3(val) __write_ulong_gc0_register(18, 3, val)
1994#define write_gc0_watchlo4(val) __write_ulong_gc0_register(18, 4, val)
1995#define write_gc0_watchlo5(val) __write_ulong_gc0_register(18, 5, val)
1996#define write_gc0_watchlo6(val) __write_ulong_gc0_register(18, 6, val)
1997#define write_gc0_watchlo7(val) __write_ulong_gc0_register(18, 7, val)
1998
1999#define read_gc0_watchhi0() __read_32bit_gc0_register(19, 0)
2000#define read_gc0_watchhi1() __read_32bit_gc0_register(19, 1)
2001#define read_gc0_watchhi2() __read_32bit_gc0_register(19, 2)
2002#define read_gc0_watchhi3() __read_32bit_gc0_register(19, 3)
2003#define read_gc0_watchhi4() __read_32bit_gc0_register(19, 4)
2004#define read_gc0_watchhi5() __read_32bit_gc0_register(19, 5)
2005#define read_gc0_watchhi6() __read_32bit_gc0_register(19, 6)
2006#define read_gc0_watchhi7() __read_32bit_gc0_register(19, 7)
2007#define write_gc0_watchhi0(val) __write_32bit_gc0_register(19, 0, val)
2008#define write_gc0_watchhi1(val) __write_32bit_gc0_register(19, 1, val)
2009#define write_gc0_watchhi2(val) __write_32bit_gc0_register(19, 2, val)
2010#define write_gc0_watchhi3(val) __write_32bit_gc0_register(19, 3, val)
2011#define write_gc0_watchhi4(val) __write_32bit_gc0_register(19, 4, val)
2012#define write_gc0_watchhi5(val) __write_32bit_gc0_register(19, 5, val)
2013#define write_gc0_watchhi6(val) __write_32bit_gc0_register(19, 6, val)
2014#define write_gc0_watchhi7(val) __write_32bit_gc0_register(19, 7, val)
2015
2016#define read_gc0_xcontext() __read_ulong_gc0_register(20, 0)
2017#define write_gc0_xcontext(val) __write_ulong_gc0_register(20, 0, val)
2018
2019#define read_gc0_perfctrl0() __read_32bit_gc0_register(25, 0)
2020#define write_gc0_perfctrl0(val) __write_32bit_gc0_register(25, 0, val)
2021#define read_gc0_perfcntr0() __read_32bit_gc0_register(25, 1)
2022#define write_gc0_perfcntr0(val) __write_32bit_gc0_register(25, 1, val)
2023#define read_gc0_perfcntr0_64() __read_64bit_gc0_register(25, 1)
2024#define write_gc0_perfcntr0_64(val) __write_64bit_gc0_register(25, 1, val)
2025#define read_gc0_perfctrl1() __read_32bit_gc0_register(25, 2)
2026#define write_gc0_perfctrl1(val) __write_32bit_gc0_register(25, 2, val)
2027#define read_gc0_perfcntr1() __read_32bit_gc0_register(25, 3)
2028#define write_gc0_perfcntr1(val) __write_32bit_gc0_register(25, 3, val)
2029#define read_gc0_perfcntr1_64() __read_64bit_gc0_register(25, 3)
2030#define write_gc0_perfcntr1_64(val) __write_64bit_gc0_register(25, 3, val)
2031#define read_gc0_perfctrl2() __read_32bit_gc0_register(25, 4)
2032#define write_gc0_perfctrl2(val) __write_32bit_gc0_register(25, 4, val)
2033#define read_gc0_perfcntr2() __read_32bit_gc0_register(25, 5)
2034#define write_gc0_perfcntr2(val) __write_32bit_gc0_register(25, 5, val)
2035#define read_gc0_perfcntr2_64() __read_64bit_gc0_register(25, 5)
2036#define write_gc0_perfcntr2_64(val) __write_64bit_gc0_register(25, 5, val)
2037#define read_gc0_perfctrl3() __read_32bit_gc0_register(25, 6)
2038#define write_gc0_perfctrl3(val) __write_32bit_gc0_register(25, 6, val)
2039#define read_gc0_perfcntr3() __read_32bit_gc0_register(25, 7)
2040#define write_gc0_perfcntr3(val) __write_32bit_gc0_register(25, 7, val)
2041#define read_gc0_perfcntr3_64() __read_64bit_gc0_register(25, 7)
2042#define write_gc0_perfcntr3_64(val) __write_64bit_gc0_register(25, 7, val)
2043
2044#define read_gc0_errorepc() __read_ulong_gc0_register(30, 0)
2045#define write_gc0_errorepc(val) __write_ulong_gc0_register(30, 0, val)
2046
2047#define read_gc0_kscratch1() __read_ulong_gc0_register(31, 2)
2048#define read_gc0_kscratch2() __read_ulong_gc0_register(31, 3)
2049#define read_gc0_kscratch3() __read_ulong_gc0_register(31, 4)
2050#define read_gc0_kscratch4() __read_ulong_gc0_register(31, 5)
2051#define read_gc0_kscratch5() __read_ulong_gc0_register(31, 6)
2052#define read_gc0_kscratch6() __read_ulong_gc0_register(31, 7)
2053#define write_gc0_kscratch1(val) __write_ulong_gc0_register(31, 2, val)
2054#define write_gc0_kscratch2(val) __write_ulong_gc0_register(31, 3, val)
2055#define write_gc0_kscratch3(val) __write_ulong_gc0_register(31, 4, val)
2056#define write_gc0_kscratch4(val) __write_ulong_gc0_register(31, 5, val)
2057#define write_gc0_kscratch5(val) __write_ulong_gc0_register(31, 6, val)
2058#define write_gc0_kscratch6(val) __write_ulong_gc0_register(31, 7, val)
2059
2060/*
2061 * Macros to access the floating point coprocessor control registers
2062 */
2063#define _read_32bit_cp1_register(source, gas_hardfloat) \
2064({ \
2065 unsigned int __res; \
2066 \
2067 __asm__ __volatile__( \
2068 " .set push \n" \
2069 " .set reorder \n" \
2070 " # gas fails to assemble cfc1 for some archs, \n" \
2071 " # like Octeon. \n" \
2072 " .set mips1 \n" \
2073 " "STR(gas_hardfloat)" \n" \
2074 " cfc1 %0,"STR(source)" \n" \
2075 " .set pop \n" \
2076 : "=r" (__res)); \
2077 __res; \
2078})
2079
2080#define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
2081do { \
2082 __asm__ __volatile__( \
2083 " .set push \n" \
2084 " .set reorder \n" \
2085 " "STR(gas_hardfloat)" \n" \
2086 " ctc1 %0,"STR(dest)" \n" \
2087 " .set pop \n" \
2088 : : "r" (val)); \
2089} while (0)
2090
2091#ifdef GAS_HAS_SET_HARDFLOAT
2092#define read_32bit_cp1_register(source) \
2093 _read_32bit_cp1_register(source, .set hardfloat)
2094#define write_32bit_cp1_register(dest, val) \
2095 _write_32bit_cp1_register(dest, val, .set hardfloat)
2096#else
2097#define read_32bit_cp1_register(source) \
2098 _read_32bit_cp1_register(source, )
2099#define write_32bit_cp1_register(dest, val) \
2100 _write_32bit_cp1_register(dest, val, )
2101#endif
2102
2103#ifdef HAVE_AS_DSP
2104#define rddsp(mask) \
2105({ \
2106 unsigned int __dspctl; \
2107 \
2108 __asm__ __volatile__( \
2109 " .set push \n" \
2110 " .set dsp \n" \
2111 " rddsp %0, %x1 \n" \
2112 " .set pop \n" \
2113 : "=r" (__dspctl) \
2114 : "i" (mask)); \
2115 __dspctl; \
2116})
2117
2118#define wrdsp(val, mask) \
2119do { \
2120 __asm__ __volatile__( \
2121 " .set push \n" \
2122 " .set dsp \n" \
2123 " wrdsp %0, %x1 \n" \
2124 " .set pop \n" \
2125 : \
2126 : "r" (val), "i" (mask)); \
2127} while (0)
2128
2129#define mflo0() \
2130({ \
2131 long mflo0; \
2132 __asm__( \
2133 " .set push \n" \
2134 " .set dsp \n" \
2135 " mflo %0, $ac0 \n" \
2136 " .set pop \n" \
2137 : "=r" (mflo0)); \
2138 mflo0; \
2139})
2140
2141#define mflo1() \
2142({ \
2143 long mflo1; \
2144 __asm__( \
2145 " .set push \n" \
2146 " .set dsp \n" \
2147 " mflo %0, $ac1 \n" \
2148 " .set pop \n" \
2149 : "=r" (mflo1)); \
2150 mflo1; \
2151})
2152
2153#define mflo2() \
2154({ \
2155 long mflo2; \
2156 __asm__( \
2157 " .set push \n" \
2158 " .set dsp \n" \
2159 " mflo %0, $ac2 \n" \
2160 " .set pop \n" \
2161 : "=r" (mflo2)); \
2162 mflo2; \
2163})
2164
2165#define mflo3() \
2166({ \
2167 long mflo3; \
2168 __asm__( \
2169 " .set push \n" \
2170 " .set dsp \n" \
2171 " mflo %0, $ac3 \n" \
2172 " .set pop \n" \
2173 : "=r" (mflo3)); \
2174 mflo3; \
2175})
2176
2177#define mfhi0() \
2178({ \
2179 long mfhi0; \
2180 __asm__( \
2181 " .set push \n" \
2182 " .set dsp \n" \
2183 " mfhi %0, $ac0 \n" \
2184 " .set pop \n" \
2185 : "=r" (mfhi0)); \
2186 mfhi0; \
2187})
2188
2189#define mfhi1() \
2190({ \
2191 long mfhi1; \
2192 __asm__( \
2193 " .set push \n" \
2194 " .set dsp \n" \
2195 " mfhi %0, $ac1 \n" \
2196 " .set pop \n" \
2197 : "=r" (mfhi1)); \
2198 mfhi1; \
2199})
2200
2201#define mfhi2() \
2202({ \
2203 long mfhi2; \
2204 __asm__( \
2205 " .set push \n" \
2206 " .set dsp \n" \
2207 " mfhi %0, $ac2 \n" \
2208 " .set pop \n" \
2209 : "=r" (mfhi2)); \
2210 mfhi2; \
2211})
2212
2213#define mfhi3() \
2214({ \
2215 long mfhi3; \
2216 __asm__( \
2217 " .set push \n" \
2218 " .set dsp \n" \
2219 " mfhi %0, $ac3 \n" \
2220 " .set pop \n" \
2221 : "=r" (mfhi3)); \
2222 mfhi3; \
2223})
2224
2225
2226#define mtlo0(x) \
2227({ \
2228 __asm__( \
2229 " .set push \n" \
2230 " .set dsp \n" \
2231 " mtlo %0, $ac0 \n" \
2232 " .set pop \n" \
2233 : \
2234 : "r" (x)); \
2235})
2236
2237#define mtlo1(x) \
2238({ \
2239 __asm__( \
2240 " .set push \n" \
2241 " .set dsp \n" \
2242 " mtlo %0, $ac1 \n" \
2243 " .set pop \n" \
2244 : \
2245 : "r" (x)); \
2246})
2247
2248#define mtlo2(x) \
2249({ \
2250 __asm__( \
2251 " .set push \n" \
2252 " .set dsp \n" \
2253 " mtlo %0, $ac2 \n" \
2254 " .set pop \n" \
2255 : \
2256 : "r" (x)); \
2257})
2258
2259#define mtlo3(x) \
2260({ \
2261 __asm__( \
2262 " .set push \n" \
2263 " .set dsp \n" \
2264 " mtlo %0, $ac3 \n" \
2265 " .set pop \n" \
2266 : \
2267 : "r" (x)); \
2268})
2269
2270#define mthi0(x) \
2271({ \
2272 __asm__( \
2273 " .set push \n" \
2274 " .set dsp \n" \
2275 " mthi %0, $ac0 \n" \
2276 " .set pop \n" \
2277 : \
2278 : "r" (x)); \
2279})
2280
2281#define mthi1(x) \
2282({ \
2283 __asm__( \
2284 " .set push \n" \
2285 " .set dsp \n" \
2286 " mthi %0, $ac1 \n" \
2287 " .set pop \n" \
2288 : \
2289 : "r" (x)); \
2290})
2291
2292#define mthi2(x) \
2293({ \
2294 __asm__( \
2295 " .set push \n" \
2296 " .set dsp \n" \
2297 " mthi %0, $ac2 \n" \
2298 " .set pop \n" \
2299 : \
2300 : "r" (x)); \
2301})
2302
2303#define mthi3(x) \
2304({ \
2305 __asm__( \
2306 " .set push \n" \
2307 " .set dsp \n" \
2308 " mthi %0, $ac3 \n" \
2309 " .set pop \n" \
2310 : \
2311 : "r" (x)); \
2312})
2313
2314#else
2315
2316#define rddsp(mask) \
2317({ \
2318 unsigned int __res; \
2319 \
2320 __asm__ __volatile__( \
2321 " .set push \n" \
2322 " .set noat \n" \
2323 " # rddsp $1, %x1 \n" \
2324 _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16)) \
2325 _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14)) \
2326 " move %0, $1 \n" \
2327 " .set pop \n" \
2328 : "=r" (__res) \
2329 : "i" (mask)); \
2330 __res; \
2331})
2332
2333#define wrdsp(val, mask) \
2334do { \
2335 __asm__ __volatile__( \
2336 " .set push \n" \
2337 " .set noat \n" \
2338 " move $1, %0 \n" \
2339 " # wrdsp $1, %x1 \n" \
2340 _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11)) \
2341 _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14)) \
2342 " .set pop \n" \
2343 : \
2344 : "r" (val), "i" (mask)); \
2345} while (0)
2346
2347#define _dsp_mfxxx(ins) \
2348({ \
2349 unsigned long __treg; \
2350 \
2351 __asm__ __volatile__( \
2352 " .set push \n" \
2353 " .set noat \n" \
2354 _ASM_INSN_IF_MIPS(0x00000810 | %X1) \
2355 _ASM_INSN32_IF_MM(0x0001007c | %x1) \
2356 " move %0, $1 \n" \
2357 " .set pop \n" \
2358 : "=r" (__treg) \
2359 : "i" (ins)); \
2360 __treg; \
2361})
2362
2363#define _dsp_mtxxx(val, ins) \
2364do { \
2365 __asm__ __volatile__( \
2366 " .set push \n" \
2367 " .set noat \n" \
2368 " move $1, %0 \n" \
2369 _ASM_INSN_IF_MIPS(0x00200011 | %X1) \
2370 _ASM_INSN32_IF_MM(0x0001207c | %x1) \
2371 " .set pop \n" \
2372 : \
2373 : "r" (val), "i" (ins)); \
2374} while (0)
2375
2376#ifdef CONFIG_CPU_MICROMIPS
2377
2378#define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2379#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2380
2381#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2382#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2383
2384#else /* !CONFIG_CPU_MICROMIPS */
2385
2386#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2387#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2388
2389#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2390#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2391
2392#endif /* CONFIG_CPU_MICROMIPS */
2393
2394#define mflo0() _dsp_mflo(0)
2395#define mflo1() _dsp_mflo(1)
2396#define mflo2() _dsp_mflo(2)
2397#define mflo3() _dsp_mflo(3)
2398
2399#define mfhi0() _dsp_mfhi(0)
2400#define mfhi1() _dsp_mfhi(1)
2401#define mfhi2() _dsp_mfhi(2)
2402#define mfhi3() _dsp_mfhi(3)
2403
2404#define mtlo0(x) _dsp_mtlo(x, 0)
2405#define mtlo1(x) _dsp_mtlo(x, 1)
2406#define mtlo2(x) _dsp_mtlo(x, 2)
2407#define mtlo3(x) _dsp_mtlo(x, 3)
2408
2409#define mthi0(x) _dsp_mthi(x, 0)
2410#define mthi1(x) _dsp_mthi(x, 1)
2411#define mthi2(x) _dsp_mthi(x, 2)
2412#define mthi3(x) _dsp_mthi(x, 3)
2413
2414#endif
2415
2416/*
2417 * TLB operations.
2418 *
2419 * It is responsibility of the caller to take care of any TLB hazards.
2420 */
2421static inline void tlb_probe(void)
2422{
2423 __asm__ __volatile__(
2424 ".set noreorder\n\t"
2425 "tlbp\n\t"
2426 ".set reorder");
2427}
2428
2429static inline void tlb_read(void)
2430{
2431#if MIPS34K_MISSED_ITLB_WAR
2432 int res = 0;
2433
2434 __asm__ __volatile__(
2435 " .set push \n"
2436 " .set noreorder \n"
2437 " .set noat \n"
2438 " .set mips32r2 \n"
2439 " .word 0x41610001 # dvpe $1 \n"
2440 " move %0, $1 \n"
2441 " ehb \n"
2442 " .set pop \n"
2443 : "=r" (res));
2444
2445 instruction_hazard();
2446#endif
2447
2448 __asm__ __volatile__(
2449 ".set noreorder\n\t"
2450 "tlbr\n\t"
2451 ".set reorder");
2452
2453#if MIPS34K_MISSED_ITLB_WAR
2454 if ((res & _ULCAST_(1)))
2455 __asm__ __volatile__(
2456 " .set push \n"
2457 " .set noreorder \n"
2458 " .set noat \n"
2459 " .set mips32r2 \n"
2460 " .word 0x41600021 # evpe \n"
2461 " ehb \n"
2462 " .set pop \n");
2463#endif
2464}
2465
2466static inline void tlb_write_indexed(void)
2467{
2468 __asm__ __volatile__(
2469 ".set noreorder\n\t"
2470 "tlbwi\n\t"
2471 ".set reorder");
2472}
2473
2474static inline void tlb_write_random(void)
2475{
2476 __asm__ __volatile__(
2477 ".set noreorder\n\t"
2478 "tlbwr\n\t"
2479 ".set reorder");
2480}
2481
2482#ifdef TOOLCHAIN_SUPPORTS_VIRT
2483
2484/*
2485 * Guest TLB operations.
2486 *
2487 * It is responsibility of the caller to take care of any TLB hazards.
2488 */
2489static inline void guest_tlb_probe(void)
2490{
2491 __asm__ __volatile__(
2492 ".set push\n\t"
2493 ".set noreorder\n\t"
2494 ".set virt\n\t"
2495 "tlbgp\n\t"
2496 ".set pop");
2497}
2498
2499static inline void guest_tlb_read(void)
2500{
2501 __asm__ __volatile__(
2502 ".set push\n\t"
2503 ".set noreorder\n\t"
2504 ".set virt\n\t"
2505 "tlbgr\n\t"
2506 ".set pop");
2507}
2508
2509static inline void guest_tlb_write_indexed(void)
2510{
2511 __asm__ __volatile__(
2512 ".set push\n\t"
2513 ".set noreorder\n\t"
2514 ".set virt\n\t"
2515 "tlbgwi\n\t"
2516 ".set pop");
2517}
2518
2519static inline void guest_tlb_write_random(void)
2520{
2521 __asm__ __volatile__(
2522 ".set push\n\t"
2523 ".set noreorder\n\t"
2524 ".set virt\n\t"
2525 "tlbgwr\n\t"
2526 ".set pop");
2527}
2528
2529/*
2530 * Guest TLB Invalidate Flush
2531 */
2532static inline void guest_tlbinvf(void)
2533{
2534 __asm__ __volatile__(
2535 ".set push\n\t"
2536 ".set noreorder\n\t"
2537 ".set virt\n\t"
2538 "tlbginvf\n\t"
2539 ".set pop");
2540}
2541
2542#else /* TOOLCHAIN_SUPPORTS_VIRT */
2543
2544/*
2545 * Guest TLB operations.
2546 *
2547 * It is responsibility of the caller to take care of any TLB hazards.
2548 */
2549static inline void guest_tlb_probe(void)
2550{
2551 __asm__ __volatile__(
2552 "# tlbgp\n\t"
2553 _ASM_INSN_IF_MIPS(0x42000010)
2554 _ASM_INSN32_IF_MM(0x0000017c));
2555}
2556
2557static inline void guest_tlb_read(void)
2558{
2559 __asm__ __volatile__(
2560 "# tlbgr\n\t"
2561 _ASM_INSN_IF_MIPS(0x42000009)
2562 _ASM_INSN32_IF_MM(0x0000117c));
2563}
2564
2565static inline void guest_tlb_write_indexed(void)
2566{
2567 __asm__ __volatile__(
2568 "# tlbgwi\n\t"
2569 _ASM_INSN_IF_MIPS(0x4200000a)
2570 _ASM_INSN32_IF_MM(0x0000217c));
2571}
2572
2573static inline void guest_tlb_write_random(void)
2574{
2575 __asm__ __volatile__(
2576 "# tlbgwr\n\t"
2577 _ASM_INSN_IF_MIPS(0x4200000e)
2578 _ASM_INSN32_IF_MM(0x0000317c));
2579}
2580
2581/*
2582 * Guest TLB Invalidate Flush
2583 */
2584static inline void guest_tlbinvf(void)
2585{
2586 __asm__ __volatile__(
2587 "# tlbginvf\n\t"
2588 _ASM_INSN_IF_MIPS(0x4200000c)
2589 _ASM_INSN32_IF_MM(0x0000517c));
2590}
2591
2592#endif /* !TOOLCHAIN_SUPPORTS_VIRT */
2593
2594/*
2595 * Manipulate bits in a register.
2596 */
2597#define __BUILD_SET_COMMON(name) \
2598static inline unsigned int \
2599set_##name(unsigned int set) \
2600{ \
2601 unsigned int res, new; \
2602 \
2603 res = read_##name(); \
2604 new = res | set; \
2605 write_##name(new); \
2606 \
2607 return res; \
2608} \
2609 \
2610static inline unsigned int \
2611clear_##name(unsigned int clear) \
2612{ \
2613 unsigned int res, new; \
2614 \
2615 res = read_##name(); \
2616 new = res & ~clear; \
2617 write_##name(new); \
2618 \
2619 return res; \
2620} \
2621 \
2622static inline unsigned int \
2623change_##name(unsigned int change, unsigned int val) \
2624{ \
2625 unsigned int res, new; \
2626 \
2627 res = read_##name(); \
2628 new = res & ~change; \
2629 new |= (val & change); \
2630 write_##name(new); \
2631 \
2632 return res; \
2633}
2634
2635/*
2636 * Manipulate bits in a c0 register.
2637 */
2638#define __BUILD_SET_C0(name) __BUILD_SET_COMMON(c0_##name)
2639
2640__BUILD_SET_C0(status)
2641__BUILD_SET_C0(cause)
2642__BUILD_SET_C0(config)
2643__BUILD_SET_C0(config5)
2644__BUILD_SET_C0(intcontrol)
2645__BUILD_SET_C0(intctl)
2646__BUILD_SET_C0(srsmap)
2647__BUILD_SET_C0(pagegrain)
2648__BUILD_SET_C0(guestctl0)
2649__BUILD_SET_C0(guestctl0ext)
2650__BUILD_SET_C0(guestctl1)
2651__BUILD_SET_C0(guestctl2)
2652__BUILD_SET_C0(guestctl3)
2653__BUILD_SET_C0(brcm_config_0)
2654__BUILD_SET_C0(brcm_bus_pll)
2655__BUILD_SET_C0(brcm_reset)
2656__BUILD_SET_C0(brcm_cmt_intr)
2657__BUILD_SET_C0(brcm_cmt_ctrl)
2658__BUILD_SET_C0(brcm_config)
2659__BUILD_SET_C0(brcm_mode)
2660
2661/*
2662 * Manipulate bits in a guest c0 register.
2663 */
2664#define __BUILD_SET_GC0(name) __BUILD_SET_COMMON(gc0_##name)
2665
2666__BUILD_SET_GC0(status)
2667__BUILD_SET_GC0(cause)
2668__BUILD_SET_GC0(ebase)
2669
2670/*
2671 * Return low 10 bits of ebase.
2672 * Note that under KVM (MIPSVZ) this returns vcpu id.
2673 */
2674static inline unsigned int get_ebase_cpunum(void)
2675{
2676 return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2677}
2678
2679#endif /* !__ASSEMBLY__ */
2680
2681#endif /* _ASM_MIPSREGS_H */