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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63#include <linux/agp_backend.h>
64#include <linux/atomic.h>
65#include <linux/wait.h>
66#include <linux/list.h>
67#include <linux/kref.h>
68#include <linux/interval_tree.h>
69#include <linux/hashtable.h>
70#include <linux/dma-fence.h>
71
72#ifdef CONFIG_MMU_NOTIFIER
73#include <linux/mmu_notifier.h>
74#endif
75
76#include <drm/ttm/ttm_bo.h>
77#include <drm/ttm/ttm_placement.h>
78#include <drm/ttm/ttm_execbuf_util.h>
79
80#include <drm/drm_gem.h>
81#include <drm/drm_audio_component.h>
82#include <drm/drm_suballoc.h>
83
84#include "radeon_family.h"
85#include "radeon_mode.h"
86#include "radeon_reg.h"
87
88/*
89 * Modules parameters.
90 */
91extern int radeon_no_wb;
92extern int radeon_modeset;
93extern int radeon_dynclks;
94extern int radeon_r4xx_atom;
95extern int radeon_agpmode;
96extern int radeon_vram_limit;
97extern int radeon_gart_size;
98extern int radeon_benchmarking;
99extern int radeon_testing;
100extern int radeon_connector_table;
101extern int radeon_tv;
102extern int radeon_audio;
103extern int radeon_disp_priority;
104extern int radeon_hw_i2c;
105extern int radeon_pcie_gen2;
106extern int radeon_msi;
107extern int radeon_lockup_timeout;
108extern int radeon_fastfb;
109extern int radeon_dpm;
110extern int radeon_aspm;
111extern int radeon_runtime_pm;
112extern int radeon_hard_reset;
113extern int radeon_vm_size;
114extern int radeon_vm_block_size;
115extern int radeon_deep_color;
116extern int radeon_use_pflipirq;
117extern int radeon_bapm;
118extern int radeon_backlight;
119extern int radeon_auxch;
120extern int radeon_uvd;
121extern int radeon_vce;
122extern int radeon_si_support;
123extern int radeon_cik_support;
124
125/*
126 * Copy from radeon_drv.h so we don't have to include both and have conflicting
127 * symbol;
128 */
129#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
130#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
131#define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */
132/* RADEON_IB_POOL_SIZE must be a power of 2 */
133#define RADEON_IB_POOL_SIZE 16
134#define RADEON_DEBUGFS_MAX_COMPONENTS 32
135#define RADEON_BIOS_NUM_SCRATCH 8
136
137/* internal ring indices */
138/* r1xx+ has gfx CP ring */
139#define RADEON_RING_TYPE_GFX_INDEX 0
140
141/* cayman has 2 compute CP rings */
142#define CAYMAN_RING_TYPE_CP1_INDEX 1
143#define CAYMAN_RING_TYPE_CP2_INDEX 2
144
145/* R600+ has an async dma ring */
146#define R600_RING_TYPE_DMA_INDEX 3
147/* cayman add a second async dma ring */
148#define CAYMAN_RING_TYPE_DMA1_INDEX 4
149
150/* R600+ */
151#define R600_RING_TYPE_UVD_INDEX 5
152
153/* TN+ */
154#define TN_RING_TYPE_VCE1_INDEX 6
155#define TN_RING_TYPE_VCE2_INDEX 7
156
157/* max number of rings */
158#define RADEON_NUM_RINGS 8
159
160/* number of hw syncs before falling back on blocking */
161#define RADEON_NUM_SYNCS 4
162
163/* hardcode those limit for now */
164#define RADEON_VA_IB_OFFSET (1 << 20)
165#define RADEON_VA_RESERVED_SIZE (8 << 20)
166#define RADEON_IB_VM_MAX_SIZE (64 << 10)
167
168/* hard reset data */
169#define RADEON_ASIC_RESET_DATA 0x39d5e86b
170
171/* reset flags */
172#define RADEON_RESET_GFX (1 << 0)
173#define RADEON_RESET_COMPUTE (1 << 1)
174#define RADEON_RESET_DMA (1 << 2)
175#define RADEON_RESET_CP (1 << 3)
176#define RADEON_RESET_GRBM (1 << 4)
177#define RADEON_RESET_DMA1 (1 << 5)
178#define RADEON_RESET_RLC (1 << 6)
179#define RADEON_RESET_SEM (1 << 7)
180#define RADEON_RESET_IH (1 << 8)
181#define RADEON_RESET_VMC (1 << 9)
182#define RADEON_RESET_MC (1 << 10)
183#define RADEON_RESET_DISPLAY (1 << 11)
184
185/* CG block flags */
186#define RADEON_CG_BLOCK_GFX (1 << 0)
187#define RADEON_CG_BLOCK_MC (1 << 1)
188#define RADEON_CG_BLOCK_SDMA (1 << 2)
189#define RADEON_CG_BLOCK_UVD (1 << 3)
190#define RADEON_CG_BLOCK_VCE (1 << 4)
191#define RADEON_CG_BLOCK_HDP (1 << 5)
192#define RADEON_CG_BLOCK_BIF (1 << 6)
193
194/* CG flags */
195#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
196#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
197#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
198#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
199#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
200#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
201#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
202#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
203#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
204#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
205#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
206#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
207#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
208#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
209#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
210#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
211#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
212
213/* PG flags */
214#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
215#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
216#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
217#define RADEON_PG_SUPPORT_UVD (1 << 3)
218#define RADEON_PG_SUPPORT_VCE (1 << 4)
219#define RADEON_PG_SUPPORT_CP (1 << 5)
220#define RADEON_PG_SUPPORT_GDS (1 << 6)
221#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
222#define RADEON_PG_SUPPORT_SDMA (1 << 8)
223#define RADEON_PG_SUPPORT_ACP (1 << 9)
224#define RADEON_PG_SUPPORT_SAMU (1 << 10)
225
226/* max cursor sizes (in pixels) */
227#define CURSOR_WIDTH 64
228#define CURSOR_HEIGHT 64
229
230#define CIK_CURSOR_WIDTH 128
231#define CIK_CURSOR_HEIGHT 128
232
233/*
234 * Errata workarounds.
235 */
236enum radeon_pll_errata {
237 CHIP_ERRATA_R300_CG = 0x00000001,
238 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
239 CHIP_ERRATA_PLL_DELAY = 0x00000004
240};
241
242
243struct radeon_device;
244
245
246/*
247 * BIOS.
248 */
249bool radeon_get_bios(struct radeon_device *rdev);
250
251/*
252 * Dummy page
253 */
254struct radeon_dummy_page {
255 uint64_t entry;
256 struct page *page;
257 dma_addr_t addr;
258};
259int radeon_dummy_page_init(struct radeon_device *rdev);
260void radeon_dummy_page_fini(struct radeon_device *rdev);
261
262
263/*
264 * Clocks
265 */
266struct radeon_clock {
267 struct radeon_pll p1pll;
268 struct radeon_pll p2pll;
269 struct radeon_pll dcpll;
270 struct radeon_pll spll;
271 struct radeon_pll mpll;
272 /* 10 Khz units */
273 uint32_t default_mclk;
274 uint32_t default_sclk;
275 uint32_t default_dispclk;
276 uint32_t current_dispclk;
277 uint32_t dp_extclk;
278 uint32_t max_pixel_clock;
279 uint32_t vco_freq;
280};
281
282/*
283 * Power management
284 */
285int radeon_pm_init(struct radeon_device *rdev);
286int radeon_pm_late_init(struct radeon_device *rdev);
287void radeon_pm_fini(struct radeon_device *rdev);
288void radeon_pm_compute_clocks(struct radeon_device *rdev);
289void radeon_pm_suspend(struct radeon_device *rdev);
290void radeon_pm_resume(struct radeon_device *rdev);
291void radeon_combios_get_power_modes(struct radeon_device *rdev);
292void radeon_atombios_get_power_modes(struct radeon_device *rdev);
293int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
294 u8 clock_type,
295 u32 clock,
296 bool strobe_mode,
297 struct atom_clock_dividers *dividers);
298int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
299 u32 clock,
300 bool strobe_mode,
301 struct atom_mpll_param *mpll_param);
302void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
303int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
304 u16 voltage_level, u8 voltage_type,
305 u32 *gpio_value, u32 *gpio_mask);
306void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
307 u32 eng_clock, u32 mem_clock);
308int radeon_atom_get_voltage_step(struct radeon_device *rdev,
309 u8 voltage_type, u16 *voltage_step);
310int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
311 u16 voltage_id, u16 *voltage);
312int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
313 u16 *voltage,
314 u16 leakage_idx);
315int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
316 u16 *leakage_id);
317int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
318 u16 *vddc, u16 *vddci,
319 u16 virtual_voltage_id,
320 u16 vbios_voltage_id);
321int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
322 u16 virtual_voltage_id,
323 u16 *voltage);
324int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
325 u8 voltage_type,
326 u16 nominal_voltage,
327 u16 *true_voltage);
328int radeon_atom_get_min_voltage(struct radeon_device *rdev,
329 u8 voltage_type, u16 *min_voltage);
330int radeon_atom_get_max_voltage(struct radeon_device *rdev,
331 u8 voltage_type, u16 *max_voltage);
332int radeon_atom_get_voltage_table(struct radeon_device *rdev,
333 u8 voltage_type, u8 voltage_mode,
334 struct atom_voltage_table *voltage_table);
335bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
336 u8 voltage_type, u8 voltage_mode);
337int radeon_atom_get_svi2_info(struct radeon_device *rdev,
338 u8 voltage_type,
339 u8 *svd_gpio_id, u8 *svc_gpio_id);
340void radeon_atom_update_memory_dll(struct radeon_device *rdev,
341 u32 mem_clock);
342void radeon_atom_set_ac_timing(struct radeon_device *rdev,
343 u32 mem_clock);
344int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
345 u8 module_index,
346 struct atom_mc_reg_table *reg_table);
347int radeon_atom_get_memory_info(struct radeon_device *rdev,
348 u8 module_index, struct atom_memory_info *mem_info);
349int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
350 bool gddr5, u8 module_index,
351 struct atom_memory_clock_range_table *mclk_range_table);
352int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
353 u16 voltage_id, u16 *voltage);
354void rs690_pm_info(struct radeon_device *rdev);
355extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
356 unsigned *bankh, unsigned *mtaspect,
357 unsigned *tile_split);
358
359/*
360 * Fences.
361 */
362struct radeon_fence_driver {
363 struct radeon_device *rdev;
364 uint32_t scratch_reg;
365 uint64_t gpu_addr;
366 volatile uint32_t *cpu_addr;
367 /* sync_seq is protected by ring emission lock */
368 uint64_t sync_seq[RADEON_NUM_RINGS];
369 atomic64_t last_seq;
370 bool initialized, delayed_irq;
371 struct delayed_work lockup_work;
372};
373
374struct radeon_fence {
375 struct dma_fence base;
376
377 struct radeon_device *rdev;
378 uint64_t seq;
379 /* RB, DMA, etc. */
380 unsigned ring;
381 bool is_vm_update;
382
383 wait_queue_entry_t fence_wake;
384};
385
386int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
387void radeon_fence_driver_init(struct radeon_device *rdev);
388void radeon_fence_driver_fini(struct radeon_device *rdev);
389void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
390int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
391void radeon_fence_process(struct radeon_device *rdev, int ring);
392bool radeon_fence_signaled(struct radeon_fence *fence);
393long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
394int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
395int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
396int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
397int radeon_fence_wait_any(struct radeon_device *rdev,
398 struct radeon_fence **fences,
399 bool intr);
400struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
401void radeon_fence_unref(struct radeon_fence **fence);
402unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
403bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
404void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
405static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
406 struct radeon_fence *b)
407{
408 if (!a) {
409 return b;
410 }
411
412 if (!b) {
413 return a;
414 }
415
416 BUG_ON(a->ring != b->ring);
417
418 if (a->seq > b->seq) {
419 return a;
420 } else {
421 return b;
422 }
423}
424
425static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
426 struct radeon_fence *b)
427{
428 if (!a) {
429 return false;
430 }
431
432 if (!b) {
433 return true;
434 }
435
436 BUG_ON(a->ring != b->ring);
437
438 return a->seq < b->seq;
439}
440
441/*
442 * Tiling registers
443 */
444struct radeon_surface_reg {
445 struct radeon_bo *bo;
446};
447
448#define RADEON_GEM_MAX_SURFACES 8
449
450/*
451 * TTM.
452 */
453struct radeon_mman {
454 struct ttm_device bdev;
455 bool initialized;
456};
457
458struct radeon_bo_list {
459 struct radeon_bo *robj;
460 struct ttm_validate_buffer tv;
461 uint64_t gpu_offset;
462 unsigned preferred_domains;
463 unsigned allowed_domains;
464 uint32_t tiling_flags;
465};
466
467/* bo virtual address in a specific vm */
468struct radeon_bo_va {
469 /* protected by bo being reserved */
470 struct list_head bo_list;
471 uint32_t flags;
472 struct radeon_fence *last_pt_update;
473 unsigned ref_count;
474
475 /* protected by vm mutex */
476 struct interval_tree_node it;
477 struct list_head vm_status;
478
479 /* constant after initialization */
480 struct radeon_vm *vm;
481 struct radeon_bo *bo;
482};
483
484struct radeon_bo {
485 /* Protected by gem.mutex */
486 struct list_head list;
487 /* Protected by tbo.reserved */
488 u32 initial_domain;
489 struct ttm_place placements[4];
490 struct ttm_placement placement;
491 struct ttm_buffer_object tbo;
492 struct ttm_bo_kmap_obj kmap;
493 u32 flags;
494 void *kptr;
495 u32 tiling_flags;
496 u32 pitch;
497 int surface_reg;
498 unsigned prime_shared_count;
499 /* list of all virtual address to which this bo
500 * is associated to
501 */
502 struct list_head va;
503 /* Constant after initialization */
504 struct radeon_device *rdev;
505
506 pid_t pid;
507
508#ifdef CONFIG_MMU_NOTIFIER
509 struct mmu_interval_notifier notifier;
510#endif
511};
512#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, tbo.base)
513
514struct radeon_sa_manager {
515 struct drm_suballoc_manager base;
516 struct radeon_bo *bo;
517 uint64_t gpu_addr;
518 void *cpu_ptr;
519 u32 domain;
520};
521
522/*
523 * GEM objects.
524 */
525struct radeon_gem {
526 struct mutex mutex;
527 struct list_head objects;
528};
529
530extern const struct drm_gem_object_funcs radeon_gem_object_funcs;
531
532int radeon_align_pitch(struct radeon_device *rdev, int width, int cpp, bool tiled);
533
534int radeon_gem_init(struct radeon_device *rdev);
535void radeon_gem_fini(struct radeon_device *rdev);
536int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
537 int alignment, int initial_domain,
538 u32 flags, bool kernel,
539 struct drm_gem_object **obj);
540
541int radeon_mode_dumb_create(struct drm_file *file_priv,
542 struct drm_device *dev,
543 struct drm_mode_create_dumb *args);
544int radeon_mode_dumb_mmap(struct drm_file *filp,
545 struct drm_device *dev,
546 uint32_t handle, uint64_t *offset_p);
547
548/*
549 * Semaphores.
550 */
551struct radeon_semaphore {
552 struct drm_suballoc *sa_bo;
553 signed waiters;
554 uint64_t gpu_addr;
555};
556
557int radeon_semaphore_create(struct radeon_device *rdev,
558 struct radeon_semaphore **semaphore);
559bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
560 struct radeon_semaphore *semaphore);
561bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
562 struct radeon_semaphore *semaphore);
563void radeon_semaphore_free(struct radeon_device *rdev,
564 struct radeon_semaphore **semaphore,
565 struct radeon_fence *fence);
566
567/*
568 * Synchronization
569 */
570struct radeon_sync {
571 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
572 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
573 struct radeon_fence *last_vm_update;
574};
575
576void radeon_sync_create(struct radeon_sync *sync);
577void radeon_sync_fence(struct radeon_sync *sync,
578 struct radeon_fence *fence);
579int radeon_sync_resv(struct radeon_device *rdev,
580 struct radeon_sync *sync,
581 struct dma_resv *resv,
582 bool shared);
583int radeon_sync_rings(struct radeon_device *rdev,
584 struct radeon_sync *sync,
585 int waiting_ring);
586void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
587 struct radeon_fence *fence);
588
589/*
590 * GART structures, functions & helpers
591 */
592struct radeon_mc;
593
594#define RADEON_GPU_PAGE_SIZE 4096
595#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
596#define RADEON_GPU_PAGE_SHIFT 12
597#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
598
599#define RADEON_GART_PAGE_DUMMY 0
600#define RADEON_GART_PAGE_VALID (1 << 0)
601#define RADEON_GART_PAGE_READ (1 << 1)
602#define RADEON_GART_PAGE_WRITE (1 << 2)
603#define RADEON_GART_PAGE_SNOOP (1 << 3)
604
605struct radeon_gart {
606 dma_addr_t table_addr;
607 struct radeon_bo *robj;
608 void *ptr;
609 unsigned num_gpu_pages;
610 unsigned num_cpu_pages;
611 unsigned table_size;
612 struct page **pages;
613 uint64_t *pages_entry;
614 bool ready;
615};
616
617int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
618void radeon_gart_table_ram_free(struct radeon_device *rdev);
619int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
620void radeon_gart_table_vram_free(struct radeon_device *rdev);
621int radeon_gart_table_vram_pin(struct radeon_device *rdev);
622void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
623int radeon_gart_init(struct radeon_device *rdev);
624void radeon_gart_fini(struct radeon_device *rdev);
625void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
626 int pages);
627int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
628 int pages, struct page **pagelist,
629 dma_addr_t *dma_addr, uint32_t flags);
630
631
632/*
633 * GPU MC structures, functions & helpers
634 */
635struct radeon_mc {
636 resource_size_t aper_size;
637 resource_size_t aper_base;
638 resource_size_t agp_base;
639 /* for some chips with <= 32MB we need to lie
640 * about vram size near mc fb location */
641 u64 mc_vram_size;
642 u64 visible_vram_size;
643 u64 gtt_size;
644 u64 gtt_start;
645 u64 gtt_end;
646 u64 vram_start;
647 u64 vram_end;
648 unsigned vram_width;
649 u64 real_vram_size;
650 int vram_mtrr;
651 bool vram_is_ddr;
652 bool igp_sideport_enabled;
653 u64 gtt_base_align;
654 u64 mc_mask;
655};
656
657bool radeon_combios_sideport_present(struct radeon_device *rdev);
658bool radeon_atombios_sideport_present(struct radeon_device *rdev);
659
660/*
661 * GPU scratch registers structures, functions & helpers
662 */
663struct radeon_scratch {
664 unsigned num_reg;
665 uint32_t reg_base;
666 bool free[32];
667 uint32_t reg[32];
668};
669
670int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
671void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
672
673/*
674 * GPU doorbell structures, functions & helpers
675 */
676#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
677
678struct radeon_doorbell {
679 /* doorbell mmio */
680 resource_size_t base;
681 resource_size_t size;
682 u32 __iomem *ptr;
683 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
684 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
685};
686
687int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
688void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
689
690/*
691 * IRQS.
692 */
693
694struct radeon_flip_work {
695 struct work_struct flip_work;
696 struct work_struct unpin_work;
697 struct radeon_device *rdev;
698 int crtc_id;
699 u32 target_vblank;
700 uint64_t base;
701 struct drm_pending_vblank_event *event;
702 struct radeon_bo *old_rbo;
703 struct dma_fence *fence;
704 bool async;
705};
706
707struct r500_irq_stat_regs {
708 u32 disp_int;
709 u32 hdmi0_status;
710};
711
712struct r600_irq_stat_regs {
713 u32 disp_int;
714 u32 disp_int_cont;
715 u32 disp_int_cont2;
716 u32 d1grph_int;
717 u32 d2grph_int;
718 u32 hdmi0_status;
719 u32 hdmi1_status;
720};
721
722struct evergreen_irq_stat_regs {
723 u32 disp_int[6];
724 u32 grph_int[6];
725 u32 afmt_status[6];
726};
727
728struct cik_irq_stat_regs {
729 u32 disp_int;
730 u32 disp_int_cont;
731 u32 disp_int_cont2;
732 u32 disp_int_cont3;
733 u32 disp_int_cont4;
734 u32 disp_int_cont5;
735 u32 disp_int_cont6;
736 u32 d1grph_int;
737 u32 d2grph_int;
738 u32 d3grph_int;
739 u32 d4grph_int;
740 u32 d5grph_int;
741 u32 d6grph_int;
742};
743
744union radeon_irq_stat_regs {
745 struct r500_irq_stat_regs r500;
746 struct r600_irq_stat_regs r600;
747 struct evergreen_irq_stat_regs evergreen;
748 struct cik_irq_stat_regs cik;
749};
750
751struct radeon_irq {
752 bool installed;
753 spinlock_t lock;
754 atomic_t ring_int[RADEON_NUM_RINGS];
755 bool crtc_vblank_int[RADEON_MAX_CRTCS];
756 atomic_t pflip[RADEON_MAX_CRTCS];
757 wait_queue_head_t vblank_queue;
758 bool hpd[RADEON_MAX_HPD_PINS];
759 bool afmt[RADEON_MAX_AFMT_BLOCKS];
760 union radeon_irq_stat_regs stat_regs;
761 bool dpm_thermal;
762};
763
764int radeon_irq_kms_init(struct radeon_device *rdev);
765void radeon_irq_kms_fini(struct radeon_device *rdev);
766void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
767bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
768void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
769void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
770void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
771void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
772void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
773void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
774void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
775
776/*
777 * CP & rings.
778 */
779
780struct radeon_ib {
781 struct drm_suballoc *sa_bo;
782 uint32_t length_dw;
783 uint64_t gpu_addr;
784 uint32_t *ptr;
785 int ring;
786 struct radeon_fence *fence;
787 struct radeon_vm *vm;
788 bool is_const_ib;
789 struct radeon_sync sync;
790};
791
792struct radeon_ring {
793 struct radeon_device *rdev;
794 struct radeon_bo *ring_obj;
795 volatile uint32_t *ring;
796 unsigned rptr_offs;
797 unsigned rptr_save_reg;
798 u64 next_rptr_gpu_addr;
799 volatile u32 *next_rptr_cpu_addr;
800 unsigned wptr;
801 unsigned wptr_old;
802 unsigned ring_size;
803 unsigned ring_free_dw;
804 int count_dw;
805 atomic_t last_rptr;
806 atomic64_t last_activity;
807 uint64_t gpu_addr;
808 uint32_t align_mask;
809 uint32_t ptr_mask;
810 bool ready;
811 u32 nop;
812 u32 idx;
813 u64 last_semaphore_signal_addr;
814 u64 last_semaphore_wait_addr;
815 /* for CIK queues */
816 u32 me;
817 u32 pipe;
818 u32 queue;
819 struct radeon_bo *mqd_obj;
820 u32 doorbell_index;
821 unsigned wptr_offs;
822};
823
824struct radeon_mec {
825 struct radeon_bo *hpd_eop_obj;
826 u64 hpd_eop_gpu_addr;
827 u32 num_pipe;
828 u32 num_mec;
829 u32 num_queue;
830};
831
832/*
833 * VM
834 */
835
836/* maximum number of VMIDs */
837#define RADEON_NUM_VM 16
838
839/* number of entries in page table */
840#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
841
842/* PTBs (Page Table Blocks) need to be aligned to 32K */
843#define RADEON_VM_PTB_ALIGN_SIZE 32768
844#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
845#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
846
847#define R600_PTE_VALID (1 << 0)
848#define R600_PTE_SYSTEM (1 << 1)
849#define R600_PTE_SNOOPED (1 << 2)
850#define R600_PTE_READABLE (1 << 5)
851#define R600_PTE_WRITEABLE (1 << 6)
852
853/* PTE (Page Table Entry) fragment field for different page sizes */
854#define R600_PTE_FRAG_4KB (0 << 7)
855#define R600_PTE_FRAG_64KB (4 << 7)
856#define R600_PTE_FRAG_256KB (6 << 7)
857
858/* flags needed to be set so we can copy directly from the GART table */
859#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
860 R600_PTE_SYSTEM | R600_PTE_VALID )
861
862struct radeon_vm_pt {
863 struct radeon_bo *bo;
864 uint64_t addr;
865};
866
867struct radeon_vm_id {
868 unsigned id;
869 uint64_t pd_gpu_addr;
870 /* last flushed PD/PT update */
871 struct radeon_fence *flushed_updates;
872 /* last use of vmid */
873 struct radeon_fence *last_id_use;
874};
875
876struct radeon_vm {
877 struct mutex mutex;
878
879 struct rb_root_cached va;
880
881 /* protecting invalidated and freed */
882 spinlock_t status_lock;
883
884 /* BOs moved, but not yet updated in the PT */
885 struct list_head invalidated;
886
887 /* BOs freed, but not yet updated in the PT */
888 struct list_head freed;
889
890 /* BOs cleared in the PT */
891 struct list_head cleared;
892
893 /* contains the page directory */
894 struct radeon_bo *page_directory;
895 unsigned max_pde_used;
896
897 /* array of page tables, one for each page directory entry */
898 struct radeon_vm_pt *page_tables;
899
900 struct radeon_bo_va *ib_bo_va;
901
902 /* for id and flush management per ring */
903 struct radeon_vm_id ids[RADEON_NUM_RINGS];
904};
905
906struct radeon_vm_manager {
907 struct radeon_fence *active[RADEON_NUM_VM];
908 uint32_t max_pfn;
909 /* number of VMIDs */
910 unsigned nvm;
911 /* vram base address for page table entry */
912 u64 vram_base_offset;
913 /* is vm enabled? */
914 bool enabled;
915 /* for hw to save the PD addr on suspend/resume */
916 uint32_t saved_table_addr[RADEON_NUM_VM];
917};
918
919/*
920 * file private structure
921 */
922struct radeon_fpriv {
923 struct radeon_vm vm;
924};
925
926/*
927 * R6xx+ IH ring
928 */
929struct r600_ih {
930 struct radeon_bo *ring_obj;
931 volatile uint32_t *ring;
932 unsigned rptr;
933 unsigned ring_size;
934 uint64_t gpu_addr;
935 uint32_t ptr_mask;
936 atomic_t lock;
937 bool enabled;
938};
939
940/*
941 * RLC stuff
942 */
943#include "clearstate_defs.h"
944
945struct radeon_rlc {
946 /* for power gating */
947 struct radeon_bo *save_restore_obj;
948 uint64_t save_restore_gpu_addr;
949 volatile uint32_t *sr_ptr;
950 const u32 *reg_list;
951 u32 reg_list_size;
952 /* for clear state */
953 struct radeon_bo *clear_state_obj;
954 uint64_t clear_state_gpu_addr;
955 volatile uint32_t *cs_ptr;
956 const struct cs_section_def *cs_data;
957 u32 clear_state_size;
958 /* for cp tables */
959 struct radeon_bo *cp_table_obj;
960 uint64_t cp_table_gpu_addr;
961 volatile uint32_t *cp_table_ptr;
962 u32 cp_table_size;
963};
964
965int radeon_ib_get(struct radeon_device *rdev, int ring,
966 struct radeon_ib *ib, struct radeon_vm *vm,
967 unsigned size);
968void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
969int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
970 struct radeon_ib *const_ib, bool hdp_flush);
971int radeon_ib_pool_init(struct radeon_device *rdev);
972void radeon_ib_pool_fini(struct radeon_device *rdev);
973int radeon_ib_ring_tests(struct radeon_device *rdev);
974/* Ring access between begin & end cannot sleep */
975bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
976 struct radeon_ring *ring);
977void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
978int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
979int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
980void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
981 bool hdp_flush);
982void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
983 bool hdp_flush);
984void radeon_ring_undo(struct radeon_ring *ring);
985void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
986int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
987void radeon_ring_lockup_update(struct radeon_device *rdev,
988 struct radeon_ring *ring);
989bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
990unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
991 uint32_t **data);
992int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
993 unsigned size, uint32_t *data);
994int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
995 unsigned rptr_offs, u32 nop);
996void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
997
998
999/* r600 async dma */
1000void r600_dma_stop(struct radeon_device *rdev);
1001int r600_dma_resume(struct radeon_device *rdev);
1002void r600_dma_fini(struct radeon_device *rdev);
1003
1004void cayman_dma_stop(struct radeon_device *rdev);
1005int cayman_dma_resume(struct radeon_device *rdev);
1006void cayman_dma_fini(struct radeon_device *rdev);
1007
1008/*
1009 * CS.
1010 */
1011struct radeon_cs_chunk {
1012 uint32_t length_dw;
1013 uint32_t *kdata;
1014 void __user *user_ptr;
1015};
1016
1017struct radeon_cs_parser {
1018 struct device *dev;
1019 struct radeon_device *rdev;
1020 struct drm_file *filp;
1021 /* chunks */
1022 unsigned nchunks;
1023 struct radeon_cs_chunk *chunks;
1024 uint64_t *chunks_array;
1025 /* IB */
1026 unsigned idx;
1027 /* relocations */
1028 unsigned nrelocs;
1029 struct radeon_bo_list *relocs;
1030 struct radeon_bo_list *vm_bos;
1031 struct list_head validated;
1032 unsigned dma_reloc_idx;
1033 /* indices of various chunks */
1034 struct radeon_cs_chunk *chunk_ib;
1035 struct radeon_cs_chunk *chunk_relocs;
1036 struct radeon_cs_chunk *chunk_flags;
1037 struct radeon_cs_chunk *chunk_const_ib;
1038 struct radeon_ib ib;
1039 struct radeon_ib const_ib;
1040 void *track;
1041 unsigned family;
1042 int parser_error;
1043 u32 cs_flags;
1044 u32 ring;
1045 s32 priority;
1046 struct ww_acquire_ctx ticket;
1047};
1048
1049static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1050{
1051 struct radeon_cs_chunk *ibc = p->chunk_ib;
1052
1053 if (ibc->kdata)
1054 return ibc->kdata[idx];
1055 return p->ib.ptr[idx];
1056}
1057
1058
1059struct radeon_cs_packet {
1060 unsigned idx;
1061 unsigned type;
1062 unsigned reg;
1063 unsigned opcode;
1064 int count;
1065 unsigned one_reg_wr;
1066};
1067
1068typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1069 struct radeon_cs_packet *pkt,
1070 unsigned idx, unsigned reg);
1071
1072/*
1073 * AGP
1074 */
1075
1076struct radeon_agp_mode {
1077 unsigned long mode; /**< AGP mode */
1078};
1079
1080struct radeon_agp_info {
1081 int agp_version_major;
1082 int agp_version_minor;
1083 unsigned long mode;
1084 unsigned long aperture_base; /* physical address */
1085 unsigned long aperture_size; /* bytes */
1086 unsigned long memory_allowed; /* bytes */
1087 unsigned long memory_used;
1088
1089 /* PCI information */
1090 unsigned short id_vendor;
1091 unsigned short id_device;
1092};
1093
1094struct radeon_agp_head {
1095 struct agp_kern_info agp_info;
1096 struct list_head memory;
1097 unsigned long mode;
1098 struct agp_bridge_data *bridge;
1099 int enabled;
1100 int acquired;
1101 unsigned long base;
1102 int agp_mtrr;
1103 int cant_use_aperture;
1104 unsigned long page_mask;
1105};
1106
1107#if IS_ENABLED(CONFIG_AGP)
1108struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev);
1109#else
1110static inline struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev)
1111{
1112 return NULL;
1113}
1114#endif
1115int radeon_agp_init(struct radeon_device *rdev);
1116void radeon_agp_resume(struct radeon_device *rdev);
1117void radeon_agp_suspend(struct radeon_device *rdev);
1118void radeon_agp_fini(struct radeon_device *rdev);
1119
1120
1121/*
1122 * Writeback
1123 */
1124struct radeon_wb {
1125 struct radeon_bo *wb_obj;
1126 volatile uint32_t *wb;
1127 uint64_t gpu_addr;
1128 bool enabled;
1129 bool use_event;
1130};
1131
1132#define RADEON_WB_SCRATCH_OFFSET 0
1133#define RADEON_WB_RING0_NEXT_RPTR 256
1134#define RADEON_WB_CP_RPTR_OFFSET 1024
1135#define RADEON_WB_CP1_RPTR_OFFSET 1280
1136#define RADEON_WB_CP2_RPTR_OFFSET 1536
1137#define R600_WB_DMA_RPTR_OFFSET 1792
1138#define R600_WB_IH_WPTR_OFFSET 2048
1139#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1140#define R600_WB_EVENT_OFFSET 3072
1141#define CIK_WB_CP1_WPTR_OFFSET 3328
1142#define CIK_WB_CP2_WPTR_OFFSET 3584
1143#define R600_WB_DMA_RING_TEST_OFFSET 3588
1144#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1145
1146/**
1147 * struct radeon_pm - power management datas
1148 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1149 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1150 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1151 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1152 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1153 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1154 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1155 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1156 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1157 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1158 * @needed_bandwidth: current bandwidth needs
1159 *
1160 * It keeps track of various data needed to take powermanagement decision.
1161 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1162 * Equation between gpu/memory clock and available bandwidth is hw dependent
1163 * (type of memory, bus size, efficiency, ...)
1164 */
1165
1166enum radeon_pm_method {
1167 PM_METHOD_PROFILE,
1168 PM_METHOD_DYNPM,
1169 PM_METHOD_DPM,
1170};
1171
1172enum radeon_dynpm_state {
1173 DYNPM_STATE_DISABLED,
1174 DYNPM_STATE_MINIMUM,
1175 DYNPM_STATE_PAUSED,
1176 DYNPM_STATE_ACTIVE,
1177 DYNPM_STATE_SUSPENDED,
1178};
1179enum radeon_dynpm_action {
1180 DYNPM_ACTION_NONE,
1181 DYNPM_ACTION_MINIMUM,
1182 DYNPM_ACTION_DOWNCLOCK,
1183 DYNPM_ACTION_UPCLOCK,
1184 DYNPM_ACTION_DEFAULT
1185};
1186
1187enum radeon_voltage_type {
1188 VOLTAGE_NONE = 0,
1189 VOLTAGE_GPIO,
1190 VOLTAGE_VDDC,
1191 VOLTAGE_SW
1192};
1193
1194enum radeon_pm_state_type {
1195 /* not used for dpm */
1196 POWER_STATE_TYPE_DEFAULT,
1197 POWER_STATE_TYPE_POWERSAVE,
1198 /* user selectable states */
1199 POWER_STATE_TYPE_BATTERY,
1200 POWER_STATE_TYPE_BALANCED,
1201 POWER_STATE_TYPE_PERFORMANCE,
1202 /* internal states */
1203 POWER_STATE_TYPE_INTERNAL_UVD,
1204 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1205 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1206 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1207 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1208 POWER_STATE_TYPE_INTERNAL_BOOT,
1209 POWER_STATE_TYPE_INTERNAL_THERMAL,
1210 POWER_STATE_TYPE_INTERNAL_ACPI,
1211 POWER_STATE_TYPE_INTERNAL_ULV,
1212 POWER_STATE_TYPE_INTERNAL_3DPERF,
1213};
1214
1215enum radeon_pm_profile_type {
1216 PM_PROFILE_DEFAULT,
1217 PM_PROFILE_AUTO,
1218 PM_PROFILE_LOW,
1219 PM_PROFILE_MID,
1220 PM_PROFILE_HIGH,
1221};
1222
1223#define PM_PROFILE_DEFAULT_IDX 0
1224#define PM_PROFILE_LOW_SH_IDX 1
1225#define PM_PROFILE_MID_SH_IDX 2
1226#define PM_PROFILE_HIGH_SH_IDX 3
1227#define PM_PROFILE_LOW_MH_IDX 4
1228#define PM_PROFILE_MID_MH_IDX 5
1229#define PM_PROFILE_HIGH_MH_IDX 6
1230#define PM_PROFILE_MAX 7
1231
1232struct radeon_pm_profile {
1233 int dpms_off_ps_idx;
1234 int dpms_on_ps_idx;
1235 int dpms_off_cm_idx;
1236 int dpms_on_cm_idx;
1237};
1238
1239enum radeon_int_thermal_type {
1240 THERMAL_TYPE_NONE,
1241 THERMAL_TYPE_EXTERNAL,
1242 THERMAL_TYPE_EXTERNAL_GPIO,
1243 THERMAL_TYPE_RV6XX,
1244 THERMAL_TYPE_RV770,
1245 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1246 THERMAL_TYPE_EVERGREEN,
1247 THERMAL_TYPE_SUMO,
1248 THERMAL_TYPE_NI,
1249 THERMAL_TYPE_SI,
1250 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1251 THERMAL_TYPE_CI,
1252 THERMAL_TYPE_KV,
1253};
1254
1255struct radeon_voltage {
1256 enum radeon_voltage_type type;
1257 /* gpio voltage */
1258 struct radeon_gpio_rec gpio;
1259 u32 delay; /* delay in usec from voltage drop to sclk change */
1260 bool active_high; /* voltage drop is active when bit is high */
1261 /* VDDC voltage */
1262 u8 vddc_id; /* index into vddc voltage table */
1263 u8 vddci_id; /* index into vddci voltage table */
1264 bool vddci_enabled;
1265 /* r6xx+ sw */
1266 u16 voltage;
1267 /* evergreen+ vddci */
1268 u16 vddci;
1269};
1270
1271/* clock mode flags */
1272#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1273
1274struct radeon_pm_clock_info {
1275 /* memory clock */
1276 u32 mclk;
1277 /* engine clock */
1278 u32 sclk;
1279 /* voltage info */
1280 struct radeon_voltage voltage;
1281 /* standardized clock flags */
1282 u32 flags;
1283};
1284
1285/* state flags */
1286#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1287
1288struct radeon_power_state {
1289 enum radeon_pm_state_type type;
1290 struct radeon_pm_clock_info *clock_info;
1291 /* number of valid clock modes in this power state */
1292 int num_clock_modes;
1293 struct radeon_pm_clock_info *default_clock_mode;
1294 /* standardized state flags */
1295 u32 flags;
1296 u32 misc; /* vbios specific flags */
1297 u32 misc2; /* vbios specific flags */
1298 int pcie_lanes; /* pcie lanes */
1299};
1300
1301/*
1302 * Some modes are overclocked by very low value, accept them
1303 */
1304#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1305
1306enum radeon_dpm_auto_throttle_src {
1307 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1308 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1309};
1310
1311enum radeon_dpm_event_src {
1312 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1313 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1314 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1315 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1316 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1317};
1318
1319#define RADEON_MAX_VCE_LEVELS 6
1320
1321enum radeon_vce_level {
1322 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1323 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1324 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1325 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1326 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1327 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1328};
1329
1330struct radeon_ps {
1331 u32 caps; /* vbios flags */
1332 u32 class; /* vbios flags */
1333 u32 class2; /* vbios flags */
1334 /* UVD clocks */
1335 u32 vclk;
1336 u32 dclk;
1337 /* VCE clocks */
1338 u32 evclk;
1339 u32 ecclk;
1340 bool vce_active;
1341 enum radeon_vce_level vce_level;
1342 /* asic priv */
1343 void *ps_priv;
1344};
1345
1346struct radeon_dpm_thermal {
1347 /* thermal interrupt work */
1348 struct work_struct work;
1349 /* low temperature threshold */
1350 int min_temp;
1351 /* high temperature threshold */
1352 int max_temp;
1353 /* was interrupt low to high or high to low */
1354 bool high_to_low;
1355};
1356
1357enum radeon_clk_action {
1358 RADEON_SCLK_UP = 1,
1359 RADEON_SCLK_DOWN
1360};
1361
1362struct radeon_blacklist_clocks {
1363 u32 sclk;
1364 u32 mclk;
1365 enum radeon_clk_action action;
1366};
1367
1368struct radeon_clock_and_voltage_limits {
1369 u32 sclk;
1370 u32 mclk;
1371 u16 vddc;
1372 u16 vddci;
1373};
1374
1375struct radeon_clock_array {
1376 u32 count;
1377 u32 *values;
1378};
1379
1380struct radeon_clock_voltage_dependency_entry {
1381 u32 clk;
1382 u16 v;
1383};
1384
1385struct radeon_clock_voltage_dependency_table {
1386 u32 count;
1387 struct radeon_clock_voltage_dependency_entry *entries;
1388};
1389
1390union radeon_cac_leakage_entry {
1391 struct {
1392 u16 vddc;
1393 u32 leakage;
1394 };
1395 struct {
1396 u16 vddc1;
1397 u16 vddc2;
1398 u16 vddc3;
1399 };
1400};
1401
1402struct radeon_cac_leakage_table {
1403 u32 count;
1404 union radeon_cac_leakage_entry *entries;
1405};
1406
1407struct radeon_phase_shedding_limits_entry {
1408 u16 voltage;
1409 u32 sclk;
1410 u32 mclk;
1411};
1412
1413struct radeon_phase_shedding_limits_table {
1414 u32 count;
1415 struct radeon_phase_shedding_limits_entry *entries;
1416};
1417
1418struct radeon_uvd_clock_voltage_dependency_entry {
1419 u32 vclk;
1420 u32 dclk;
1421 u16 v;
1422};
1423
1424struct radeon_uvd_clock_voltage_dependency_table {
1425 u8 count;
1426 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1427};
1428
1429struct radeon_vce_clock_voltage_dependency_entry {
1430 u32 ecclk;
1431 u32 evclk;
1432 u16 v;
1433};
1434
1435struct radeon_vce_clock_voltage_dependency_table {
1436 u8 count;
1437 struct radeon_vce_clock_voltage_dependency_entry *entries;
1438};
1439
1440struct radeon_ppm_table {
1441 u8 ppm_design;
1442 u16 cpu_core_number;
1443 u32 platform_tdp;
1444 u32 small_ac_platform_tdp;
1445 u32 platform_tdc;
1446 u32 small_ac_platform_tdc;
1447 u32 apu_tdp;
1448 u32 dgpu_tdp;
1449 u32 dgpu_ulv_power;
1450 u32 tj_max;
1451};
1452
1453struct radeon_cac_tdp_table {
1454 u16 tdp;
1455 u16 configurable_tdp;
1456 u16 tdc;
1457 u16 battery_power_limit;
1458 u16 small_power_limit;
1459 u16 low_cac_leakage;
1460 u16 high_cac_leakage;
1461 u16 maximum_power_delivery_limit;
1462};
1463
1464struct radeon_dpm_dynamic_state {
1465 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1466 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1467 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1468 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1469 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1470 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1471 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1472 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1473 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1474 struct radeon_clock_array valid_sclk_values;
1475 struct radeon_clock_array valid_mclk_values;
1476 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1477 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1478 u32 mclk_sclk_ratio;
1479 u32 sclk_mclk_delta;
1480 u16 vddc_vddci_delta;
1481 u16 min_vddc_for_pcie_gen2;
1482 struct radeon_cac_leakage_table cac_leakage_table;
1483 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1484 struct radeon_ppm_table *ppm_table;
1485 struct radeon_cac_tdp_table *cac_tdp_table;
1486};
1487
1488struct radeon_dpm_fan {
1489 u16 t_min;
1490 u16 t_med;
1491 u16 t_high;
1492 u16 pwm_min;
1493 u16 pwm_med;
1494 u16 pwm_high;
1495 u8 t_hyst;
1496 u32 cycle_delay;
1497 u16 t_max;
1498 u8 control_mode;
1499 u16 default_max_fan_pwm;
1500 u16 default_fan_output_sensitivity;
1501 u16 fan_output_sensitivity;
1502 bool ucode_fan_control;
1503};
1504
1505enum radeon_pcie_gen {
1506 RADEON_PCIE_GEN1 = 0,
1507 RADEON_PCIE_GEN2 = 1,
1508 RADEON_PCIE_GEN3 = 2,
1509 RADEON_PCIE_GEN_INVALID = 0xffff
1510};
1511
1512enum radeon_dpm_forced_level {
1513 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1514 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1515 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1516};
1517
1518struct radeon_vce_state {
1519 /* vce clocks */
1520 u32 evclk;
1521 u32 ecclk;
1522 /* gpu clocks */
1523 u32 sclk;
1524 u32 mclk;
1525 u8 clk_idx;
1526 u8 pstate;
1527};
1528
1529struct radeon_dpm {
1530 struct radeon_ps *ps;
1531 /* number of valid power states */
1532 int num_ps;
1533 /* current power state that is active */
1534 struct radeon_ps *current_ps;
1535 /* requested power state */
1536 struct radeon_ps *requested_ps;
1537 /* boot up power state */
1538 struct radeon_ps *boot_ps;
1539 /* default uvd power state */
1540 struct radeon_ps *uvd_ps;
1541 /* vce requirements */
1542 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1543 enum radeon_vce_level vce_level;
1544 enum radeon_pm_state_type state;
1545 enum radeon_pm_state_type user_state;
1546 u32 platform_caps;
1547 u32 voltage_response_time;
1548 u32 backbias_response_time;
1549 void *priv;
1550 u32 new_active_crtcs;
1551 int new_active_crtc_count;
1552 int high_pixelclock_count;
1553 u32 current_active_crtcs;
1554 int current_active_crtc_count;
1555 bool single_display;
1556 struct radeon_dpm_dynamic_state dyn_state;
1557 struct radeon_dpm_fan fan;
1558 u32 tdp_limit;
1559 u32 near_tdp_limit;
1560 u32 near_tdp_limit_adjusted;
1561 u32 sq_ramping_threshold;
1562 u32 cac_leakage;
1563 u16 tdp_od_limit;
1564 u32 tdp_adjustment;
1565 u16 load_line_slope;
1566 bool power_control;
1567 bool ac_power;
1568 /* special states active */
1569 bool thermal_active;
1570 bool uvd_active;
1571 bool vce_active;
1572 /* thermal handling */
1573 struct radeon_dpm_thermal thermal;
1574 /* forced levels */
1575 enum radeon_dpm_forced_level forced_level;
1576 /* track UVD streams */
1577 unsigned sd;
1578 unsigned hd;
1579};
1580
1581void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1582void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1583
1584struct radeon_pm {
1585 struct mutex mutex;
1586 /* write locked while reprogramming mclk */
1587 struct rw_semaphore mclk_lock;
1588 u32 active_crtcs;
1589 int active_crtc_count;
1590 int req_vblank;
1591 bool vblank_sync;
1592 fixed20_12 max_bandwidth;
1593 fixed20_12 igp_sideport_mclk;
1594 fixed20_12 igp_system_mclk;
1595 fixed20_12 igp_ht_link_clk;
1596 fixed20_12 igp_ht_link_width;
1597 fixed20_12 k8_bandwidth;
1598 fixed20_12 sideport_bandwidth;
1599 fixed20_12 ht_bandwidth;
1600 fixed20_12 core_bandwidth;
1601 fixed20_12 sclk;
1602 fixed20_12 mclk;
1603 fixed20_12 needed_bandwidth;
1604 struct radeon_power_state *power_state;
1605 /* number of valid power states */
1606 int num_power_states;
1607 int current_power_state_index;
1608 int current_clock_mode_index;
1609 int requested_power_state_index;
1610 int requested_clock_mode_index;
1611 int default_power_state_index;
1612 u32 current_sclk;
1613 u32 current_mclk;
1614 u16 current_vddc;
1615 u16 current_vddci;
1616 u32 default_sclk;
1617 u32 default_mclk;
1618 u16 default_vddc;
1619 u16 default_vddci;
1620 struct radeon_i2c_chan *i2c_bus;
1621 /* selected pm method */
1622 enum radeon_pm_method pm_method;
1623 /* dynpm power management */
1624 struct delayed_work dynpm_idle_work;
1625 enum radeon_dynpm_state dynpm_state;
1626 enum radeon_dynpm_action dynpm_planned_action;
1627 unsigned long dynpm_action_timeout;
1628 bool dynpm_can_upclock;
1629 bool dynpm_can_downclock;
1630 /* profile-based power management */
1631 enum radeon_pm_profile_type profile;
1632 int profile_index;
1633 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1634 /* internal thermal controller on rv6xx+ */
1635 enum radeon_int_thermal_type int_thermal_type;
1636 struct device *int_hwmon_dev;
1637 /* fan control parameters */
1638 bool no_fan;
1639 u8 fan_pulses_per_revolution;
1640 u8 fan_min_rpm;
1641 u8 fan_max_rpm;
1642 /* dpm */
1643 bool dpm_enabled;
1644 bool sysfs_initialized;
1645 struct radeon_dpm dpm;
1646};
1647
1648#define RADEON_PCIE_SPEED_25 1
1649#define RADEON_PCIE_SPEED_50 2
1650#define RADEON_PCIE_SPEED_80 4
1651
1652int radeon_pm_get_type_index(struct radeon_device *rdev,
1653 enum radeon_pm_state_type ps_type,
1654 int instance);
1655/*
1656 * UVD
1657 */
1658#define RADEON_DEFAULT_UVD_HANDLES 10
1659#define RADEON_MAX_UVD_HANDLES 30
1660#define RADEON_UVD_STACK_SIZE (200*1024)
1661#define RADEON_UVD_HEAP_SIZE (256*1024)
1662#define RADEON_UVD_SESSION_SIZE (50*1024)
1663
1664struct radeon_uvd {
1665 bool fw_header_present;
1666 struct radeon_bo *vcpu_bo;
1667 void *cpu_addr;
1668 uint64_t gpu_addr;
1669 unsigned max_handles;
1670 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1671 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1672 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1673 struct delayed_work idle_work;
1674};
1675
1676int radeon_uvd_init(struct radeon_device *rdev);
1677void radeon_uvd_fini(struct radeon_device *rdev);
1678int radeon_uvd_suspend(struct radeon_device *rdev);
1679int radeon_uvd_resume(struct radeon_device *rdev);
1680int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1681 uint32_t handle, struct radeon_fence **fence);
1682int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1683 uint32_t handle, struct radeon_fence **fence);
1684void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1685 uint32_t allowed_domains);
1686void radeon_uvd_free_handles(struct radeon_device *rdev,
1687 struct drm_file *filp);
1688int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1689void radeon_uvd_note_usage(struct radeon_device *rdev);
1690int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1691 unsigned vclk, unsigned dclk,
1692 unsigned vco_min, unsigned vco_max,
1693 unsigned fb_factor, unsigned fb_mask,
1694 unsigned pd_min, unsigned pd_max,
1695 unsigned pd_even,
1696 unsigned *optimal_fb_div,
1697 unsigned *optimal_vclk_div,
1698 unsigned *optimal_dclk_div);
1699int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1700 unsigned cg_upll_func_cntl);
1701
1702/*
1703 * VCE
1704 */
1705#define RADEON_MAX_VCE_HANDLES 16
1706
1707struct radeon_vce {
1708 struct radeon_bo *vcpu_bo;
1709 uint64_t gpu_addr;
1710 unsigned fw_version;
1711 unsigned fb_version;
1712 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1713 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1714 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1715 struct delayed_work idle_work;
1716 uint32_t keyselect;
1717};
1718
1719int radeon_vce_init(struct radeon_device *rdev);
1720void radeon_vce_fini(struct radeon_device *rdev);
1721int radeon_vce_suspend(struct radeon_device *rdev);
1722int radeon_vce_resume(struct radeon_device *rdev);
1723int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1724 uint32_t handle, struct radeon_fence **fence);
1725int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1726 uint32_t handle, struct radeon_fence **fence);
1727void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1728void radeon_vce_note_usage(struct radeon_device *rdev);
1729int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1730int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1731bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1732 struct radeon_ring *ring,
1733 struct radeon_semaphore *semaphore,
1734 bool emit_wait);
1735void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1736void radeon_vce_fence_emit(struct radeon_device *rdev,
1737 struct radeon_fence *fence);
1738int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1739int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1740
1741struct r600_audio_pin {
1742 int channels;
1743 int rate;
1744 int bits_per_sample;
1745 u8 status_bits;
1746 u8 category_code;
1747 u32 offset;
1748 bool connected;
1749 u32 id;
1750};
1751
1752struct r600_audio {
1753 bool enabled;
1754 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1755 int num_pins;
1756 struct radeon_audio_funcs *hdmi_funcs;
1757 struct radeon_audio_funcs *dp_funcs;
1758 struct radeon_audio_basic_funcs *funcs;
1759 struct drm_audio_component *component;
1760 bool component_registered;
1761 struct mutex component_mutex;
1762};
1763
1764/*
1765 * Benchmarking
1766 */
1767void radeon_benchmark(struct radeon_device *rdev, int test_number);
1768
1769
1770/*
1771 * Testing
1772 */
1773void radeon_test_moves(struct radeon_device *rdev);
1774void radeon_test_ring_sync(struct radeon_device *rdev,
1775 struct radeon_ring *cpA,
1776 struct radeon_ring *cpB);
1777void radeon_test_syncing(struct radeon_device *rdev);
1778
1779/*
1780 * MMU Notifier
1781 */
1782#if defined(CONFIG_MMU_NOTIFIER)
1783int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1784void radeon_mn_unregister(struct radeon_bo *bo);
1785#else
1786static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1787{
1788 return -ENODEV;
1789}
1790static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1791#endif
1792
1793/*
1794 * Debugfs
1795 */
1796void radeon_debugfs_fence_init(struct radeon_device *rdev);
1797void radeon_gem_debugfs_init(struct radeon_device *rdev);
1798
1799/*
1800 * ASIC ring specific functions.
1801 */
1802struct radeon_asic_ring {
1803 /* ring read/write ptr handling */
1804 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1805 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1806 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1807
1808 /* validating and patching of IBs */
1809 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1810 int (*cs_parse)(struct radeon_cs_parser *p);
1811
1812 /* command emmit functions */
1813 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1814 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1815 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1816 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1817 struct radeon_semaphore *semaphore, bool emit_wait);
1818 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1819 unsigned vm_id, uint64_t pd_addr);
1820
1821 /* testing functions */
1822 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1823 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1824 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1825
1826 /* deprecated */
1827 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1828};
1829
1830/*
1831 * ASIC specific functions.
1832 */
1833struct radeon_asic {
1834 int (*init)(struct radeon_device *rdev);
1835 void (*fini)(struct radeon_device *rdev);
1836 int (*resume)(struct radeon_device *rdev);
1837 int (*suspend)(struct radeon_device *rdev);
1838 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1839 int (*asic_reset)(struct radeon_device *rdev, bool hard);
1840 /* Flush the HDP cache via MMIO */
1841 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1842 /* check if 3D engine is idle */
1843 bool (*gui_idle)(struct radeon_device *rdev);
1844 /* wait for mc_idle */
1845 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1846 /* get the reference clock */
1847 u32 (*get_xclk)(struct radeon_device *rdev);
1848 /* get the gpu clock counter */
1849 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1850 /* get register for info ioctl */
1851 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
1852 /* gart */
1853 struct {
1854 void (*tlb_flush)(struct radeon_device *rdev);
1855 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
1856 void (*set_page)(struct radeon_device *rdev, unsigned i,
1857 uint64_t entry);
1858 } gart;
1859 struct {
1860 int (*init)(struct radeon_device *rdev);
1861 void (*fini)(struct radeon_device *rdev);
1862 void (*copy_pages)(struct radeon_device *rdev,
1863 struct radeon_ib *ib,
1864 uint64_t pe, uint64_t src,
1865 unsigned count);
1866 void (*write_pages)(struct radeon_device *rdev,
1867 struct radeon_ib *ib,
1868 uint64_t pe,
1869 uint64_t addr, unsigned count,
1870 uint32_t incr, uint32_t flags);
1871 void (*set_pages)(struct radeon_device *rdev,
1872 struct radeon_ib *ib,
1873 uint64_t pe,
1874 uint64_t addr, unsigned count,
1875 uint32_t incr, uint32_t flags);
1876 void (*pad_ib)(struct radeon_ib *ib);
1877 } vm;
1878 /* ring specific callbacks */
1879 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1880 /* irqs */
1881 struct {
1882 int (*set)(struct radeon_device *rdev);
1883 int (*process)(struct radeon_device *rdev);
1884 } irq;
1885 /* displays */
1886 struct {
1887 /* display watermarks */
1888 void (*bandwidth_update)(struct radeon_device *rdev);
1889 /* get frame count */
1890 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1891 /* wait for vblank */
1892 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1893 /* set backlight level */
1894 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1895 /* get backlight level */
1896 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1897 /* audio callbacks */
1898 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1899 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1900 } display;
1901 /* copy functions for bo handling */
1902 struct {
1903 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1904 uint64_t src_offset,
1905 uint64_t dst_offset,
1906 unsigned num_gpu_pages,
1907 struct dma_resv *resv);
1908 u32 blit_ring_index;
1909 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1910 uint64_t src_offset,
1911 uint64_t dst_offset,
1912 unsigned num_gpu_pages,
1913 struct dma_resv *resv);
1914 u32 dma_ring_index;
1915 /* method used for bo copy */
1916 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1917 uint64_t src_offset,
1918 uint64_t dst_offset,
1919 unsigned num_gpu_pages,
1920 struct dma_resv *resv);
1921 /* ring used for bo copies */
1922 u32 copy_ring_index;
1923 } copy;
1924 /* surfaces */
1925 struct {
1926 int (*set_reg)(struct radeon_device *rdev, int reg,
1927 uint32_t tiling_flags, uint32_t pitch,
1928 uint32_t offset, uint32_t obj_size);
1929 void (*clear_reg)(struct radeon_device *rdev, int reg);
1930 } surface;
1931 /* hotplug detect */
1932 struct {
1933 void (*init)(struct radeon_device *rdev);
1934 void (*fini)(struct radeon_device *rdev);
1935 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1936 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1937 } hpd;
1938 /* static power management */
1939 struct {
1940 void (*misc)(struct radeon_device *rdev);
1941 void (*prepare)(struct radeon_device *rdev);
1942 void (*finish)(struct radeon_device *rdev);
1943 void (*init_profile)(struct radeon_device *rdev);
1944 void (*get_dynpm_state)(struct radeon_device *rdev);
1945 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1946 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1947 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1948 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1949 int (*get_pcie_lanes)(struct radeon_device *rdev);
1950 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1951 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1952 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1953 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1954 int (*get_temperature)(struct radeon_device *rdev);
1955 } pm;
1956 /* dynamic power management */
1957 struct {
1958 int (*init)(struct radeon_device *rdev);
1959 void (*setup_asic)(struct radeon_device *rdev);
1960 int (*enable)(struct radeon_device *rdev);
1961 int (*late_enable)(struct radeon_device *rdev);
1962 void (*disable)(struct radeon_device *rdev);
1963 int (*pre_set_power_state)(struct radeon_device *rdev);
1964 int (*set_power_state)(struct radeon_device *rdev);
1965 void (*post_set_power_state)(struct radeon_device *rdev);
1966 void (*display_configuration_changed)(struct radeon_device *rdev);
1967 void (*fini)(struct radeon_device *rdev);
1968 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1969 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1970 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1971 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1972 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1973 bool (*vblank_too_short)(struct radeon_device *rdev);
1974 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1975 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1976 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
1977 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
1978 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
1979 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
1980 u32 (*get_current_sclk)(struct radeon_device *rdev);
1981 u32 (*get_current_mclk)(struct radeon_device *rdev);
1982 u16 (*get_current_vddc)(struct radeon_device *rdev);
1983 } dpm;
1984 /* pageflipping */
1985 struct {
1986 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async);
1987 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1988 } pflip;
1989};
1990
1991/*
1992 * Asic structures
1993 */
1994struct r100_asic {
1995 const unsigned *reg_safe_bm;
1996 unsigned reg_safe_bm_size;
1997 u32 hdp_cntl;
1998};
1999
2000struct r300_asic {
2001 const unsigned *reg_safe_bm;
2002 unsigned reg_safe_bm_size;
2003 u32 resync_scratch;
2004 u32 hdp_cntl;
2005};
2006
2007struct r600_asic {
2008 unsigned max_pipes;
2009 unsigned max_tile_pipes;
2010 unsigned max_simds;
2011 unsigned max_backends;
2012 unsigned max_gprs;
2013 unsigned max_threads;
2014 unsigned max_stack_entries;
2015 unsigned max_hw_contexts;
2016 unsigned max_gs_threads;
2017 unsigned sx_max_export_size;
2018 unsigned sx_max_export_pos_size;
2019 unsigned sx_max_export_smx_size;
2020 unsigned sq_num_cf_insts;
2021 unsigned tiling_nbanks;
2022 unsigned tiling_npipes;
2023 unsigned tiling_group_size;
2024 unsigned tile_config;
2025 unsigned backend_map;
2026 unsigned active_simds;
2027};
2028
2029struct rv770_asic {
2030 unsigned max_pipes;
2031 unsigned max_tile_pipes;
2032 unsigned max_simds;
2033 unsigned max_backends;
2034 unsigned max_gprs;
2035 unsigned max_threads;
2036 unsigned max_stack_entries;
2037 unsigned max_hw_contexts;
2038 unsigned max_gs_threads;
2039 unsigned sx_max_export_size;
2040 unsigned sx_max_export_pos_size;
2041 unsigned sx_max_export_smx_size;
2042 unsigned sq_num_cf_insts;
2043 unsigned sx_num_of_sets;
2044 unsigned sc_prim_fifo_size;
2045 unsigned sc_hiz_tile_fifo_size;
2046 unsigned sc_earlyz_tile_fifo_fize;
2047 unsigned tiling_nbanks;
2048 unsigned tiling_npipes;
2049 unsigned tiling_group_size;
2050 unsigned tile_config;
2051 unsigned backend_map;
2052 unsigned active_simds;
2053};
2054
2055struct evergreen_asic {
2056 unsigned num_ses;
2057 unsigned max_pipes;
2058 unsigned max_tile_pipes;
2059 unsigned max_simds;
2060 unsigned max_backends;
2061 unsigned max_gprs;
2062 unsigned max_threads;
2063 unsigned max_stack_entries;
2064 unsigned max_hw_contexts;
2065 unsigned max_gs_threads;
2066 unsigned sx_max_export_size;
2067 unsigned sx_max_export_pos_size;
2068 unsigned sx_max_export_smx_size;
2069 unsigned sq_num_cf_insts;
2070 unsigned sx_num_of_sets;
2071 unsigned sc_prim_fifo_size;
2072 unsigned sc_hiz_tile_fifo_size;
2073 unsigned sc_earlyz_tile_fifo_size;
2074 unsigned tiling_nbanks;
2075 unsigned tiling_npipes;
2076 unsigned tiling_group_size;
2077 unsigned tile_config;
2078 unsigned backend_map;
2079 unsigned active_simds;
2080};
2081
2082struct cayman_asic {
2083 unsigned max_shader_engines;
2084 unsigned max_pipes_per_simd;
2085 unsigned max_tile_pipes;
2086 unsigned max_simds_per_se;
2087 unsigned max_backends_per_se;
2088 unsigned max_texture_channel_caches;
2089 unsigned max_gprs;
2090 unsigned max_threads;
2091 unsigned max_gs_threads;
2092 unsigned max_stack_entries;
2093 unsigned sx_num_of_sets;
2094 unsigned sx_max_export_size;
2095 unsigned sx_max_export_pos_size;
2096 unsigned sx_max_export_smx_size;
2097 unsigned max_hw_contexts;
2098 unsigned sq_num_cf_insts;
2099 unsigned sc_prim_fifo_size;
2100 unsigned sc_hiz_tile_fifo_size;
2101 unsigned sc_earlyz_tile_fifo_size;
2102
2103 unsigned num_shader_engines;
2104 unsigned num_shader_pipes_per_simd;
2105 unsigned num_tile_pipes;
2106 unsigned num_simds_per_se;
2107 unsigned num_backends_per_se;
2108 unsigned backend_disable_mask_per_asic;
2109 unsigned backend_map;
2110 unsigned num_texture_channel_caches;
2111 unsigned mem_max_burst_length_bytes;
2112 unsigned mem_row_size_in_kb;
2113 unsigned shader_engine_tile_size;
2114 unsigned num_gpus;
2115 unsigned multi_gpu_tile_size;
2116
2117 unsigned tile_config;
2118 unsigned active_simds;
2119};
2120
2121struct si_asic {
2122 unsigned max_shader_engines;
2123 unsigned max_tile_pipes;
2124 unsigned max_cu_per_sh;
2125 unsigned max_sh_per_se;
2126 unsigned max_backends_per_se;
2127 unsigned max_texture_channel_caches;
2128 unsigned max_gprs;
2129 unsigned max_gs_threads;
2130 unsigned max_hw_contexts;
2131 unsigned sc_prim_fifo_size_frontend;
2132 unsigned sc_prim_fifo_size_backend;
2133 unsigned sc_hiz_tile_fifo_size;
2134 unsigned sc_earlyz_tile_fifo_size;
2135
2136 unsigned num_tile_pipes;
2137 unsigned backend_enable_mask;
2138 unsigned backend_disable_mask_per_asic;
2139 unsigned backend_map;
2140 unsigned num_texture_channel_caches;
2141 unsigned mem_max_burst_length_bytes;
2142 unsigned mem_row_size_in_kb;
2143 unsigned shader_engine_tile_size;
2144 unsigned num_gpus;
2145 unsigned multi_gpu_tile_size;
2146
2147 unsigned tile_config;
2148 uint32_t tile_mode_array[32];
2149 uint32_t active_cus;
2150};
2151
2152struct cik_asic {
2153 unsigned max_shader_engines;
2154 unsigned max_tile_pipes;
2155 unsigned max_cu_per_sh;
2156 unsigned max_sh_per_se;
2157 unsigned max_backends_per_se;
2158 unsigned max_texture_channel_caches;
2159 unsigned max_gprs;
2160 unsigned max_gs_threads;
2161 unsigned max_hw_contexts;
2162 unsigned sc_prim_fifo_size_frontend;
2163 unsigned sc_prim_fifo_size_backend;
2164 unsigned sc_hiz_tile_fifo_size;
2165 unsigned sc_earlyz_tile_fifo_size;
2166
2167 unsigned num_tile_pipes;
2168 unsigned backend_enable_mask;
2169 unsigned backend_disable_mask_per_asic;
2170 unsigned backend_map;
2171 unsigned num_texture_channel_caches;
2172 unsigned mem_max_burst_length_bytes;
2173 unsigned mem_row_size_in_kb;
2174 unsigned shader_engine_tile_size;
2175 unsigned num_gpus;
2176 unsigned multi_gpu_tile_size;
2177
2178 unsigned tile_config;
2179 uint32_t tile_mode_array[32];
2180 uint32_t macrotile_mode_array[16];
2181 uint32_t active_cus;
2182};
2183
2184union radeon_asic_config {
2185 struct r300_asic r300;
2186 struct r100_asic r100;
2187 struct r600_asic r600;
2188 struct rv770_asic rv770;
2189 struct evergreen_asic evergreen;
2190 struct cayman_asic cayman;
2191 struct si_asic si;
2192 struct cik_asic cik;
2193};
2194
2195/*
2196 * asic initizalization from radeon_asic.c
2197 */
2198void radeon_agp_disable(struct radeon_device *rdev);
2199int radeon_asic_init(struct radeon_device *rdev);
2200
2201
2202/*
2203 * IOCTL.
2204 */
2205int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2206 struct drm_file *filp);
2207int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2208 struct drm_file *filp);
2209int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2210 struct drm_file *filp);
2211int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2212 struct drm_file *file_priv);
2213int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2214 struct drm_file *file_priv);
2215int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2216 struct drm_file *filp);
2217int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2218 struct drm_file *filp);
2219int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2220 struct drm_file *filp);
2221int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2222 struct drm_file *filp);
2223int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2224 struct drm_file *filp);
2225int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2226 struct drm_file *filp);
2227int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2228int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2229 struct drm_file *filp);
2230int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2231 struct drm_file *filp);
2232int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2233
2234/* VRAM scratch page for HDP bug, default vram page */
2235struct r600_vram_scratch {
2236 struct radeon_bo *robj;
2237 volatile uint32_t *ptr;
2238 u64 gpu_addr;
2239};
2240
2241/*
2242 * ACPI
2243 */
2244struct radeon_atif_notification_cfg {
2245 bool enabled;
2246 int command_code;
2247};
2248
2249struct radeon_atif_notifications {
2250 bool display_switch;
2251 bool expansion_mode_change;
2252 bool thermal_state;
2253 bool forced_power_state;
2254 bool system_power_state;
2255 bool display_conf_change;
2256 bool px_gfx_switch;
2257 bool brightness_change;
2258 bool dgpu_display_event;
2259};
2260
2261struct radeon_atif_functions {
2262 bool system_params;
2263 bool sbios_requests;
2264 bool select_active_disp;
2265 bool lid_state;
2266 bool get_tv_standard;
2267 bool set_tv_standard;
2268 bool get_panel_expansion_mode;
2269 bool set_panel_expansion_mode;
2270 bool temperature_change;
2271 bool graphics_device_types;
2272};
2273
2274struct radeon_atif {
2275 struct radeon_atif_notifications notifications;
2276 struct radeon_atif_functions functions;
2277 struct radeon_atif_notification_cfg notification_cfg;
2278 struct radeon_encoder *encoder_for_bl;
2279};
2280
2281struct radeon_atcs_functions {
2282 bool get_ext_state;
2283 bool pcie_perf_req;
2284 bool pcie_dev_rdy;
2285 bool pcie_bus_width;
2286};
2287
2288struct radeon_atcs {
2289 struct radeon_atcs_functions functions;
2290};
2291
2292/*
2293 * Core structure, functions and helpers.
2294 */
2295typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2296typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2297
2298struct radeon_device {
2299 struct device *dev;
2300 struct drm_device ddev;
2301 struct pci_dev *pdev;
2302#ifdef __alpha__
2303 struct pci_controller *hose;
2304#endif
2305 struct radeon_agp_head *agp;
2306 struct rw_semaphore exclusive_lock;
2307 /* ASIC */
2308 union radeon_asic_config config;
2309 enum radeon_family family;
2310 unsigned long flags;
2311 int usec_timeout;
2312 enum radeon_pll_errata pll_errata;
2313 int num_gb_pipes;
2314 int num_z_pipes;
2315 int disp_priority;
2316 /* BIOS */
2317 uint8_t *bios;
2318 bool is_atom_bios;
2319 uint16_t bios_header_start;
2320 struct radeon_bo *stolen_vga_memory;
2321 /* Register mmio */
2322 resource_size_t rmmio_base;
2323 resource_size_t rmmio_size;
2324 /* protects concurrent MM_INDEX/DATA based register access */
2325 spinlock_t mmio_idx_lock;
2326 /* protects concurrent SMC based register access */
2327 spinlock_t smc_idx_lock;
2328 /* protects concurrent PLL register access */
2329 spinlock_t pll_idx_lock;
2330 /* protects concurrent MC register access */
2331 spinlock_t mc_idx_lock;
2332 /* protects concurrent PCIE register access */
2333 spinlock_t pcie_idx_lock;
2334 /* protects concurrent PCIE_PORT register access */
2335 spinlock_t pciep_idx_lock;
2336 /* protects concurrent PIF register access */
2337 spinlock_t pif_idx_lock;
2338 /* protects concurrent CG register access */
2339 spinlock_t cg_idx_lock;
2340 /* protects concurrent UVD register access */
2341 spinlock_t uvd_idx_lock;
2342 /* protects concurrent RCU register access */
2343 spinlock_t rcu_idx_lock;
2344 /* protects concurrent DIDT register access */
2345 spinlock_t didt_idx_lock;
2346 /* protects concurrent ENDPOINT (audio) register access */
2347 spinlock_t end_idx_lock;
2348 void __iomem *rmmio;
2349 radeon_rreg_t mc_rreg;
2350 radeon_wreg_t mc_wreg;
2351 radeon_rreg_t pll_rreg;
2352 radeon_wreg_t pll_wreg;
2353 uint32_t pcie_reg_mask;
2354 radeon_rreg_t pciep_rreg;
2355 radeon_wreg_t pciep_wreg;
2356 /* io port */
2357 void __iomem *rio_mem;
2358 resource_size_t rio_mem_size;
2359 struct radeon_clock clock;
2360 struct radeon_mc mc;
2361 struct radeon_gart gart;
2362 struct radeon_mode_info mode_info;
2363 struct radeon_scratch scratch;
2364 struct radeon_doorbell doorbell;
2365 struct radeon_mman mman;
2366 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2367 wait_queue_head_t fence_queue;
2368 u64 fence_context;
2369 struct mutex ring_lock;
2370 struct radeon_ring ring[RADEON_NUM_RINGS];
2371 bool ib_pool_ready;
2372 struct radeon_sa_manager ring_tmp_bo;
2373 struct radeon_irq irq;
2374 struct radeon_asic *asic;
2375 struct radeon_gem gem;
2376 struct radeon_pm pm;
2377 struct radeon_uvd uvd;
2378 struct radeon_vce vce;
2379 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2380 struct radeon_wb wb;
2381 struct radeon_dummy_page dummy_page;
2382 bool shutdown;
2383 bool need_swiotlb;
2384 bool accel_working;
2385 bool fastfb_working; /* IGP feature*/
2386 bool needs_reset, in_reset;
2387 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2388 const struct firmware *me_fw; /* all family ME firmware */
2389 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2390 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2391 const struct firmware *mc_fw; /* NI MC firmware */
2392 const struct firmware *ce_fw; /* SI CE firmware */
2393 const struct firmware *mec_fw; /* CIK MEC firmware */
2394 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2395 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2396 const struct firmware *smc_fw; /* SMC firmware */
2397 const struct firmware *uvd_fw; /* UVD firmware */
2398 const struct firmware *vce_fw; /* VCE firmware */
2399 bool new_fw;
2400 struct r600_vram_scratch vram_scratch;
2401 int msi_enabled; /* msi enabled */
2402 struct r600_ih ih; /* r6/700 interrupt ring */
2403 struct radeon_rlc rlc;
2404 struct radeon_mec mec;
2405 struct delayed_work hotplug_work;
2406 struct work_struct dp_work;
2407 struct work_struct audio_work;
2408 int num_crtc; /* number of crtcs */
2409 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2410 bool has_uvd;
2411 bool has_vce;
2412 struct r600_audio audio; /* audio stuff */
2413 struct notifier_block acpi_nb;
2414 /* only one userspace can use Hyperz features or CMASK at a time */
2415 struct drm_file *hyperz_filp;
2416 struct drm_file *cmask_filp;
2417 /* i2c buses */
2418 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2419 /* virtual memory */
2420 struct radeon_vm_manager vm_manager;
2421 struct mutex gpu_clock_mutex;
2422 /* memory stats */
2423 atomic64_t num_bytes_moved;
2424 atomic_t gpu_reset_counter;
2425 /* ACPI interface */
2426 struct radeon_atif atif;
2427 struct radeon_atcs atcs;
2428 /* srbm instance registers */
2429 struct mutex srbm_mutex;
2430 /* clock, powergating flags */
2431 u32 cg_flags;
2432 u32 pg_flags;
2433
2434 struct dev_pm_domain vga_pm_domain;
2435 bool have_disp_power_ref;
2436 u32 px_quirk_flags;
2437
2438 /* tracking pinned memory */
2439 u64 vram_pin_size;
2440 u64 gart_pin_size;
2441};
2442
2443bool radeon_is_px(struct drm_device *dev);
2444int radeon_device_init(struct radeon_device *rdev,
2445 struct drm_device *ddev,
2446 struct pci_dev *pdev,
2447 uint32_t flags);
2448void radeon_device_fini(struct radeon_device *rdev);
2449int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2450
2451#define RADEON_MIN_MMIO_SIZE 0x10000
2452
2453uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2454void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2455static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2456 bool always_indirect)
2457{
2458 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2459 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2460 return readl(((void __iomem *)rdev->rmmio) + reg);
2461 else
2462 return r100_mm_rreg_slow(rdev, reg);
2463}
2464static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2465 bool always_indirect)
2466{
2467 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2468 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2469 else
2470 r100_mm_wreg_slow(rdev, reg, v);
2471}
2472
2473u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2474void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2475
2476u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2477void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2478
2479static inline struct drm_device *rdev_to_drm(struct radeon_device *rdev)
2480{
2481 return &rdev->ddev;
2482}
2483
2484/*
2485 * Cast helper
2486 */
2487extern const struct dma_fence_ops radeon_fence_ops;
2488
2489static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f)
2490{
2491 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2492
2493 if (__f->base.ops == &radeon_fence_ops)
2494 return __f;
2495
2496 return NULL;
2497}
2498
2499/*
2500 * Registers read & write functions.
2501 */
2502#define RREG8(reg) readb((rdev->rmmio) + (reg))
2503#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2504#define RREG16(reg) readw((rdev->rmmio) + (reg))
2505#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2506#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2507#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2508#define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \
2509 r100_mm_rreg(rdev, (reg), false))
2510#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2511#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2512#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2513#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2514#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2515#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2516#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2517#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2518#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2519#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2520#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2521#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2522#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2523#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2524#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2525#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2526#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2527#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2528#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2529#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2530#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2531#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2532#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2533#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2534#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2535#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2536#define WREG32_P(reg, val, mask) \
2537 do { \
2538 uint32_t tmp_ = RREG32(reg); \
2539 tmp_ &= (mask); \
2540 tmp_ |= ((val) & ~(mask)); \
2541 WREG32(reg, tmp_); \
2542 } while (0)
2543#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2544#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2545#define WREG32_PLL_P(reg, val, mask) \
2546 do { \
2547 uint32_t tmp_ = RREG32_PLL(reg); \
2548 tmp_ &= (mask); \
2549 tmp_ |= ((val) & ~(mask)); \
2550 WREG32_PLL(reg, tmp_); \
2551 } while (0)
2552#define WREG32_SMC_P(reg, val, mask) \
2553 do { \
2554 uint32_t tmp_ = RREG32_SMC(reg); \
2555 tmp_ &= (mask); \
2556 tmp_ |= ((val) & ~(mask)); \
2557 WREG32_SMC(reg, tmp_); \
2558 } while (0)
2559#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2560#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2561#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2562
2563#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2564#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2565
2566/*
2567 * Indirect registers accessors.
2568 * They used to be inlined, but this increases code size by ~65 kbytes.
2569 * Since each performs a pair of MMIO ops
2570 * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2571 * the cost of call+ret is almost negligible. MMIO and locking
2572 * costs several dozens of cycles each at best, call+ret is ~5 cycles.
2573 */
2574uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2575void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2576u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2577void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2578u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2579void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2580u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2581void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2582u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2583void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2584u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2585void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2586u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2587void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2588u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2589void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2590
2591void r100_pll_errata_after_index(struct radeon_device *rdev);
2592
2593
2594/*
2595 * ASICs helpers.
2596 */
2597#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2598 (rdev->pdev->device == 0x5969))
2599#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2600 (rdev->family == CHIP_RV200) || \
2601 (rdev->family == CHIP_RS100) || \
2602 (rdev->family == CHIP_RS200) || \
2603 (rdev->family == CHIP_RV250) || \
2604 (rdev->family == CHIP_RV280) || \
2605 (rdev->family == CHIP_RS300))
2606#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2607 (rdev->family == CHIP_RV350) || \
2608 (rdev->family == CHIP_R350) || \
2609 (rdev->family == CHIP_RV380) || \
2610 (rdev->family == CHIP_R420) || \
2611 (rdev->family == CHIP_R423) || \
2612 (rdev->family == CHIP_RV410) || \
2613 (rdev->family == CHIP_RS400) || \
2614 (rdev->family == CHIP_RS480))
2615#define ASIC_IS_X2(rdev) ((rdev->pdev->device == 0x9441) || \
2616 (rdev->pdev->device == 0x9443) || \
2617 (rdev->pdev->device == 0x944B) || \
2618 (rdev->pdev->device == 0x9506) || \
2619 (rdev->pdev->device == 0x9509) || \
2620 (rdev->pdev->device == 0x950F) || \
2621 (rdev->pdev->device == 0x689C) || \
2622 (rdev->pdev->device == 0x689D))
2623#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2624#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2625 (rdev->family == CHIP_RS690) || \
2626 (rdev->family == CHIP_RS740) || \
2627 (rdev->family >= CHIP_R600))
2628#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2629#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2630#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2631#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2632 (rdev->flags & RADEON_IS_IGP))
2633#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2634#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2635#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2636 (rdev->flags & RADEON_IS_IGP))
2637#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2638#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2639#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2640#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2641#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2642#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2643 (rdev->family == CHIP_MULLINS))
2644
2645#define ASIC_IS_LOMBOK(rdev) ((rdev->pdev->device == 0x6849) || \
2646 (rdev->pdev->device == 0x6850) || \
2647 (rdev->pdev->device == 0x6858) || \
2648 (rdev->pdev->device == 0x6859) || \
2649 (rdev->pdev->device == 0x6840) || \
2650 (rdev->pdev->device == 0x6841) || \
2651 (rdev->pdev->device == 0x6842) || \
2652 (rdev->pdev->device == 0x6843))
2653
2654/*
2655 * BIOS helpers.
2656 */
2657#define RBIOS8(i) (rdev->bios[i])
2658#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2659#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2660
2661int radeon_combios_init(struct radeon_device *rdev);
2662void radeon_combios_fini(struct radeon_device *rdev);
2663int radeon_atombios_init(struct radeon_device *rdev);
2664void radeon_atombios_fini(struct radeon_device *rdev);
2665
2666
2667/*
2668 * RING helpers.
2669 */
2670
2671/**
2672 * radeon_ring_write - write a value to the ring
2673 *
2674 * @ring: radeon_ring structure holding ring information
2675 * @v: dword (dw) value to write
2676 *
2677 * Write a value to the requested ring buffer (all asics).
2678 */
2679static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2680{
2681 if (ring->count_dw <= 0)
2682 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2683
2684 ring->ring[ring->wptr++] = v;
2685 ring->wptr &= ring->ptr_mask;
2686 ring->count_dw--;
2687 ring->ring_free_dw--;
2688}
2689
2690/*
2691 * ASICs macro.
2692 */
2693#define radeon_init(rdev) (rdev)->asic->init((rdev))
2694#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2695#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2696#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2697#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2698#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2699#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false)
2700#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2701#define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2702#define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2703#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2704#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2705#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2706#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2707#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2708#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2709#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2710#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2711#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2712#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2713#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2714#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2715#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2716#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2717#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2718#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2719#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2720#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2721#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2722#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2723#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2724#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2725#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2726#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2727#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2728#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2729#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2730#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2731#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2732#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2733#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2734#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2735#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2736#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2737#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2738#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2739#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2740#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2741#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2742#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2743#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2744#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2745#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2746#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2747#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2748#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2749#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2750#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2751#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2752#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2753#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2754#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2755#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2756#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2757#define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async))
2758#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2759#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2760#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2761#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2762#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2763#define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
2764#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2765#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2766#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2767#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2768#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2769#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2770#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2771#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2772#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2773#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2774#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2775#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2776#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2777#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2778#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2779#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2780#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2781#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2782#define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2783#define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
2784
2785/* Common functions */
2786/* AGP */
2787extern int radeon_gpu_reset(struct radeon_device *rdev);
2788extern void radeon_pci_config_reset(struct radeon_device *rdev);
2789extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2790extern void radeon_agp_disable(struct radeon_device *rdev);
2791extern int radeon_modeset_init(struct radeon_device *rdev);
2792extern void radeon_modeset_fini(struct radeon_device *rdev);
2793extern bool radeon_card_posted(struct radeon_device *rdev);
2794extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2795extern void radeon_update_display_priority(struct radeon_device *rdev);
2796extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2797extern void radeon_scratch_init(struct radeon_device *rdev);
2798extern void radeon_wb_fini(struct radeon_device *rdev);
2799extern int radeon_wb_init(struct radeon_device *rdev);
2800extern void radeon_wb_disable(struct radeon_device *rdev);
2801extern void radeon_surface_init(struct radeon_device *rdev);
2802extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2803extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2804extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2805extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2806extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2807extern int radeon_ttm_tt_set_userptr(struct radeon_device *rdev,
2808 struct ttm_tt *ttm, uint64_t addr,
2809 uint32_t flags);
2810extern bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev, struct ttm_tt *ttm);
2811extern bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev, struct ttm_tt *ttm);
2812bool radeon_ttm_tt_is_bound(struct ttm_device *bdev, struct ttm_tt *ttm);
2813extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2814extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2815extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2816extern int radeon_suspend_kms(struct drm_device *dev, bool suspend,
2817 bool fbcon, bool freeze);
2818extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2819extern void radeon_program_register_sequence(struct radeon_device *rdev,
2820 const u32 *registers,
2821 const u32 array_size);
2822struct radeon_device *radeon_get_rdev(struct ttm_device *bdev);
2823
2824/* KMS */
2825
2826u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc);
2827int radeon_enable_vblank_kms(struct drm_crtc *crtc);
2828void radeon_disable_vblank_kms(struct drm_crtc *crtc);
2829
2830/*
2831 * vm
2832 */
2833int radeon_vm_manager_init(struct radeon_device *rdev);
2834void radeon_vm_manager_fini(struct radeon_device *rdev);
2835int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2836void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2837struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
2838 struct radeon_vm *vm,
2839 struct list_head *head);
2840struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2841 struct radeon_vm *vm, int ring);
2842void radeon_vm_flush(struct radeon_device *rdev,
2843 struct radeon_vm *vm,
2844 int ring, struct radeon_fence *fence);
2845void radeon_vm_fence(struct radeon_device *rdev,
2846 struct radeon_vm *vm,
2847 struct radeon_fence *fence);
2848uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2849int radeon_vm_update_page_directory(struct radeon_device *rdev,
2850 struct radeon_vm *vm);
2851int radeon_vm_clear_freed(struct radeon_device *rdev,
2852 struct radeon_vm *vm);
2853int radeon_vm_clear_invalids(struct radeon_device *rdev,
2854 struct radeon_vm *vm);
2855int radeon_vm_bo_update(struct radeon_device *rdev,
2856 struct radeon_bo_va *bo_va,
2857 struct ttm_resource *mem);
2858void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2859 struct radeon_bo *bo);
2860struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2861 struct radeon_bo *bo);
2862struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2863 struct radeon_vm *vm,
2864 struct radeon_bo *bo);
2865int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2866 struct radeon_bo_va *bo_va,
2867 uint64_t offset,
2868 uint32_t flags);
2869void radeon_vm_bo_rmv(struct radeon_device *rdev,
2870 struct radeon_bo_va *bo_va);
2871
2872/* audio */
2873void r600_audio_update_hdmi(struct work_struct *work);
2874struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2875struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2876void r600_audio_enable(struct radeon_device *rdev,
2877 struct r600_audio_pin *pin,
2878 u8 enable_mask);
2879void dce6_audio_enable(struct radeon_device *rdev,
2880 struct r600_audio_pin *pin,
2881 u8 enable_mask);
2882
2883/*
2884 * R600 vram scratch functions
2885 */
2886int r600_vram_scratch_init(struct radeon_device *rdev);
2887void r600_vram_scratch_fini(struct radeon_device *rdev);
2888
2889/*
2890 * r600 cs checking helper
2891 */
2892unsigned r600_mip_minify(unsigned size, unsigned level);
2893bool r600_fmt_is_valid_color(u32 format);
2894bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2895int r600_fmt_get_blocksize(u32 format);
2896int r600_fmt_get_nblocksx(u32 format, u32 w);
2897int r600_fmt_get_nblocksy(u32 format, u32 h);
2898
2899/*
2900 * r600 functions used by radeon_encoder.c
2901 */
2902struct radeon_hdmi_acr {
2903 u32 clock;
2904
2905 int n_32khz;
2906 int cts_32khz;
2907
2908 int n_44_1khz;
2909 int cts_44_1khz;
2910
2911 int n_48khz;
2912 int cts_48khz;
2913
2914};
2915
2916extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2917 u32 tiling_pipe_num,
2918 u32 max_rb_num,
2919 u32 total_max_rb_num,
2920 u32 enabled_rb_mask);
2921
2922/*
2923 * evergreen functions used by radeon_encoder.c
2924 */
2925
2926extern int ni_init_microcode(struct radeon_device *rdev);
2927extern int ni_mc_load_microcode(struct radeon_device *rdev);
2928
2929/* radeon_acpi.c */
2930#if defined(CONFIG_ACPI)
2931extern int radeon_acpi_init(struct radeon_device *rdev);
2932extern void radeon_acpi_fini(struct radeon_device *rdev);
2933extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2934extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2935 u8 perf_req, bool advertise);
2936extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2937#else
2938static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2939static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2940#endif
2941
2942int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2943 struct radeon_cs_packet *pkt,
2944 unsigned idx);
2945bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2946void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2947 struct radeon_cs_packet *pkt);
2948int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2949 struct radeon_bo_list **cs_reloc,
2950 int nomm);
2951int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2952 uint32_t *vline_start_end,
2953 uint32_t *vline_status);
2954
2955/* interrupt control register helpers */
2956void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev,
2957 u32 reg, u32 mask,
2958 bool enable, const char *name,
2959 unsigned n);
2960
2961/* Audio component binding */
2962void radeon_audio_component_init(struct radeon_device *rdev);
2963void radeon_audio_component_fini(struct radeon_device *rdev);
2964
2965#include "radeon_object.h"
2966
2967#endif
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63#include <linux/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67#include <linux/interval_tree.h>
68#include <linux/hashtable.h>
69#include <linux/dma-fence.h>
70
71#include <ttm/ttm_bo_api.h>
72#include <ttm/ttm_bo_driver.h>
73#include <ttm/ttm_placement.h>
74#include <ttm/ttm_module.h>
75#include <ttm/ttm_execbuf_util.h>
76
77#include <drm/drm_gem.h>
78
79#include "radeon_family.h"
80#include "radeon_mode.h"
81#include "radeon_reg.h"
82
83/*
84 * Modules parameters.
85 */
86extern int radeon_no_wb;
87extern int radeon_modeset;
88extern int radeon_dynclks;
89extern int radeon_r4xx_atom;
90extern int radeon_agpmode;
91extern int radeon_vram_limit;
92extern int radeon_gart_size;
93extern int radeon_benchmarking;
94extern int radeon_testing;
95extern int radeon_connector_table;
96extern int radeon_tv;
97extern int radeon_audio;
98extern int radeon_disp_priority;
99extern int radeon_hw_i2c;
100extern int radeon_pcie_gen2;
101extern int radeon_msi;
102extern int radeon_lockup_timeout;
103extern int radeon_fastfb;
104extern int radeon_dpm;
105extern int radeon_aspm;
106extern int radeon_runtime_pm;
107extern int radeon_hard_reset;
108extern int radeon_vm_size;
109extern int radeon_vm_block_size;
110extern int radeon_deep_color;
111extern int radeon_use_pflipirq;
112extern int radeon_bapm;
113extern int radeon_backlight;
114extern int radeon_auxch;
115extern int radeon_mst;
116extern int radeon_uvd;
117extern int radeon_vce;
118
119/*
120 * Copy from radeon_drv.h so we don't have to include both and have conflicting
121 * symbol;
122 */
123#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
124#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
125#define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */
126/* RADEON_IB_POOL_SIZE must be a power of 2 */
127#define RADEON_IB_POOL_SIZE 16
128#define RADEON_DEBUGFS_MAX_COMPONENTS 32
129#define RADEONFB_CONN_LIMIT 4
130#define RADEON_BIOS_NUM_SCRATCH 8
131
132/* internal ring indices */
133/* r1xx+ has gfx CP ring */
134#define RADEON_RING_TYPE_GFX_INDEX 0
135
136/* cayman has 2 compute CP rings */
137#define CAYMAN_RING_TYPE_CP1_INDEX 1
138#define CAYMAN_RING_TYPE_CP2_INDEX 2
139
140/* R600+ has an async dma ring */
141#define R600_RING_TYPE_DMA_INDEX 3
142/* cayman add a second async dma ring */
143#define CAYMAN_RING_TYPE_DMA1_INDEX 4
144
145/* R600+ */
146#define R600_RING_TYPE_UVD_INDEX 5
147
148/* TN+ */
149#define TN_RING_TYPE_VCE1_INDEX 6
150#define TN_RING_TYPE_VCE2_INDEX 7
151
152/* max number of rings */
153#define RADEON_NUM_RINGS 8
154
155/* number of hw syncs before falling back on blocking */
156#define RADEON_NUM_SYNCS 4
157
158/* hardcode those limit for now */
159#define RADEON_VA_IB_OFFSET (1 << 20)
160#define RADEON_VA_RESERVED_SIZE (8 << 20)
161#define RADEON_IB_VM_MAX_SIZE (64 << 10)
162
163/* hard reset data */
164#define RADEON_ASIC_RESET_DATA 0x39d5e86b
165
166/* reset flags */
167#define RADEON_RESET_GFX (1 << 0)
168#define RADEON_RESET_COMPUTE (1 << 1)
169#define RADEON_RESET_DMA (1 << 2)
170#define RADEON_RESET_CP (1 << 3)
171#define RADEON_RESET_GRBM (1 << 4)
172#define RADEON_RESET_DMA1 (1 << 5)
173#define RADEON_RESET_RLC (1 << 6)
174#define RADEON_RESET_SEM (1 << 7)
175#define RADEON_RESET_IH (1 << 8)
176#define RADEON_RESET_VMC (1 << 9)
177#define RADEON_RESET_MC (1 << 10)
178#define RADEON_RESET_DISPLAY (1 << 11)
179
180/* CG block flags */
181#define RADEON_CG_BLOCK_GFX (1 << 0)
182#define RADEON_CG_BLOCK_MC (1 << 1)
183#define RADEON_CG_BLOCK_SDMA (1 << 2)
184#define RADEON_CG_BLOCK_UVD (1 << 3)
185#define RADEON_CG_BLOCK_VCE (1 << 4)
186#define RADEON_CG_BLOCK_HDP (1 << 5)
187#define RADEON_CG_BLOCK_BIF (1 << 6)
188
189/* CG flags */
190#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
191#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
192#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
193#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
194#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
195#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
196#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
197#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
198#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
199#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
200#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
201#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
202#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
203#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
204#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
205#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
206#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
207
208/* PG flags */
209#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
210#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
211#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
212#define RADEON_PG_SUPPORT_UVD (1 << 3)
213#define RADEON_PG_SUPPORT_VCE (1 << 4)
214#define RADEON_PG_SUPPORT_CP (1 << 5)
215#define RADEON_PG_SUPPORT_GDS (1 << 6)
216#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
217#define RADEON_PG_SUPPORT_SDMA (1 << 8)
218#define RADEON_PG_SUPPORT_ACP (1 << 9)
219#define RADEON_PG_SUPPORT_SAMU (1 << 10)
220
221/* max cursor sizes (in pixels) */
222#define CURSOR_WIDTH 64
223#define CURSOR_HEIGHT 64
224
225#define CIK_CURSOR_WIDTH 128
226#define CIK_CURSOR_HEIGHT 128
227
228/*
229 * Errata workarounds.
230 */
231enum radeon_pll_errata {
232 CHIP_ERRATA_R300_CG = 0x00000001,
233 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
234 CHIP_ERRATA_PLL_DELAY = 0x00000004
235};
236
237
238struct radeon_device;
239
240
241/*
242 * BIOS.
243 */
244bool radeon_get_bios(struct radeon_device *rdev);
245
246/*
247 * Dummy page
248 */
249struct radeon_dummy_page {
250 uint64_t entry;
251 struct page *page;
252 dma_addr_t addr;
253};
254int radeon_dummy_page_init(struct radeon_device *rdev);
255void radeon_dummy_page_fini(struct radeon_device *rdev);
256
257
258/*
259 * Clocks
260 */
261struct radeon_clock {
262 struct radeon_pll p1pll;
263 struct radeon_pll p2pll;
264 struct radeon_pll dcpll;
265 struct radeon_pll spll;
266 struct radeon_pll mpll;
267 /* 10 Khz units */
268 uint32_t default_mclk;
269 uint32_t default_sclk;
270 uint32_t default_dispclk;
271 uint32_t current_dispclk;
272 uint32_t dp_extclk;
273 uint32_t max_pixel_clock;
274 uint32_t vco_freq;
275};
276
277/*
278 * Power management
279 */
280int radeon_pm_init(struct radeon_device *rdev);
281int radeon_pm_late_init(struct radeon_device *rdev);
282void radeon_pm_fini(struct radeon_device *rdev);
283void radeon_pm_compute_clocks(struct radeon_device *rdev);
284void radeon_pm_suspend(struct radeon_device *rdev);
285void radeon_pm_resume(struct radeon_device *rdev);
286void radeon_combios_get_power_modes(struct radeon_device *rdev);
287void radeon_atombios_get_power_modes(struct radeon_device *rdev);
288int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
289 u8 clock_type,
290 u32 clock,
291 bool strobe_mode,
292 struct atom_clock_dividers *dividers);
293int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
294 u32 clock,
295 bool strobe_mode,
296 struct atom_mpll_param *mpll_param);
297void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
298int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
299 u16 voltage_level, u8 voltage_type,
300 u32 *gpio_value, u32 *gpio_mask);
301void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
302 u32 eng_clock, u32 mem_clock);
303int radeon_atom_get_voltage_step(struct radeon_device *rdev,
304 u8 voltage_type, u16 *voltage_step);
305int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
306 u16 voltage_id, u16 *voltage);
307int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
308 u16 *voltage,
309 u16 leakage_idx);
310int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
311 u16 *leakage_id);
312int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
313 u16 *vddc, u16 *vddci,
314 u16 virtual_voltage_id,
315 u16 vbios_voltage_id);
316int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
317 u16 virtual_voltage_id,
318 u16 *voltage);
319int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
320 u8 voltage_type,
321 u16 nominal_voltage,
322 u16 *true_voltage);
323int radeon_atom_get_min_voltage(struct radeon_device *rdev,
324 u8 voltage_type, u16 *min_voltage);
325int radeon_atom_get_max_voltage(struct radeon_device *rdev,
326 u8 voltage_type, u16 *max_voltage);
327int radeon_atom_get_voltage_table(struct radeon_device *rdev,
328 u8 voltage_type, u8 voltage_mode,
329 struct atom_voltage_table *voltage_table);
330bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
331 u8 voltage_type, u8 voltage_mode);
332int radeon_atom_get_svi2_info(struct radeon_device *rdev,
333 u8 voltage_type,
334 u8 *svd_gpio_id, u8 *svc_gpio_id);
335void radeon_atom_update_memory_dll(struct radeon_device *rdev,
336 u32 mem_clock);
337void radeon_atom_set_ac_timing(struct radeon_device *rdev,
338 u32 mem_clock);
339int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
340 u8 module_index,
341 struct atom_mc_reg_table *reg_table);
342int radeon_atom_get_memory_info(struct radeon_device *rdev,
343 u8 module_index, struct atom_memory_info *mem_info);
344int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
345 bool gddr5, u8 module_index,
346 struct atom_memory_clock_range_table *mclk_range_table);
347int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
348 u16 voltage_id, u16 *voltage);
349void rs690_pm_info(struct radeon_device *rdev);
350extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
351 unsigned *bankh, unsigned *mtaspect,
352 unsigned *tile_split);
353
354/*
355 * Fences.
356 */
357struct radeon_fence_driver {
358 struct radeon_device *rdev;
359 uint32_t scratch_reg;
360 uint64_t gpu_addr;
361 volatile uint32_t *cpu_addr;
362 /* sync_seq is protected by ring emission lock */
363 uint64_t sync_seq[RADEON_NUM_RINGS];
364 atomic64_t last_seq;
365 bool initialized, delayed_irq;
366 struct delayed_work lockup_work;
367};
368
369struct radeon_fence {
370 struct dma_fence base;
371
372 struct radeon_device *rdev;
373 uint64_t seq;
374 /* RB, DMA, etc. */
375 unsigned ring;
376 bool is_vm_update;
377
378 wait_queue_t fence_wake;
379};
380
381int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
382int radeon_fence_driver_init(struct radeon_device *rdev);
383void radeon_fence_driver_fini(struct radeon_device *rdev);
384void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
385int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
386void radeon_fence_process(struct radeon_device *rdev, int ring);
387bool radeon_fence_signaled(struct radeon_fence *fence);
388long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
389int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
390int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
391int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
392int radeon_fence_wait_any(struct radeon_device *rdev,
393 struct radeon_fence **fences,
394 bool intr);
395struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
396void radeon_fence_unref(struct radeon_fence **fence);
397unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
398bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
399void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
400static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
401 struct radeon_fence *b)
402{
403 if (!a) {
404 return b;
405 }
406
407 if (!b) {
408 return a;
409 }
410
411 BUG_ON(a->ring != b->ring);
412
413 if (a->seq > b->seq) {
414 return a;
415 } else {
416 return b;
417 }
418}
419
420static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
421 struct radeon_fence *b)
422{
423 if (!a) {
424 return false;
425 }
426
427 if (!b) {
428 return true;
429 }
430
431 BUG_ON(a->ring != b->ring);
432
433 return a->seq < b->seq;
434}
435
436/*
437 * Tiling registers
438 */
439struct radeon_surface_reg {
440 struct radeon_bo *bo;
441};
442
443#define RADEON_GEM_MAX_SURFACES 8
444
445/*
446 * TTM.
447 */
448struct radeon_mman {
449 struct ttm_bo_global_ref bo_global_ref;
450 struct drm_global_reference mem_global_ref;
451 struct ttm_bo_device bdev;
452 bool mem_global_referenced;
453 bool initialized;
454
455#if defined(CONFIG_DEBUG_FS)
456 struct dentry *vram;
457 struct dentry *gtt;
458#endif
459};
460
461struct radeon_bo_list {
462 struct radeon_bo *robj;
463 struct ttm_validate_buffer tv;
464 uint64_t gpu_offset;
465 unsigned prefered_domains;
466 unsigned allowed_domains;
467 uint32_t tiling_flags;
468};
469
470/* bo virtual address in a specific vm */
471struct radeon_bo_va {
472 /* protected by bo being reserved */
473 struct list_head bo_list;
474 uint32_t flags;
475 struct radeon_fence *last_pt_update;
476 unsigned ref_count;
477
478 /* protected by vm mutex */
479 struct interval_tree_node it;
480 struct list_head vm_status;
481
482 /* constant after initialization */
483 struct radeon_vm *vm;
484 struct radeon_bo *bo;
485};
486
487struct radeon_bo {
488 /* Protected by gem.mutex */
489 struct list_head list;
490 /* Protected by tbo.reserved */
491 u32 initial_domain;
492 struct ttm_place placements[4];
493 struct ttm_placement placement;
494 struct ttm_buffer_object tbo;
495 struct ttm_bo_kmap_obj kmap;
496 u32 flags;
497 unsigned pin_count;
498 void *kptr;
499 u32 tiling_flags;
500 u32 pitch;
501 int surface_reg;
502 /* list of all virtual address to which this bo
503 * is associated to
504 */
505 struct list_head va;
506 /* Constant after initialization */
507 struct radeon_device *rdev;
508 struct drm_gem_object gem_base;
509
510 struct ttm_bo_kmap_obj dma_buf_vmap;
511 pid_t pid;
512
513 struct radeon_mn *mn;
514 struct list_head mn_list;
515};
516#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
517
518int radeon_gem_debugfs_init(struct radeon_device *rdev);
519
520/* sub-allocation manager, it has to be protected by another lock.
521 * By conception this is an helper for other part of the driver
522 * like the indirect buffer or semaphore, which both have their
523 * locking.
524 *
525 * Principe is simple, we keep a list of sub allocation in offset
526 * order (first entry has offset == 0, last entry has the highest
527 * offset).
528 *
529 * When allocating new object we first check if there is room at
530 * the end total_size - (last_object_offset + last_object_size) >=
531 * alloc_size. If so we allocate new object there.
532 *
533 * When there is not enough room at the end, we start waiting for
534 * each sub object until we reach object_offset+object_size >=
535 * alloc_size, this object then become the sub object we return.
536 *
537 * Alignment can't be bigger than page size.
538 *
539 * Hole are not considered for allocation to keep things simple.
540 * Assumption is that there won't be hole (all object on same
541 * alignment).
542 */
543struct radeon_sa_manager {
544 wait_queue_head_t wq;
545 struct radeon_bo *bo;
546 struct list_head *hole;
547 struct list_head flist[RADEON_NUM_RINGS];
548 struct list_head olist;
549 unsigned size;
550 uint64_t gpu_addr;
551 void *cpu_ptr;
552 uint32_t domain;
553 uint32_t align;
554};
555
556struct radeon_sa_bo;
557
558/* sub-allocation buffer */
559struct radeon_sa_bo {
560 struct list_head olist;
561 struct list_head flist;
562 struct radeon_sa_manager *manager;
563 unsigned soffset;
564 unsigned eoffset;
565 struct radeon_fence *fence;
566};
567
568/*
569 * GEM objects.
570 */
571struct radeon_gem {
572 struct mutex mutex;
573 struct list_head objects;
574};
575
576int radeon_gem_init(struct radeon_device *rdev);
577void radeon_gem_fini(struct radeon_device *rdev);
578int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
579 int alignment, int initial_domain,
580 u32 flags, bool kernel,
581 struct drm_gem_object **obj);
582
583int radeon_mode_dumb_create(struct drm_file *file_priv,
584 struct drm_device *dev,
585 struct drm_mode_create_dumb *args);
586int radeon_mode_dumb_mmap(struct drm_file *filp,
587 struct drm_device *dev,
588 uint32_t handle, uint64_t *offset_p);
589
590/*
591 * Semaphores.
592 */
593struct radeon_semaphore {
594 struct radeon_sa_bo *sa_bo;
595 signed waiters;
596 uint64_t gpu_addr;
597};
598
599int radeon_semaphore_create(struct radeon_device *rdev,
600 struct radeon_semaphore **semaphore);
601bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
602 struct radeon_semaphore *semaphore);
603bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
604 struct radeon_semaphore *semaphore);
605void radeon_semaphore_free(struct radeon_device *rdev,
606 struct radeon_semaphore **semaphore,
607 struct radeon_fence *fence);
608
609/*
610 * Synchronization
611 */
612struct radeon_sync {
613 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
614 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
615 struct radeon_fence *last_vm_update;
616};
617
618void radeon_sync_create(struct radeon_sync *sync);
619void radeon_sync_fence(struct radeon_sync *sync,
620 struct radeon_fence *fence);
621int radeon_sync_resv(struct radeon_device *rdev,
622 struct radeon_sync *sync,
623 struct reservation_object *resv,
624 bool shared);
625int radeon_sync_rings(struct radeon_device *rdev,
626 struct radeon_sync *sync,
627 int waiting_ring);
628void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
629 struct radeon_fence *fence);
630
631/*
632 * GART structures, functions & helpers
633 */
634struct radeon_mc;
635
636#define RADEON_GPU_PAGE_SIZE 4096
637#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
638#define RADEON_GPU_PAGE_SHIFT 12
639#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
640
641#define RADEON_GART_PAGE_DUMMY 0
642#define RADEON_GART_PAGE_VALID (1 << 0)
643#define RADEON_GART_PAGE_READ (1 << 1)
644#define RADEON_GART_PAGE_WRITE (1 << 2)
645#define RADEON_GART_PAGE_SNOOP (1 << 3)
646
647struct radeon_gart {
648 dma_addr_t table_addr;
649 struct radeon_bo *robj;
650 void *ptr;
651 unsigned num_gpu_pages;
652 unsigned num_cpu_pages;
653 unsigned table_size;
654 struct page **pages;
655 uint64_t *pages_entry;
656 bool ready;
657};
658
659int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
660void radeon_gart_table_ram_free(struct radeon_device *rdev);
661int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
662void radeon_gart_table_vram_free(struct radeon_device *rdev);
663int radeon_gart_table_vram_pin(struct radeon_device *rdev);
664void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
665int radeon_gart_init(struct radeon_device *rdev);
666void radeon_gart_fini(struct radeon_device *rdev);
667void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
668 int pages);
669int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
670 int pages, struct page **pagelist,
671 dma_addr_t *dma_addr, uint32_t flags);
672
673
674/*
675 * GPU MC structures, functions & helpers
676 */
677struct radeon_mc {
678 resource_size_t aper_size;
679 resource_size_t aper_base;
680 resource_size_t agp_base;
681 /* for some chips with <= 32MB we need to lie
682 * about vram size near mc fb location */
683 u64 mc_vram_size;
684 u64 visible_vram_size;
685 u64 gtt_size;
686 u64 gtt_start;
687 u64 gtt_end;
688 u64 vram_start;
689 u64 vram_end;
690 unsigned vram_width;
691 u64 real_vram_size;
692 int vram_mtrr;
693 bool vram_is_ddr;
694 bool igp_sideport_enabled;
695 u64 gtt_base_align;
696 u64 mc_mask;
697};
698
699bool radeon_combios_sideport_present(struct radeon_device *rdev);
700bool radeon_atombios_sideport_present(struct radeon_device *rdev);
701
702/*
703 * GPU scratch registers structures, functions & helpers
704 */
705struct radeon_scratch {
706 unsigned num_reg;
707 uint32_t reg_base;
708 bool free[32];
709 uint32_t reg[32];
710};
711
712int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
713void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
714
715/*
716 * GPU doorbell structures, functions & helpers
717 */
718#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
719
720struct radeon_doorbell {
721 /* doorbell mmio */
722 resource_size_t base;
723 resource_size_t size;
724 u32 __iomem *ptr;
725 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
726 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
727};
728
729int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
730void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
731void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
732 phys_addr_t *aperture_base,
733 size_t *aperture_size,
734 size_t *start_offset);
735
736/*
737 * IRQS.
738 */
739
740struct radeon_flip_work {
741 struct work_struct flip_work;
742 struct work_struct unpin_work;
743 struct radeon_device *rdev;
744 int crtc_id;
745 u32 target_vblank;
746 uint64_t base;
747 struct drm_pending_vblank_event *event;
748 struct radeon_bo *old_rbo;
749 struct dma_fence *fence;
750 bool async;
751};
752
753struct r500_irq_stat_regs {
754 u32 disp_int;
755 u32 hdmi0_status;
756};
757
758struct r600_irq_stat_regs {
759 u32 disp_int;
760 u32 disp_int_cont;
761 u32 disp_int_cont2;
762 u32 d1grph_int;
763 u32 d2grph_int;
764 u32 hdmi0_status;
765 u32 hdmi1_status;
766};
767
768struct evergreen_irq_stat_regs {
769 u32 disp_int;
770 u32 disp_int_cont;
771 u32 disp_int_cont2;
772 u32 disp_int_cont3;
773 u32 disp_int_cont4;
774 u32 disp_int_cont5;
775 u32 d1grph_int;
776 u32 d2grph_int;
777 u32 d3grph_int;
778 u32 d4grph_int;
779 u32 d5grph_int;
780 u32 d6grph_int;
781 u32 afmt_status1;
782 u32 afmt_status2;
783 u32 afmt_status3;
784 u32 afmt_status4;
785 u32 afmt_status5;
786 u32 afmt_status6;
787};
788
789struct cik_irq_stat_regs {
790 u32 disp_int;
791 u32 disp_int_cont;
792 u32 disp_int_cont2;
793 u32 disp_int_cont3;
794 u32 disp_int_cont4;
795 u32 disp_int_cont5;
796 u32 disp_int_cont6;
797 u32 d1grph_int;
798 u32 d2grph_int;
799 u32 d3grph_int;
800 u32 d4grph_int;
801 u32 d5grph_int;
802 u32 d6grph_int;
803};
804
805union radeon_irq_stat_regs {
806 struct r500_irq_stat_regs r500;
807 struct r600_irq_stat_regs r600;
808 struct evergreen_irq_stat_regs evergreen;
809 struct cik_irq_stat_regs cik;
810};
811
812struct radeon_irq {
813 bool installed;
814 spinlock_t lock;
815 atomic_t ring_int[RADEON_NUM_RINGS];
816 bool crtc_vblank_int[RADEON_MAX_CRTCS];
817 atomic_t pflip[RADEON_MAX_CRTCS];
818 wait_queue_head_t vblank_queue;
819 bool hpd[RADEON_MAX_HPD_PINS];
820 bool afmt[RADEON_MAX_AFMT_BLOCKS];
821 union radeon_irq_stat_regs stat_regs;
822 bool dpm_thermal;
823};
824
825int radeon_irq_kms_init(struct radeon_device *rdev);
826void radeon_irq_kms_fini(struct radeon_device *rdev);
827void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
828bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
829void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
830void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
831void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
832void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
833void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
834void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
835void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
836
837/*
838 * CP & rings.
839 */
840
841struct radeon_ib {
842 struct radeon_sa_bo *sa_bo;
843 uint32_t length_dw;
844 uint64_t gpu_addr;
845 uint32_t *ptr;
846 int ring;
847 struct radeon_fence *fence;
848 struct radeon_vm *vm;
849 bool is_const_ib;
850 struct radeon_sync sync;
851};
852
853struct radeon_ring {
854 struct radeon_bo *ring_obj;
855 volatile uint32_t *ring;
856 unsigned rptr_offs;
857 unsigned rptr_save_reg;
858 u64 next_rptr_gpu_addr;
859 volatile u32 *next_rptr_cpu_addr;
860 unsigned wptr;
861 unsigned wptr_old;
862 unsigned ring_size;
863 unsigned ring_free_dw;
864 int count_dw;
865 atomic_t last_rptr;
866 atomic64_t last_activity;
867 uint64_t gpu_addr;
868 uint32_t align_mask;
869 uint32_t ptr_mask;
870 bool ready;
871 u32 nop;
872 u32 idx;
873 u64 last_semaphore_signal_addr;
874 u64 last_semaphore_wait_addr;
875 /* for CIK queues */
876 u32 me;
877 u32 pipe;
878 u32 queue;
879 struct radeon_bo *mqd_obj;
880 u32 doorbell_index;
881 unsigned wptr_offs;
882};
883
884struct radeon_mec {
885 struct radeon_bo *hpd_eop_obj;
886 u64 hpd_eop_gpu_addr;
887 u32 num_pipe;
888 u32 num_mec;
889 u32 num_queue;
890};
891
892/*
893 * VM
894 */
895
896/* maximum number of VMIDs */
897#define RADEON_NUM_VM 16
898
899/* number of entries in page table */
900#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
901
902/* PTBs (Page Table Blocks) need to be aligned to 32K */
903#define RADEON_VM_PTB_ALIGN_SIZE 32768
904#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
905#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
906
907#define R600_PTE_VALID (1 << 0)
908#define R600_PTE_SYSTEM (1 << 1)
909#define R600_PTE_SNOOPED (1 << 2)
910#define R600_PTE_READABLE (1 << 5)
911#define R600_PTE_WRITEABLE (1 << 6)
912
913/* PTE (Page Table Entry) fragment field for different page sizes */
914#define R600_PTE_FRAG_4KB (0 << 7)
915#define R600_PTE_FRAG_64KB (4 << 7)
916#define R600_PTE_FRAG_256KB (6 << 7)
917
918/* flags needed to be set so we can copy directly from the GART table */
919#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
920 R600_PTE_SYSTEM | R600_PTE_VALID )
921
922struct radeon_vm_pt {
923 struct radeon_bo *bo;
924 uint64_t addr;
925};
926
927struct radeon_vm_id {
928 unsigned id;
929 uint64_t pd_gpu_addr;
930 /* last flushed PD/PT update */
931 struct radeon_fence *flushed_updates;
932 /* last use of vmid */
933 struct radeon_fence *last_id_use;
934};
935
936struct radeon_vm {
937 struct mutex mutex;
938
939 struct rb_root va;
940
941 /* protecting invalidated and freed */
942 spinlock_t status_lock;
943
944 /* BOs moved, but not yet updated in the PT */
945 struct list_head invalidated;
946
947 /* BOs freed, but not yet updated in the PT */
948 struct list_head freed;
949
950 /* BOs cleared in the PT */
951 struct list_head cleared;
952
953 /* contains the page directory */
954 struct radeon_bo *page_directory;
955 unsigned max_pde_used;
956
957 /* array of page tables, one for each page directory entry */
958 struct radeon_vm_pt *page_tables;
959
960 struct radeon_bo_va *ib_bo_va;
961
962 /* for id and flush management per ring */
963 struct radeon_vm_id ids[RADEON_NUM_RINGS];
964};
965
966struct radeon_vm_manager {
967 struct radeon_fence *active[RADEON_NUM_VM];
968 uint32_t max_pfn;
969 /* number of VMIDs */
970 unsigned nvm;
971 /* vram base address for page table entry */
972 u64 vram_base_offset;
973 /* is vm enabled? */
974 bool enabled;
975 /* for hw to save the PD addr on suspend/resume */
976 uint32_t saved_table_addr[RADEON_NUM_VM];
977};
978
979/*
980 * file private structure
981 */
982struct radeon_fpriv {
983 struct radeon_vm vm;
984};
985
986/*
987 * R6xx+ IH ring
988 */
989struct r600_ih {
990 struct radeon_bo *ring_obj;
991 volatile uint32_t *ring;
992 unsigned rptr;
993 unsigned ring_size;
994 uint64_t gpu_addr;
995 uint32_t ptr_mask;
996 atomic_t lock;
997 bool enabled;
998};
999
1000/*
1001 * RLC stuff
1002 */
1003#include "clearstate_defs.h"
1004
1005struct radeon_rlc {
1006 /* for power gating */
1007 struct radeon_bo *save_restore_obj;
1008 uint64_t save_restore_gpu_addr;
1009 volatile uint32_t *sr_ptr;
1010 const u32 *reg_list;
1011 u32 reg_list_size;
1012 /* for clear state */
1013 struct radeon_bo *clear_state_obj;
1014 uint64_t clear_state_gpu_addr;
1015 volatile uint32_t *cs_ptr;
1016 const struct cs_section_def *cs_data;
1017 u32 clear_state_size;
1018 /* for cp tables */
1019 struct radeon_bo *cp_table_obj;
1020 uint64_t cp_table_gpu_addr;
1021 volatile uint32_t *cp_table_ptr;
1022 u32 cp_table_size;
1023};
1024
1025int radeon_ib_get(struct radeon_device *rdev, int ring,
1026 struct radeon_ib *ib, struct radeon_vm *vm,
1027 unsigned size);
1028void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
1029int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1030 struct radeon_ib *const_ib, bool hdp_flush);
1031int radeon_ib_pool_init(struct radeon_device *rdev);
1032void radeon_ib_pool_fini(struct radeon_device *rdev);
1033int radeon_ib_ring_tests(struct radeon_device *rdev);
1034/* Ring access between begin & end cannot sleep */
1035bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1036 struct radeon_ring *ring);
1037void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1038int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1039int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1040void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1041 bool hdp_flush);
1042void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1043 bool hdp_flush);
1044void radeon_ring_undo(struct radeon_ring *ring);
1045void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1046int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1047void radeon_ring_lockup_update(struct radeon_device *rdev,
1048 struct radeon_ring *ring);
1049bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1050unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1051 uint32_t **data);
1052int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1053 unsigned size, uint32_t *data);
1054int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1055 unsigned rptr_offs, u32 nop);
1056void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1057
1058
1059/* r600 async dma */
1060void r600_dma_stop(struct radeon_device *rdev);
1061int r600_dma_resume(struct radeon_device *rdev);
1062void r600_dma_fini(struct radeon_device *rdev);
1063
1064void cayman_dma_stop(struct radeon_device *rdev);
1065int cayman_dma_resume(struct radeon_device *rdev);
1066void cayman_dma_fini(struct radeon_device *rdev);
1067
1068/*
1069 * CS.
1070 */
1071struct radeon_cs_chunk {
1072 uint32_t length_dw;
1073 uint32_t *kdata;
1074 void __user *user_ptr;
1075};
1076
1077struct radeon_cs_parser {
1078 struct device *dev;
1079 struct radeon_device *rdev;
1080 struct drm_file *filp;
1081 /* chunks */
1082 unsigned nchunks;
1083 struct radeon_cs_chunk *chunks;
1084 uint64_t *chunks_array;
1085 /* IB */
1086 unsigned idx;
1087 /* relocations */
1088 unsigned nrelocs;
1089 struct radeon_bo_list *relocs;
1090 struct radeon_bo_list *vm_bos;
1091 struct list_head validated;
1092 unsigned dma_reloc_idx;
1093 /* indices of various chunks */
1094 struct radeon_cs_chunk *chunk_ib;
1095 struct radeon_cs_chunk *chunk_relocs;
1096 struct radeon_cs_chunk *chunk_flags;
1097 struct radeon_cs_chunk *chunk_const_ib;
1098 struct radeon_ib ib;
1099 struct radeon_ib const_ib;
1100 void *track;
1101 unsigned family;
1102 int parser_error;
1103 u32 cs_flags;
1104 u32 ring;
1105 s32 priority;
1106 struct ww_acquire_ctx ticket;
1107};
1108
1109static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1110{
1111 struct radeon_cs_chunk *ibc = p->chunk_ib;
1112
1113 if (ibc->kdata)
1114 return ibc->kdata[idx];
1115 return p->ib.ptr[idx];
1116}
1117
1118
1119struct radeon_cs_packet {
1120 unsigned idx;
1121 unsigned type;
1122 unsigned reg;
1123 unsigned opcode;
1124 int count;
1125 unsigned one_reg_wr;
1126};
1127
1128typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1129 struct radeon_cs_packet *pkt,
1130 unsigned idx, unsigned reg);
1131typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1132 struct radeon_cs_packet *pkt);
1133
1134
1135/*
1136 * AGP
1137 */
1138int radeon_agp_init(struct radeon_device *rdev);
1139void radeon_agp_resume(struct radeon_device *rdev);
1140void radeon_agp_suspend(struct radeon_device *rdev);
1141void radeon_agp_fini(struct radeon_device *rdev);
1142
1143
1144/*
1145 * Writeback
1146 */
1147struct radeon_wb {
1148 struct radeon_bo *wb_obj;
1149 volatile uint32_t *wb;
1150 uint64_t gpu_addr;
1151 bool enabled;
1152 bool use_event;
1153};
1154
1155#define RADEON_WB_SCRATCH_OFFSET 0
1156#define RADEON_WB_RING0_NEXT_RPTR 256
1157#define RADEON_WB_CP_RPTR_OFFSET 1024
1158#define RADEON_WB_CP1_RPTR_OFFSET 1280
1159#define RADEON_WB_CP2_RPTR_OFFSET 1536
1160#define R600_WB_DMA_RPTR_OFFSET 1792
1161#define R600_WB_IH_WPTR_OFFSET 2048
1162#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1163#define R600_WB_EVENT_OFFSET 3072
1164#define CIK_WB_CP1_WPTR_OFFSET 3328
1165#define CIK_WB_CP2_WPTR_OFFSET 3584
1166#define R600_WB_DMA_RING_TEST_OFFSET 3588
1167#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1168
1169/**
1170 * struct radeon_pm - power management datas
1171 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1172 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1173 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1174 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1175 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1176 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1177 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1178 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1179 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1180 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1181 * @needed_bandwidth: current bandwidth needs
1182 *
1183 * It keeps track of various data needed to take powermanagement decision.
1184 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1185 * Equation between gpu/memory clock and available bandwidth is hw dependent
1186 * (type of memory, bus size, efficiency, ...)
1187 */
1188
1189enum radeon_pm_method {
1190 PM_METHOD_PROFILE,
1191 PM_METHOD_DYNPM,
1192 PM_METHOD_DPM,
1193};
1194
1195enum radeon_dynpm_state {
1196 DYNPM_STATE_DISABLED,
1197 DYNPM_STATE_MINIMUM,
1198 DYNPM_STATE_PAUSED,
1199 DYNPM_STATE_ACTIVE,
1200 DYNPM_STATE_SUSPENDED,
1201};
1202enum radeon_dynpm_action {
1203 DYNPM_ACTION_NONE,
1204 DYNPM_ACTION_MINIMUM,
1205 DYNPM_ACTION_DOWNCLOCK,
1206 DYNPM_ACTION_UPCLOCK,
1207 DYNPM_ACTION_DEFAULT
1208};
1209
1210enum radeon_voltage_type {
1211 VOLTAGE_NONE = 0,
1212 VOLTAGE_GPIO,
1213 VOLTAGE_VDDC,
1214 VOLTAGE_SW
1215};
1216
1217enum radeon_pm_state_type {
1218 /* not used for dpm */
1219 POWER_STATE_TYPE_DEFAULT,
1220 POWER_STATE_TYPE_POWERSAVE,
1221 /* user selectable states */
1222 POWER_STATE_TYPE_BATTERY,
1223 POWER_STATE_TYPE_BALANCED,
1224 POWER_STATE_TYPE_PERFORMANCE,
1225 /* internal states */
1226 POWER_STATE_TYPE_INTERNAL_UVD,
1227 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1228 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1229 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1230 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1231 POWER_STATE_TYPE_INTERNAL_BOOT,
1232 POWER_STATE_TYPE_INTERNAL_THERMAL,
1233 POWER_STATE_TYPE_INTERNAL_ACPI,
1234 POWER_STATE_TYPE_INTERNAL_ULV,
1235 POWER_STATE_TYPE_INTERNAL_3DPERF,
1236};
1237
1238enum radeon_pm_profile_type {
1239 PM_PROFILE_DEFAULT,
1240 PM_PROFILE_AUTO,
1241 PM_PROFILE_LOW,
1242 PM_PROFILE_MID,
1243 PM_PROFILE_HIGH,
1244};
1245
1246#define PM_PROFILE_DEFAULT_IDX 0
1247#define PM_PROFILE_LOW_SH_IDX 1
1248#define PM_PROFILE_MID_SH_IDX 2
1249#define PM_PROFILE_HIGH_SH_IDX 3
1250#define PM_PROFILE_LOW_MH_IDX 4
1251#define PM_PROFILE_MID_MH_IDX 5
1252#define PM_PROFILE_HIGH_MH_IDX 6
1253#define PM_PROFILE_MAX 7
1254
1255struct radeon_pm_profile {
1256 int dpms_off_ps_idx;
1257 int dpms_on_ps_idx;
1258 int dpms_off_cm_idx;
1259 int dpms_on_cm_idx;
1260};
1261
1262enum radeon_int_thermal_type {
1263 THERMAL_TYPE_NONE,
1264 THERMAL_TYPE_EXTERNAL,
1265 THERMAL_TYPE_EXTERNAL_GPIO,
1266 THERMAL_TYPE_RV6XX,
1267 THERMAL_TYPE_RV770,
1268 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1269 THERMAL_TYPE_EVERGREEN,
1270 THERMAL_TYPE_SUMO,
1271 THERMAL_TYPE_NI,
1272 THERMAL_TYPE_SI,
1273 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1274 THERMAL_TYPE_CI,
1275 THERMAL_TYPE_KV,
1276};
1277
1278struct radeon_voltage {
1279 enum radeon_voltage_type type;
1280 /* gpio voltage */
1281 struct radeon_gpio_rec gpio;
1282 u32 delay; /* delay in usec from voltage drop to sclk change */
1283 bool active_high; /* voltage drop is active when bit is high */
1284 /* VDDC voltage */
1285 u8 vddc_id; /* index into vddc voltage table */
1286 u8 vddci_id; /* index into vddci voltage table */
1287 bool vddci_enabled;
1288 /* r6xx+ sw */
1289 u16 voltage;
1290 /* evergreen+ vddci */
1291 u16 vddci;
1292};
1293
1294/* clock mode flags */
1295#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1296
1297struct radeon_pm_clock_info {
1298 /* memory clock */
1299 u32 mclk;
1300 /* engine clock */
1301 u32 sclk;
1302 /* voltage info */
1303 struct radeon_voltage voltage;
1304 /* standardized clock flags */
1305 u32 flags;
1306};
1307
1308/* state flags */
1309#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1310
1311struct radeon_power_state {
1312 enum radeon_pm_state_type type;
1313 struct radeon_pm_clock_info *clock_info;
1314 /* number of valid clock modes in this power state */
1315 int num_clock_modes;
1316 struct radeon_pm_clock_info *default_clock_mode;
1317 /* standardized state flags */
1318 u32 flags;
1319 u32 misc; /* vbios specific flags */
1320 u32 misc2; /* vbios specific flags */
1321 int pcie_lanes; /* pcie lanes */
1322};
1323
1324/*
1325 * Some modes are overclocked by very low value, accept them
1326 */
1327#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1328
1329enum radeon_dpm_auto_throttle_src {
1330 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1331 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1332};
1333
1334enum radeon_dpm_event_src {
1335 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1336 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1337 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1338 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1339 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1340};
1341
1342#define RADEON_MAX_VCE_LEVELS 6
1343
1344enum radeon_vce_level {
1345 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1346 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1347 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1348 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1349 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1350 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1351};
1352
1353struct radeon_ps {
1354 u32 caps; /* vbios flags */
1355 u32 class; /* vbios flags */
1356 u32 class2; /* vbios flags */
1357 /* UVD clocks */
1358 u32 vclk;
1359 u32 dclk;
1360 /* VCE clocks */
1361 u32 evclk;
1362 u32 ecclk;
1363 bool vce_active;
1364 enum radeon_vce_level vce_level;
1365 /* asic priv */
1366 void *ps_priv;
1367};
1368
1369struct radeon_dpm_thermal {
1370 /* thermal interrupt work */
1371 struct work_struct work;
1372 /* low temperature threshold */
1373 int min_temp;
1374 /* high temperature threshold */
1375 int max_temp;
1376 /* was interrupt low to high or high to low */
1377 bool high_to_low;
1378};
1379
1380enum radeon_clk_action
1381{
1382 RADEON_SCLK_UP = 1,
1383 RADEON_SCLK_DOWN
1384};
1385
1386struct radeon_blacklist_clocks
1387{
1388 u32 sclk;
1389 u32 mclk;
1390 enum radeon_clk_action action;
1391};
1392
1393struct radeon_clock_and_voltage_limits {
1394 u32 sclk;
1395 u32 mclk;
1396 u16 vddc;
1397 u16 vddci;
1398};
1399
1400struct radeon_clock_array {
1401 u32 count;
1402 u32 *values;
1403};
1404
1405struct radeon_clock_voltage_dependency_entry {
1406 u32 clk;
1407 u16 v;
1408};
1409
1410struct radeon_clock_voltage_dependency_table {
1411 u32 count;
1412 struct radeon_clock_voltage_dependency_entry *entries;
1413};
1414
1415union radeon_cac_leakage_entry {
1416 struct {
1417 u16 vddc;
1418 u32 leakage;
1419 };
1420 struct {
1421 u16 vddc1;
1422 u16 vddc2;
1423 u16 vddc3;
1424 };
1425};
1426
1427struct radeon_cac_leakage_table {
1428 u32 count;
1429 union radeon_cac_leakage_entry *entries;
1430};
1431
1432struct radeon_phase_shedding_limits_entry {
1433 u16 voltage;
1434 u32 sclk;
1435 u32 mclk;
1436};
1437
1438struct radeon_phase_shedding_limits_table {
1439 u32 count;
1440 struct radeon_phase_shedding_limits_entry *entries;
1441};
1442
1443struct radeon_uvd_clock_voltage_dependency_entry {
1444 u32 vclk;
1445 u32 dclk;
1446 u16 v;
1447};
1448
1449struct radeon_uvd_clock_voltage_dependency_table {
1450 u8 count;
1451 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1452};
1453
1454struct radeon_vce_clock_voltage_dependency_entry {
1455 u32 ecclk;
1456 u32 evclk;
1457 u16 v;
1458};
1459
1460struct radeon_vce_clock_voltage_dependency_table {
1461 u8 count;
1462 struct radeon_vce_clock_voltage_dependency_entry *entries;
1463};
1464
1465struct radeon_ppm_table {
1466 u8 ppm_design;
1467 u16 cpu_core_number;
1468 u32 platform_tdp;
1469 u32 small_ac_platform_tdp;
1470 u32 platform_tdc;
1471 u32 small_ac_platform_tdc;
1472 u32 apu_tdp;
1473 u32 dgpu_tdp;
1474 u32 dgpu_ulv_power;
1475 u32 tj_max;
1476};
1477
1478struct radeon_cac_tdp_table {
1479 u16 tdp;
1480 u16 configurable_tdp;
1481 u16 tdc;
1482 u16 battery_power_limit;
1483 u16 small_power_limit;
1484 u16 low_cac_leakage;
1485 u16 high_cac_leakage;
1486 u16 maximum_power_delivery_limit;
1487};
1488
1489struct radeon_dpm_dynamic_state {
1490 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1491 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1492 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1493 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1494 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1495 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1496 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1497 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1498 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1499 struct radeon_clock_array valid_sclk_values;
1500 struct radeon_clock_array valid_mclk_values;
1501 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1502 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1503 u32 mclk_sclk_ratio;
1504 u32 sclk_mclk_delta;
1505 u16 vddc_vddci_delta;
1506 u16 min_vddc_for_pcie_gen2;
1507 struct radeon_cac_leakage_table cac_leakage_table;
1508 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1509 struct radeon_ppm_table *ppm_table;
1510 struct radeon_cac_tdp_table *cac_tdp_table;
1511};
1512
1513struct radeon_dpm_fan {
1514 u16 t_min;
1515 u16 t_med;
1516 u16 t_high;
1517 u16 pwm_min;
1518 u16 pwm_med;
1519 u16 pwm_high;
1520 u8 t_hyst;
1521 u32 cycle_delay;
1522 u16 t_max;
1523 u8 control_mode;
1524 u16 default_max_fan_pwm;
1525 u16 default_fan_output_sensitivity;
1526 u16 fan_output_sensitivity;
1527 bool ucode_fan_control;
1528};
1529
1530enum radeon_pcie_gen {
1531 RADEON_PCIE_GEN1 = 0,
1532 RADEON_PCIE_GEN2 = 1,
1533 RADEON_PCIE_GEN3 = 2,
1534 RADEON_PCIE_GEN_INVALID = 0xffff
1535};
1536
1537enum radeon_dpm_forced_level {
1538 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1539 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1540 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1541};
1542
1543struct radeon_vce_state {
1544 /* vce clocks */
1545 u32 evclk;
1546 u32 ecclk;
1547 /* gpu clocks */
1548 u32 sclk;
1549 u32 mclk;
1550 u8 clk_idx;
1551 u8 pstate;
1552};
1553
1554struct radeon_dpm {
1555 struct radeon_ps *ps;
1556 /* number of valid power states */
1557 int num_ps;
1558 /* current power state that is active */
1559 struct radeon_ps *current_ps;
1560 /* requested power state */
1561 struct radeon_ps *requested_ps;
1562 /* boot up power state */
1563 struct radeon_ps *boot_ps;
1564 /* default uvd power state */
1565 struct radeon_ps *uvd_ps;
1566 /* vce requirements */
1567 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1568 enum radeon_vce_level vce_level;
1569 enum radeon_pm_state_type state;
1570 enum radeon_pm_state_type user_state;
1571 u32 platform_caps;
1572 u32 voltage_response_time;
1573 u32 backbias_response_time;
1574 void *priv;
1575 u32 new_active_crtcs;
1576 int new_active_crtc_count;
1577 u32 current_active_crtcs;
1578 int current_active_crtc_count;
1579 bool single_display;
1580 struct radeon_dpm_dynamic_state dyn_state;
1581 struct radeon_dpm_fan fan;
1582 u32 tdp_limit;
1583 u32 near_tdp_limit;
1584 u32 near_tdp_limit_adjusted;
1585 u32 sq_ramping_threshold;
1586 u32 cac_leakage;
1587 u16 tdp_od_limit;
1588 u32 tdp_adjustment;
1589 u16 load_line_slope;
1590 bool power_control;
1591 bool ac_power;
1592 /* special states active */
1593 bool thermal_active;
1594 bool uvd_active;
1595 bool vce_active;
1596 /* thermal handling */
1597 struct radeon_dpm_thermal thermal;
1598 /* forced levels */
1599 enum radeon_dpm_forced_level forced_level;
1600 /* track UVD streams */
1601 unsigned sd;
1602 unsigned hd;
1603};
1604
1605void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1606void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1607
1608struct radeon_pm {
1609 struct mutex mutex;
1610 /* write locked while reprogramming mclk */
1611 struct rw_semaphore mclk_lock;
1612 u32 active_crtcs;
1613 int active_crtc_count;
1614 int req_vblank;
1615 bool vblank_sync;
1616 fixed20_12 max_bandwidth;
1617 fixed20_12 igp_sideport_mclk;
1618 fixed20_12 igp_system_mclk;
1619 fixed20_12 igp_ht_link_clk;
1620 fixed20_12 igp_ht_link_width;
1621 fixed20_12 k8_bandwidth;
1622 fixed20_12 sideport_bandwidth;
1623 fixed20_12 ht_bandwidth;
1624 fixed20_12 core_bandwidth;
1625 fixed20_12 sclk;
1626 fixed20_12 mclk;
1627 fixed20_12 needed_bandwidth;
1628 struct radeon_power_state *power_state;
1629 /* number of valid power states */
1630 int num_power_states;
1631 int current_power_state_index;
1632 int current_clock_mode_index;
1633 int requested_power_state_index;
1634 int requested_clock_mode_index;
1635 int default_power_state_index;
1636 u32 current_sclk;
1637 u32 current_mclk;
1638 u16 current_vddc;
1639 u16 current_vddci;
1640 u32 default_sclk;
1641 u32 default_mclk;
1642 u16 default_vddc;
1643 u16 default_vddci;
1644 struct radeon_i2c_chan *i2c_bus;
1645 /* selected pm method */
1646 enum radeon_pm_method pm_method;
1647 /* dynpm power management */
1648 struct delayed_work dynpm_idle_work;
1649 enum radeon_dynpm_state dynpm_state;
1650 enum radeon_dynpm_action dynpm_planned_action;
1651 unsigned long dynpm_action_timeout;
1652 bool dynpm_can_upclock;
1653 bool dynpm_can_downclock;
1654 /* profile-based power management */
1655 enum radeon_pm_profile_type profile;
1656 int profile_index;
1657 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1658 /* internal thermal controller on rv6xx+ */
1659 enum radeon_int_thermal_type int_thermal_type;
1660 struct device *int_hwmon_dev;
1661 /* fan control parameters */
1662 bool no_fan;
1663 u8 fan_pulses_per_revolution;
1664 u8 fan_min_rpm;
1665 u8 fan_max_rpm;
1666 /* dpm */
1667 bool dpm_enabled;
1668 bool sysfs_initialized;
1669 struct radeon_dpm dpm;
1670};
1671
1672int radeon_pm_get_type_index(struct radeon_device *rdev,
1673 enum radeon_pm_state_type ps_type,
1674 int instance);
1675/*
1676 * UVD
1677 */
1678#define RADEON_DEFAULT_UVD_HANDLES 10
1679#define RADEON_MAX_UVD_HANDLES 30
1680#define RADEON_UVD_STACK_SIZE (200*1024)
1681#define RADEON_UVD_HEAP_SIZE (256*1024)
1682#define RADEON_UVD_SESSION_SIZE (50*1024)
1683
1684struct radeon_uvd {
1685 bool fw_header_present;
1686 struct radeon_bo *vcpu_bo;
1687 void *cpu_addr;
1688 uint64_t gpu_addr;
1689 unsigned max_handles;
1690 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1691 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1692 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1693 struct delayed_work idle_work;
1694};
1695
1696int radeon_uvd_init(struct radeon_device *rdev);
1697void radeon_uvd_fini(struct radeon_device *rdev);
1698int radeon_uvd_suspend(struct radeon_device *rdev);
1699int radeon_uvd_resume(struct radeon_device *rdev);
1700int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1701 uint32_t handle, struct radeon_fence **fence);
1702int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1703 uint32_t handle, struct radeon_fence **fence);
1704void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1705 uint32_t allowed_domains);
1706void radeon_uvd_free_handles(struct radeon_device *rdev,
1707 struct drm_file *filp);
1708int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1709void radeon_uvd_note_usage(struct radeon_device *rdev);
1710int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1711 unsigned vclk, unsigned dclk,
1712 unsigned vco_min, unsigned vco_max,
1713 unsigned fb_factor, unsigned fb_mask,
1714 unsigned pd_min, unsigned pd_max,
1715 unsigned pd_even,
1716 unsigned *optimal_fb_div,
1717 unsigned *optimal_vclk_div,
1718 unsigned *optimal_dclk_div);
1719int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1720 unsigned cg_upll_func_cntl);
1721
1722/*
1723 * VCE
1724 */
1725#define RADEON_MAX_VCE_HANDLES 16
1726
1727struct radeon_vce {
1728 struct radeon_bo *vcpu_bo;
1729 uint64_t gpu_addr;
1730 unsigned fw_version;
1731 unsigned fb_version;
1732 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1733 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1734 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1735 struct delayed_work idle_work;
1736 uint32_t keyselect;
1737};
1738
1739int radeon_vce_init(struct radeon_device *rdev);
1740void radeon_vce_fini(struct radeon_device *rdev);
1741int radeon_vce_suspend(struct radeon_device *rdev);
1742int radeon_vce_resume(struct radeon_device *rdev);
1743int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1744 uint32_t handle, struct radeon_fence **fence);
1745int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1746 uint32_t handle, struct radeon_fence **fence);
1747void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1748void radeon_vce_note_usage(struct radeon_device *rdev);
1749int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1750int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1751bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1752 struct radeon_ring *ring,
1753 struct radeon_semaphore *semaphore,
1754 bool emit_wait);
1755void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1756void radeon_vce_fence_emit(struct radeon_device *rdev,
1757 struct radeon_fence *fence);
1758int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1759int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1760
1761struct r600_audio_pin {
1762 int channels;
1763 int rate;
1764 int bits_per_sample;
1765 u8 status_bits;
1766 u8 category_code;
1767 u32 offset;
1768 bool connected;
1769 u32 id;
1770};
1771
1772struct r600_audio {
1773 bool enabled;
1774 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1775 int num_pins;
1776 struct radeon_audio_funcs *hdmi_funcs;
1777 struct radeon_audio_funcs *dp_funcs;
1778 struct radeon_audio_basic_funcs *funcs;
1779};
1780
1781/*
1782 * Benchmarking
1783 */
1784void radeon_benchmark(struct radeon_device *rdev, int test_number);
1785
1786
1787/*
1788 * Testing
1789 */
1790void radeon_test_moves(struct radeon_device *rdev);
1791void radeon_test_ring_sync(struct radeon_device *rdev,
1792 struct radeon_ring *cpA,
1793 struct radeon_ring *cpB);
1794void radeon_test_syncing(struct radeon_device *rdev);
1795
1796/*
1797 * MMU Notifier
1798 */
1799#if defined(CONFIG_MMU_NOTIFIER)
1800int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1801void radeon_mn_unregister(struct radeon_bo *bo);
1802#else
1803static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1804{
1805 return -ENODEV;
1806}
1807static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1808#endif
1809
1810/*
1811 * Debugfs
1812 */
1813struct radeon_debugfs {
1814 struct drm_info_list *files;
1815 unsigned num_files;
1816};
1817
1818int radeon_debugfs_add_files(struct radeon_device *rdev,
1819 struct drm_info_list *files,
1820 unsigned nfiles);
1821int radeon_debugfs_fence_init(struct radeon_device *rdev);
1822
1823/*
1824 * ASIC ring specific functions.
1825 */
1826struct radeon_asic_ring {
1827 /* ring read/write ptr handling */
1828 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1829 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1830 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1831
1832 /* validating and patching of IBs */
1833 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1834 int (*cs_parse)(struct radeon_cs_parser *p);
1835
1836 /* command emmit functions */
1837 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1838 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1839 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1840 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1841 struct radeon_semaphore *semaphore, bool emit_wait);
1842 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1843 unsigned vm_id, uint64_t pd_addr);
1844
1845 /* testing functions */
1846 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1847 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1848 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1849
1850 /* deprecated */
1851 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1852};
1853
1854/*
1855 * ASIC specific functions.
1856 */
1857struct radeon_asic {
1858 int (*init)(struct radeon_device *rdev);
1859 void (*fini)(struct radeon_device *rdev);
1860 int (*resume)(struct radeon_device *rdev);
1861 int (*suspend)(struct radeon_device *rdev);
1862 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1863 int (*asic_reset)(struct radeon_device *rdev, bool hard);
1864 /* Flush the HDP cache via MMIO */
1865 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1866 /* check if 3D engine is idle */
1867 bool (*gui_idle)(struct radeon_device *rdev);
1868 /* wait for mc_idle */
1869 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1870 /* get the reference clock */
1871 u32 (*get_xclk)(struct radeon_device *rdev);
1872 /* get the gpu clock counter */
1873 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1874 /* get register for info ioctl */
1875 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
1876 /* gart */
1877 struct {
1878 void (*tlb_flush)(struct radeon_device *rdev);
1879 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
1880 void (*set_page)(struct radeon_device *rdev, unsigned i,
1881 uint64_t entry);
1882 } gart;
1883 struct {
1884 int (*init)(struct radeon_device *rdev);
1885 void (*fini)(struct radeon_device *rdev);
1886 void (*copy_pages)(struct radeon_device *rdev,
1887 struct radeon_ib *ib,
1888 uint64_t pe, uint64_t src,
1889 unsigned count);
1890 void (*write_pages)(struct radeon_device *rdev,
1891 struct radeon_ib *ib,
1892 uint64_t pe,
1893 uint64_t addr, unsigned count,
1894 uint32_t incr, uint32_t flags);
1895 void (*set_pages)(struct radeon_device *rdev,
1896 struct radeon_ib *ib,
1897 uint64_t pe,
1898 uint64_t addr, unsigned count,
1899 uint32_t incr, uint32_t flags);
1900 void (*pad_ib)(struct radeon_ib *ib);
1901 } vm;
1902 /* ring specific callbacks */
1903 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1904 /* irqs */
1905 struct {
1906 int (*set)(struct radeon_device *rdev);
1907 int (*process)(struct radeon_device *rdev);
1908 } irq;
1909 /* displays */
1910 struct {
1911 /* display watermarks */
1912 void (*bandwidth_update)(struct radeon_device *rdev);
1913 /* get frame count */
1914 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1915 /* wait for vblank */
1916 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1917 /* set backlight level */
1918 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1919 /* get backlight level */
1920 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1921 /* audio callbacks */
1922 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1923 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1924 } display;
1925 /* copy functions for bo handling */
1926 struct {
1927 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1928 uint64_t src_offset,
1929 uint64_t dst_offset,
1930 unsigned num_gpu_pages,
1931 struct reservation_object *resv);
1932 u32 blit_ring_index;
1933 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1934 uint64_t src_offset,
1935 uint64_t dst_offset,
1936 unsigned num_gpu_pages,
1937 struct reservation_object *resv);
1938 u32 dma_ring_index;
1939 /* method used for bo copy */
1940 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1941 uint64_t src_offset,
1942 uint64_t dst_offset,
1943 unsigned num_gpu_pages,
1944 struct reservation_object *resv);
1945 /* ring used for bo copies */
1946 u32 copy_ring_index;
1947 } copy;
1948 /* surfaces */
1949 struct {
1950 int (*set_reg)(struct radeon_device *rdev, int reg,
1951 uint32_t tiling_flags, uint32_t pitch,
1952 uint32_t offset, uint32_t obj_size);
1953 void (*clear_reg)(struct radeon_device *rdev, int reg);
1954 } surface;
1955 /* hotplug detect */
1956 struct {
1957 void (*init)(struct radeon_device *rdev);
1958 void (*fini)(struct radeon_device *rdev);
1959 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1960 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1961 } hpd;
1962 /* static power management */
1963 struct {
1964 void (*misc)(struct radeon_device *rdev);
1965 void (*prepare)(struct radeon_device *rdev);
1966 void (*finish)(struct radeon_device *rdev);
1967 void (*init_profile)(struct radeon_device *rdev);
1968 void (*get_dynpm_state)(struct radeon_device *rdev);
1969 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1970 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1971 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1972 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1973 int (*get_pcie_lanes)(struct radeon_device *rdev);
1974 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1975 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1976 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1977 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1978 int (*get_temperature)(struct radeon_device *rdev);
1979 } pm;
1980 /* dynamic power management */
1981 struct {
1982 int (*init)(struct radeon_device *rdev);
1983 void (*setup_asic)(struct radeon_device *rdev);
1984 int (*enable)(struct radeon_device *rdev);
1985 int (*late_enable)(struct radeon_device *rdev);
1986 void (*disable)(struct radeon_device *rdev);
1987 int (*pre_set_power_state)(struct radeon_device *rdev);
1988 int (*set_power_state)(struct radeon_device *rdev);
1989 void (*post_set_power_state)(struct radeon_device *rdev);
1990 void (*display_configuration_changed)(struct radeon_device *rdev);
1991 void (*fini)(struct radeon_device *rdev);
1992 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1993 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1994 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1995 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1996 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1997 bool (*vblank_too_short)(struct radeon_device *rdev);
1998 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1999 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
2000 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
2001 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
2002 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
2003 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
2004 u32 (*get_current_sclk)(struct radeon_device *rdev);
2005 u32 (*get_current_mclk)(struct radeon_device *rdev);
2006 } dpm;
2007 /* pageflipping */
2008 struct {
2009 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async);
2010 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
2011 } pflip;
2012};
2013
2014/*
2015 * Asic structures
2016 */
2017struct r100_asic {
2018 const unsigned *reg_safe_bm;
2019 unsigned reg_safe_bm_size;
2020 u32 hdp_cntl;
2021};
2022
2023struct r300_asic {
2024 const unsigned *reg_safe_bm;
2025 unsigned reg_safe_bm_size;
2026 u32 resync_scratch;
2027 u32 hdp_cntl;
2028};
2029
2030struct r600_asic {
2031 unsigned max_pipes;
2032 unsigned max_tile_pipes;
2033 unsigned max_simds;
2034 unsigned max_backends;
2035 unsigned max_gprs;
2036 unsigned max_threads;
2037 unsigned max_stack_entries;
2038 unsigned max_hw_contexts;
2039 unsigned max_gs_threads;
2040 unsigned sx_max_export_size;
2041 unsigned sx_max_export_pos_size;
2042 unsigned sx_max_export_smx_size;
2043 unsigned sq_num_cf_insts;
2044 unsigned tiling_nbanks;
2045 unsigned tiling_npipes;
2046 unsigned tiling_group_size;
2047 unsigned tile_config;
2048 unsigned backend_map;
2049 unsigned active_simds;
2050};
2051
2052struct rv770_asic {
2053 unsigned max_pipes;
2054 unsigned max_tile_pipes;
2055 unsigned max_simds;
2056 unsigned max_backends;
2057 unsigned max_gprs;
2058 unsigned max_threads;
2059 unsigned max_stack_entries;
2060 unsigned max_hw_contexts;
2061 unsigned max_gs_threads;
2062 unsigned sx_max_export_size;
2063 unsigned sx_max_export_pos_size;
2064 unsigned sx_max_export_smx_size;
2065 unsigned sq_num_cf_insts;
2066 unsigned sx_num_of_sets;
2067 unsigned sc_prim_fifo_size;
2068 unsigned sc_hiz_tile_fifo_size;
2069 unsigned sc_earlyz_tile_fifo_fize;
2070 unsigned tiling_nbanks;
2071 unsigned tiling_npipes;
2072 unsigned tiling_group_size;
2073 unsigned tile_config;
2074 unsigned backend_map;
2075 unsigned active_simds;
2076};
2077
2078struct evergreen_asic {
2079 unsigned num_ses;
2080 unsigned max_pipes;
2081 unsigned max_tile_pipes;
2082 unsigned max_simds;
2083 unsigned max_backends;
2084 unsigned max_gprs;
2085 unsigned max_threads;
2086 unsigned max_stack_entries;
2087 unsigned max_hw_contexts;
2088 unsigned max_gs_threads;
2089 unsigned sx_max_export_size;
2090 unsigned sx_max_export_pos_size;
2091 unsigned sx_max_export_smx_size;
2092 unsigned sq_num_cf_insts;
2093 unsigned sx_num_of_sets;
2094 unsigned sc_prim_fifo_size;
2095 unsigned sc_hiz_tile_fifo_size;
2096 unsigned sc_earlyz_tile_fifo_size;
2097 unsigned tiling_nbanks;
2098 unsigned tiling_npipes;
2099 unsigned tiling_group_size;
2100 unsigned tile_config;
2101 unsigned backend_map;
2102 unsigned active_simds;
2103};
2104
2105struct cayman_asic {
2106 unsigned max_shader_engines;
2107 unsigned max_pipes_per_simd;
2108 unsigned max_tile_pipes;
2109 unsigned max_simds_per_se;
2110 unsigned max_backends_per_se;
2111 unsigned max_texture_channel_caches;
2112 unsigned max_gprs;
2113 unsigned max_threads;
2114 unsigned max_gs_threads;
2115 unsigned max_stack_entries;
2116 unsigned sx_num_of_sets;
2117 unsigned sx_max_export_size;
2118 unsigned sx_max_export_pos_size;
2119 unsigned sx_max_export_smx_size;
2120 unsigned max_hw_contexts;
2121 unsigned sq_num_cf_insts;
2122 unsigned sc_prim_fifo_size;
2123 unsigned sc_hiz_tile_fifo_size;
2124 unsigned sc_earlyz_tile_fifo_size;
2125
2126 unsigned num_shader_engines;
2127 unsigned num_shader_pipes_per_simd;
2128 unsigned num_tile_pipes;
2129 unsigned num_simds_per_se;
2130 unsigned num_backends_per_se;
2131 unsigned backend_disable_mask_per_asic;
2132 unsigned backend_map;
2133 unsigned num_texture_channel_caches;
2134 unsigned mem_max_burst_length_bytes;
2135 unsigned mem_row_size_in_kb;
2136 unsigned shader_engine_tile_size;
2137 unsigned num_gpus;
2138 unsigned multi_gpu_tile_size;
2139
2140 unsigned tile_config;
2141 unsigned active_simds;
2142};
2143
2144struct si_asic {
2145 unsigned max_shader_engines;
2146 unsigned max_tile_pipes;
2147 unsigned max_cu_per_sh;
2148 unsigned max_sh_per_se;
2149 unsigned max_backends_per_se;
2150 unsigned max_texture_channel_caches;
2151 unsigned max_gprs;
2152 unsigned max_gs_threads;
2153 unsigned max_hw_contexts;
2154 unsigned sc_prim_fifo_size_frontend;
2155 unsigned sc_prim_fifo_size_backend;
2156 unsigned sc_hiz_tile_fifo_size;
2157 unsigned sc_earlyz_tile_fifo_size;
2158
2159 unsigned num_tile_pipes;
2160 unsigned backend_enable_mask;
2161 unsigned backend_disable_mask_per_asic;
2162 unsigned backend_map;
2163 unsigned num_texture_channel_caches;
2164 unsigned mem_max_burst_length_bytes;
2165 unsigned mem_row_size_in_kb;
2166 unsigned shader_engine_tile_size;
2167 unsigned num_gpus;
2168 unsigned multi_gpu_tile_size;
2169
2170 unsigned tile_config;
2171 uint32_t tile_mode_array[32];
2172 uint32_t active_cus;
2173};
2174
2175struct cik_asic {
2176 unsigned max_shader_engines;
2177 unsigned max_tile_pipes;
2178 unsigned max_cu_per_sh;
2179 unsigned max_sh_per_se;
2180 unsigned max_backends_per_se;
2181 unsigned max_texture_channel_caches;
2182 unsigned max_gprs;
2183 unsigned max_gs_threads;
2184 unsigned max_hw_contexts;
2185 unsigned sc_prim_fifo_size_frontend;
2186 unsigned sc_prim_fifo_size_backend;
2187 unsigned sc_hiz_tile_fifo_size;
2188 unsigned sc_earlyz_tile_fifo_size;
2189
2190 unsigned num_tile_pipes;
2191 unsigned backend_enable_mask;
2192 unsigned backend_disable_mask_per_asic;
2193 unsigned backend_map;
2194 unsigned num_texture_channel_caches;
2195 unsigned mem_max_burst_length_bytes;
2196 unsigned mem_row_size_in_kb;
2197 unsigned shader_engine_tile_size;
2198 unsigned num_gpus;
2199 unsigned multi_gpu_tile_size;
2200
2201 unsigned tile_config;
2202 uint32_t tile_mode_array[32];
2203 uint32_t macrotile_mode_array[16];
2204 uint32_t active_cus;
2205};
2206
2207union radeon_asic_config {
2208 struct r300_asic r300;
2209 struct r100_asic r100;
2210 struct r600_asic r600;
2211 struct rv770_asic rv770;
2212 struct evergreen_asic evergreen;
2213 struct cayman_asic cayman;
2214 struct si_asic si;
2215 struct cik_asic cik;
2216};
2217
2218/*
2219 * asic initizalization from radeon_asic.c
2220 */
2221void radeon_agp_disable(struct radeon_device *rdev);
2222int radeon_asic_init(struct radeon_device *rdev);
2223
2224
2225/*
2226 * IOCTL.
2227 */
2228int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2229 struct drm_file *filp);
2230int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2231 struct drm_file *filp);
2232int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2233 struct drm_file *filp);
2234int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2235 struct drm_file *file_priv);
2236int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2237 struct drm_file *file_priv);
2238int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2239 struct drm_file *file_priv);
2240int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2241 struct drm_file *file_priv);
2242int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2243 struct drm_file *filp);
2244int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2245 struct drm_file *filp);
2246int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2247 struct drm_file *filp);
2248int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2249 struct drm_file *filp);
2250int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2251 struct drm_file *filp);
2252int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2253 struct drm_file *filp);
2254int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2255int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2256 struct drm_file *filp);
2257int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2258 struct drm_file *filp);
2259
2260/* VRAM scratch page for HDP bug, default vram page */
2261struct r600_vram_scratch {
2262 struct radeon_bo *robj;
2263 volatile uint32_t *ptr;
2264 u64 gpu_addr;
2265};
2266
2267/*
2268 * ACPI
2269 */
2270struct radeon_atif_notification_cfg {
2271 bool enabled;
2272 int command_code;
2273};
2274
2275struct radeon_atif_notifications {
2276 bool display_switch;
2277 bool expansion_mode_change;
2278 bool thermal_state;
2279 bool forced_power_state;
2280 bool system_power_state;
2281 bool display_conf_change;
2282 bool px_gfx_switch;
2283 bool brightness_change;
2284 bool dgpu_display_event;
2285};
2286
2287struct radeon_atif_functions {
2288 bool system_params;
2289 bool sbios_requests;
2290 bool select_active_disp;
2291 bool lid_state;
2292 bool get_tv_standard;
2293 bool set_tv_standard;
2294 bool get_panel_expansion_mode;
2295 bool set_panel_expansion_mode;
2296 bool temperature_change;
2297 bool graphics_device_types;
2298};
2299
2300struct radeon_atif {
2301 struct radeon_atif_notifications notifications;
2302 struct radeon_atif_functions functions;
2303 struct radeon_atif_notification_cfg notification_cfg;
2304 struct radeon_encoder *encoder_for_bl;
2305};
2306
2307struct radeon_atcs_functions {
2308 bool get_ext_state;
2309 bool pcie_perf_req;
2310 bool pcie_dev_rdy;
2311 bool pcie_bus_width;
2312};
2313
2314struct radeon_atcs {
2315 struct radeon_atcs_functions functions;
2316};
2317
2318/*
2319 * Core structure, functions and helpers.
2320 */
2321typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2322typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2323
2324struct radeon_device {
2325 struct device *dev;
2326 struct drm_device *ddev;
2327 struct pci_dev *pdev;
2328 struct rw_semaphore exclusive_lock;
2329 /* ASIC */
2330 union radeon_asic_config config;
2331 enum radeon_family family;
2332 unsigned long flags;
2333 int usec_timeout;
2334 enum radeon_pll_errata pll_errata;
2335 int num_gb_pipes;
2336 int num_z_pipes;
2337 int disp_priority;
2338 /* BIOS */
2339 uint8_t *bios;
2340 bool is_atom_bios;
2341 uint16_t bios_header_start;
2342 struct radeon_bo *stollen_vga_memory;
2343 /* Register mmio */
2344 resource_size_t rmmio_base;
2345 resource_size_t rmmio_size;
2346 /* protects concurrent MM_INDEX/DATA based register access */
2347 spinlock_t mmio_idx_lock;
2348 /* protects concurrent SMC based register access */
2349 spinlock_t smc_idx_lock;
2350 /* protects concurrent PLL register access */
2351 spinlock_t pll_idx_lock;
2352 /* protects concurrent MC register access */
2353 spinlock_t mc_idx_lock;
2354 /* protects concurrent PCIE register access */
2355 spinlock_t pcie_idx_lock;
2356 /* protects concurrent PCIE_PORT register access */
2357 spinlock_t pciep_idx_lock;
2358 /* protects concurrent PIF register access */
2359 spinlock_t pif_idx_lock;
2360 /* protects concurrent CG register access */
2361 spinlock_t cg_idx_lock;
2362 /* protects concurrent UVD register access */
2363 spinlock_t uvd_idx_lock;
2364 /* protects concurrent RCU register access */
2365 spinlock_t rcu_idx_lock;
2366 /* protects concurrent DIDT register access */
2367 spinlock_t didt_idx_lock;
2368 /* protects concurrent ENDPOINT (audio) register access */
2369 spinlock_t end_idx_lock;
2370 void __iomem *rmmio;
2371 radeon_rreg_t mc_rreg;
2372 radeon_wreg_t mc_wreg;
2373 radeon_rreg_t pll_rreg;
2374 radeon_wreg_t pll_wreg;
2375 uint32_t pcie_reg_mask;
2376 radeon_rreg_t pciep_rreg;
2377 radeon_wreg_t pciep_wreg;
2378 /* io port */
2379 void __iomem *rio_mem;
2380 resource_size_t rio_mem_size;
2381 struct radeon_clock clock;
2382 struct radeon_mc mc;
2383 struct radeon_gart gart;
2384 struct radeon_mode_info mode_info;
2385 struct radeon_scratch scratch;
2386 struct radeon_doorbell doorbell;
2387 struct radeon_mman mman;
2388 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2389 wait_queue_head_t fence_queue;
2390 u64 fence_context;
2391 struct mutex ring_lock;
2392 struct radeon_ring ring[RADEON_NUM_RINGS];
2393 bool ib_pool_ready;
2394 struct radeon_sa_manager ring_tmp_bo;
2395 struct radeon_irq irq;
2396 struct radeon_asic *asic;
2397 struct radeon_gem gem;
2398 struct radeon_pm pm;
2399 struct radeon_uvd uvd;
2400 struct radeon_vce vce;
2401 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2402 struct radeon_wb wb;
2403 struct radeon_dummy_page dummy_page;
2404 bool shutdown;
2405 bool need_dma32;
2406 bool accel_working;
2407 bool fastfb_working; /* IGP feature*/
2408 bool needs_reset, in_reset;
2409 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2410 const struct firmware *me_fw; /* all family ME firmware */
2411 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2412 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2413 const struct firmware *mc_fw; /* NI MC firmware */
2414 const struct firmware *ce_fw; /* SI CE firmware */
2415 const struct firmware *mec_fw; /* CIK MEC firmware */
2416 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2417 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2418 const struct firmware *smc_fw; /* SMC firmware */
2419 const struct firmware *uvd_fw; /* UVD firmware */
2420 const struct firmware *vce_fw; /* VCE firmware */
2421 bool new_fw;
2422 struct r600_vram_scratch vram_scratch;
2423 int msi_enabled; /* msi enabled */
2424 struct r600_ih ih; /* r6/700 interrupt ring */
2425 struct radeon_rlc rlc;
2426 struct radeon_mec mec;
2427 struct delayed_work hotplug_work;
2428 struct work_struct dp_work;
2429 struct work_struct audio_work;
2430 int num_crtc; /* number of crtcs */
2431 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2432 bool has_uvd;
2433 bool has_vce;
2434 struct r600_audio audio; /* audio stuff */
2435 struct notifier_block acpi_nb;
2436 /* only one userspace can use Hyperz features or CMASK at a time */
2437 struct drm_file *hyperz_filp;
2438 struct drm_file *cmask_filp;
2439 /* i2c buses */
2440 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2441 /* debugfs */
2442 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2443 unsigned debugfs_count;
2444 /* virtual memory */
2445 struct radeon_vm_manager vm_manager;
2446 struct mutex gpu_clock_mutex;
2447 /* memory stats */
2448 atomic64_t vram_usage;
2449 atomic64_t gtt_usage;
2450 atomic64_t num_bytes_moved;
2451 atomic_t gpu_reset_counter;
2452 /* ACPI interface */
2453 struct radeon_atif atif;
2454 struct radeon_atcs atcs;
2455 /* srbm instance registers */
2456 struct mutex srbm_mutex;
2457 /* GRBM index mutex. Protects concurrents access to GRBM index */
2458 struct mutex grbm_idx_mutex;
2459 /* clock, powergating flags */
2460 u32 cg_flags;
2461 u32 pg_flags;
2462
2463 struct dev_pm_domain vga_pm_domain;
2464 bool have_disp_power_ref;
2465 u32 px_quirk_flags;
2466
2467 /* tracking pinned memory */
2468 u64 vram_pin_size;
2469 u64 gart_pin_size;
2470
2471 /* amdkfd interface */
2472 struct kfd_dev *kfd;
2473
2474 struct mutex mn_lock;
2475 DECLARE_HASHTABLE(mn_hash, 7);
2476};
2477
2478bool radeon_is_px(struct drm_device *dev);
2479int radeon_device_init(struct radeon_device *rdev,
2480 struct drm_device *ddev,
2481 struct pci_dev *pdev,
2482 uint32_t flags);
2483void radeon_device_fini(struct radeon_device *rdev);
2484int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2485
2486#define RADEON_MIN_MMIO_SIZE 0x10000
2487
2488uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2489void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2490static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2491 bool always_indirect)
2492{
2493 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2494 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2495 return readl(((void __iomem *)rdev->rmmio) + reg);
2496 else
2497 return r100_mm_rreg_slow(rdev, reg);
2498}
2499static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2500 bool always_indirect)
2501{
2502 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2503 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2504 else
2505 r100_mm_wreg_slow(rdev, reg, v);
2506}
2507
2508u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2509void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2510
2511u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2512void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2513
2514/*
2515 * Cast helper
2516 */
2517extern const struct dma_fence_ops radeon_fence_ops;
2518
2519static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f)
2520{
2521 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2522
2523 if (__f->base.ops == &radeon_fence_ops)
2524 return __f;
2525
2526 return NULL;
2527}
2528
2529/*
2530 * Registers read & write functions.
2531 */
2532#define RREG8(reg) readb((rdev->rmmio) + (reg))
2533#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2534#define RREG16(reg) readw((rdev->rmmio) + (reg))
2535#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2536#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2537#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2538#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2539#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2540#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2541#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2542#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2543#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2544#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2545#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2546#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2547#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2548#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2549#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2550#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2551#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2552#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2553#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2554#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2555#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2556#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2557#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2558#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2559#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2560#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2561#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2562#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2563#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2564#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2565#define WREG32_P(reg, val, mask) \
2566 do { \
2567 uint32_t tmp_ = RREG32(reg); \
2568 tmp_ &= (mask); \
2569 tmp_ |= ((val) & ~(mask)); \
2570 WREG32(reg, tmp_); \
2571 } while (0)
2572#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2573#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2574#define WREG32_PLL_P(reg, val, mask) \
2575 do { \
2576 uint32_t tmp_ = RREG32_PLL(reg); \
2577 tmp_ &= (mask); \
2578 tmp_ |= ((val) & ~(mask)); \
2579 WREG32_PLL(reg, tmp_); \
2580 } while (0)
2581#define WREG32_SMC_P(reg, val, mask) \
2582 do { \
2583 uint32_t tmp_ = RREG32_SMC(reg); \
2584 tmp_ &= (mask); \
2585 tmp_ |= ((val) & ~(mask)); \
2586 WREG32_SMC(reg, tmp_); \
2587 } while (0)
2588#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2589#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2590#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2591
2592#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2593#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2594
2595/*
2596 * Indirect registers accessors.
2597 * They used to be inlined, but this increases code size by ~65 kbytes.
2598 * Since each performs a pair of MMIO ops
2599 * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2600 * the cost of call+ret is almost negligible. MMIO and locking
2601 * costs several dozens of cycles each at best, call+ret is ~5 cycles.
2602 */
2603uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2604void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2605u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2606void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2607u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2608void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2609u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2610void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2611u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2612void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2613u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2614void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2615u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2616void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2617u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2618void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2619
2620void r100_pll_errata_after_index(struct radeon_device *rdev);
2621
2622
2623/*
2624 * ASICs helpers.
2625 */
2626#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2627 (rdev->pdev->device == 0x5969))
2628#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2629 (rdev->family == CHIP_RV200) || \
2630 (rdev->family == CHIP_RS100) || \
2631 (rdev->family == CHIP_RS200) || \
2632 (rdev->family == CHIP_RV250) || \
2633 (rdev->family == CHIP_RV280) || \
2634 (rdev->family == CHIP_RS300))
2635#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2636 (rdev->family == CHIP_RV350) || \
2637 (rdev->family == CHIP_R350) || \
2638 (rdev->family == CHIP_RV380) || \
2639 (rdev->family == CHIP_R420) || \
2640 (rdev->family == CHIP_R423) || \
2641 (rdev->family == CHIP_RV410) || \
2642 (rdev->family == CHIP_RS400) || \
2643 (rdev->family == CHIP_RS480))
2644#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2645 (rdev->ddev->pdev->device == 0x9443) || \
2646 (rdev->ddev->pdev->device == 0x944B) || \
2647 (rdev->ddev->pdev->device == 0x9506) || \
2648 (rdev->ddev->pdev->device == 0x9509) || \
2649 (rdev->ddev->pdev->device == 0x950F) || \
2650 (rdev->ddev->pdev->device == 0x689C) || \
2651 (rdev->ddev->pdev->device == 0x689D))
2652#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2653#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2654 (rdev->family == CHIP_RS690) || \
2655 (rdev->family == CHIP_RS740) || \
2656 (rdev->family >= CHIP_R600))
2657#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2658#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2659#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2660#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2661 (rdev->flags & RADEON_IS_IGP))
2662#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2663#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2664#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2665 (rdev->flags & RADEON_IS_IGP))
2666#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2667#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2668#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2669#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2670#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2671#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2672 (rdev->family == CHIP_MULLINS))
2673
2674#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2675 (rdev->ddev->pdev->device == 0x6850) || \
2676 (rdev->ddev->pdev->device == 0x6858) || \
2677 (rdev->ddev->pdev->device == 0x6859) || \
2678 (rdev->ddev->pdev->device == 0x6840) || \
2679 (rdev->ddev->pdev->device == 0x6841) || \
2680 (rdev->ddev->pdev->device == 0x6842) || \
2681 (rdev->ddev->pdev->device == 0x6843))
2682
2683/*
2684 * BIOS helpers.
2685 */
2686#define RBIOS8(i) (rdev->bios[i])
2687#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2688#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2689
2690int radeon_combios_init(struct radeon_device *rdev);
2691void radeon_combios_fini(struct radeon_device *rdev);
2692int radeon_atombios_init(struct radeon_device *rdev);
2693void radeon_atombios_fini(struct radeon_device *rdev);
2694
2695
2696/*
2697 * RING helpers.
2698 */
2699
2700/**
2701 * radeon_ring_write - write a value to the ring
2702 *
2703 * @ring: radeon_ring structure holding ring information
2704 * @v: dword (dw) value to write
2705 *
2706 * Write a value to the requested ring buffer (all asics).
2707 */
2708static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2709{
2710 if (ring->count_dw <= 0)
2711 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2712
2713 ring->ring[ring->wptr++] = v;
2714 ring->wptr &= ring->ptr_mask;
2715 ring->count_dw--;
2716 ring->ring_free_dw--;
2717}
2718
2719/*
2720 * ASICs macro.
2721 */
2722#define radeon_init(rdev) (rdev)->asic->init((rdev))
2723#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2724#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2725#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2726#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2727#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2728#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false)
2729#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2730#define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2731#define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2732#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2733#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2734#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2735#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2736#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2737#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2738#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2739#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2740#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2741#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2742#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2743#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2744#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2745#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2746#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2747#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2748#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2749#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2750#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2751#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2752#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2753#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2754#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2755#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2756#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2757#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2758#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2759#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2760#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2761#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2762#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2763#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2764#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2765#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2766#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2767#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2768#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2769#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2770#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2771#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2772#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2773#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2774#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2775#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2776#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2777#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2778#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2779#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2780#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2781#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2782#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2783#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2784#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2785#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2786#define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async))
2787#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2788#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2789#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2790#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2791#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2792#define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
2793#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2794#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2795#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2796#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2797#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2798#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2799#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2800#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2801#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2802#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2803#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2804#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2805#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2806#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2807#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2808#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2809#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2810#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2811#define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2812#define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
2813
2814/* Common functions */
2815/* AGP */
2816extern int radeon_gpu_reset(struct radeon_device *rdev);
2817extern void radeon_pci_config_reset(struct radeon_device *rdev);
2818extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2819extern void radeon_agp_disable(struct radeon_device *rdev);
2820extern int radeon_modeset_init(struct radeon_device *rdev);
2821extern void radeon_modeset_fini(struct radeon_device *rdev);
2822extern bool radeon_card_posted(struct radeon_device *rdev);
2823extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2824extern void radeon_update_display_priority(struct radeon_device *rdev);
2825extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2826extern void radeon_scratch_init(struct radeon_device *rdev);
2827extern void radeon_wb_fini(struct radeon_device *rdev);
2828extern int radeon_wb_init(struct radeon_device *rdev);
2829extern void radeon_wb_disable(struct radeon_device *rdev);
2830extern void radeon_surface_init(struct radeon_device *rdev);
2831extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2832extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2833extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2834extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2835extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2836extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2837 uint32_t flags);
2838extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2839extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
2840extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2841extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2842extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2843extern int radeon_suspend_kms(struct drm_device *dev, bool suspend,
2844 bool fbcon, bool freeze);
2845extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2846extern void radeon_program_register_sequence(struct radeon_device *rdev,
2847 const u32 *registers,
2848 const u32 array_size);
2849
2850/*
2851 * vm
2852 */
2853int radeon_vm_manager_init(struct radeon_device *rdev);
2854void radeon_vm_manager_fini(struct radeon_device *rdev);
2855int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2856void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2857struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
2858 struct radeon_vm *vm,
2859 struct list_head *head);
2860struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2861 struct radeon_vm *vm, int ring);
2862void radeon_vm_flush(struct radeon_device *rdev,
2863 struct radeon_vm *vm,
2864 int ring, struct radeon_fence *fence);
2865void radeon_vm_fence(struct radeon_device *rdev,
2866 struct radeon_vm *vm,
2867 struct radeon_fence *fence);
2868uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2869int radeon_vm_update_page_directory(struct radeon_device *rdev,
2870 struct radeon_vm *vm);
2871int radeon_vm_clear_freed(struct radeon_device *rdev,
2872 struct radeon_vm *vm);
2873int radeon_vm_clear_invalids(struct radeon_device *rdev,
2874 struct radeon_vm *vm);
2875int radeon_vm_bo_update(struct radeon_device *rdev,
2876 struct radeon_bo_va *bo_va,
2877 struct ttm_mem_reg *mem);
2878void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2879 struct radeon_bo *bo);
2880struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2881 struct radeon_bo *bo);
2882struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2883 struct radeon_vm *vm,
2884 struct radeon_bo *bo);
2885int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2886 struct radeon_bo_va *bo_va,
2887 uint64_t offset,
2888 uint32_t flags);
2889void radeon_vm_bo_rmv(struct radeon_device *rdev,
2890 struct radeon_bo_va *bo_va);
2891
2892/* audio */
2893void r600_audio_update_hdmi(struct work_struct *work);
2894struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2895struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2896void r600_audio_enable(struct radeon_device *rdev,
2897 struct r600_audio_pin *pin,
2898 u8 enable_mask);
2899void dce6_audio_enable(struct radeon_device *rdev,
2900 struct r600_audio_pin *pin,
2901 u8 enable_mask);
2902
2903/*
2904 * R600 vram scratch functions
2905 */
2906int r600_vram_scratch_init(struct radeon_device *rdev);
2907void r600_vram_scratch_fini(struct radeon_device *rdev);
2908
2909/*
2910 * r600 cs checking helper
2911 */
2912unsigned r600_mip_minify(unsigned size, unsigned level);
2913bool r600_fmt_is_valid_color(u32 format);
2914bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2915int r600_fmt_get_blocksize(u32 format);
2916int r600_fmt_get_nblocksx(u32 format, u32 w);
2917int r600_fmt_get_nblocksy(u32 format, u32 h);
2918
2919/*
2920 * r600 functions used by radeon_encoder.c
2921 */
2922struct radeon_hdmi_acr {
2923 u32 clock;
2924
2925 int n_32khz;
2926 int cts_32khz;
2927
2928 int n_44_1khz;
2929 int cts_44_1khz;
2930
2931 int n_48khz;
2932 int cts_48khz;
2933
2934};
2935
2936extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2937
2938extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2939 u32 tiling_pipe_num,
2940 u32 max_rb_num,
2941 u32 total_max_rb_num,
2942 u32 enabled_rb_mask);
2943
2944/*
2945 * evergreen functions used by radeon_encoder.c
2946 */
2947
2948extern int ni_init_microcode(struct radeon_device *rdev);
2949extern int ni_mc_load_microcode(struct radeon_device *rdev);
2950
2951/* radeon_acpi.c */
2952#if defined(CONFIG_ACPI)
2953extern int radeon_acpi_init(struct radeon_device *rdev);
2954extern void radeon_acpi_fini(struct radeon_device *rdev);
2955extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2956extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2957 u8 perf_req, bool advertise);
2958extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2959#else
2960static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2961static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2962#endif
2963
2964int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2965 struct radeon_cs_packet *pkt,
2966 unsigned idx);
2967bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2968void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2969 struct radeon_cs_packet *pkt);
2970int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2971 struct radeon_bo_list **cs_reloc,
2972 int nomm);
2973int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2974 uint32_t *vline_start_end,
2975 uint32_t *vline_status);
2976
2977#include "radeon_object.h"
2978
2979#endif