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1// SPDX-License-Identifier: GPL-2.0-only
2/******************************************************************************
3 * emulate.c
4 *
5 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
6 *
7 * Copyright (c) 2005 Keir Fraser
8 *
9 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
10 * privileged instructions:
11 *
12 * Copyright (C) 2006 Qumranet
13 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 *
15 * Avi Kivity <avi@qumranet.com>
16 * Yaniv Kamay <yaniv@qumranet.com>
17 *
18 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
19 */
20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22#include <linux/kvm_host.h>
23#include "kvm_cache_regs.h"
24#include "kvm_emulate.h"
25#include <linux/stringify.h>
26#include <asm/debugreg.h>
27#include <asm/nospec-branch.h>
28#include <asm/ibt.h>
29
30#include "x86.h"
31#include "tss.h"
32#include "mmu.h"
33#include "pmu.h"
34
35/*
36 * Operand types
37 */
38#define OpNone 0ull
39#define OpImplicit 1ull /* No generic decode */
40#define OpReg 2ull /* Register */
41#define OpMem 3ull /* Memory */
42#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
43#define OpDI 5ull /* ES:DI/EDI/RDI */
44#define OpMem64 6ull /* Memory, 64-bit */
45#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
46#define OpDX 8ull /* DX register */
47#define OpCL 9ull /* CL register (for shifts) */
48#define OpImmByte 10ull /* 8-bit sign extended immediate */
49#define OpOne 11ull /* Implied 1 */
50#define OpImm 12ull /* Sign extended up to 32-bit immediate */
51#define OpMem16 13ull /* Memory operand (16-bit). */
52#define OpMem32 14ull /* Memory operand (32-bit). */
53#define OpImmU 15ull /* Immediate operand, zero extended */
54#define OpSI 16ull /* SI/ESI/RSI */
55#define OpImmFAddr 17ull /* Immediate far address */
56#define OpMemFAddr 18ull /* Far address in memory */
57#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
58#define OpES 20ull /* ES */
59#define OpCS 21ull /* CS */
60#define OpSS 22ull /* SS */
61#define OpDS 23ull /* DS */
62#define OpFS 24ull /* FS */
63#define OpGS 25ull /* GS */
64#define OpMem8 26ull /* 8-bit zero extended memory operand */
65#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
66#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
67#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
68#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
69
70#define OpBits 5 /* Width of operand field */
71#define OpMask ((1ull << OpBits) - 1)
72
73/*
74 * Opcode effective-address decode tables.
75 * Note that we only emulate instructions that have at least one memory
76 * operand (excluding implicit stack references). We assume that stack
77 * references and instruction fetches will never occur in special memory
78 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
79 * not be handled.
80 */
81
82/* Operand sizes: 8-bit operands or specified/overridden size. */
83#define ByteOp (1<<0) /* 8-bit operands. */
84/* Destination operand type. */
85#define DstShift 1
86#define ImplicitOps (OpImplicit << DstShift)
87#define DstReg (OpReg << DstShift)
88#define DstMem (OpMem << DstShift)
89#define DstAcc (OpAcc << DstShift)
90#define DstDI (OpDI << DstShift)
91#define DstMem64 (OpMem64 << DstShift)
92#define DstMem16 (OpMem16 << DstShift)
93#define DstImmUByte (OpImmUByte << DstShift)
94#define DstDX (OpDX << DstShift)
95#define DstAccLo (OpAccLo << DstShift)
96#define DstMask (OpMask << DstShift)
97/* Source operand type. */
98#define SrcShift 6
99#define SrcNone (OpNone << SrcShift)
100#define SrcReg (OpReg << SrcShift)
101#define SrcMem (OpMem << SrcShift)
102#define SrcMem16 (OpMem16 << SrcShift)
103#define SrcMem32 (OpMem32 << SrcShift)
104#define SrcImm (OpImm << SrcShift)
105#define SrcImmByte (OpImmByte << SrcShift)
106#define SrcOne (OpOne << SrcShift)
107#define SrcImmUByte (OpImmUByte << SrcShift)
108#define SrcImmU (OpImmU << SrcShift)
109#define SrcSI (OpSI << SrcShift)
110#define SrcXLat (OpXLat << SrcShift)
111#define SrcImmFAddr (OpImmFAddr << SrcShift)
112#define SrcMemFAddr (OpMemFAddr << SrcShift)
113#define SrcAcc (OpAcc << SrcShift)
114#define SrcImmU16 (OpImmU16 << SrcShift)
115#define SrcImm64 (OpImm64 << SrcShift)
116#define SrcDX (OpDX << SrcShift)
117#define SrcMem8 (OpMem8 << SrcShift)
118#define SrcAccHi (OpAccHi << SrcShift)
119#define SrcMask (OpMask << SrcShift)
120#define BitOp (1<<11)
121#define MemAbs (1<<12) /* Memory operand is absolute displacement */
122#define String (1<<13) /* String instruction (rep capable) */
123#define Stack (1<<14) /* Stack instruction (push/pop) */
124#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
125#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
126#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
127#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
128#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
129#define Escape (5<<15) /* Escape to coprocessor instruction */
130#define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */
131#define ModeDual (7<<15) /* Different instruction for 32/64 bit */
132#define Sse (1<<18) /* SSE Vector instruction */
133/* Generic ModRM decode. */
134#define ModRM (1<<19)
135/* Destination is only written; never read. */
136#define Mov (1<<20)
137/* Misc flags */
138#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
139#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
140#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
141#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
142#define Undefined (1<<25) /* No Such Instruction */
143#define Lock (1<<26) /* lock prefix is allowed for the instruction */
144#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
145#define No64 (1<<28)
146#define PageTable (1 << 29) /* instruction used to write page table */
147#define NotImpl (1 << 30) /* instruction is not implemented */
148/* Source 2 operand type */
149#define Src2Shift (31)
150#define Src2None (OpNone << Src2Shift)
151#define Src2Mem (OpMem << Src2Shift)
152#define Src2CL (OpCL << Src2Shift)
153#define Src2ImmByte (OpImmByte << Src2Shift)
154#define Src2One (OpOne << Src2Shift)
155#define Src2Imm (OpImm << Src2Shift)
156#define Src2ES (OpES << Src2Shift)
157#define Src2CS (OpCS << Src2Shift)
158#define Src2SS (OpSS << Src2Shift)
159#define Src2DS (OpDS << Src2Shift)
160#define Src2FS (OpFS << Src2Shift)
161#define Src2GS (OpGS << Src2Shift)
162#define Src2Mask (OpMask << Src2Shift)
163#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
164#define AlignMask ((u64)7 << 41)
165#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
166#define Unaligned ((u64)2 << 41) /* Explicitly unaligned (e.g. MOVDQU) */
167#define Avx ((u64)3 << 41) /* Advanced Vector Extensions */
168#define Aligned16 ((u64)4 << 41) /* Aligned to 16 byte boundary (e.g. FXSAVE) */
169#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
170#define NoWrite ((u64)1 << 45) /* No writeback */
171#define SrcWrite ((u64)1 << 46) /* Write back src operand */
172#define NoMod ((u64)1 << 47) /* Mod field is ignored */
173#define Intercept ((u64)1 << 48) /* Has valid intercept field */
174#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
175#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
176#define NearBranch ((u64)1 << 52) /* Near branches */
177#define No16 ((u64)1 << 53) /* No 16 bit operand */
178#define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */
179#define TwoMemOp ((u64)1 << 55) /* Instruction has two memory operand */
180#define IsBranch ((u64)1 << 56) /* Instruction is considered a branch. */
181
182#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
183
184#define X2(x...) x, x
185#define X3(x...) X2(x), x
186#define X4(x...) X2(x), X2(x)
187#define X5(x...) X4(x), x
188#define X6(x...) X4(x), X2(x)
189#define X7(x...) X4(x), X3(x)
190#define X8(x...) X4(x), X4(x)
191#define X16(x...) X8(x), X8(x)
192
193struct opcode {
194 u64 flags;
195 u8 intercept;
196 u8 pad[7];
197 union {
198 int (*execute)(struct x86_emulate_ctxt *ctxt);
199 const struct opcode *group;
200 const struct group_dual *gdual;
201 const struct gprefix *gprefix;
202 const struct escape *esc;
203 const struct instr_dual *idual;
204 const struct mode_dual *mdual;
205 void (*fastop)(struct fastop *fake);
206 } u;
207 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
208};
209
210struct group_dual {
211 struct opcode mod012[8];
212 struct opcode mod3[8];
213};
214
215struct gprefix {
216 struct opcode pfx_no;
217 struct opcode pfx_66;
218 struct opcode pfx_f2;
219 struct opcode pfx_f3;
220};
221
222struct escape {
223 struct opcode op[8];
224 struct opcode high[64];
225};
226
227struct instr_dual {
228 struct opcode mod012;
229 struct opcode mod3;
230};
231
232struct mode_dual {
233 struct opcode mode32;
234 struct opcode mode64;
235};
236
237#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
238
239enum x86_transfer_type {
240 X86_TRANSFER_NONE,
241 X86_TRANSFER_CALL_JMP,
242 X86_TRANSFER_RET,
243 X86_TRANSFER_TASK_SWITCH,
244};
245
246static void writeback_registers(struct x86_emulate_ctxt *ctxt)
247{
248 unsigned long dirty = ctxt->regs_dirty;
249 unsigned reg;
250
251 for_each_set_bit(reg, &dirty, NR_EMULATOR_GPRS)
252 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
253}
254
255static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
256{
257 ctxt->regs_dirty = 0;
258 ctxt->regs_valid = 0;
259}
260
261/*
262 * These EFLAGS bits are restored from saved value during emulation, and
263 * any changes are written back to the saved value after emulation.
264 */
265#define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\
266 X86_EFLAGS_PF|X86_EFLAGS_CF)
267
268#ifdef CONFIG_X86_64
269#define ON64(x) x
270#else
271#define ON64(x)
272#endif
273
274/*
275 * fastop functions have a special calling convention:
276 *
277 * dst: rax (in/out)
278 * src: rdx (in/out)
279 * src2: rcx (in)
280 * flags: rflags (in/out)
281 * ex: rsi (in:fastop pointer, out:zero if exception)
282 *
283 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
284 * different operand sizes can be reached by calculation, rather than a jump
285 * table (which would be bigger than the code).
286 *
287 * The 16 byte alignment, considering 5 bytes for the RET thunk, 3 for ENDBR
288 * and 1 for the straight line speculation INT3, leaves 7 bytes for the
289 * body of the function. Currently none is larger than 4.
290 */
291static int fastop(struct x86_emulate_ctxt *ctxt, fastop_t fop);
292
293#define FASTOP_SIZE 16
294
295#define __FOP_FUNC(name) \
296 ".align " __stringify(FASTOP_SIZE) " \n\t" \
297 ".type " name ", @function \n\t" \
298 name ":\n\t" \
299 ASM_ENDBR \
300 IBT_NOSEAL(name)
301
302#define FOP_FUNC(name) \
303 __FOP_FUNC(#name)
304
305#define __FOP_RET(name) \
306 "11: " ASM_RET \
307 ".size " name ", .-" name "\n\t"
308
309#define FOP_RET(name) \
310 __FOP_RET(#name)
311
312#define __FOP_START(op, align) \
313 extern void em_##op(struct fastop *fake); \
314 asm(".pushsection .text, \"ax\" \n\t" \
315 ".global em_" #op " \n\t" \
316 ".align " __stringify(align) " \n\t" \
317 "em_" #op ":\n\t"
318
319#define FOP_START(op) __FOP_START(op, FASTOP_SIZE)
320
321#define FOP_END \
322 ".popsection")
323
324#define __FOPNOP(name) \
325 __FOP_FUNC(name) \
326 __FOP_RET(name)
327
328#define FOPNOP() \
329 __FOPNOP(__stringify(__UNIQUE_ID(nop)))
330
331#define FOP1E(op, dst) \
332 __FOP_FUNC(#op "_" #dst) \
333 "10: " #op " %" #dst " \n\t" \
334 __FOP_RET(#op "_" #dst)
335
336#define FOP1EEX(op, dst) \
337 FOP1E(op, dst) _ASM_EXTABLE_TYPE_REG(10b, 11b, EX_TYPE_ZERO_REG, %%esi)
338
339#define FASTOP1(op) \
340 FOP_START(op) \
341 FOP1E(op##b, al) \
342 FOP1E(op##w, ax) \
343 FOP1E(op##l, eax) \
344 ON64(FOP1E(op##q, rax)) \
345 FOP_END
346
347/* 1-operand, using src2 (for MUL/DIV r/m) */
348#define FASTOP1SRC2(op, name) \
349 FOP_START(name) \
350 FOP1E(op, cl) \
351 FOP1E(op, cx) \
352 FOP1E(op, ecx) \
353 ON64(FOP1E(op, rcx)) \
354 FOP_END
355
356/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
357#define FASTOP1SRC2EX(op, name) \
358 FOP_START(name) \
359 FOP1EEX(op, cl) \
360 FOP1EEX(op, cx) \
361 FOP1EEX(op, ecx) \
362 ON64(FOP1EEX(op, rcx)) \
363 FOP_END
364
365#define FOP2E(op, dst, src) \
366 __FOP_FUNC(#op "_" #dst "_" #src) \
367 #op " %" #src ", %" #dst " \n\t" \
368 __FOP_RET(#op "_" #dst "_" #src)
369
370#define FASTOP2(op) \
371 FOP_START(op) \
372 FOP2E(op##b, al, dl) \
373 FOP2E(op##w, ax, dx) \
374 FOP2E(op##l, eax, edx) \
375 ON64(FOP2E(op##q, rax, rdx)) \
376 FOP_END
377
378/* 2 operand, word only */
379#define FASTOP2W(op) \
380 FOP_START(op) \
381 FOPNOP() \
382 FOP2E(op##w, ax, dx) \
383 FOP2E(op##l, eax, edx) \
384 ON64(FOP2E(op##q, rax, rdx)) \
385 FOP_END
386
387/* 2 operand, src is CL */
388#define FASTOP2CL(op) \
389 FOP_START(op) \
390 FOP2E(op##b, al, cl) \
391 FOP2E(op##w, ax, cl) \
392 FOP2E(op##l, eax, cl) \
393 ON64(FOP2E(op##q, rax, cl)) \
394 FOP_END
395
396/* 2 operand, src and dest are reversed */
397#define FASTOP2R(op, name) \
398 FOP_START(name) \
399 FOP2E(op##b, dl, al) \
400 FOP2E(op##w, dx, ax) \
401 FOP2E(op##l, edx, eax) \
402 ON64(FOP2E(op##q, rdx, rax)) \
403 FOP_END
404
405#define FOP3E(op, dst, src, src2) \
406 __FOP_FUNC(#op "_" #dst "_" #src "_" #src2) \
407 #op " %" #src2 ", %" #src ", %" #dst " \n\t"\
408 __FOP_RET(#op "_" #dst "_" #src "_" #src2)
409
410/* 3-operand, word-only, src2=cl */
411#define FASTOP3WCL(op) \
412 FOP_START(op) \
413 FOPNOP() \
414 FOP3E(op##w, ax, dx, cl) \
415 FOP3E(op##l, eax, edx, cl) \
416 ON64(FOP3E(op##q, rax, rdx, cl)) \
417 FOP_END
418
419/* Special case for SETcc - 1 instruction per cc */
420#define FOP_SETCC(op) \
421 FOP_FUNC(op) \
422 #op " %al \n\t" \
423 FOP_RET(op)
424
425FOP_START(setcc)
426FOP_SETCC(seto)
427FOP_SETCC(setno)
428FOP_SETCC(setc)
429FOP_SETCC(setnc)
430FOP_SETCC(setz)
431FOP_SETCC(setnz)
432FOP_SETCC(setbe)
433FOP_SETCC(setnbe)
434FOP_SETCC(sets)
435FOP_SETCC(setns)
436FOP_SETCC(setp)
437FOP_SETCC(setnp)
438FOP_SETCC(setl)
439FOP_SETCC(setnl)
440FOP_SETCC(setle)
441FOP_SETCC(setnle)
442FOP_END;
443
444FOP_START(salc)
445FOP_FUNC(salc)
446"pushf; sbb %al, %al; popf \n\t"
447FOP_RET(salc)
448FOP_END;
449
450/*
451 * XXX: inoutclob user must know where the argument is being expanded.
452 * Using asm goto would allow us to remove _fault.
453 */
454#define asm_safe(insn, inoutclob...) \
455({ \
456 int _fault = 0; \
457 \
458 asm volatile("1:" insn "\n" \
459 "2:\n" \
460 _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_ONE_REG, %[_fault]) \
461 : [_fault] "+r"(_fault) inoutclob ); \
462 \
463 _fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \
464})
465
466static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
467 enum x86_intercept intercept,
468 enum x86_intercept_stage stage)
469{
470 struct x86_instruction_info info = {
471 .intercept = intercept,
472 .rep_prefix = ctxt->rep_prefix,
473 .modrm_mod = ctxt->modrm_mod,
474 .modrm_reg = ctxt->modrm_reg,
475 .modrm_rm = ctxt->modrm_rm,
476 .src_val = ctxt->src.val64,
477 .dst_val = ctxt->dst.val64,
478 .src_bytes = ctxt->src.bytes,
479 .dst_bytes = ctxt->dst.bytes,
480 .ad_bytes = ctxt->ad_bytes,
481 .next_rip = ctxt->eip,
482 };
483
484 return ctxt->ops->intercept(ctxt, &info, stage);
485}
486
487static void assign_masked(ulong *dest, ulong src, ulong mask)
488{
489 *dest = (*dest & ~mask) | (src & mask);
490}
491
492static void assign_register(unsigned long *reg, u64 val, int bytes)
493{
494 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
495 switch (bytes) {
496 case 1:
497 *(u8 *)reg = (u8)val;
498 break;
499 case 2:
500 *(u16 *)reg = (u16)val;
501 break;
502 case 4:
503 *reg = (u32)val;
504 break; /* 64b: zero-extend */
505 case 8:
506 *reg = val;
507 break;
508 }
509}
510
511static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
512{
513 return (1UL << (ctxt->ad_bytes << 3)) - 1;
514}
515
516static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
517{
518 u16 sel;
519 struct desc_struct ss;
520
521 if (ctxt->mode == X86EMUL_MODE_PROT64)
522 return ~0UL;
523 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
524 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
525}
526
527static int stack_size(struct x86_emulate_ctxt *ctxt)
528{
529 return (__fls(stack_mask(ctxt)) + 1) >> 3;
530}
531
532/* Access/update address held in a register, based on addressing mode. */
533static inline unsigned long
534address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
535{
536 if (ctxt->ad_bytes == sizeof(unsigned long))
537 return reg;
538 else
539 return reg & ad_mask(ctxt);
540}
541
542static inline unsigned long
543register_address(struct x86_emulate_ctxt *ctxt, int reg)
544{
545 return address_mask(ctxt, reg_read(ctxt, reg));
546}
547
548static void masked_increment(ulong *reg, ulong mask, int inc)
549{
550 assign_masked(reg, *reg + inc, mask);
551}
552
553static inline void
554register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
555{
556 ulong *preg = reg_rmw(ctxt, reg);
557
558 assign_register(preg, *preg + inc, ctxt->ad_bytes);
559}
560
561static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
562{
563 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
564}
565
566static u32 desc_limit_scaled(struct desc_struct *desc)
567{
568 u32 limit = get_desc_limit(desc);
569
570 return desc->g ? (limit << 12) | 0xfff : limit;
571}
572
573static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
574{
575 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
576 return 0;
577
578 return ctxt->ops->get_cached_segment_base(ctxt, seg);
579}
580
581static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
582 u32 error, bool valid)
583{
584 if (KVM_EMULATOR_BUG_ON(vec > 0x1f, ctxt))
585 return X86EMUL_UNHANDLEABLE;
586
587 ctxt->exception.vector = vec;
588 ctxt->exception.error_code = error;
589 ctxt->exception.error_code_valid = valid;
590 return X86EMUL_PROPAGATE_FAULT;
591}
592
593static int emulate_db(struct x86_emulate_ctxt *ctxt)
594{
595 return emulate_exception(ctxt, DB_VECTOR, 0, false);
596}
597
598static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
599{
600 return emulate_exception(ctxt, GP_VECTOR, err, true);
601}
602
603static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
604{
605 return emulate_exception(ctxt, SS_VECTOR, err, true);
606}
607
608static int emulate_ud(struct x86_emulate_ctxt *ctxt)
609{
610 return emulate_exception(ctxt, UD_VECTOR, 0, false);
611}
612
613static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
614{
615 return emulate_exception(ctxt, TS_VECTOR, err, true);
616}
617
618static int emulate_de(struct x86_emulate_ctxt *ctxt)
619{
620 return emulate_exception(ctxt, DE_VECTOR, 0, false);
621}
622
623static int emulate_nm(struct x86_emulate_ctxt *ctxt)
624{
625 return emulate_exception(ctxt, NM_VECTOR, 0, false);
626}
627
628static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
629{
630 u16 selector;
631 struct desc_struct desc;
632
633 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
634 return selector;
635}
636
637static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
638 unsigned seg)
639{
640 u16 dummy;
641 u32 base3;
642 struct desc_struct desc;
643
644 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
645 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
646}
647
648static inline u8 ctxt_virt_addr_bits(struct x86_emulate_ctxt *ctxt)
649{
650 return (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_LA57) ? 57 : 48;
651}
652
653static inline bool emul_is_noncanonical_address(u64 la,
654 struct x86_emulate_ctxt *ctxt,
655 unsigned int flags)
656{
657 return !ctxt->ops->is_canonical_addr(ctxt, la, flags);
658}
659
660/*
661 * x86 defines three classes of vector instructions: explicitly
662 * aligned, explicitly unaligned, and the rest, which change behaviour
663 * depending on whether they're AVX encoded or not.
664 *
665 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
666 * subject to the same check. FXSAVE and FXRSTOR are checked here too as their
667 * 512 bytes of data must be aligned to a 16 byte boundary.
668 */
669static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size)
670{
671 u64 alignment = ctxt->d & AlignMask;
672
673 if (likely(size < 16))
674 return 1;
675
676 switch (alignment) {
677 case Unaligned:
678 case Avx:
679 return 1;
680 case Aligned16:
681 return 16;
682 case Aligned:
683 default:
684 return size;
685 }
686}
687
688static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
689 struct segmented_address addr,
690 unsigned *max_size, unsigned size,
691 enum x86emul_mode mode, ulong *linear,
692 unsigned int flags)
693{
694 struct desc_struct desc;
695 bool usable;
696 ulong la;
697 u32 lim;
698 u16 sel;
699 u8 va_bits;
700
701 la = seg_base(ctxt, addr.seg) + addr.ea;
702 *max_size = 0;
703 switch (mode) {
704 case X86EMUL_MODE_PROT64:
705 *linear = la = ctxt->ops->get_untagged_addr(ctxt, la, flags);
706 va_bits = ctxt_virt_addr_bits(ctxt);
707 if (!__is_canonical_address(la, va_bits))
708 goto bad;
709
710 *max_size = min_t(u64, ~0u, (1ull << va_bits) - la);
711 if (size > *max_size)
712 goto bad;
713 break;
714 default:
715 *linear = la = (u32)la;
716 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
717 addr.seg);
718 if (!usable)
719 goto bad;
720 /* code segment in protected mode or read-only data segment */
721 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8)) || !(desc.type & 2)) &&
722 (flags & X86EMUL_F_WRITE))
723 goto bad;
724 /* unreadable code segment */
725 if (!(flags & X86EMUL_F_FETCH) && (desc.type & 8) && !(desc.type & 2))
726 goto bad;
727 lim = desc_limit_scaled(&desc);
728 if (!(desc.type & 8) && (desc.type & 4)) {
729 /* expand-down segment */
730 if (addr.ea <= lim)
731 goto bad;
732 lim = desc.d ? 0xffffffff : 0xffff;
733 }
734 if (addr.ea > lim)
735 goto bad;
736 if (lim == 0xffffffff)
737 *max_size = ~0u;
738 else {
739 *max_size = (u64)lim + 1 - addr.ea;
740 if (size > *max_size)
741 goto bad;
742 }
743 break;
744 }
745 if (la & (insn_alignment(ctxt, size) - 1))
746 return emulate_gp(ctxt, 0);
747 return X86EMUL_CONTINUE;
748bad:
749 if (addr.seg == VCPU_SREG_SS)
750 return emulate_ss(ctxt, 0);
751 else
752 return emulate_gp(ctxt, 0);
753}
754
755static int linearize(struct x86_emulate_ctxt *ctxt,
756 struct segmented_address addr,
757 unsigned size, bool write,
758 ulong *linear)
759{
760 unsigned max_size;
761 return __linearize(ctxt, addr, &max_size, size, ctxt->mode, linear,
762 write ? X86EMUL_F_WRITE : 0);
763}
764
765static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst)
766{
767 ulong linear;
768 int rc;
769 unsigned max_size;
770 struct segmented_address addr = { .seg = VCPU_SREG_CS,
771 .ea = dst };
772
773 if (ctxt->op_bytes != sizeof(unsigned long))
774 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
775 rc = __linearize(ctxt, addr, &max_size, 1, ctxt->mode, &linear,
776 X86EMUL_F_FETCH);
777 if (rc == X86EMUL_CONTINUE)
778 ctxt->_eip = addr.ea;
779 return rc;
780}
781
782static inline int emulator_recalc_and_set_mode(struct x86_emulate_ctxt *ctxt)
783{
784 u64 efer;
785 struct desc_struct cs;
786 u16 selector;
787 u32 base3;
788
789 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
790
791 if (!(ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PE)) {
792 /* Real mode. cpu must not have long mode active */
793 if (efer & EFER_LMA)
794 return X86EMUL_UNHANDLEABLE;
795 ctxt->mode = X86EMUL_MODE_REAL;
796 return X86EMUL_CONTINUE;
797 }
798
799 if (ctxt->eflags & X86_EFLAGS_VM) {
800 /* Protected/VM86 mode. cpu must not have long mode active */
801 if (efer & EFER_LMA)
802 return X86EMUL_UNHANDLEABLE;
803 ctxt->mode = X86EMUL_MODE_VM86;
804 return X86EMUL_CONTINUE;
805 }
806
807 if (!ctxt->ops->get_segment(ctxt, &selector, &cs, &base3, VCPU_SREG_CS))
808 return X86EMUL_UNHANDLEABLE;
809
810 if (efer & EFER_LMA) {
811 if (cs.l) {
812 /* Proper long mode */
813 ctxt->mode = X86EMUL_MODE_PROT64;
814 } else if (cs.d) {
815 /* 32 bit compatibility mode*/
816 ctxt->mode = X86EMUL_MODE_PROT32;
817 } else {
818 ctxt->mode = X86EMUL_MODE_PROT16;
819 }
820 } else {
821 /* Legacy 32 bit / 16 bit mode */
822 ctxt->mode = cs.d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
823 }
824
825 return X86EMUL_CONTINUE;
826}
827
828static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
829{
830 return assign_eip(ctxt, dst);
831}
832
833static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst)
834{
835 int rc = emulator_recalc_and_set_mode(ctxt);
836
837 if (rc != X86EMUL_CONTINUE)
838 return rc;
839
840 return assign_eip(ctxt, dst);
841}
842
843static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
844{
845 return assign_eip_near(ctxt, ctxt->_eip + rel);
846}
847
848static int linear_read_system(struct x86_emulate_ctxt *ctxt, ulong linear,
849 void *data, unsigned size)
850{
851 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, true);
852}
853
854static int linear_write_system(struct x86_emulate_ctxt *ctxt,
855 ulong linear, void *data,
856 unsigned int size)
857{
858 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, true);
859}
860
861static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
862 struct segmented_address addr,
863 void *data,
864 unsigned size)
865{
866 int rc;
867 ulong linear;
868
869 rc = linearize(ctxt, addr, size, false, &linear);
870 if (rc != X86EMUL_CONTINUE)
871 return rc;
872 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, false);
873}
874
875static int segmented_write_std(struct x86_emulate_ctxt *ctxt,
876 struct segmented_address addr,
877 void *data,
878 unsigned int size)
879{
880 int rc;
881 ulong linear;
882
883 rc = linearize(ctxt, addr, size, true, &linear);
884 if (rc != X86EMUL_CONTINUE)
885 return rc;
886 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, false);
887}
888
889/*
890 * Prefetch the remaining bytes of the instruction without crossing page
891 * boundary if they are not in fetch_cache yet.
892 */
893static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
894{
895 int rc;
896 unsigned size, max_size;
897 unsigned long linear;
898 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
899 struct segmented_address addr = { .seg = VCPU_SREG_CS,
900 .ea = ctxt->eip + cur_size };
901
902 /*
903 * We do not know exactly how many bytes will be needed, and
904 * __linearize is expensive, so fetch as much as possible. We
905 * just have to avoid going beyond the 15 byte limit, the end
906 * of the segment, or the end of the page.
907 *
908 * __linearize is called with size 0 so that it does not do any
909 * boundary check itself. Instead, we use max_size to check
910 * against op_size.
911 */
912 rc = __linearize(ctxt, addr, &max_size, 0, ctxt->mode, &linear,
913 X86EMUL_F_FETCH);
914 if (unlikely(rc != X86EMUL_CONTINUE))
915 return rc;
916
917 size = min_t(unsigned, 15UL ^ cur_size, max_size);
918 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
919
920 /*
921 * One instruction can only straddle two pages,
922 * and one has been loaded at the beginning of
923 * x86_decode_insn. So, if not enough bytes
924 * still, we must have hit the 15-byte boundary.
925 */
926 if (unlikely(size < op_size))
927 return emulate_gp(ctxt, 0);
928
929 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
930 size, &ctxt->exception);
931 if (unlikely(rc != X86EMUL_CONTINUE))
932 return rc;
933 ctxt->fetch.end += size;
934 return X86EMUL_CONTINUE;
935}
936
937static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
938 unsigned size)
939{
940 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
941
942 if (unlikely(done_size < size))
943 return __do_insn_fetch_bytes(ctxt, size - done_size);
944 else
945 return X86EMUL_CONTINUE;
946}
947
948/* Fetch next part of the instruction being emulated. */
949#define insn_fetch(_type, _ctxt) \
950({ _type _x; \
951 \
952 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
953 if (rc != X86EMUL_CONTINUE) \
954 goto done; \
955 ctxt->_eip += sizeof(_type); \
956 memcpy(&_x, ctxt->fetch.ptr, sizeof(_type)); \
957 ctxt->fetch.ptr += sizeof(_type); \
958 _x; \
959})
960
961#define insn_fetch_arr(_arr, _size, _ctxt) \
962({ \
963 rc = do_insn_fetch_bytes(_ctxt, _size); \
964 if (rc != X86EMUL_CONTINUE) \
965 goto done; \
966 ctxt->_eip += (_size); \
967 memcpy(_arr, ctxt->fetch.ptr, _size); \
968 ctxt->fetch.ptr += (_size); \
969})
970
971/*
972 * Given the 'reg' portion of a ModRM byte, and a register block, return a
973 * pointer into the block that addresses the relevant register.
974 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
975 */
976static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
977 int byteop)
978{
979 void *p;
980 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
981
982 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
983 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
984 else
985 p = reg_rmw(ctxt, modrm_reg);
986 return p;
987}
988
989static int read_descriptor(struct x86_emulate_ctxt *ctxt,
990 struct segmented_address addr,
991 u16 *size, unsigned long *address, int op_bytes)
992{
993 int rc;
994
995 if (op_bytes == 2)
996 op_bytes = 3;
997 *address = 0;
998 rc = segmented_read_std(ctxt, addr, size, 2);
999 if (rc != X86EMUL_CONTINUE)
1000 return rc;
1001 addr.ea += 2;
1002 rc = segmented_read_std(ctxt, addr, address, op_bytes);
1003 return rc;
1004}
1005
1006FASTOP2(add);
1007FASTOP2(or);
1008FASTOP2(adc);
1009FASTOP2(sbb);
1010FASTOP2(and);
1011FASTOP2(sub);
1012FASTOP2(xor);
1013FASTOP2(cmp);
1014FASTOP2(test);
1015
1016FASTOP1SRC2(mul, mul_ex);
1017FASTOP1SRC2(imul, imul_ex);
1018FASTOP1SRC2EX(div, div_ex);
1019FASTOP1SRC2EX(idiv, idiv_ex);
1020
1021FASTOP3WCL(shld);
1022FASTOP3WCL(shrd);
1023
1024FASTOP2W(imul);
1025
1026FASTOP1(not);
1027FASTOP1(neg);
1028FASTOP1(inc);
1029FASTOP1(dec);
1030
1031FASTOP2CL(rol);
1032FASTOP2CL(ror);
1033FASTOP2CL(rcl);
1034FASTOP2CL(rcr);
1035FASTOP2CL(shl);
1036FASTOP2CL(shr);
1037FASTOP2CL(sar);
1038
1039FASTOP2W(bsf);
1040FASTOP2W(bsr);
1041FASTOP2W(bt);
1042FASTOP2W(bts);
1043FASTOP2W(btr);
1044FASTOP2W(btc);
1045
1046FASTOP2(xadd);
1047
1048FASTOP2R(cmp, cmp_r);
1049
1050static int em_bsf_c(struct x86_emulate_ctxt *ctxt)
1051{
1052 /* If src is zero, do not writeback, but update flags */
1053 if (ctxt->src.val == 0)
1054 ctxt->dst.type = OP_NONE;
1055 return fastop(ctxt, em_bsf);
1056}
1057
1058static int em_bsr_c(struct x86_emulate_ctxt *ctxt)
1059{
1060 /* If src is zero, do not writeback, but update flags */
1061 if (ctxt->src.val == 0)
1062 ctxt->dst.type = OP_NONE;
1063 return fastop(ctxt, em_bsr);
1064}
1065
1066static __always_inline u8 test_cc(unsigned int condition, unsigned long flags)
1067{
1068 u8 rc;
1069 void (*fop)(void) = (void *)em_setcc + FASTOP_SIZE * (condition & 0xf);
1070
1071 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
1072 asm("push %[flags]; popf; " CALL_NOSPEC
1073 : "=a"(rc), ASM_CALL_CONSTRAINT : [thunk_target]"r"(fop), [flags]"r"(flags));
1074 return rc;
1075}
1076
1077static void fetch_register_operand(struct operand *op)
1078{
1079 switch (op->bytes) {
1080 case 1:
1081 op->val = *(u8 *)op->addr.reg;
1082 break;
1083 case 2:
1084 op->val = *(u16 *)op->addr.reg;
1085 break;
1086 case 4:
1087 op->val = *(u32 *)op->addr.reg;
1088 break;
1089 case 8:
1090 op->val = *(u64 *)op->addr.reg;
1091 break;
1092 }
1093}
1094
1095static int em_fninit(struct x86_emulate_ctxt *ctxt)
1096{
1097 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1098 return emulate_nm(ctxt);
1099
1100 kvm_fpu_get();
1101 asm volatile("fninit");
1102 kvm_fpu_put();
1103 return X86EMUL_CONTINUE;
1104}
1105
1106static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1107{
1108 u16 fcw;
1109
1110 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1111 return emulate_nm(ctxt);
1112
1113 kvm_fpu_get();
1114 asm volatile("fnstcw %0": "+m"(fcw));
1115 kvm_fpu_put();
1116
1117 ctxt->dst.val = fcw;
1118
1119 return X86EMUL_CONTINUE;
1120}
1121
1122static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1123{
1124 u16 fsw;
1125
1126 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1127 return emulate_nm(ctxt);
1128
1129 kvm_fpu_get();
1130 asm volatile("fnstsw %0": "+m"(fsw));
1131 kvm_fpu_put();
1132
1133 ctxt->dst.val = fsw;
1134
1135 return X86EMUL_CONTINUE;
1136}
1137
1138static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
1139 struct operand *op)
1140{
1141 unsigned int reg;
1142
1143 if (ctxt->d & ModRM)
1144 reg = ctxt->modrm_reg;
1145 else
1146 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1147
1148 if (ctxt->d & Sse) {
1149 op->type = OP_XMM;
1150 op->bytes = 16;
1151 op->addr.xmm = reg;
1152 kvm_read_sse_reg(reg, &op->vec_val);
1153 return;
1154 }
1155 if (ctxt->d & Mmx) {
1156 reg &= 7;
1157 op->type = OP_MM;
1158 op->bytes = 8;
1159 op->addr.mm = reg;
1160 return;
1161 }
1162
1163 op->type = OP_REG;
1164 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1165 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1166
1167 fetch_register_operand(op);
1168 op->orig_val = op->val;
1169}
1170
1171static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1172{
1173 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1174 ctxt->modrm_seg = VCPU_SREG_SS;
1175}
1176
1177static int decode_modrm(struct x86_emulate_ctxt *ctxt,
1178 struct operand *op)
1179{
1180 u8 sib;
1181 int index_reg, base_reg, scale;
1182 int rc = X86EMUL_CONTINUE;
1183 ulong modrm_ea = 0;
1184
1185 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1186 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1187 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1188
1189 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
1190 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1191 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
1192 ctxt->modrm_seg = VCPU_SREG_DS;
1193
1194 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
1195 op->type = OP_REG;
1196 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1197 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
1198 ctxt->d & ByteOp);
1199 if (ctxt->d & Sse) {
1200 op->type = OP_XMM;
1201 op->bytes = 16;
1202 op->addr.xmm = ctxt->modrm_rm;
1203 kvm_read_sse_reg(ctxt->modrm_rm, &op->vec_val);
1204 return rc;
1205 }
1206 if (ctxt->d & Mmx) {
1207 op->type = OP_MM;
1208 op->bytes = 8;
1209 op->addr.mm = ctxt->modrm_rm & 7;
1210 return rc;
1211 }
1212 fetch_register_operand(op);
1213 return rc;
1214 }
1215
1216 op->type = OP_MEM;
1217
1218 if (ctxt->ad_bytes == 2) {
1219 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1220 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1221 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1222 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1223
1224 /* 16-bit ModR/M decode. */
1225 switch (ctxt->modrm_mod) {
1226 case 0:
1227 if (ctxt->modrm_rm == 6)
1228 modrm_ea += insn_fetch(u16, ctxt);
1229 break;
1230 case 1:
1231 modrm_ea += insn_fetch(s8, ctxt);
1232 break;
1233 case 2:
1234 modrm_ea += insn_fetch(u16, ctxt);
1235 break;
1236 }
1237 switch (ctxt->modrm_rm) {
1238 case 0:
1239 modrm_ea += bx + si;
1240 break;
1241 case 1:
1242 modrm_ea += bx + di;
1243 break;
1244 case 2:
1245 modrm_ea += bp + si;
1246 break;
1247 case 3:
1248 modrm_ea += bp + di;
1249 break;
1250 case 4:
1251 modrm_ea += si;
1252 break;
1253 case 5:
1254 modrm_ea += di;
1255 break;
1256 case 6:
1257 if (ctxt->modrm_mod != 0)
1258 modrm_ea += bp;
1259 break;
1260 case 7:
1261 modrm_ea += bx;
1262 break;
1263 }
1264 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1265 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1266 ctxt->modrm_seg = VCPU_SREG_SS;
1267 modrm_ea = (u16)modrm_ea;
1268 } else {
1269 /* 32/64-bit ModR/M decode. */
1270 if ((ctxt->modrm_rm & 7) == 4) {
1271 sib = insn_fetch(u8, ctxt);
1272 index_reg |= (sib >> 3) & 7;
1273 base_reg |= sib & 7;
1274 scale = sib >> 6;
1275
1276 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
1277 modrm_ea += insn_fetch(s32, ctxt);
1278 else {
1279 modrm_ea += reg_read(ctxt, base_reg);
1280 adjust_modrm_seg(ctxt, base_reg);
1281 /* Increment ESP on POP [ESP] */
1282 if ((ctxt->d & IncSP) &&
1283 base_reg == VCPU_REGS_RSP)
1284 modrm_ea += ctxt->op_bytes;
1285 }
1286 if (index_reg != 4)
1287 modrm_ea += reg_read(ctxt, index_reg) << scale;
1288 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
1289 modrm_ea += insn_fetch(s32, ctxt);
1290 if (ctxt->mode == X86EMUL_MODE_PROT64)
1291 ctxt->rip_relative = 1;
1292 } else {
1293 base_reg = ctxt->modrm_rm;
1294 modrm_ea += reg_read(ctxt, base_reg);
1295 adjust_modrm_seg(ctxt, base_reg);
1296 }
1297 switch (ctxt->modrm_mod) {
1298 case 1:
1299 modrm_ea += insn_fetch(s8, ctxt);
1300 break;
1301 case 2:
1302 modrm_ea += insn_fetch(s32, ctxt);
1303 break;
1304 }
1305 }
1306 op->addr.mem.ea = modrm_ea;
1307 if (ctxt->ad_bytes != 8)
1308 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1309
1310done:
1311 return rc;
1312}
1313
1314static int decode_abs(struct x86_emulate_ctxt *ctxt,
1315 struct operand *op)
1316{
1317 int rc = X86EMUL_CONTINUE;
1318
1319 op->type = OP_MEM;
1320 switch (ctxt->ad_bytes) {
1321 case 2:
1322 op->addr.mem.ea = insn_fetch(u16, ctxt);
1323 break;
1324 case 4:
1325 op->addr.mem.ea = insn_fetch(u32, ctxt);
1326 break;
1327 case 8:
1328 op->addr.mem.ea = insn_fetch(u64, ctxt);
1329 break;
1330 }
1331done:
1332 return rc;
1333}
1334
1335static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
1336{
1337 long sv = 0, mask;
1338
1339 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1340 mask = ~((long)ctxt->dst.bytes * 8 - 1);
1341
1342 if (ctxt->src.bytes == 2)
1343 sv = (s16)ctxt->src.val & (s16)mask;
1344 else if (ctxt->src.bytes == 4)
1345 sv = (s32)ctxt->src.val & (s32)mask;
1346 else
1347 sv = (s64)ctxt->src.val & (s64)mask;
1348
1349 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1350 ctxt->dst.addr.mem.ea + (sv >> 3));
1351 }
1352
1353 /* only subword offset */
1354 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
1355}
1356
1357static int read_emulated(struct x86_emulate_ctxt *ctxt,
1358 unsigned long addr, void *dest, unsigned size)
1359{
1360 int rc;
1361 struct read_cache *mc = &ctxt->mem_read;
1362
1363 if (mc->pos < mc->end)
1364 goto read_cached;
1365
1366 if (KVM_EMULATOR_BUG_ON((mc->end + size) >= sizeof(mc->data), ctxt))
1367 return X86EMUL_UNHANDLEABLE;
1368
1369 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1370 &ctxt->exception);
1371 if (rc != X86EMUL_CONTINUE)
1372 return rc;
1373
1374 mc->end += size;
1375
1376read_cached:
1377 memcpy(dest, mc->data + mc->pos, size);
1378 mc->pos += size;
1379 return X86EMUL_CONTINUE;
1380}
1381
1382static int segmented_read(struct x86_emulate_ctxt *ctxt,
1383 struct segmented_address addr,
1384 void *data,
1385 unsigned size)
1386{
1387 int rc;
1388 ulong linear;
1389
1390 rc = linearize(ctxt, addr, size, false, &linear);
1391 if (rc != X86EMUL_CONTINUE)
1392 return rc;
1393 return read_emulated(ctxt, linear, data, size);
1394}
1395
1396static int segmented_write(struct x86_emulate_ctxt *ctxt,
1397 struct segmented_address addr,
1398 const void *data,
1399 unsigned size)
1400{
1401 int rc;
1402 ulong linear;
1403
1404 rc = linearize(ctxt, addr, size, true, &linear);
1405 if (rc != X86EMUL_CONTINUE)
1406 return rc;
1407 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1408 &ctxt->exception);
1409}
1410
1411static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1412 struct segmented_address addr,
1413 const void *orig_data, const void *data,
1414 unsigned size)
1415{
1416 int rc;
1417 ulong linear;
1418
1419 rc = linearize(ctxt, addr, size, true, &linear);
1420 if (rc != X86EMUL_CONTINUE)
1421 return rc;
1422 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1423 size, &ctxt->exception);
1424}
1425
1426static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1427 unsigned int size, unsigned short port,
1428 void *dest)
1429{
1430 struct read_cache *rc = &ctxt->io_read;
1431
1432 if (rc->pos == rc->end) { /* refill pio read ahead */
1433 unsigned int in_page, n;
1434 unsigned int count = ctxt->rep_prefix ?
1435 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
1436 in_page = (ctxt->eflags & X86_EFLAGS_DF) ?
1437 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1438 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
1439 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
1440 if (n == 0)
1441 n = 1;
1442 rc->pos = rc->end = 0;
1443 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1444 return 0;
1445 rc->end = n * size;
1446 }
1447
1448 if (ctxt->rep_prefix && (ctxt->d & String) &&
1449 !(ctxt->eflags & X86_EFLAGS_DF)) {
1450 ctxt->dst.data = rc->data + rc->pos;
1451 ctxt->dst.type = OP_MEM_STR;
1452 ctxt->dst.count = (rc->end - rc->pos) / size;
1453 rc->pos = rc->end;
1454 } else {
1455 memcpy(dest, rc->data + rc->pos, size);
1456 rc->pos += size;
1457 }
1458 return 1;
1459}
1460
1461static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1462 u16 index, struct desc_struct *desc)
1463{
1464 struct desc_ptr dt;
1465 ulong addr;
1466
1467 ctxt->ops->get_idt(ctxt, &dt);
1468
1469 if (dt.size < index * 8 + 7)
1470 return emulate_gp(ctxt, index << 3 | 0x2);
1471
1472 addr = dt.address + index * 8;
1473 return linear_read_system(ctxt, addr, desc, sizeof(*desc));
1474}
1475
1476static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1477 u16 selector, struct desc_ptr *dt)
1478{
1479 const struct x86_emulate_ops *ops = ctxt->ops;
1480 u32 base3 = 0;
1481
1482 if (selector & 1 << 2) {
1483 struct desc_struct desc;
1484 u16 sel;
1485
1486 memset(dt, 0, sizeof(*dt));
1487 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1488 VCPU_SREG_LDTR))
1489 return;
1490
1491 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1492 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
1493 } else
1494 ops->get_gdt(ctxt, dt);
1495}
1496
1497static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt,
1498 u16 selector, ulong *desc_addr_p)
1499{
1500 struct desc_ptr dt;
1501 u16 index = selector >> 3;
1502 ulong addr;
1503
1504 get_descriptor_table_ptr(ctxt, selector, &dt);
1505
1506 if (dt.size < index * 8 + 7)
1507 return emulate_gp(ctxt, selector & 0xfffc);
1508
1509 addr = dt.address + index * 8;
1510
1511#ifdef CONFIG_X86_64
1512 if (addr >> 32 != 0) {
1513 u64 efer = 0;
1514
1515 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1516 if (!(efer & EFER_LMA))
1517 addr &= (u32)-1;
1518 }
1519#endif
1520
1521 *desc_addr_p = addr;
1522 return X86EMUL_CONTINUE;
1523}
1524
1525/* allowed just for 8 bytes segments */
1526static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1527 u16 selector, struct desc_struct *desc,
1528 ulong *desc_addr_p)
1529{
1530 int rc;
1531
1532 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p);
1533 if (rc != X86EMUL_CONTINUE)
1534 return rc;
1535
1536 return linear_read_system(ctxt, *desc_addr_p, desc, sizeof(*desc));
1537}
1538
1539/* allowed just for 8 bytes segments */
1540static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1541 u16 selector, struct desc_struct *desc)
1542{
1543 int rc;
1544 ulong addr;
1545
1546 rc = get_descriptor_ptr(ctxt, selector, &addr);
1547 if (rc != X86EMUL_CONTINUE)
1548 return rc;
1549
1550 return linear_write_system(ctxt, addr, desc, sizeof(*desc));
1551}
1552
1553static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1554 u16 selector, int seg, u8 cpl,
1555 enum x86_transfer_type transfer,
1556 struct desc_struct *desc)
1557{
1558 struct desc_struct seg_desc, old_desc;
1559 u8 dpl, rpl;
1560 unsigned err_vec = GP_VECTOR;
1561 u32 err_code = 0;
1562 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1563 ulong desc_addr;
1564 int ret;
1565 u16 dummy;
1566 u32 base3 = 0;
1567
1568 memset(&seg_desc, 0, sizeof(seg_desc));
1569
1570 if (ctxt->mode == X86EMUL_MODE_REAL) {
1571 /* set real mode segment descriptor (keep limit etc. for
1572 * unreal mode) */
1573 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
1574 set_desc_base(&seg_desc, selector << 4);
1575 goto load;
1576 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1577 /* VM86 needs a clean new segment descriptor */
1578 set_desc_base(&seg_desc, selector << 4);
1579 set_desc_limit(&seg_desc, 0xffff);
1580 seg_desc.type = 3;
1581 seg_desc.p = 1;
1582 seg_desc.s = 1;
1583 seg_desc.dpl = 3;
1584 goto load;
1585 }
1586
1587 rpl = selector & 3;
1588
1589 /* TR should be in GDT only */
1590 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1591 goto exception;
1592
1593 /* NULL selector is not valid for TR, CS and (except for long mode) SS */
1594 if (null_selector) {
1595 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_TR)
1596 goto exception;
1597
1598 if (seg == VCPU_SREG_SS) {
1599 if (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl)
1600 goto exception;
1601
1602 /*
1603 * ctxt->ops->set_segment expects the CPL to be in
1604 * SS.DPL, so fake an expand-up 32-bit data segment.
1605 */
1606 seg_desc.type = 3;
1607 seg_desc.p = 1;
1608 seg_desc.s = 1;
1609 seg_desc.dpl = cpl;
1610 seg_desc.d = 1;
1611 seg_desc.g = 1;
1612 }
1613
1614 /* Skip all following checks */
1615 goto load;
1616 }
1617
1618 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
1619 if (ret != X86EMUL_CONTINUE)
1620 return ret;
1621
1622 err_code = selector & 0xfffc;
1623 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR :
1624 GP_VECTOR;
1625
1626 /* can't load system descriptor into segment selector */
1627 if (seg <= VCPU_SREG_GS && !seg_desc.s) {
1628 if (transfer == X86_TRANSFER_CALL_JMP)
1629 return X86EMUL_UNHANDLEABLE;
1630 goto exception;
1631 }
1632
1633 dpl = seg_desc.dpl;
1634
1635 switch (seg) {
1636 case VCPU_SREG_SS:
1637 /*
1638 * segment is not a writable data segment or segment
1639 * selector's RPL != CPL or DPL != CPL
1640 */
1641 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1642 goto exception;
1643 break;
1644 case VCPU_SREG_CS:
1645 /*
1646 * KVM uses "none" when loading CS as part of emulating Real
1647 * Mode exceptions and IRET (handled above). In all other
1648 * cases, loading CS without a control transfer is a KVM bug.
1649 */
1650 if (WARN_ON_ONCE(transfer == X86_TRANSFER_NONE))
1651 goto exception;
1652
1653 if (!(seg_desc.type & 8))
1654 goto exception;
1655
1656 if (transfer == X86_TRANSFER_RET) {
1657 /* RET can never return to an inner privilege level. */
1658 if (rpl < cpl)
1659 goto exception;
1660 /* Outer-privilege level return is not implemented */
1661 if (rpl > cpl)
1662 return X86EMUL_UNHANDLEABLE;
1663 }
1664 if (transfer == X86_TRANSFER_RET || transfer == X86_TRANSFER_TASK_SWITCH) {
1665 if (seg_desc.type & 4) {
1666 /* conforming */
1667 if (dpl > rpl)
1668 goto exception;
1669 } else {
1670 /* nonconforming */
1671 if (dpl != rpl)
1672 goto exception;
1673 }
1674 } else { /* X86_TRANSFER_CALL_JMP */
1675 if (seg_desc.type & 4) {
1676 /* conforming */
1677 if (dpl > cpl)
1678 goto exception;
1679 } else {
1680 /* nonconforming */
1681 if (rpl > cpl || dpl != cpl)
1682 goto exception;
1683 }
1684 }
1685 /* in long-mode d/b must be clear if l is set */
1686 if (seg_desc.d && seg_desc.l) {
1687 u64 efer = 0;
1688
1689 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1690 if (efer & EFER_LMA)
1691 goto exception;
1692 }
1693
1694 /* CS(RPL) <- CPL */
1695 selector = (selector & 0xfffc) | cpl;
1696 break;
1697 case VCPU_SREG_TR:
1698 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1699 goto exception;
1700 break;
1701 case VCPU_SREG_LDTR:
1702 if (seg_desc.s || seg_desc.type != 2)
1703 goto exception;
1704 break;
1705 default: /* DS, ES, FS, or GS */
1706 /*
1707 * segment is not a data or readable code segment or
1708 * ((segment is a data or nonconforming code segment)
1709 * and ((RPL > DPL) or (CPL > DPL)))
1710 */
1711 if ((seg_desc.type & 0xa) == 0x8 ||
1712 (((seg_desc.type & 0xc) != 0xc) &&
1713 (rpl > dpl || cpl > dpl)))
1714 goto exception;
1715 break;
1716 }
1717
1718 if (!seg_desc.p) {
1719 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1720 goto exception;
1721 }
1722
1723 if (seg_desc.s) {
1724 /* mark segment as accessed */
1725 if (!(seg_desc.type & 1)) {
1726 seg_desc.type |= 1;
1727 ret = write_segment_descriptor(ctxt, selector,
1728 &seg_desc);
1729 if (ret != X86EMUL_CONTINUE)
1730 return ret;
1731 }
1732 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1733 ret = linear_read_system(ctxt, desc_addr+8, &base3, sizeof(base3));
1734 if (ret != X86EMUL_CONTINUE)
1735 return ret;
1736 if (emul_is_noncanonical_address(get_desc_base(&seg_desc) |
1737 ((u64)base3 << 32), ctxt,
1738 X86EMUL_F_DT_LOAD))
1739 return emulate_gp(ctxt, err_code);
1740 }
1741
1742 if (seg == VCPU_SREG_TR) {
1743 old_desc = seg_desc;
1744 seg_desc.type |= 2; /* busy */
1745 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1746 sizeof(seg_desc), &ctxt->exception);
1747 if (ret != X86EMUL_CONTINUE)
1748 return ret;
1749 }
1750load:
1751 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
1752 if (desc)
1753 *desc = seg_desc;
1754 return X86EMUL_CONTINUE;
1755exception:
1756 return emulate_exception(ctxt, err_vec, err_code, true);
1757}
1758
1759static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1760 u16 selector, int seg)
1761{
1762 u8 cpl = ctxt->ops->cpl(ctxt);
1763
1764 /*
1765 * None of MOV, POP and LSS can load a NULL selector in CPL=3, but
1766 * they can load it at CPL<3 (Intel's manual says only LSS can,
1767 * but it's wrong).
1768 *
1769 * However, the Intel manual says that putting IST=1/DPL=3 in
1770 * an interrupt gate will result in SS=3 (the AMD manual instead
1771 * says it doesn't), so allow SS=3 in __load_segment_descriptor
1772 * and only forbid it here.
1773 */
1774 if (seg == VCPU_SREG_SS && selector == 3 &&
1775 ctxt->mode == X86EMUL_MODE_PROT64)
1776 return emulate_exception(ctxt, GP_VECTOR, 0, true);
1777
1778 return __load_segment_descriptor(ctxt, selector, seg, cpl,
1779 X86_TRANSFER_NONE, NULL);
1780}
1781
1782static void write_register_operand(struct operand *op)
1783{
1784 return assign_register(op->addr.reg, op->val, op->bytes);
1785}
1786
1787static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
1788{
1789 switch (op->type) {
1790 case OP_REG:
1791 write_register_operand(op);
1792 break;
1793 case OP_MEM:
1794 if (ctxt->lock_prefix)
1795 return segmented_cmpxchg(ctxt,
1796 op->addr.mem,
1797 &op->orig_val,
1798 &op->val,
1799 op->bytes);
1800 else
1801 return segmented_write(ctxt,
1802 op->addr.mem,
1803 &op->val,
1804 op->bytes);
1805 case OP_MEM_STR:
1806 return segmented_write(ctxt,
1807 op->addr.mem,
1808 op->data,
1809 op->bytes * op->count);
1810 case OP_XMM:
1811 kvm_write_sse_reg(op->addr.xmm, &op->vec_val);
1812 break;
1813 case OP_MM:
1814 kvm_write_mmx_reg(op->addr.mm, &op->mm_val);
1815 break;
1816 case OP_NONE:
1817 /* no writeback */
1818 break;
1819 default:
1820 break;
1821 }
1822 return X86EMUL_CONTINUE;
1823}
1824
1825static int emulate_push(struct x86_emulate_ctxt *ctxt, const void *data, int len)
1826{
1827 struct segmented_address addr;
1828
1829 rsp_increment(ctxt, -len);
1830 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1831 addr.seg = VCPU_SREG_SS;
1832
1833 return segmented_write(ctxt, addr, data, len);
1834}
1835
1836static int em_push(struct x86_emulate_ctxt *ctxt)
1837{
1838 /* Disable writeback. */
1839 ctxt->dst.type = OP_NONE;
1840 return emulate_push(ctxt, &ctxt->src.val, ctxt->op_bytes);
1841}
1842
1843static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1844 void *dest, int len)
1845{
1846 int rc;
1847 struct segmented_address addr;
1848
1849 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1850 addr.seg = VCPU_SREG_SS;
1851 rc = segmented_read(ctxt, addr, dest, len);
1852 if (rc != X86EMUL_CONTINUE)
1853 return rc;
1854
1855 rsp_increment(ctxt, len);
1856 return rc;
1857}
1858
1859static int em_pop(struct x86_emulate_ctxt *ctxt)
1860{
1861 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1862}
1863
1864static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1865 void *dest, int len)
1866{
1867 int rc;
1868 unsigned long val = 0;
1869 unsigned long change_mask;
1870 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
1871 int cpl = ctxt->ops->cpl(ctxt);
1872
1873 rc = emulate_pop(ctxt, &val, len);
1874 if (rc != X86EMUL_CONTINUE)
1875 return rc;
1876
1877 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
1878 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF |
1879 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT |
1880 X86_EFLAGS_AC | X86_EFLAGS_ID;
1881
1882 switch(ctxt->mode) {
1883 case X86EMUL_MODE_PROT64:
1884 case X86EMUL_MODE_PROT32:
1885 case X86EMUL_MODE_PROT16:
1886 if (cpl == 0)
1887 change_mask |= X86_EFLAGS_IOPL;
1888 if (cpl <= iopl)
1889 change_mask |= X86_EFLAGS_IF;
1890 break;
1891 case X86EMUL_MODE_VM86:
1892 if (iopl < 3)
1893 return emulate_gp(ctxt, 0);
1894 change_mask |= X86_EFLAGS_IF;
1895 break;
1896 default: /* real mode */
1897 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF);
1898 break;
1899 }
1900
1901 *(unsigned long *)dest =
1902 (ctxt->eflags & ~change_mask) | (val & change_mask);
1903
1904 return rc;
1905}
1906
1907static int em_popf(struct x86_emulate_ctxt *ctxt)
1908{
1909 ctxt->dst.type = OP_REG;
1910 ctxt->dst.addr.reg = &ctxt->eflags;
1911 ctxt->dst.bytes = ctxt->op_bytes;
1912 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1913}
1914
1915static int em_enter(struct x86_emulate_ctxt *ctxt)
1916{
1917 int rc;
1918 unsigned frame_size = ctxt->src.val;
1919 unsigned nesting_level = ctxt->src2.val & 31;
1920 ulong rbp;
1921
1922 if (nesting_level)
1923 return X86EMUL_UNHANDLEABLE;
1924
1925 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1926 rc = emulate_push(ctxt, &rbp, stack_size(ctxt));
1927 if (rc != X86EMUL_CONTINUE)
1928 return rc;
1929 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
1930 stack_mask(ctxt));
1931 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1932 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
1933 stack_mask(ctxt));
1934 return X86EMUL_CONTINUE;
1935}
1936
1937static int em_leave(struct x86_emulate_ctxt *ctxt)
1938{
1939 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
1940 stack_mask(ctxt));
1941 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
1942}
1943
1944static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
1945{
1946 int seg = ctxt->src2.val;
1947
1948 ctxt->src.val = get_segment_selector(ctxt, seg);
1949 if (ctxt->op_bytes == 4) {
1950 rsp_increment(ctxt, -2);
1951 ctxt->op_bytes = 2;
1952 }
1953
1954 return em_push(ctxt);
1955}
1956
1957static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
1958{
1959 int seg = ctxt->src2.val;
1960 unsigned long selector = 0;
1961 int rc;
1962
1963 rc = emulate_pop(ctxt, &selector, 2);
1964 if (rc != X86EMUL_CONTINUE)
1965 return rc;
1966
1967 if (seg == VCPU_SREG_SS)
1968 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1969 if (ctxt->op_bytes > 2)
1970 rsp_increment(ctxt, ctxt->op_bytes - 2);
1971
1972 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
1973 return rc;
1974}
1975
1976static int em_pusha(struct x86_emulate_ctxt *ctxt)
1977{
1978 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
1979 int rc = X86EMUL_CONTINUE;
1980 int reg = VCPU_REGS_RAX;
1981
1982 while (reg <= VCPU_REGS_RDI) {
1983 (reg == VCPU_REGS_RSP) ?
1984 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
1985
1986 rc = em_push(ctxt);
1987 if (rc != X86EMUL_CONTINUE)
1988 return rc;
1989
1990 ++reg;
1991 }
1992
1993 return rc;
1994}
1995
1996static int em_pushf(struct x86_emulate_ctxt *ctxt)
1997{
1998 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM;
1999 return em_push(ctxt);
2000}
2001
2002static int em_popa(struct x86_emulate_ctxt *ctxt)
2003{
2004 int rc = X86EMUL_CONTINUE;
2005 int reg = VCPU_REGS_RDI;
2006 u32 val = 0;
2007
2008 while (reg >= VCPU_REGS_RAX) {
2009 if (reg == VCPU_REGS_RSP) {
2010 rsp_increment(ctxt, ctxt->op_bytes);
2011 --reg;
2012 }
2013
2014 rc = emulate_pop(ctxt, &val, ctxt->op_bytes);
2015 if (rc != X86EMUL_CONTINUE)
2016 break;
2017 assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes);
2018 --reg;
2019 }
2020 return rc;
2021}
2022
2023static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2024{
2025 const struct x86_emulate_ops *ops = ctxt->ops;
2026 int rc;
2027 struct desc_ptr dt;
2028 gva_t cs_addr;
2029 gva_t eip_addr;
2030 u16 cs, eip;
2031
2032 /* TODO: Add limit checks */
2033 ctxt->src.val = ctxt->eflags;
2034 rc = em_push(ctxt);
2035 if (rc != X86EMUL_CONTINUE)
2036 return rc;
2037
2038 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC);
2039
2040 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
2041 rc = em_push(ctxt);
2042 if (rc != X86EMUL_CONTINUE)
2043 return rc;
2044
2045 ctxt->src.val = ctxt->_eip;
2046 rc = em_push(ctxt);
2047 if (rc != X86EMUL_CONTINUE)
2048 return rc;
2049
2050 ops->get_idt(ctxt, &dt);
2051
2052 eip_addr = dt.address + (irq << 2);
2053 cs_addr = dt.address + (irq << 2) + 2;
2054
2055 rc = linear_read_system(ctxt, cs_addr, &cs, 2);
2056 if (rc != X86EMUL_CONTINUE)
2057 return rc;
2058
2059 rc = linear_read_system(ctxt, eip_addr, &eip, 2);
2060 if (rc != X86EMUL_CONTINUE)
2061 return rc;
2062
2063 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
2064 if (rc != X86EMUL_CONTINUE)
2065 return rc;
2066
2067 ctxt->_eip = eip;
2068
2069 return rc;
2070}
2071
2072int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2073{
2074 int rc;
2075
2076 invalidate_registers(ctxt);
2077 rc = __emulate_int_real(ctxt, irq);
2078 if (rc == X86EMUL_CONTINUE)
2079 writeback_registers(ctxt);
2080 return rc;
2081}
2082
2083static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
2084{
2085 switch(ctxt->mode) {
2086 case X86EMUL_MODE_REAL:
2087 return __emulate_int_real(ctxt, irq);
2088 case X86EMUL_MODE_VM86:
2089 case X86EMUL_MODE_PROT16:
2090 case X86EMUL_MODE_PROT32:
2091 case X86EMUL_MODE_PROT64:
2092 default:
2093 /* Protected mode interrupts unimplemented yet */
2094 return X86EMUL_UNHANDLEABLE;
2095 }
2096}
2097
2098static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
2099{
2100 int rc = X86EMUL_CONTINUE;
2101 unsigned long temp_eip = 0;
2102 unsigned long temp_eflags = 0;
2103 unsigned long cs = 0;
2104 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
2105 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF |
2106 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF |
2107 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF |
2108 X86_EFLAGS_AC | X86_EFLAGS_ID |
2109 X86_EFLAGS_FIXED;
2110 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF |
2111 X86_EFLAGS_VIP;
2112
2113 /* TODO: Add stack limit check */
2114
2115 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
2116
2117 if (rc != X86EMUL_CONTINUE)
2118 return rc;
2119
2120 if (temp_eip & ~0xffff)
2121 return emulate_gp(ctxt, 0);
2122
2123 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2124
2125 if (rc != X86EMUL_CONTINUE)
2126 return rc;
2127
2128 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
2129
2130 if (rc != X86EMUL_CONTINUE)
2131 return rc;
2132
2133 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
2134
2135 if (rc != X86EMUL_CONTINUE)
2136 return rc;
2137
2138 ctxt->_eip = temp_eip;
2139
2140 if (ctxt->op_bytes == 4)
2141 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
2142 else if (ctxt->op_bytes == 2) {
2143 ctxt->eflags &= ~0xffff;
2144 ctxt->eflags |= temp_eflags;
2145 }
2146
2147 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2148 ctxt->eflags |= X86_EFLAGS_FIXED;
2149 ctxt->ops->set_nmi_mask(ctxt, false);
2150
2151 return rc;
2152}
2153
2154static int em_iret(struct x86_emulate_ctxt *ctxt)
2155{
2156 switch(ctxt->mode) {
2157 case X86EMUL_MODE_REAL:
2158 return emulate_iret_real(ctxt);
2159 case X86EMUL_MODE_VM86:
2160 case X86EMUL_MODE_PROT16:
2161 case X86EMUL_MODE_PROT32:
2162 case X86EMUL_MODE_PROT64:
2163 default:
2164 /* iret from protected mode unimplemented yet */
2165 return X86EMUL_UNHANDLEABLE;
2166 }
2167}
2168
2169static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2170{
2171 int rc;
2172 unsigned short sel;
2173 struct desc_struct new_desc;
2174 u8 cpl = ctxt->ops->cpl(ctxt);
2175
2176 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2177
2178 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
2179 X86_TRANSFER_CALL_JMP,
2180 &new_desc);
2181 if (rc != X86EMUL_CONTINUE)
2182 return rc;
2183
2184 rc = assign_eip_far(ctxt, ctxt->src.val);
2185 /* Error handling is not implemented. */
2186 if (rc != X86EMUL_CONTINUE)
2187 return X86EMUL_UNHANDLEABLE;
2188
2189 return rc;
2190}
2191
2192static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
2193{
2194 return assign_eip_near(ctxt, ctxt->src.val);
2195}
2196
2197static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2198{
2199 int rc;
2200 long int old_eip;
2201
2202 old_eip = ctxt->_eip;
2203 rc = assign_eip_near(ctxt, ctxt->src.val);
2204 if (rc != X86EMUL_CONTINUE)
2205 return rc;
2206 ctxt->src.val = old_eip;
2207 rc = em_push(ctxt);
2208 return rc;
2209}
2210
2211static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
2212{
2213 u64 old = ctxt->dst.orig_val64;
2214
2215 if (ctxt->dst.bytes == 16)
2216 return X86EMUL_UNHANDLEABLE;
2217
2218 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2219 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2220 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2221 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
2222 ctxt->eflags &= ~X86_EFLAGS_ZF;
2223 } else {
2224 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2225 (u32) reg_read(ctxt, VCPU_REGS_RBX);
2226
2227 ctxt->eflags |= X86_EFLAGS_ZF;
2228 }
2229 return X86EMUL_CONTINUE;
2230}
2231
2232static int em_ret(struct x86_emulate_ctxt *ctxt)
2233{
2234 int rc;
2235 unsigned long eip = 0;
2236
2237 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2238 if (rc != X86EMUL_CONTINUE)
2239 return rc;
2240
2241 return assign_eip_near(ctxt, eip);
2242}
2243
2244static int em_ret_far(struct x86_emulate_ctxt *ctxt)
2245{
2246 int rc;
2247 unsigned long eip = 0;
2248 unsigned long cs = 0;
2249 int cpl = ctxt->ops->cpl(ctxt);
2250 struct desc_struct new_desc;
2251
2252 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2253 if (rc != X86EMUL_CONTINUE)
2254 return rc;
2255 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2256 if (rc != X86EMUL_CONTINUE)
2257 return rc;
2258 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl,
2259 X86_TRANSFER_RET,
2260 &new_desc);
2261 if (rc != X86EMUL_CONTINUE)
2262 return rc;
2263 rc = assign_eip_far(ctxt, eip);
2264 /* Error handling is not implemented. */
2265 if (rc != X86EMUL_CONTINUE)
2266 return X86EMUL_UNHANDLEABLE;
2267
2268 return rc;
2269}
2270
2271static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2272{
2273 int rc;
2274
2275 rc = em_ret_far(ctxt);
2276 if (rc != X86EMUL_CONTINUE)
2277 return rc;
2278 rsp_increment(ctxt, ctxt->src.val);
2279 return X86EMUL_CONTINUE;
2280}
2281
2282static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2283{
2284 /* Save real source value, then compare EAX against destination. */
2285 ctxt->dst.orig_val = ctxt->dst.val;
2286 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
2287 ctxt->src.orig_val = ctxt->src.val;
2288 ctxt->src.val = ctxt->dst.orig_val;
2289 fastop(ctxt, em_cmp);
2290
2291 if (ctxt->eflags & X86_EFLAGS_ZF) {
2292 /* Success: write back to memory; no update of EAX */
2293 ctxt->src.type = OP_NONE;
2294 ctxt->dst.val = ctxt->src.orig_val;
2295 } else {
2296 /* Failure: write the value we saw to EAX. */
2297 ctxt->src.type = OP_REG;
2298 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2299 ctxt->src.val = ctxt->dst.orig_val;
2300 /* Create write-cycle to dest by writing the same value */
2301 ctxt->dst.val = ctxt->dst.orig_val;
2302 }
2303 return X86EMUL_CONTINUE;
2304}
2305
2306static int em_lseg(struct x86_emulate_ctxt *ctxt)
2307{
2308 int seg = ctxt->src2.val;
2309 unsigned short sel;
2310 int rc;
2311
2312 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2313
2314 rc = load_segment_descriptor(ctxt, sel, seg);
2315 if (rc != X86EMUL_CONTINUE)
2316 return rc;
2317
2318 ctxt->dst.val = ctxt->src.val;
2319 return rc;
2320}
2321
2322static int em_rsm(struct x86_emulate_ctxt *ctxt)
2323{
2324 if (!ctxt->ops->is_smm(ctxt))
2325 return emulate_ud(ctxt);
2326
2327 if (ctxt->ops->leave_smm(ctxt))
2328 ctxt->ops->triple_fault(ctxt);
2329
2330 return emulator_recalc_and_set_mode(ctxt);
2331}
2332
2333static void
2334setup_syscalls_segments(struct desc_struct *cs, struct desc_struct *ss)
2335{
2336 cs->l = 0; /* will be adjusted later */
2337 set_desc_base(cs, 0); /* flat segment */
2338 cs->g = 1; /* 4kb granularity */
2339 set_desc_limit(cs, 0xfffff); /* 4GB limit */
2340 cs->type = 0x0b; /* Read, Execute, Accessed */
2341 cs->s = 1;
2342 cs->dpl = 0; /* will be adjusted later */
2343 cs->p = 1;
2344 cs->d = 1;
2345 cs->avl = 0;
2346
2347 set_desc_base(ss, 0); /* flat segment */
2348 set_desc_limit(ss, 0xfffff); /* 4GB limit */
2349 ss->g = 1; /* 4kb granularity */
2350 ss->s = 1;
2351 ss->type = 0x03; /* Read/Write, Accessed */
2352 ss->d = 1; /* 32bit stack segment */
2353 ss->dpl = 0;
2354 ss->p = 1;
2355 ss->l = 0;
2356 ss->avl = 0;
2357}
2358
2359static int em_syscall(struct x86_emulate_ctxt *ctxt)
2360{
2361 const struct x86_emulate_ops *ops = ctxt->ops;
2362 struct desc_struct cs, ss;
2363 u64 msr_data;
2364 u16 cs_sel, ss_sel;
2365 u64 efer = 0;
2366
2367 /* syscall is not available in real mode */
2368 if (ctxt->mode == X86EMUL_MODE_REAL ||
2369 ctxt->mode == X86EMUL_MODE_VM86)
2370 return emulate_ud(ctxt);
2371
2372 /*
2373 * Intel compatible CPUs only support SYSCALL in 64-bit mode, whereas
2374 * AMD allows SYSCALL in any flavor of protected mode. Note, it's
2375 * infeasible to emulate Intel behavior when running on AMD hardware,
2376 * as SYSCALL won't fault in the "wrong" mode, i.e. there is no #UD
2377 * for KVM to trap-and-emulate, unlike emulating AMD on Intel.
2378 */
2379 if (ctxt->mode != X86EMUL_MODE_PROT64 &&
2380 ctxt->ops->guest_cpuid_is_intel_compatible(ctxt))
2381 return emulate_ud(ctxt);
2382
2383 ops->get_msr(ctxt, MSR_EFER, &efer);
2384 if (!(efer & EFER_SCE))
2385 return emulate_ud(ctxt);
2386
2387 setup_syscalls_segments(&cs, &ss);
2388 ops->get_msr(ctxt, MSR_STAR, &msr_data);
2389 msr_data >>= 32;
2390 cs_sel = (u16)(msr_data & 0xfffc);
2391 ss_sel = (u16)(msr_data + 8);
2392
2393 if (efer & EFER_LMA) {
2394 cs.d = 0;
2395 cs.l = 1;
2396 }
2397 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2398 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2399
2400 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
2401 if (efer & EFER_LMA) {
2402#ifdef CONFIG_X86_64
2403 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
2404
2405 ops->get_msr(ctxt,
2406 ctxt->mode == X86EMUL_MODE_PROT64 ?
2407 MSR_LSTAR : MSR_CSTAR, &msr_data);
2408 ctxt->_eip = msr_data;
2409
2410 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
2411 ctxt->eflags &= ~msr_data;
2412 ctxt->eflags |= X86_EFLAGS_FIXED;
2413#endif
2414 } else {
2415 /* legacy mode */
2416 ops->get_msr(ctxt, MSR_STAR, &msr_data);
2417 ctxt->_eip = (u32)msr_data;
2418
2419 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
2420 }
2421
2422 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
2423 return X86EMUL_CONTINUE;
2424}
2425
2426static int em_sysenter(struct x86_emulate_ctxt *ctxt)
2427{
2428 const struct x86_emulate_ops *ops = ctxt->ops;
2429 struct desc_struct cs, ss;
2430 u64 msr_data;
2431 u16 cs_sel, ss_sel;
2432 u64 efer = 0;
2433
2434 ops->get_msr(ctxt, MSR_EFER, &efer);
2435 /* inject #GP if in real mode */
2436 if (ctxt->mode == X86EMUL_MODE_REAL)
2437 return emulate_gp(ctxt, 0);
2438
2439 /*
2440 * Intel's architecture allows SYSENTER in compatibility mode, but AMD
2441 * does not. Note, AMD does allow SYSENTER in legacy protected mode.
2442 */
2443 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA) &&
2444 !ctxt->ops->guest_cpuid_is_intel_compatible(ctxt))
2445 return emulate_ud(ctxt);
2446
2447 /* sysenter/sysexit have not been tested in 64bit mode. */
2448 if (ctxt->mode == X86EMUL_MODE_PROT64)
2449 return X86EMUL_UNHANDLEABLE;
2450
2451 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2452 if ((msr_data & 0xfffc) == 0x0)
2453 return emulate_gp(ctxt, 0);
2454
2455 setup_syscalls_segments(&cs, &ss);
2456 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
2457 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK;
2458 ss_sel = cs_sel + 8;
2459 if (efer & EFER_LMA) {
2460 cs.d = 0;
2461 cs.l = 1;
2462 }
2463
2464 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2465 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2466
2467 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
2468 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data;
2469
2470 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
2471 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data :
2472 (u32)msr_data;
2473 if (efer & EFER_LMA)
2474 ctxt->mode = X86EMUL_MODE_PROT64;
2475
2476 return X86EMUL_CONTINUE;
2477}
2478
2479static int em_sysexit(struct x86_emulate_ctxt *ctxt)
2480{
2481 const struct x86_emulate_ops *ops = ctxt->ops;
2482 struct desc_struct cs, ss;
2483 u64 msr_data, rcx, rdx;
2484 int usermode;
2485 u16 cs_sel = 0, ss_sel = 0;
2486
2487 /* inject #GP if in real mode or Virtual 8086 mode */
2488 if (ctxt->mode == X86EMUL_MODE_REAL ||
2489 ctxt->mode == X86EMUL_MODE_VM86)
2490 return emulate_gp(ctxt, 0);
2491
2492 setup_syscalls_segments(&cs, &ss);
2493
2494 if ((ctxt->rex_prefix & 0x8) != 0x0)
2495 usermode = X86EMUL_MODE_PROT64;
2496 else
2497 usermode = X86EMUL_MODE_PROT32;
2498
2499 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2500 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2501
2502 cs.dpl = 3;
2503 ss.dpl = 3;
2504 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2505 switch (usermode) {
2506 case X86EMUL_MODE_PROT32:
2507 cs_sel = (u16)(msr_data + 16);
2508 if ((msr_data & 0xfffc) == 0x0)
2509 return emulate_gp(ctxt, 0);
2510 ss_sel = (u16)(msr_data + 24);
2511 rcx = (u32)rcx;
2512 rdx = (u32)rdx;
2513 break;
2514 case X86EMUL_MODE_PROT64:
2515 cs_sel = (u16)(msr_data + 32);
2516 if (msr_data == 0x0)
2517 return emulate_gp(ctxt, 0);
2518 ss_sel = cs_sel + 8;
2519 cs.d = 0;
2520 cs.l = 1;
2521 if (emul_is_noncanonical_address(rcx, ctxt, 0) ||
2522 emul_is_noncanonical_address(rdx, ctxt, 0))
2523 return emulate_gp(ctxt, 0);
2524 break;
2525 }
2526 cs_sel |= SEGMENT_RPL_MASK;
2527 ss_sel |= SEGMENT_RPL_MASK;
2528
2529 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2530 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2531
2532 ctxt->_eip = rdx;
2533 ctxt->mode = usermode;
2534 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
2535
2536 return X86EMUL_CONTINUE;
2537}
2538
2539static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
2540{
2541 int iopl;
2542 if (ctxt->mode == X86EMUL_MODE_REAL)
2543 return false;
2544 if (ctxt->mode == X86EMUL_MODE_VM86)
2545 return true;
2546 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
2547 return ctxt->ops->cpl(ctxt) > iopl;
2548}
2549
2550#define VMWARE_PORT_VMPORT (0x5658)
2551#define VMWARE_PORT_VMRPC (0x5659)
2552
2553static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2554 u16 port, u16 len)
2555{
2556 const struct x86_emulate_ops *ops = ctxt->ops;
2557 struct desc_struct tr_seg;
2558 u32 base3;
2559 int r;
2560 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
2561 unsigned mask = (1 << len) - 1;
2562 unsigned long base;
2563
2564 /*
2565 * VMware allows access to these ports even if denied
2566 * by TSS I/O permission bitmap. Mimic behavior.
2567 */
2568 if (enable_vmware_backdoor &&
2569 ((port == VMWARE_PORT_VMPORT) || (port == VMWARE_PORT_VMRPC)))
2570 return true;
2571
2572 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
2573 if (!tr_seg.p)
2574 return false;
2575 if (desc_limit_scaled(&tr_seg) < 103)
2576 return false;
2577 base = get_desc_base(&tr_seg);
2578#ifdef CONFIG_X86_64
2579 base |= ((u64)base3) << 32;
2580#endif
2581 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL, true);
2582 if (r != X86EMUL_CONTINUE)
2583 return false;
2584 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2585 return false;
2586 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL, true);
2587 if (r != X86EMUL_CONTINUE)
2588 return false;
2589 if ((perm >> bit_idx) & mask)
2590 return false;
2591 return true;
2592}
2593
2594static bool emulator_io_permitted(struct x86_emulate_ctxt *ctxt,
2595 u16 port, u16 len)
2596{
2597 if (ctxt->perm_ok)
2598 return true;
2599
2600 if (emulator_bad_iopl(ctxt))
2601 if (!emulator_io_port_access_allowed(ctxt, port, len))
2602 return false;
2603
2604 ctxt->perm_ok = true;
2605
2606 return true;
2607}
2608
2609static void string_registers_quirk(struct x86_emulate_ctxt *ctxt)
2610{
2611 /*
2612 * Intel CPUs mask the counter and pointers in quite strange
2613 * manner when ECX is zero due to REP-string optimizations.
2614 */
2615#ifdef CONFIG_X86_64
2616 u32 eax, ebx, ecx, edx;
2617
2618 if (ctxt->ad_bytes != 4)
2619 return;
2620
2621 eax = ecx = 0;
2622 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true);
2623 if (!is_guest_vendor_intel(ebx, ecx, edx))
2624 return;
2625
2626 *reg_write(ctxt, VCPU_REGS_RCX) = 0;
2627
2628 switch (ctxt->b) {
2629 case 0xa4: /* movsb */
2630 case 0xa5: /* movsd/w */
2631 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1;
2632 fallthrough;
2633 case 0xaa: /* stosb */
2634 case 0xab: /* stosd/w */
2635 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1;
2636 }
2637#endif
2638}
2639
2640static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2641 struct tss_segment_16 *tss)
2642{
2643 tss->ip = ctxt->_eip;
2644 tss->flag = ctxt->eflags;
2645 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2646 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2647 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2648 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2649 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2650 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2651 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2652 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
2653
2654 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2655 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2656 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2657 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2658 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2659}
2660
2661static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2662 struct tss_segment_16 *tss)
2663{
2664 int ret;
2665 u8 cpl;
2666
2667 ctxt->_eip = tss->ip;
2668 ctxt->eflags = tss->flag | 2;
2669 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2670 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2671 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2672 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2673 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2674 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2675 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2676 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
2677
2678 /*
2679 * SDM says that segment selectors are loaded before segment
2680 * descriptors
2681 */
2682 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2683 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2684 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2685 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2686 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2687
2688 cpl = tss->cs & 3;
2689
2690 /*
2691 * Now load segment descriptors. If fault happens at this stage
2692 * it is handled in a context of new task
2693 */
2694 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
2695 X86_TRANSFER_TASK_SWITCH, NULL);
2696 if (ret != X86EMUL_CONTINUE)
2697 return ret;
2698 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2699 X86_TRANSFER_TASK_SWITCH, NULL);
2700 if (ret != X86EMUL_CONTINUE)
2701 return ret;
2702 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2703 X86_TRANSFER_TASK_SWITCH, NULL);
2704 if (ret != X86EMUL_CONTINUE)
2705 return ret;
2706 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2707 X86_TRANSFER_TASK_SWITCH, NULL);
2708 if (ret != X86EMUL_CONTINUE)
2709 return ret;
2710 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2711 X86_TRANSFER_TASK_SWITCH, NULL);
2712 if (ret != X86EMUL_CONTINUE)
2713 return ret;
2714
2715 return X86EMUL_CONTINUE;
2716}
2717
2718static int task_switch_16(struct x86_emulate_ctxt *ctxt, u16 old_tss_sel,
2719 ulong old_tss_base, struct desc_struct *new_desc)
2720{
2721 struct tss_segment_16 tss_seg;
2722 int ret;
2723 u32 new_tss_base = get_desc_base(new_desc);
2724
2725 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg));
2726 if (ret != X86EMUL_CONTINUE)
2727 return ret;
2728
2729 save_state_to_tss16(ctxt, &tss_seg);
2730
2731 ret = linear_write_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg));
2732 if (ret != X86EMUL_CONTINUE)
2733 return ret;
2734
2735 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg));
2736 if (ret != X86EMUL_CONTINUE)
2737 return ret;
2738
2739 if (old_tss_sel != 0xffff) {
2740 tss_seg.prev_task_link = old_tss_sel;
2741
2742 ret = linear_write_system(ctxt, new_tss_base,
2743 &tss_seg.prev_task_link,
2744 sizeof(tss_seg.prev_task_link));
2745 if (ret != X86EMUL_CONTINUE)
2746 return ret;
2747 }
2748
2749 return load_state_from_tss16(ctxt, &tss_seg);
2750}
2751
2752static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2753 struct tss_segment_32 *tss)
2754{
2755 /* CR3 and ldt selector are not saved intentionally */
2756 tss->eip = ctxt->_eip;
2757 tss->eflags = ctxt->eflags;
2758 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2759 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2760 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2761 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2762 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2763 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2764 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2765 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
2766
2767 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2768 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2769 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2770 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2771 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2772 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2773}
2774
2775static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2776 struct tss_segment_32 *tss)
2777{
2778 int ret;
2779 u8 cpl;
2780
2781 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
2782 return emulate_gp(ctxt, 0);
2783 ctxt->_eip = tss->eip;
2784 ctxt->eflags = tss->eflags | 2;
2785
2786 /* General purpose registers */
2787 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2788 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2789 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2790 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2791 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2792 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2793 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2794 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
2795
2796 /*
2797 * SDM says that segment selectors are loaded before segment
2798 * descriptors. This is important because CPL checks will
2799 * use CS.RPL.
2800 */
2801 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2802 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2803 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2804 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2805 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2806 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2807 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
2808
2809 /*
2810 * If we're switching between Protected Mode and VM86, we need to make
2811 * sure to update the mode before loading the segment descriptors so
2812 * that the selectors are interpreted correctly.
2813 */
2814 if (ctxt->eflags & X86_EFLAGS_VM) {
2815 ctxt->mode = X86EMUL_MODE_VM86;
2816 cpl = 3;
2817 } else {
2818 ctxt->mode = X86EMUL_MODE_PROT32;
2819 cpl = tss->cs & 3;
2820 }
2821
2822 /*
2823 * Now load segment descriptors. If fault happens at this stage
2824 * it is handled in a context of new task
2825 */
2826 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
2827 cpl, X86_TRANSFER_TASK_SWITCH, NULL);
2828 if (ret != X86EMUL_CONTINUE)
2829 return ret;
2830 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2831 X86_TRANSFER_TASK_SWITCH, NULL);
2832 if (ret != X86EMUL_CONTINUE)
2833 return ret;
2834 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2835 X86_TRANSFER_TASK_SWITCH, NULL);
2836 if (ret != X86EMUL_CONTINUE)
2837 return ret;
2838 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2839 X86_TRANSFER_TASK_SWITCH, NULL);
2840 if (ret != X86EMUL_CONTINUE)
2841 return ret;
2842 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2843 X86_TRANSFER_TASK_SWITCH, NULL);
2844 if (ret != X86EMUL_CONTINUE)
2845 return ret;
2846 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
2847 X86_TRANSFER_TASK_SWITCH, NULL);
2848 if (ret != X86EMUL_CONTINUE)
2849 return ret;
2850 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
2851 X86_TRANSFER_TASK_SWITCH, NULL);
2852
2853 return ret;
2854}
2855
2856static int task_switch_32(struct x86_emulate_ctxt *ctxt, u16 old_tss_sel,
2857 ulong old_tss_base, struct desc_struct *new_desc)
2858{
2859 struct tss_segment_32 tss_seg;
2860 int ret;
2861 u32 new_tss_base = get_desc_base(new_desc);
2862 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2863 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
2864
2865 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg));
2866 if (ret != X86EMUL_CONTINUE)
2867 return ret;
2868
2869 save_state_to_tss32(ctxt, &tss_seg);
2870
2871 /* Only GP registers and segment selectors are saved */
2872 ret = linear_write_system(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2873 ldt_sel_offset - eip_offset);
2874 if (ret != X86EMUL_CONTINUE)
2875 return ret;
2876
2877 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg));
2878 if (ret != X86EMUL_CONTINUE)
2879 return ret;
2880
2881 if (old_tss_sel != 0xffff) {
2882 tss_seg.prev_task_link = old_tss_sel;
2883
2884 ret = linear_write_system(ctxt, new_tss_base,
2885 &tss_seg.prev_task_link,
2886 sizeof(tss_seg.prev_task_link));
2887 if (ret != X86EMUL_CONTINUE)
2888 return ret;
2889 }
2890
2891 return load_state_from_tss32(ctxt, &tss_seg);
2892}
2893
2894static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2895 u16 tss_selector, int idt_index, int reason,
2896 bool has_error_code, u32 error_code)
2897{
2898 const struct x86_emulate_ops *ops = ctxt->ops;
2899 struct desc_struct curr_tss_desc, next_tss_desc;
2900 int ret;
2901 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
2902 ulong old_tss_base =
2903 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
2904 u32 desc_limit;
2905 ulong desc_addr, dr7;
2906
2907 /* FIXME: old_tss_base == ~0 ? */
2908
2909 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
2910 if (ret != X86EMUL_CONTINUE)
2911 return ret;
2912 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
2913 if (ret != X86EMUL_CONTINUE)
2914 return ret;
2915
2916 /* FIXME: check that next_tss_desc is tss */
2917
2918 /*
2919 * Check privileges. The three cases are task switch caused by...
2920 *
2921 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2922 * 2. Exception/IRQ/iret: No check is performed
2923 * 3. jmp/call to TSS/task-gate: No check is performed since the
2924 * hardware checks it before exiting.
2925 */
2926 if (reason == TASK_SWITCH_GATE) {
2927 if (idt_index != -1) {
2928 /* Software interrupts */
2929 struct desc_struct task_gate_desc;
2930 int dpl;
2931
2932 ret = read_interrupt_descriptor(ctxt, idt_index,
2933 &task_gate_desc);
2934 if (ret != X86EMUL_CONTINUE)
2935 return ret;
2936
2937 dpl = task_gate_desc.dpl;
2938 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2939 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2940 }
2941 }
2942
2943 desc_limit = desc_limit_scaled(&next_tss_desc);
2944 if (!next_tss_desc.p ||
2945 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2946 desc_limit < 0x2b)) {
2947 return emulate_ts(ctxt, tss_selector & 0xfffc);
2948 }
2949
2950 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2951 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2952 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
2953 }
2954
2955 if (reason == TASK_SWITCH_IRET)
2956 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2957
2958 /* set back link to prev task only if NT bit is set in eflags
2959 note that old_tss_sel is not used after this point */
2960 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2961 old_tss_sel = 0xffff;
2962
2963 if (next_tss_desc.type & 8)
2964 ret = task_switch_32(ctxt, old_tss_sel, old_tss_base, &next_tss_desc);
2965 else
2966 ret = task_switch_16(ctxt, old_tss_sel,
2967 old_tss_base, &next_tss_desc);
2968 if (ret != X86EMUL_CONTINUE)
2969 return ret;
2970
2971 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2972 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2973
2974 if (reason != TASK_SWITCH_IRET) {
2975 next_tss_desc.type |= (1 << 1); /* set busy flag */
2976 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
2977 }
2978
2979 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
2980 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
2981
2982 if (has_error_code) {
2983 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2984 ctxt->lock_prefix = 0;
2985 ctxt->src.val = (unsigned long) error_code;
2986 ret = em_push(ctxt);
2987 }
2988
2989 dr7 = ops->get_dr(ctxt, 7);
2990 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN));
2991
2992 return ret;
2993}
2994
2995int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2996 u16 tss_selector, int idt_index, int reason,
2997 bool has_error_code, u32 error_code)
2998{
2999 int rc;
3000
3001 invalidate_registers(ctxt);
3002 ctxt->_eip = ctxt->eip;
3003 ctxt->dst.type = OP_NONE;
3004
3005 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
3006 has_error_code, error_code);
3007
3008 if (rc == X86EMUL_CONTINUE) {
3009 ctxt->eip = ctxt->_eip;
3010 writeback_registers(ctxt);
3011 }
3012
3013 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
3014}
3015
3016static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
3017 struct operand *op)
3018{
3019 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count;
3020
3021 register_address_increment(ctxt, reg, df * op->bytes);
3022 op->addr.mem.ea = register_address(ctxt, reg);
3023}
3024
3025static int em_das(struct x86_emulate_ctxt *ctxt)
3026{
3027 u8 al, old_al;
3028 bool af, cf, old_cf;
3029
3030 cf = ctxt->eflags & X86_EFLAGS_CF;
3031 al = ctxt->dst.val;
3032
3033 old_al = al;
3034 old_cf = cf;
3035 cf = false;
3036 af = ctxt->eflags & X86_EFLAGS_AF;
3037 if ((al & 0x0f) > 9 || af) {
3038 al -= 6;
3039 cf = old_cf | (al >= 250);
3040 af = true;
3041 } else {
3042 af = false;
3043 }
3044 if (old_al > 0x99 || old_cf) {
3045 al -= 0x60;
3046 cf = true;
3047 }
3048
3049 ctxt->dst.val = al;
3050 /* Set PF, ZF, SF */
3051 ctxt->src.type = OP_IMM;
3052 ctxt->src.val = 0;
3053 ctxt->src.bytes = 1;
3054 fastop(ctxt, em_or);
3055 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
3056 if (cf)
3057 ctxt->eflags |= X86_EFLAGS_CF;
3058 if (af)
3059 ctxt->eflags |= X86_EFLAGS_AF;
3060 return X86EMUL_CONTINUE;
3061}
3062
3063static int em_aam(struct x86_emulate_ctxt *ctxt)
3064{
3065 u8 al, ah;
3066
3067 if (ctxt->src.val == 0)
3068 return emulate_de(ctxt);
3069
3070 al = ctxt->dst.val & 0xff;
3071 ah = al / ctxt->src.val;
3072 al %= ctxt->src.val;
3073
3074 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3075
3076 /* Set PF, ZF, SF */
3077 ctxt->src.type = OP_IMM;
3078 ctxt->src.val = 0;
3079 ctxt->src.bytes = 1;
3080 fastop(ctxt, em_or);
3081
3082 return X86EMUL_CONTINUE;
3083}
3084
3085static int em_aad(struct x86_emulate_ctxt *ctxt)
3086{
3087 u8 al = ctxt->dst.val & 0xff;
3088 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3089
3090 al = (al + (ah * ctxt->src.val)) & 0xff;
3091
3092 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3093
3094 /* Set PF, ZF, SF */
3095 ctxt->src.type = OP_IMM;
3096 ctxt->src.val = 0;
3097 ctxt->src.bytes = 1;
3098 fastop(ctxt, em_or);
3099
3100 return X86EMUL_CONTINUE;
3101}
3102
3103static int em_call(struct x86_emulate_ctxt *ctxt)
3104{
3105 int rc;
3106 long rel = ctxt->src.val;
3107
3108 ctxt->src.val = (unsigned long)ctxt->_eip;
3109 rc = jmp_rel(ctxt, rel);
3110 if (rc != X86EMUL_CONTINUE)
3111 return rc;
3112 return em_push(ctxt);
3113}
3114
3115static int em_call_far(struct x86_emulate_ctxt *ctxt)
3116{
3117 u16 sel, old_cs;
3118 ulong old_eip;
3119 int rc;
3120 struct desc_struct old_desc, new_desc;
3121 const struct x86_emulate_ops *ops = ctxt->ops;
3122 int cpl = ctxt->ops->cpl(ctxt);
3123 enum x86emul_mode prev_mode = ctxt->mode;
3124
3125 old_eip = ctxt->_eip;
3126 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
3127
3128 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3129 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
3130 X86_TRANSFER_CALL_JMP, &new_desc);
3131 if (rc != X86EMUL_CONTINUE)
3132 return rc;
3133
3134 rc = assign_eip_far(ctxt, ctxt->src.val);
3135 if (rc != X86EMUL_CONTINUE)
3136 goto fail;
3137
3138 ctxt->src.val = old_cs;
3139 rc = em_push(ctxt);
3140 if (rc != X86EMUL_CONTINUE)
3141 goto fail;
3142
3143 ctxt->src.val = old_eip;
3144 rc = em_push(ctxt);
3145 /* If we failed, we tainted the memory, but the very least we should
3146 restore cs */
3147 if (rc != X86EMUL_CONTINUE) {
3148 pr_warn_once("faulting far call emulation tainted memory\n");
3149 goto fail;
3150 }
3151 return rc;
3152fail:
3153 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
3154 ctxt->mode = prev_mode;
3155 return rc;
3156
3157}
3158
3159static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3160{
3161 int rc;
3162 unsigned long eip = 0;
3163
3164 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3165 if (rc != X86EMUL_CONTINUE)
3166 return rc;
3167 rc = assign_eip_near(ctxt, eip);
3168 if (rc != X86EMUL_CONTINUE)
3169 return rc;
3170 rsp_increment(ctxt, ctxt->src.val);
3171 return X86EMUL_CONTINUE;
3172}
3173
3174static int em_xchg(struct x86_emulate_ctxt *ctxt)
3175{
3176 /* Write back the register source. */
3177 ctxt->src.val = ctxt->dst.val;
3178 write_register_operand(&ctxt->src);
3179
3180 /* Write back the memory destination with implicit LOCK prefix. */
3181 ctxt->dst.val = ctxt->src.orig_val;
3182 ctxt->lock_prefix = 1;
3183 return X86EMUL_CONTINUE;
3184}
3185
3186static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3187{
3188 ctxt->dst.val = ctxt->src2.val;
3189 return fastop(ctxt, em_imul);
3190}
3191
3192static int em_cwd(struct x86_emulate_ctxt *ctxt)
3193{
3194 ctxt->dst.type = OP_REG;
3195 ctxt->dst.bytes = ctxt->src.bytes;
3196 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
3197 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
3198
3199 return X86EMUL_CONTINUE;
3200}
3201
3202static int em_rdpid(struct x86_emulate_ctxt *ctxt)
3203{
3204 u64 tsc_aux = 0;
3205
3206 if (!ctxt->ops->guest_has_rdpid(ctxt))
3207 return emulate_ud(ctxt);
3208
3209 ctxt->ops->get_msr(ctxt, MSR_TSC_AUX, &tsc_aux);
3210 ctxt->dst.val = tsc_aux;
3211 return X86EMUL_CONTINUE;
3212}
3213
3214static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3215{
3216 u64 tsc = 0;
3217
3218 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
3219 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3220 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
3221 return X86EMUL_CONTINUE;
3222}
3223
3224static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3225{
3226 u64 pmc;
3227
3228 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
3229 return emulate_gp(ctxt, 0);
3230 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3231 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
3232 return X86EMUL_CONTINUE;
3233}
3234
3235static int em_mov(struct x86_emulate_ctxt *ctxt)
3236{
3237 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
3238 return X86EMUL_CONTINUE;
3239}
3240
3241static int em_movbe(struct x86_emulate_ctxt *ctxt)
3242{
3243 u16 tmp;
3244
3245 if (!ctxt->ops->guest_has_movbe(ctxt))
3246 return emulate_ud(ctxt);
3247
3248 switch (ctxt->op_bytes) {
3249 case 2:
3250 /*
3251 * From MOVBE definition: "...When the operand size is 16 bits,
3252 * the upper word of the destination register remains unchanged
3253 * ..."
3254 *
3255 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3256 * rules so we have to do the operation almost per hand.
3257 */
3258 tmp = (u16)ctxt->src.val;
3259 ctxt->dst.val &= ~0xffffUL;
3260 ctxt->dst.val |= (unsigned long)swab16(tmp);
3261 break;
3262 case 4:
3263 ctxt->dst.val = swab32((u32)ctxt->src.val);
3264 break;
3265 case 8:
3266 ctxt->dst.val = swab64(ctxt->src.val);
3267 break;
3268 default:
3269 BUG();
3270 }
3271 return X86EMUL_CONTINUE;
3272}
3273
3274static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3275{
3276 int cr_num = ctxt->modrm_reg;
3277 int r;
3278
3279 if (ctxt->ops->set_cr(ctxt, cr_num, ctxt->src.val))
3280 return emulate_gp(ctxt, 0);
3281
3282 /* Disable writeback. */
3283 ctxt->dst.type = OP_NONE;
3284
3285 if (cr_num == 0) {
3286 /*
3287 * CR0 write might have updated CR0.PE and/or CR0.PG
3288 * which can affect the cpu's execution mode.
3289 */
3290 r = emulator_recalc_and_set_mode(ctxt);
3291 if (r != X86EMUL_CONTINUE)
3292 return r;
3293 }
3294
3295 return X86EMUL_CONTINUE;
3296}
3297
3298static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3299{
3300 unsigned long val;
3301
3302 if (ctxt->mode == X86EMUL_MODE_PROT64)
3303 val = ctxt->src.val & ~0ULL;
3304 else
3305 val = ctxt->src.val & ~0U;
3306
3307 /* #UD condition is already handled. */
3308 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3309 return emulate_gp(ctxt, 0);
3310
3311 /* Disable writeback. */
3312 ctxt->dst.type = OP_NONE;
3313 return X86EMUL_CONTINUE;
3314}
3315
3316static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3317{
3318 u64 msr_index = reg_read(ctxt, VCPU_REGS_RCX);
3319 u64 msr_data;
3320 int r;
3321
3322 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3323 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3324 r = ctxt->ops->set_msr_with_filter(ctxt, msr_index, msr_data);
3325
3326 if (r == X86EMUL_PROPAGATE_FAULT)
3327 return emulate_gp(ctxt, 0);
3328
3329 return r;
3330}
3331
3332static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3333{
3334 u64 msr_index = reg_read(ctxt, VCPU_REGS_RCX);
3335 u64 msr_data;
3336 int r;
3337
3338 r = ctxt->ops->get_msr_with_filter(ctxt, msr_index, &msr_data);
3339
3340 if (r == X86EMUL_PROPAGATE_FAULT)
3341 return emulate_gp(ctxt, 0);
3342
3343 if (r == X86EMUL_CONTINUE) {
3344 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3345 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
3346 }
3347 return r;
3348}
3349
3350static int em_store_sreg(struct x86_emulate_ctxt *ctxt, int segment)
3351{
3352 if (segment > VCPU_SREG_GS &&
3353 (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) &&
3354 ctxt->ops->cpl(ctxt) > 0)
3355 return emulate_gp(ctxt, 0);
3356
3357 ctxt->dst.val = get_segment_selector(ctxt, segment);
3358 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3359 ctxt->dst.bytes = 2;
3360 return X86EMUL_CONTINUE;
3361}
3362
3363static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3364{
3365 if (ctxt->modrm_reg > VCPU_SREG_GS)
3366 return emulate_ud(ctxt);
3367
3368 return em_store_sreg(ctxt, ctxt->modrm_reg);
3369}
3370
3371static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3372{
3373 u16 sel = ctxt->src.val;
3374
3375 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
3376 return emulate_ud(ctxt);
3377
3378 if (ctxt->modrm_reg == VCPU_SREG_SS)
3379 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3380
3381 /* Disable writeback. */
3382 ctxt->dst.type = OP_NONE;
3383 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
3384}
3385
3386static int em_sldt(struct x86_emulate_ctxt *ctxt)
3387{
3388 return em_store_sreg(ctxt, VCPU_SREG_LDTR);
3389}
3390
3391static int em_lldt(struct x86_emulate_ctxt *ctxt)
3392{
3393 u16 sel = ctxt->src.val;
3394
3395 /* Disable writeback. */
3396 ctxt->dst.type = OP_NONE;
3397 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3398}
3399
3400static int em_str(struct x86_emulate_ctxt *ctxt)
3401{
3402 return em_store_sreg(ctxt, VCPU_SREG_TR);
3403}
3404
3405static int em_ltr(struct x86_emulate_ctxt *ctxt)
3406{
3407 u16 sel = ctxt->src.val;
3408
3409 /* Disable writeback. */
3410 ctxt->dst.type = OP_NONE;
3411 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3412}
3413
3414static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3415{
3416 int rc;
3417 ulong linear;
3418 unsigned int max_size;
3419
3420 rc = __linearize(ctxt, ctxt->src.addr.mem, &max_size, 1, ctxt->mode,
3421 &linear, X86EMUL_F_INVLPG);
3422 if (rc == X86EMUL_CONTINUE)
3423 ctxt->ops->invlpg(ctxt, linear);
3424 /* Disable writeback. */
3425 ctxt->dst.type = OP_NONE;
3426 return X86EMUL_CONTINUE;
3427}
3428
3429static int em_clts(struct x86_emulate_ctxt *ctxt)
3430{
3431 ulong cr0;
3432
3433 cr0 = ctxt->ops->get_cr(ctxt, 0);
3434 cr0 &= ~X86_CR0_TS;
3435 ctxt->ops->set_cr(ctxt, 0, cr0);
3436 return X86EMUL_CONTINUE;
3437}
3438
3439static int em_hypercall(struct x86_emulate_ctxt *ctxt)
3440{
3441 int rc = ctxt->ops->fix_hypercall(ctxt);
3442
3443 if (rc != X86EMUL_CONTINUE)
3444 return rc;
3445
3446 /* Let the processor re-execute the fixed hypercall */
3447 ctxt->_eip = ctxt->eip;
3448 /* Disable writeback. */
3449 ctxt->dst.type = OP_NONE;
3450 return X86EMUL_CONTINUE;
3451}
3452
3453static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3454 void (*get)(struct x86_emulate_ctxt *ctxt,
3455 struct desc_ptr *ptr))
3456{
3457 struct desc_ptr desc_ptr;
3458
3459 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) &&
3460 ctxt->ops->cpl(ctxt) > 0)
3461 return emulate_gp(ctxt, 0);
3462
3463 if (ctxt->mode == X86EMUL_MODE_PROT64)
3464 ctxt->op_bytes = 8;
3465 get(ctxt, &desc_ptr);
3466 if (ctxt->op_bytes == 2) {
3467 ctxt->op_bytes = 4;
3468 desc_ptr.address &= 0x00ffffff;
3469 }
3470 /* Disable writeback. */
3471 ctxt->dst.type = OP_NONE;
3472 return segmented_write_std(ctxt, ctxt->dst.addr.mem,
3473 &desc_ptr, 2 + ctxt->op_bytes);
3474}
3475
3476static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3477{
3478 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3479}
3480
3481static int em_sidt(struct x86_emulate_ctxt *ctxt)
3482{
3483 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3484}
3485
3486static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
3487{
3488 struct desc_ptr desc_ptr;
3489 int rc;
3490
3491 if (ctxt->mode == X86EMUL_MODE_PROT64)
3492 ctxt->op_bytes = 8;
3493 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3494 &desc_ptr.size, &desc_ptr.address,
3495 ctxt->op_bytes);
3496 if (rc != X86EMUL_CONTINUE)
3497 return rc;
3498 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3499 emul_is_noncanonical_address(desc_ptr.address, ctxt,
3500 X86EMUL_F_DT_LOAD))
3501 return emulate_gp(ctxt, 0);
3502 if (lgdt)
3503 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3504 else
3505 ctxt->ops->set_idt(ctxt, &desc_ptr);
3506 /* Disable writeback. */
3507 ctxt->dst.type = OP_NONE;
3508 return X86EMUL_CONTINUE;
3509}
3510
3511static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3512{
3513 return em_lgdt_lidt(ctxt, true);
3514}
3515
3516static int em_lidt(struct x86_emulate_ctxt *ctxt)
3517{
3518 return em_lgdt_lidt(ctxt, false);
3519}
3520
3521static int em_smsw(struct x86_emulate_ctxt *ctxt)
3522{
3523 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) &&
3524 ctxt->ops->cpl(ctxt) > 0)
3525 return emulate_gp(ctxt, 0);
3526
3527 if (ctxt->dst.type == OP_MEM)
3528 ctxt->dst.bytes = 2;
3529 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
3530 return X86EMUL_CONTINUE;
3531}
3532
3533static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3534{
3535 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
3536 | (ctxt->src.val & 0x0f));
3537 ctxt->dst.type = OP_NONE;
3538 return X86EMUL_CONTINUE;
3539}
3540
3541static int em_loop(struct x86_emulate_ctxt *ctxt)
3542{
3543 int rc = X86EMUL_CONTINUE;
3544
3545 register_address_increment(ctxt, VCPU_REGS_RCX, -1);
3546 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
3547 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3548 rc = jmp_rel(ctxt, ctxt->src.val);
3549
3550 return rc;
3551}
3552
3553static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3554{
3555 int rc = X86EMUL_CONTINUE;
3556
3557 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
3558 rc = jmp_rel(ctxt, ctxt->src.val);
3559
3560 return rc;
3561}
3562
3563static int em_in(struct x86_emulate_ctxt *ctxt)
3564{
3565 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3566 &ctxt->dst.val))
3567 return X86EMUL_IO_NEEDED;
3568
3569 return X86EMUL_CONTINUE;
3570}
3571
3572static int em_out(struct x86_emulate_ctxt *ctxt)
3573{
3574 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3575 &ctxt->src.val, 1);
3576 /* Disable writeback. */
3577 ctxt->dst.type = OP_NONE;
3578 return X86EMUL_CONTINUE;
3579}
3580
3581static int em_cli(struct x86_emulate_ctxt *ctxt)
3582{
3583 if (emulator_bad_iopl(ctxt))
3584 return emulate_gp(ctxt, 0);
3585
3586 ctxt->eflags &= ~X86_EFLAGS_IF;
3587 return X86EMUL_CONTINUE;
3588}
3589
3590static int em_sti(struct x86_emulate_ctxt *ctxt)
3591{
3592 if (emulator_bad_iopl(ctxt))
3593 return emulate_gp(ctxt, 0);
3594
3595 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3596 ctxt->eflags |= X86_EFLAGS_IF;
3597 return X86EMUL_CONTINUE;
3598}
3599
3600static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3601{
3602 u32 eax, ebx, ecx, edx;
3603 u64 msr = 0;
3604
3605 ctxt->ops->get_msr(ctxt, MSR_MISC_FEATURES_ENABLES, &msr);
3606 if (msr & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3607 ctxt->ops->cpl(ctxt)) {
3608 return emulate_gp(ctxt, 0);
3609 }
3610
3611 eax = reg_read(ctxt, VCPU_REGS_RAX);
3612 ecx = reg_read(ctxt, VCPU_REGS_RCX);
3613 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
3614 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3615 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3616 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3617 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
3618 return X86EMUL_CONTINUE;
3619}
3620
3621static int em_sahf(struct x86_emulate_ctxt *ctxt)
3622{
3623 u32 flags;
3624
3625 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
3626 X86_EFLAGS_SF;
3627 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3628
3629 ctxt->eflags &= ~0xffUL;
3630 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3631 return X86EMUL_CONTINUE;
3632}
3633
3634static int em_lahf(struct x86_emulate_ctxt *ctxt)
3635{
3636 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3637 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
3638 return X86EMUL_CONTINUE;
3639}
3640
3641static int em_bswap(struct x86_emulate_ctxt *ctxt)
3642{
3643 switch (ctxt->op_bytes) {
3644#ifdef CONFIG_X86_64
3645 case 8:
3646 asm("bswap %0" : "+r"(ctxt->dst.val));
3647 break;
3648#endif
3649 default:
3650 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3651 break;
3652 }
3653 return X86EMUL_CONTINUE;
3654}
3655
3656static int em_clflush(struct x86_emulate_ctxt *ctxt)
3657{
3658 /* emulating clflush regardless of cpuid */
3659 return X86EMUL_CONTINUE;
3660}
3661
3662static int em_clflushopt(struct x86_emulate_ctxt *ctxt)
3663{
3664 /* emulating clflushopt regardless of cpuid */
3665 return X86EMUL_CONTINUE;
3666}
3667
3668static int em_movsxd(struct x86_emulate_ctxt *ctxt)
3669{
3670 ctxt->dst.val = (s32) ctxt->src.val;
3671 return X86EMUL_CONTINUE;
3672}
3673
3674static int check_fxsr(struct x86_emulate_ctxt *ctxt)
3675{
3676 if (!ctxt->ops->guest_has_fxsr(ctxt))
3677 return emulate_ud(ctxt);
3678
3679 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
3680 return emulate_nm(ctxt);
3681
3682 /*
3683 * Don't emulate a case that should never be hit, instead of working
3684 * around a lack of fxsave64/fxrstor64 on old compilers.
3685 */
3686 if (ctxt->mode >= X86EMUL_MODE_PROT64)
3687 return X86EMUL_UNHANDLEABLE;
3688
3689 return X86EMUL_CONTINUE;
3690}
3691
3692/*
3693 * Hardware doesn't save and restore XMM 0-7 without CR4.OSFXSR, but does save
3694 * and restore MXCSR.
3695 */
3696static size_t __fxstate_size(int nregs)
3697{
3698 return offsetof(struct fxregs_state, xmm_space[0]) + nregs * 16;
3699}
3700
3701static inline size_t fxstate_size(struct x86_emulate_ctxt *ctxt)
3702{
3703 bool cr4_osfxsr;
3704 if (ctxt->mode == X86EMUL_MODE_PROT64)
3705 return __fxstate_size(16);
3706
3707 cr4_osfxsr = ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR;
3708 return __fxstate_size(cr4_osfxsr ? 8 : 0);
3709}
3710
3711/*
3712 * FXSAVE and FXRSTOR have 4 different formats depending on execution mode,
3713 * 1) 16 bit mode
3714 * 2) 32 bit mode
3715 * - like (1), but FIP and FDP (foo) are only 16 bit. At least Intel CPUs
3716 * preserve whole 32 bit values, though, so (1) and (2) are the same wrt.
3717 * save and restore
3718 * 3) 64-bit mode with REX.W prefix
3719 * - like (2), but XMM 8-15 are being saved and restored
3720 * 4) 64-bit mode without REX.W prefix
3721 * - like (3), but FIP and FDP are 64 bit
3722 *
3723 * Emulation uses (3) for (1) and (2) and preserves XMM 8-15 to reach the
3724 * desired result. (4) is not emulated.
3725 *
3726 * Note: Guest and host CPUID.(EAX=07H,ECX=0H):EBX[bit 13] (deprecate FPU CS
3727 * and FPU DS) should match.
3728 */
3729static int em_fxsave(struct x86_emulate_ctxt *ctxt)
3730{
3731 struct fxregs_state fx_state;
3732 int rc;
3733
3734 rc = check_fxsr(ctxt);
3735 if (rc != X86EMUL_CONTINUE)
3736 return rc;
3737
3738 kvm_fpu_get();
3739
3740 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state));
3741
3742 kvm_fpu_put();
3743
3744 if (rc != X86EMUL_CONTINUE)
3745 return rc;
3746
3747 return segmented_write_std(ctxt, ctxt->memop.addr.mem, &fx_state,
3748 fxstate_size(ctxt));
3749}
3750
3751/*
3752 * FXRSTOR might restore XMM registers not provided by the guest. Fill
3753 * in the host registers (via FXSAVE) instead, so they won't be modified.
3754 * (preemption has to stay disabled until FXRSTOR).
3755 *
3756 * Use noinline to keep the stack for other functions called by callers small.
3757 */
3758static noinline int fxregs_fixup(struct fxregs_state *fx_state,
3759 const size_t used_size)
3760{
3761 struct fxregs_state fx_tmp;
3762 int rc;
3763
3764 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_tmp));
3765 memcpy((void *)fx_state + used_size, (void *)&fx_tmp + used_size,
3766 __fxstate_size(16) - used_size);
3767
3768 return rc;
3769}
3770
3771static int em_fxrstor(struct x86_emulate_ctxt *ctxt)
3772{
3773 struct fxregs_state fx_state;
3774 int rc;
3775 size_t size;
3776
3777 rc = check_fxsr(ctxt);
3778 if (rc != X86EMUL_CONTINUE)
3779 return rc;
3780
3781 size = fxstate_size(ctxt);
3782 rc = segmented_read_std(ctxt, ctxt->memop.addr.mem, &fx_state, size);
3783 if (rc != X86EMUL_CONTINUE)
3784 return rc;
3785
3786 kvm_fpu_get();
3787
3788 if (size < __fxstate_size(16)) {
3789 rc = fxregs_fixup(&fx_state, size);
3790 if (rc != X86EMUL_CONTINUE)
3791 goto out;
3792 }
3793
3794 if (fx_state.mxcsr >> 16) {
3795 rc = emulate_gp(ctxt, 0);
3796 goto out;
3797 }
3798
3799 if (rc == X86EMUL_CONTINUE)
3800 rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state));
3801
3802out:
3803 kvm_fpu_put();
3804
3805 return rc;
3806}
3807
3808static int em_xsetbv(struct x86_emulate_ctxt *ctxt)
3809{
3810 u32 eax, ecx, edx;
3811
3812 if (!(ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSXSAVE))
3813 return emulate_ud(ctxt);
3814
3815 eax = reg_read(ctxt, VCPU_REGS_RAX);
3816 edx = reg_read(ctxt, VCPU_REGS_RDX);
3817 ecx = reg_read(ctxt, VCPU_REGS_RCX);
3818
3819 if (ctxt->ops->set_xcr(ctxt, ecx, ((u64)edx << 32) | eax))
3820 return emulate_gp(ctxt, 0);
3821
3822 return X86EMUL_CONTINUE;
3823}
3824
3825static bool valid_cr(int nr)
3826{
3827 switch (nr) {
3828 case 0:
3829 case 2 ... 4:
3830 case 8:
3831 return true;
3832 default:
3833 return false;
3834 }
3835}
3836
3837static int check_cr_access(struct x86_emulate_ctxt *ctxt)
3838{
3839 if (!valid_cr(ctxt->modrm_reg))
3840 return emulate_ud(ctxt);
3841
3842 return X86EMUL_CONTINUE;
3843}
3844
3845static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3846{
3847 int dr = ctxt->modrm_reg;
3848 u64 cr4;
3849
3850 if (dr > 7)
3851 return emulate_ud(ctxt);
3852
3853 cr4 = ctxt->ops->get_cr(ctxt, 4);
3854 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3855 return emulate_ud(ctxt);
3856
3857 if (ctxt->ops->get_dr(ctxt, 7) & DR7_GD) {
3858 ulong dr6;
3859
3860 dr6 = ctxt->ops->get_dr(ctxt, 6);
3861 dr6 &= ~DR_TRAP_BITS;
3862 dr6 |= DR6_BD | DR6_ACTIVE_LOW;
3863 ctxt->ops->set_dr(ctxt, 6, dr6);
3864 return emulate_db(ctxt);
3865 }
3866
3867 return X86EMUL_CONTINUE;
3868}
3869
3870static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3871{
3872 u64 new_val = ctxt->src.val64;
3873 int dr = ctxt->modrm_reg;
3874
3875 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3876 return emulate_gp(ctxt, 0);
3877
3878 return check_dr_read(ctxt);
3879}
3880
3881static int check_svme(struct x86_emulate_ctxt *ctxt)
3882{
3883 u64 efer = 0;
3884
3885 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3886
3887 if (!(efer & EFER_SVME))
3888 return emulate_ud(ctxt);
3889
3890 return X86EMUL_CONTINUE;
3891}
3892
3893static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3894{
3895 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
3896
3897 /* Valid physical address? */
3898 if (rax & 0xffff000000000000ULL)
3899 return emulate_gp(ctxt, 0);
3900
3901 return check_svme(ctxt);
3902}
3903
3904static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3905{
3906 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
3907
3908 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
3909 return emulate_gp(ctxt, 0);
3910
3911 return X86EMUL_CONTINUE;
3912}
3913
3914static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3915{
3916 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
3917 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
3918
3919 /*
3920 * VMware allows access to these Pseduo-PMCs even when read via RDPMC
3921 * in Ring3 when CR4.PCE=0.
3922 */
3923 if (enable_vmware_backdoor && is_vmware_backdoor_pmc(rcx))
3924 return X86EMUL_CONTINUE;
3925
3926 /*
3927 * If CR4.PCE is set, the SDM requires CPL=0 or CR0.PE=0. The CR0.PE
3928 * check however is unnecessary because CPL is always 0 outside
3929 * protected mode.
3930 */
3931 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
3932 ctxt->ops->check_rdpmc_early(ctxt, rcx))
3933 return emulate_gp(ctxt, 0);
3934
3935 return X86EMUL_CONTINUE;
3936}
3937
3938static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3939{
3940 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3941 if (!emulator_io_permitted(ctxt, ctxt->src.val, ctxt->dst.bytes))
3942 return emulate_gp(ctxt, 0);
3943
3944 return X86EMUL_CONTINUE;
3945}
3946
3947static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3948{
3949 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3950 if (!emulator_io_permitted(ctxt, ctxt->dst.val, ctxt->src.bytes))
3951 return emulate_gp(ctxt, 0);
3952
3953 return X86EMUL_CONTINUE;
3954}
3955
3956#define D(_y) { .flags = (_y) }
3957#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3958#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3959 .intercept = x86_intercept_##_i, .check_perm = (_p) }
3960#define N D(NotImpl)
3961#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
3962#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3963#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
3964#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
3965#define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) }
3966#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
3967#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
3968#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
3969#define II(_f, _e, _i) \
3970 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
3971#define IIP(_f, _e, _i, _p) \
3972 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3973 .intercept = x86_intercept_##_i, .check_perm = (_p) }
3974#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
3975
3976#define D2bv(_f) D((_f) | ByteOp), D(_f)
3977#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
3978#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
3979#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
3980#define I2bvIP(_f, _e, _i, _p) \
3981 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
3982
3983#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3984 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3985 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
3986
3987static const struct opcode group7_rm0[] = {
3988 N,
3989 I(SrcNone | Priv | EmulateOnUD, em_hypercall),
3990 N, N, N, N, N, N,
3991};
3992
3993static const struct opcode group7_rm1[] = {
3994 DI(SrcNone | Priv, monitor),
3995 DI(SrcNone | Priv, mwait),
3996 N, N, N, N, N, N,
3997};
3998
3999static const struct opcode group7_rm2[] = {
4000 N,
4001 II(ImplicitOps | Priv, em_xsetbv, xsetbv),
4002 N, N, N, N, N, N,
4003};
4004
4005static const struct opcode group7_rm3[] = {
4006 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
4007 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall),
4008 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
4009 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
4010 DIP(SrcNone | Prot | Priv, stgi, check_svme),
4011 DIP(SrcNone | Prot | Priv, clgi, check_svme),
4012 DIP(SrcNone | Prot | Priv, skinit, check_svme),
4013 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
4014};
4015
4016static const struct opcode group7_rm7[] = {
4017 N,
4018 DIP(SrcNone, rdtscp, check_rdtsc),
4019 N, N, N, N, N, N,
4020};
4021
4022static const struct opcode group1[] = {
4023 F(Lock, em_add),
4024 F(Lock | PageTable, em_or),
4025 F(Lock, em_adc),
4026 F(Lock, em_sbb),
4027 F(Lock | PageTable, em_and),
4028 F(Lock, em_sub),
4029 F(Lock, em_xor),
4030 F(NoWrite, em_cmp),
4031};
4032
4033static const struct opcode group1A[] = {
4034 I(DstMem | SrcNone | Mov | Stack | IncSP | TwoMemOp, em_pop), N, N, N, N, N, N, N,
4035};
4036
4037static const struct opcode group2[] = {
4038 F(DstMem | ModRM, em_rol),
4039 F(DstMem | ModRM, em_ror),
4040 F(DstMem | ModRM, em_rcl),
4041 F(DstMem | ModRM, em_rcr),
4042 F(DstMem | ModRM, em_shl),
4043 F(DstMem | ModRM, em_shr),
4044 F(DstMem | ModRM, em_shl),
4045 F(DstMem | ModRM, em_sar),
4046};
4047
4048static const struct opcode group3[] = {
4049 F(DstMem | SrcImm | NoWrite, em_test),
4050 F(DstMem | SrcImm | NoWrite, em_test),
4051 F(DstMem | SrcNone | Lock, em_not),
4052 F(DstMem | SrcNone | Lock, em_neg),
4053 F(DstXacc | Src2Mem, em_mul_ex),
4054 F(DstXacc | Src2Mem, em_imul_ex),
4055 F(DstXacc | Src2Mem, em_div_ex),
4056 F(DstXacc | Src2Mem, em_idiv_ex),
4057};
4058
4059static const struct opcode group4[] = {
4060 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
4061 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
4062 N, N, N, N, N, N,
4063};
4064
4065static const struct opcode group5[] = {
4066 F(DstMem | SrcNone | Lock, em_inc),
4067 F(DstMem | SrcNone | Lock, em_dec),
4068 I(SrcMem | NearBranch | IsBranch, em_call_near_abs),
4069 I(SrcMemFAddr | ImplicitOps | IsBranch, em_call_far),
4070 I(SrcMem | NearBranch | IsBranch, em_jmp_abs),
4071 I(SrcMemFAddr | ImplicitOps | IsBranch, em_jmp_far),
4072 I(SrcMem | Stack | TwoMemOp, em_push), D(Undefined),
4073};
4074
4075static const struct opcode group6[] = {
4076 II(Prot | DstMem, em_sldt, sldt),
4077 II(Prot | DstMem, em_str, str),
4078 II(Prot | Priv | SrcMem16, em_lldt, lldt),
4079 II(Prot | Priv | SrcMem16, em_ltr, ltr),
4080 N, N, N, N,
4081};
4082
4083static const struct group_dual group7 = { {
4084 II(Mov | DstMem, em_sgdt, sgdt),
4085 II(Mov | DstMem, em_sidt, sidt),
4086 II(SrcMem | Priv, em_lgdt, lgdt),
4087 II(SrcMem | Priv, em_lidt, lidt),
4088 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
4089 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
4090 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
4091}, {
4092 EXT(0, group7_rm0),
4093 EXT(0, group7_rm1),
4094 EXT(0, group7_rm2),
4095 EXT(0, group7_rm3),
4096 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
4097 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
4098 EXT(0, group7_rm7),
4099} };
4100
4101static const struct opcode group8[] = {
4102 N, N, N, N,
4103 F(DstMem | SrcImmByte | NoWrite, em_bt),
4104 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
4105 F(DstMem | SrcImmByte | Lock, em_btr),
4106 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
4107};
4108
4109/*
4110 * The "memory" destination is actually always a register, since we come
4111 * from the register case of group9.
4112 */
4113static const struct gprefix pfx_0f_c7_7 = {
4114 N, N, N, II(DstMem | ModRM | Op3264 | EmulateOnUD, em_rdpid, rdpid),
4115};
4116
4117
4118static const struct group_dual group9 = { {
4119 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
4120}, {
4121 N, N, N, N, N, N, N,
4122 GP(0, &pfx_0f_c7_7),
4123} };
4124
4125static const struct opcode group11[] = {
4126 I(DstMem | SrcImm | Mov | PageTable, em_mov),
4127 X7(D(Undefined)),
4128};
4129
4130static const struct gprefix pfx_0f_ae_7 = {
4131 I(SrcMem | ByteOp, em_clflush), I(SrcMem | ByteOp, em_clflushopt), N, N,
4132};
4133
4134static const struct group_dual group15 = { {
4135 I(ModRM | Aligned16, em_fxsave),
4136 I(ModRM | Aligned16, em_fxrstor),
4137 N, N, N, N, N, GP(0, &pfx_0f_ae_7),
4138}, {
4139 N, N, N, N, N, N, N, N,
4140} };
4141
4142static const struct gprefix pfx_0f_6f_0f_7f = {
4143 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
4144};
4145
4146static const struct instr_dual instr_dual_0f_2b = {
4147 I(0, em_mov), N
4148};
4149
4150static const struct gprefix pfx_0f_2b = {
4151 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
4152};
4153
4154static const struct gprefix pfx_0f_10_0f_11 = {
4155 I(Unaligned, em_mov), I(Unaligned, em_mov), N, N,
4156};
4157
4158static const struct gprefix pfx_0f_28_0f_29 = {
4159 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
4160};
4161
4162static const struct gprefix pfx_0f_e7 = {
4163 N, I(Sse, em_mov), N, N,
4164};
4165
4166static const struct escape escape_d9 = { {
4167 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
4168}, {
4169 /* 0xC0 - 0xC7 */
4170 N, N, N, N, N, N, N, N,
4171 /* 0xC8 - 0xCF */
4172 N, N, N, N, N, N, N, N,
4173 /* 0xD0 - 0xC7 */
4174 N, N, N, N, N, N, N, N,
4175 /* 0xD8 - 0xDF */
4176 N, N, N, N, N, N, N, N,
4177 /* 0xE0 - 0xE7 */
4178 N, N, N, N, N, N, N, N,
4179 /* 0xE8 - 0xEF */
4180 N, N, N, N, N, N, N, N,
4181 /* 0xF0 - 0xF7 */
4182 N, N, N, N, N, N, N, N,
4183 /* 0xF8 - 0xFF */
4184 N, N, N, N, N, N, N, N,
4185} };
4186
4187static const struct escape escape_db = { {
4188 N, N, N, N, N, N, N, N,
4189}, {
4190 /* 0xC0 - 0xC7 */
4191 N, N, N, N, N, N, N, N,
4192 /* 0xC8 - 0xCF */
4193 N, N, N, N, N, N, N, N,
4194 /* 0xD0 - 0xC7 */
4195 N, N, N, N, N, N, N, N,
4196 /* 0xD8 - 0xDF */
4197 N, N, N, N, N, N, N, N,
4198 /* 0xE0 - 0xE7 */
4199 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
4200 /* 0xE8 - 0xEF */
4201 N, N, N, N, N, N, N, N,
4202 /* 0xF0 - 0xF7 */
4203 N, N, N, N, N, N, N, N,
4204 /* 0xF8 - 0xFF */
4205 N, N, N, N, N, N, N, N,
4206} };
4207
4208static const struct escape escape_dd = { {
4209 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
4210}, {
4211 /* 0xC0 - 0xC7 */
4212 N, N, N, N, N, N, N, N,
4213 /* 0xC8 - 0xCF */
4214 N, N, N, N, N, N, N, N,
4215 /* 0xD0 - 0xC7 */
4216 N, N, N, N, N, N, N, N,
4217 /* 0xD8 - 0xDF */
4218 N, N, N, N, N, N, N, N,
4219 /* 0xE0 - 0xE7 */
4220 N, N, N, N, N, N, N, N,
4221 /* 0xE8 - 0xEF */
4222 N, N, N, N, N, N, N, N,
4223 /* 0xF0 - 0xF7 */
4224 N, N, N, N, N, N, N, N,
4225 /* 0xF8 - 0xFF */
4226 N, N, N, N, N, N, N, N,
4227} };
4228
4229static const struct instr_dual instr_dual_0f_c3 = {
4230 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
4231};
4232
4233static const struct mode_dual mode_dual_63 = {
4234 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd)
4235};
4236
4237static const struct instr_dual instr_dual_8d = {
4238 D(DstReg | SrcMem | ModRM | NoAccess), N
4239};
4240
4241static const struct opcode opcode_table[256] = {
4242 /* 0x00 - 0x07 */
4243 F6ALU(Lock, em_add),
4244 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
4245 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
4246 /* 0x08 - 0x0F */
4247 F6ALU(Lock | PageTable, em_or),
4248 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
4249 N,
4250 /* 0x10 - 0x17 */
4251 F6ALU(Lock, em_adc),
4252 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
4253 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
4254 /* 0x18 - 0x1F */
4255 F6ALU(Lock, em_sbb),
4256 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
4257 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
4258 /* 0x20 - 0x27 */
4259 F6ALU(Lock | PageTable, em_and), N, N,
4260 /* 0x28 - 0x2F */
4261 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
4262 /* 0x30 - 0x37 */
4263 F6ALU(Lock, em_xor), N, N,
4264 /* 0x38 - 0x3F */
4265 F6ALU(NoWrite, em_cmp), N, N,
4266 /* 0x40 - 0x4F */
4267 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
4268 /* 0x50 - 0x57 */
4269 X8(I(SrcReg | Stack, em_push)),
4270 /* 0x58 - 0x5F */
4271 X8(I(DstReg | Stack, em_pop)),
4272 /* 0x60 - 0x67 */
4273 I(ImplicitOps | Stack | No64, em_pusha),
4274 I(ImplicitOps | Stack | No64, em_popa),
4275 N, MD(ModRM, &mode_dual_63),
4276 N, N, N, N,
4277 /* 0x68 - 0x6F */
4278 I(SrcImm | Mov | Stack, em_push),
4279 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
4280 I(SrcImmByte | Mov | Stack, em_push),
4281 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
4282 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
4283 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
4284 /* 0x70 - 0x7F */
4285 X16(D(SrcImmByte | NearBranch | IsBranch)),
4286 /* 0x80 - 0x87 */
4287 G(ByteOp | DstMem | SrcImm, group1),
4288 G(DstMem | SrcImm, group1),
4289 G(ByteOp | DstMem | SrcImm | No64, group1),
4290 G(DstMem | SrcImmByte, group1),
4291 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
4292 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
4293 /* 0x88 - 0x8F */
4294 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
4295 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
4296 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
4297 ID(0, &instr_dual_8d),
4298 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
4299 G(0, group1A),
4300 /* 0x90 - 0x97 */
4301 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
4302 /* 0x98 - 0x9F */
4303 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
4304 I(SrcImmFAddr | No64 | IsBranch, em_call_far), N,
4305 II(ImplicitOps | Stack, em_pushf, pushf),
4306 II(ImplicitOps | Stack, em_popf, popf),
4307 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
4308 /* 0xA0 - 0xA7 */
4309 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
4310 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
4311 I2bv(SrcSI | DstDI | Mov | String | TwoMemOp, em_mov),
4312 F2bv(SrcSI | DstDI | String | NoWrite | TwoMemOp, em_cmp_r),
4313 /* 0xA8 - 0xAF */
4314 F2bv(DstAcc | SrcImm | NoWrite, em_test),
4315 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4316 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
4317 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
4318 /* 0xB0 - 0xB7 */
4319 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
4320 /* 0xB8 - 0xBF */
4321 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
4322 /* 0xC0 - 0xC7 */
4323 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
4324 I(ImplicitOps | NearBranch | SrcImmU16 | IsBranch, em_ret_near_imm),
4325 I(ImplicitOps | NearBranch | IsBranch, em_ret),
4326 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4327 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
4328 G(ByteOp, group11), G(0, group11),
4329 /* 0xC8 - 0xCF */
4330 I(Stack | SrcImmU16 | Src2ImmByte | IsBranch, em_enter),
4331 I(Stack | IsBranch, em_leave),
4332 I(ImplicitOps | SrcImmU16 | IsBranch, em_ret_far_imm),
4333 I(ImplicitOps | IsBranch, em_ret_far),
4334 D(ImplicitOps | IsBranch), DI(SrcImmByte | IsBranch, intn),
4335 D(ImplicitOps | No64 | IsBranch),
4336 II(ImplicitOps | IsBranch, em_iret, iret),
4337 /* 0xD0 - 0xD7 */
4338 G(Src2One | ByteOp, group2), G(Src2One, group2),
4339 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
4340 I(DstAcc | SrcImmUByte | No64, em_aam),
4341 I(DstAcc | SrcImmUByte | No64, em_aad),
4342 F(DstAcc | ByteOp | No64, em_salc),
4343 I(DstAcc | SrcXLat | ByteOp, em_mov),
4344 /* 0xD8 - 0xDF */
4345 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
4346 /* 0xE0 - 0xE7 */
4347 X3(I(SrcImmByte | NearBranch | IsBranch, em_loop)),
4348 I(SrcImmByte | NearBranch | IsBranch, em_jcxz),
4349 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4350 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
4351 /* 0xE8 - 0xEF */
4352 I(SrcImm | NearBranch | IsBranch, em_call),
4353 D(SrcImm | ImplicitOps | NearBranch | IsBranch),
4354 I(SrcImmFAddr | No64 | IsBranch, em_jmp_far),
4355 D(SrcImmByte | ImplicitOps | NearBranch | IsBranch),
4356 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4357 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
4358 /* 0xF0 - 0xF7 */
4359 N, DI(ImplicitOps, icebp), N, N,
4360 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4361 G(ByteOp, group3), G(0, group3),
4362 /* 0xF8 - 0xFF */
4363 D(ImplicitOps), D(ImplicitOps),
4364 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
4365 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4366};
4367
4368static const struct opcode twobyte_table[256] = {
4369 /* 0x00 - 0x0F */
4370 G(0, group6), GD(0, &group7), N, N,
4371 N, I(ImplicitOps | EmulateOnUD | IsBranch, em_syscall),
4372 II(ImplicitOps | Priv, em_clts, clts), N,
4373 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
4374 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
4375 /* 0x10 - 0x1F */
4376 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_10_0f_11),
4377 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_10_0f_11),
4378 N, N, N, N, N, N,
4379 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 4 * prefetch + 4 * reserved NOP */
4380 D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
4381 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */
4382 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */
4383 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */
4384 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* NOP + 7 * reserved NOP */
4385 /* 0x20 - 0x2F */
4386 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_access),
4387 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4388 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4389 check_cr_access),
4390 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4391 check_dr_write),
4392 N, N, N, N,
4393 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4394 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
4395 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
4396 N, N, N, N,
4397 /* 0x30 - 0x3F */
4398 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
4399 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
4400 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
4401 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
4402 I(ImplicitOps | EmulateOnUD | IsBranch, em_sysenter),
4403 I(ImplicitOps | Priv | EmulateOnUD | IsBranch, em_sysexit),
4404 N, N,
4405 N, N, N, N, N, N, N, N,
4406 /* 0x40 - 0x4F */
4407 X16(D(DstReg | SrcMem | ModRM)),
4408 /* 0x50 - 0x5F */
4409 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4410 /* 0x60 - 0x6F */
4411 N, N, N, N,
4412 N, N, N, N,
4413 N, N, N, N,
4414 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
4415 /* 0x70 - 0x7F */
4416 N, N, N, N,
4417 N, N, N, N,
4418 N, N, N, N,
4419 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
4420 /* 0x80 - 0x8F */
4421 X16(D(SrcImm | NearBranch | IsBranch)),
4422 /* 0x90 - 0x9F */
4423 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
4424 /* 0xA0 - 0xA7 */
4425 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
4426 II(ImplicitOps, em_cpuid, cpuid),
4427 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
4428 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4429 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
4430 /* 0xA8 - 0xAF */
4431 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
4432 II(EmulateOnUD | ImplicitOps, em_rsm, rsm),
4433 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
4434 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4435 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4436 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
4437 /* 0xB0 - 0xB7 */
4438 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg),
4439 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
4440 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
4441 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4442 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
4443 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
4444 /* 0xB8 - 0xBF */
4445 N, N,
4446 G(BitOp, group8),
4447 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4448 I(DstReg | SrcMem | ModRM, em_bsf_c),
4449 I(DstReg | SrcMem | ModRM, em_bsr_c),
4450 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
4451 /* 0xC0 - 0xC7 */
4452 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
4453 N, ID(0, &instr_dual_0f_c3),
4454 N, N, N, GD(0, &group9),
4455 /* 0xC8 - 0xCF */
4456 X8(I(DstReg, em_bswap)),
4457 /* 0xD0 - 0xDF */
4458 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4459 /* 0xE0 - 0xEF */
4460 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4461 N, N, N, N, N, N, N, N,
4462 /* 0xF0 - 0xFF */
4463 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4464};
4465
4466static const struct instr_dual instr_dual_0f_38_f0 = {
4467 I(DstReg | SrcMem | Mov, em_movbe), N
4468};
4469
4470static const struct instr_dual instr_dual_0f_38_f1 = {
4471 I(DstMem | SrcReg | Mov, em_movbe), N
4472};
4473
4474static const struct gprefix three_byte_0f_38_f0 = {
4475 ID(0, &instr_dual_0f_38_f0), ID(0, &instr_dual_0f_38_f0), N, N
4476};
4477
4478static const struct gprefix three_byte_0f_38_f1 = {
4479 ID(0, &instr_dual_0f_38_f1), ID(0, &instr_dual_0f_38_f1), N, N
4480};
4481
4482/*
4483 * Insns below are selected by the prefix which indexed by the third opcode
4484 * byte.
4485 */
4486static const struct opcode opcode_map_0f_38[256] = {
4487 /* 0x00 - 0x7f */
4488 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4489 /* 0x80 - 0xef */
4490 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4491 /* 0xf0 - 0xf1 */
4492 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
4493 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
4494 /* 0xf2 - 0xff */
4495 N, N, X4(N), X8(N)
4496};
4497
4498#undef D
4499#undef N
4500#undef G
4501#undef GD
4502#undef I
4503#undef GP
4504#undef EXT
4505#undef MD
4506#undef ID
4507
4508#undef D2bv
4509#undef D2bvIP
4510#undef I2bv
4511#undef I2bvIP
4512#undef I6ALU
4513
4514static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
4515{
4516 unsigned size;
4517
4518 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4519 if (size == 8)
4520 size = 4;
4521 return size;
4522}
4523
4524static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4525 unsigned size, bool sign_extension)
4526{
4527 int rc = X86EMUL_CONTINUE;
4528
4529 op->type = OP_IMM;
4530 op->bytes = size;
4531 op->addr.mem.ea = ctxt->_eip;
4532 /* NB. Immediates are sign-extended as necessary. */
4533 switch (op->bytes) {
4534 case 1:
4535 op->val = insn_fetch(s8, ctxt);
4536 break;
4537 case 2:
4538 op->val = insn_fetch(s16, ctxt);
4539 break;
4540 case 4:
4541 op->val = insn_fetch(s32, ctxt);
4542 break;
4543 case 8:
4544 op->val = insn_fetch(s64, ctxt);
4545 break;
4546 }
4547 if (!sign_extension) {
4548 switch (op->bytes) {
4549 case 1:
4550 op->val &= 0xff;
4551 break;
4552 case 2:
4553 op->val &= 0xffff;
4554 break;
4555 case 4:
4556 op->val &= 0xffffffff;
4557 break;
4558 }
4559 }
4560done:
4561 return rc;
4562}
4563
4564static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4565 unsigned d)
4566{
4567 int rc = X86EMUL_CONTINUE;
4568
4569 switch (d) {
4570 case OpReg:
4571 decode_register_operand(ctxt, op);
4572 break;
4573 case OpImmUByte:
4574 rc = decode_imm(ctxt, op, 1, false);
4575 break;
4576 case OpMem:
4577 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4578 mem_common:
4579 *op = ctxt->memop;
4580 ctxt->memopp = op;
4581 if (ctxt->d & BitOp)
4582 fetch_bit_operand(ctxt);
4583 op->orig_val = op->val;
4584 break;
4585 case OpMem64:
4586 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
4587 goto mem_common;
4588 case OpAcc:
4589 op->type = OP_REG;
4590 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4591 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4592 fetch_register_operand(op);
4593 op->orig_val = op->val;
4594 break;
4595 case OpAccLo:
4596 op->type = OP_REG;
4597 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4598 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4599 fetch_register_operand(op);
4600 op->orig_val = op->val;
4601 break;
4602 case OpAccHi:
4603 if (ctxt->d & ByteOp) {
4604 op->type = OP_NONE;
4605 break;
4606 }
4607 op->type = OP_REG;
4608 op->bytes = ctxt->op_bytes;
4609 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4610 fetch_register_operand(op);
4611 op->orig_val = op->val;
4612 break;
4613 case OpDI:
4614 op->type = OP_MEM;
4615 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4616 op->addr.mem.ea =
4617 register_address(ctxt, VCPU_REGS_RDI);
4618 op->addr.mem.seg = VCPU_SREG_ES;
4619 op->val = 0;
4620 op->count = 1;
4621 break;
4622 case OpDX:
4623 op->type = OP_REG;
4624 op->bytes = 2;
4625 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4626 fetch_register_operand(op);
4627 break;
4628 case OpCL:
4629 op->type = OP_IMM;
4630 op->bytes = 1;
4631 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4632 break;
4633 case OpImmByte:
4634 rc = decode_imm(ctxt, op, 1, true);
4635 break;
4636 case OpOne:
4637 op->type = OP_IMM;
4638 op->bytes = 1;
4639 op->val = 1;
4640 break;
4641 case OpImm:
4642 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4643 break;
4644 case OpImm64:
4645 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4646 break;
4647 case OpMem8:
4648 ctxt->memop.bytes = 1;
4649 if (ctxt->memop.type == OP_REG) {
4650 ctxt->memop.addr.reg = decode_register(ctxt,
4651 ctxt->modrm_rm, true);
4652 fetch_register_operand(&ctxt->memop);
4653 }
4654 goto mem_common;
4655 case OpMem16:
4656 ctxt->memop.bytes = 2;
4657 goto mem_common;
4658 case OpMem32:
4659 ctxt->memop.bytes = 4;
4660 goto mem_common;
4661 case OpImmU16:
4662 rc = decode_imm(ctxt, op, 2, false);
4663 break;
4664 case OpImmU:
4665 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4666 break;
4667 case OpSI:
4668 op->type = OP_MEM;
4669 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4670 op->addr.mem.ea =
4671 register_address(ctxt, VCPU_REGS_RSI);
4672 op->addr.mem.seg = ctxt->seg_override;
4673 op->val = 0;
4674 op->count = 1;
4675 break;
4676 case OpXLat:
4677 op->type = OP_MEM;
4678 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4679 op->addr.mem.ea =
4680 address_mask(ctxt,
4681 reg_read(ctxt, VCPU_REGS_RBX) +
4682 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
4683 op->addr.mem.seg = ctxt->seg_override;
4684 op->val = 0;
4685 break;
4686 case OpImmFAddr:
4687 op->type = OP_IMM;
4688 op->addr.mem.ea = ctxt->_eip;
4689 op->bytes = ctxt->op_bytes + 2;
4690 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4691 break;
4692 case OpMemFAddr:
4693 ctxt->memop.bytes = ctxt->op_bytes + 2;
4694 goto mem_common;
4695 case OpES:
4696 op->type = OP_IMM;
4697 op->val = VCPU_SREG_ES;
4698 break;
4699 case OpCS:
4700 op->type = OP_IMM;
4701 op->val = VCPU_SREG_CS;
4702 break;
4703 case OpSS:
4704 op->type = OP_IMM;
4705 op->val = VCPU_SREG_SS;
4706 break;
4707 case OpDS:
4708 op->type = OP_IMM;
4709 op->val = VCPU_SREG_DS;
4710 break;
4711 case OpFS:
4712 op->type = OP_IMM;
4713 op->val = VCPU_SREG_FS;
4714 break;
4715 case OpGS:
4716 op->type = OP_IMM;
4717 op->val = VCPU_SREG_GS;
4718 break;
4719 case OpImplicit:
4720 /* Special instructions do their own operand decoding. */
4721 default:
4722 op->type = OP_NONE; /* Disable writeback. */
4723 break;
4724 }
4725
4726done:
4727 return rc;
4728}
4729
4730int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len, int emulation_type)
4731{
4732 int rc = X86EMUL_CONTINUE;
4733 int mode = ctxt->mode;
4734 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
4735 bool op_prefix = false;
4736 bool has_seg_override = false;
4737 struct opcode opcode;
4738 u16 dummy;
4739 struct desc_struct desc;
4740
4741 ctxt->memop.type = OP_NONE;
4742 ctxt->memopp = NULL;
4743 ctxt->_eip = ctxt->eip;
4744 ctxt->fetch.ptr = ctxt->fetch.data;
4745 ctxt->fetch.end = ctxt->fetch.data + insn_len;
4746 ctxt->opcode_len = 1;
4747 ctxt->intercept = x86_intercept_none;
4748 if (insn_len > 0)
4749 memcpy(ctxt->fetch.data, insn, insn_len);
4750 else {
4751 rc = __do_insn_fetch_bytes(ctxt, 1);
4752 if (rc != X86EMUL_CONTINUE)
4753 goto done;
4754 }
4755
4756 switch (mode) {
4757 case X86EMUL_MODE_REAL:
4758 case X86EMUL_MODE_VM86:
4759 def_op_bytes = def_ad_bytes = 2;
4760 ctxt->ops->get_segment(ctxt, &dummy, &desc, NULL, VCPU_SREG_CS);
4761 if (desc.d)
4762 def_op_bytes = def_ad_bytes = 4;
4763 break;
4764 case X86EMUL_MODE_PROT16:
4765 def_op_bytes = def_ad_bytes = 2;
4766 break;
4767 case X86EMUL_MODE_PROT32:
4768 def_op_bytes = def_ad_bytes = 4;
4769 break;
4770#ifdef CONFIG_X86_64
4771 case X86EMUL_MODE_PROT64:
4772 def_op_bytes = 4;
4773 def_ad_bytes = 8;
4774 break;
4775#endif
4776 default:
4777 return EMULATION_FAILED;
4778 }
4779
4780 ctxt->op_bytes = def_op_bytes;
4781 ctxt->ad_bytes = def_ad_bytes;
4782
4783 /* Legacy prefixes. */
4784 for (;;) {
4785 switch (ctxt->b = insn_fetch(u8, ctxt)) {
4786 case 0x66: /* operand-size override */
4787 op_prefix = true;
4788 /* switch between 2/4 bytes */
4789 ctxt->op_bytes = def_op_bytes ^ 6;
4790 break;
4791 case 0x67: /* address-size override */
4792 if (mode == X86EMUL_MODE_PROT64)
4793 /* switch between 4/8 bytes */
4794 ctxt->ad_bytes = def_ad_bytes ^ 12;
4795 else
4796 /* switch between 2/4 bytes */
4797 ctxt->ad_bytes = def_ad_bytes ^ 6;
4798 break;
4799 case 0x26: /* ES override */
4800 has_seg_override = true;
4801 ctxt->seg_override = VCPU_SREG_ES;
4802 break;
4803 case 0x2e: /* CS override */
4804 has_seg_override = true;
4805 ctxt->seg_override = VCPU_SREG_CS;
4806 break;
4807 case 0x36: /* SS override */
4808 has_seg_override = true;
4809 ctxt->seg_override = VCPU_SREG_SS;
4810 break;
4811 case 0x3e: /* DS override */
4812 has_seg_override = true;
4813 ctxt->seg_override = VCPU_SREG_DS;
4814 break;
4815 case 0x64: /* FS override */
4816 has_seg_override = true;
4817 ctxt->seg_override = VCPU_SREG_FS;
4818 break;
4819 case 0x65: /* GS override */
4820 has_seg_override = true;
4821 ctxt->seg_override = VCPU_SREG_GS;
4822 break;
4823 case 0x40 ... 0x4f: /* REX */
4824 if (mode != X86EMUL_MODE_PROT64)
4825 goto done_prefixes;
4826 ctxt->rex_prefix = ctxt->b;
4827 continue;
4828 case 0xf0: /* LOCK */
4829 ctxt->lock_prefix = 1;
4830 break;
4831 case 0xf2: /* REPNE/REPNZ */
4832 case 0xf3: /* REP/REPE/REPZ */
4833 ctxt->rep_prefix = ctxt->b;
4834 break;
4835 default:
4836 goto done_prefixes;
4837 }
4838
4839 /* Any legacy prefix after a REX prefix nullifies its effect. */
4840
4841 ctxt->rex_prefix = 0;
4842 }
4843
4844done_prefixes:
4845
4846 /* REX prefix. */
4847 if (ctxt->rex_prefix & 8)
4848 ctxt->op_bytes = 8; /* REX.W */
4849
4850 /* Opcode byte(s). */
4851 opcode = opcode_table[ctxt->b];
4852 /* Two-byte opcode? */
4853 if (ctxt->b == 0x0f) {
4854 ctxt->opcode_len = 2;
4855 ctxt->b = insn_fetch(u8, ctxt);
4856 opcode = twobyte_table[ctxt->b];
4857
4858 /* 0F_38 opcode map */
4859 if (ctxt->b == 0x38) {
4860 ctxt->opcode_len = 3;
4861 ctxt->b = insn_fetch(u8, ctxt);
4862 opcode = opcode_map_0f_38[ctxt->b];
4863 }
4864 }
4865 ctxt->d = opcode.flags;
4866
4867 if (ctxt->d & ModRM)
4868 ctxt->modrm = insn_fetch(u8, ctxt);
4869
4870 /* vex-prefix instructions are not implemented */
4871 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
4872 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
4873 ctxt->d = NotImpl;
4874 }
4875
4876 while (ctxt->d & GroupMask) {
4877 switch (ctxt->d & GroupMask) {
4878 case Group:
4879 goffset = (ctxt->modrm >> 3) & 7;
4880 opcode = opcode.u.group[goffset];
4881 break;
4882 case GroupDual:
4883 goffset = (ctxt->modrm >> 3) & 7;
4884 if ((ctxt->modrm >> 6) == 3)
4885 opcode = opcode.u.gdual->mod3[goffset];
4886 else
4887 opcode = opcode.u.gdual->mod012[goffset];
4888 break;
4889 case RMExt:
4890 goffset = ctxt->modrm & 7;
4891 opcode = opcode.u.group[goffset];
4892 break;
4893 case Prefix:
4894 if (ctxt->rep_prefix && op_prefix)
4895 return EMULATION_FAILED;
4896 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
4897 switch (simd_prefix) {
4898 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4899 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4900 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4901 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4902 }
4903 break;
4904 case Escape:
4905 if (ctxt->modrm > 0xbf) {
4906 size_t size = ARRAY_SIZE(opcode.u.esc->high);
4907 u32 index = array_index_nospec(
4908 ctxt->modrm - 0xc0, size);
4909
4910 opcode = opcode.u.esc->high[index];
4911 } else {
4912 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4913 }
4914 break;
4915 case InstrDual:
4916 if ((ctxt->modrm >> 6) == 3)
4917 opcode = opcode.u.idual->mod3;
4918 else
4919 opcode = opcode.u.idual->mod012;
4920 break;
4921 case ModeDual:
4922 if (ctxt->mode == X86EMUL_MODE_PROT64)
4923 opcode = opcode.u.mdual->mode64;
4924 else
4925 opcode = opcode.u.mdual->mode32;
4926 break;
4927 default:
4928 return EMULATION_FAILED;
4929 }
4930
4931 ctxt->d &= ~(u64)GroupMask;
4932 ctxt->d |= opcode.flags;
4933 }
4934
4935 ctxt->is_branch = opcode.flags & IsBranch;
4936
4937 /* Unrecognised? */
4938 if (ctxt->d == 0)
4939 return EMULATION_FAILED;
4940
4941 ctxt->execute = opcode.u.execute;
4942
4943 if (unlikely(emulation_type & EMULTYPE_TRAP_UD) &&
4944 likely(!(ctxt->d & EmulateOnUD)))
4945 return EMULATION_FAILED;
4946
4947 if (unlikely(ctxt->d &
4948 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
4949 No16))) {
4950 /*
4951 * These are copied unconditionally here, and checked unconditionally
4952 * in x86_emulate_insn.
4953 */
4954 ctxt->check_perm = opcode.check_perm;
4955 ctxt->intercept = opcode.intercept;
4956
4957 if (ctxt->d & NotImpl)
4958 return EMULATION_FAILED;
4959
4960 if (mode == X86EMUL_MODE_PROT64) {
4961 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
4962 ctxt->op_bytes = 8;
4963 else if (ctxt->d & NearBranch)
4964 ctxt->op_bytes = 8;
4965 }
4966
4967 if (ctxt->d & Op3264) {
4968 if (mode == X86EMUL_MODE_PROT64)
4969 ctxt->op_bytes = 8;
4970 else
4971 ctxt->op_bytes = 4;
4972 }
4973
4974 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
4975 ctxt->op_bytes = 4;
4976
4977 if (ctxt->d & Sse)
4978 ctxt->op_bytes = 16;
4979 else if (ctxt->d & Mmx)
4980 ctxt->op_bytes = 8;
4981 }
4982
4983 /* ModRM and SIB bytes. */
4984 if (ctxt->d & ModRM) {
4985 rc = decode_modrm(ctxt, &ctxt->memop);
4986 if (!has_seg_override) {
4987 has_seg_override = true;
4988 ctxt->seg_override = ctxt->modrm_seg;
4989 }
4990 } else if (ctxt->d & MemAbs)
4991 rc = decode_abs(ctxt, &ctxt->memop);
4992 if (rc != X86EMUL_CONTINUE)
4993 goto done;
4994
4995 if (!has_seg_override)
4996 ctxt->seg_override = VCPU_SREG_DS;
4997
4998 ctxt->memop.addr.mem.seg = ctxt->seg_override;
4999
5000 /*
5001 * Decode and fetch the source operand: register, memory
5002 * or immediate.
5003 */
5004 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
5005 if (rc != X86EMUL_CONTINUE)
5006 goto done;
5007
5008 /*
5009 * Decode and fetch the second source operand: register, memory
5010 * or immediate.
5011 */
5012 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
5013 if (rc != X86EMUL_CONTINUE)
5014 goto done;
5015
5016 /* Decode and fetch the destination operand: register or memory. */
5017 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
5018
5019 if (ctxt->rip_relative && likely(ctxt->memopp))
5020 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
5021 ctxt->memopp->addr.mem.ea + ctxt->_eip);
5022
5023done:
5024 if (rc == X86EMUL_PROPAGATE_FAULT)
5025 ctxt->have_exception = true;
5026 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
5027}
5028
5029bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
5030{
5031 return ctxt->d & PageTable;
5032}
5033
5034static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
5035{
5036 /* The second termination condition only applies for REPE
5037 * and REPNE. Test if the repeat string operation prefix is
5038 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
5039 * corresponding termination condition according to:
5040 * - if REPE/REPZ and ZF = 0 then done
5041 * - if REPNE/REPNZ and ZF = 1 then done
5042 */
5043 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
5044 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
5045 && (((ctxt->rep_prefix == REPE_PREFIX) &&
5046 ((ctxt->eflags & X86_EFLAGS_ZF) == 0))
5047 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
5048 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF))))
5049 return true;
5050
5051 return false;
5052}
5053
5054static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
5055{
5056 int rc;
5057
5058 kvm_fpu_get();
5059 rc = asm_safe("fwait");
5060 kvm_fpu_put();
5061
5062 if (unlikely(rc != X86EMUL_CONTINUE))
5063 return emulate_exception(ctxt, MF_VECTOR, 0, false);
5064
5065 return X86EMUL_CONTINUE;
5066}
5067
5068static void fetch_possible_mmx_operand(struct operand *op)
5069{
5070 if (op->type == OP_MM)
5071 kvm_read_mmx_reg(op->addr.mm, &op->mm_val);
5072}
5073
5074static int fastop(struct x86_emulate_ctxt *ctxt, fastop_t fop)
5075{
5076 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
5077
5078 if (!(ctxt->d & ByteOp))
5079 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
5080
5081 asm("push %[flags]; popf; " CALL_NOSPEC " ; pushf; pop %[flags]\n"
5082 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
5083 [thunk_target]"+S"(fop), ASM_CALL_CONSTRAINT
5084 : "c"(ctxt->src2.val));
5085
5086 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
5087 if (!fop) /* exception is returned in fop variable */
5088 return emulate_de(ctxt);
5089 return X86EMUL_CONTINUE;
5090}
5091
5092void init_decode_cache(struct x86_emulate_ctxt *ctxt)
5093{
5094 /* Clear fields that are set conditionally but read without a guard. */
5095 ctxt->rip_relative = false;
5096 ctxt->rex_prefix = 0;
5097 ctxt->lock_prefix = 0;
5098 ctxt->rep_prefix = 0;
5099 ctxt->regs_valid = 0;
5100 ctxt->regs_dirty = 0;
5101
5102 ctxt->io_read.pos = 0;
5103 ctxt->io_read.end = 0;
5104 ctxt->mem_read.end = 0;
5105}
5106
5107int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
5108{
5109 const struct x86_emulate_ops *ops = ctxt->ops;
5110 int rc = X86EMUL_CONTINUE;
5111 int saved_dst_type = ctxt->dst.type;
5112 bool is_guest_mode = ctxt->ops->is_guest_mode(ctxt);
5113
5114 ctxt->mem_read.pos = 0;
5115
5116 /* LOCK prefix is allowed only with some instructions */
5117 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
5118 rc = emulate_ud(ctxt);
5119 goto done;
5120 }
5121
5122 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
5123 rc = emulate_ud(ctxt);
5124 goto done;
5125 }
5126
5127 if (unlikely(ctxt->d &
5128 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
5129 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
5130 (ctxt->d & Undefined)) {
5131 rc = emulate_ud(ctxt);
5132 goto done;
5133 }
5134
5135 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
5136 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
5137 rc = emulate_ud(ctxt);
5138 goto done;
5139 }
5140
5141 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
5142 rc = emulate_nm(ctxt);
5143 goto done;
5144 }
5145
5146 if (ctxt->d & Mmx) {
5147 rc = flush_pending_x87_faults(ctxt);
5148 if (rc != X86EMUL_CONTINUE)
5149 goto done;
5150 /*
5151 * Now that we know the fpu is exception safe, we can fetch
5152 * operands from it.
5153 */
5154 fetch_possible_mmx_operand(&ctxt->src);
5155 fetch_possible_mmx_operand(&ctxt->src2);
5156 if (!(ctxt->d & Mov))
5157 fetch_possible_mmx_operand(&ctxt->dst);
5158 }
5159
5160 if (unlikely(is_guest_mode) && ctxt->intercept) {
5161 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5162 X86_ICPT_PRE_EXCEPT);
5163 if (rc != X86EMUL_CONTINUE)
5164 goto done;
5165 }
5166
5167 /* Instruction can only be executed in protected mode */
5168 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
5169 rc = emulate_ud(ctxt);
5170 goto done;
5171 }
5172
5173 /* Privileged instruction can be executed only in CPL=0 */
5174 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
5175 if (ctxt->d & PrivUD)
5176 rc = emulate_ud(ctxt);
5177 else
5178 rc = emulate_gp(ctxt, 0);
5179 goto done;
5180 }
5181
5182 /* Do instruction specific permission checks */
5183 if (ctxt->d & CheckPerm) {
5184 rc = ctxt->check_perm(ctxt);
5185 if (rc != X86EMUL_CONTINUE)
5186 goto done;
5187 }
5188
5189 if (unlikely(is_guest_mode) && (ctxt->d & Intercept)) {
5190 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5191 X86_ICPT_POST_EXCEPT);
5192 if (rc != X86EMUL_CONTINUE)
5193 goto done;
5194 }
5195
5196 if (ctxt->rep_prefix && (ctxt->d & String)) {
5197 /* All REP prefixes have the same first termination condition */
5198 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
5199 string_registers_quirk(ctxt);
5200 ctxt->eip = ctxt->_eip;
5201 ctxt->eflags &= ~X86_EFLAGS_RF;
5202 goto done;
5203 }
5204 }
5205 }
5206
5207 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
5208 rc = segmented_read(ctxt, ctxt->src.addr.mem,
5209 ctxt->src.valptr, ctxt->src.bytes);
5210 if (rc != X86EMUL_CONTINUE)
5211 goto done;
5212 ctxt->src.orig_val64 = ctxt->src.val64;
5213 }
5214
5215 if (ctxt->src2.type == OP_MEM) {
5216 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
5217 &ctxt->src2.val, ctxt->src2.bytes);
5218 if (rc != X86EMUL_CONTINUE)
5219 goto done;
5220 }
5221
5222 if ((ctxt->d & DstMask) == ImplicitOps)
5223 goto special_insn;
5224
5225
5226 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
5227 /* optimisation - avoid slow emulated read if Mov */
5228 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
5229 &ctxt->dst.val, ctxt->dst.bytes);
5230 if (rc != X86EMUL_CONTINUE) {
5231 if (!(ctxt->d & NoWrite) &&
5232 rc == X86EMUL_PROPAGATE_FAULT &&
5233 ctxt->exception.vector == PF_VECTOR)
5234 ctxt->exception.error_code |= PFERR_WRITE_MASK;
5235 goto done;
5236 }
5237 }
5238 /* Copy full 64-bit value for CMPXCHG8B. */
5239 ctxt->dst.orig_val64 = ctxt->dst.val64;
5240
5241special_insn:
5242
5243 if (unlikely(is_guest_mode) && (ctxt->d & Intercept)) {
5244 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5245 X86_ICPT_POST_MEMACCESS);
5246 if (rc != X86EMUL_CONTINUE)
5247 goto done;
5248 }
5249
5250 if (ctxt->rep_prefix && (ctxt->d & String))
5251 ctxt->eflags |= X86_EFLAGS_RF;
5252 else
5253 ctxt->eflags &= ~X86_EFLAGS_RF;
5254
5255 if (ctxt->execute) {
5256 if (ctxt->d & Fastop)
5257 rc = fastop(ctxt, ctxt->fop);
5258 else
5259 rc = ctxt->execute(ctxt);
5260 if (rc != X86EMUL_CONTINUE)
5261 goto done;
5262 goto writeback;
5263 }
5264
5265 if (ctxt->opcode_len == 2)
5266 goto twobyte_insn;
5267 else if (ctxt->opcode_len == 3)
5268 goto threebyte_insn;
5269
5270 switch (ctxt->b) {
5271 case 0x70 ... 0x7f: /* jcc (short) */
5272 if (test_cc(ctxt->b, ctxt->eflags))
5273 rc = jmp_rel(ctxt, ctxt->src.val);
5274 break;
5275 case 0x8d: /* lea r16/r32, m */
5276 ctxt->dst.val = ctxt->src.addr.mem.ea;
5277 break;
5278 case 0x90 ... 0x97: /* nop / xchg reg, rax */
5279 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
5280 ctxt->dst.type = OP_NONE;
5281 else
5282 rc = em_xchg(ctxt);
5283 break;
5284 case 0x98: /* cbw/cwde/cdqe */
5285 switch (ctxt->op_bytes) {
5286 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
5287 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
5288 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
5289 }
5290 break;
5291 case 0xcc: /* int3 */
5292 rc = emulate_int(ctxt, 3);
5293 break;
5294 case 0xcd: /* int n */
5295 rc = emulate_int(ctxt, ctxt->src.val);
5296 break;
5297 case 0xce: /* into */
5298 if (ctxt->eflags & X86_EFLAGS_OF)
5299 rc = emulate_int(ctxt, 4);
5300 break;
5301 case 0xe9: /* jmp rel */
5302 case 0xeb: /* jmp rel short */
5303 rc = jmp_rel(ctxt, ctxt->src.val);
5304 ctxt->dst.type = OP_NONE; /* Disable writeback. */
5305 break;
5306 case 0xf4: /* hlt */
5307 ctxt->ops->halt(ctxt);
5308 break;
5309 case 0xf5: /* cmc */
5310 /* complement carry flag from eflags reg */
5311 ctxt->eflags ^= X86_EFLAGS_CF;
5312 break;
5313 case 0xf8: /* clc */
5314 ctxt->eflags &= ~X86_EFLAGS_CF;
5315 break;
5316 case 0xf9: /* stc */
5317 ctxt->eflags |= X86_EFLAGS_CF;
5318 break;
5319 case 0xfc: /* cld */
5320 ctxt->eflags &= ~X86_EFLAGS_DF;
5321 break;
5322 case 0xfd: /* std */
5323 ctxt->eflags |= X86_EFLAGS_DF;
5324 break;
5325 default:
5326 goto cannot_emulate;
5327 }
5328
5329 if (rc != X86EMUL_CONTINUE)
5330 goto done;
5331
5332writeback:
5333 if (ctxt->d & SrcWrite) {
5334 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
5335 rc = writeback(ctxt, &ctxt->src);
5336 if (rc != X86EMUL_CONTINUE)
5337 goto done;
5338 }
5339 if (!(ctxt->d & NoWrite)) {
5340 rc = writeback(ctxt, &ctxt->dst);
5341 if (rc != X86EMUL_CONTINUE)
5342 goto done;
5343 }
5344
5345 /*
5346 * restore dst type in case the decoding will be reused
5347 * (happens for string instruction )
5348 */
5349 ctxt->dst.type = saved_dst_type;
5350
5351 if ((ctxt->d & SrcMask) == SrcSI)
5352 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
5353
5354 if ((ctxt->d & DstMask) == DstDI)
5355 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
5356
5357 if (ctxt->rep_prefix && (ctxt->d & String)) {
5358 unsigned int count;
5359 struct read_cache *r = &ctxt->io_read;
5360 if ((ctxt->d & SrcMask) == SrcSI)
5361 count = ctxt->src.count;
5362 else
5363 count = ctxt->dst.count;
5364 register_address_increment(ctxt, VCPU_REGS_RCX, -count);
5365
5366 if (!string_insn_completed(ctxt)) {
5367 /*
5368 * Re-enter guest when pio read ahead buffer is empty
5369 * or, if it is not used, after each 1024 iteration.
5370 */
5371 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
5372 (r->end == 0 || r->end != r->pos)) {
5373 /*
5374 * Reset read cache. Usually happens before
5375 * decode, but since instruction is restarted
5376 * we have to do it here.
5377 */
5378 ctxt->mem_read.end = 0;
5379 writeback_registers(ctxt);
5380 return EMULATION_RESTART;
5381 }
5382 goto done; /* skip rip writeback */
5383 }
5384 ctxt->eflags &= ~X86_EFLAGS_RF;
5385 }
5386
5387 ctxt->eip = ctxt->_eip;
5388 if (ctxt->mode != X86EMUL_MODE_PROT64)
5389 ctxt->eip = (u32)ctxt->_eip;
5390
5391done:
5392 if (rc == X86EMUL_PROPAGATE_FAULT) {
5393 if (KVM_EMULATOR_BUG_ON(ctxt->exception.vector > 0x1f, ctxt))
5394 return EMULATION_FAILED;
5395 ctxt->have_exception = true;
5396 }
5397 if (rc == X86EMUL_INTERCEPTED)
5398 return EMULATION_INTERCEPTED;
5399
5400 if (rc == X86EMUL_CONTINUE)
5401 writeback_registers(ctxt);
5402
5403 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
5404
5405twobyte_insn:
5406 switch (ctxt->b) {
5407 case 0x09: /* wbinvd */
5408 (ctxt->ops->wbinvd)(ctxt);
5409 break;
5410 case 0x08: /* invd */
5411 case 0x0d: /* GrpP (prefetch) */
5412 case 0x18: /* Grp16 (prefetch/nop) */
5413 case 0x1f: /* nop */
5414 break;
5415 case 0x20: /* mov cr, reg */
5416 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
5417 break;
5418 case 0x21: /* mov from dr to reg */
5419 ctxt->dst.val = ops->get_dr(ctxt, ctxt->modrm_reg);
5420 break;
5421 case 0x40 ... 0x4f: /* cmov */
5422 if (test_cc(ctxt->b, ctxt->eflags))
5423 ctxt->dst.val = ctxt->src.val;
5424 else if (ctxt->op_bytes != 4)
5425 ctxt->dst.type = OP_NONE; /* no writeback */
5426 break;
5427 case 0x80 ... 0x8f: /* jnz rel, etc*/
5428 if (test_cc(ctxt->b, ctxt->eflags))
5429 rc = jmp_rel(ctxt, ctxt->src.val);
5430 break;
5431 case 0x90 ... 0x9f: /* setcc r/m8 */
5432 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
5433 break;
5434 case 0xb6 ... 0xb7: /* movzx */
5435 ctxt->dst.bytes = ctxt->op_bytes;
5436 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
5437 : (u16) ctxt->src.val;
5438 break;
5439 case 0xbe ... 0xbf: /* movsx */
5440 ctxt->dst.bytes = ctxt->op_bytes;
5441 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
5442 (s16) ctxt->src.val;
5443 break;
5444 default:
5445 goto cannot_emulate;
5446 }
5447
5448threebyte_insn:
5449
5450 if (rc != X86EMUL_CONTINUE)
5451 goto done;
5452
5453 goto writeback;
5454
5455cannot_emulate:
5456 return EMULATION_FAILED;
5457}
5458
5459void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5460{
5461 invalidate_registers(ctxt);
5462}
5463
5464void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5465{
5466 writeback_registers(ctxt);
5467}
5468
5469bool emulator_can_use_gpa(struct x86_emulate_ctxt *ctxt)
5470{
5471 if (ctxt->rep_prefix && (ctxt->d & String))
5472 return false;
5473
5474 if (ctxt->d & TwoMemOp)
5475 return false;
5476
5477 return true;
5478}
1/******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23#include <linux/kvm_host.h>
24#include "kvm_cache_regs.h"
25#include <asm/kvm_emulate.h>
26#include <linux/stringify.h>
27#include <asm/debugreg.h>
28
29#include "x86.h"
30#include "tss.h"
31
32/*
33 * Operand types
34 */
35#define OpNone 0ull
36#define OpImplicit 1ull /* No generic decode */
37#define OpReg 2ull /* Register */
38#define OpMem 3ull /* Memory */
39#define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40#define OpDI 5ull /* ES:DI/EDI/RDI */
41#define OpMem64 6ull /* Memory, 64-bit */
42#define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43#define OpDX 8ull /* DX register */
44#define OpCL 9ull /* CL register (for shifts) */
45#define OpImmByte 10ull /* 8-bit sign extended immediate */
46#define OpOne 11ull /* Implied 1 */
47#define OpImm 12ull /* Sign extended up to 32-bit immediate */
48#define OpMem16 13ull /* Memory operand (16-bit). */
49#define OpMem32 14ull /* Memory operand (32-bit). */
50#define OpImmU 15ull /* Immediate operand, zero extended */
51#define OpSI 16ull /* SI/ESI/RSI */
52#define OpImmFAddr 17ull /* Immediate far address */
53#define OpMemFAddr 18ull /* Far address in memory */
54#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
55#define OpES 20ull /* ES */
56#define OpCS 21ull /* CS */
57#define OpSS 22ull /* SS */
58#define OpDS 23ull /* DS */
59#define OpFS 24ull /* FS */
60#define OpGS 25ull /* GS */
61#define OpMem8 26ull /* 8-bit zero extended memory operand */
62#define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
63#define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
64#define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65#define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
66
67#define OpBits 5 /* Width of operand field */
68#define OpMask ((1ull << OpBits) - 1)
69
70/*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79/* Operand sizes: 8-bit operands or specified/overridden size. */
80#define ByteOp (1<<0) /* 8-bit operands. */
81/* Destination operand type. */
82#define DstShift 1
83#define ImplicitOps (OpImplicit << DstShift)
84#define DstReg (OpReg << DstShift)
85#define DstMem (OpMem << DstShift)
86#define DstAcc (OpAcc << DstShift)
87#define DstDI (OpDI << DstShift)
88#define DstMem64 (OpMem64 << DstShift)
89#define DstMem16 (OpMem16 << DstShift)
90#define DstImmUByte (OpImmUByte << DstShift)
91#define DstDX (OpDX << DstShift)
92#define DstAccLo (OpAccLo << DstShift)
93#define DstMask (OpMask << DstShift)
94/* Source operand type. */
95#define SrcShift 6
96#define SrcNone (OpNone << SrcShift)
97#define SrcReg (OpReg << SrcShift)
98#define SrcMem (OpMem << SrcShift)
99#define SrcMem16 (OpMem16 << SrcShift)
100#define SrcMem32 (OpMem32 << SrcShift)
101#define SrcImm (OpImm << SrcShift)
102#define SrcImmByte (OpImmByte << SrcShift)
103#define SrcOne (OpOne << SrcShift)
104#define SrcImmUByte (OpImmUByte << SrcShift)
105#define SrcImmU (OpImmU << SrcShift)
106#define SrcSI (OpSI << SrcShift)
107#define SrcXLat (OpXLat << SrcShift)
108#define SrcImmFAddr (OpImmFAddr << SrcShift)
109#define SrcMemFAddr (OpMemFAddr << SrcShift)
110#define SrcAcc (OpAcc << SrcShift)
111#define SrcImmU16 (OpImmU16 << SrcShift)
112#define SrcImm64 (OpImm64 << SrcShift)
113#define SrcDX (OpDX << SrcShift)
114#define SrcMem8 (OpMem8 << SrcShift)
115#define SrcAccHi (OpAccHi << SrcShift)
116#define SrcMask (OpMask << SrcShift)
117#define BitOp (1<<11)
118#define MemAbs (1<<12) /* Memory operand is absolute displacement */
119#define String (1<<13) /* String instruction (rep capable) */
120#define Stack (1<<14) /* Stack instruction (push/pop) */
121#define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
122#define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
123#define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
124#define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
125#define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
126#define Escape (5<<15) /* Escape to coprocessor instruction */
127#define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */
128#define ModeDual (7<<15) /* Different instruction for 32/64 bit */
129#define Sse (1<<18) /* SSE Vector instruction */
130/* Generic ModRM decode. */
131#define ModRM (1<<19)
132/* Destination is only written; never read. */
133#define Mov (1<<20)
134/* Misc flags */
135#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
136#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
137#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
138#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
139#define Undefined (1<<25) /* No Such Instruction */
140#define Lock (1<<26) /* lock prefix is allowed for the instruction */
141#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
142#define No64 (1<<28)
143#define PageTable (1 << 29) /* instruction used to write page table */
144#define NotImpl (1 << 30) /* instruction is not implemented */
145/* Source 2 operand type */
146#define Src2Shift (31)
147#define Src2None (OpNone << Src2Shift)
148#define Src2Mem (OpMem << Src2Shift)
149#define Src2CL (OpCL << Src2Shift)
150#define Src2ImmByte (OpImmByte << Src2Shift)
151#define Src2One (OpOne << Src2Shift)
152#define Src2Imm (OpImm << Src2Shift)
153#define Src2ES (OpES << Src2Shift)
154#define Src2CS (OpCS << Src2Shift)
155#define Src2SS (OpSS << Src2Shift)
156#define Src2DS (OpDS << Src2Shift)
157#define Src2FS (OpFS << Src2Shift)
158#define Src2GS (OpGS << Src2Shift)
159#define Src2Mask (OpMask << Src2Shift)
160#define Mmx ((u64)1 << 40) /* MMX Vector instruction */
161#define AlignMask ((u64)7 << 41)
162#define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
163#define Unaligned ((u64)2 << 41) /* Explicitly unaligned (e.g. MOVDQU) */
164#define Avx ((u64)3 << 41) /* Advanced Vector Extensions */
165#define Aligned16 ((u64)4 << 41) /* Aligned to 16 byte boundary (e.g. FXSAVE) */
166#define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
167#define NoWrite ((u64)1 << 45) /* No writeback */
168#define SrcWrite ((u64)1 << 46) /* Write back src operand */
169#define NoMod ((u64)1 << 47) /* Mod field is ignored */
170#define Intercept ((u64)1 << 48) /* Has valid intercept field */
171#define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
172#define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
173#define NearBranch ((u64)1 << 52) /* Near branches */
174#define No16 ((u64)1 << 53) /* No 16 bit operand */
175#define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */
176
177#define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
178
179#define X2(x...) x, x
180#define X3(x...) X2(x), x
181#define X4(x...) X2(x), X2(x)
182#define X5(x...) X4(x), x
183#define X6(x...) X4(x), X2(x)
184#define X7(x...) X4(x), X3(x)
185#define X8(x...) X4(x), X4(x)
186#define X16(x...) X8(x), X8(x)
187
188#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
189#define FASTOP_SIZE 8
190
191/*
192 * fastop functions have a special calling convention:
193 *
194 * dst: rax (in/out)
195 * src: rdx (in/out)
196 * src2: rcx (in)
197 * flags: rflags (in/out)
198 * ex: rsi (in:fastop pointer, out:zero if exception)
199 *
200 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
201 * different operand sizes can be reached by calculation, rather than a jump
202 * table (which would be bigger than the code).
203 *
204 * fastop functions are declared as taking a never-defined fastop parameter,
205 * so they can't be called from C directly.
206 */
207
208struct fastop;
209
210struct opcode {
211 u64 flags : 56;
212 u64 intercept : 8;
213 union {
214 int (*execute)(struct x86_emulate_ctxt *ctxt);
215 const struct opcode *group;
216 const struct group_dual *gdual;
217 const struct gprefix *gprefix;
218 const struct escape *esc;
219 const struct instr_dual *idual;
220 const struct mode_dual *mdual;
221 void (*fastop)(struct fastop *fake);
222 } u;
223 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
224};
225
226struct group_dual {
227 struct opcode mod012[8];
228 struct opcode mod3[8];
229};
230
231struct gprefix {
232 struct opcode pfx_no;
233 struct opcode pfx_66;
234 struct opcode pfx_f2;
235 struct opcode pfx_f3;
236};
237
238struct escape {
239 struct opcode op[8];
240 struct opcode high[64];
241};
242
243struct instr_dual {
244 struct opcode mod012;
245 struct opcode mod3;
246};
247
248struct mode_dual {
249 struct opcode mode32;
250 struct opcode mode64;
251};
252
253#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
254
255enum x86_transfer_type {
256 X86_TRANSFER_NONE,
257 X86_TRANSFER_CALL_JMP,
258 X86_TRANSFER_RET,
259 X86_TRANSFER_TASK_SWITCH,
260};
261
262static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
263{
264 if (!(ctxt->regs_valid & (1 << nr))) {
265 ctxt->regs_valid |= 1 << nr;
266 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
267 }
268 return ctxt->_regs[nr];
269}
270
271static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
272{
273 ctxt->regs_valid |= 1 << nr;
274 ctxt->regs_dirty |= 1 << nr;
275 return &ctxt->_regs[nr];
276}
277
278static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
279{
280 reg_read(ctxt, nr);
281 return reg_write(ctxt, nr);
282}
283
284static void writeback_registers(struct x86_emulate_ctxt *ctxt)
285{
286 unsigned reg;
287
288 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
289 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
290}
291
292static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
293{
294 ctxt->regs_dirty = 0;
295 ctxt->regs_valid = 0;
296}
297
298/*
299 * These EFLAGS bits are restored from saved value during emulation, and
300 * any changes are written back to the saved value after emulation.
301 */
302#define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\
303 X86_EFLAGS_PF|X86_EFLAGS_CF)
304
305#ifdef CONFIG_X86_64
306#define ON64(x) x
307#else
308#define ON64(x)
309#endif
310
311static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
312
313#define FOP_FUNC(name) \
314 ".align " __stringify(FASTOP_SIZE) " \n\t" \
315 ".type " name ", @function \n\t" \
316 name ":\n\t"
317
318#define FOP_RET "ret \n\t"
319
320#define FOP_START(op) \
321 extern void em_##op(struct fastop *fake); \
322 asm(".pushsection .text, \"ax\" \n\t" \
323 ".global em_" #op " \n\t" \
324 FOP_FUNC("em_" #op)
325
326#define FOP_END \
327 ".popsection")
328
329#define FOPNOP() \
330 FOP_FUNC(__stringify(__UNIQUE_ID(nop))) \
331 FOP_RET
332
333#define FOP1E(op, dst) \
334 FOP_FUNC(#op "_" #dst) \
335 "10: " #op " %" #dst " \n\t" FOP_RET
336
337#define FOP1EEX(op, dst) \
338 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
339
340#define FASTOP1(op) \
341 FOP_START(op) \
342 FOP1E(op##b, al) \
343 FOP1E(op##w, ax) \
344 FOP1E(op##l, eax) \
345 ON64(FOP1E(op##q, rax)) \
346 FOP_END
347
348/* 1-operand, using src2 (for MUL/DIV r/m) */
349#define FASTOP1SRC2(op, name) \
350 FOP_START(name) \
351 FOP1E(op, cl) \
352 FOP1E(op, cx) \
353 FOP1E(op, ecx) \
354 ON64(FOP1E(op, rcx)) \
355 FOP_END
356
357/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
358#define FASTOP1SRC2EX(op, name) \
359 FOP_START(name) \
360 FOP1EEX(op, cl) \
361 FOP1EEX(op, cx) \
362 FOP1EEX(op, ecx) \
363 ON64(FOP1EEX(op, rcx)) \
364 FOP_END
365
366#define FOP2E(op, dst, src) \
367 FOP_FUNC(#op "_" #dst "_" #src) \
368 #op " %" #src ", %" #dst " \n\t" FOP_RET
369
370#define FASTOP2(op) \
371 FOP_START(op) \
372 FOP2E(op##b, al, dl) \
373 FOP2E(op##w, ax, dx) \
374 FOP2E(op##l, eax, edx) \
375 ON64(FOP2E(op##q, rax, rdx)) \
376 FOP_END
377
378/* 2 operand, word only */
379#define FASTOP2W(op) \
380 FOP_START(op) \
381 FOPNOP() \
382 FOP2E(op##w, ax, dx) \
383 FOP2E(op##l, eax, edx) \
384 ON64(FOP2E(op##q, rax, rdx)) \
385 FOP_END
386
387/* 2 operand, src is CL */
388#define FASTOP2CL(op) \
389 FOP_START(op) \
390 FOP2E(op##b, al, cl) \
391 FOP2E(op##w, ax, cl) \
392 FOP2E(op##l, eax, cl) \
393 ON64(FOP2E(op##q, rax, cl)) \
394 FOP_END
395
396/* 2 operand, src and dest are reversed */
397#define FASTOP2R(op, name) \
398 FOP_START(name) \
399 FOP2E(op##b, dl, al) \
400 FOP2E(op##w, dx, ax) \
401 FOP2E(op##l, edx, eax) \
402 ON64(FOP2E(op##q, rdx, rax)) \
403 FOP_END
404
405#define FOP3E(op, dst, src, src2) \
406 FOP_FUNC(#op "_" #dst "_" #src "_" #src2) \
407 #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
408
409/* 3-operand, word-only, src2=cl */
410#define FASTOP3WCL(op) \
411 FOP_START(op) \
412 FOPNOP() \
413 FOP3E(op##w, ax, dx, cl) \
414 FOP3E(op##l, eax, edx, cl) \
415 ON64(FOP3E(op##q, rax, rdx, cl)) \
416 FOP_END
417
418/* Special case for SETcc - 1 instruction per cc */
419#define FOP_SETCC(op) \
420 ".align 4 \n\t" \
421 ".type " #op ", @function \n\t" \
422 #op ": \n\t" \
423 #op " %al \n\t" \
424 FOP_RET
425
426asm(".global kvm_fastop_exception \n"
427 "kvm_fastop_exception: xor %esi, %esi; ret");
428
429FOP_START(setcc)
430FOP_SETCC(seto)
431FOP_SETCC(setno)
432FOP_SETCC(setc)
433FOP_SETCC(setnc)
434FOP_SETCC(setz)
435FOP_SETCC(setnz)
436FOP_SETCC(setbe)
437FOP_SETCC(setnbe)
438FOP_SETCC(sets)
439FOP_SETCC(setns)
440FOP_SETCC(setp)
441FOP_SETCC(setnp)
442FOP_SETCC(setl)
443FOP_SETCC(setnl)
444FOP_SETCC(setle)
445FOP_SETCC(setnle)
446FOP_END;
447
448FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
449FOP_END;
450
451/*
452 * XXX: inoutclob user must know where the argument is being expanded.
453 * Relying on CC_HAVE_ASM_GOTO would allow us to remove _fault.
454 */
455#define asm_safe(insn, inoutclob...) \
456({ \
457 int _fault = 0; \
458 \
459 asm volatile("1:" insn "\n" \
460 "2:\n" \
461 ".pushsection .fixup, \"ax\"\n" \
462 "3: movl $1, %[_fault]\n" \
463 " jmp 2b\n" \
464 ".popsection\n" \
465 _ASM_EXTABLE(1b, 3b) \
466 : [_fault] "+qm"(_fault) inoutclob ); \
467 \
468 _fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \
469})
470
471static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
472 enum x86_intercept intercept,
473 enum x86_intercept_stage stage)
474{
475 struct x86_instruction_info info = {
476 .intercept = intercept,
477 .rep_prefix = ctxt->rep_prefix,
478 .modrm_mod = ctxt->modrm_mod,
479 .modrm_reg = ctxt->modrm_reg,
480 .modrm_rm = ctxt->modrm_rm,
481 .src_val = ctxt->src.val64,
482 .dst_val = ctxt->dst.val64,
483 .src_bytes = ctxt->src.bytes,
484 .dst_bytes = ctxt->dst.bytes,
485 .ad_bytes = ctxt->ad_bytes,
486 .next_rip = ctxt->eip,
487 };
488
489 return ctxt->ops->intercept(ctxt, &info, stage);
490}
491
492static void assign_masked(ulong *dest, ulong src, ulong mask)
493{
494 *dest = (*dest & ~mask) | (src & mask);
495}
496
497static void assign_register(unsigned long *reg, u64 val, int bytes)
498{
499 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
500 switch (bytes) {
501 case 1:
502 *(u8 *)reg = (u8)val;
503 break;
504 case 2:
505 *(u16 *)reg = (u16)val;
506 break;
507 case 4:
508 *reg = (u32)val;
509 break; /* 64b: zero-extend */
510 case 8:
511 *reg = val;
512 break;
513 }
514}
515
516static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
517{
518 return (1UL << (ctxt->ad_bytes << 3)) - 1;
519}
520
521static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
522{
523 u16 sel;
524 struct desc_struct ss;
525
526 if (ctxt->mode == X86EMUL_MODE_PROT64)
527 return ~0UL;
528 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
529 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
530}
531
532static int stack_size(struct x86_emulate_ctxt *ctxt)
533{
534 return (__fls(stack_mask(ctxt)) + 1) >> 3;
535}
536
537/* Access/update address held in a register, based on addressing mode. */
538static inline unsigned long
539address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
540{
541 if (ctxt->ad_bytes == sizeof(unsigned long))
542 return reg;
543 else
544 return reg & ad_mask(ctxt);
545}
546
547static inline unsigned long
548register_address(struct x86_emulate_ctxt *ctxt, int reg)
549{
550 return address_mask(ctxt, reg_read(ctxt, reg));
551}
552
553static void masked_increment(ulong *reg, ulong mask, int inc)
554{
555 assign_masked(reg, *reg + inc, mask);
556}
557
558static inline void
559register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
560{
561 ulong *preg = reg_rmw(ctxt, reg);
562
563 assign_register(preg, *preg + inc, ctxt->ad_bytes);
564}
565
566static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
567{
568 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
569}
570
571static u32 desc_limit_scaled(struct desc_struct *desc)
572{
573 u32 limit = get_desc_limit(desc);
574
575 return desc->g ? (limit << 12) | 0xfff : limit;
576}
577
578static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
579{
580 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
581 return 0;
582
583 return ctxt->ops->get_cached_segment_base(ctxt, seg);
584}
585
586static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
587 u32 error, bool valid)
588{
589 WARN_ON(vec > 0x1f);
590 ctxt->exception.vector = vec;
591 ctxt->exception.error_code = error;
592 ctxt->exception.error_code_valid = valid;
593 return X86EMUL_PROPAGATE_FAULT;
594}
595
596static int emulate_db(struct x86_emulate_ctxt *ctxt)
597{
598 return emulate_exception(ctxt, DB_VECTOR, 0, false);
599}
600
601static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
602{
603 return emulate_exception(ctxt, GP_VECTOR, err, true);
604}
605
606static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
607{
608 return emulate_exception(ctxt, SS_VECTOR, err, true);
609}
610
611static int emulate_ud(struct x86_emulate_ctxt *ctxt)
612{
613 return emulate_exception(ctxt, UD_VECTOR, 0, false);
614}
615
616static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
617{
618 return emulate_exception(ctxt, TS_VECTOR, err, true);
619}
620
621static int emulate_de(struct x86_emulate_ctxt *ctxt)
622{
623 return emulate_exception(ctxt, DE_VECTOR, 0, false);
624}
625
626static int emulate_nm(struct x86_emulate_ctxt *ctxt)
627{
628 return emulate_exception(ctxt, NM_VECTOR, 0, false);
629}
630
631static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
632{
633 u16 selector;
634 struct desc_struct desc;
635
636 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
637 return selector;
638}
639
640static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
641 unsigned seg)
642{
643 u16 dummy;
644 u32 base3;
645 struct desc_struct desc;
646
647 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
648 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
649}
650
651/*
652 * x86 defines three classes of vector instructions: explicitly
653 * aligned, explicitly unaligned, and the rest, which change behaviour
654 * depending on whether they're AVX encoded or not.
655 *
656 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
657 * subject to the same check. FXSAVE and FXRSTOR are checked here too as their
658 * 512 bytes of data must be aligned to a 16 byte boundary.
659 */
660static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size)
661{
662 u64 alignment = ctxt->d & AlignMask;
663
664 if (likely(size < 16))
665 return 1;
666
667 switch (alignment) {
668 case Unaligned:
669 case Avx:
670 return 1;
671 case Aligned16:
672 return 16;
673 case Aligned:
674 default:
675 return size;
676 }
677}
678
679static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
680 struct segmented_address addr,
681 unsigned *max_size, unsigned size,
682 bool write, bool fetch,
683 enum x86emul_mode mode, ulong *linear)
684{
685 struct desc_struct desc;
686 bool usable;
687 ulong la;
688 u32 lim;
689 u16 sel;
690
691 la = seg_base(ctxt, addr.seg) + addr.ea;
692 *max_size = 0;
693 switch (mode) {
694 case X86EMUL_MODE_PROT64:
695 *linear = la;
696 if (is_noncanonical_address(la))
697 goto bad;
698
699 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
700 if (size > *max_size)
701 goto bad;
702 break;
703 default:
704 *linear = la = (u32)la;
705 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
706 addr.seg);
707 if (!usable)
708 goto bad;
709 /* code segment in protected mode or read-only data segment */
710 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
711 || !(desc.type & 2)) && write)
712 goto bad;
713 /* unreadable code segment */
714 if (!fetch && (desc.type & 8) && !(desc.type & 2))
715 goto bad;
716 lim = desc_limit_scaled(&desc);
717 if (!(desc.type & 8) && (desc.type & 4)) {
718 /* expand-down segment */
719 if (addr.ea <= lim)
720 goto bad;
721 lim = desc.d ? 0xffffffff : 0xffff;
722 }
723 if (addr.ea > lim)
724 goto bad;
725 if (lim == 0xffffffff)
726 *max_size = ~0u;
727 else {
728 *max_size = (u64)lim + 1 - addr.ea;
729 if (size > *max_size)
730 goto bad;
731 }
732 break;
733 }
734 if (la & (insn_alignment(ctxt, size) - 1))
735 return emulate_gp(ctxt, 0);
736 return X86EMUL_CONTINUE;
737bad:
738 if (addr.seg == VCPU_SREG_SS)
739 return emulate_ss(ctxt, 0);
740 else
741 return emulate_gp(ctxt, 0);
742}
743
744static int linearize(struct x86_emulate_ctxt *ctxt,
745 struct segmented_address addr,
746 unsigned size, bool write,
747 ulong *linear)
748{
749 unsigned max_size;
750 return __linearize(ctxt, addr, &max_size, size, write, false,
751 ctxt->mode, linear);
752}
753
754static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
755 enum x86emul_mode mode)
756{
757 ulong linear;
758 int rc;
759 unsigned max_size;
760 struct segmented_address addr = { .seg = VCPU_SREG_CS,
761 .ea = dst };
762
763 if (ctxt->op_bytes != sizeof(unsigned long))
764 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
765 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
766 if (rc == X86EMUL_CONTINUE)
767 ctxt->_eip = addr.ea;
768 return rc;
769}
770
771static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
772{
773 return assign_eip(ctxt, dst, ctxt->mode);
774}
775
776static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
777 const struct desc_struct *cs_desc)
778{
779 enum x86emul_mode mode = ctxt->mode;
780 int rc;
781
782#ifdef CONFIG_X86_64
783 if (ctxt->mode >= X86EMUL_MODE_PROT16) {
784 if (cs_desc->l) {
785 u64 efer = 0;
786
787 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
788 if (efer & EFER_LMA)
789 mode = X86EMUL_MODE_PROT64;
790 } else
791 mode = X86EMUL_MODE_PROT32; /* temporary value */
792 }
793#endif
794 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
795 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
796 rc = assign_eip(ctxt, dst, mode);
797 if (rc == X86EMUL_CONTINUE)
798 ctxt->mode = mode;
799 return rc;
800}
801
802static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
803{
804 return assign_eip_near(ctxt, ctxt->_eip + rel);
805}
806
807static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
808 struct segmented_address addr,
809 void *data,
810 unsigned size)
811{
812 int rc;
813 ulong linear;
814
815 rc = linearize(ctxt, addr, size, false, &linear);
816 if (rc != X86EMUL_CONTINUE)
817 return rc;
818 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
819}
820
821static int segmented_write_std(struct x86_emulate_ctxt *ctxt,
822 struct segmented_address addr,
823 void *data,
824 unsigned int size)
825{
826 int rc;
827 ulong linear;
828
829 rc = linearize(ctxt, addr, size, true, &linear);
830 if (rc != X86EMUL_CONTINUE)
831 return rc;
832 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception);
833}
834
835/*
836 * Prefetch the remaining bytes of the instruction without crossing page
837 * boundary if they are not in fetch_cache yet.
838 */
839static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
840{
841 int rc;
842 unsigned size, max_size;
843 unsigned long linear;
844 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
845 struct segmented_address addr = { .seg = VCPU_SREG_CS,
846 .ea = ctxt->eip + cur_size };
847
848 /*
849 * We do not know exactly how many bytes will be needed, and
850 * __linearize is expensive, so fetch as much as possible. We
851 * just have to avoid going beyond the 15 byte limit, the end
852 * of the segment, or the end of the page.
853 *
854 * __linearize is called with size 0 so that it does not do any
855 * boundary check itself. Instead, we use max_size to check
856 * against op_size.
857 */
858 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
859 &linear);
860 if (unlikely(rc != X86EMUL_CONTINUE))
861 return rc;
862
863 size = min_t(unsigned, 15UL ^ cur_size, max_size);
864 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
865
866 /*
867 * One instruction can only straddle two pages,
868 * and one has been loaded at the beginning of
869 * x86_decode_insn. So, if not enough bytes
870 * still, we must have hit the 15-byte boundary.
871 */
872 if (unlikely(size < op_size))
873 return emulate_gp(ctxt, 0);
874
875 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
876 size, &ctxt->exception);
877 if (unlikely(rc != X86EMUL_CONTINUE))
878 return rc;
879 ctxt->fetch.end += size;
880 return X86EMUL_CONTINUE;
881}
882
883static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
884 unsigned size)
885{
886 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
887
888 if (unlikely(done_size < size))
889 return __do_insn_fetch_bytes(ctxt, size - done_size);
890 else
891 return X86EMUL_CONTINUE;
892}
893
894/* Fetch next part of the instruction being emulated. */
895#define insn_fetch(_type, _ctxt) \
896({ _type _x; \
897 \
898 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
899 if (rc != X86EMUL_CONTINUE) \
900 goto done; \
901 ctxt->_eip += sizeof(_type); \
902 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
903 ctxt->fetch.ptr += sizeof(_type); \
904 _x; \
905})
906
907#define insn_fetch_arr(_arr, _size, _ctxt) \
908({ \
909 rc = do_insn_fetch_bytes(_ctxt, _size); \
910 if (rc != X86EMUL_CONTINUE) \
911 goto done; \
912 ctxt->_eip += (_size); \
913 memcpy(_arr, ctxt->fetch.ptr, _size); \
914 ctxt->fetch.ptr += (_size); \
915})
916
917/*
918 * Given the 'reg' portion of a ModRM byte, and a register block, return a
919 * pointer into the block that addresses the relevant register.
920 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
921 */
922static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
923 int byteop)
924{
925 void *p;
926 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
927
928 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
929 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
930 else
931 p = reg_rmw(ctxt, modrm_reg);
932 return p;
933}
934
935static int read_descriptor(struct x86_emulate_ctxt *ctxt,
936 struct segmented_address addr,
937 u16 *size, unsigned long *address, int op_bytes)
938{
939 int rc;
940
941 if (op_bytes == 2)
942 op_bytes = 3;
943 *address = 0;
944 rc = segmented_read_std(ctxt, addr, size, 2);
945 if (rc != X86EMUL_CONTINUE)
946 return rc;
947 addr.ea += 2;
948 rc = segmented_read_std(ctxt, addr, address, op_bytes);
949 return rc;
950}
951
952FASTOP2(add);
953FASTOP2(or);
954FASTOP2(adc);
955FASTOP2(sbb);
956FASTOP2(and);
957FASTOP2(sub);
958FASTOP2(xor);
959FASTOP2(cmp);
960FASTOP2(test);
961
962FASTOP1SRC2(mul, mul_ex);
963FASTOP1SRC2(imul, imul_ex);
964FASTOP1SRC2EX(div, div_ex);
965FASTOP1SRC2EX(idiv, idiv_ex);
966
967FASTOP3WCL(shld);
968FASTOP3WCL(shrd);
969
970FASTOP2W(imul);
971
972FASTOP1(not);
973FASTOP1(neg);
974FASTOP1(inc);
975FASTOP1(dec);
976
977FASTOP2CL(rol);
978FASTOP2CL(ror);
979FASTOP2CL(rcl);
980FASTOP2CL(rcr);
981FASTOP2CL(shl);
982FASTOP2CL(shr);
983FASTOP2CL(sar);
984
985FASTOP2W(bsf);
986FASTOP2W(bsr);
987FASTOP2W(bt);
988FASTOP2W(bts);
989FASTOP2W(btr);
990FASTOP2W(btc);
991
992FASTOP2(xadd);
993
994FASTOP2R(cmp, cmp_r);
995
996static int em_bsf_c(struct x86_emulate_ctxt *ctxt)
997{
998 /* If src is zero, do not writeback, but update flags */
999 if (ctxt->src.val == 0)
1000 ctxt->dst.type = OP_NONE;
1001 return fastop(ctxt, em_bsf);
1002}
1003
1004static int em_bsr_c(struct x86_emulate_ctxt *ctxt)
1005{
1006 /* If src is zero, do not writeback, but update flags */
1007 if (ctxt->src.val == 0)
1008 ctxt->dst.type = OP_NONE;
1009 return fastop(ctxt, em_bsr);
1010}
1011
1012static __always_inline u8 test_cc(unsigned int condition, unsigned long flags)
1013{
1014 u8 rc;
1015 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
1016
1017 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
1018 asm("push %[flags]; popf; call *%[fastop]"
1019 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
1020 return rc;
1021}
1022
1023static void fetch_register_operand(struct operand *op)
1024{
1025 switch (op->bytes) {
1026 case 1:
1027 op->val = *(u8 *)op->addr.reg;
1028 break;
1029 case 2:
1030 op->val = *(u16 *)op->addr.reg;
1031 break;
1032 case 4:
1033 op->val = *(u32 *)op->addr.reg;
1034 break;
1035 case 8:
1036 op->val = *(u64 *)op->addr.reg;
1037 break;
1038 }
1039}
1040
1041static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
1042{
1043 ctxt->ops->get_fpu(ctxt);
1044 switch (reg) {
1045 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
1046 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
1047 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
1048 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
1049 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
1050 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
1051 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
1052 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1053#ifdef CONFIG_X86_64
1054 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
1055 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
1056 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
1057 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
1058 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
1059 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
1060 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
1061 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1062#endif
1063 default: BUG();
1064 }
1065 ctxt->ops->put_fpu(ctxt);
1066}
1067
1068static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1069 int reg)
1070{
1071 ctxt->ops->get_fpu(ctxt);
1072 switch (reg) {
1073 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1074 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1075 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1076 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1077 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1078 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1079 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1080 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1081#ifdef CONFIG_X86_64
1082 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1083 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1084 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1085 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1086 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1087 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1088 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1089 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1090#endif
1091 default: BUG();
1092 }
1093 ctxt->ops->put_fpu(ctxt);
1094}
1095
1096static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1097{
1098 ctxt->ops->get_fpu(ctxt);
1099 switch (reg) {
1100 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1101 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1102 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1103 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1104 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1105 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1106 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1107 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1108 default: BUG();
1109 }
1110 ctxt->ops->put_fpu(ctxt);
1111}
1112
1113static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1114{
1115 ctxt->ops->get_fpu(ctxt);
1116 switch (reg) {
1117 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1118 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1119 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1120 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1121 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1122 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1123 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1124 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1125 default: BUG();
1126 }
1127 ctxt->ops->put_fpu(ctxt);
1128}
1129
1130static int em_fninit(struct x86_emulate_ctxt *ctxt)
1131{
1132 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1133 return emulate_nm(ctxt);
1134
1135 ctxt->ops->get_fpu(ctxt);
1136 asm volatile("fninit");
1137 ctxt->ops->put_fpu(ctxt);
1138 return X86EMUL_CONTINUE;
1139}
1140
1141static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1142{
1143 u16 fcw;
1144
1145 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1146 return emulate_nm(ctxt);
1147
1148 ctxt->ops->get_fpu(ctxt);
1149 asm volatile("fnstcw %0": "+m"(fcw));
1150 ctxt->ops->put_fpu(ctxt);
1151
1152 ctxt->dst.val = fcw;
1153
1154 return X86EMUL_CONTINUE;
1155}
1156
1157static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1158{
1159 u16 fsw;
1160
1161 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1162 return emulate_nm(ctxt);
1163
1164 ctxt->ops->get_fpu(ctxt);
1165 asm volatile("fnstsw %0": "+m"(fsw));
1166 ctxt->ops->put_fpu(ctxt);
1167
1168 ctxt->dst.val = fsw;
1169
1170 return X86EMUL_CONTINUE;
1171}
1172
1173static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
1174 struct operand *op)
1175{
1176 unsigned reg = ctxt->modrm_reg;
1177
1178 if (!(ctxt->d & ModRM))
1179 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1180
1181 if (ctxt->d & Sse) {
1182 op->type = OP_XMM;
1183 op->bytes = 16;
1184 op->addr.xmm = reg;
1185 read_sse_reg(ctxt, &op->vec_val, reg);
1186 return;
1187 }
1188 if (ctxt->d & Mmx) {
1189 reg &= 7;
1190 op->type = OP_MM;
1191 op->bytes = 8;
1192 op->addr.mm = reg;
1193 return;
1194 }
1195
1196 op->type = OP_REG;
1197 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1198 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1199
1200 fetch_register_operand(op);
1201 op->orig_val = op->val;
1202}
1203
1204static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1205{
1206 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1207 ctxt->modrm_seg = VCPU_SREG_SS;
1208}
1209
1210static int decode_modrm(struct x86_emulate_ctxt *ctxt,
1211 struct operand *op)
1212{
1213 u8 sib;
1214 int index_reg, base_reg, scale;
1215 int rc = X86EMUL_CONTINUE;
1216 ulong modrm_ea = 0;
1217
1218 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1219 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1220 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1221
1222 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
1223 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1224 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
1225 ctxt->modrm_seg = VCPU_SREG_DS;
1226
1227 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
1228 op->type = OP_REG;
1229 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1230 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
1231 ctxt->d & ByteOp);
1232 if (ctxt->d & Sse) {
1233 op->type = OP_XMM;
1234 op->bytes = 16;
1235 op->addr.xmm = ctxt->modrm_rm;
1236 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1237 return rc;
1238 }
1239 if (ctxt->d & Mmx) {
1240 op->type = OP_MM;
1241 op->bytes = 8;
1242 op->addr.mm = ctxt->modrm_rm & 7;
1243 return rc;
1244 }
1245 fetch_register_operand(op);
1246 return rc;
1247 }
1248
1249 op->type = OP_MEM;
1250
1251 if (ctxt->ad_bytes == 2) {
1252 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1253 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1254 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1255 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1256
1257 /* 16-bit ModR/M decode. */
1258 switch (ctxt->modrm_mod) {
1259 case 0:
1260 if (ctxt->modrm_rm == 6)
1261 modrm_ea += insn_fetch(u16, ctxt);
1262 break;
1263 case 1:
1264 modrm_ea += insn_fetch(s8, ctxt);
1265 break;
1266 case 2:
1267 modrm_ea += insn_fetch(u16, ctxt);
1268 break;
1269 }
1270 switch (ctxt->modrm_rm) {
1271 case 0:
1272 modrm_ea += bx + si;
1273 break;
1274 case 1:
1275 modrm_ea += bx + di;
1276 break;
1277 case 2:
1278 modrm_ea += bp + si;
1279 break;
1280 case 3:
1281 modrm_ea += bp + di;
1282 break;
1283 case 4:
1284 modrm_ea += si;
1285 break;
1286 case 5:
1287 modrm_ea += di;
1288 break;
1289 case 6:
1290 if (ctxt->modrm_mod != 0)
1291 modrm_ea += bp;
1292 break;
1293 case 7:
1294 modrm_ea += bx;
1295 break;
1296 }
1297 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1298 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1299 ctxt->modrm_seg = VCPU_SREG_SS;
1300 modrm_ea = (u16)modrm_ea;
1301 } else {
1302 /* 32/64-bit ModR/M decode. */
1303 if ((ctxt->modrm_rm & 7) == 4) {
1304 sib = insn_fetch(u8, ctxt);
1305 index_reg |= (sib >> 3) & 7;
1306 base_reg |= sib & 7;
1307 scale = sib >> 6;
1308
1309 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
1310 modrm_ea += insn_fetch(s32, ctxt);
1311 else {
1312 modrm_ea += reg_read(ctxt, base_reg);
1313 adjust_modrm_seg(ctxt, base_reg);
1314 /* Increment ESP on POP [ESP] */
1315 if ((ctxt->d & IncSP) &&
1316 base_reg == VCPU_REGS_RSP)
1317 modrm_ea += ctxt->op_bytes;
1318 }
1319 if (index_reg != 4)
1320 modrm_ea += reg_read(ctxt, index_reg) << scale;
1321 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
1322 modrm_ea += insn_fetch(s32, ctxt);
1323 if (ctxt->mode == X86EMUL_MODE_PROT64)
1324 ctxt->rip_relative = 1;
1325 } else {
1326 base_reg = ctxt->modrm_rm;
1327 modrm_ea += reg_read(ctxt, base_reg);
1328 adjust_modrm_seg(ctxt, base_reg);
1329 }
1330 switch (ctxt->modrm_mod) {
1331 case 1:
1332 modrm_ea += insn_fetch(s8, ctxt);
1333 break;
1334 case 2:
1335 modrm_ea += insn_fetch(s32, ctxt);
1336 break;
1337 }
1338 }
1339 op->addr.mem.ea = modrm_ea;
1340 if (ctxt->ad_bytes != 8)
1341 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1342
1343done:
1344 return rc;
1345}
1346
1347static int decode_abs(struct x86_emulate_ctxt *ctxt,
1348 struct operand *op)
1349{
1350 int rc = X86EMUL_CONTINUE;
1351
1352 op->type = OP_MEM;
1353 switch (ctxt->ad_bytes) {
1354 case 2:
1355 op->addr.mem.ea = insn_fetch(u16, ctxt);
1356 break;
1357 case 4:
1358 op->addr.mem.ea = insn_fetch(u32, ctxt);
1359 break;
1360 case 8:
1361 op->addr.mem.ea = insn_fetch(u64, ctxt);
1362 break;
1363 }
1364done:
1365 return rc;
1366}
1367
1368static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
1369{
1370 long sv = 0, mask;
1371
1372 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1373 mask = ~((long)ctxt->dst.bytes * 8 - 1);
1374
1375 if (ctxt->src.bytes == 2)
1376 sv = (s16)ctxt->src.val & (s16)mask;
1377 else if (ctxt->src.bytes == 4)
1378 sv = (s32)ctxt->src.val & (s32)mask;
1379 else
1380 sv = (s64)ctxt->src.val & (s64)mask;
1381
1382 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1383 ctxt->dst.addr.mem.ea + (sv >> 3));
1384 }
1385
1386 /* only subword offset */
1387 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
1388}
1389
1390static int read_emulated(struct x86_emulate_ctxt *ctxt,
1391 unsigned long addr, void *dest, unsigned size)
1392{
1393 int rc;
1394 struct read_cache *mc = &ctxt->mem_read;
1395
1396 if (mc->pos < mc->end)
1397 goto read_cached;
1398
1399 WARN_ON((mc->end + size) >= sizeof(mc->data));
1400
1401 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1402 &ctxt->exception);
1403 if (rc != X86EMUL_CONTINUE)
1404 return rc;
1405
1406 mc->end += size;
1407
1408read_cached:
1409 memcpy(dest, mc->data + mc->pos, size);
1410 mc->pos += size;
1411 return X86EMUL_CONTINUE;
1412}
1413
1414static int segmented_read(struct x86_emulate_ctxt *ctxt,
1415 struct segmented_address addr,
1416 void *data,
1417 unsigned size)
1418{
1419 int rc;
1420 ulong linear;
1421
1422 rc = linearize(ctxt, addr, size, false, &linear);
1423 if (rc != X86EMUL_CONTINUE)
1424 return rc;
1425 return read_emulated(ctxt, linear, data, size);
1426}
1427
1428static int segmented_write(struct x86_emulate_ctxt *ctxt,
1429 struct segmented_address addr,
1430 const void *data,
1431 unsigned size)
1432{
1433 int rc;
1434 ulong linear;
1435
1436 rc = linearize(ctxt, addr, size, true, &linear);
1437 if (rc != X86EMUL_CONTINUE)
1438 return rc;
1439 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1440 &ctxt->exception);
1441}
1442
1443static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1444 struct segmented_address addr,
1445 const void *orig_data, const void *data,
1446 unsigned size)
1447{
1448 int rc;
1449 ulong linear;
1450
1451 rc = linearize(ctxt, addr, size, true, &linear);
1452 if (rc != X86EMUL_CONTINUE)
1453 return rc;
1454 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1455 size, &ctxt->exception);
1456}
1457
1458static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1459 unsigned int size, unsigned short port,
1460 void *dest)
1461{
1462 struct read_cache *rc = &ctxt->io_read;
1463
1464 if (rc->pos == rc->end) { /* refill pio read ahead */
1465 unsigned int in_page, n;
1466 unsigned int count = ctxt->rep_prefix ?
1467 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
1468 in_page = (ctxt->eflags & X86_EFLAGS_DF) ?
1469 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1470 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
1471 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
1472 if (n == 0)
1473 n = 1;
1474 rc->pos = rc->end = 0;
1475 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1476 return 0;
1477 rc->end = n * size;
1478 }
1479
1480 if (ctxt->rep_prefix && (ctxt->d & String) &&
1481 !(ctxt->eflags & X86_EFLAGS_DF)) {
1482 ctxt->dst.data = rc->data + rc->pos;
1483 ctxt->dst.type = OP_MEM_STR;
1484 ctxt->dst.count = (rc->end - rc->pos) / size;
1485 rc->pos = rc->end;
1486 } else {
1487 memcpy(dest, rc->data + rc->pos, size);
1488 rc->pos += size;
1489 }
1490 return 1;
1491}
1492
1493static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1494 u16 index, struct desc_struct *desc)
1495{
1496 struct desc_ptr dt;
1497 ulong addr;
1498
1499 ctxt->ops->get_idt(ctxt, &dt);
1500
1501 if (dt.size < index * 8 + 7)
1502 return emulate_gp(ctxt, index << 3 | 0x2);
1503
1504 addr = dt.address + index * 8;
1505 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1506 &ctxt->exception);
1507}
1508
1509static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1510 u16 selector, struct desc_ptr *dt)
1511{
1512 const struct x86_emulate_ops *ops = ctxt->ops;
1513 u32 base3 = 0;
1514
1515 if (selector & 1 << 2) {
1516 struct desc_struct desc;
1517 u16 sel;
1518
1519 memset (dt, 0, sizeof *dt);
1520 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1521 VCPU_SREG_LDTR))
1522 return;
1523
1524 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1525 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
1526 } else
1527 ops->get_gdt(ctxt, dt);
1528}
1529
1530static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt,
1531 u16 selector, ulong *desc_addr_p)
1532{
1533 struct desc_ptr dt;
1534 u16 index = selector >> 3;
1535 ulong addr;
1536
1537 get_descriptor_table_ptr(ctxt, selector, &dt);
1538
1539 if (dt.size < index * 8 + 7)
1540 return emulate_gp(ctxt, selector & 0xfffc);
1541
1542 addr = dt.address + index * 8;
1543
1544#ifdef CONFIG_X86_64
1545 if (addr >> 32 != 0) {
1546 u64 efer = 0;
1547
1548 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1549 if (!(efer & EFER_LMA))
1550 addr &= (u32)-1;
1551 }
1552#endif
1553
1554 *desc_addr_p = addr;
1555 return X86EMUL_CONTINUE;
1556}
1557
1558/* allowed just for 8 bytes segments */
1559static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1560 u16 selector, struct desc_struct *desc,
1561 ulong *desc_addr_p)
1562{
1563 int rc;
1564
1565 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p);
1566 if (rc != X86EMUL_CONTINUE)
1567 return rc;
1568
1569 return ctxt->ops->read_std(ctxt, *desc_addr_p, desc, sizeof(*desc),
1570 &ctxt->exception);
1571}
1572
1573/* allowed just for 8 bytes segments */
1574static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1575 u16 selector, struct desc_struct *desc)
1576{
1577 int rc;
1578 ulong addr;
1579
1580 rc = get_descriptor_ptr(ctxt, selector, &addr);
1581 if (rc != X86EMUL_CONTINUE)
1582 return rc;
1583
1584 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1585 &ctxt->exception);
1586}
1587
1588static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1589 u16 selector, int seg, u8 cpl,
1590 enum x86_transfer_type transfer,
1591 struct desc_struct *desc)
1592{
1593 struct desc_struct seg_desc, old_desc;
1594 u8 dpl, rpl;
1595 unsigned err_vec = GP_VECTOR;
1596 u32 err_code = 0;
1597 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1598 ulong desc_addr;
1599 int ret;
1600 u16 dummy;
1601 u32 base3 = 0;
1602
1603 memset(&seg_desc, 0, sizeof seg_desc);
1604
1605 if (ctxt->mode == X86EMUL_MODE_REAL) {
1606 /* set real mode segment descriptor (keep limit etc. for
1607 * unreal mode) */
1608 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
1609 set_desc_base(&seg_desc, selector << 4);
1610 goto load;
1611 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1612 /* VM86 needs a clean new segment descriptor */
1613 set_desc_base(&seg_desc, selector << 4);
1614 set_desc_limit(&seg_desc, 0xffff);
1615 seg_desc.type = 3;
1616 seg_desc.p = 1;
1617 seg_desc.s = 1;
1618 seg_desc.dpl = 3;
1619 goto load;
1620 }
1621
1622 rpl = selector & 3;
1623
1624 /* TR should be in GDT only */
1625 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1626 goto exception;
1627
1628 /* NULL selector is not valid for TR, CS and (except for long mode) SS */
1629 if (null_selector) {
1630 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_TR)
1631 goto exception;
1632
1633 if (seg == VCPU_SREG_SS) {
1634 if (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl)
1635 goto exception;
1636
1637 /*
1638 * ctxt->ops->set_segment expects the CPL to be in
1639 * SS.DPL, so fake an expand-up 32-bit data segment.
1640 */
1641 seg_desc.type = 3;
1642 seg_desc.p = 1;
1643 seg_desc.s = 1;
1644 seg_desc.dpl = cpl;
1645 seg_desc.d = 1;
1646 seg_desc.g = 1;
1647 }
1648
1649 /* Skip all following checks */
1650 goto load;
1651 }
1652
1653 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
1654 if (ret != X86EMUL_CONTINUE)
1655 return ret;
1656
1657 err_code = selector & 0xfffc;
1658 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR :
1659 GP_VECTOR;
1660
1661 /* can't load system descriptor into segment selector */
1662 if (seg <= VCPU_SREG_GS && !seg_desc.s) {
1663 if (transfer == X86_TRANSFER_CALL_JMP)
1664 return X86EMUL_UNHANDLEABLE;
1665 goto exception;
1666 }
1667
1668 if (!seg_desc.p) {
1669 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1670 goto exception;
1671 }
1672
1673 dpl = seg_desc.dpl;
1674
1675 switch (seg) {
1676 case VCPU_SREG_SS:
1677 /*
1678 * segment is not a writable data segment or segment
1679 * selector's RPL != CPL or segment selector's RPL != CPL
1680 */
1681 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1682 goto exception;
1683 break;
1684 case VCPU_SREG_CS:
1685 if (!(seg_desc.type & 8))
1686 goto exception;
1687
1688 if (seg_desc.type & 4) {
1689 /* conforming */
1690 if (dpl > cpl)
1691 goto exception;
1692 } else {
1693 /* nonconforming */
1694 if (rpl > cpl || dpl != cpl)
1695 goto exception;
1696 }
1697 /* in long-mode d/b must be clear if l is set */
1698 if (seg_desc.d && seg_desc.l) {
1699 u64 efer = 0;
1700
1701 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1702 if (efer & EFER_LMA)
1703 goto exception;
1704 }
1705
1706 /* CS(RPL) <- CPL */
1707 selector = (selector & 0xfffc) | cpl;
1708 break;
1709 case VCPU_SREG_TR:
1710 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1711 goto exception;
1712 old_desc = seg_desc;
1713 seg_desc.type |= 2; /* busy */
1714 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1715 sizeof(seg_desc), &ctxt->exception);
1716 if (ret != X86EMUL_CONTINUE)
1717 return ret;
1718 break;
1719 case VCPU_SREG_LDTR:
1720 if (seg_desc.s || seg_desc.type != 2)
1721 goto exception;
1722 break;
1723 default: /* DS, ES, FS, or GS */
1724 /*
1725 * segment is not a data or readable code segment or
1726 * ((segment is a data or nonconforming code segment)
1727 * and (both RPL and CPL > DPL))
1728 */
1729 if ((seg_desc.type & 0xa) == 0x8 ||
1730 (((seg_desc.type & 0xc) != 0xc) &&
1731 (rpl > dpl && cpl > dpl)))
1732 goto exception;
1733 break;
1734 }
1735
1736 if (seg_desc.s) {
1737 /* mark segment as accessed */
1738 if (!(seg_desc.type & 1)) {
1739 seg_desc.type |= 1;
1740 ret = write_segment_descriptor(ctxt, selector,
1741 &seg_desc);
1742 if (ret != X86EMUL_CONTINUE)
1743 return ret;
1744 }
1745 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1746 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1747 sizeof(base3), &ctxt->exception);
1748 if (ret != X86EMUL_CONTINUE)
1749 return ret;
1750 if (is_noncanonical_address(get_desc_base(&seg_desc) |
1751 ((u64)base3 << 32)))
1752 return emulate_gp(ctxt, 0);
1753 }
1754load:
1755 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
1756 if (desc)
1757 *desc = seg_desc;
1758 return X86EMUL_CONTINUE;
1759exception:
1760 return emulate_exception(ctxt, err_vec, err_code, true);
1761}
1762
1763static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1764 u16 selector, int seg)
1765{
1766 u8 cpl = ctxt->ops->cpl(ctxt);
1767
1768 /*
1769 * None of MOV, POP and LSS can load a NULL selector in CPL=3, but
1770 * they can load it at CPL<3 (Intel's manual says only LSS can,
1771 * but it's wrong).
1772 *
1773 * However, the Intel manual says that putting IST=1/DPL=3 in
1774 * an interrupt gate will result in SS=3 (the AMD manual instead
1775 * says it doesn't), so allow SS=3 in __load_segment_descriptor
1776 * and only forbid it here.
1777 */
1778 if (seg == VCPU_SREG_SS && selector == 3 &&
1779 ctxt->mode == X86EMUL_MODE_PROT64)
1780 return emulate_exception(ctxt, GP_VECTOR, 0, true);
1781
1782 return __load_segment_descriptor(ctxt, selector, seg, cpl,
1783 X86_TRANSFER_NONE, NULL);
1784}
1785
1786static void write_register_operand(struct operand *op)
1787{
1788 return assign_register(op->addr.reg, op->val, op->bytes);
1789}
1790
1791static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
1792{
1793 switch (op->type) {
1794 case OP_REG:
1795 write_register_operand(op);
1796 break;
1797 case OP_MEM:
1798 if (ctxt->lock_prefix)
1799 return segmented_cmpxchg(ctxt,
1800 op->addr.mem,
1801 &op->orig_val,
1802 &op->val,
1803 op->bytes);
1804 else
1805 return segmented_write(ctxt,
1806 op->addr.mem,
1807 &op->val,
1808 op->bytes);
1809 break;
1810 case OP_MEM_STR:
1811 return segmented_write(ctxt,
1812 op->addr.mem,
1813 op->data,
1814 op->bytes * op->count);
1815 break;
1816 case OP_XMM:
1817 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1818 break;
1819 case OP_MM:
1820 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
1821 break;
1822 case OP_NONE:
1823 /* no writeback */
1824 break;
1825 default:
1826 break;
1827 }
1828 return X86EMUL_CONTINUE;
1829}
1830
1831static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
1832{
1833 struct segmented_address addr;
1834
1835 rsp_increment(ctxt, -bytes);
1836 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1837 addr.seg = VCPU_SREG_SS;
1838
1839 return segmented_write(ctxt, addr, data, bytes);
1840}
1841
1842static int em_push(struct x86_emulate_ctxt *ctxt)
1843{
1844 /* Disable writeback. */
1845 ctxt->dst.type = OP_NONE;
1846 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
1847}
1848
1849static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1850 void *dest, int len)
1851{
1852 int rc;
1853 struct segmented_address addr;
1854
1855 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1856 addr.seg = VCPU_SREG_SS;
1857 rc = segmented_read(ctxt, addr, dest, len);
1858 if (rc != X86EMUL_CONTINUE)
1859 return rc;
1860
1861 rsp_increment(ctxt, len);
1862 return rc;
1863}
1864
1865static int em_pop(struct x86_emulate_ctxt *ctxt)
1866{
1867 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1868}
1869
1870static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1871 void *dest, int len)
1872{
1873 int rc;
1874 unsigned long val, change_mask;
1875 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
1876 int cpl = ctxt->ops->cpl(ctxt);
1877
1878 rc = emulate_pop(ctxt, &val, len);
1879 if (rc != X86EMUL_CONTINUE)
1880 return rc;
1881
1882 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
1883 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF |
1884 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT |
1885 X86_EFLAGS_AC | X86_EFLAGS_ID;
1886
1887 switch(ctxt->mode) {
1888 case X86EMUL_MODE_PROT64:
1889 case X86EMUL_MODE_PROT32:
1890 case X86EMUL_MODE_PROT16:
1891 if (cpl == 0)
1892 change_mask |= X86_EFLAGS_IOPL;
1893 if (cpl <= iopl)
1894 change_mask |= X86_EFLAGS_IF;
1895 break;
1896 case X86EMUL_MODE_VM86:
1897 if (iopl < 3)
1898 return emulate_gp(ctxt, 0);
1899 change_mask |= X86_EFLAGS_IF;
1900 break;
1901 default: /* real mode */
1902 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF);
1903 break;
1904 }
1905
1906 *(unsigned long *)dest =
1907 (ctxt->eflags & ~change_mask) | (val & change_mask);
1908
1909 return rc;
1910}
1911
1912static int em_popf(struct x86_emulate_ctxt *ctxt)
1913{
1914 ctxt->dst.type = OP_REG;
1915 ctxt->dst.addr.reg = &ctxt->eflags;
1916 ctxt->dst.bytes = ctxt->op_bytes;
1917 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1918}
1919
1920static int em_enter(struct x86_emulate_ctxt *ctxt)
1921{
1922 int rc;
1923 unsigned frame_size = ctxt->src.val;
1924 unsigned nesting_level = ctxt->src2.val & 31;
1925 ulong rbp;
1926
1927 if (nesting_level)
1928 return X86EMUL_UNHANDLEABLE;
1929
1930 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1931 rc = push(ctxt, &rbp, stack_size(ctxt));
1932 if (rc != X86EMUL_CONTINUE)
1933 return rc;
1934 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
1935 stack_mask(ctxt));
1936 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1937 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
1938 stack_mask(ctxt));
1939 return X86EMUL_CONTINUE;
1940}
1941
1942static int em_leave(struct x86_emulate_ctxt *ctxt)
1943{
1944 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
1945 stack_mask(ctxt));
1946 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
1947}
1948
1949static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
1950{
1951 int seg = ctxt->src2.val;
1952
1953 ctxt->src.val = get_segment_selector(ctxt, seg);
1954 if (ctxt->op_bytes == 4) {
1955 rsp_increment(ctxt, -2);
1956 ctxt->op_bytes = 2;
1957 }
1958
1959 return em_push(ctxt);
1960}
1961
1962static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
1963{
1964 int seg = ctxt->src2.val;
1965 unsigned long selector;
1966 int rc;
1967
1968 rc = emulate_pop(ctxt, &selector, 2);
1969 if (rc != X86EMUL_CONTINUE)
1970 return rc;
1971
1972 if (ctxt->modrm_reg == VCPU_SREG_SS)
1973 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1974 if (ctxt->op_bytes > 2)
1975 rsp_increment(ctxt, ctxt->op_bytes - 2);
1976
1977 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
1978 return rc;
1979}
1980
1981static int em_pusha(struct x86_emulate_ctxt *ctxt)
1982{
1983 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
1984 int rc = X86EMUL_CONTINUE;
1985 int reg = VCPU_REGS_RAX;
1986
1987 while (reg <= VCPU_REGS_RDI) {
1988 (reg == VCPU_REGS_RSP) ?
1989 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
1990
1991 rc = em_push(ctxt);
1992 if (rc != X86EMUL_CONTINUE)
1993 return rc;
1994
1995 ++reg;
1996 }
1997
1998 return rc;
1999}
2000
2001static int em_pushf(struct x86_emulate_ctxt *ctxt)
2002{
2003 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM;
2004 return em_push(ctxt);
2005}
2006
2007static int em_popa(struct x86_emulate_ctxt *ctxt)
2008{
2009 int rc = X86EMUL_CONTINUE;
2010 int reg = VCPU_REGS_RDI;
2011 u32 val;
2012
2013 while (reg >= VCPU_REGS_RAX) {
2014 if (reg == VCPU_REGS_RSP) {
2015 rsp_increment(ctxt, ctxt->op_bytes);
2016 --reg;
2017 }
2018
2019 rc = emulate_pop(ctxt, &val, ctxt->op_bytes);
2020 if (rc != X86EMUL_CONTINUE)
2021 break;
2022 assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes);
2023 --reg;
2024 }
2025 return rc;
2026}
2027
2028static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2029{
2030 const struct x86_emulate_ops *ops = ctxt->ops;
2031 int rc;
2032 struct desc_ptr dt;
2033 gva_t cs_addr;
2034 gva_t eip_addr;
2035 u16 cs, eip;
2036
2037 /* TODO: Add limit checks */
2038 ctxt->src.val = ctxt->eflags;
2039 rc = em_push(ctxt);
2040 if (rc != X86EMUL_CONTINUE)
2041 return rc;
2042
2043 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC);
2044
2045 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
2046 rc = em_push(ctxt);
2047 if (rc != X86EMUL_CONTINUE)
2048 return rc;
2049
2050 ctxt->src.val = ctxt->_eip;
2051 rc = em_push(ctxt);
2052 if (rc != X86EMUL_CONTINUE)
2053 return rc;
2054
2055 ops->get_idt(ctxt, &dt);
2056
2057 eip_addr = dt.address + (irq << 2);
2058 cs_addr = dt.address + (irq << 2) + 2;
2059
2060 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
2061 if (rc != X86EMUL_CONTINUE)
2062 return rc;
2063
2064 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
2065 if (rc != X86EMUL_CONTINUE)
2066 return rc;
2067
2068 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
2069 if (rc != X86EMUL_CONTINUE)
2070 return rc;
2071
2072 ctxt->_eip = eip;
2073
2074 return rc;
2075}
2076
2077int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2078{
2079 int rc;
2080
2081 invalidate_registers(ctxt);
2082 rc = __emulate_int_real(ctxt, irq);
2083 if (rc == X86EMUL_CONTINUE)
2084 writeback_registers(ctxt);
2085 return rc;
2086}
2087
2088static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
2089{
2090 switch(ctxt->mode) {
2091 case X86EMUL_MODE_REAL:
2092 return __emulate_int_real(ctxt, irq);
2093 case X86EMUL_MODE_VM86:
2094 case X86EMUL_MODE_PROT16:
2095 case X86EMUL_MODE_PROT32:
2096 case X86EMUL_MODE_PROT64:
2097 default:
2098 /* Protected mode interrupts unimplemented yet */
2099 return X86EMUL_UNHANDLEABLE;
2100 }
2101}
2102
2103static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
2104{
2105 int rc = X86EMUL_CONTINUE;
2106 unsigned long temp_eip = 0;
2107 unsigned long temp_eflags = 0;
2108 unsigned long cs = 0;
2109 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
2110 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF |
2111 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF |
2112 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF |
2113 X86_EFLAGS_AC | X86_EFLAGS_ID |
2114 X86_EFLAGS_FIXED;
2115 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF |
2116 X86_EFLAGS_VIP;
2117
2118 /* TODO: Add stack limit check */
2119
2120 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
2121
2122 if (rc != X86EMUL_CONTINUE)
2123 return rc;
2124
2125 if (temp_eip & ~0xffff)
2126 return emulate_gp(ctxt, 0);
2127
2128 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2129
2130 if (rc != X86EMUL_CONTINUE)
2131 return rc;
2132
2133 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
2134
2135 if (rc != X86EMUL_CONTINUE)
2136 return rc;
2137
2138 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
2139
2140 if (rc != X86EMUL_CONTINUE)
2141 return rc;
2142
2143 ctxt->_eip = temp_eip;
2144
2145 if (ctxt->op_bytes == 4)
2146 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
2147 else if (ctxt->op_bytes == 2) {
2148 ctxt->eflags &= ~0xffff;
2149 ctxt->eflags |= temp_eflags;
2150 }
2151
2152 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2153 ctxt->eflags |= X86_EFLAGS_FIXED;
2154 ctxt->ops->set_nmi_mask(ctxt, false);
2155
2156 return rc;
2157}
2158
2159static int em_iret(struct x86_emulate_ctxt *ctxt)
2160{
2161 switch(ctxt->mode) {
2162 case X86EMUL_MODE_REAL:
2163 return emulate_iret_real(ctxt);
2164 case X86EMUL_MODE_VM86:
2165 case X86EMUL_MODE_PROT16:
2166 case X86EMUL_MODE_PROT32:
2167 case X86EMUL_MODE_PROT64:
2168 default:
2169 /* iret from protected mode unimplemented yet */
2170 return X86EMUL_UNHANDLEABLE;
2171 }
2172}
2173
2174static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2175{
2176 int rc;
2177 unsigned short sel;
2178 struct desc_struct new_desc;
2179 u8 cpl = ctxt->ops->cpl(ctxt);
2180
2181 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2182
2183 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
2184 X86_TRANSFER_CALL_JMP,
2185 &new_desc);
2186 if (rc != X86EMUL_CONTINUE)
2187 return rc;
2188
2189 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
2190 /* Error handling is not implemented. */
2191 if (rc != X86EMUL_CONTINUE)
2192 return X86EMUL_UNHANDLEABLE;
2193
2194 return rc;
2195}
2196
2197static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
2198{
2199 return assign_eip_near(ctxt, ctxt->src.val);
2200}
2201
2202static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2203{
2204 int rc;
2205 long int old_eip;
2206
2207 old_eip = ctxt->_eip;
2208 rc = assign_eip_near(ctxt, ctxt->src.val);
2209 if (rc != X86EMUL_CONTINUE)
2210 return rc;
2211 ctxt->src.val = old_eip;
2212 rc = em_push(ctxt);
2213 return rc;
2214}
2215
2216static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
2217{
2218 u64 old = ctxt->dst.orig_val64;
2219
2220 if (ctxt->dst.bytes == 16)
2221 return X86EMUL_UNHANDLEABLE;
2222
2223 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2224 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2225 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2226 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
2227 ctxt->eflags &= ~X86_EFLAGS_ZF;
2228 } else {
2229 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2230 (u32) reg_read(ctxt, VCPU_REGS_RBX);
2231
2232 ctxt->eflags |= X86_EFLAGS_ZF;
2233 }
2234 return X86EMUL_CONTINUE;
2235}
2236
2237static int em_ret(struct x86_emulate_ctxt *ctxt)
2238{
2239 int rc;
2240 unsigned long eip;
2241
2242 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2243 if (rc != X86EMUL_CONTINUE)
2244 return rc;
2245
2246 return assign_eip_near(ctxt, eip);
2247}
2248
2249static int em_ret_far(struct x86_emulate_ctxt *ctxt)
2250{
2251 int rc;
2252 unsigned long eip, cs;
2253 int cpl = ctxt->ops->cpl(ctxt);
2254 struct desc_struct new_desc;
2255
2256 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2257 if (rc != X86EMUL_CONTINUE)
2258 return rc;
2259 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2260 if (rc != X86EMUL_CONTINUE)
2261 return rc;
2262 /* Outer-privilege level return is not implemented */
2263 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2264 return X86EMUL_UNHANDLEABLE;
2265 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl,
2266 X86_TRANSFER_RET,
2267 &new_desc);
2268 if (rc != X86EMUL_CONTINUE)
2269 return rc;
2270 rc = assign_eip_far(ctxt, eip, &new_desc);
2271 /* Error handling is not implemented. */
2272 if (rc != X86EMUL_CONTINUE)
2273 return X86EMUL_UNHANDLEABLE;
2274
2275 return rc;
2276}
2277
2278static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2279{
2280 int rc;
2281
2282 rc = em_ret_far(ctxt);
2283 if (rc != X86EMUL_CONTINUE)
2284 return rc;
2285 rsp_increment(ctxt, ctxt->src.val);
2286 return X86EMUL_CONTINUE;
2287}
2288
2289static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2290{
2291 /* Save real source value, then compare EAX against destination. */
2292 ctxt->dst.orig_val = ctxt->dst.val;
2293 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
2294 ctxt->src.orig_val = ctxt->src.val;
2295 ctxt->src.val = ctxt->dst.orig_val;
2296 fastop(ctxt, em_cmp);
2297
2298 if (ctxt->eflags & X86_EFLAGS_ZF) {
2299 /* Success: write back to memory; no update of EAX */
2300 ctxt->src.type = OP_NONE;
2301 ctxt->dst.val = ctxt->src.orig_val;
2302 } else {
2303 /* Failure: write the value we saw to EAX. */
2304 ctxt->src.type = OP_REG;
2305 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2306 ctxt->src.val = ctxt->dst.orig_val;
2307 /* Create write-cycle to dest by writing the same value */
2308 ctxt->dst.val = ctxt->dst.orig_val;
2309 }
2310 return X86EMUL_CONTINUE;
2311}
2312
2313static int em_lseg(struct x86_emulate_ctxt *ctxt)
2314{
2315 int seg = ctxt->src2.val;
2316 unsigned short sel;
2317 int rc;
2318
2319 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2320
2321 rc = load_segment_descriptor(ctxt, sel, seg);
2322 if (rc != X86EMUL_CONTINUE)
2323 return rc;
2324
2325 ctxt->dst.val = ctxt->src.val;
2326 return rc;
2327}
2328
2329static int emulator_has_longmode(struct x86_emulate_ctxt *ctxt)
2330{
2331 u32 eax, ebx, ecx, edx;
2332
2333 eax = 0x80000001;
2334 ecx = 0;
2335 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2336 return edx & bit(X86_FEATURE_LM);
2337}
2338
2339#define GET_SMSTATE(type, smbase, offset) \
2340 ({ \
2341 type __val; \
2342 int r = ctxt->ops->read_phys(ctxt, smbase + offset, &__val, \
2343 sizeof(__val)); \
2344 if (r != X86EMUL_CONTINUE) \
2345 return X86EMUL_UNHANDLEABLE; \
2346 __val; \
2347 })
2348
2349static void rsm_set_desc_flags(struct desc_struct *desc, u32 flags)
2350{
2351 desc->g = (flags >> 23) & 1;
2352 desc->d = (flags >> 22) & 1;
2353 desc->l = (flags >> 21) & 1;
2354 desc->avl = (flags >> 20) & 1;
2355 desc->p = (flags >> 15) & 1;
2356 desc->dpl = (flags >> 13) & 3;
2357 desc->s = (flags >> 12) & 1;
2358 desc->type = (flags >> 8) & 15;
2359}
2360
2361static int rsm_load_seg_32(struct x86_emulate_ctxt *ctxt, u64 smbase, int n)
2362{
2363 struct desc_struct desc;
2364 int offset;
2365 u16 selector;
2366
2367 selector = GET_SMSTATE(u32, smbase, 0x7fa8 + n * 4);
2368
2369 if (n < 3)
2370 offset = 0x7f84 + n * 12;
2371 else
2372 offset = 0x7f2c + (n - 3) * 12;
2373
2374 set_desc_base(&desc, GET_SMSTATE(u32, smbase, offset + 8));
2375 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, offset + 4));
2376 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, offset));
2377 ctxt->ops->set_segment(ctxt, selector, &desc, 0, n);
2378 return X86EMUL_CONTINUE;
2379}
2380
2381static int rsm_load_seg_64(struct x86_emulate_ctxt *ctxt, u64 smbase, int n)
2382{
2383 struct desc_struct desc;
2384 int offset;
2385 u16 selector;
2386 u32 base3;
2387
2388 offset = 0x7e00 + n * 16;
2389
2390 selector = GET_SMSTATE(u16, smbase, offset);
2391 rsm_set_desc_flags(&desc, GET_SMSTATE(u16, smbase, offset + 2) << 8);
2392 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, offset + 4));
2393 set_desc_base(&desc, GET_SMSTATE(u32, smbase, offset + 8));
2394 base3 = GET_SMSTATE(u32, smbase, offset + 12);
2395
2396 ctxt->ops->set_segment(ctxt, selector, &desc, base3, n);
2397 return X86EMUL_CONTINUE;
2398}
2399
2400static int rsm_enter_protected_mode(struct x86_emulate_ctxt *ctxt,
2401 u64 cr0, u64 cr4)
2402{
2403 int bad;
2404
2405 /*
2406 * First enable PAE, long mode needs it before CR0.PG = 1 is set.
2407 * Then enable protected mode. However, PCID cannot be enabled
2408 * if EFER.LMA=0, so set it separately.
2409 */
2410 bad = ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
2411 if (bad)
2412 return X86EMUL_UNHANDLEABLE;
2413
2414 bad = ctxt->ops->set_cr(ctxt, 0, cr0);
2415 if (bad)
2416 return X86EMUL_UNHANDLEABLE;
2417
2418 if (cr4 & X86_CR4_PCIDE) {
2419 bad = ctxt->ops->set_cr(ctxt, 4, cr4);
2420 if (bad)
2421 return X86EMUL_UNHANDLEABLE;
2422 }
2423
2424 return X86EMUL_CONTINUE;
2425}
2426
2427static int rsm_load_state_32(struct x86_emulate_ctxt *ctxt, u64 smbase)
2428{
2429 struct desc_struct desc;
2430 struct desc_ptr dt;
2431 u16 selector;
2432 u32 val, cr0, cr4;
2433 int i;
2434
2435 cr0 = GET_SMSTATE(u32, smbase, 0x7ffc);
2436 ctxt->ops->set_cr(ctxt, 3, GET_SMSTATE(u32, smbase, 0x7ff8));
2437 ctxt->eflags = GET_SMSTATE(u32, smbase, 0x7ff4) | X86_EFLAGS_FIXED;
2438 ctxt->_eip = GET_SMSTATE(u32, smbase, 0x7ff0);
2439
2440 for (i = 0; i < 8; i++)
2441 *reg_write(ctxt, i) = GET_SMSTATE(u32, smbase, 0x7fd0 + i * 4);
2442
2443 val = GET_SMSTATE(u32, smbase, 0x7fcc);
2444 ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1);
2445 val = GET_SMSTATE(u32, smbase, 0x7fc8);
2446 ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1);
2447
2448 selector = GET_SMSTATE(u32, smbase, 0x7fc4);
2449 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7f64));
2450 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7f60));
2451 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7f5c));
2452 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_TR);
2453
2454 selector = GET_SMSTATE(u32, smbase, 0x7fc0);
2455 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7f80));
2456 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7f7c));
2457 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7f78));
2458 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_LDTR);
2459
2460 dt.address = GET_SMSTATE(u32, smbase, 0x7f74);
2461 dt.size = GET_SMSTATE(u32, smbase, 0x7f70);
2462 ctxt->ops->set_gdt(ctxt, &dt);
2463
2464 dt.address = GET_SMSTATE(u32, smbase, 0x7f58);
2465 dt.size = GET_SMSTATE(u32, smbase, 0x7f54);
2466 ctxt->ops->set_idt(ctxt, &dt);
2467
2468 for (i = 0; i < 6; i++) {
2469 int r = rsm_load_seg_32(ctxt, smbase, i);
2470 if (r != X86EMUL_CONTINUE)
2471 return r;
2472 }
2473
2474 cr4 = GET_SMSTATE(u32, smbase, 0x7f14);
2475
2476 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7ef8));
2477
2478 return rsm_enter_protected_mode(ctxt, cr0, cr4);
2479}
2480
2481static int rsm_load_state_64(struct x86_emulate_ctxt *ctxt, u64 smbase)
2482{
2483 struct desc_struct desc;
2484 struct desc_ptr dt;
2485 u64 val, cr0, cr4;
2486 u32 base3;
2487 u16 selector;
2488 int i, r;
2489
2490 for (i = 0; i < 16; i++)
2491 *reg_write(ctxt, i) = GET_SMSTATE(u64, smbase, 0x7ff8 - i * 8);
2492
2493 ctxt->_eip = GET_SMSTATE(u64, smbase, 0x7f78);
2494 ctxt->eflags = GET_SMSTATE(u32, smbase, 0x7f70) | X86_EFLAGS_FIXED;
2495
2496 val = GET_SMSTATE(u32, smbase, 0x7f68);
2497 ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1);
2498 val = GET_SMSTATE(u32, smbase, 0x7f60);
2499 ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1);
2500
2501 cr0 = GET_SMSTATE(u64, smbase, 0x7f58);
2502 ctxt->ops->set_cr(ctxt, 3, GET_SMSTATE(u64, smbase, 0x7f50));
2503 cr4 = GET_SMSTATE(u64, smbase, 0x7f48);
2504 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7f00));
2505 val = GET_SMSTATE(u64, smbase, 0x7ed0);
2506 ctxt->ops->set_msr(ctxt, MSR_EFER, val & ~EFER_LMA);
2507
2508 selector = GET_SMSTATE(u32, smbase, 0x7e90);
2509 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7e92) << 8);
2510 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7e94));
2511 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7e98));
2512 base3 = GET_SMSTATE(u32, smbase, 0x7e9c);
2513 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_TR);
2514
2515 dt.size = GET_SMSTATE(u32, smbase, 0x7e84);
2516 dt.address = GET_SMSTATE(u64, smbase, 0x7e88);
2517 ctxt->ops->set_idt(ctxt, &dt);
2518
2519 selector = GET_SMSTATE(u32, smbase, 0x7e70);
2520 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7e72) << 8);
2521 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7e74));
2522 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7e78));
2523 base3 = GET_SMSTATE(u32, smbase, 0x7e7c);
2524 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_LDTR);
2525
2526 dt.size = GET_SMSTATE(u32, smbase, 0x7e64);
2527 dt.address = GET_SMSTATE(u64, smbase, 0x7e68);
2528 ctxt->ops->set_gdt(ctxt, &dt);
2529
2530 r = rsm_enter_protected_mode(ctxt, cr0, cr4);
2531 if (r != X86EMUL_CONTINUE)
2532 return r;
2533
2534 for (i = 0; i < 6; i++) {
2535 r = rsm_load_seg_64(ctxt, smbase, i);
2536 if (r != X86EMUL_CONTINUE)
2537 return r;
2538 }
2539
2540 return X86EMUL_CONTINUE;
2541}
2542
2543static int em_rsm(struct x86_emulate_ctxt *ctxt)
2544{
2545 unsigned long cr0, cr4, efer;
2546 u64 smbase;
2547 int ret;
2548
2549 if ((ctxt->emul_flags & X86EMUL_SMM_MASK) == 0)
2550 return emulate_ud(ctxt);
2551
2552 /*
2553 * Get back to real mode, to prepare a safe state in which to load
2554 * CR0/CR3/CR4/EFER. It's all a bit more complicated if the vCPU
2555 * supports long mode.
2556 */
2557 cr4 = ctxt->ops->get_cr(ctxt, 4);
2558 if (emulator_has_longmode(ctxt)) {
2559 struct desc_struct cs_desc;
2560
2561 /* Zero CR4.PCIDE before CR0.PG. */
2562 if (cr4 & X86_CR4_PCIDE) {
2563 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
2564 cr4 &= ~X86_CR4_PCIDE;
2565 }
2566
2567 /* A 32-bit code segment is required to clear EFER.LMA. */
2568 memset(&cs_desc, 0, sizeof(cs_desc));
2569 cs_desc.type = 0xb;
2570 cs_desc.s = cs_desc.g = cs_desc.p = 1;
2571 ctxt->ops->set_segment(ctxt, 0, &cs_desc, 0, VCPU_SREG_CS);
2572 }
2573
2574 /* For the 64-bit case, this will clear EFER.LMA. */
2575 cr0 = ctxt->ops->get_cr(ctxt, 0);
2576 if (cr0 & X86_CR0_PE)
2577 ctxt->ops->set_cr(ctxt, 0, cr0 & ~(X86_CR0_PG | X86_CR0_PE));
2578
2579 /* Now clear CR4.PAE (which must be done before clearing EFER.LME). */
2580 if (cr4 & X86_CR4_PAE)
2581 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PAE);
2582
2583 /* And finally go back to 32-bit mode. */
2584 efer = 0;
2585 ctxt->ops->set_msr(ctxt, MSR_EFER, efer);
2586
2587 smbase = ctxt->ops->get_smbase(ctxt);
2588 if (emulator_has_longmode(ctxt))
2589 ret = rsm_load_state_64(ctxt, smbase + 0x8000);
2590 else
2591 ret = rsm_load_state_32(ctxt, smbase + 0x8000);
2592
2593 if (ret != X86EMUL_CONTINUE) {
2594 /* FIXME: should triple fault */
2595 return X86EMUL_UNHANDLEABLE;
2596 }
2597
2598 if ((ctxt->emul_flags & X86EMUL_SMM_INSIDE_NMI_MASK) == 0)
2599 ctxt->ops->set_nmi_mask(ctxt, false);
2600
2601 ctxt->emul_flags &= ~X86EMUL_SMM_INSIDE_NMI_MASK;
2602 ctxt->emul_flags &= ~X86EMUL_SMM_MASK;
2603 return X86EMUL_CONTINUE;
2604}
2605
2606static void
2607setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
2608 struct desc_struct *cs, struct desc_struct *ss)
2609{
2610 cs->l = 0; /* will be adjusted later */
2611 set_desc_base(cs, 0); /* flat segment */
2612 cs->g = 1; /* 4kb granularity */
2613 set_desc_limit(cs, 0xfffff); /* 4GB limit */
2614 cs->type = 0x0b; /* Read, Execute, Accessed */
2615 cs->s = 1;
2616 cs->dpl = 0; /* will be adjusted later */
2617 cs->p = 1;
2618 cs->d = 1;
2619 cs->avl = 0;
2620
2621 set_desc_base(ss, 0); /* flat segment */
2622 set_desc_limit(ss, 0xfffff); /* 4GB limit */
2623 ss->g = 1; /* 4kb granularity */
2624 ss->s = 1;
2625 ss->type = 0x03; /* Read/Write, Accessed */
2626 ss->d = 1; /* 32bit stack segment */
2627 ss->dpl = 0;
2628 ss->p = 1;
2629 ss->l = 0;
2630 ss->avl = 0;
2631}
2632
2633static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2634{
2635 u32 eax, ebx, ecx, edx;
2636
2637 eax = ecx = 0;
2638 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2639 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
2640 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2641 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2642}
2643
2644static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2645{
2646 const struct x86_emulate_ops *ops = ctxt->ops;
2647 u32 eax, ebx, ecx, edx;
2648
2649 /*
2650 * syscall should always be enabled in longmode - so only become
2651 * vendor specific (cpuid) if other modes are active...
2652 */
2653 if (ctxt->mode == X86EMUL_MODE_PROT64)
2654 return true;
2655
2656 eax = 0x00000000;
2657 ecx = 0x00000000;
2658 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2659 /*
2660 * Intel ("GenuineIntel")
2661 * remark: Intel CPUs only support "syscall" in 64bit
2662 * longmode. Also an 64bit guest with a
2663 * 32bit compat-app running will #UD !! While this
2664 * behaviour can be fixed (by emulating) into AMD
2665 * response - CPUs of AMD can't behave like Intel.
2666 */
2667 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2668 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2669 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2670 return false;
2671
2672 /* AMD ("AuthenticAMD") */
2673 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2674 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2675 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2676 return true;
2677
2678 /* AMD ("AMDisbetter!") */
2679 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2680 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2681 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2682 return true;
2683
2684 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2685 return false;
2686}
2687
2688static int em_syscall(struct x86_emulate_ctxt *ctxt)
2689{
2690 const struct x86_emulate_ops *ops = ctxt->ops;
2691 struct desc_struct cs, ss;
2692 u64 msr_data;
2693 u16 cs_sel, ss_sel;
2694 u64 efer = 0;
2695
2696 /* syscall is not available in real mode */
2697 if (ctxt->mode == X86EMUL_MODE_REAL ||
2698 ctxt->mode == X86EMUL_MODE_VM86)
2699 return emulate_ud(ctxt);
2700
2701 if (!(em_syscall_is_enabled(ctxt)))
2702 return emulate_ud(ctxt);
2703
2704 ops->get_msr(ctxt, MSR_EFER, &efer);
2705 setup_syscalls_segments(ctxt, &cs, &ss);
2706
2707 if (!(efer & EFER_SCE))
2708 return emulate_ud(ctxt);
2709
2710 ops->get_msr(ctxt, MSR_STAR, &msr_data);
2711 msr_data >>= 32;
2712 cs_sel = (u16)(msr_data & 0xfffc);
2713 ss_sel = (u16)(msr_data + 8);
2714
2715 if (efer & EFER_LMA) {
2716 cs.d = 0;
2717 cs.l = 1;
2718 }
2719 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2720 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2721
2722 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
2723 if (efer & EFER_LMA) {
2724#ifdef CONFIG_X86_64
2725 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
2726
2727 ops->get_msr(ctxt,
2728 ctxt->mode == X86EMUL_MODE_PROT64 ?
2729 MSR_LSTAR : MSR_CSTAR, &msr_data);
2730 ctxt->_eip = msr_data;
2731
2732 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
2733 ctxt->eflags &= ~msr_data;
2734 ctxt->eflags |= X86_EFLAGS_FIXED;
2735#endif
2736 } else {
2737 /* legacy mode */
2738 ops->get_msr(ctxt, MSR_STAR, &msr_data);
2739 ctxt->_eip = (u32)msr_data;
2740
2741 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
2742 }
2743
2744 return X86EMUL_CONTINUE;
2745}
2746
2747static int em_sysenter(struct x86_emulate_ctxt *ctxt)
2748{
2749 const struct x86_emulate_ops *ops = ctxt->ops;
2750 struct desc_struct cs, ss;
2751 u64 msr_data;
2752 u16 cs_sel, ss_sel;
2753 u64 efer = 0;
2754
2755 ops->get_msr(ctxt, MSR_EFER, &efer);
2756 /* inject #GP if in real mode */
2757 if (ctxt->mode == X86EMUL_MODE_REAL)
2758 return emulate_gp(ctxt, 0);
2759
2760 /*
2761 * Not recognized on AMD in compat mode (but is recognized in legacy
2762 * mode).
2763 */
2764 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA)
2765 && !vendor_intel(ctxt))
2766 return emulate_ud(ctxt);
2767
2768 /* sysenter/sysexit have not been tested in 64bit mode. */
2769 if (ctxt->mode == X86EMUL_MODE_PROT64)
2770 return X86EMUL_UNHANDLEABLE;
2771
2772 setup_syscalls_segments(ctxt, &cs, &ss);
2773
2774 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2775 if ((msr_data & 0xfffc) == 0x0)
2776 return emulate_gp(ctxt, 0);
2777
2778 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
2779 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK;
2780 ss_sel = cs_sel + 8;
2781 if (efer & EFER_LMA) {
2782 cs.d = 0;
2783 cs.l = 1;
2784 }
2785
2786 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2787 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2788
2789 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
2790 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data;
2791
2792 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
2793 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data :
2794 (u32)msr_data;
2795
2796 return X86EMUL_CONTINUE;
2797}
2798
2799static int em_sysexit(struct x86_emulate_ctxt *ctxt)
2800{
2801 const struct x86_emulate_ops *ops = ctxt->ops;
2802 struct desc_struct cs, ss;
2803 u64 msr_data, rcx, rdx;
2804 int usermode;
2805 u16 cs_sel = 0, ss_sel = 0;
2806
2807 /* inject #GP if in real mode or Virtual 8086 mode */
2808 if (ctxt->mode == X86EMUL_MODE_REAL ||
2809 ctxt->mode == X86EMUL_MODE_VM86)
2810 return emulate_gp(ctxt, 0);
2811
2812 setup_syscalls_segments(ctxt, &cs, &ss);
2813
2814 if ((ctxt->rex_prefix & 0x8) != 0x0)
2815 usermode = X86EMUL_MODE_PROT64;
2816 else
2817 usermode = X86EMUL_MODE_PROT32;
2818
2819 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2820 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2821
2822 cs.dpl = 3;
2823 ss.dpl = 3;
2824 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2825 switch (usermode) {
2826 case X86EMUL_MODE_PROT32:
2827 cs_sel = (u16)(msr_data + 16);
2828 if ((msr_data & 0xfffc) == 0x0)
2829 return emulate_gp(ctxt, 0);
2830 ss_sel = (u16)(msr_data + 24);
2831 rcx = (u32)rcx;
2832 rdx = (u32)rdx;
2833 break;
2834 case X86EMUL_MODE_PROT64:
2835 cs_sel = (u16)(msr_data + 32);
2836 if (msr_data == 0x0)
2837 return emulate_gp(ctxt, 0);
2838 ss_sel = cs_sel + 8;
2839 cs.d = 0;
2840 cs.l = 1;
2841 if (is_noncanonical_address(rcx) ||
2842 is_noncanonical_address(rdx))
2843 return emulate_gp(ctxt, 0);
2844 break;
2845 }
2846 cs_sel |= SEGMENT_RPL_MASK;
2847 ss_sel |= SEGMENT_RPL_MASK;
2848
2849 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2850 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2851
2852 ctxt->_eip = rdx;
2853 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
2854
2855 return X86EMUL_CONTINUE;
2856}
2857
2858static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
2859{
2860 int iopl;
2861 if (ctxt->mode == X86EMUL_MODE_REAL)
2862 return false;
2863 if (ctxt->mode == X86EMUL_MODE_VM86)
2864 return true;
2865 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
2866 return ctxt->ops->cpl(ctxt) > iopl;
2867}
2868
2869static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2870 u16 port, u16 len)
2871{
2872 const struct x86_emulate_ops *ops = ctxt->ops;
2873 struct desc_struct tr_seg;
2874 u32 base3;
2875 int r;
2876 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
2877 unsigned mask = (1 << len) - 1;
2878 unsigned long base;
2879
2880 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
2881 if (!tr_seg.p)
2882 return false;
2883 if (desc_limit_scaled(&tr_seg) < 103)
2884 return false;
2885 base = get_desc_base(&tr_seg);
2886#ifdef CONFIG_X86_64
2887 base |= ((u64)base3) << 32;
2888#endif
2889 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2890 if (r != X86EMUL_CONTINUE)
2891 return false;
2892 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2893 return false;
2894 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2895 if (r != X86EMUL_CONTINUE)
2896 return false;
2897 if ((perm >> bit_idx) & mask)
2898 return false;
2899 return true;
2900}
2901
2902static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2903 u16 port, u16 len)
2904{
2905 if (ctxt->perm_ok)
2906 return true;
2907
2908 if (emulator_bad_iopl(ctxt))
2909 if (!emulator_io_port_access_allowed(ctxt, port, len))
2910 return false;
2911
2912 ctxt->perm_ok = true;
2913
2914 return true;
2915}
2916
2917static void string_registers_quirk(struct x86_emulate_ctxt *ctxt)
2918{
2919 /*
2920 * Intel CPUs mask the counter and pointers in quite strange
2921 * manner when ECX is zero due to REP-string optimizations.
2922 */
2923#ifdef CONFIG_X86_64
2924 if (ctxt->ad_bytes != 4 || !vendor_intel(ctxt))
2925 return;
2926
2927 *reg_write(ctxt, VCPU_REGS_RCX) = 0;
2928
2929 switch (ctxt->b) {
2930 case 0xa4: /* movsb */
2931 case 0xa5: /* movsd/w */
2932 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1;
2933 /* fall through */
2934 case 0xaa: /* stosb */
2935 case 0xab: /* stosd/w */
2936 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1;
2937 }
2938#endif
2939}
2940
2941static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2942 struct tss_segment_16 *tss)
2943{
2944 tss->ip = ctxt->_eip;
2945 tss->flag = ctxt->eflags;
2946 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2947 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2948 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2949 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2950 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2951 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2952 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2953 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
2954
2955 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2956 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2957 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2958 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2959 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2960}
2961
2962static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2963 struct tss_segment_16 *tss)
2964{
2965 int ret;
2966 u8 cpl;
2967
2968 ctxt->_eip = tss->ip;
2969 ctxt->eflags = tss->flag | 2;
2970 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2971 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2972 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2973 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2974 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2975 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2976 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2977 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
2978
2979 /*
2980 * SDM says that segment selectors are loaded before segment
2981 * descriptors
2982 */
2983 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2984 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2985 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2986 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2987 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2988
2989 cpl = tss->cs & 3;
2990
2991 /*
2992 * Now load segment descriptors. If fault happens at this stage
2993 * it is handled in a context of new task
2994 */
2995 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
2996 X86_TRANSFER_TASK_SWITCH, NULL);
2997 if (ret != X86EMUL_CONTINUE)
2998 return ret;
2999 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3000 X86_TRANSFER_TASK_SWITCH, NULL);
3001 if (ret != X86EMUL_CONTINUE)
3002 return ret;
3003 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3004 X86_TRANSFER_TASK_SWITCH, NULL);
3005 if (ret != X86EMUL_CONTINUE)
3006 return ret;
3007 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3008 X86_TRANSFER_TASK_SWITCH, NULL);
3009 if (ret != X86EMUL_CONTINUE)
3010 return ret;
3011 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3012 X86_TRANSFER_TASK_SWITCH, NULL);
3013 if (ret != X86EMUL_CONTINUE)
3014 return ret;
3015
3016 return X86EMUL_CONTINUE;
3017}
3018
3019static int task_switch_16(struct x86_emulate_ctxt *ctxt,
3020 u16 tss_selector, u16 old_tss_sel,
3021 ulong old_tss_base, struct desc_struct *new_desc)
3022{
3023 const struct x86_emulate_ops *ops = ctxt->ops;
3024 struct tss_segment_16 tss_seg;
3025 int ret;
3026 u32 new_tss_base = get_desc_base(new_desc);
3027
3028 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
3029 &ctxt->exception);
3030 if (ret != X86EMUL_CONTINUE)
3031 return ret;
3032
3033 save_state_to_tss16(ctxt, &tss_seg);
3034
3035 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
3036 &ctxt->exception);
3037 if (ret != X86EMUL_CONTINUE)
3038 return ret;
3039
3040 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
3041 &ctxt->exception);
3042 if (ret != X86EMUL_CONTINUE)
3043 return ret;
3044
3045 if (old_tss_sel != 0xffff) {
3046 tss_seg.prev_task_link = old_tss_sel;
3047
3048 ret = ops->write_std(ctxt, new_tss_base,
3049 &tss_seg.prev_task_link,
3050 sizeof tss_seg.prev_task_link,
3051 &ctxt->exception);
3052 if (ret != X86EMUL_CONTINUE)
3053 return ret;
3054 }
3055
3056 return load_state_from_tss16(ctxt, &tss_seg);
3057}
3058
3059static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
3060 struct tss_segment_32 *tss)
3061{
3062 /* CR3 and ldt selector are not saved intentionally */
3063 tss->eip = ctxt->_eip;
3064 tss->eflags = ctxt->eflags;
3065 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
3066 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
3067 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
3068 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
3069 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
3070 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
3071 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
3072 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
3073
3074 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
3075 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
3076 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
3077 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
3078 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
3079 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
3080}
3081
3082static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
3083 struct tss_segment_32 *tss)
3084{
3085 int ret;
3086 u8 cpl;
3087
3088 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
3089 return emulate_gp(ctxt, 0);
3090 ctxt->_eip = tss->eip;
3091 ctxt->eflags = tss->eflags | 2;
3092
3093 /* General purpose registers */
3094 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
3095 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
3096 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
3097 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
3098 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
3099 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
3100 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
3101 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
3102
3103 /*
3104 * SDM says that segment selectors are loaded before segment
3105 * descriptors. This is important because CPL checks will
3106 * use CS.RPL.
3107 */
3108 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
3109 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
3110 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
3111 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
3112 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
3113 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
3114 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
3115
3116 /*
3117 * If we're switching between Protected Mode and VM86, we need to make
3118 * sure to update the mode before loading the segment descriptors so
3119 * that the selectors are interpreted correctly.
3120 */
3121 if (ctxt->eflags & X86_EFLAGS_VM) {
3122 ctxt->mode = X86EMUL_MODE_VM86;
3123 cpl = 3;
3124 } else {
3125 ctxt->mode = X86EMUL_MODE_PROT32;
3126 cpl = tss->cs & 3;
3127 }
3128
3129 /*
3130 * Now load segment descriptors. If fault happenes at this stage
3131 * it is handled in a context of new task
3132 */
3133 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
3134 cpl, X86_TRANSFER_TASK_SWITCH, NULL);
3135 if (ret != X86EMUL_CONTINUE)
3136 return ret;
3137 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3138 X86_TRANSFER_TASK_SWITCH, NULL);
3139 if (ret != X86EMUL_CONTINUE)
3140 return ret;
3141 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3142 X86_TRANSFER_TASK_SWITCH, NULL);
3143 if (ret != X86EMUL_CONTINUE)
3144 return ret;
3145 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3146 X86_TRANSFER_TASK_SWITCH, NULL);
3147 if (ret != X86EMUL_CONTINUE)
3148 return ret;
3149 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3150 X86_TRANSFER_TASK_SWITCH, NULL);
3151 if (ret != X86EMUL_CONTINUE)
3152 return ret;
3153 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
3154 X86_TRANSFER_TASK_SWITCH, NULL);
3155 if (ret != X86EMUL_CONTINUE)
3156 return ret;
3157 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
3158 X86_TRANSFER_TASK_SWITCH, NULL);
3159
3160 return ret;
3161}
3162
3163static int task_switch_32(struct x86_emulate_ctxt *ctxt,
3164 u16 tss_selector, u16 old_tss_sel,
3165 ulong old_tss_base, struct desc_struct *new_desc)
3166{
3167 const struct x86_emulate_ops *ops = ctxt->ops;
3168 struct tss_segment_32 tss_seg;
3169 int ret;
3170 u32 new_tss_base = get_desc_base(new_desc);
3171 u32 eip_offset = offsetof(struct tss_segment_32, eip);
3172 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
3173
3174 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
3175 &ctxt->exception);
3176 if (ret != X86EMUL_CONTINUE)
3177 return ret;
3178
3179 save_state_to_tss32(ctxt, &tss_seg);
3180
3181 /* Only GP registers and segment selectors are saved */
3182 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
3183 ldt_sel_offset - eip_offset, &ctxt->exception);
3184 if (ret != X86EMUL_CONTINUE)
3185 return ret;
3186
3187 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
3188 &ctxt->exception);
3189 if (ret != X86EMUL_CONTINUE)
3190 return ret;
3191
3192 if (old_tss_sel != 0xffff) {
3193 tss_seg.prev_task_link = old_tss_sel;
3194
3195 ret = ops->write_std(ctxt, new_tss_base,
3196 &tss_seg.prev_task_link,
3197 sizeof tss_seg.prev_task_link,
3198 &ctxt->exception);
3199 if (ret != X86EMUL_CONTINUE)
3200 return ret;
3201 }
3202
3203 return load_state_from_tss32(ctxt, &tss_seg);
3204}
3205
3206static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
3207 u16 tss_selector, int idt_index, int reason,
3208 bool has_error_code, u32 error_code)
3209{
3210 const struct x86_emulate_ops *ops = ctxt->ops;
3211 struct desc_struct curr_tss_desc, next_tss_desc;
3212 int ret;
3213 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
3214 ulong old_tss_base =
3215 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
3216 u32 desc_limit;
3217 ulong desc_addr, dr7;
3218
3219 /* FIXME: old_tss_base == ~0 ? */
3220
3221 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
3222 if (ret != X86EMUL_CONTINUE)
3223 return ret;
3224 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
3225 if (ret != X86EMUL_CONTINUE)
3226 return ret;
3227
3228 /* FIXME: check that next_tss_desc is tss */
3229
3230 /*
3231 * Check privileges. The three cases are task switch caused by...
3232 *
3233 * 1. jmp/call/int to task gate: Check against DPL of the task gate
3234 * 2. Exception/IRQ/iret: No check is performed
3235 * 3. jmp/call to TSS/task-gate: No check is performed since the
3236 * hardware checks it before exiting.
3237 */
3238 if (reason == TASK_SWITCH_GATE) {
3239 if (idt_index != -1) {
3240 /* Software interrupts */
3241 struct desc_struct task_gate_desc;
3242 int dpl;
3243
3244 ret = read_interrupt_descriptor(ctxt, idt_index,
3245 &task_gate_desc);
3246 if (ret != X86EMUL_CONTINUE)
3247 return ret;
3248
3249 dpl = task_gate_desc.dpl;
3250 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
3251 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
3252 }
3253 }
3254
3255 desc_limit = desc_limit_scaled(&next_tss_desc);
3256 if (!next_tss_desc.p ||
3257 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
3258 desc_limit < 0x2b)) {
3259 return emulate_ts(ctxt, tss_selector & 0xfffc);
3260 }
3261
3262 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3263 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
3264 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
3265 }
3266
3267 if (reason == TASK_SWITCH_IRET)
3268 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
3269
3270 /* set back link to prev task only if NT bit is set in eflags
3271 note that old_tss_sel is not used after this point */
3272 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
3273 old_tss_sel = 0xffff;
3274
3275 if (next_tss_desc.type & 8)
3276 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
3277 old_tss_base, &next_tss_desc);
3278 else
3279 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
3280 old_tss_base, &next_tss_desc);
3281 if (ret != X86EMUL_CONTINUE)
3282 return ret;
3283
3284 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
3285 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
3286
3287 if (reason != TASK_SWITCH_IRET) {
3288 next_tss_desc.type |= (1 << 1); /* set busy flag */
3289 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
3290 }
3291
3292 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
3293 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
3294
3295 if (has_error_code) {
3296 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
3297 ctxt->lock_prefix = 0;
3298 ctxt->src.val = (unsigned long) error_code;
3299 ret = em_push(ctxt);
3300 }
3301
3302 ops->get_dr(ctxt, 7, &dr7);
3303 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN));
3304
3305 return ret;
3306}
3307
3308int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
3309 u16 tss_selector, int idt_index, int reason,
3310 bool has_error_code, u32 error_code)
3311{
3312 int rc;
3313
3314 invalidate_registers(ctxt);
3315 ctxt->_eip = ctxt->eip;
3316 ctxt->dst.type = OP_NONE;
3317
3318 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
3319 has_error_code, error_code);
3320
3321 if (rc == X86EMUL_CONTINUE) {
3322 ctxt->eip = ctxt->_eip;
3323 writeback_registers(ctxt);
3324 }
3325
3326 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
3327}
3328
3329static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
3330 struct operand *op)
3331{
3332 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count;
3333
3334 register_address_increment(ctxt, reg, df * op->bytes);
3335 op->addr.mem.ea = register_address(ctxt, reg);
3336}
3337
3338static int em_das(struct x86_emulate_ctxt *ctxt)
3339{
3340 u8 al, old_al;
3341 bool af, cf, old_cf;
3342
3343 cf = ctxt->eflags & X86_EFLAGS_CF;
3344 al = ctxt->dst.val;
3345
3346 old_al = al;
3347 old_cf = cf;
3348 cf = false;
3349 af = ctxt->eflags & X86_EFLAGS_AF;
3350 if ((al & 0x0f) > 9 || af) {
3351 al -= 6;
3352 cf = old_cf | (al >= 250);
3353 af = true;
3354 } else {
3355 af = false;
3356 }
3357 if (old_al > 0x99 || old_cf) {
3358 al -= 0x60;
3359 cf = true;
3360 }
3361
3362 ctxt->dst.val = al;
3363 /* Set PF, ZF, SF */
3364 ctxt->src.type = OP_IMM;
3365 ctxt->src.val = 0;
3366 ctxt->src.bytes = 1;
3367 fastop(ctxt, em_or);
3368 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
3369 if (cf)
3370 ctxt->eflags |= X86_EFLAGS_CF;
3371 if (af)
3372 ctxt->eflags |= X86_EFLAGS_AF;
3373 return X86EMUL_CONTINUE;
3374}
3375
3376static int em_aam(struct x86_emulate_ctxt *ctxt)
3377{
3378 u8 al, ah;
3379
3380 if (ctxt->src.val == 0)
3381 return emulate_de(ctxt);
3382
3383 al = ctxt->dst.val & 0xff;
3384 ah = al / ctxt->src.val;
3385 al %= ctxt->src.val;
3386
3387 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3388
3389 /* Set PF, ZF, SF */
3390 ctxt->src.type = OP_IMM;
3391 ctxt->src.val = 0;
3392 ctxt->src.bytes = 1;
3393 fastop(ctxt, em_or);
3394
3395 return X86EMUL_CONTINUE;
3396}
3397
3398static int em_aad(struct x86_emulate_ctxt *ctxt)
3399{
3400 u8 al = ctxt->dst.val & 0xff;
3401 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3402
3403 al = (al + (ah * ctxt->src.val)) & 0xff;
3404
3405 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3406
3407 /* Set PF, ZF, SF */
3408 ctxt->src.type = OP_IMM;
3409 ctxt->src.val = 0;
3410 ctxt->src.bytes = 1;
3411 fastop(ctxt, em_or);
3412
3413 return X86EMUL_CONTINUE;
3414}
3415
3416static int em_call(struct x86_emulate_ctxt *ctxt)
3417{
3418 int rc;
3419 long rel = ctxt->src.val;
3420
3421 ctxt->src.val = (unsigned long)ctxt->_eip;
3422 rc = jmp_rel(ctxt, rel);
3423 if (rc != X86EMUL_CONTINUE)
3424 return rc;
3425 return em_push(ctxt);
3426}
3427
3428static int em_call_far(struct x86_emulate_ctxt *ctxt)
3429{
3430 u16 sel, old_cs;
3431 ulong old_eip;
3432 int rc;
3433 struct desc_struct old_desc, new_desc;
3434 const struct x86_emulate_ops *ops = ctxt->ops;
3435 int cpl = ctxt->ops->cpl(ctxt);
3436 enum x86emul_mode prev_mode = ctxt->mode;
3437
3438 old_eip = ctxt->_eip;
3439 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
3440
3441 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3442 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
3443 X86_TRANSFER_CALL_JMP, &new_desc);
3444 if (rc != X86EMUL_CONTINUE)
3445 return rc;
3446
3447 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
3448 if (rc != X86EMUL_CONTINUE)
3449 goto fail;
3450
3451 ctxt->src.val = old_cs;
3452 rc = em_push(ctxt);
3453 if (rc != X86EMUL_CONTINUE)
3454 goto fail;
3455
3456 ctxt->src.val = old_eip;
3457 rc = em_push(ctxt);
3458 /* If we failed, we tainted the memory, but the very least we should
3459 restore cs */
3460 if (rc != X86EMUL_CONTINUE) {
3461 pr_warn_once("faulting far call emulation tainted memory\n");
3462 goto fail;
3463 }
3464 return rc;
3465fail:
3466 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
3467 ctxt->mode = prev_mode;
3468 return rc;
3469
3470}
3471
3472static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3473{
3474 int rc;
3475 unsigned long eip;
3476
3477 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3478 if (rc != X86EMUL_CONTINUE)
3479 return rc;
3480 rc = assign_eip_near(ctxt, eip);
3481 if (rc != X86EMUL_CONTINUE)
3482 return rc;
3483 rsp_increment(ctxt, ctxt->src.val);
3484 return X86EMUL_CONTINUE;
3485}
3486
3487static int em_xchg(struct x86_emulate_ctxt *ctxt)
3488{
3489 /* Write back the register source. */
3490 ctxt->src.val = ctxt->dst.val;
3491 write_register_operand(&ctxt->src);
3492
3493 /* Write back the memory destination with implicit LOCK prefix. */
3494 ctxt->dst.val = ctxt->src.orig_val;
3495 ctxt->lock_prefix = 1;
3496 return X86EMUL_CONTINUE;
3497}
3498
3499static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3500{
3501 ctxt->dst.val = ctxt->src2.val;
3502 return fastop(ctxt, em_imul);
3503}
3504
3505static int em_cwd(struct x86_emulate_ctxt *ctxt)
3506{
3507 ctxt->dst.type = OP_REG;
3508 ctxt->dst.bytes = ctxt->src.bytes;
3509 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
3510 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
3511
3512 return X86EMUL_CONTINUE;
3513}
3514
3515static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3516{
3517 u64 tsc = 0;
3518
3519 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
3520 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3521 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
3522 return X86EMUL_CONTINUE;
3523}
3524
3525static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3526{
3527 u64 pmc;
3528
3529 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
3530 return emulate_gp(ctxt, 0);
3531 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3532 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
3533 return X86EMUL_CONTINUE;
3534}
3535
3536static int em_mov(struct x86_emulate_ctxt *ctxt)
3537{
3538 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
3539 return X86EMUL_CONTINUE;
3540}
3541
3542#define FFL(x) bit(X86_FEATURE_##x)
3543
3544static int em_movbe(struct x86_emulate_ctxt *ctxt)
3545{
3546 u32 ebx, ecx, edx, eax = 1;
3547 u16 tmp;
3548
3549 /*
3550 * Check MOVBE is set in the guest-visible CPUID leaf.
3551 */
3552 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3553 if (!(ecx & FFL(MOVBE)))
3554 return emulate_ud(ctxt);
3555
3556 switch (ctxt->op_bytes) {
3557 case 2:
3558 /*
3559 * From MOVBE definition: "...When the operand size is 16 bits,
3560 * the upper word of the destination register remains unchanged
3561 * ..."
3562 *
3563 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3564 * rules so we have to do the operation almost per hand.
3565 */
3566 tmp = (u16)ctxt->src.val;
3567 ctxt->dst.val &= ~0xffffUL;
3568 ctxt->dst.val |= (unsigned long)swab16(tmp);
3569 break;
3570 case 4:
3571 ctxt->dst.val = swab32((u32)ctxt->src.val);
3572 break;
3573 case 8:
3574 ctxt->dst.val = swab64(ctxt->src.val);
3575 break;
3576 default:
3577 BUG();
3578 }
3579 return X86EMUL_CONTINUE;
3580}
3581
3582static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3583{
3584 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3585 return emulate_gp(ctxt, 0);
3586
3587 /* Disable writeback. */
3588 ctxt->dst.type = OP_NONE;
3589 return X86EMUL_CONTINUE;
3590}
3591
3592static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3593{
3594 unsigned long val;
3595
3596 if (ctxt->mode == X86EMUL_MODE_PROT64)
3597 val = ctxt->src.val & ~0ULL;
3598 else
3599 val = ctxt->src.val & ~0U;
3600
3601 /* #UD condition is already handled. */
3602 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3603 return emulate_gp(ctxt, 0);
3604
3605 /* Disable writeback. */
3606 ctxt->dst.type = OP_NONE;
3607 return X86EMUL_CONTINUE;
3608}
3609
3610static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3611{
3612 u64 msr_data;
3613
3614 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3615 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3616 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
3617 return emulate_gp(ctxt, 0);
3618
3619 return X86EMUL_CONTINUE;
3620}
3621
3622static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3623{
3624 u64 msr_data;
3625
3626 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
3627 return emulate_gp(ctxt, 0);
3628
3629 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3630 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
3631 return X86EMUL_CONTINUE;
3632}
3633
3634static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3635{
3636 if (ctxt->modrm_reg > VCPU_SREG_GS)
3637 return emulate_ud(ctxt);
3638
3639 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
3640 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3641 ctxt->dst.bytes = 2;
3642 return X86EMUL_CONTINUE;
3643}
3644
3645static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3646{
3647 u16 sel = ctxt->src.val;
3648
3649 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
3650 return emulate_ud(ctxt);
3651
3652 if (ctxt->modrm_reg == VCPU_SREG_SS)
3653 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3654
3655 /* Disable writeback. */
3656 ctxt->dst.type = OP_NONE;
3657 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
3658}
3659
3660static int em_lldt(struct x86_emulate_ctxt *ctxt)
3661{
3662 u16 sel = ctxt->src.val;
3663
3664 /* Disable writeback. */
3665 ctxt->dst.type = OP_NONE;
3666 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3667}
3668
3669static int em_ltr(struct x86_emulate_ctxt *ctxt)
3670{
3671 u16 sel = ctxt->src.val;
3672
3673 /* Disable writeback. */
3674 ctxt->dst.type = OP_NONE;
3675 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3676}
3677
3678static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3679{
3680 int rc;
3681 ulong linear;
3682
3683 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
3684 if (rc == X86EMUL_CONTINUE)
3685 ctxt->ops->invlpg(ctxt, linear);
3686 /* Disable writeback. */
3687 ctxt->dst.type = OP_NONE;
3688 return X86EMUL_CONTINUE;
3689}
3690
3691static int em_clts(struct x86_emulate_ctxt *ctxt)
3692{
3693 ulong cr0;
3694
3695 cr0 = ctxt->ops->get_cr(ctxt, 0);
3696 cr0 &= ~X86_CR0_TS;
3697 ctxt->ops->set_cr(ctxt, 0, cr0);
3698 return X86EMUL_CONTINUE;
3699}
3700
3701static int em_hypercall(struct x86_emulate_ctxt *ctxt)
3702{
3703 int rc = ctxt->ops->fix_hypercall(ctxt);
3704
3705 if (rc != X86EMUL_CONTINUE)
3706 return rc;
3707
3708 /* Let the processor re-execute the fixed hypercall */
3709 ctxt->_eip = ctxt->eip;
3710 /* Disable writeback. */
3711 ctxt->dst.type = OP_NONE;
3712 return X86EMUL_CONTINUE;
3713}
3714
3715static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3716 void (*get)(struct x86_emulate_ctxt *ctxt,
3717 struct desc_ptr *ptr))
3718{
3719 struct desc_ptr desc_ptr;
3720
3721 if (ctxt->mode == X86EMUL_MODE_PROT64)
3722 ctxt->op_bytes = 8;
3723 get(ctxt, &desc_ptr);
3724 if (ctxt->op_bytes == 2) {
3725 ctxt->op_bytes = 4;
3726 desc_ptr.address &= 0x00ffffff;
3727 }
3728 /* Disable writeback. */
3729 ctxt->dst.type = OP_NONE;
3730 return segmented_write_std(ctxt, ctxt->dst.addr.mem,
3731 &desc_ptr, 2 + ctxt->op_bytes);
3732}
3733
3734static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3735{
3736 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3737}
3738
3739static int em_sidt(struct x86_emulate_ctxt *ctxt)
3740{
3741 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3742}
3743
3744static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
3745{
3746 struct desc_ptr desc_ptr;
3747 int rc;
3748
3749 if (ctxt->mode == X86EMUL_MODE_PROT64)
3750 ctxt->op_bytes = 8;
3751 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3752 &desc_ptr.size, &desc_ptr.address,
3753 ctxt->op_bytes);
3754 if (rc != X86EMUL_CONTINUE)
3755 return rc;
3756 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3757 is_noncanonical_address(desc_ptr.address))
3758 return emulate_gp(ctxt, 0);
3759 if (lgdt)
3760 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3761 else
3762 ctxt->ops->set_idt(ctxt, &desc_ptr);
3763 /* Disable writeback. */
3764 ctxt->dst.type = OP_NONE;
3765 return X86EMUL_CONTINUE;
3766}
3767
3768static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3769{
3770 return em_lgdt_lidt(ctxt, true);
3771}
3772
3773static int em_lidt(struct x86_emulate_ctxt *ctxt)
3774{
3775 return em_lgdt_lidt(ctxt, false);
3776}
3777
3778static int em_smsw(struct x86_emulate_ctxt *ctxt)
3779{
3780 if (ctxt->dst.type == OP_MEM)
3781 ctxt->dst.bytes = 2;
3782 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
3783 return X86EMUL_CONTINUE;
3784}
3785
3786static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3787{
3788 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
3789 | (ctxt->src.val & 0x0f));
3790 ctxt->dst.type = OP_NONE;
3791 return X86EMUL_CONTINUE;
3792}
3793
3794static int em_loop(struct x86_emulate_ctxt *ctxt)
3795{
3796 int rc = X86EMUL_CONTINUE;
3797
3798 register_address_increment(ctxt, VCPU_REGS_RCX, -1);
3799 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
3800 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3801 rc = jmp_rel(ctxt, ctxt->src.val);
3802
3803 return rc;
3804}
3805
3806static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3807{
3808 int rc = X86EMUL_CONTINUE;
3809
3810 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
3811 rc = jmp_rel(ctxt, ctxt->src.val);
3812
3813 return rc;
3814}
3815
3816static int em_in(struct x86_emulate_ctxt *ctxt)
3817{
3818 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3819 &ctxt->dst.val))
3820 return X86EMUL_IO_NEEDED;
3821
3822 return X86EMUL_CONTINUE;
3823}
3824
3825static int em_out(struct x86_emulate_ctxt *ctxt)
3826{
3827 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3828 &ctxt->src.val, 1);
3829 /* Disable writeback. */
3830 ctxt->dst.type = OP_NONE;
3831 return X86EMUL_CONTINUE;
3832}
3833
3834static int em_cli(struct x86_emulate_ctxt *ctxt)
3835{
3836 if (emulator_bad_iopl(ctxt))
3837 return emulate_gp(ctxt, 0);
3838
3839 ctxt->eflags &= ~X86_EFLAGS_IF;
3840 return X86EMUL_CONTINUE;
3841}
3842
3843static int em_sti(struct x86_emulate_ctxt *ctxt)
3844{
3845 if (emulator_bad_iopl(ctxt))
3846 return emulate_gp(ctxt, 0);
3847
3848 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3849 ctxt->eflags |= X86_EFLAGS_IF;
3850 return X86EMUL_CONTINUE;
3851}
3852
3853static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3854{
3855 u32 eax, ebx, ecx, edx;
3856
3857 eax = reg_read(ctxt, VCPU_REGS_RAX);
3858 ecx = reg_read(ctxt, VCPU_REGS_RCX);
3859 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3860 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3861 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3862 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3863 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
3864 return X86EMUL_CONTINUE;
3865}
3866
3867static int em_sahf(struct x86_emulate_ctxt *ctxt)
3868{
3869 u32 flags;
3870
3871 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
3872 X86_EFLAGS_SF;
3873 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3874
3875 ctxt->eflags &= ~0xffUL;
3876 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3877 return X86EMUL_CONTINUE;
3878}
3879
3880static int em_lahf(struct x86_emulate_ctxt *ctxt)
3881{
3882 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3883 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
3884 return X86EMUL_CONTINUE;
3885}
3886
3887static int em_bswap(struct x86_emulate_ctxt *ctxt)
3888{
3889 switch (ctxt->op_bytes) {
3890#ifdef CONFIG_X86_64
3891 case 8:
3892 asm("bswap %0" : "+r"(ctxt->dst.val));
3893 break;
3894#endif
3895 default:
3896 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3897 break;
3898 }
3899 return X86EMUL_CONTINUE;
3900}
3901
3902static int em_clflush(struct x86_emulate_ctxt *ctxt)
3903{
3904 /* emulating clflush regardless of cpuid */
3905 return X86EMUL_CONTINUE;
3906}
3907
3908static int em_movsxd(struct x86_emulate_ctxt *ctxt)
3909{
3910 ctxt->dst.val = (s32) ctxt->src.val;
3911 return X86EMUL_CONTINUE;
3912}
3913
3914static int check_fxsr(struct x86_emulate_ctxt *ctxt)
3915{
3916 u32 eax = 1, ebx, ecx = 0, edx;
3917
3918 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3919 if (!(edx & FFL(FXSR)))
3920 return emulate_ud(ctxt);
3921
3922 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
3923 return emulate_nm(ctxt);
3924
3925 /*
3926 * Don't emulate a case that should never be hit, instead of working
3927 * around a lack of fxsave64/fxrstor64 on old compilers.
3928 */
3929 if (ctxt->mode >= X86EMUL_MODE_PROT64)
3930 return X86EMUL_UNHANDLEABLE;
3931
3932 return X86EMUL_CONTINUE;
3933}
3934
3935/*
3936 * FXSAVE and FXRSTOR have 4 different formats depending on execution mode,
3937 * 1) 16 bit mode
3938 * 2) 32 bit mode
3939 * - like (1), but FIP and FDP (foo) are only 16 bit. At least Intel CPUs
3940 * preserve whole 32 bit values, though, so (1) and (2) are the same wrt.
3941 * save and restore
3942 * 3) 64-bit mode with REX.W prefix
3943 * - like (2), but XMM 8-15 are being saved and restored
3944 * 4) 64-bit mode without REX.W prefix
3945 * - like (3), but FIP and FDP are 64 bit
3946 *
3947 * Emulation uses (3) for (1) and (2) and preserves XMM 8-15 to reach the
3948 * desired result. (4) is not emulated.
3949 *
3950 * Note: Guest and host CPUID.(EAX=07H,ECX=0H):EBX[bit 13] (deprecate FPU CS
3951 * and FPU DS) should match.
3952 */
3953static int em_fxsave(struct x86_emulate_ctxt *ctxt)
3954{
3955 struct fxregs_state fx_state;
3956 size_t size;
3957 int rc;
3958
3959 rc = check_fxsr(ctxt);
3960 if (rc != X86EMUL_CONTINUE)
3961 return rc;
3962
3963 ctxt->ops->get_fpu(ctxt);
3964
3965 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state));
3966
3967 ctxt->ops->put_fpu(ctxt);
3968
3969 if (rc != X86EMUL_CONTINUE)
3970 return rc;
3971
3972 if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR)
3973 size = offsetof(struct fxregs_state, xmm_space[8 * 16/4]);
3974 else
3975 size = offsetof(struct fxregs_state, xmm_space[0]);
3976
3977 return segmented_write_std(ctxt, ctxt->memop.addr.mem, &fx_state, size);
3978}
3979
3980static int fxrstor_fixup(struct x86_emulate_ctxt *ctxt,
3981 struct fxregs_state *new)
3982{
3983 int rc = X86EMUL_CONTINUE;
3984 struct fxregs_state old;
3985
3986 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(old));
3987 if (rc != X86EMUL_CONTINUE)
3988 return rc;
3989
3990 /*
3991 * 64 bit host will restore XMM 8-15, which is not correct on non-64
3992 * bit guests. Load the current values in order to preserve 64 bit
3993 * XMMs after fxrstor.
3994 */
3995#ifdef CONFIG_X86_64
3996 /* XXX: accessing XMM 8-15 very awkwardly */
3997 memcpy(&new->xmm_space[8 * 16/4], &old.xmm_space[8 * 16/4], 8 * 16);
3998#endif
3999
4000 /*
4001 * Hardware doesn't save and restore XMM 0-7 without CR4.OSFXSR, but
4002 * does save and restore MXCSR.
4003 */
4004 if (!(ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))
4005 memcpy(new->xmm_space, old.xmm_space, 8 * 16);
4006
4007 return rc;
4008}
4009
4010static int em_fxrstor(struct x86_emulate_ctxt *ctxt)
4011{
4012 struct fxregs_state fx_state;
4013 int rc;
4014
4015 rc = check_fxsr(ctxt);
4016 if (rc != X86EMUL_CONTINUE)
4017 return rc;
4018
4019 rc = segmented_read_std(ctxt, ctxt->memop.addr.mem, &fx_state, 512);
4020 if (rc != X86EMUL_CONTINUE)
4021 return rc;
4022
4023 if (fx_state.mxcsr >> 16)
4024 return emulate_gp(ctxt, 0);
4025
4026 ctxt->ops->get_fpu(ctxt);
4027
4028 if (ctxt->mode < X86EMUL_MODE_PROT64)
4029 rc = fxrstor_fixup(ctxt, &fx_state);
4030
4031 if (rc == X86EMUL_CONTINUE)
4032 rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state));
4033
4034 ctxt->ops->put_fpu(ctxt);
4035
4036 return rc;
4037}
4038
4039static bool valid_cr(int nr)
4040{
4041 switch (nr) {
4042 case 0:
4043 case 2 ... 4:
4044 case 8:
4045 return true;
4046 default:
4047 return false;
4048 }
4049}
4050
4051static int check_cr_read(struct x86_emulate_ctxt *ctxt)
4052{
4053 if (!valid_cr(ctxt->modrm_reg))
4054 return emulate_ud(ctxt);
4055
4056 return X86EMUL_CONTINUE;
4057}
4058
4059static int check_cr_write(struct x86_emulate_ctxt *ctxt)
4060{
4061 u64 new_val = ctxt->src.val64;
4062 int cr = ctxt->modrm_reg;
4063 u64 efer = 0;
4064
4065 static u64 cr_reserved_bits[] = {
4066 0xffffffff00000000ULL,
4067 0, 0, 0, /* CR3 checked later */
4068 CR4_RESERVED_BITS,
4069 0, 0, 0,
4070 CR8_RESERVED_BITS,
4071 };
4072
4073 if (!valid_cr(cr))
4074 return emulate_ud(ctxt);
4075
4076 if (new_val & cr_reserved_bits[cr])
4077 return emulate_gp(ctxt, 0);
4078
4079 switch (cr) {
4080 case 0: {
4081 u64 cr4;
4082 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
4083 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
4084 return emulate_gp(ctxt, 0);
4085
4086 cr4 = ctxt->ops->get_cr(ctxt, 4);
4087 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
4088
4089 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
4090 !(cr4 & X86_CR4_PAE))
4091 return emulate_gp(ctxt, 0);
4092
4093 break;
4094 }
4095 case 3: {
4096 u64 rsvd = 0;
4097
4098 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
4099 if (efer & EFER_LMA)
4100 rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD;
4101
4102 if (new_val & rsvd)
4103 return emulate_gp(ctxt, 0);
4104
4105 break;
4106 }
4107 case 4: {
4108 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
4109
4110 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
4111 return emulate_gp(ctxt, 0);
4112
4113 break;
4114 }
4115 }
4116
4117 return X86EMUL_CONTINUE;
4118}
4119
4120static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
4121{
4122 unsigned long dr7;
4123
4124 ctxt->ops->get_dr(ctxt, 7, &dr7);
4125
4126 /* Check if DR7.Global_Enable is set */
4127 return dr7 & (1 << 13);
4128}
4129
4130static int check_dr_read(struct x86_emulate_ctxt *ctxt)
4131{
4132 int dr = ctxt->modrm_reg;
4133 u64 cr4;
4134
4135 if (dr > 7)
4136 return emulate_ud(ctxt);
4137
4138 cr4 = ctxt->ops->get_cr(ctxt, 4);
4139 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
4140 return emulate_ud(ctxt);
4141
4142 if (check_dr7_gd(ctxt)) {
4143 ulong dr6;
4144
4145 ctxt->ops->get_dr(ctxt, 6, &dr6);
4146 dr6 &= ~15;
4147 dr6 |= DR6_BD | DR6_RTM;
4148 ctxt->ops->set_dr(ctxt, 6, dr6);
4149 return emulate_db(ctxt);
4150 }
4151
4152 return X86EMUL_CONTINUE;
4153}
4154
4155static int check_dr_write(struct x86_emulate_ctxt *ctxt)
4156{
4157 u64 new_val = ctxt->src.val64;
4158 int dr = ctxt->modrm_reg;
4159
4160 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
4161 return emulate_gp(ctxt, 0);
4162
4163 return check_dr_read(ctxt);
4164}
4165
4166static int check_svme(struct x86_emulate_ctxt *ctxt)
4167{
4168 u64 efer;
4169
4170 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
4171
4172 if (!(efer & EFER_SVME))
4173 return emulate_ud(ctxt);
4174
4175 return X86EMUL_CONTINUE;
4176}
4177
4178static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
4179{
4180 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
4181
4182 /* Valid physical address? */
4183 if (rax & 0xffff000000000000ULL)
4184 return emulate_gp(ctxt, 0);
4185
4186 return check_svme(ctxt);
4187}
4188
4189static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
4190{
4191 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
4192
4193 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
4194 return emulate_ud(ctxt);
4195
4196 return X86EMUL_CONTINUE;
4197}
4198
4199static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
4200{
4201 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
4202 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
4203
4204 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
4205 ctxt->ops->check_pmc(ctxt, rcx))
4206 return emulate_gp(ctxt, 0);
4207
4208 return X86EMUL_CONTINUE;
4209}
4210
4211static int check_perm_in(struct x86_emulate_ctxt *ctxt)
4212{
4213 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
4214 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
4215 return emulate_gp(ctxt, 0);
4216
4217 return X86EMUL_CONTINUE;
4218}
4219
4220static int check_perm_out(struct x86_emulate_ctxt *ctxt)
4221{
4222 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
4223 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
4224 return emulate_gp(ctxt, 0);
4225
4226 return X86EMUL_CONTINUE;
4227}
4228
4229#define D(_y) { .flags = (_y) }
4230#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
4231#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
4232 .intercept = x86_intercept_##_i, .check_perm = (_p) }
4233#define N D(NotImpl)
4234#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
4235#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
4236#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
4237#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
4238#define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) }
4239#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
4240#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
4241#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
4242#define II(_f, _e, _i) \
4243 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
4244#define IIP(_f, _e, _i, _p) \
4245 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
4246 .intercept = x86_intercept_##_i, .check_perm = (_p) }
4247#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
4248
4249#define D2bv(_f) D((_f) | ByteOp), D(_f)
4250#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
4251#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
4252#define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
4253#define I2bvIP(_f, _e, _i, _p) \
4254 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
4255
4256#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
4257 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
4258 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
4259
4260static const struct opcode group7_rm0[] = {
4261 N,
4262 I(SrcNone | Priv | EmulateOnUD, em_hypercall),
4263 N, N, N, N, N, N,
4264};
4265
4266static const struct opcode group7_rm1[] = {
4267 DI(SrcNone | Priv, monitor),
4268 DI(SrcNone | Priv, mwait),
4269 N, N, N, N, N, N,
4270};
4271
4272static const struct opcode group7_rm3[] = {
4273 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
4274 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall),
4275 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
4276 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
4277 DIP(SrcNone | Prot | Priv, stgi, check_svme),
4278 DIP(SrcNone | Prot | Priv, clgi, check_svme),
4279 DIP(SrcNone | Prot | Priv, skinit, check_svme),
4280 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
4281};
4282
4283static const struct opcode group7_rm7[] = {
4284 N,
4285 DIP(SrcNone, rdtscp, check_rdtsc),
4286 N, N, N, N, N, N,
4287};
4288
4289static const struct opcode group1[] = {
4290 F(Lock, em_add),
4291 F(Lock | PageTable, em_or),
4292 F(Lock, em_adc),
4293 F(Lock, em_sbb),
4294 F(Lock | PageTable, em_and),
4295 F(Lock, em_sub),
4296 F(Lock, em_xor),
4297 F(NoWrite, em_cmp),
4298};
4299
4300static const struct opcode group1A[] = {
4301 I(DstMem | SrcNone | Mov | Stack | IncSP, em_pop), N, N, N, N, N, N, N,
4302};
4303
4304static const struct opcode group2[] = {
4305 F(DstMem | ModRM, em_rol),
4306 F(DstMem | ModRM, em_ror),
4307 F(DstMem | ModRM, em_rcl),
4308 F(DstMem | ModRM, em_rcr),
4309 F(DstMem | ModRM, em_shl),
4310 F(DstMem | ModRM, em_shr),
4311 F(DstMem | ModRM, em_shl),
4312 F(DstMem | ModRM, em_sar),
4313};
4314
4315static const struct opcode group3[] = {
4316 F(DstMem | SrcImm | NoWrite, em_test),
4317 F(DstMem | SrcImm | NoWrite, em_test),
4318 F(DstMem | SrcNone | Lock, em_not),
4319 F(DstMem | SrcNone | Lock, em_neg),
4320 F(DstXacc | Src2Mem, em_mul_ex),
4321 F(DstXacc | Src2Mem, em_imul_ex),
4322 F(DstXacc | Src2Mem, em_div_ex),
4323 F(DstXacc | Src2Mem, em_idiv_ex),
4324};
4325
4326static const struct opcode group4[] = {
4327 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
4328 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
4329 N, N, N, N, N, N,
4330};
4331
4332static const struct opcode group5[] = {
4333 F(DstMem | SrcNone | Lock, em_inc),
4334 F(DstMem | SrcNone | Lock, em_dec),
4335 I(SrcMem | NearBranch, em_call_near_abs),
4336 I(SrcMemFAddr | ImplicitOps, em_call_far),
4337 I(SrcMem | NearBranch, em_jmp_abs),
4338 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
4339 I(SrcMem | Stack, em_push), D(Undefined),
4340};
4341
4342static const struct opcode group6[] = {
4343 DI(Prot | DstMem, sldt),
4344 DI(Prot | DstMem, str),
4345 II(Prot | Priv | SrcMem16, em_lldt, lldt),
4346 II(Prot | Priv | SrcMem16, em_ltr, ltr),
4347 N, N, N, N,
4348};
4349
4350static const struct group_dual group7 = { {
4351 II(Mov | DstMem, em_sgdt, sgdt),
4352 II(Mov | DstMem, em_sidt, sidt),
4353 II(SrcMem | Priv, em_lgdt, lgdt),
4354 II(SrcMem | Priv, em_lidt, lidt),
4355 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
4356 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
4357 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
4358}, {
4359 EXT(0, group7_rm0),
4360 EXT(0, group7_rm1),
4361 N, EXT(0, group7_rm3),
4362 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
4363 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
4364 EXT(0, group7_rm7),
4365} };
4366
4367static const struct opcode group8[] = {
4368 N, N, N, N,
4369 F(DstMem | SrcImmByte | NoWrite, em_bt),
4370 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
4371 F(DstMem | SrcImmByte | Lock, em_btr),
4372 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
4373};
4374
4375static const struct group_dual group9 = { {
4376 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
4377}, {
4378 N, N, N, N, N, N, N, N,
4379} };
4380
4381static const struct opcode group11[] = {
4382 I(DstMem | SrcImm | Mov | PageTable, em_mov),
4383 X7(D(Undefined)),
4384};
4385
4386static const struct gprefix pfx_0f_ae_7 = {
4387 I(SrcMem | ByteOp, em_clflush), N, N, N,
4388};
4389
4390static const struct group_dual group15 = { {
4391 I(ModRM | Aligned16, em_fxsave),
4392 I(ModRM | Aligned16, em_fxrstor),
4393 N, N, N, N, N, GP(0, &pfx_0f_ae_7),
4394}, {
4395 N, N, N, N, N, N, N, N,
4396} };
4397
4398static const struct gprefix pfx_0f_6f_0f_7f = {
4399 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
4400};
4401
4402static const struct instr_dual instr_dual_0f_2b = {
4403 I(0, em_mov), N
4404};
4405
4406static const struct gprefix pfx_0f_2b = {
4407 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
4408};
4409
4410static const struct gprefix pfx_0f_28_0f_29 = {
4411 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
4412};
4413
4414static const struct gprefix pfx_0f_e7 = {
4415 N, I(Sse, em_mov), N, N,
4416};
4417
4418static const struct escape escape_d9 = { {
4419 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
4420}, {
4421 /* 0xC0 - 0xC7 */
4422 N, N, N, N, N, N, N, N,
4423 /* 0xC8 - 0xCF */
4424 N, N, N, N, N, N, N, N,
4425 /* 0xD0 - 0xC7 */
4426 N, N, N, N, N, N, N, N,
4427 /* 0xD8 - 0xDF */
4428 N, N, N, N, N, N, N, N,
4429 /* 0xE0 - 0xE7 */
4430 N, N, N, N, N, N, N, N,
4431 /* 0xE8 - 0xEF */
4432 N, N, N, N, N, N, N, N,
4433 /* 0xF0 - 0xF7 */
4434 N, N, N, N, N, N, N, N,
4435 /* 0xF8 - 0xFF */
4436 N, N, N, N, N, N, N, N,
4437} };
4438
4439static const struct escape escape_db = { {
4440 N, N, N, N, N, N, N, N,
4441}, {
4442 /* 0xC0 - 0xC7 */
4443 N, N, N, N, N, N, N, N,
4444 /* 0xC8 - 0xCF */
4445 N, N, N, N, N, N, N, N,
4446 /* 0xD0 - 0xC7 */
4447 N, N, N, N, N, N, N, N,
4448 /* 0xD8 - 0xDF */
4449 N, N, N, N, N, N, N, N,
4450 /* 0xE0 - 0xE7 */
4451 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
4452 /* 0xE8 - 0xEF */
4453 N, N, N, N, N, N, N, N,
4454 /* 0xF0 - 0xF7 */
4455 N, N, N, N, N, N, N, N,
4456 /* 0xF8 - 0xFF */
4457 N, N, N, N, N, N, N, N,
4458} };
4459
4460static const struct escape escape_dd = { {
4461 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
4462}, {
4463 /* 0xC0 - 0xC7 */
4464 N, N, N, N, N, N, N, N,
4465 /* 0xC8 - 0xCF */
4466 N, N, N, N, N, N, N, N,
4467 /* 0xD0 - 0xC7 */
4468 N, N, N, N, N, N, N, N,
4469 /* 0xD8 - 0xDF */
4470 N, N, N, N, N, N, N, N,
4471 /* 0xE0 - 0xE7 */
4472 N, N, N, N, N, N, N, N,
4473 /* 0xE8 - 0xEF */
4474 N, N, N, N, N, N, N, N,
4475 /* 0xF0 - 0xF7 */
4476 N, N, N, N, N, N, N, N,
4477 /* 0xF8 - 0xFF */
4478 N, N, N, N, N, N, N, N,
4479} };
4480
4481static const struct instr_dual instr_dual_0f_c3 = {
4482 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
4483};
4484
4485static const struct mode_dual mode_dual_63 = {
4486 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd)
4487};
4488
4489static const struct opcode opcode_table[256] = {
4490 /* 0x00 - 0x07 */
4491 F6ALU(Lock, em_add),
4492 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
4493 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
4494 /* 0x08 - 0x0F */
4495 F6ALU(Lock | PageTable, em_or),
4496 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
4497 N,
4498 /* 0x10 - 0x17 */
4499 F6ALU(Lock, em_adc),
4500 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
4501 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
4502 /* 0x18 - 0x1F */
4503 F6ALU(Lock, em_sbb),
4504 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
4505 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
4506 /* 0x20 - 0x27 */
4507 F6ALU(Lock | PageTable, em_and), N, N,
4508 /* 0x28 - 0x2F */
4509 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
4510 /* 0x30 - 0x37 */
4511 F6ALU(Lock, em_xor), N, N,
4512 /* 0x38 - 0x3F */
4513 F6ALU(NoWrite, em_cmp), N, N,
4514 /* 0x40 - 0x4F */
4515 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
4516 /* 0x50 - 0x57 */
4517 X8(I(SrcReg | Stack, em_push)),
4518 /* 0x58 - 0x5F */
4519 X8(I(DstReg | Stack, em_pop)),
4520 /* 0x60 - 0x67 */
4521 I(ImplicitOps | Stack | No64, em_pusha),
4522 I(ImplicitOps | Stack | No64, em_popa),
4523 N, MD(ModRM, &mode_dual_63),
4524 N, N, N, N,
4525 /* 0x68 - 0x6F */
4526 I(SrcImm | Mov | Stack, em_push),
4527 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
4528 I(SrcImmByte | Mov | Stack, em_push),
4529 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
4530 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
4531 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
4532 /* 0x70 - 0x7F */
4533 X16(D(SrcImmByte | NearBranch)),
4534 /* 0x80 - 0x87 */
4535 G(ByteOp | DstMem | SrcImm, group1),
4536 G(DstMem | SrcImm, group1),
4537 G(ByteOp | DstMem | SrcImm | No64, group1),
4538 G(DstMem | SrcImmByte, group1),
4539 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
4540 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
4541 /* 0x88 - 0x8F */
4542 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
4543 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
4544 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
4545 D(ModRM | SrcMem | NoAccess | DstReg),
4546 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
4547 G(0, group1A),
4548 /* 0x90 - 0x97 */
4549 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
4550 /* 0x98 - 0x9F */
4551 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
4552 I(SrcImmFAddr | No64, em_call_far), N,
4553 II(ImplicitOps | Stack, em_pushf, pushf),
4554 II(ImplicitOps | Stack, em_popf, popf),
4555 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
4556 /* 0xA0 - 0xA7 */
4557 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
4558 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
4559 I2bv(SrcSI | DstDI | Mov | String, em_mov),
4560 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r),
4561 /* 0xA8 - 0xAF */
4562 F2bv(DstAcc | SrcImm | NoWrite, em_test),
4563 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4564 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
4565 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
4566 /* 0xB0 - 0xB7 */
4567 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
4568 /* 0xB8 - 0xBF */
4569 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
4570 /* 0xC0 - 0xC7 */
4571 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
4572 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4573 I(ImplicitOps | NearBranch, em_ret),
4574 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4575 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
4576 G(ByteOp, group11), G(0, group11),
4577 /* 0xC8 - 0xCF */
4578 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
4579 I(ImplicitOps | SrcImmU16, em_ret_far_imm),
4580 I(ImplicitOps, em_ret_far),
4581 D(ImplicitOps), DI(SrcImmByte, intn),
4582 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
4583 /* 0xD0 - 0xD7 */
4584 G(Src2One | ByteOp, group2), G(Src2One, group2),
4585 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
4586 I(DstAcc | SrcImmUByte | No64, em_aam),
4587 I(DstAcc | SrcImmUByte | No64, em_aad),
4588 F(DstAcc | ByteOp | No64, em_salc),
4589 I(DstAcc | SrcXLat | ByteOp, em_mov),
4590 /* 0xD8 - 0xDF */
4591 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
4592 /* 0xE0 - 0xE7 */
4593 X3(I(SrcImmByte | NearBranch, em_loop)),
4594 I(SrcImmByte | NearBranch, em_jcxz),
4595 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4596 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
4597 /* 0xE8 - 0xEF */
4598 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4599 I(SrcImmFAddr | No64, em_jmp_far),
4600 D(SrcImmByte | ImplicitOps | NearBranch),
4601 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4602 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
4603 /* 0xF0 - 0xF7 */
4604 N, DI(ImplicitOps, icebp), N, N,
4605 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4606 G(ByteOp, group3), G(0, group3),
4607 /* 0xF8 - 0xFF */
4608 D(ImplicitOps), D(ImplicitOps),
4609 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
4610 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4611};
4612
4613static const struct opcode twobyte_table[256] = {
4614 /* 0x00 - 0x0F */
4615 G(0, group6), GD(0, &group7), N, N,
4616 N, I(ImplicitOps | EmulateOnUD, em_syscall),
4617 II(ImplicitOps | Priv, em_clts, clts), N,
4618 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
4619 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
4620 /* 0x10 - 0x1F */
4621 N, N, N, N, N, N, N, N,
4622 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4623 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
4624 /* 0x20 - 0x2F */
4625 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4626 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4627 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4628 check_cr_write),
4629 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4630 check_dr_write),
4631 N, N, N, N,
4632 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4633 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
4634 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
4635 N, N, N, N,
4636 /* 0x30 - 0x3F */
4637 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
4638 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
4639 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
4640 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
4641 I(ImplicitOps | EmulateOnUD, em_sysenter),
4642 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
4643 N, N,
4644 N, N, N, N, N, N, N, N,
4645 /* 0x40 - 0x4F */
4646 X16(D(DstReg | SrcMem | ModRM)),
4647 /* 0x50 - 0x5F */
4648 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4649 /* 0x60 - 0x6F */
4650 N, N, N, N,
4651 N, N, N, N,
4652 N, N, N, N,
4653 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
4654 /* 0x70 - 0x7F */
4655 N, N, N, N,
4656 N, N, N, N,
4657 N, N, N, N,
4658 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
4659 /* 0x80 - 0x8F */
4660 X16(D(SrcImm | NearBranch)),
4661 /* 0x90 - 0x9F */
4662 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
4663 /* 0xA0 - 0xA7 */
4664 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
4665 II(ImplicitOps, em_cpuid, cpuid),
4666 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
4667 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4668 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
4669 /* 0xA8 - 0xAF */
4670 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
4671 II(EmulateOnUD | ImplicitOps, em_rsm, rsm),
4672 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
4673 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4674 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4675 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
4676 /* 0xB0 - 0xB7 */
4677 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg),
4678 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
4679 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
4680 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4681 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
4682 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
4683 /* 0xB8 - 0xBF */
4684 N, N,
4685 G(BitOp, group8),
4686 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4687 I(DstReg | SrcMem | ModRM, em_bsf_c),
4688 I(DstReg | SrcMem | ModRM, em_bsr_c),
4689 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
4690 /* 0xC0 - 0xC7 */
4691 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
4692 N, ID(0, &instr_dual_0f_c3),
4693 N, N, N, GD(0, &group9),
4694 /* 0xC8 - 0xCF */
4695 X8(I(DstReg, em_bswap)),
4696 /* 0xD0 - 0xDF */
4697 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4698 /* 0xE0 - 0xEF */
4699 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4700 N, N, N, N, N, N, N, N,
4701 /* 0xF0 - 0xFF */
4702 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4703};
4704
4705static const struct instr_dual instr_dual_0f_38_f0 = {
4706 I(DstReg | SrcMem | Mov, em_movbe), N
4707};
4708
4709static const struct instr_dual instr_dual_0f_38_f1 = {
4710 I(DstMem | SrcReg | Mov, em_movbe), N
4711};
4712
4713static const struct gprefix three_byte_0f_38_f0 = {
4714 ID(0, &instr_dual_0f_38_f0), N, N, N
4715};
4716
4717static const struct gprefix three_byte_0f_38_f1 = {
4718 ID(0, &instr_dual_0f_38_f1), N, N, N
4719};
4720
4721/*
4722 * Insns below are selected by the prefix which indexed by the third opcode
4723 * byte.
4724 */
4725static const struct opcode opcode_map_0f_38[256] = {
4726 /* 0x00 - 0x7f */
4727 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4728 /* 0x80 - 0xef */
4729 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4730 /* 0xf0 - 0xf1 */
4731 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
4732 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
4733 /* 0xf2 - 0xff */
4734 N, N, X4(N), X8(N)
4735};
4736
4737#undef D
4738#undef N
4739#undef G
4740#undef GD
4741#undef I
4742#undef GP
4743#undef EXT
4744#undef MD
4745#undef ID
4746
4747#undef D2bv
4748#undef D2bvIP
4749#undef I2bv
4750#undef I2bvIP
4751#undef I6ALU
4752
4753static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
4754{
4755 unsigned size;
4756
4757 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4758 if (size == 8)
4759 size = 4;
4760 return size;
4761}
4762
4763static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4764 unsigned size, bool sign_extension)
4765{
4766 int rc = X86EMUL_CONTINUE;
4767
4768 op->type = OP_IMM;
4769 op->bytes = size;
4770 op->addr.mem.ea = ctxt->_eip;
4771 /* NB. Immediates are sign-extended as necessary. */
4772 switch (op->bytes) {
4773 case 1:
4774 op->val = insn_fetch(s8, ctxt);
4775 break;
4776 case 2:
4777 op->val = insn_fetch(s16, ctxt);
4778 break;
4779 case 4:
4780 op->val = insn_fetch(s32, ctxt);
4781 break;
4782 case 8:
4783 op->val = insn_fetch(s64, ctxt);
4784 break;
4785 }
4786 if (!sign_extension) {
4787 switch (op->bytes) {
4788 case 1:
4789 op->val &= 0xff;
4790 break;
4791 case 2:
4792 op->val &= 0xffff;
4793 break;
4794 case 4:
4795 op->val &= 0xffffffff;
4796 break;
4797 }
4798 }
4799done:
4800 return rc;
4801}
4802
4803static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4804 unsigned d)
4805{
4806 int rc = X86EMUL_CONTINUE;
4807
4808 switch (d) {
4809 case OpReg:
4810 decode_register_operand(ctxt, op);
4811 break;
4812 case OpImmUByte:
4813 rc = decode_imm(ctxt, op, 1, false);
4814 break;
4815 case OpMem:
4816 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4817 mem_common:
4818 *op = ctxt->memop;
4819 ctxt->memopp = op;
4820 if (ctxt->d & BitOp)
4821 fetch_bit_operand(ctxt);
4822 op->orig_val = op->val;
4823 break;
4824 case OpMem64:
4825 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
4826 goto mem_common;
4827 case OpAcc:
4828 op->type = OP_REG;
4829 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4830 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4831 fetch_register_operand(op);
4832 op->orig_val = op->val;
4833 break;
4834 case OpAccLo:
4835 op->type = OP_REG;
4836 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4837 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4838 fetch_register_operand(op);
4839 op->orig_val = op->val;
4840 break;
4841 case OpAccHi:
4842 if (ctxt->d & ByteOp) {
4843 op->type = OP_NONE;
4844 break;
4845 }
4846 op->type = OP_REG;
4847 op->bytes = ctxt->op_bytes;
4848 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4849 fetch_register_operand(op);
4850 op->orig_val = op->val;
4851 break;
4852 case OpDI:
4853 op->type = OP_MEM;
4854 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4855 op->addr.mem.ea =
4856 register_address(ctxt, VCPU_REGS_RDI);
4857 op->addr.mem.seg = VCPU_SREG_ES;
4858 op->val = 0;
4859 op->count = 1;
4860 break;
4861 case OpDX:
4862 op->type = OP_REG;
4863 op->bytes = 2;
4864 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4865 fetch_register_operand(op);
4866 break;
4867 case OpCL:
4868 op->type = OP_IMM;
4869 op->bytes = 1;
4870 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4871 break;
4872 case OpImmByte:
4873 rc = decode_imm(ctxt, op, 1, true);
4874 break;
4875 case OpOne:
4876 op->type = OP_IMM;
4877 op->bytes = 1;
4878 op->val = 1;
4879 break;
4880 case OpImm:
4881 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4882 break;
4883 case OpImm64:
4884 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4885 break;
4886 case OpMem8:
4887 ctxt->memop.bytes = 1;
4888 if (ctxt->memop.type == OP_REG) {
4889 ctxt->memop.addr.reg = decode_register(ctxt,
4890 ctxt->modrm_rm, true);
4891 fetch_register_operand(&ctxt->memop);
4892 }
4893 goto mem_common;
4894 case OpMem16:
4895 ctxt->memop.bytes = 2;
4896 goto mem_common;
4897 case OpMem32:
4898 ctxt->memop.bytes = 4;
4899 goto mem_common;
4900 case OpImmU16:
4901 rc = decode_imm(ctxt, op, 2, false);
4902 break;
4903 case OpImmU:
4904 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4905 break;
4906 case OpSI:
4907 op->type = OP_MEM;
4908 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4909 op->addr.mem.ea =
4910 register_address(ctxt, VCPU_REGS_RSI);
4911 op->addr.mem.seg = ctxt->seg_override;
4912 op->val = 0;
4913 op->count = 1;
4914 break;
4915 case OpXLat:
4916 op->type = OP_MEM;
4917 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4918 op->addr.mem.ea =
4919 address_mask(ctxt,
4920 reg_read(ctxt, VCPU_REGS_RBX) +
4921 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
4922 op->addr.mem.seg = ctxt->seg_override;
4923 op->val = 0;
4924 break;
4925 case OpImmFAddr:
4926 op->type = OP_IMM;
4927 op->addr.mem.ea = ctxt->_eip;
4928 op->bytes = ctxt->op_bytes + 2;
4929 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4930 break;
4931 case OpMemFAddr:
4932 ctxt->memop.bytes = ctxt->op_bytes + 2;
4933 goto mem_common;
4934 case OpES:
4935 op->type = OP_IMM;
4936 op->val = VCPU_SREG_ES;
4937 break;
4938 case OpCS:
4939 op->type = OP_IMM;
4940 op->val = VCPU_SREG_CS;
4941 break;
4942 case OpSS:
4943 op->type = OP_IMM;
4944 op->val = VCPU_SREG_SS;
4945 break;
4946 case OpDS:
4947 op->type = OP_IMM;
4948 op->val = VCPU_SREG_DS;
4949 break;
4950 case OpFS:
4951 op->type = OP_IMM;
4952 op->val = VCPU_SREG_FS;
4953 break;
4954 case OpGS:
4955 op->type = OP_IMM;
4956 op->val = VCPU_SREG_GS;
4957 break;
4958 case OpImplicit:
4959 /* Special instructions do their own operand decoding. */
4960 default:
4961 op->type = OP_NONE; /* Disable writeback. */
4962 break;
4963 }
4964
4965done:
4966 return rc;
4967}
4968
4969int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
4970{
4971 int rc = X86EMUL_CONTINUE;
4972 int mode = ctxt->mode;
4973 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
4974 bool op_prefix = false;
4975 bool has_seg_override = false;
4976 struct opcode opcode;
4977
4978 ctxt->memop.type = OP_NONE;
4979 ctxt->memopp = NULL;
4980 ctxt->_eip = ctxt->eip;
4981 ctxt->fetch.ptr = ctxt->fetch.data;
4982 ctxt->fetch.end = ctxt->fetch.data + insn_len;
4983 ctxt->opcode_len = 1;
4984 if (insn_len > 0)
4985 memcpy(ctxt->fetch.data, insn, insn_len);
4986 else {
4987 rc = __do_insn_fetch_bytes(ctxt, 1);
4988 if (rc != X86EMUL_CONTINUE)
4989 return rc;
4990 }
4991
4992 switch (mode) {
4993 case X86EMUL_MODE_REAL:
4994 case X86EMUL_MODE_VM86:
4995 case X86EMUL_MODE_PROT16:
4996 def_op_bytes = def_ad_bytes = 2;
4997 break;
4998 case X86EMUL_MODE_PROT32:
4999 def_op_bytes = def_ad_bytes = 4;
5000 break;
5001#ifdef CONFIG_X86_64
5002 case X86EMUL_MODE_PROT64:
5003 def_op_bytes = 4;
5004 def_ad_bytes = 8;
5005 break;
5006#endif
5007 default:
5008 return EMULATION_FAILED;
5009 }
5010
5011 ctxt->op_bytes = def_op_bytes;
5012 ctxt->ad_bytes = def_ad_bytes;
5013
5014 /* Legacy prefixes. */
5015 for (;;) {
5016 switch (ctxt->b = insn_fetch(u8, ctxt)) {
5017 case 0x66: /* operand-size override */
5018 op_prefix = true;
5019 /* switch between 2/4 bytes */
5020 ctxt->op_bytes = def_op_bytes ^ 6;
5021 break;
5022 case 0x67: /* address-size override */
5023 if (mode == X86EMUL_MODE_PROT64)
5024 /* switch between 4/8 bytes */
5025 ctxt->ad_bytes = def_ad_bytes ^ 12;
5026 else
5027 /* switch between 2/4 bytes */
5028 ctxt->ad_bytes = def_ad_bytes ^ 6;
5029 break;
5030 case 0x26: /* ES override */
5031 case 0x2e: /* CS override */
5032 case 0x36: /* SS override */
5033 case 0x3e: /* DS override */
5034 has_seg_override = true;
5035 ctxt->seg_override = (ctxt->b >> 3) & 3;
5036 break;
5037 case 0x64: /* FS override */
5038 case 0x65: /* GS override */
5039 has_seg_override = true;
5040 ctxt->seg_override = ctxt->b & 7;
5041 break;
5042 case 0x40 ... 0x4f: /* REX */
5043 if (mode != X86EMUL_MODE_PROT64)
5044 goto done_prefixes;
5045 ctxt->rex_prefix = ctxt->b;
5046 continue;
5047 case 0xf0: /* LOCK */
5048 ctxt->lock_prefix = 1;
5049 break;
5050 case 0xf2: /* REPNE/REPNZ */
5051 case 0xf3: /* REP/REPE/REPZ */
5052 ctxt->rep_prefix = ctxt->b;
5053 break;
5054 default:
5055 goto done_prefixes;
5056 }
5057
5058 /* Any legacy prefix after a REX prefix nullifies its effect. */
5059
5060 ctxt->rex_prefix = 0;
5061 }
5062
5063done_prefixes:
5064
5065 /* REX prefix. */
5066 if (ctxt->rex_prefix & 8)
5067 ctxt->op_bytes = 8; /* REX.W */
5068
5069 /* Opcode byte(s). */
5070 opcode = opcode_table[ctxt->b];
5071 /* Two-byte opcode? */
5072 if (ctxt->b == 0x0f) {
5073 ctxt->opcode_len = 2;
5074 ctxt->b = insn_fetch(u8, ctxt);
5075 opcode = twobyte_table[ctxt->b];
5076
5077 /* 0F_38 opcode map */
5078 if (ctxt->b == 0x38) {
5079 ctxt->opcode_len = 3;
5080 ctxt->b = insn_fetch(u8, ctxt);
5081 opcode = opcode_map_0f_38[ctxt->b];
5082 }
5083 }
5084 ctxt->d = opcode.flags;
5085
5086 if (ctxt->d & ModRM)
5087 ctxt->modrm = insn_fetch(u8, ctxt);
5088
5089 /* vex-prefix instructions are not implemented */
5090 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
5091 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
5092 ctxt->d = NotImpl;
5093 }
5094
5095 while (ctxt->d & GroupMask) {
5096 switch (ctxt->d & GroupMask) {
5097 case Group:
5098 goffset = (ctxt->modrm >> 3) & 7;
5099 opcode = opcode.u.group[goffset];
5100 break;
5101 case GroupDual:
5102 goffset = (ctxt->modrm >> 3) & 7;
5103 if ((ctxt->modrm >> 6) == 3)
5104 opcode = opcode.u.gdual->mod3[goffset];
5105 else
5106 opcode = opcode.u.gdual->mod012[goffset];
5107 break;
5108 case RMExt:
5109 goffset = ctxt->modrm & 7;
5110 opcode = opcode.u.group[goffset];
5111 break;
5112 case Prefix:
5113 if (ctxt->rep_prefix && op_prefix)
5114 return EMULATION_FAILED;
5115 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
5116 switch (simd_prefix) {
5117 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
5118 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
5119 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
5120 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
5121 }
5122 break;
5123 case Escape:
5124 if (ctxt->modrm > 0xbf)
5125 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
5126 else
5127 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
5128 break;
5129 case InstrDual:
5130 if ((ctxt->modrm >> 6) == 3)
5131 opcode = opcode.u.idual->mod3;
5132 else
5133 opcode = opcode.u.idual->mod012;
5134 break;
5135 case ModeDual:
5136 if (ctxt->mode == X86EMUL_MODE_PROT64)
5137 opcode = opcode.u.mdual->mode64;
5138 else
5139 opcode = opcode.u.mdual->mode32;
5140 break;
5141 default:
5142 return EMULATION_FAILED;
5143 }
5144
5145 ctxt->d &= ~(u64)GroupMask;
5146 ctxt->d |= opcode.flags;
5147 }
5148
5149 /* Unrecognised? */
5150 if (ctxt->d == 0)
5151 return EMULATION_FAILED;
5152
5153 ctxt->execute = opcode.u.execute;
5154
5155 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
5156 return EMULATION_FAILED;
5157
5158 if (unlikely(ctxt->d &
5159 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
5160 No16))) {
5161 /*
5162 * These are copied unconditionally here, and checked unconditionally
5163 * in x86_emulate_insn.
5164 */
5165 ctxt->check_perm = opcode.check_perm;
5166 ctxt->intercept = opcode.intercept;
5167
5168 if (ctxt->d & NotImpl)
5169 return EMULATION_FAILED;
5170
5171 if (mode == X86EMUL_MODE_PROT64) {
5172 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
5173 ctxt->op_bytes = 8;
5174 else if (ctxt->d & NearBranch)
5175 ctxt->op_bytes = 8;
5176 }
5177
5178 if (ctxt->d & Op3264) {
5179 if (mode == X86EMUL_MODE_PROT64)
5180 ctxt->op_bytes = 8;
5181 else
5182 ctxt->op_bytes = 4;
5183 }
5184
5185 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
5186 ctxt->op_bytes = 4;
5187
5188 if (ctxt->d & Sse)
5189 ctxt->op_bytes = 16;
5190 else if (ctxt->d & Mmx)
5191 ctxt->op_bytes = 8;
5192 }
5193
5194 /* ModRM and SIB bytes. */
5195 if (ctxt->d & ModRM) {
5196 rc = decode_modrm(ctxt, &ctxt->memop);
5197 if (!has_seg_override) {
5198 has_seg_override = true;
5199 ctxt->seg_override = ctxt->modrm_seg;
5200 }
5201 } else if (ctxt->d & MemAbs)
5202 rc = decode_abs(ctxt, &ctxt->memop);
5203 if (rc != X86EMUL_CONTINUE)
5204 goto done;
5205
5206 if (!has_seg_override)
5207 ctxt->seg_override = VCPU_SREG_DS;
5208
5209 ctxt->memop.addr.mem.seg = ctxt->seg_override;
5210
5211 /*
5212 * Decode and fetch the source operand: register, memory
5213 * or immediate.
5214 */
5215 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
5216 if (rc != X86EMUL_CONTINUE)
5217 goto done;
5218
5219 /*
5220 * Decode and fetch the second source operand: register, memory
5221 * or immediate.
5222 */
5223 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
5224 if (rc != X86EMUL_CONTINUE)
5225 goto done;
5226
5227 /* Decode and fetch the destination operand: register or memory. */
5228 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
5229
5230 if (ctxt->rip_relative && likely(ctxt->memopp))
5231 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
5232 ctxt->memopp->addr.mem.ea + ctxt->_eip);
5233
5234done:
5235 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
5236}
5237
5238bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
5239{
5240 return ctxt->d & PageTable;
5241}
5242
5243static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
5244{
5245 /* The second termination condition only applies for REPE
5246 * and REPNE. Test if the repeat string operation prefix is
5247 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
5248 * corresponding termination condition according to:
5249 * - if REPE/REPZ and ZF = 0 then done
5250 * - if REPNE/REPNZ and ZF = 1 then done
5251 */
5252 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
5253 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
5254 && (((ctxt->rep_prefix == REPE_PREFIX) &&
5255 ((ctxt->eflags & X86_EFLAGS_ZF) == 0))
5256 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
5257 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF))))
5258 return true;
5259
5260 return false;
5261}
5262
5263static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
5264{
5265 int rc;
5266
5267 ctxt->ops->get_fpu(ctxt);
5268 rc = asm_safe("fwait");
5269 ctxt->ops->put_fpu(ctxt);
5270
5271 if (unlikely(rc != X86EMUL_CONTINUE))
5272 return emulate_exception(ctxt, MF_VECTOR, 0, false);
5273
5274 return X86EMUL_CONTINUE;
5275}
5276
5277static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
5278 struct operand *op)
5279{
5280 if (op->type == OP_MM)
5281 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
5282}
5283
5284static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
5285{
5286 register void *__sp asm(_ASM_SP);
5287 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
5288
5289 if (!(ctxt->d & ByteOp))
5290 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
5291
5292 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
5293 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
5294 [fastop]"+S"(fop), "+r"(__sp)
5295 : "c"(ctxt->src2.val));
5296
5297 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
5298 if (!fop) /* exception is returned in fop variable */
5299 return emulate_de(ctxt);
5300 return X86EMUL_CONTINUE;
5301}
5302
5303void init_decode_cache(struct x86_emulate_ctxt *ctxt)
5304{
5305 memset(&ctxt->rip_relative, 0,
5306 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
5307
5308 ctxt->io_read.pos = 0;
5309 ctxt->io_read.end = 0;
5310 ctxt->mem_read.end = 0;
5311}
5312
5313int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
5314{
5315 const struct x86_emulate_ops *ops = ctxt->ops;
5316 int rc = X86EMUL_CONTINUE;
5317 int saved_dst_type = ctxt->dst.type;
5318
5319 ctxt->mem_read.pos = 0;
5320
5321 /* LOCK prefix is allowed only with some instructions */
5322 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
5323 rc = emulate_ud(ctxt);
5324 goto done;
5325 }
5326
5327 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
5328 rc = emulate_ud(ctxt);
5329 goto done;
5330 }
5331
5332 if (unlikely(ctxt->d &
5333 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
5334 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
5335 (ctxt->d & Undefined)) {
5336 rc = emulate_ud(ctxt);
5337 goto done;
5338 }
5339
5340 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
5341 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
5342 rc = emulate_ud(ctxt);
5343 goto done;
5344 }
5345
5346 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
5347 rc = emulate_nm(ctxt);
5348 goto done;
5349 }
5350
5351 if (ctxt->d & Mmx) {
5352 rc = flush_pending_x87_faults(ctxt);
5353 if (rc != X86EMUL_CONTINUE)
5354 goto done;
5355 /*
5356 * Now that we know the fpu is exception safe, we can fetch
5357 * operands from it.
5358 */
5359 fetch_possible_mmx_operand(ctxt, &ctxt->src);
5360 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
5361 if (!(ctxt->d & Mov))
5362 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
5363 }
5364
5365 if (unlikely(ctxt->emul_flags & X86EMUL_GUEST_MASK) && ctxt->intercept) {
5366 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5367 X86_ICPT_PRE_EXCEPT);
5368 if (rc != X86EMUL_CONTINUE)
5369 goto done;
5370 }
5371
5372 /* Instruction can only be executed in protected mode */
5373 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
5374 rc = emulate_ud(ctxt);
5375 goto done;
5376 }
5377
5378 /* Privileged instruction can be executed only in CPL=0 */
5379 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
5380 if (ctxt->d & PrivUD)
5381 rc = emulate_ud(ctxt);
5382 else
5383 rc = emulate_gp(ctxt, 0);
5384 goto done;
5385 }
5386
5387 /* Do instruction specific permission checks */
5388 if (ctxt->d & CheckPerm) {
5389 rc = ctxt->check_perm(ctxt);
5390 if (rc != X86EMUL_CONTINUE)
5391 goto done;
5392 }
5393
5394 if (unlikely(ctxt->emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
5395 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5396 X86_ICPT_POST_EXCEPT);
5397 if (rc != X86EMUL_CONTINUE)
5398 goto done;
5399 }
5400
5401 if (ctxt->rep_prefix && (ctxt->d & String)) {
5402 /* All REP prefixes have the same first termination condition */
5403 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
5404 string_registers_quirk(ctxt);
5405 ctxt->eip = ctxt->_eip;
5406 ctxt->eflags &= ~X86_EFLAGS_RF;
5407 goto done;
5408 }
5409 }
5410 }
5411
5412 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
5413 rc = segmented_read(ctxt, ctxt->src.addr.mem,
5414 ctxt->src.valptr, ctxt->src.bytes);
5415 if (rc != X86EMUL_CONTINUE)
5416 goto done;
5417 ctxt->src.orig_val64 = ctxt->src.val64;
5418 }
5419
5420 if (ctxt->src2.type == OP_MEM) {
5421 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
5422 &ctxt->src2.val, ctxt->src2.bytes);
5423 if (rc != X86EMUL_CONTINUE)
5424 goto done;
5425 }
5426
5427 if ((ctxt->d & DstMask) == ImplicitOps)
5428 goto special_insn;
5429
5430
5431 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
5432 /* optimisation - avoid slow emulated read if Mov */
5433 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
5434 &ctxt->dst.val, ctxt->dst.bytes);
5435 if (rc != X86EMUL_CONTINUE) {
5436 if (!(ctxt->d & NoWrite) &&
5437 rc == X86EMUL_PROPAGATE_FAULT &&
5438 ctxt->exception.vector == PF_VECTOR)
5439 ctxt->exception.error_code |= PFERR_WRITE_MASK;
5440 goto done;
5441 }
5442 }
5443 /* Copy full 64-bit value for CMPXCHG8B. */
5444 ctxt->dst.orig_val64 = ctxt->dst.val64;
5445
5446special_insn:
5447
5448 if (unlikely(ctxt->emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
5449 rc = emulator_check_intercept(ctxt, ctxt->intercept,
5450 X86_ICPT_POST_MEMACCESS);
5451 if (rc != X86EMUL_CONTINUE)
5452 goto done;
5453 }
5454
5455 if (ctxt->rep_prefix && (ctxt->d & String))
5456 ctxt->eflags |= X86_EFLAGS_RF;
5457 else
5458 ctxt->eflags &= ~X86_EFLAGS_RF;
5459
5460 if (ctxt->execute) {
5461 if (ctxt->d & Fastop) {
5462 void (*fop)(struct fastop *) = (void *)ctxt->execute;
5463 rc = fastop(ctxt, fop);
5464 if (rc != X86EMUL_CONTINUE)
5465 goto done;
5466 goto writeback;
5467 }
5468 rc = ctxt->execute(ctxt);
5469 if (rc != X86EMUL_CONTINUE)
5470 goto done;
5471 goto writeback;
5472 }
5473
5474 if (ctxt->opcode_len == 2)
5475 goto twobyte_insn;
5476 else if (ctxt->opcode_len == 3)
5477 goto threebyte_insn;
5478
5479 switch (ctxt->b) {
5480 case 0x70 ... 0x7f: /* jcc (short) */
5481 if (test_cc(ctxt->b, ctxt->eflags))
5482 rc = jmp_rel(ctxt, ctxt->src.val);
5483 break;
5484 case 0x8d: /* lea r16/r32, m */
5485 ctxt->dst.val = ctxt->src.addr.mem.ea;
5486 break;
5487 case 0x90 ... 0x97: /* nop / xchg reg, rax */
5488 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
5489 ctxt->dst.type = OP_NONE;
5490 else
5491 rc = em_xchg(ctxt);
5492 break;
5493 case 0x98: /* cbw/cwde/cdqe */
5494 switch (ctxt->op_bytes) {
5495 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
5496 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
5497 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
5498 }
5499 break;
5500 case 0xcc: /* int3 */
5501 rc = emulate_int(ctxt, 3);
5502 break;
5503 case 0xcd: /* int n */
5504 rc = emulate_int(ctxt, ctxt->src.val);
5505 break;
5506 case 0xce: /* into */
5507 if (ctxt->eflags & X86_EFLAGS_OF)
5508 rc = emulate_int(ctxt, 4);
5509 break;
5510 case 0xe9: /* jmp rel */
5511 case 0xeb: /* jmp rel short */
5512 rc = jmp_rel(ctxt, ctxt->src.val);
5513 ctxt->dst.type = OP_NONE; /* Disable writeback. */
5514 break;
5515 case 0xf4: /* hlt */
5516 ctxt->ops->halt(ctxt);
5517 break;
5518 case 0xf5: /* cmc */
5519 /* complement carry flag from eflags reg */
5520 ctxt->eflags ^= X86_EFLAGS_CF;
5521 break;
5522 case 0xf8: /* clc */
5523 ctxt->eflags &= ~X86_EFLAGS_CF;
5524 break;
5525 case 0xf9: /* stc */
5526 ctxt->eflags |= X86_EFLAGS_CF;
5527 break;
5528 case 0xfc: /* cld */
5529 ctxt->eflags &= ~X86_EFLAGS_DF;
5530 break;
5531 case 0xfd: /* std */
5532 ctxt->eflags |= X86_EFLAGS_DF;
5533 break;
5534 default:
5535 goto cannot_emulate;
5536 }
5537
5538 if (rc != X86EMUL_CONTINUE)
5539 goto done;
5540
5541writeback:
5542 if (ctxt->d & SrcWrite) {
5543 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
5544 rc = writeback(ctxt, &ctxt->src);
5545 if (rc != X86EMUL_CONTINUE)
5546 goto done;
5547 }
5548 if (!(ctxt->d & NoWrite)) {
5549 rc = writeback(ctxt, &ctxt->dst);
5550 if (rc != X86EMUL_CONTINUE)
5551 goto done;
5552 }
5553
5554 /*
5555 * restore dst type in case the decoding will be reused
5556 * (happens for string instruction )
5557 */
5558 ctxt->dst.type = saved_dst_type;
5559
5560 if ((ctxt->d & SrcMask) == SrcSI)
5561 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
5562
5563 if ((ctxt->d & DstMask) == DstDI)
5564 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
5565
5566 if (ctxt->rep_prefix && (ctxt->d & String)) {
5567 unsigned int count;
5568 struct read_cache *r = &ctxt->io_read;
5569 if ((ctxt->d & SrcMask) == SrcSI)
5570 count = ctxt->src.count;
5571 else
5572 count = ctxt->dst.count;
5573 register_address_increment(ctxt, VCPU_REGS_RCX, -count);
5574
5575 if (!string_insn_completed(ctxt)) {
5576 /*
5577 * Re-enter guest when pio read ahead buffer is empty
5578 * or, if it is not used, after each 1024 iteration.
5579 */
5580 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
5581 (r->end == 0 || r->end != r->pos)) {
5582 /*
5583 * Reset read cache. Usually happens before
5584 * decode, but since instruction is restarted
5585 * we have to do it here.
5586 */
5587 ctxt->mem_read.end = 0;
5588 writeback_registers(ctxt);
5589 return EMULATION_RESTART;
5590 }
5591 goto done; /* skip rip writeback */
5592 }
5593 ctxt->eflags &= ~X86_EFLAGS_RF;
5594 }
5595
5596 ctxt->eip = ctxt->_eip;
5597
5598done:
5599 if (rc == X86EMUL_PROPAGATE_FAULT) {
5600 WARN_ON(ctxt->exception.vector > 0x1f);
5601 ctxt->have_exception = true;
5602 }
5603 if (rc == X86EMUL_INTERCEPTED)
5604 return EMULATION_INTERCEPTED;
5605
5606 if (rc == X86EMUL_CONTINUE)
5607 writeback_registers(ctxt);
5608
5609 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
5610
5611twobyte_insn:
5612 switch (ctxt->b) {
5613 case 0x09: /* wbinvd */
5614 (ctxt->ops->wbinvd)(ctxt);
5615 break;
5616 case 0x08: /* invd */
5617 case 0x0d: /* GrpP (prefetch) */
5618 case 0x18: /* Grp16 (prefetch/nop) */
5619 case 0x1f: /* nop */
5620 break;
5621 case 0x20: /* mov cr, reg */
5622 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
5623 break;
5624 case 0x21: /* mov from dr to reg */
5625 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
5626 break;
5627 case 0x40 ... 0x4f: /* cmov */
5628 if (test_cc(ctxt->b, ctxt->eflags))
5629 ctxt->dst.val = ctxt->src.val;
5630 else if (ctxt->op_bytes != 4)
5631 ctxt->dst.type = OP_NONE; /* no writeback */
5632 break;
5633 case 0x80 ... 0x8f: /* jnz rel, etc*/
5634 if (test_cc(ctxt->b, ctxt->eflags))
5635 rc = jmp_rel(ctxt, ctxt->src.val);
5636 break;
5637 case 0x90 ... 0x9f: /* setcc r/m8 */
5638 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
5639 break;
5640 case 0xb6 ... 0xb7: /* movzx */
5641 ctxt->dst.bytes = ctxt->op_bytes;
5642 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
5643 : (u16) ctxt->src.val;
5644 break;
5645 case 0xbe ... 0xbf: /* movsx */
5646 ctxt->dst.bytes = ctxt->op_bytes;
5647 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
5648 (s16) ctxt->src.val;
5649 break;
5650 default:
5651 goto cannot_emulate;
5652 }
5653
5654threebyte_insn:
5655
5656 if (rc != X86EMUL_CONTINUE)
5657 goto done;
5658
5659 goto writeback;
5660
5661cannot_emulate:
5662 return EMULATION_FAILED;
5663}
5664
5665void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5666{
5667 invalidate_registers(ctxt);
5668}
5669
5670void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5671{
5672 writeback_registers(ctxt);
5673}