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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/pci.h>
30#include <linux/pm_runtime.h>
31#include <linux/slab.h>
32#include <linux/uaccess.h>
33#include <linux/vga_switcheroo.h>
34
35#include <drm/drm_file.h>
36#include <drm/drm_ioctl.h>
37#include <drm/radeon_drm.h>
38
39#include "radeon.h"
40#include "radeon_asic.h"
41#include "radeon_drv.h"
42#include "radeon_kms.h"
43
44#if defined(CONFIG_VGA_SWITCHEROO)
45bool radeon_has_atpx(void);
46#else
47static inline bool radeon_has_atpx(void) { return false; }
48#endif
49
50/**
51 * radeon_driver_unload_kms - Main unload function for KMS.
52 *
53 * @dev: drm dev pointer
54 *
55 * This is the main unload function for KMS (all asics).
56 * It calls radeon_modeset_fini() to tear down the
57 * displays, and radeon_device_fini() to tear down
58 * the rest of the device (CP, writeback, etc.).
59 * Returns 0 on success.
60 */
61void radeon_driver_unload_kms(struct drm_device *dev)
62{
63 struct radeon_device *rdev = dev->dev_private;
64
65 if (rdev == NULL)
66 return;
67
68 if (rdev->rmmio == NULL)
69 goto done_free;
70
71 if (radeon_is_px(dev)) {
72 pm_runtime_get_sync(dev->dev);
73 pm_runtime_forbid(dev->dev);
74 }
75
76 radeon_acpi_fini(rdev);
77
78 radeon_modeset_fini(rdev);
79 radeon_device_fini(rdev);
80
81 if (rdev->agp)
82 arch_phys_wc_del(rdev->agp->agp_mtrr);
83 kfree(rdev->agp);
84 rdev->agp = NULL;
85
86done_free:
87 kfree(rdev);
88 dev->dev_private = NULL;
89}
90
91/**
92 * radeon_driver_load_kms - Main load function for KMS.
93 *
94 * @dev: drm dev pointer
95 * @flags: device flags
96 *
97 * This is the main load function for KMS (all asics).
98 * It calls radeon_device_init() to set up the non-display
99 * parts of the chip (asic init, CP, writeback, etc.), and
100 * radeon_modeset_init() to set up the display parts
101 * (crtcs, encoders, hotplug detect, etc.).
102 * Returns 0 on success, error on failure.
103 */
104int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
105{
106 struct pci_dev *pdev = to_pci_dev(dev->dev);
107 struct radeon_device *rdev = dev->dev_private;
108 int r, acpi_status;
109
110#ifdef __alpha__
111 rdev->hose = pdev->sysdata;
112#endif
113
114 if (pci_find_capability(pdev, PCI_CAP_ID_AGP))
115 rdev->agp = radeon_agp_head_init(dev);
116 if (rdev->agp) {
117 rdev->agp->agp_mtrr = arch_phys_wc_add(
118 rdev->agp->agp_info.aper_base,
119 rdev->agp->agp_info.aper_size *
120 1024 * 1024);
121 }
122
123 /* update BUS flag */
124 if (pci_find_capability(pdev, PCI_CAP_ID_AGP)) {
125 flags |= RADEON_IS_AGP;
126 } else if (pci_is_pcie(pdev)) {
127 flags |= RADEON_IS_PCIE;
128 } else {
129 flags |= RADEON_IS_PCI;
130 }
131
132 if ((radeon_runtime_pm != 0) &&
133 radeon_has_atpx() &&
134 ((flags & RADEON_IS_IGP) == 0) &&
135 !pci_is_thunderbolt_attached(pdev))
136 flags |= RADEON_IS_PX;
137
138 /* radeon_device_init should report only fatal error
139 * like memory allocation failure or iomapping failure,
140 * or memory manager initialization failure, it must
141 * properly initialize the GPU MC controller and permit
142 * VRAM allocation
143 */
144 r = radeon_device_init(rdev, dev, pdev, flags);
145 if (r) {
146 dev_err(dev->dev, "Fatal error during GPU init\n");
147 goto out;
148 }
149
150 /* Again modeset_init should fail only on fatal error
151 * otherwise it should provide enough functionalities
152 * for shadowfb to run
153 */
154 r = radeon_modeset_init(rdev);
155 if (r)
156 dev_err(dev->dev, "Fatal error during modeset init\n");
157
158 /* Call ACPI methods: require modeset init
159 * but failure is not fatal
160 */
161 if (!r) {
162 acpi_status = radeon_acpi_init(rdev);
163 if (acpi_status)
164 dev_dbg(dev->dev, "Error during ACPI methods call\n");
165 }
166
167 if (radeon_is_px(dev)) {
168 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
169 pm_runtime_use_autosuspend(dev->dev);
170 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
171 pm_runtime_set_active(dev->dev);
172 pm_runtime_allow(dev->dev);
173 pm_runtime_mark_last_busy(dev->dev);
174 pm_runtime_put_autosuspend(dev->dev);
175 }
176
177out:
178 if (r)
179 radeon_driver_unload_kms(dev);
180
181
182 return r;
183}
184
185/**
186 * radeon_set_filp_rights - Set filp right.
187 *
188 * @dev: drm dev pointer
189 * @owner: drm file
190 * @applier: drm file
191 * @value: value
192 *
193 * Sets the filp rights for the device (all asics).
194 */
195static void radeon_set_filp_rights(struct drm_device *dev,
196 struct drm_file **owner,
197 struct drm_file *applier,
198 uint32_t *value)
199{
200 struct radeon_device *rdev = dev->dev_private;
201
202 mutex_lock(&rdev->gem.mutex);
203 if (*value == 1) {
204 /* wants rights */
205 if (!*owner)
206 *owner = applier;
207 } else if (*value == 0) {
208 /* revokes rights */
209 if (*owner == applier)
210 *owner = NULL;
211 }
212 *value = *owner == applier ? 1 : 0;
213 mutex_unlock(&rdev->gem.mutex);
214}
215
216/*
217 * Userspace get information ioctl
218 */
219/**
220 * radeon_info_ioctl - answer a device specific request.
221 *
222 * @dev: drm device pointer
223 * @data: request object
224 * @filp: drm filp
225 *
226 * This function is used to pass device specific parameters to the userspace
227 * drivers. Examples include: pci device id, pipeline parms, tiling params,
228 * etc. (all asics).
229 * Returns 0 on success, -EINVAL on failure.
230 */
231int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
232{
233 struct radeon_device *rdev = dev->dev_private;
234 struct drm_radeon_info *info = data;
235 struct radeon_mode_info *minfo = &rdev->mode_info;
236 uint32_t *value, value_tmp, *value_ptr, value_size;
237 struct ttm_resource_manager *man;
238 uint64_t value64;
239 struct drm_crtc *crtc;
240 int i, found;
241
242 value_ptr = (uint32_t *)((unsigned long)info->value);
243 value = &value_tmp;
244 value_size = sizeof(uint32_t);
245
246 switch (info->request) {
247 case RADEON_INFO_DEVICE_ID:
248 *value = to_pci_dev(dev->dev)->device;
249 break;
250 case RADEON_INFO_NUM_GB_PIPES:
251 *value = rdev->num_gb_pipes;
252 break;
253 case RADEON_INFO_NUM_Z_PIPES:
254 *value = rdev->num_z_pipes;
255 break;
256 case RADEON_INFO_ACCEL_WORKING:
257 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
258 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
259 *value = false;
260 else
261 *value = rdev->accel_working;
262 break;
263 case RADEON_INFO_CRTC_FROM_ID:
264 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
265 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
266 return -EFAULT;
267 }
268 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
269 crtc = (struct drm_crtc *)minfo->crtcs[i];
270 if (crtc && crtc->base.id == *value) {
271 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
272 *value = radeon_crtc->crtc_id;
273 found = 1;
274 break;
275 }
276 }
277 if (!found) {
278 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
279 return -EINVAL;
280 }
281 break;
282 case RADEON_INFO_ACCEL_WORKING2:
283 if (rdev->family == CHIP_HAWAII) {
284 if (rdev->accel_working) {
285 if (rdev->new_fw)
286 *value = 3;
287 else
288 *value = 2;
289 } else {
290 *value = 0;
291 }
292 } else {
293 *value = rdev->accel_working;
294 }
295 break;
296 case RADEON_INFO_TILING_CONFIG:
297 if (rdev->family >= CHIP_BONAIRE)
298 *value = rdev->config.cik.tile_config;
299 else if (rdev->family >= CHIP_TAHITI)
300 *value = rdev->config.si.tile_config;
301 else if (rdev->family >= CHIP_CAYMAN)
302 *value = rdev->config.cayman.tile_config;
303 else if (rdev->family >= CHIP_CEDAR)
304 *value = rdev->config.evergreen.tile_config;
305 else if (rdev->family >= CHIP_RV770)
306 *value = rdev->config.rv770.tile_config;
307 else if (rdev->family >= CHIP_R600)
308 *value = rdev->config.r600.tile_config;
309 else {
310 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
311 return -EINVAL;
312 }
313 break;
314 case RADEON_INFO_WANT_HYPERZ:
315 /* The "value" here is both an input and output parameter.
316 * If the input value is 1, filp requests hyper-z access.
317 * If the input value is 0, filp revokes its hyper-z access.
318 *
319 * When returning, the value is 1 if filp owns hyper-z access,
320 * 0 otherwise. */
321 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
322 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
323 return -EFAULT;
324 }
325 if (*value >= 2) {
326 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
327 return -EINVAL;
328 }
329 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
330 break;
331 case RADEON_INFO_WANT_CMASK:
332 /* The same logic as Hyper-Z. */
333 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
334 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
335 return -EFAULT;
336 }
337 if (*value >= 2) {
338 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
339 return -EINVAL;
340 }
341 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
342 break;
343 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
344 /* return clock value in KHz */
345 if (rdev->asic->get_xclk)
346 *value = radeon_get_xclk(rdev) * 10;
347 else
348 *value = rdev->clock.spll.reference_freq * 10;
349 break;
350 case RADEON_INFO_NUM_BACKENDS:
351 if (rdev->family >= CHIP_BONAIRE)
352 *value = rdev->config.cik.max_backends_per_se *
353 rdev->config.cik.max_shader_engines;
354 else if (rdev->family >= CHIP_TAHITI)
355 *value = rdev->config.si.max_backends_per_se *
356 rdev->config.si.max_shader_engines;
357 else if (rdev->family >= CHIP_CAYMAN)
358 *value = rdev->config.cayman.max_backends_per_se *
359 rdev->config.cayman.max_shader_engines;
360 else if (rdev->family >= CHIP_CEDAR)
361 *value = rdev->config.evergreen.max_backends;
362 else if (rdev->family >= CHIP_RV770)
363 *value = rdev->config.rv770.max_backends;
364 else if (rdev->family >= CHIP_R600)
365 *value = rdev->config.r600.max_backends;
366 else {
367 return -EINVAL;
368 }
369 break;
370 case RADEON_INFO_NUM_TILE_PIPES:
371 if (rdev->family >= CHIP_BONAIRE)
372 *value = rdev->config.cik.max_tile_pipes;
373 else if (rdev->family >= CHIP_TAHITI)
374 *value = rdev->config.si.max_tile_pipes;
375 else if (rdev->family >= CHIP_CAYMAN)
376 *value = rdev->config.cayman.max_tile_pipes;
377 else if (rdev->family >= CHIP_CEDAR)
378 *value = rdev->config.evergreen.max_tile_pipes;
379 else if (rdev->family >= CHIP_RV770)
380 *value = rdev->config.rv770.max_tile_pipes;
381 else if (rdev->family >= CHIP_R600)
382 *value = rdev->config.r600.max_tile_pipes;
383 else {
384 return -EINVAL;
385 }
386 break;
387 case RADEON_INFO_FUSION_GART_WORKING:
388 *value = 1;
389 break;
390 case RADEON_INFO_BACKEND_MAP:
391 if (rdev->family >= CHIP_BONAIRE)
392 *value = rdev->config.cik.backend_map;
393 else if (rdev->family >= CHIP_TAHITI)
394 *value = rdev->config.si.backend_map;
395 else if (rdev->family >= CHIP_CAYMAN)
396 *value = rdev->config.cayman.backend_map;
397 else if (rdev->family >= CHIP_CEDAR)
398 *value = rdev->config.evergreen.backend_map;
399 else if (rdev->family >= CHIP_RV770)
400 *value = rdev->config.rv770.backend_map;
401 else if (rdev->family >= CHIP_R600)
402 *value = rdev->config.r600.backend_map;
403 else {
404 return -EINVAL;
405 }
406 break;
407 case RADEON_INFO_VA_START:
408 /* this is where we report if vm is supported or not */
409 if (rdev->family < CHIP_CAYMAN)
410 return -EINVAL;
411 *value = RADEON_VA_RESERVED_SIZE;
412 break;
413 case RADEON_INFO_IB_VM_MAX_SIZE:
414 /* this is where we report if vm is supported or not */
415 if (rdev->family < CHIP_CAYMAN)
416 return -EINVAL;
417 *value = RADEON_IB_VM_MAX_SIZE;
418 break;
419 case RADEON_INFO_MAX_PIPES:
420 if (rdev->family >= CHIP_BONAIRE)
421 *value = rdev->config.cik.max_cu_per_sh;
422 else if (rdev->family >= CHIP_TAHITI)
423 *value = rdev->config.si.max_cu_per_sh;
424 else if (rdev->family >= CHIP_CAYMAN)
425 *value = rdev->config.cayman.max_pipes_per_simd;
426 else if (rdev->family >= CHIP_CEDAR)
427 *value = rdev->config.evergreen.max_pipes;
428 else if (rdev->family >= CHIP_RV770)
429 *value = rdev->config.rv770.max_pipes;
430 else if (rdev->family >= CHIP_R600)
431 *value = rdev->config.r600.max_pipes;
432 else {
433 return -EINVAL;
434 }
435 break;
436 case RADEON_INFO_TIMESTAMP:
437 if (rdev->family < CHIP_R600) {
438 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
439 return -EINVAL;
440 }
441 value = (uint32_t *)&value64;
442 value_size = sizeof(uint64_t);
443 value64 = radeon_get_gpu_clock_counter(rdev);
444 break;
445 case RADEON_INFO_MAX_SE:
446 if (rdev->family >= CHIP_BONAIRE)
447 *value = rdev->config.cik.max_shader_engines;
448 else if (rdev->family >= CHIP_TAHITI)
449 *value = rdev->config.si.max_shader_engines;
450 else if (rdev->family >= CHIP_CAYMAN)
451 *value = rdev->config.cayman.max_shader_engines;
452 else if (rdev->family >= CHIP_CEDAR)
453 *value = rdev->config.evergreen.num_ses;
454 else
455 *value = 1;
456 break;
457 case RADEON_INFO_MAX_SH_PER_SE:
458 if (rdev->family >= CHIP_BONAIRE)
459 *value = rdev->config.cik.max_sh_per_se;
460 else if (rdev->family >= CHIP_TAHITI)
461 *value = rdev->config.si.max_sh_per_se;
462 else
463 return -EINVAL;
464 break;
465 case RADEON_INFO_FASTFB_WORKING:
466 *value = rdev->fastfb_working;
467 break;
468 case RADEON_INFO_RING_WORKING:
469 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
470 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
471 return -EFAULT;
472 }
473 switch (*value) {
474 case RADEON_CS_RING_GFX:
475 case RADEON_CS_RING_COMPUTE:
476 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
477 break;
478 case RADEON_CS_RING_DMA:
479 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
480 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
481 break;
482 case RADEON_CS_RING_UVD:
483 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
484 break;
485 case RADEON_CS_RING_VCE:
486 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
487 break;
488 default:
489 return -EINVAL;
490 }
491 break;
492 case RADEON_INFO_SI_TILE_MODE_ARRAY:
493 if (rdev->family >= CHIP_BONAIRE) {
494 value = rdev->config.cik.tile_mode_array;
495 value_size = sizeof(uint32_t)*32;
496 } else if (rdev->family >= CHIP_TAHITI) {
497 value = rdev->config.si.tile_mode_array;
498 value_size = sizeof(uint32_t)*32;
499 } else {
500 DRM_DEBUG_KMS("tile mode array is si+ only!\n");
501 return -EINVAL;
502 }
503 break;
504 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
505 if (rdev->family >= CHIP_BONAIRE) {
506 value = rdev->config.cik.macrotile_mode_array;
507 value_size = sizeof(uint32_t)*16;
508 } else {
509 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
510 return -EINVAL;
511 }
512 break;
513 case RADEON_INFO_SI_CP_DMA_COMPUTE:
514 *value = 1;
515 break;
516 case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
517 if (rdev->family >= CHIP_BONAIRE) {
518 *value = rdev->config.cik.backend_enable_mask;
519 } else if (rdev->family >= CHIP_TAHITI) {
520 *value = rdev->config.si.backend_enable_mask;
521 } else {
522 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
523 return -EINVAL;
524 }
525 break;
526 case RADEON_INFO_MAX_SCLK:
527 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
528 rdev->pm.dpm_enabled)
529 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
530 else
531 *value = rdev->pm.default_sclk * 10;
532 break;
533 case RADEON_INFO_VCE_FW_VERSION:
534 *value = rdev->vce.fw_version;
535 break;
536 case RADEON_INFO_VCE_FB_VERSION:
537 *value = rdev->vce.fb_version;
538 break;
539 case RADEON_INFO_NUM_BYTES_MOVED:
540 value = (uint32_t *)&value64;
541 value_size = sizeof(uint64_t);
542 value64 = atomic64_read(&rdev->num_bytes_moved);
543 break;
544 case RADEON_INFO_VRAM_USAGE:
545 value = (uint32_t *)&value64;
546 value_size = sizeof(uint64_t);
547 man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM);
548 value64 = ttm_resource_manager_usage(man);
549 break;
550 case RADEON_INFO_GTT_USAGE:
551 value = (uint32_t *)&value64;
552 value_size = sizeof(uint64_t);
553 man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_TT);
554 value64 = ttm_resource_manager_usage(man);
555 break;
556 case RADEON_INFO_ACTIVE_CU_COUNT:
557 if (rdev->family >= CHIP_BONAIRE)
558 *value = rdev->config.cik.active_cus;
559 else if (rdev->family >= CHIP_TAHITI)
560 *value = rdev->config.si.active_cus;
561 else if (rdev->family >= CHIP_CAYMAN)
562 *value = rdev->config.cayman.active_simds;
563 else if (rdev->family >= CHIP_CEDAR)
564 *value = rdev->config.evergreen.active_simds;
565 else if (rdev->family >= CHIP_RV770)
566 *value = rdev->config.rv770.active_simds;
567 else if (rdev->family >= CHIP_R600)
568 *value = rdev->config.r600.active_simds;
569 else
570 *value = 1;
571 break;
572 case RADEON_INFO_CURRENT_GPU_TEMP:
573 /* get temperature in millidegrees C */
574 if (rdev->asic->pm.get_temperature)
575 *value = radeon_get_temperature(rdev);
576 else
577 *value = 0;
578 break;
579 case RADEON_INFO_CURRENT_GPU_SCLK:
580 /* get sclk in Mhz */
581 if (rdev->pm.dpm_enabled)
582 *value = radeon_dpm_get_current_sclk(rdev) / 100;
583 else
584 *value = rdev->pm.current_sclk / 100;
585 break;
586 case RADEON_INFO_CURRENT_GPU_MCLK:
587 /* get mclk in Mhz */
588 if (rdev->pm.dpm_enabled)
589 *value = radeon_dpm_get_current_mclk(rdev) / 100;
590 else
591 *value = rdev->pm.current_mclk / 100;
592 break;
593 case RADEON_INFO_READ_REG:
594 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
595 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
596 return -EFAULT;
597 }
598 if (radeon_get_allowed_info_register(rdev, *value, value))
599 return -EINVAL;
600 break;
601 case RADEON_INFO_VA_UNMAP_WORKING:
602 *value = true;
603 break;
604 case RADEON_INFO_GPU_RESET_COUNTER:
605 *value = atomic_read(&rdev->gpu_reset_counter);
606 break;
607 default:
608 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
609 return -EINVAL;
610 }
611 if (copy_to_user(value_ptr, (char *)value, value_size)) {
612 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
613 return -EFAULT;
614 }
615 return 0;
616}
617
618/**
619 * radeon_driver_open_kms - drm callback for open
620 *
621 * @dev: drm dev pointer
622 * @file_priv: drm file
623 *
624 * On device open, init vm on cayman+ (all asics).
625 * Returns 0 on success, error on failure.
626 */
627int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
628{
629 struct radeon_device *rdev = dev->dev_private;
630 struct radeon_fpriv *fpriv;
631 struct radeon_vm *vm;
632 int r;
633
634 file_priv->driver_priv = NULL;
635
636 r = pm_runtime_get_sync(dev->dev);
637 if (r < 0) {
638 pm_runtime_put_autosuspend(dev->dev);
639 return r;
640 }
641
642 /* new gpu have virtual address space support */
643 if (rdev->family >= CHIP_CAYMAN) {
644
645 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
646 if (unlikely(!fpriv)) {
647 r = -ENOMEM;
648 goto err_suspend;
649 }
650
651 if (rdev->accel_working) {
652 vm = &fpriv->vm;
653 r = radeon_vm_init(rdev, vm);
654 if (r)
655 goto err_fpriv;
656
657 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
658 if (r)
659 goto err_vm_fini;
660
661 /* map the ib pool buffer read only into
662 * virtual address space */
663 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
664 rdev->ring_tmp_bo.bo);
665 if (!vm->ib_bo_va) {
666 r = -ENOMEM;
667 goto err_vm_fini;
668 }
669
670 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
671 RADEON_VA_IB_OFFSET,
672 RADEON_VM_PAGE_READABLE |
673 RADEON_VM_PAGE_SNOOPED);
674 if (r)
675 goto err_vm_fini;
676 }
677 file_priv->driver_priv = fpriv;
678 }
679
680 pm_runtime_mark_last_busy(dev->dev);
681 pm_runtime_put_autosuspend(dev->dev);
682 return 0;
683
684err_vm_fini:
685 radeon_vm_fini(rdev, vm);
686err_fpriv:
687 kfree(fpriv);
688
689err_suspend:
690 pm_runtime_mark_last_busy(dev->dev);
691 pm_runtime_put_autosuspend(dev->dev);
692 return r;
693}
694
695/**
696 * radeon_driver_postclose_kms - drm callback for post close
697 *
698 * @dev: drm dev pointer
699 * @file_priv: drm file
700 *
701 * On device close, tear down hyperz and cmask filps on r1xx-r5xx
702 * (all asics). And tear down vm on cayman+ (all asics).
703 */
704void radeon_driver_postclose_kms(struct drm_device *dev,
705 struct drm_file *file_priv)
706{
707 struct radeon_device *rdev = dev->dev_private;
708
709 pm_runtime_get_sync(dev->dev);
710
711 mutex_lock(&rdev->gem.mutex);
712 if (rdev->hyperz_filp == file_priv)
713 rdev->hyperz_filp = NULL;
714 if (rdev->cmask_filp == file_priv)
715 rdev->cmask_filp = NULL;
716 mutex_unlock(&rdev->gem.mutex);
717
718 radeon_uvd_free_handles(rdev, file_priv);
719 radeon_vce_free_handles(rdev, file_priv);
720
721 /* new gpu have virtual address space support */
722 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
723 struct radeon_fpriv *fpriv = file_priv->driver_priv;
724 struct radeon_vm *vm = &fpriv->vm;
725 int r;
726
727 if (rdev->accel_working) {
728 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
729 if (!r) {
730 if (vm->ib_bo_va)
731 radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
732 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
733 }
734 radeon_vm_fini(rdev, vm);
735 }
736
737 kfree(fpriv);
738 file_priv->driver_priv = NULL;
739 }
740 pm_runtime_mark_last_busy(dev->dev);
741 pm_runtime_put_autosuspend(dev->dev);
742}
743
744/*
745 * VBlank related functions.
746 */
747/**
748 * radeon_get_vblank_counter_kms - get frame count
749 *
750 * @crtc: crtc to get the frame count from
751 *
752 * Gets the frame count on the requested crtc (all asics).
753 * Returns frame count on success, -EINVAL on failure.
754 */
755u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc)
756{
757 struct drm_device *dev = crtc->dev;
758 unsigned int pipe = crtc->index;
759 int vpos, hpos, stat;
760 u32 count;
761 struct radeon_device *rdev = dev->dev_private;
762
763 if (pipe >= rdev->num_crtc) {
764 DRM_ERROR("Invalid crtc %u\n", pipe);
765 return -EINVAL;
766 }
767
768 /* The hw increments its frame counter at start of vsync, not at start
769 * of vblank, as is required by DRM core vblank counter handling.
770 * Cook the hw count here to make it appear to the caller as if it
771 * incremented at start of vblank. We measure distance to start of
772 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
773 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
774 * result by 1 to give the proper appearance to caller.
775 */
776 if (rdev->mode_info.crtcs[pipe]) {
777 /* Repeat readout if needed to provide stable result if
778 * we cross start of vsync during the queries.
779 */
780 do {
781 count = radeon_get_vblank_counter(rdev, pipe);
782 /* Ask radeon_get_crtc_scanoutpos to return vpos as
783 * distance to start of vblank, instead of regular
784 * vertical scanout pos.
785 */
786 stat = radeon_get_crtc_scanoutpos(
787 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
788 &vpos, &hpos, NULL, NULL,
789 &rdev->mode_info.crtcs[pipe]->base.hwmode);
790 } while (count != radeon_get_vblank_counter(rdev, pipe));
791
792 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
793 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
794 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
795 }
796 else {
797 DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n",
798 pipe, vpos);
799
800 /* Bump counter if we are at >= leading edge of vblank,
801 * but before vsync where vpos would turn negative and
802 * the hw counter really increments.
803 */
804 if (vpos >= 0)
805 count++;
806 }
807 }
808 else {
809 /* Fallback to use value as is. */
810 count = radeon_get_vblank_counter(rdev, pipe);
811 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
812 }
813
814 return count;
815}
816
817/**
818 * radeon_enable_vblank_kms - enable vblank interrupt
819 *
820 * @crtc: crtc to enable vblank interrupt for
821 *
822 * Enable the interrupt on the requested crtc (all asics).
823 * Returns 0 on success, -EINVAL on failure.
824 */
825int radeon_enable_vblank_kms(struct drm_crtc *crtc)
826{
827 struct drm_device *dev = crtc->dev;
828 unsigned int pipe = crtc->index;
829 struct radeon_device *rdev = dev->dev_private;
830 unsigned long irqflags;
831 int r;
832
833 if (pipe >= rdev->num_crtc) {
834 DRM_ERROR("Invalid crtc %d\n", pipe);
835 return -EINVAL;
836 }
837
838 spin_lock_irqsave(&rdev->irq.lock, irqflags);
839 rdev->irq.crtc_vblank_int[pipe] = true;
840 r = radeon_irq_set(rdev);
841 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
842 return r;
843}
844
845/**
846 * radeon_disable_vblank_kms - disable vblank interrupt
847 *
848 * @crtc: crtc to disable vblank interrupt for
849 *
850 * Disable the interrupt on the requested crtc (all asics).
851 */
852void radeon_disable_vblank_kms(struct drm_crtc *crtc)
853{
854 struct drm_device *dev = crtc->dev;
855 unsigned int pipe = crtc->index;
856 struct radeon_device *rdev = dev->dev_private;
857 unsigned long irqflags;
858
859 if (pipe >= rdev->num_crtc) {
860 DRM_ERROR("Invalid crtc %d\n", pipe);
861 return;
862 }
863
864 spin_lock_irqsave(&rdev->irq.lock, irqflags);
865 rdev->irq.crtc_vblank_int[pipe] = false;
866 radeon_irq_set(rdev);
867 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
868}
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
29#include "drm_sarea.h"
30#include "radeon.h"
31#include "radeon_drm.h"
32
33#include <linux/vga_switcheroo.h>
34#include <linux/slab.h>
35
36int radeon_driver_unload_kms(struct drm_device *dev)
37{
38 struct radeon_device *rdev = dev->dev_private;
39
40 if (rdev == NULL)
41 return 0;
42 radeon_modeset_fini(rdev);
43 radeon_device_fini(rdev);
44 kfree(rdev);
45 dev->dev_private = NULL;
46 return 0;
47}
48
49int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
50{
51 struct radeon_device *rdev;
52 int r, acpi_status;
53
54 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
55 if (rdev == NULL) {
56 return -ENOMEM;
57 }
58 dev->dev_private = (void *)rdev;
59
60 /* update BUS flag */
61 if (drm_pci_device_is_agp(dev)) {
62 flags |= RADEON_IS_AGP;
63 } else if (pci_is_pcie(dev->pdev)) {
64 flags |= RADEON_IS_PCIE;
65 } else {
66 flags |= RADEON_IS_PCI;
67 }
68
69 /* radeon_device_init should report only fatal error
70 * like memory allocation failure or iomapping failure,
71 * or memory manager initialization failure, it must
72 * properly initialize the GPU MC controller and permit
73 * VRAM allocation
74 */
75 r = radeon_device_init(rdev, dev, dev->pdev, flags);
76 if (r) {
77 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
78 goto out;
79 }
80
81 /* Call ACPI methods */
82 acpi_status = radeon_acpi_init(rdev);
83 if (acpi_status)
84 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");
85
86 /* Again modeset_init should fail only on fatal error
87 * otherwise it should provide enough functionalities
88 * for shadowfb to run
89 */
90 r = radeon_modeset_init(rdev);
91 if (r)
92 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
93out:
94 if (r)
95 radeon_driver_unload_kms(dev);
96 return r;
97}
98
99static void radeon_set_filp_rights(struct drm_device *dev,
100 struct drm_file **owner,
101 struct drm_file *applier,
102 uint32_t *value)
103{
104 mutex_lock(&dev->struct_mutex);
105 if (*value == 1) {
106 /* wants rights */
107 if (!*owner)
108 *owner = applier;
109 } else if (*value == 0) {
110 /* revokes rights */
111 if (*owner == applier)
112 *owner = NULL;
113 }
114 *value = *owner == applier ? 1 : 0;
115 mutex_unlock(&dev->struct_mutex);
116}
117
118/*
119 * Userspace get information ioctl
120 */
121int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
122{
123 struct radeon_device *rdev = dev->dev_private;
124 struct drm_radeon_info *info;
125 struct radeon_mode_info *minfo = &rdev->mode_info;
126 uint32_t *value_ptr;
127 uint32_t value;
128 struct drm_crtc *crtc;
129 int i, found;
130
131 info = data;
132 value_ptr = (uint32_t *)((unsigned long)info->value);
133 if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value)))
134 return -EFAULT;
135
136 switch (info->request) {
137 case RADEON_INFO_DEVICE_ID:
138 value = dev->pci_device;
139 break;
140 case RADEON_INFO_NUM_GB_PIPES:
141 value = rdev->num_gb_pipes;
142 break;
143 case RADEON_INFO_NUM_Z_PIPES:
144 value = rdev->num_z_pipes;
145 break;
146 case RADEON_INFO_ACCEL_WORKING:
147 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
148 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
149 value = false;
150 else
151 value = rdev->accel_working;
152 break;
153 case RADEON_INFO_CRTC_FROM_ID:
154 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
155 crtc = (struct drm_crtc *)minfo->crtcs[i];
156 if (crtc && crtc->base.id == value) {
157 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
158 value = radeon_crtc->crtc_id;
159 found = 1;
160 break;
161 }
162 }
163 if (!found) {
164 DRM_DEBUG_KMS("unknown crtc id %d\n", value);
165 return -EINVAL;
166 }
167 break;
168 case RADEON_INFO_ACCEL_WORKING2:
169 value = rdev->accel_working;
170 break;
171 case RADEON_INFO_TILING_CONFIG:
172 if (rdev->family >= CHIP_TAHITI)
173 value = rdev->config.si.tile_config;
174 else if (rdev->family >= CHIP_CAYMAN)
175 value = rdev->config.cayman.tile_config;
176 else if (rdev->family >= CHIP_CEDAR)
177 value = rdev->config.evergreen.tile_config;
178 else if (rdev->family >= CHIP_RV770)
179 value = rdev->config.rv770.tile_config;
180 else if (rdev->family >= CHIP_R600)
181 value = rdev->config.r600.tile_config;
182 else {
183 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
184 return -EINVAL;
185 }
186 break;
187 case RADEON_INFO_WANT_HYPERZ:
188 /* The "value" here is both an input and output parameter.
189 * If the input value is 1, filp requests hyper-z access.
190 * If the input value is 0, filp revokes its hyper-z access.
191 *
192 * When returning, the value is 1 if filp owns hyper-z access,
193 * 0 otherwise. */
194 if (value >= 2) {
195 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value);
196 return -EINVAL;
197 }
198 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value);
199 break;
200 case RADEON_INFO_WANT_CMASK:
201 /* The same logic as Hyper-Z. */
202 if (value >= 2) {
203 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value);
204 return -EINVAL;
205 }
206 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value);
207 break;
208 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
209 /* return clock value in KHz */
210 value = rdev->clock.spll.reference_freq * 10;
211 break;
212 case RADEON_INFO_NUM_BACKENDS:
213 if (rdev->family >= CHIP_TAHITI)
214 value = rdev->config.si.max_backends_per_se *
215 rdev->config.si.max_shader_engines;
216 else if (rdev->family >= CHIP_CAYMAN)
217 value = rdev->config.cayman.max_backends_per_se *
218 rdev->config.cayman.max_shader_engines;
219 else if (rdev->family >= CHIP_CEDAR)
220 value = rdev->config.evergreen.max_backends;
221 else if (rdev->family >= CHIP_RV770)
222 value = rdev->config.rv770.max_backends;
223 else if (rdev->family >= CHIP_R600)
224 value = rdev->config.r600.max_backends;
225 else {
226 return -EINVAL;
227 }
228 break;
229 case RADEON_INFO_NUM_TILE_PIPES:
230 if (rdev->family >= CHIP_TAHITI)
231 value = rdev->config.si.max_tile_pipes;
232 else if (rdev->family >= CHIP_CAYMAN)
233 value = rdev->config.cayman.max_tile_pipes;
234 else if (rdev->family >= CHIP_CEDAR)
235 value = rdev->config.evergreen.max_tile_pipes;
236 else if (rdev->family >= CHIP_RV770)
237 value = rdev->config.rv770.max_tile_pipes;
238 else if (rdev->family >= CHIP_R600)
239 value = rdev->config.r600.max_tile_pipes;
240 else {
241 return -EINVAL;
242 }
243 break;
244 case RADEON_INFO_FUSION_GART_WORKING:
245 value = 1;
246 break;
247 case RADEON_INFO_BACKEND_MAP:
248 if (rdev->family >= CHIP_TAHITI)
249 value = rdev->config.si.backend_map;
250 else if (rdev->family >= CHIP_CAYMAN)
251 value = rdev->config.cayman.backend_map;
252 else if (rdev->family >= CHIP_CEDAR)
253 value = rdev->config.evergreen.backend_map;
254 else if (rdev->family >= CHIP_RV770)
255 value = rdev->config.rv770.backend_map;
256 else if (rdev->family >= CHIP_R600)
257 value = rdev->config.r600.backend_map;
258 else {
259 return -EINVAL;
260 }
261 break;
262 case RADEON_INFO_VA_START:
263 /* this is where we report if vm is supported or not */
264 if (rdev->family < CHIP_CAYMAN)
265 return -EINVAL;
266 value = RADEON_VA_RESERVED_SIZE;
267 break;
268 case RADEON_INFO_IB_VM_MAX_SIZE:
269 /* this is where we report if vm is supported or not */
270 if (rdev->family < CHIP_CAYMAN)
271 return -EINVAL;
272 value = RADEON_IB_VM_MAX_SIZE;
273 break;
274 case RADEON_INFO_MAX_PIPES:
275 if (rdev->family >= CHIP_TAHITI)
276 value = rdev->config.si.max_cu_per_sh;
277 else if (rdev->family >= CHIP_CAYMAN)
278 value = rdev->config.cayman.max_pipes_per_simd;
279 else if (rdev->family >= CHIP_CEDAR)
280 value = rdev->config.evergreen.max_pipes;
281 else if (rdev->family >= CHIP_RV770)
282 value = rdev->config.rv770.max_pipes;
283 else if (rdev->family >= CHIP_R600)
284 value = rdev->config.r600.max_pipes;
285 else {
286 return -EINVAL;
287 }
288 break;
289 default:
290 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
291 return -EINVAL;
292 }
293 if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
294 DRM_ERROR("copy_to_user\n");
295 return -EFAULT;
296 }
297 return 0;
298}
299
300
301/*
302 * Outdated mess for old drm with Xorg being in charge (void function now).
303 */
304int radeon_driver_firstopen_kms(struct drm_device *dev)
305{
306 return 0;
307}
308
309void radeon_driver_lastclose_kms(struct drm_device *dev)
310{
311 vga_switcheroo_process_delayed_switch();
312}
313
314int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
315{
316 struct radeon_device *rdev = dev->dev_private;
317
318 file_priv->driver_priv = NULL;
319
320 /* new gpu have virtual address space support */
321 if (rdev->family >= CHIP_CAYMAN) {
322 struct radeon_fpriv *fpriv;
323 int r;
324
325 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
326 if (unlikely(!fpriv)) {
327 return -ENOMEM;
328 }
329
330 r = radeon_vm_init(rdev, &fpriv->vm);
331 if (r) {
332 radeon_vm_fini(rdev, &fpriv->vm);
333 kfree(fpriv);
334 return r;
335 }
336
337 file_priv->driver_priv = fpriv;
338 }
339 return 0;
340}
341
342void radeon_driver_postclose_kms(struct drm_device *dev,
343 struct drm_file *file_priv)
344{
345 struct radeon_device *rdev = dev->dev_private;
346
347 /* new gpu have virtual address space support */
348 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
349 struct radeon_fpriv *fpriv = file_priv->driver_priv;
350
351 radeon_vm_fini(rdev, &fpriv->vm);
352 kfree(fpriv);
353 file_priv->driver_priv = NULL;
354 }
355}
356
357void radeon_driver_preclose_kms(struct drm_device *dev,
358 struct drm_file *file_priv)
359{
360 struct radeon_device *rdev = dev->dev_private;
361 if (rdev->hyperz_filp == file_priv)
362 rdev->hyperz_filp = NULL;
363 if (rdev->cmask_filp == file_priv)
364 rdev->cmask_filp = NULL;
365}
366
367/*
368 * VBlank related functions.
369 */
370u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
371{
372 struct radeon_device *rdev = dev->dev_private;
373
374 if (crtc < 0 || crtc >= rdev->num_crtc) {
375 DRM_ERROR("Invalid crtc %d\n", crtc);
376 return -EINVAL;
377 }
378
379 return radeon_get_vblank_counter(rdev, crtc);
380}
381
382int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
383{
384 struct radeon_device *rdev = dev->dev_private;
385
386 if (crtc < 0 || crtc >= rdev->num_crtc) {
387 DRM_ERROR("Invalid crtc %d\n", crtc);
388 return -EINVAL;
389 }
390
391 rdev->irq.crtc_vblank_int[crtc] = true;
392
393 return radeon_irq_set(rdev);
394}
395
396void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
397{
398 struct radeon_device *rdev = dev->dev_private;
399
400 if (crtc < 0 || crtc >= rdev->num_crtc) {
401 DRM_ERROR("Invalid crtc %d\n", crtc);
402 return;
403 }
404
405 rdev->irq.crtc_vblank_int[crtc] = false;
406
407 radeon_irq_set(rdev);
408}
409
410int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
411 int *max_error,
412 struct timeval *vblank_time,
413 unsigned flags)
414{
415 struct drm_crtc *drmcrtc;
416 struct radeon_device *rdev = dev->dev_private;
417
418 if (crtc < 0 || crtc >= dev->num_crtcs) {
419 DRM_ERROR("Invalid crtc %d\n", crtc);
420 return -EINVAL;
421 }
422
423 /* Get associated drm_crtc: */
424 drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
425
426 /* Helper routine in DRM core does all the work: */
427 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
428 vblank_time, flags,
429 drmcrtc);
430}
431
432/*
433 * IOCTL.
434 */
435int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
436 struct drm_file *file_priv)
437{
438 /* Not valid in KMS. */
439 return -EINVAL;
440}
441
442#define KMS_INVALID_IOCTL(name) \
443int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
444{ \
445 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
446 return -EINVAL; \
447}
448
449/*
450 * All these ioctls are invalid in kms world.
451 */
452KMS_INVALID_IOCTL(radeon_cp_init_kms)
453KMS_INVALID_IOCTL(radeon_cp_start_kms)
454KMS_INVALID_IOCTL(radeon_cp_stop_kms)
455KMS_INVALID_IOCTL(radeon_cp_reset_kms)
456KMS_INVALID_IOCTL(radeon_cp_idle_kms)
457KMS_INVALID_IOCTL(radeon_cp_resume_kms)
458KMS_INVALID_IOCTL(radeon_engine_reset_kms)
459KMS_INVALID_IOCTL(radeon_fullscreen_kms)
460KMS_INVALID_IOCTL(radeon_cp_swap_kms)
461KMS_INVALID_IOCTL(radeon_cp_clear_kms)
462KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
463KMS_INVALID_IOCTL(radeon_cp_indices_kms)
464KMS_INVALID_IOCTL(radeon_cp_texture_kms)
465KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
466KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
467KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
468KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
469KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
470KMS_INVALID_IOCTL(radeon_cp_flip_kms)
471KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
472KMS_INVALID_IOCTL(radeon_mem_free_kms)
473KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
474KMS_INVALID_IOCTL(radeon_irq_emit_kms)
475KMS_INVALID_IOCTL(radeon_irq_wait_kms)
476KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
477KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
478KMS_INVALID_IOCTL(radeon_surface_free_kms)
479
480
481struct drm_ioctl_desc radeon_ioctls_kms[] = {
482 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
483 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
484 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
485 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
486 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
487 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
488 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
489 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
490 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
491 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
492 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
493 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
494 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
495 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
496 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
497 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
498 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
499 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
500 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
501 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
502 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
503 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
504 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
505 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
506 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
507 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
508 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
509 /* KMS */
510 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
511 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
512 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
513 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
514 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
515 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
516 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
517 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
518 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
519 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
520 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
521 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
522 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED),
523};
524int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);